From 1922e74bb9790e6fb1ebb772ca0520b28aa8e1e3 Mon Sep 17 00:00:00 2001 From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> Date: Thu, 11 Aug 2011 18:24:18 +0000 Subject: [PATCH] Add Kinetis ENET header file git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3868 42af7a65-404d-4744-a932-0658087f49c3 --- arch/arm/src/kinetis/chip.h | 36 +- arch/arm/src/kinetis/kinetis_enet.h | 449 +++++++++++++++++++++++ arch/arm/src/kinetis/kinetis_memorymap.h | 4 +- arch/arm/src/kinetis/kinetis_usbotg.h | 222 +++++++++++ 4 files changed, 691 insertions(+), 20 deletions(-) create mode 100644 arch/arm/src/kinetis/kinetis_enet.h create mode 100644 arch/arm/src/kinetis/kinetis_usbotg.h diff --git a/arch/arm/src/kinetis/chip.h b/arch/arm/src/kinetis/chip.h index d893d104f9..842e833a5f 100644 --- a/arch/arm/src/kinetis/chip.h +++ b/arch/arm/src/kinetis/chip.h @@ -58,7 +58,7 @@ # undef KINETIS_MPU /* No memory protection unit */ # undef KINETIS_EXTBUS /* No external bus interface */ # define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# undef KINETIS_NETHERNET /* No Ethernet controller */ +# undef KINETIS_NENET /* No Ethernet controller */ # define KINETIS_NUSBHOST 1 /* One USB host controller */ # define KINETIS_NUSBOTG 1 /* With USB OTG controller */ # define KINETIS_NUSBDEV 1 /* One USB device controller */ @@ -107,7 +107,7 @@ # undef KINETIS_MPU /* No memory protection unit */ # undef KINETIS_EXTBUS /* No external bus interface */ # define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# undef KINETIS_NETHERNET /* No Ethernet controller */ +# undef KINETIS_NENET /* No Ethernet controller */ # define KINETIS_NUSBHOST 1 /* One USB host controller */ # define KINETIS_NUSBOTG 1 /* With USB OTG controller */ # define KINETIS_NUSBDEV 1 /* One USB device controller */ @@ -148,7 +148,7 @@ # undef KINETIS_MPU /* No memory protection unit */ # undef KINETIS_EXTBUS /* No external bus interface */ # define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# undef KINETIS_NETHERNET /* No Ethernet controller */ +# undef KINETIS_NENET /* No Ethernet controller */ # define KINETIS_NUSBHOST 1 /* One USB host controller */ # define KINETIS_NUSBOTG 1 /* With USB OTG controller */ # define KINETIS_NUSBDEV 1 /* One USB device controller */ @@ -188,7 +188,7 @@ # define KINETIS_MPU 1 /* Memory protection unit */ # define KINETIS_EXTBUS 1 /* External bus interface */ # define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# undef KINETIS_NETHERNET /* No Ethernet controller */ +# undef KINETIS_NENET /* No Ethernet controller */ # define KINETIS_NUSBHOST 1 /* One USB host controller */ # define KINETIS_NUSBOTG 1 /* With USB OTG controller */ # define KINETIS_NUSBDEV 1 /* One USB device controller */ @@ -228,7 +228,7 @@ # define KINETIS_MPU 1 /* Memory protection unit */ # define KINETIS_EXTBUS 1 /* External bus interface */ # define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# undef KINETIS_NETHERNET /* No Ethernet controller */ +# undef KINETIS_NENET /* No Ethernet controller */ # define KINETIS_NUSBHOST 1 /* One USB host controller */ # define KINETIS_NUSBOTG 1 /* With USB OTG controller */ # define KINETIS_NUSBDEV 1 /* One USB device controller */ @@ -270,7 +270,7 @@ # define KINETIS_MPU 1 /* Memory protection unit */ # define KINETIS_EXTBUS 1 /* External bus interface */ # define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# undef KINETIS_NETHERNET /* No Ethernet controller */ +# undef KINETIS_NENET /* No Ethernet controller */ # define KINETIS_NUSBHOST 1 /* One USB host controller */ # define KINETIS_NUSBOTG 1 /* With USB OTG controller */ # define KINETIS_NUSBDEV 1 /* One USB device controller */ @@ -311,7 +311,7 @@ # define KINETIS_MPU 1 /* Memory protection unit */ # define KINETIS_EXTBUS 1 /* External bus interface */ # define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NETHERNET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ # define KINETIS_NUSBHOST 1 /* One USB host controller */ # define KINETIS_NUSBOTG 1 /* With USB OTG controller */ # define KINETIS_NUSBDEV 1 /* One USB device controller */ @@ -354,7 +354,7 @@ # define KINETIS_MPU 1 /* Memory protection unit */ # define KINETIS_EXTBUS 1 /* External bus interface */ # define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NETHERNET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ # define KINETIS_NUSBHOST 1 /* One USB host controller */ # define KINETIS_NUSBOTG 1 /* With USB OTG controller */ # define KINETIS_NUSBDEV 1 /* One USB device controller */ @@ -397,7 +397,7 @@ # define KINETIS_MPU 1 /* Memory protection unit */ # define KINETIS_EXTBUS 1 /* External bus interface */ # define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NETHERNET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ # define KINETIS_NUSBHOST 1 /* One USB host controller */ # define KINETIS_NUSBOTG 1 /* With USB OTG controller */ # define KINETIS_NUSBDEV 1 /* One USB device controller */ @@ -440,7 +440,7 @@ # define KINETIS_MPU 1 /* Memory protection unit */ # define KINETIS_EXTBUS 1 /* External bus interface */ # define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NETHERNET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ # define KINETIS_NUSBHOST 1 /* One USB host controller */ # define KINETIS_NUSBOTG 1 /* With USB OTG controller */ # define KINETIS_NUSBDEV 1 /* One USB device controller */ @@ -483,7 +483,7 @@ # define KINETIS_MPU 1 /* Memory protection unit */ # define KINETIS_EXTBUS 1 /* External bus interface */ # define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NETHERNET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ # define KINETIS_NUSBHOST 1 /* One USB host controller */ # define KINETIS_NUSBOTG 1 /* With USB OTG controller */ # define KINETIS_NUSBDEV 1 /* One USB device controller */ @@ -526,7 +526,7 @@ # define KINETIS_MPU 1 /* Memory protection unit */ # define KINETIS_EXTBUS 1 /* External bus interface */ # define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NETHERNET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ # define KINETIS_NUSBHOST 1 /* One USB host controller */ # define KINETIS_NUSBOTG 1 /* With USB OTG controller */ # define KINETIS_NUSBDEV 1 /* One USB device controller */ @@ -569,7 +569,7 @@ # define KINETIS_MPU 1 /* Memory protection unit */ # define KINETIS_EXTBUS 1 /* External bus interface */ # define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NETHERNET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ # define KINETIS_NUSBHOST 1 /* One USB host controller */ # define KINETIS_NUSBOTG 1 /* With USB OTG controller */ # define KINETIS_NUSBDEV 1 /* One USB device controller */ @@ -612,7 +612,7 @@ # define KINETIS_MPU 1 /* Memory protection unit */ # define KINETIS_EXTBUS 1 /* External bus interface */ # define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NETHERNET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ # define KINETIS_NUSBHOST 1 /* One USB host controller */ # define KINETIS_NUSBOTG 1 /* With USB OTG controller */ # define KINETIS_NUSBDEV 1 /* One USB device controller */ @@ -655,7 +655,7 @@ # define KINETIS_MPU 1 /* Memory protection unit */ # define KINETIS_EXTBUS 1 /* External bus interface */ # define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NETHERNET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ # define KINETIS_NUSBHOST 1 /* One USB host controller */ # define KINETIS_NUSBOTG 1 /* With USB OTG controller */ # define KINETIS_NUSBDEV 1 /* One USB device controller */ @@ -698,7 +698,7 @@ # define KINETIS_MPU 1 /* Memory protection unit */ # define KINETIS_EXTBUS 1 /* External bus interface */ # define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NETHERNET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ # define KINETIS_NUSBHOST 1 /* One USB host controller */ # define KINETIS_NUSBOTG 1 /* With USB OTG controller */ # define KINETIS_NUSBDEV 1 /* One USB device controller */ @@ -741,7 +741,7 @@ # define KINETIS_MPU 1 /* Memory protection unit */ # define KINETIS_EXTBUS 1 /* External bus interface */ # define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NETHERNET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ # define KINETIS_NUSBHOST 1 /* One USB host controller */ # define KINETIS_NUSBOTG 1 /* With USB OTG controller */ # define KINETIS_NUSBDEV 1 /* One USB device controller */ @@ -784,7 +784,7 @@ # define KINETIS_MPU 1 /* Memory protection unit */ # define KINETIS_EXTBUS 1 /* External bus interface */ # define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NETHERNET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ # define KINETIS_NUSBHOST 1 /* One USB host controller */ # define KINETIS_NUSBOTG 1 /* With USB OTG controller */ # define KINETIS_NUSBDEV 1 /* One USB device controller */ diff --git a/arch/arm/src/kinetis/kinetis_enet.h b/arch/arm/src/kinetis/kinetis_enet.h new file mode 100644 index 0000000000..793866800b --- /dev/null +++ b/arch/arm/src/kinetis/kinetis_enet.h @@ -0,0 +1,449 @@ +/******************************************************************************************** + * arch/arm/src/kinetis/kinetis_enet.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_ENET_H +#define __ARCH_ARM_SRC_KINETIS_KINETIS_ENET_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" + +#if defined(KINETIS_NENET) && KINETIS_NENET > 0 + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/* Register Offsets *************************************************************************/ + +#define KINETIS_ENET_EIR_OFFSET 0x0004 /* Interrupt Event Register */ +#define KINETIS_ENET_EIMR_OFFSET 0x0008 /* Interrupt Mask Register */ +#define KINETIS_ENET_RDAR_OFFSET 0x0010 /* Receive Descriptor Active Register */ +#define KINETIS_ENET_TDAR_OFFSET 0x0014 /* Transmit Descriptor Active Register */ +#define KINETIS_ENET_ECR_OFFSET 0x0024 /* Ethernet Control Register */ +#define KINETIS_ENET_MMFR_OFFSET 0x0040 /* MII Management Frame Register */ +#define KINETIS_ENET_MSCR_OFFSET 0x0044 /* MII Speed Control Register */ +#define KINETIS_ENET_MIBC_OFFSET 0x0064 /* MIB Control Register */ +#define KINETIS_ENET_RCR_OFFSET 0x0084 /* Receive Control Register */ +#define KINETIS_ENET_TCR_OFFSET 0x00c4 /* Transmit Control Register */ +#define KINETIS_ENET_PALR_OFFSET 0x00e4 /* Physical Address Lower Register */ +#define KINETIS_ENET_PAUR_OFFSET 0x00e8 /* Physical Address Upper Register */ +#define KINETIS_ENET_OPD_OFFSET 0x00ec /* Opcode/Pause Duration Register */ +#define KINETIS_ENET_IAUR_OFFSET 0x0118 /* Descriptor Individual Upper Address Register */ +#define KINETIS_ENET_IALR_OFFSET 0x011c /* Descriptor Individual Lower Address Register */ +#define KINETIS_ENET_GAUR_OFFSET 0x0120 /* Descriptor Group Upper Address Register */ +#define KINETIS_ENET_GALR_OFFSET 0x0124 /* Descriptor Group Lower Address Register */ +#define KINETIS_ENET_TFWR_OFFSET 0x0144 /* Transmit FIFO Watermark Register */ +#define KINETIS_ENET_RDSR_OFFSET 0x0180 /* Receive Descriptor Ring Start Register */ +#define KINETIS_ENET_TDSR_OFFSET 0x0184 /* Transmit Buffer Descriptor Ring Start Register */ +#define KINETIS_ENET_MRBR_OFFSET 0x0188 /* Maximum Receive Buffer Size Register */ +#define KINETIS_ENET_RSFL_OFFSET 0x0190 /* Receive FIFO Section Full Threshold */ +#define KINETIS_ENET_RSEM_OFFSET 0x0194 /* Receive FIFO Section Empty Threshold */ +#define KINETIS_ENET_RAEM_OFFSET 0x0198 /* Receive FIFO Almost Empty Threshold */ +#define KINETIS_ENET_RAFL_OFFSET 0x019c /* Receive FIFO Almost Full Threshold */ +#define KINETIS_ENET_TSEM_OFFSET 0x01a0 /* Transmit FIFO Section Empty Threshold */ +#define KINETIS_ENET_TAEM_OFFSET 0x01a4 /* Transmit FIFO Almost Empty Threshold */ +#define KINETIS_ENET_TAFL_OFFSET 0x01a8 /* Transmit FIFO Almost Full Threshold */ +#define KINETIS_ENET_TIPG_OFFSET 0x01ac /* Transmit Inter-Packet Gap */ +#define KINETIS_ENET_FTRL_OFFSET 0x01b0 /* Frame Truncation Length */ +#define KINETIS_ENET_TACC_OFFSET 0x01c0 /* Transmit Accelerator Function Configuration */ +#define KINETIS_ENET_RACC_OFFSET 0x01c4 /* Receive Accelerator Function Configuration */ + +#define KINETIS_ENET_ATCR_OFFSET 0x0400 /* Timer Control Register */ +#define KINETIS_ENET_ATVR_OFFSET 0x0404 /* Timer Value Register */ +#define KINETIS_ENET_ATOFF_OFFSET 0x0408 /* Timer Offset Register */ +#define KINETIS_ENET_ATPER_OFFSET 0x040c /* Timer Period Register */ +#define KINETIS_ENET_ATCOR_OFFSET 0x0410 /* Timer Correction Register */ +#define KINETIS_ENET_ATINC_OFFSET 0x0414 /* Time-Stamping Clock Period Register */ +#define KINETIS_ENET_ATSTMP_OFFSET 0x0418 /* Timestamp of Last Transmitted Frame */ + +#define KINETIS_ENET_TGSR_OFFSET 0x0604 /* Timer Global Status Register */ +#define KINETIS_ENET_TCSR0_OFFSET 0x0608 /* Timer Control Status Register */ +#define KINETIS_ENET_TCCR0_OFFSET 0x060c /* Timer Compare Capture Register */ +#define KINETIS_ENET_TCSR1_OFFSET 0x0610 /* Timer Control Status Register */ +#define KINETIS_ENET_TCCR1_OFFSET 0x0614 /* Timer Compare Capture Register */ +#define KINETIS_ENET_TCSR2_OFFSET 0x0618 /* Timer Control Status Register */ +#define KINETIS_ENET_TCCR2_OFFSET 0x061c /* Timer Compare Capture Register */ +#define KINETIS_ENET_TCSR3_OFFSET 0x0620 /* Timer Control Status Register */ +#define KINETIS_ENET_TCCR3_OFFSET 0x0624 /* Timer Compare Capture Register */ + +/* Register Addresses ***********************************************************************/ + +#define KINETIS_ENET_EIR (KINETIS_EMAC_BASE+KINETIS_ENET_EIR_OFFSET) +#define KINETIS_ENET_EIMR (KINETIS_EMAC_BASE+KINETIS_ENET_EIMR_OFFSET) +#define KINETIS_ENET_RDAR (KINETIS_EMAC_BASE+KINETIS_ENET_RDAR_OFFSET) +#define KINETIS_ENET_TDAR (KINETIS_EMAC_BASE+KINETIS_ENET_TDAR_OFFSET) +#define KINETIS_ENET_ECR (KINETIS_EMAC_BASE+KINETIS_ENET_ECR_OFFSET) +#define KINETIS_ENET_MMFR (KINETIS_EMAC_BASE+KINETIS_ENET_MMFR_OFFSET) +#define KINETIS_ENET_MSCR (KINETIS_EMAC_BASE+KINETIS_ENET_MSCR_OFFSET) +#define KINETIS_ENET_MIBC (KINETIS_EMAC_BASE+KINETIS_ENET_MIBC_OFFSET) +#define KINETIS_ENET_RCR (KINETIS_EMAC_BASE+KINETIS_ENET_RCR_OFFSET) +#define KINETIS_ENET_TCR (KINETIS_EMAC_BASE+KINETIS_ENET_TCR_OFFSET) +#define KINETIS_ENET_PALR (KINETIS_EMAC_BASE+KINETIS_ENET_PALR_OFFSET) +#define KINETIS_ENET_PAUR (KINETIS_EMAC_BASE+KINETIS_ENET_PAUR_OFFSET) +#define KINETIS_ENET_OPD (KINETIS_EMAC_BASE+KINETIS_ENET_OPD_OFFSET) +#define KINETIS_ENET_IAUR (KINETIS_EMAC_BASE+KINETIS_ENET_IAUR_OFFSET) +#define KINETIS_ENET_IALR (KINETIS_EMAC_BASE+KINETIS_ENET_IALR_OFFSET) +#define KINETIS_ENET_GAUR (KINETIS_EMAC_BASE+KINETIS_ENET_GAUR_OFFSET) +#define KINETIS_ENET_GALR (KINETIS_EMAC_BASE+KINETIS_ENET_GALR_OFFSET) +#define KINETIS_ENET_TFWR (KINETIS_EMAC_BASE+KINETIS_ENET_TFWR_OFFSET) +#define KINETIS_ENET_RDSR (KINETIS_EMAC_BASE+KINETIS_ENET_RDSR_OFFSET) +#define KINETIS_ENET_TDSR (KINETIS_EMAC_BASE+KINETIS_ENET_TDSR_OFFSET) +#define KINETIS_ENET_MRBR (KINETIS_EMAC_BASE+KINETIS_ENET_MRBR_OFFSET) +#define KINETIS_ENET_RSFL (KINETIS_EMAC_BASE+KINETIS_ENET_RSFL_OFFSET) +#define KINETIS_ENET_RSEM (KINETIS_EMAC_BASE+KINETIS_ENET_RSEM_OFFSET) +#define KINETIS_ENET_RAEM (KINETIS_EMAC_BASE+KINETIS_ENET_RAEM_OFFSET) +#define KINETIS_ENET_RAFL (KINETIS_EMAC_BASE+KINETIS_ENET_RAFL_OFFSET) +#define KINETIS_ENET_TSEM (KINETIS_EMAC_BASE+KINETIS_ENET_TSEM_OFFSET) +#define KINETIS_ENET_TAEM (KINETIS_EMAC_BASE+KINETIS_ENET_TAEM_OFFSET) +#define KINETIS_ENET_TAFL (KINETIS_EMAC_BASE+KINETIS_ENET_TAFL_OFFSET) +#define KINETIS_ENET_TIPG (KINETIS_EMAC_BASE+KINETIS_ENET_TIPG_OFFSET) +#define KINETIS_ENET_FTRL (KINETIS_EMAC_BASE+KINETIS_ENET_FTRL_OFFSET) +#define KINETIS_ENET_TACC (KINETIS_EMAC_BASE+KINETIS_ENET_TACC_OFFSET) +#define KINETIS_ENET_RACC (KINETIS_EMAC_BASE+KINETIS_ENET_RACC_OFFSET) + +#define KINETIS_ENET_ATCR (KINETIS_EMAC_BASE+KINETIS_ENET_ATCR_OFFSET) +#define KINETIS_ENET_ATVR (KINETIS_EMAC_BASE+KINETIS_ENET_ATVR_OFFSET) +#define KINETIS_ENET_ATOFF (KINETIS_EMAC_BASE+KINETIS_ENET_ATOFF_OFFSET) +#define KINETIS_ENET_ATPER (KINETIS_EMAC_BASE+KINETIS_ENET_ATPER_OFFSET) +#define KINETIS_ENET_ATCOR (KINETIS_EMAC_BASE+KINETIS_ENET_ATCOR_OFFSET) +#define KINETIS_ENET_ATINC (KINETIS_EMAC_BASE+KINETIS_ENET_ATINC_OFFSET) +#define KINETIS_ENET_ATSTMP (KINETIS_EMAC_BASE+KINETIS_ENET_ATSTMP_OFFSET) + +#define KINETIS_ENET_TGSR (KINETIS_EMAC_BASE+KINETIS_ENET_TGSR_OFFSET) +#define KINETIS_ENET_TCSR0 (KINETIS_EMAC_BASE+KINETIS_ENET_TCSR0_OFFSET) +#define KINETIS_ENET_TCCR0 (KINETIS_EMAC_BASE+KINETIS_ENET_TCCR0_OFFSET) +#define KINETIS_ENET_TCSR1 (KINETIS_EMAC_BASE+KINETIS_ENET_TCSR1_OFFSET) +#define KINETIS_ENET_TCCR1 (KINETIS_EMAC_BASE+KINETIS_ENET_TCCR1_OFFSET) +#define KINETIS_ENET_TCSR2 (KINETIS_EMAC_BASE+KINETIS_ENET_TCSR2_OFFSET) +#define KINETIS_ENET_TCCR2 (KINETIS_EMAC_BASE+KINETIS_ENET_TCCR2_OFFSET) +#define KINETIS_ENET_TCSR3 (KINETIS_EMAC_BASE+KINETIS_ENET_TCSR3_OFFSET) +#define KINETIS_ENET_TCCR3 (KINETIS_EMAC_BASE+KINETIS_ENET_TCCR3_OFFSET) + +/* Register Bit Definitions *****************************************************************/ + +/* Interrupt Event Register, Interrupt Mask Register */ + + /* Bit 31: Reserved */ +#define ENET_INT_BABR (1 << 30) /* Bit 30: Babbling Receive Error */ +#define ENET_INT_BABT (1 << 29) /* Bit 29: Babbling Transmit Error */ +#define ENET_INT_GRA (1 << 28) /* Bit 28: Graceful Stop Complete */ +#define ENET_INT_TXF (1 << 27) /* Bit 27: Transmit Frame Interrupt */ +#define ENET_INT_TXB (1 << 26) /* Bit 26: Transmit Buffer Interrupt */ +#define ENET_INT_RXF (1 << 25) /* Bit 25: Receive Frame Interrupt */ +#define ENET_INT_RXB (1 << 24) /* Bit 24: Receive Buffer Interrupt */ +#define ENET_INT_MII (1 << 23) /* Bit 23: MII Interrupt */ +#define ENET_INT_EBERR (1 << 22) /* Bit 22: Ethernet Bus Error */ +#define ENET_INT_LC (1 << 21) /* Bit 21: Late Collision */ +#define ENET_INT_RL (1 << 20) /* Bit 20: Collision Retry Limit */ +#define ENET_INT_UN (1 << 19) /* Bit 19: Transmit FIFO underrun */ +#define ENET_INT_PLR (1 << 18) /* Bit 18: Payload receive error */ +#define ENET_INT_WAKEUP (1 << 17) /* Bit 17: Node wake-up request indication */ +#define ENET_INT_TS_AVAIL (1 << 16) /* Bit 16: Transmit timestamp available */ +#define ENET_INT_TS_TIMER (1 << 15) /* Bit 15: Timestamp timer */ + /* Bits 0-14: Reserved */ +/* Receive Descriptor Active Register */ + /* Bits 0-23: Reserved */ +#define ENET_RDAR (1 << 24) /* Bit 24: Receive descriptor active */ + /* Bits 25-31: Reserved */ +/* Transmit Descriptor Active Register */ + /* Bits 0-23: Reserved */ +#define ENET_TDAR (1 << 24) /* Bit 24: Transmit descriptor active */ + /* Bits 25-31: Reserved */ +/* Ethernet Control Register */ + +#define ENET_ECR_RESET (1 << 0) /* Bit 0: Ethernet MAC reset */ +#define ENET_ECR_ETHEREN (1 << 1) /* Bit 1: Ethernet enable */ +#define ENET_ECR_MAGICEN (1 << 2) /* Bit 2: Magic packet detection enable */ +#define ENET_ECR_SLEEP (1 << 3) /* Bit 3: Sleep mode enable */ +#define ENET_ECR_EN1588 (1 << 4) /* Bit 4: EN1588 enable */ + /* Bit 5: Reserved */ +#define ENET_ECR_DBGEN (1 << 6) /* Bit 6: Debug enable */ +#define ENET_ECR_STOPEN (1 << 7) /* Bit 7: STOPEN Signal Control */ + /* Bits 8-31: Reserved */ +/* MII Management Frame Register */ + +#define ENET_MMFR_DATA_SHIFT (0) /* Bits 0-15: Management frame data */ +#define ENET_MMFR_DATA_MASK (0xffff << ENET_MMFR_DATA_SHIFT) +#define ENET_MMFR_TA_SHIFT (16) /* Bits 16-17: Turn around */ +#define ENET_MMFR_TA_MASK (3 << ENET_MMFR_TA_SHIFT) +#define ENET_MMFR_RA_SHIFT (18) /* Bits 18-22: Register address */ +#define ENET_MMFR_RA_MASK (31 << ENET_MMFR_RA_SHIFT) +#define ENET_MMFR_PA_SHIFT (23) /* Bits 23-27: PHY address */ +#define ENET_MMFR_PA_MASK (31 << ENET_MMFR_PA_SHIFT) +#define ENET_MMFR_OP_SHIFT (28) /* Bits 28-29: Operation code */ +#define ENET_MMFR_OP_MASK (3 << ENET_MMFR_OP_SHIFT) +# define ENET_MMFR_OP_WRNOTMII (0 << ENET_MMFR_OP_SHIFT) /* Write frame, not MII compliant */ +# define ENET_MMFR_OP_WRMII (1 << ENET_MMFR_OP_SHIFT) /* Write frame, MII management frame */ +# define ENET_MMFR_OP_RDMII (2 << ENET_MMFR_OP_SHIFT) /* Read frame, MII management frame */ +# define ENET_MMFR_OP_RdNOTMII (3 << ENET_MMFR_OP_SHIFT) /* Read frame, not MII compliant */ +#define ENET_MMFR_ST_SHIFT (30) /* Bits 30-31: Start of frame delimiter */ +#define ENET_MMFR_ST_MASK (3 << ENET_MMFR_ST_SHIFT) + +/* MII Speed Control Register */ + /* Bit 0: Reserved */ +#define ENET_MSCR_MII_SPEED_SHIFT (1) /* Bits 1-6: MII speed */ +#define ENET_MSCR_MII_SPEED_MASK (63 << ENET_MSCR_MII_SPEED_SHIFT) +#define ENET_MSCR_DIS_PRE (1 << 7) /* Bit 7: Disable preamble */ +#define ENET_MSCR_HOLDTIME_SHIFT (8) /* Bits 8-10: Holdtime on MDIO output */ +#define ENET_MSCR_HOLDTIME_MASK (7 << ENET_MSCR_HOLDTIME_SHIFT) +# define ENET_MSCR_HOLDTIME_1CYCLE (0 << ENET_MSCR_HOLDTIME_SHIFT) /* 1 internal module clock cycle */ +# define ENET_MSCR_HOLDTIME_2CYCLES (1 << ENET_MSCR_HOLDTIME_SHIFT) /* 2 internal module clock cycles */ +# define ENET_MSCR_HOLDTIME_3CYCLES (2 << ENET_MSCR_HOLDTIME_SHIFT) /* 3 internal module clock cycles */ +# define ENET_MSCR_HOLDTIME_8CYCLES (7 << ENET_MSCR_HOLDTIME_SHIFT) /* 8 internal module clock cycles */ + /* Bits 11-31: Reserved */ +/* MIB Control Register */ + /* Bits 0-28: Reserved */ +#define ENET_MIBC_MIB_CLEAR (1 << 29) /* Bit 29: MIB clear */ +#define ENET_MIBC_MIB_IDLE (1 << 30) /* Bit 30: MIB idle */ +#define ENET_MIBC_MIB_DIS (1 << 31) /* Bit 31: Disable MIB logic */ + +/* Receive Control Register */ + +#define ENET_RCR_LOOP (1 << 0) /* Bit 0: Internal loopback */ +#define ENET_RCR_DRT (1 << 1) /* Bit 1: Disable receive on transmit */ +#define ENET_RCR_MII_MODE (1 << 2) /* Bit 2: Media independent interface mode */ +#define ENET_RCR_PROM (1 << 3) /* Bit 3: Promiscuous mode */ +#define ENET_RCR_BC_REJ (1 << 4) /* Bit 4: Broadcast frame reject */ +#define ENET_RCR_FCE (1 << 5) /* Bit 5: Flow control enable */ + /* Bits 6-7: Reserved */ +#define ENET_RCR_RMII_MODE (1 << 8) /* Bit 8: RMII mode enable */ +#define ENET_RCR_RMII_10T (1 << 9) /* Bit 9: Enables 10-Mbps mode of the RMII */ + /* Bits 10-11: Reserved */ +#define ENET_RCR_PADEN (1 << 12) /* Bit 12: Enable frame padding remove on receive */ +#define ENET_RCR_PAUFWD (1 << 13) /* Bit 13: Terminate/forward pause frames */ +#define ENET_RCR_CRCFWD (1 << 14) /* Bit 14: Terminate/forward received CRC */ +#define ENET_RCR_CFEN (1 << 15) /* Bit 15: MAC control frame enable */ +#define ENET_RCR_MAX_FL_SHIFT (16) /* Bits 16-29: Maximum frame length */ +#define ENET_RCR_MAX_FL_MASK (0x3fff << ENET_RCR_MAX_FL_SHIFT) +#define ENET_RCR_NLC (1 << 30) /* Bit 30: Payload length check disable */ +#define ENET_RCR_GRS (1 << 31) /* Bit 31: Graceful receive stopped */ + +/* Transmit Control Register */ + +#define ENET_TCR_GTS (1 << 0) /* Bit 0: Graceful transmit stop */ + /* Bit 1: Reserved */ +#define ENET_TCR_ADDINS (1 << 8) /* Bit 8: Set MAC address on transmit */ +#define ENET_TCR_FDEN (1 << 2) /* Bit 2: Full duplex enable */ +#define ENET_TCR_TFC_PAUSE (1 << 3) /* Bit 3: Transmit frame control pause */ +#define ENET_TCR_RFC_PAUSE (1 << 4) /* Bit 4: Receive frame control pause */ +#define ENET_TCR_ADDSEL_SHIFT (5) /* Bits 5-7: Source MAC address select on transmit */ +#define ENET_TCR_ADDSEL_MASK (7 << ENET_TCR_ADDSEL_SHIFT) +# define ENET_TCR_ADDSEL_PADDR12 (0 << ENET_TCR_ADDSEL_SHIFT) /* Node MAC address programmed on PADDR1/2 registers */ +#define ENET_TCR_CRCFWD (1 << 9) /* Bit 9: Forward frame from application with CRC */ + /* Bits 10-31: Reserved */ +/* Physical Address Lower/Upper Register (32-bits of 48-address) */ +/* Physical Address Upper Register */ + +#define ENET_PAUR_TYPE_SHIFT (0) /* Bits 0-15: Type field in PAUSE frame */ +#define ENET_PAUR_TYPE_MASK (0xffff << ENET_PAUR_TYPE_MASK) +#define ENET_PAUR_PADDR2_SHIFT (16) /* Bits 16-31: Bytes 4 and 5 of the 6-byte address */ +#define ENET_PAUR_PADDR2_MASK (0xffff << ENET_PAUR_PADDR2_SHIFT) + +/* Opcode/Pause Duration Register */ + +#define ENET_OPD_PAUSE_DUR_SHIFT (0) /* Bits 0-15: Pause duration */ +#define ENET_OPD_PAUSE_DUR_MASK (0xffff << ENET_OPD_PAUSE_DUR_SHIFT) +#define ENET_OPD_OPCODE_SHIFT (16) /* Bits 16-31: Opcode field in PAUSE frames */ +#define ENET_OPD_OPCODE_MASK (0xffff << ENET_OPD_OPCODE_SHIFT) + +/* Descriptor Individual Uupper/Lower Address Register (64-bit address in two 32-bit registers) */ +/* Descriptor Group Upper/Lower Address Register (64-bit address in two 32-bit registers) */ + +/* Transmit FIFO Watermark Register */ + +#define ENET_TFWR_TFWR_SHIFT (0) /* Bits 0-5: Transmit FIFO write */ + /* Bits 6-7: Reserved */ +#define ENET_TFWR_TFWR_MASK (63 << ENET_TFWR_TFWR_SHIFT) +#define ENET_TFWR_STRFWD (1 << 8) /* Bit 8: Store and forward enable */ + /* Bits 9-31: Reserved */ +/* Receive Descriptor Ring Start Register */ + /* Bits 0-2: Reserved */ +#define ENET_RDSR_SHIFT (3) /* Bits 3-31: Start of the receive buffer descriptor queue */ +#define ENET_RDSR_MASK (0xfffffff8) + +/* Transmit Buffer Descriptor Ring Start Register */ + /* Bits 0-2: Reserved */ +#define ENET_TDSR_SHIFT (3) /* Bits 3-31: Start of the transmit buffer descriptor queue */ +#define ENET_TDSR_MASK (0xfffffff8) + +/* Maximum Receive Buffer Size Register */ + /* Bits 14-31: Reserved */ +#define ENET_MRBR_SHIFT (4) /* Bits 4-13: Receive buffer size in bytes */ +#define ENET_MRBR_MASK (0x3ff << ENET_MRBR_SHIFT) + /* Bits 0-3: Reserved */ +/* Receive FIFO Section Full Threshold */ + /* Bits 8-31: Reserved */ +#define ENET_RSFL_SHIFT (0) /* Bits 0-7: Value of receive FIFO section full threshold */ +#define ENET_RSFL_MASK (0xff << ENET_RSFL_SHIFT) + +/* Receive FIFO Section Empty Threshold */ + +#define ENET_RSEM_SHIFT (0) /* Bits 0-7: Value of the receive FIFO section empty threshold */ +#define ENET_RSEM_MASK (0xff << ENET_RSEM_SHIFT) + /* Bits 8-31: Reserved */ +/* Receive FIFO Almost Empty Threshold */ + +#define ENET_RAEM_SHIFT (0) /* Bits 0-7: Value of the receive FIFO almost empty threshold */ +#define ENET_RSEM_MASK (0xff << ENET_RAEM_SHIFT) + /* Bits 8-31: Reserved */ +/* Receive FIFO Almost Full Threshold */ + +#define ENET_RAFL_SHIFT (0) /* Bits 0-7: Value of the receive FIFO almost full threshold */ +#define ENET_RAFL_MASK (0xff << ENET_RAFL_SHIFT) + /* Bits 8-31: Reserved */ +/* Transmit FIFO Section Empty Threshold */ + +#define ENET_TSEM_SHIFT (0) /* Bits 0-7: Value of the transmit FIFO section empty threshold */ +#define ENET_TSEM_MASK (0xff << ENET_TSEM_SHIFT) + /* Bits 8-31: Reserved */ +/* Transmit FIFO Almost Empty Threshold */ + +#define ENET_TAEM_SHIFT (0) /* Bits 0-7: Value of the transmit FIFO section empty threshold */ +#define ENET_TAEM_MASK (0xff << ENET_TAEM_SHIFT) + /* Bits 8-31: Reserved */ +/* Transmit FIFO Almost Full Threshold */ + +#define ENET_TAFL_SHIFT (0) /* Bits 0-7: Value of the transmit FIFO section empty threshold */ +#define ENET_TAFL_MASK (0xff << ENET_TAFL_SHIFT) + /* Bits 8-31: Reserved */ +/* Transmit Inter-Packet Gap */ + +#define ENET_TIPG_SHIFT (0) /* Bits 0-4: Value of the transmit FIFO section empty threshold */ +#define ENET_TIPG_MASK (31 << ENET_TIPG_SHIFT) + /* Bits 5-31: Reserved */ +/* Frame Truncation Length */ + +#define ENET_FTRL_SHIFT (0) /* Bits 0-13: Value of the transmit FIFO section empty threshold */ +#define ENET_FTRL_MASK (0x3fff << ENET_FTRL_SHIFT) + /* Bits 14-31: Reserved */ +/* Transmit Accelerator Function Configuration */ + +#define ENET_TACC_SHIFT16 (1 << 0) /* Bit 0: TX FIFO shift-16 */ + /* Bits 1-2: Reserved */ +#define ENET_TACC_IPCHK (1 << 3) /* Bit 3: Enables insertion of IP header checksum */ +#define ENET_TACC_PROCHK (1 << 4) /* Bit 4: Enables insertion of protocol checksum */ + /* Bits 5-31: Reserved */ +/* Receive Accelerator Function Configuration */ + +#define ENET_RACC_PADREM (1 << 0) /* Bit 0: Enable padding removal for short IP frames */ +#define ENET_RACC_IPDIS (1 << 1) /* Bit 1: Enable discard of frames with wrong IPv4 header checksum */ +#define ENET_RACC_PRODIS (1 << 2) /* Bit 2: Enable discard of frames with wrong protocol checksum */ + /* Bits 3-5: Reserved */ +#define ENET_RACC_LINEDIS (1 << 6) /* Bit 6: Enable discard of frames with MAC layer errors */ +#define ENET_RACC_SHIFT16 (1 << 7) /* Bit 7: RX FIFO shift-16 */ + /* Bits 8-31: Reserved */ +/* Timer Control Register */ + +#define ENET_ATCR_EN (1 << 0) /* Bit 0: Enable timer */ + /* Bit 1: Reserved */ +#define ENET_ATCR_OFFEN (1 << 2) /* Bit 2: Enable one-shot offset event */ +#define ENET_ATCR_OFFRST (1 << 3) /* Bit 3: Reset timer on offset event */ +#define ENET_ATCR_PEREN (1 << 4) /* Bit 4: Enable periodical event */ + /* Bits 5-6: Reserved */ +#define ENET_ATCR_PINPER (1 << 7) /* Bit 7: Enables event signal output assertion on period event */ + /* Bit 8: Reserved */ +#define ENET_ATCR_RESTART (1 << 9) /* Bit 9: Reset timer */ + /* Bit 10: Reserved */ +#define ENET_ATCR_CAPTURE (1 << 11) /* Bit 11: Capture timer value */ + /* Bit 12: Reserved */ +#define ENET_ATCR_SLAVE (1 << 13) /* Bit 13: Enable timer slave mode */ + /* Bits 14-31: Reserved */ +/* Timer Value Register (32-bit timer value) */ +/* Timer Offset Register (32-bit offset value) */ +/* Timer Period Register (32-bit timer period) */ + +/* Timer Correction Register */ + +#define ENET_ATCOR_MASK (0x7fffffff) /* Bits 0-3: Correction counter wrap-around value */ + /* Bit 31: Reserved */ +/* Time-Stamping Clock Period Register */ + +#define ENET_ATINC_INC_SHIFT (0) /* Bits 0-6: Clock period of the timestamping clock (ts_clk) in nanoseconds */ +#define ENET_ATINC_INC_MASK (0x7f << ENET_ATINC_INC_SHIFT) + /* Bit 7: Reserved */ +#define ENET_ATINC_INC_CORR_SHIFT (8) /* Bits 8-14: Correction increment value */ +#define ENET_ATINC_INC_CORR_MASK (0x7f << ENET_ATINC_INC_CORR_SHIFT) + /* Bits 15-31: Reserved */ +/* Timestamp of Last Transmitted Frame (32-bit timestamp) */ + +/* Timer Global Status Register */ + +#define ENET_TGSR_TF0 (1 << 0) /* Bit 0: Copy of Timer Flag for channel 0 */ +#define ENET_TGSR_TF1 (1 << 1) /* Bit 1: Copy of Timer Flag for channel 1 */ +#define ENET_TGSR_TF2 (1 << 2) /* Bit 2: Copy of Timer Flag for channel 2 */ +#define ENET_TGSR_TF3 (1 << 3) /* Bit 3: Copy of Timer Flag for channel 3 */ + /* Bits 14-31: Reserved */ +/* Timer Control Status Register n */ + +#define ENET_TCSR_TDRE (1 << 0) /* Bit 0: Timer DMA Request Enable */ + /* Bit 1: Reserved */ +#define ENET_TCSR_TMODE_SHIFT (2) /* Bits 2-5: Timer Mode */ +#define ENET_TCSR_TMODE_MASK (15 << ENET_TCSR_TMODE_SHIFT) +# define ENET_TCSR_TMODE_DISABLED (0 << ENET_TCSR_TMODE_SHIFT) /* Disabled */ +# define ENET_TCSR_TMODE_ICRISING (1 << ENET_TCSR_TMODE_SHIFT) /* Input Capture on rising edge */ +# define ENET_TCSR_TMODE_ICFALLLING (2 << ENET_TCSR_TMODE_SHIFT) /* Input Capture on falling edge */ +# define ENET_TCSR_TMODE_ICBOTH (3 << ENET_TCSR_TMODE_SHIFT) /* Input Capture on both edges */ +# define ENET_TCSR_TMODE_OCSW (4 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, S/W only */ +# define ENET_TCSR_TMODE_OCTOGGLE (5 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, toggle on compare */ +# define ENET_TCSR_TMODE_OCCLR (6 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, clear on compare */ +# define ENET_TCSR_TMODE_OCSET (7 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, set on compare */ +# define ENET_TCSR_TMODE_OCSETCLR (9 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, set on compare, clear on overflow */ +# define ENET_TCSR_TMODE_OCCLRSET (10 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, clear on compare, set on overflow */ +# define ENET_TCSR_TMODE_PCPULSEL (14 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, pulse low on compare */ +# define ENET_TCSR_TMODE_PCPULSEH (15 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, pulse high on compare */ +#define ENET_TCSR_TIE (1 << 6) /* Bit 6: Timer interrupt enable */ +#define ENET_TCSR_TF (1 << 7) /* Bit 7: Timer Flag */ + /* Bits 8-31: Reserved */ +/* Timer Compare Capture Register (32-bit compare value) */ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +#endif /* KINETIS_NENET && KINETIS_NENET > 0 */ +#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_ENET_H */ diff --git a/arch/arm/src/kinetis/kinetis_memorymap.h b/arch/arm/src/kinetis/kinetis_memorymap.h index 4f1a84151e..e7eeb8d117 100644 --- a/arch/arm/src/kinetis/kinetis_memorymap.h +++ b/arch/arm/src/kinetis/kinetis_memorymap.h @@ -141,7 +141,7 @@ # define KINETIS_UART1_BASE 0x4006b000 /* UART1 */ # define KINETIS_UART2_BASE 0x4006c000 /* UART2 */ # define KINETIS_UART3_BASE 0x4006d000 /* UART3 */ -# define KINETIS_USBOTG_BASE 0x40072000 /* USB OTG FS/LS */ +# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */ # define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ # define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */ # define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */ @@ -272,7 +272,7 @@ # define KINETIS_UART1_BASE 0x4006b000 /* UART1 */ # define KINETIS_UART2_BASE 0x4006c000 /* UART2 */ # define KINETIS_UART3_BASE 0x4006d000 /* UART3 */ -# define KINETIS_USBOTG_BASE 0x40072000 /* USB OTG FS/LS */ +# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */ # define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ # define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */ # define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */ diff --git a/arch/arm/src/kinetis/kinetis_usbotg.h b/arch/arm/src/kinetis/kinetis_usbotg.h new file mode 100644 index 0000000000..743a7d1385 --- /dev/null +++ b/arch/arm/src/kinetis/kinetis_usbotg.h @@ -0,0 +1,222 @@ +/******************************************************************************************** + * arch/arm/src/kinetis/kinetis_usbotg.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_USBOTG_H +#define __ARCH_ARM_SRC_KINETIS_KINETIS_USBOTG_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/* Register Offsets *************************************************************************/ + +#define KINETIS_USB_PERID_OFFSET 0x0000 /* Peripheral ID Register */ +#define KINETIS_USB_IDCOMP_OFFSET 0x0004 /* Peripheral ID Complement Register */ +#define KINETIS_USB_REV_OFFSET 0x0008 /* Peripheral Revision Register */ +#define KINETIS_USB_ADDINFO_OFFSET 0x000c /* Peripheral Additional Info Register */ +#define KINETIS_USB_OTGISTAT_OFFSET 0x0010 /* OTG Interrupt Status Register */ +#define KINETIS_USB_OTGICR_OFFSET 0x0014 /* OTG Interrupt Control Register */ +#define KINETIS_USB_OTGSTAT_OFFSET 0x0018 /* OTG Status Register */ +#define KINETIS_USB_OTGCTL_OFFSET 0x001c /* OTG Control Register */ +#define KINETIS_USB_ISTAT_OFFSET 0x0080 /* Interrupt Status Register */ +#define KINETIS_USB_INTEN_OFFSET 0x0084 /* Interrupt Enable Register */ +#define KINETIS_USB_ERRSTAT_OFFSET 0x0088 /* Error Interrupt Status Register */ +#define KINETIS_USB_ERREN_OFFSET 0x008c /* Error Interrupt Enable Register */ +#define KINETIS_USB_STAT_OFFSET 0x0090 /* Status Register */ +#define KINETIS_USB_CTL_OFFSET 0x0094 /* Control Register */ +#define KINETIS_USB_ADDR_OFFSET 0x0098 /* Address Register */ +#define KINETIS_USB_BDTPAGE1_OFFSET 0x009c /* BDT Page Register 1 */ +#define KINETIS_USB_FRMNUML_OFFSET 0x00a0 /* Frame Number Register Low */ +#define KINETIS_USB_FRMNUMH_OFFSET 0x00a4 /* Frame Number Register High */ +#define KINETIS_USB_TOKEN_OFFSET 0x00a8 /* Token Register */ +#define KINETIS_USB_SOFTHLD_OFFSET 0x00ac /* SOF Threshold Register */ +#define KINETIS_USB_BDTPAGE2_OFFSET 0x00b0 /* BDT Page Register 2 */ +#define KINETIS_USB_BDTPAGE3_OFFSET 0x00b4 /* BDT Page Register 3 */ + +#define KINETIS_USB_ENDPT_OFFSET(n) (0x00c0+((n)<<2)) /* Endpoint n Control Register */ +#define KINETIS_USB_ENDPT0_OFFSET 0x00c0 /* Endpoint 0 Control Register */ +#define KINETIS_USB_ENDPT1_OFFSET 0x00c4 /* Endpoint 1 Control Register */ +#define KINETIS_USB_ENDPT2_OFFSET 0x00c8 /* Endpoint 2 Control Register */ +#define KINETIS_USB_ENDPT3_OFFSET 0x00cc /* Endpoint 3 Control Register */ +#define KINETIS_USB_ENDPT4_OFFSET 0x00d0 /* Endpoint 4 Control Register */ +#define KINETIS_USB_ENDPT5_OFFSET 0x00d4 /* Endpoint 5 Control Register */ +#define KINETIS_USB_ENDPT6_OFFSET 0x00d8 /* Endpoint 6 Control Register */ +#define KINETIS_USB_ENDPT7_OFFSET 0x00dc /* Endpoint 7 Control Register */ +#define KINETIS_USB_ENDPT8_OFFSET 0x00e0 /* Endpoint 8 Control Register */ +#define KINETIS_USB_ENDPT9_OFFSET 0x00e4 /* Endpoint 9 Control Register */ +#define KINETIS_USB_ENDPT10_OFFSET 0x00e8 /* Endpoint 10 Control Register */ +#define KINETIS_USB_ENDPT11_OFFSET 0x00ec /* Endpoint 11 Control Register */ +#define KINETIS_USB_ENDPT12_OFFSET 0x00f0 /* Endpoint 12 Control Register */ +#define KINETIS_USB_ENDPT13_OFFSET 0x00f4 /* Endpoint 13 Control Register */ +#define KINETIS_USB_ENDPT14_OFFSET 0x00f8 /* Endpoint 14 Control Register */ +#define KINETIS_USB_ENDPT15_OFFSET 0x00fc /* Endpoint 15 Control Register */ + +#define KINETIS_USB_USBCTRL_OFFSET 0x0100 /* USB Control Register */ +#define KINETIS_USB_OBSERVE_OFFSET 0x0104 /* USB OTG Observe Register */ +#define KINETIS_USB_CONTROL_OFFSET 0x0108 /* USB OTG Control Register */ +#define KINETIS_USB_USBTRC0_OFFSET 0x010c /* USB Transceiver Control Register 0 */ + +/* Register Addresses ***********************************************************************/ + +#define KINETIS_USB0_PERID (KINETIS_USB0_BASE+KINETIS_USB_PERID_OFFSET) +#define KINETIS_USB0_IDCOMP (KINETIS_USB0_BASE+KINETIS_USB_IDCOMP_OFFSET) +#define KINETIS_USB0_REV (KINETIS_USB0_BASE+KINETIS_USB_REV_OFFSET) +#define KINETIS_USB0_ADDINFO (KINETIS_USB0_BASE+KINETIS_USB_ADDINFO_OFFSET) +#define KINETIS_USB0_OTGISTAT (KINETIS_USB0_BASE+KINETIS_USB_OTGISTAT_OFFSET) +#define KINETIS_USB0_OTGICR (KINETIS_USB0_BASE+KINETIS_USB_OTGICR_OFFSET) +#define KINETIS_USB0_OTGSTAT (KINETIS_USB0_BASE+KINETIS_USB_OTGSTAT_OFFSET) +#define KINETIS_USB0_OTGCTL (KINETIS_USB0_BASE+KINETIS_USB_OTGCTL_OFFSET) +#define KINETIS_USB0_ISTAT (KINETIS_USB0_BASE+KINETIS_USB_ISTAT_OFFSET) +#define KINETIS_USB0_INTEN (KINETIS_USB0_BASE+KINETIS_USB_INTEN_OFFSET) +#define KINETIS_USB0_ERRSTAT (KINETIS_USB0_BASE+KINETIS_USB_ERRSTAT_OFFSET) +#define KINETIS_USB0_ERREN (KINETIS_USB0_BASE+KINETIS_USB_ERREN_OFFSET) +#define KINETIS_USB0_STAT (KINETIS_USB0_BASE+KINETIS_USB_STAT_OFFSET) +#define KINETIS_USB0_CTL (KINETIS_USB0_BASE+KINETIS_USB_CTL_OFFSET) +#define KINETIS_USB0_ADDR (KINETIS_USB0_BASE+KINETIS_USB_ADDR_OFFSET) +#define KINETIS_USB0_BDTPAGE1 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE1_OFFSET) +#define KINETIS_USB0_FRMNUML (KINETIS_USB0_BASE+KINETIS_USB_FRMNUML_OFFSET) +#define KINETIS_USB0_FRMNUMH (KINETIS_USB0_BASE+KINETIS_USB_FRMNUMH_OFFSET) +#define KINETIS_USB0_TOKEN (KINETIS_USB0_BASE+KINETIS_USB_TOKEN_OFFSET) +#define KINETIS_USB0_SOFTHLD (KINETIS_USB0_BASE+KINETIS_USB_SOFTHLD_OFFSET) +#define KINETIS_USB0_BDTPAGE2 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE2_OFFSET) +#define KINETIS_USB0_BDTPAGE3 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE3_OFFSET) + +#define KINETIS_USB0_ENDPT(n) (KINETIS_USB0_BASE+KINETIS_USB_ENDPT_OFFSET(n)) +#define KINETIS_USB0_ENDPT0 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT0_OFFSET) +#define KINETIS_USB0_ENDPT1 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT1_OFFSET) +#define KINETIS_USB0_ENDPT2 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT2_OFFSET) +#define KINETIS_USB0_ENDPT3 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT3_OFFSET) +#define KINETIS_USB0_ENDPT4 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT4_OFFSET) +#define KINETIS_USB0_ENDPT5 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT5_OFFSET) +#define KINETIS_USB0_ENDPT6 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT6_OFFSET) +#define KINETIS_USB0_ENDPT7 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT7_OFFSET) +#define KINETIS_USB0_ENDPT8 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT8_OFFSET) +#define KINETIS_USB0_ENDPT9 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT9_OFFSET) +#define KINETIS_USB0_ENDPT10 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT10_OFFSET) +#define KINETIS_USB0_ENDPT11 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT11_OFFSET) +#define KINETIS_USB0_ENDPT12 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT12_OFFSET) +#define KINETIS_USB0_ENDPT13 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT13_OFFSET) +#define KINETIS_USB0_ENDPT14 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT14_OFFSET) +#define KINETIS_USB0_ENDPT15 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT15_OFFSET) + +#define KINETIS_USB0_USBCTRL (KINETIS_USB0_BASE+KINETIS_USB_USBCTRL_OFFSET) +#define KINETIS_USB0_OBSERVE (KINETIS_USB0_BASE+KINETIS_USB_OBSERVE_OFFSET) +#define KINETIS_USB0_CONTROL (KINETIS_USB0_BASE+KINETIS_USB_CONTROL_OFFSET) +#define KINETIS_USB0_USBTRC0 (KINETIS_USB0_BASE+KINETIS_USB_USBTRC0_OFFSET) + +/* Register Bit Definitions *****************************************************************/ + +/* Peripheral ID Register */ +#define KINETIS_USB_PERID_ +/* Peripheral ID Complement Register */ +#define KINETIS_USB_IDCOMP_ +/* Peripheral Revision Register */ +#define KINETIS_USB_REV_ +/* Peripheral Additional Info Register */ +#define KINETIS_USB_ADDINFO_ +/* OTG Interrupt Status Register */ +#define KINETIS_USB_OTGISTAT_ +/* OTG Interrupt Control Register */ +#define KINETIS_USB_OTGICR_ +/* OTG Status Register */ +#define KINETIS_USB_OTGSTAT_ +/* OTG Control Register */ +#define KINETIS_USB_OTGCTL_ +/* Interrupt Status Register */ +#define KINETIS_USB_ISTAT_ +/* Interrupt Enable Register */ +#define KINETIS_USB_INTEN_ +/* Error Interrupt Status Register */ +#define KINETIS_USB_ERRSTAT_ +/* Error Interrupt Enable Register */ +#define KINETIS_USB_ERREN_ +/* Status Register */ +#define KINETIS_USB_STAT_ +/* Control Register */ +#define KINETIS_USB_CTL_ +/* Address Register */ +#define KINETIS_USB_ADDR_ +/* BDT Page Register 1 */ +#define KINETIS_USB_BDTPAGE1_ +/* Frame Number Register Low */ +#define KINETIS_USB_FRMNUML_ +/* Frame Number Register High */ +#define KINETIS_USB_FRMNUMH_ +/* Token Register */ +#define KINETIS_USB_TOKEN_ +/* SOF Threshold Register */ +#define KINETIS_USB_SOFTHLD_ +/* BDT Page Register 2 */ +#define KINETIS_USB_BDTPAGE2_ +/* BDT Page Register 3 */ +#define KINETIS_USB_BDTPAGE3_ + +/* Endpoint n Control Register */ +#define KINETIS_USB_ENDPT_ + +/* USB Control Register */ +#define KINETIS_USB_USBCTRL_ +/* USB OTG Observe Register */ +#define KINETIS_USB_OBSERVE_ +/* USB OTG Control Register */ +#define KINETIS_USB_CONTROL_ +/* USB Transceiver Control Register 0 */ +#define KINETIS_USB_USBTRC0_ + + (1 << nn) /* Bit nn: +_SHIFT (nn) /* Bits nn-nn: +_MASK (nn << nn) + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_USBOTG_H */ -- GitLab