diff --git a/.gitignore b/.gitignore
index 3ec700458d0a455ed748bb4a6a498a844ae197b8..409232b7376b9c452400727cdac69f42ffdc2c69 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,30 +1,33 @@
-.depend
-Make.dep
-*.o
-*.a
-*.d
-*.i
-*~
-.swp
-.*.swp
-core
-.gdbinit
-cscope.out
-/.config
-/.config.old
-/.version
-/Make.defs
-/setenv.sh
-/setenv.bat
-/nuttx
-/nuttx.*
-/nuttx-*
-/_SAVED_APPS_config
-/*.map
-/*.elf
-/*.srec
-/*.bin
-/*.ihx
-/*.hex
-/pcode
-/tags
+.depend
+Make.dep
+*.o
+*.a
+*.d
+*.i
+*~
+.swp
+.*.swp
+core
+.gdbinit
+cscope.out
+/.config
+/.config.old
+/.version
+/Make.defs
+/setenv.sh
+/setenv.bat
+/nuttx
+/nuttx.*
+/nuttx-*
+/_SAVED_APPS_config
+/*.map
+/*.elf
+/*.srec
+/*.bin
+/*.ihx
+/*.hex
+/pcode
+/tags
+/.settings/
+/.cproject
+/.project
diff --git a/COPYING b/COPYING
index 1c82d0ca2023919592e284a3d3a57f5e71f3a4f8..a8113ab027c91b871a68a2632d5f69200e4ca81b 100644
--- a/COPYING
+++ b/COPYING
@@ -93,7 +93,7 @@ has a similar BSD style license:
IGMP
^^^^
-IGMP support, if enabled in uIP, adds additional logic by Steve Reynolds:
+IGMP support, if enabled, adds additional logic by Steve Reynolds:
Copyright (c) 2002 CITEL Technologies Ltd.
All rights reserved.
diff --git a/ChangeLog b/ChangeLog
index dab311760b5513dd0fc682e9f422869f0114ae10..226425ca8fc47c0ea564a2b4feba890d483c1ace 100755
--- a/ChangeLog
+++ b/ChangeLog
@@ -11586,7 +11586,7 @@
* configs/stm32l476vg-disco: Add support for the STM32L476VG Discovery
board. From Dave (2016-03-25).
-7.16 2016-xx-xx Gregory Nutt
+7.16 2016-06-01 Gregory Nutt
* PM: Add activity domain to all PM interfaces and driver callbacks. If
CONFIG_PM_NDOMAINS == 1, then the legacy behavior is preserved. If
@@ -11615,7 +11615,7 @@
* STM3220G-EVAL: Add support for both the IAR and uVision GCC IDEs
From Kha Vo (2016-04-08).
* STM32F429I Discovery: Add support for the uVision GCC IDE. From
- * Kha Vo (2016-04-08).
+ Kha Vo (2016-04-08).
* libc/signal and include/signal.h: Rename sigset() to signal().
sigset() is the System V function; signal() is the obsoleted POSIX
name. These seem to be equivalent. Neither are relevant in modern
@@ -11640,7 +11640,7 @@
is interpreted as a packed dual frame exchange. Sebastien Lorquet
(2016-04-13).
* net/sockets/listen.c and accept.c and include/nuttx/net: Separate
- out psock_listen() and psock_accepti() for internal OS usage
+ out psock_listen() and psock_accept() for internal OS usage
(2016-04-14).
* fs/inode/, fs/vfs/, and sched/task/: File and socket descriptors are
no longer allocated for kernel threads. They must use SYSLOG for
@@ -11753,7 +11753,7 @@
* arch/srm/src/stm32l4: Add CAN support for STM32L4. From Sebastien
Lorquet (2016-05-19).
* arch/arm/src/samv7: Adds a JTAG config and ERASE config to Kconfig to
- set the CCFG_SYSIO SYSIO Pins. From Davide Sidrane (2016-05-19).
+ set the CCFG_SYSIO SYSIO Pins. From David Sidrane (2016-05-19).
* arch/sim/src: Enhance networking support for the simulation under Linux.
Includes updated support for Linux TUN/TAP, and the addition of support
for Linux bridge devices. From Steve (2016-05-20).
@@ -11767,7 +11767,7 @@
configurations (2016-05-22).
* include/nuttx/crypto/aes.h: Modifications to the crypto API needed
for LPC43xx. From Alexander Vasiljev (2016-05-23).
- * arch/arm/src/lpc32xx: Add AES support. From Alexander Vasiljev
+ * arch/arm/src/lpc43xx: Add AES support. From Alexander Vasiljev
(2016-05-24).
* configs/*/src/tiva_timer.c: Tiva boards: Fix a naming collision,
rename board-specific function from tiva_timer_initialize() to
@@ -11813,3 +11813,361 @@
* fs/: Add logic to detach a file structure from a file descriptor.
This is for use only within the OS. It permits an open file or driver
to be used across multiple threads (2016-05-26).
+ * arch/arm/src/stm32l4: Get I2C working for STM32L4. From Dave
+ (ziggurat29) (2016-05-25).
+ * fs/ and include/nuttx/fs: Add logic to detach a file structure from a
+ file descriptor. This is for use only within the OS. It permits an
+ open file or driver to be used across multiple threads. (2016-05-26).
+ * drivers/analog/adc.c, include/nuttx/analog/adc.h, and all ADC lower
+ half drivers: No longer uses global adc_receive() call. Added a new
+ bind() method to the ADC interface. Now the ADC upper half driver
+ will register its receipt-of-data callback. This change allows the
+ ADC lower half driver to be used with a differ ADC upper half
+ (2016-05-26).
+ * drivers/analog/ads1255.c: Must not do SPI access from interrupt
+ handler. Use the worker thread instead. Must also lock the SPI bus
+ before using it. (2015-05-26).
+ * drivers/: Several SPI-based drivers modified. All drivers that use
+ SPI must call SPI_LOCK and SPI_UNLOCK. This is not optional
+ (2016-05-26).
+ * drivers/sensors: Fix a bug in crc computation for ms583730.
+ Implement POSIX read (2016-05-27).
+ * arch/arm/src/samv7: This is a fix to a problem in the handling of the
+ oneshot timer. Due to a wrong assumption concerning the behavior
+ directly after the start of the timer/counter the function
+ sam_oneshot_cancel(…) calculates the wrong remaining time. The code
+ assumes that the counter register is zero directly after the start of
+ the timer, but this is not true. To start the time/counter a software
+ trigger is invoked, this trigger starts the timer/count and sets the
+ counter register to zero, but the reset of the counter register is not
+ performed instantly. According to the datasheet: "The counter can be
+ reset by a trigger. In this case, the counter value passes to zero on
+ the next valid edge of the selected clock." Thus the counter is set to
+ zero between 0 and USEC_PER_TICK microseconds after the clock was
+ started.
+ In my fix I use the freerun count value to determine if at least one
+ tick passed since the start of the timer and thus if the value of the
+ oneshot counter is correct. I also tried to use the function
+ up_timer_gettime(…) to achieve this but, at least if compiled with no
+ optimization the problem vanishes without using the value of the
+ function, the function call takes too long.
+ Another problem treated in the fix is that if the oneshot timer/counter
+ is canceled, we only know the remaining time with a precision of
+ USEC_PER_TICK microseconds. This means the calculated remaining time
+ is between 0 and USEC_PER_TICK microseconds too long. To fix this I
+ subtract one tick if the calculated remaining time is greater than one
+ tick and otherwise set the remaining time to zero. By doing so the
+ measured times are much more precise as without it. From Stefan Kolb
+ (2016-05-27).
+ * arch/arm/src/sama5: Stefan Kolb's change to the SAMV7 Oneshot Timer
+ should also be applied to the SAMA5 oneshot time since the drivers are
+ identical (2016-05-27).
+ * arch/arm/src/stm32l4: Add support for SPI 4 and 5 on stm32f411 chips.
+ From Konstantin Berezenko (2016-05-27).
+ * arch/arm/src/sam34: Stefan Kolb's change to the SAMV7 Oneshot Timer
+ should also be applied to the SAM3/4 oneshot time since the drivers
+ are identical (2016-05-29).
+ * arch/arm/src/stm32: Allow to not use all channel in a lower part of
+ PWM. From Pierre-noel Bouteville (2016-05-30).
+ * libc/math: Add a NAN test on 'x' in asin function of lib_asin.c.
+ Suggested by Pierre-noel Bouteville (2016-05-31).
+ * arch/arm/src/stm32: Fix logic in F4 RTCC driver that prevent ALARM
+ interrupt. From Neil Hancock (2016-05-31).
+ * arch/arm/src/stm32: Fix STM32 ValueLine ADC IRQ number selection.
+ From David Sidrane (2016-05-31).
+ * arch/arm/src/samv7: Fix missing unlock of device in MCAN
+ mcan_txempty(). From Frank Benkert (2016-06-01).
+
+7.17 2016-xx-xx Gregory Nutt
+
+ * drivers/mtd/flash_eraseall.c: Removed. This is no longer used
+ in the OS and is simply a wrapper around the MDIOC_BULKERASE
+ IOCTL command. It used to be called (only) from
+ apps/system/flash_eraseall, but that has been removed because it
+ violated the OS/application interface -- by calling flash_eraseall().
+ The old code can be found in the Obsoleted' repository (and a revised
+ version can be found at apps/fsutils/flash_eraseall) (2016-06-03).
+ * arch/arm/src/stm32: STM32 Timer Driver: Change calculation of per-
+ timer pre-scaler value. Add support for all timers (2016-6-03)
+ * drivers/lcd: Correct conditional compilation in ST7565 driver. From
+ Pierre-noel Bouteville (2016-6-03)
+ * arch/arm/src/stm32: Correct conditional compilation in STM32 timer
+ capture logic. From Pierre-noel Bouteville (2016-6-03)
+ * arch/arm/src/efm32: Fix EFM32 FLASH conditional compilation. From
+ Pierre-noel Bouteville (2016-6-03)
+ * arch/arm/src/lpc43xx: Fix errors in GPIO interrupt logic. From v01d
+ (phreakuencies) (2016-06-04)
+ * arch/arm/src/kl and lpc11xx: rename xyz_lowputc to up_putc. Remove
+ all references to up_lowputc, everywhere (2016-06-04).
+ * configs/stm32f103-minimum: Add minnsh configuration. From Alan
+ Carvalho de Assis (2016-06-04).
+ * arch/arm/src/stm32: Add the up_getc() function to STM32 in order to
+ support the minnsh configuration. From Alan Carvalho de Assis
+ (2016-06-04).
+ * include/sys/boardctl.h: Needs to be usable with C++ files (2016-06-05).
+ * tools/tesbuild.sh will now build NxWM configurations (2016-06-05).
+ * arch/arm/src/stm32: In PWM driver, just update duty if frequency is
+ not changed and PSM started. This removeis glitch or blinking when
+ only duty is frequently changed. From Pierre-noel Bouteville (2016-06-05).
+ * arch/arm/src/kinetis: Add a USB device controller driver. Derived from
+ the pic32mx usb driver, which uses the same usb controller. From kfazz
+ (2016-06).
+ * configs/teensy-3.x: Add USB support and a usbnsh configuration. From
+ kfazz (2016-06).
+ * arch/arm/src/stm32: Add support for the STM32F105R. From Konstantin
+ Berezenko (2016-06-06).
+ * include/signal.h: Change type of SIG_ERR, SIG_IGN, ... to
+ _sa_handler_t. They type void does not work with the IAR toolchain.
+ From Aleksandr Vyhovanec (2016-06-07).
+ * arch/arm/src/stm32f7 and include/stm32f7: Added STM32FF76xxx and
+ STM32FF7xx families. From David Sidrane (2016-06-08).
+ * Refactoring configs/nucleo-144 sub-directories to support additional
+ nucleo-144 board. Add support for the Nucleo-F767ZI board. From David
+ Sidrane (2016-06-08).
+ * arch/arm/src/kinetis: Add a USB device controller driver for kinetis.
+ Derived from pic32mx usb driver, which uses the same usb controller.
+ From kfazz (2016-06-06).
+ * configs/teensy-3.x: Add USB device support and usbnsh configuration.
+ From kfazz (2016-06-06.
+ * arch/arm/src/stm32: Add STM32F105R support. From Konstantin Berezenko
+ (2016-06-06).
+ * include/signal.h: Change type of SIG_IGN and related defines to
+ _sa_handler_t. From Aleksandr Vyhovanec (2016-06-07).
+ * configs/nucleo-144: Refactored configs/nucleo-144 sub-directories to
+ support additional nucleo-144 board. Add support for the Nucleo-F767ZI
+ board. From David Sidrane (2016-06-07).
+ * arch/arm/src/stm32f7: Add support for STM32FF76xxx and STM32FF7xx
+ families. From David Sidrane (2016-06-08).
+ * include/assert.h: Check if NDEBUG is defined. From Paul Alexander
+ Patience (2016-06-08).
+ * arch/arm/src/stm32: Fix STM32 DMA code and configuration for STM32F37X
+ chips. From Marten Svanfeldt (2016-06-08).
+ * drivers/mtd: Add a driver of IS25xP SPI flash devices. From Marten
+ Svanfeldt (2016-06-09).
+ * arch/arm/src/Kconfig and configs/teensy-3.x: Teensy clock fixes. The
+ High Gain bit in MCG_C1 was preventing teensy from booting except
+ after a programming session. The second change doesn't appear to
+ change any functionality, but complies with restrictions in the k20
+ family reference manual on FEI -> FBE clock transiions. From kfazz
+ (2016-06-09).
+ * configs/*/include/board.h: Fix timer input clock definitions. From
+ David Sidrane (2016-06-09).
+ * Networking: In both IPv6 and IPv4 incoming logic: (1) Should check
+ if the packet size is large enough before trying to access the packet
+ length in the IP header. (2) In the comparison between the IP length
+ and the full packet length, need to subtract the size of the link
+ layer header before making the comparison or we will get false
+ positives (i.e., the packet is really too small) (2016-06-09)
+ * drivers/mtd: Added driver of IS25xP SPI flash devices. Based on
+ sst25xx driver. From Marten Svanfeldt (2016-06-09).
+ * arch/arm/src/kinetis: Teensy clock fixes. The High Gain bit in
+ MCG_C1 was preventing teensy from booting except after a programming
+ session. The second change doesn't appear to change any functionality,
+ but complies with restrictions in the k20 family reference manual on
+ FEI -> FBE clock transiions. From kfazz (2016-06-09).
+ * arch/arm/src/stm32: Fix timer input clock definitions. From David
+ Sidrane (2016-06-09).
+ * configs/: All configurations that have both CONFIG_NSH_LIBRARY=y and
+ CONFIG_NET=y must now also have CONFIG_NSH_NETINIT=y (2016-06-09).
+ * arch/arm/src/kinetis: Kinetis pwm support, based on kl_pwm driver.
+ From kfazz (2016-06-09).
+ * net/: In both IPv6 and IPv4 incoming logic: (1) Should check if the
+ packet size is large enough before trying to access the packet length
+ in the IP header. (2) In the comparison between the IP length and the
+ full packet length, need to subtract the size of the link layer header
+ before making the comparison or we will get false positives (i.e., the
+ packet is really too small) (2016-06-09).
+ * arch/srm/src/stm32: Fix compilation errors in debug mode of
+ stm32_pwm.c. From Konstantin Berezenko (2016-06-09).
+ * arch/arm/src/kinetis: Support up to 8 channels per timer. From kfazz
+ (2016-06-09).
+ * lib/: crc16: fix error. From Paul Alexander Patience (2016-06-10).
+ * lib/: Add crc64 support. From Paul Alexander Patience (2016-06-10).
+ * arch/arm/src/kinetis: Added kl_dumpgpio functionality as
+ kinetis_pindump. From kfazz (2016-06-10).
+ * arch/arm/src/sam34: Fix some errors in AFEC header file. From
+ OrbitalFox (2016-06-10).
+ * arch/arm/include/stm32: Correct the can2 rx irq number for stm32f10xx
+ chips. From Konstantin Berezenko (2016-06-10).
+ * drivers/include/input: Button upper half driver: Add definitions
+ needed for compilation with the poll() interface is not disabled
+ (2016-06-11).
+ * Kconfig/, include/debug.h, and many other files: (1) Debug features
+ are now enabled separately from debug output. CONFIG_DEBUG is gone.
+ It is replaced with CONFIG_DEBUG_FEATURES. (2) The macros dbg() and
+ vdbg() have renamed as err() and info(), respectively. This also
+ applies to all of the variants as well, lldbg(), llvdbg(), XXdbg(),
+ XXvdbg(), XXlldbg(), and XXllvdbg(). (3) Add a new debug level,
+ warn() (and all variants vwarn(), llwarn(), etc.). (4) Debug
+ assertions can now be enabled separately from debug output. (5) You
+ can now enable subsystem/device driver debug output at different
+ output levels. For example, CONFIG_DEBUG_FS no longer enables file
+ system debug output. It enables general file system debug logic and
+ enables selection of CONFIG_DEBUG_FS_ERROR, CONFIG_DEBUG_FS_WARN,
+ and CONFIG_DEBUG_FS_INFO (2016-06-12).
+ * strtoul() and strtoull(): Fix errno settings required by function
+ definition. Resolved Bitbucket Issue #1. From Sebastien Lorquet
+ (2016-06-13)
+ * arch/arm/src/stm32f7: Add SPI driver. DMA not yet supported. From
+ David Sidrane (2016-06-14).
+ * configs/nucleo-144: Add test for STM32 F7 SPI. From David Sidrane
+ (2016-06-14).
+ * alert(): New debug macro: alert(). This is high priority,
+ unconditional output and is used to simplify and stanardize crash
+ error reporting(2016-06-14).
+ * arch/arm/src/tiva: Bug Fix in tiva_serial.c - UART5, UART6 and UART7
+ were not being configured as TTYS0 for printing over serial console.
+ From Shirshak Sengupta (2016-06-14).
+ * SAMV7: SPI: SPI-Freq. 40MHz; VARSELECT; hw-features
+ This change adds the following improvements:
+ - Increase the allowed SPI-Frequency from 20 to 40 MHz.
+ - Correct and rename the "VARSELECT" option
+ This option was included in the code as "CONFIG_SPI_VARSELECT" but
+ nowhere defined in a Kconfig file. The change renames it to
+ "CONFIG_SAMV7_SPI_VARSELECT" and corrects the implementation
+ according the datasheet of Atmel. In short, this option switches
+ the processor from "fixed peripheral selection" (single device) to
+ "variable peripheral selection" (multiple devices on the bus).
+ - Add a new Function to the interface to control the timing and delays
+ of the chip according the ChipSelect lines. This function can
+ control the delay between the assertion of the ChipSelect and the
+ first bit, between the last bit and the de-assertion of the
+ ChipSelect and between two ChipSelects. This is needed to tune the
+ transfer according the specification of the connected devices.
+ - Add three "hw-features" for the SAMV7, which controls the behavior
+ of the ChipSelect:
+ - force CS inactive after transfer: this forces a (short)
+ de-assertion of the CS after a transfer, even if more data is
+ available in time
+ - force CS active after transfer: this forces the CS to stay active
+ after a transfer, even if the chip runs out of data.
+ Btw.: this is a prerequisit to make the LASTXFER bit working at all.
+ - escape LASTXFER: this suppresses the LASTXFER bit at the end of the
+ next transfer. The "escape"-Flag is reset automatically.
+ From Frank Benkert (2016-06-14)
+ * Many CONFIG_DEBUG_* options did not have matching macros defined in
+ include/debug.h. Rather, there were various definitions scattered
+ throughout the sourse tree. These were collected together and
+ centralized with single macro definitions in include/debug.h
+ (2016-06-15)
+ * STM32F7: Add SPI, I2C, and ADC drivers. From Lok Tep (2016-06-15).
+ * err(), warn(), info(), and alert() renamed to include leading '_'.
+ This was done to avoid some naming collisions (2-06-16
+ * STM32: Move backup domain reset to to earlier in the initialization
+ sequence (stm32_rcc.c() in order to avoid disabling LSE during RTC
+ initialiation. From Alan Carvalho de Assis (2016-06-16).
+ * SYSLOG: syslog() will now automatically redirect output to lowsyslog()
+ if called from an interrupt handler (2016-06-16).
+ * STM32: When configuring a GPIO via stm32_configgpio() the function
+ will first set the mode to output and then set the initial state of
+ the gpio later on. If you have an application with an externaly
+ pulled-up pin, this would lead to a glitch on the line that may be
+ dangerous in some applications (e.G. Reset Line for other chips,
+ etc). This changes sets the output state before configuring the pin
+ as an output. From Pascal Speck (2016-06-17).
+ * STM32 F7: Apply Pascal Speck's GPIO STM32 change to STM32 L4
+ (2016-06-17).
+ * STM32 L4: Apply Pascal Speck's GPIO STM32 change to STM32 L4.
+ From Sebastien Lorquet (2016-06-17).
+ * Review all uses of *err(). These macro family should indicate only
+ error conditions. Convert *err() to either *info() or add ERROR:,
+ depending on if an error is reported (2016-06-17).
+ * STM32F7: Review, correct, and update I2C, SPI, and ADC drivers. From
+ David Sidrane (2016-06-17).
+ * LPC17 Ethernet: Needs to correctly ignore PHYID2 revision number
+ when comparing PHY IDs (2016-06-18).
+ * SYSLOG: Consolidate all SYSLOG logic in drivers/syslog. Add an
+ abstraction layer that supports: (1) redirection of SYSLOG outpout.
+ This is usually so that you can boot with one SYSLOG output but
+ transition to another SYSLOG output when the OS has initialialized,
+ (2) adds common serialization of interrupt output as a configuration
+ option. Without this configuration setting, interrupt level output
+ will be asynchronous. And (3) vsyslog is now a system call and is
+ usable with other-than-FLAT builds (2016-06-19).
+ * TCP Networking: While working with version 7.10 I discovered a
+ problem in TCP stack that could be observed on high network load.
+ Generally speaking, the problem is that RST flag is set in
+ unnecessary case, in which between loss of some TCP packet and its
+ proper retransmission, another packets had been successfully sent.
+ The scenario is as follows: NuttX did not receive ACK for some
+ sent packet, so it has been probably lost somewhere. But before
+ its retransmission starts, NuttX is correctly issuing next TCP
+ packets, with sequence numbers increasing properly. When the
+ retransmission of previously lost packet finally succeeds, tcp_input
+ receives the accumulated ACK value, which acknowledges also the
+ packets sent in the meantime (i.e. between unsuccessful sending of
+ lost packet and its proper retransmission). However, variable unackseq
+ is still set to conn->isn + conn->sent, which is truth only if no
+ further packets transmission occurred in the meantime. Because of
+ incorrect (in such specific case) unackseq value, few lines further
+ condition if (ackseq <= unackseq)is not met, and, as a result, we
+ are going to reset label. From Jakub Łągwa (2016-06-20).
+ * SYSLOG: Remove lowsyslog(), vlowsyslog(), and associated macros
+ *llinfo(), *llwarn(), and llerr(). In the redesigned syslog() logic,
+ these serve no purpose (2016-06-20).
+ * Make system: Need to build the drivers/ directory even it file
+ descriptors are not supported. There are things in the drivers/
+ directory that are still needed (like SYSLOG logic) (2016-06-20).
+ * assert.h: Define static assert for C++ usage. From Paul Alexander
+ Patience (2016-06-21).
+ * arch/arm/src/stm32l4: Add ioctls to set/get bit timing in stm32l4.
+ Add ioctl hooks to allow future management of can id filters. From
+ Sebastien Lorquet (2016-06-21).
+ * drivers/can.c: Add support for poll. From Paul Alexander Patience
+ (2016-06-21).
+ * drivers/syslog: Extend SYSLOG logic so that we can send SYSLOG output
+ to a file. Not verified on initial commit (2016-06-21).
+ * arch/arm/src/stm32l4: Add some CAN mode IOCTL calls. These will be
+ useful for device autotest when the application boots. They are
+ redundant with the CONFIG_CAN_LOOPBACK option, which can now just be
+ interpreted as a default setting. From Sebastien Lorquet (2016-06-22).
+ * drivers/syslog: syslog_dev_flush() needs to check if the inode is a
+ mountpoint before calling the flush() method. Noted by David Sidrane
+ (2016-06-22).
+ * arch/arm/src/stm32f7: Adds SDMMC1 for stm32F7 74-75. From Lok Tep
+ (2016-06-22).
+ * drivers/syslog: SYSLOG character device channel will now expand LF to
+ CR-LF. Controllable with a configuration option (2016-06-22).
+ * arch/arm/src/stm32l4: Implementation of loopback IOCTLs. From
+ Sebastien Lorquet (2016-06-22).
+ * Documentation: Add SYSLOG documentation to the porting guide
+ (2016-06-22).
+ * configs/stm32f746g-disco: Removed knsh configuration it failed to
+ refresh (via tools/refresh.sh). I assume that it is a hand-edited
+ configuration and, hence, must be removed from the repository
+ (2016-06-23).
+ * arch/arm/arc/sam34: DAC bugfix: DACC_WPMR_WPKEY_MASK -> DACC_WPMR_WPKEY.
+ Timer bugfix: Fix ops check in TCIOC_STOP. From Wolfgang Reissnegge
+ (2016-06-23).
+ * arch/arm/src/stm32: Port STM32L4 CAN IOCTLs to STM32. From Sebastien
+ Lorquet (2016-06-24).
+ * configs/Konfig:Add configuration logic to include a Kconfig file in
+ each custom configuration. Includes adding a dummy custom board
+ configuration directory. A consequence of this that each custom board
+ directory will now need to contain a Kconfig file. NOTE also that
+ the new board directory does not take effect in the configuration
+ menus until the NEXT time you run 'make menuconfig' (2016-06-24).
+ * drivers/ioexpander: Add support for a very simple GPIO driver. It
+ supports only pre-conrigured input and output pins and only basic
+ input and output operations (2016-06-24).
+ * arch/arm/src/lpc43xx: Correct auto-negotiation mode in the LPC43xx
+ Ethernet. From Alexander Vasiljev (2016-06-24)
+ * arch/arm/src/samv7: TWIHS Driver improved and GPIO-Driver fixed for
+ Open-Drain Pins
+ - sam_gpioread: Now the actual line level from the pin is read back.
+ This is extremely important for Open-Drain Pins, which can be used
+ bidirectionally
+ - Re-Implemented twi_reset-function and enhanced it so it can be
+ called from inside the driver (see next point)
+ - Glitch-Filter: Added a configuration option to enable the twi-built-
+ in glitch filter
+ - Added a "Single Master Mode": In EMC Testing the TWI-Bus got stuck
+ because the TWI-Master detected a Multi-Master access (but there is
+ no second master). With the option "Single Master" we detect these
+ events and automatically trigger a twi_reset. We also do an
+ automatic recovery if a slave got stuck (SDA stays low).
+ With the above changes I²C-Bus reliability in harsh environments (eg.
+ EMC) is greatly improved. The small change in the GPIO-Driver was
+ necessary because otherwise you cannot read back the correct line
+ status of Open-Drain Outputs and this is needed by the twi_reset
+ function. From Michael Spahlinger (2016-06-24)
diff --git a/Directories.mk b/Directories.mk
index 6eeedc79e8a484095ca15f31ccaf20cb9212bad9..2e42a8a435f25de41b1646e5bcea5a60787b7a86 100644
--- a/Directories.mk
+++ b/Directories.mk
@@ -59,7 +59,10 @@ endif
#
# FSDIRS depend on file descriptor support; NONFSDIRS do not (except for parts
# of FSDIRS). We will exclude FSDIRS from the build if file descriptor
-# support is disabled
+# support is disabled. NOTE that drivers, in general, depends on file
+# descriptor support but is always built because there are other components
+# in the drivers directory that are needed even if file descriptors are not
+# supported.
# CONTEXTDIRS include directories that have special, one-time pre-build
# requirements. Normally this includes things like auto-generation of
# configuration specific files or creation of configurable symbolic links
@@ -69,8 +72,8 @@ endif
# be cleaned to prevent garbage from collecting in them when changing
# configurations.
-NONFSDIRS = sched configs $(ARCH_SRC) $(NUTTX_ADDONS)
-FSDIRS = fs drivers binfmt
+NONFSDIRS = sched drivers configs $(ARCH_SRC) $(NUTTX_ADDONS)
+FSDIRS = fs binfmt
CONTEXTDIRS = $(APPDIR)
USERDIRS =
OTHERDIRS = lib
diff --git a/Documentation/NuttX.html b/Documentation/NuttX.html
index 9910e4c275d0cb67c8095802b5a73737d16f1286..83c42c61cfdf3d786affc954a7b1fd3bd0ae9b7c 100644
--- a/Documentation/NuttX.html
+++ b/Documentation/NuttX.html
@@ -8,7 +8,7 @@
NuttX RTOS
- Last Updated: April 12, 2016
+ Last Updated: June 1, 2016
|
@@ -1340,11 +1340,11 @@
Released Versions
In addition to the ever-changing GIT repository, there are frozen released versions of NuttX available.
- The current release is NuttX 7.15.
- NuttX 7.15 is the 115th release of NuttX.
- It was released on March 27, 2016, and is available for download from the
+ The current release is NuttX 7.16.
+ NuttX 7.16 is the 116th release of NuttX.
+ It was released on June 1, 2016, and is available for download from the
Bitbucket.org website.
- Note that the release consists of two tarballs: nuttx-7.15.tar.gz
and apps-7.15.tar.gz
.
+ Note that the release consists of two tarballs: nuttx-7.16.tar.gz
and apps-7.16.tar.gz
.
Both may be needed (see the top-level nuttx/README.txt
file for build information).
@@ -1353,7 +1353,7 @@
- nuttx.
- Release notes for NuttX 7.15 are available here.
+ Release notes for NuttX 7.16 are available here.
Release notes for all released versions on NuttX are available in the Bitbucket GIT.
The ChangeLog for all releases of NuttX is available in the ChangeLog file that can viewed in the Bitbucket GIT.
The ChangeLog for the current release is at the bottom of that file.
@@ -1361,7 +1361,7 @@
apps.
Atmel AVR
@@ -2257,7 +2257,7 @@
NXP/Freescale i.MX6.
- A port is underway for the following i.MX6 board
+ The basic port has been completed for the following i.MX6 board
-
@@ -2268,9 +2268,13 @@
STATUS:
- The basic, minimal port is code complete and introduced in NuttX-7.15, but has not yet been tested.
- I am still waiting for the reciept of the Sabre board.
- Expect to see the verified Sabre-6Quad support (with SMP!) in NuttX-7.16.
+ The basic, minimal port is code complete and introduced in NuttX-7.15, but had not yet been tested at that time due to the inavailability of hardware.
+ This basic port was verified in the NuttX-7.16 release, however.
+ The port is still mininal and more device drivers are needed to make the port usable.
+
+
+ Basic support of NuttX running in SMP mode on the i.MX6Q was also accomplished in NuttX-7.16.
+ However, there are still known issues with SMP support on this platform as described in the README file for the board.
@@ -2907,13 +2911,26 @@ nsh>
|
STMicro STM32F103C4/8 (STM32 F1 Low- and Medium-Density Family).
- This port is for "STM32 Tiny" development board.
- This board is available from several vendors on the net, and may be sold under different names.
- It is based on a STM32 F103C8T6 MCU, and is bundled with a nRF24L01 wireless communication module.
+ There are two ports available for this family:
-
- STATUS:
+ -
+
+ One port is for "STM32 Tiny" development board.
+ This board is available from several vendors on the net, and may be sold under different names.
+ It is based on a STM32 F103C8T6 MCU, and is bundled with a nRF24L01 wireless communication module.
+
+
+ -
+
+ The other port is for a generic minimual STM32F103CBT6 "blue" board contributed by Alan Carvalho de Assis.
+
+
+
+
+ STATUS:
+
+
The basic STM32F103C8 port was released in NuttX version 6.28.
This work was contributed by Laurent Latil.
Refer to the NuttX board README file for further information.
@@ -3160,11 +3177,17 @@ nsh>
- STATUS:
- The peripherals of the STM32 F2 family are compatible with the STM32 F4 family.
- See discussion of the STM3240G-EVAL board below for further information.
- Refer also to the NuttX board README file for further information.
-
+
+ STATUS:
+ The peripherals of the STM32 F2 family are compatible with the STM32 F4 family.
+ See discussion of the STM3240G-EVAL board below for further information.
+ Refer also to the NuttX board README file for further information.
+
+
+ Support for both the IAR and uVision GCC IDEs added for the STM3220G-EVAL board in NuttX 7.16.
+ From Kha Vo.
+
+
|
@@ -3779,6 +3802,10 @@ nsh>
In Nutt-7.7, Marco Krahl included support for a framebuffer based driver using the LTDC and DMA2D.
Marcos's implementation included extensions to support more advance LTDC functions through an auxiliary interface.
+
+ Support for the uVision GCC IDE added for theSTM32F429I-Discovery board in NuttX 7.16.
+ From Kha Vo.
+
Refer to the STM32F429I-Discovery board README file for further information.
@@ -3853,6 +3880,15 @@ nsh>
UART, USART, Serial Console
GPIO, DMA, I2C, RNG, SPI
+
+ NuttX-7.16.
+ Additional drivers were contributed:
+
+
+ - QSPI with DMA and memory mapped support. From Dave (ziggurat29).
+ - CAN contributed by Sebastien Lorquet.
+ - I2C made functional by Dave (ziggurat29).
+
@@ -3968,6 +4004,13 @@ nsh>
The NXP WaveShare LPC4337-WS port is was contributed by Lok Tep and first released in NuttX-7.14.
+
+ NuttX-7.16
+ Support for the LPC4337JET100 chip was contribed by Alexander Vasiljev.
+ Alexander also contributed an LPC43xx AES driver available in NuttX-7.16.
+
+
+
@@ -4407,13 +4450,24 @@ Mem: 29232 5920 23312 23312
STMicro STM32 F745/F746.
- This port uses the STMicro STM32F746G-DISCO development board featuring the STM32F746NGH6 MCU. The STM32F746NGH6 is a 216MHz Cortex-M7 operation with 1024Kb Flash.
- Refer to the STMicro web site for further information about this board.
+ Two boards are supported for this MCU:
- STATUS:
- The basic port is complete and there are two, verified configurations available.
+ STM32F746G Discovery.
+ One port uses the STMicro STM32F746G-DISCO development board featuring the STM32F746NGH6 MCU. The STM32F746NGH6 is a 216MHz Cortex-M7 operation with 1024Kb Flash.
+ Refer to the STMicro web site for further information about this board.
+
+
+ A basic port for the Nucleo-144 board with the STM32F746ZG MCU was contribued in NuttX-7.16 by Kconstantin Berezenko.
+
+
+
+ STATUS:
+
+
+
+ The basic STM32F746G-DISCO port is complete and there are two, verified configurations available.
Both configurations use the NuttShell (NSH) and a serial console; one includes Ethernet support.
DMA supports is available.
The STM32 F7 peripherals are very similar to some members of the STM32 F4 and additional drivers can easily be ported the F7 as discussed in this Wiki page: Porting Drivers to the STM32 F7
diff --git a/Documentation/NuttXCCodingStandard.html b/Documentation/NuttXCCodingStandard.html
index d1e96795c773271a3b2339bc63940a3165799d10..e3b3103297aaba92d4d8266f20c81484c0bd19c8 100644
--- a/Documentation/NuttXCCodingStandard.html
+++ b/Documentation/NuttXCCodingStandard.html
@@ -162,10 +162,10 @@
Pre-processor Definitions
-
- Private Types
+ Private Types (definitions)
-
- Private Function Prototypes
+ Private Function Prototypes (declarations)
-
Private Data (definitions)
@@ -191,7 +191,7 @@
Pre-processor Definitions
-
- Public Types
+ Public Types (definitions)
-
Public Data (declarations)
@@ -212,12 +212,12 @@
Header File Idempotence.
- C header file must protect against multipleinclusion through the use of macros that "guard" against multiple definitions if the header file is included multiple times.
+ C header file must protect against multiple inclusion through the use of macros that "guard" against multiple definitions if the header file is included multiple times.
-
- Each header file must contain the following pre-processor commands near the beginning of the header file: Between the file header and the "Included Files" block comment.
+ Each header file must contain the following pre-processor conditional logic near the beginning of the header file: Between the file header and the "Included Files" block comment.
For example,
@@ -248,7 +248,7 @@
Deoxygen Information.
- NuttX does not use Deoxygen for documentation and no file should contain Doxygen tags.
+ NuttX does not use Deoxygen for documentation and no file should contain Doxygen tags or Doxygen style comments.
diff --git a/Documentation/NuttxPortingGuide.html b/Documentation/NuttxPortingGuide.html
index ff3990c9d9b49d10459a8c82f76ef533c1273d72..d36ca6f21049566911241ccbfc14b953f1a35161 100644
--- a/Documentation/NuttxPortingGuide.html
+++ b/Documentation/NuttxPortingGuide.html
@@ -12,7 +12,7 @@
NuttX RTOS Porting Guide
- Last Updated: May 12, 2016
+ Last Updated: June 22, 2016
|
@@ -208,11 +208,18 @@
6.3.8 USB Host-Side Drivers
6.3.9 USB Device-Side Drivers
- 6.4 Power Management
+ 6.4 SYSLOG
+ 6.5 Power Management
+
Appendix A: NuttX Configuration Settings
@@ -802,7 +809,7 @@
Definitions in the Make.defs
file probably depend on some of the
settings in the .config
file. For example, the CFLAGS
will most likely be
- different if CONFIG_DEBUG=y
.
+ different if CONFIG_DEBUG_FEATURES=y
.
The included tools/Config.mk
file contains additional definitions that may
@@ -4901,8 +4908,7 @@ int kbd_decode(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *sta
include/nuttx/net/netdev.h
.
All structures and APIs needed to work with Ethernet drivers are provided in this header file.
- The structure struct net_driver_s
defines the interface and is passed to uIP via
- netdev_register()
.
+ The structure struct net_driver_s
defines the interface and is passed to the network via netdev_register()
.
@@ -5547,9 +5553,507 @@ int kbd_decode(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *sta
-
+
+
+
+
+
+ The NuttX SYSLOG is an architecture for getting debug and status
+ information from the system. The syslogging interfaces are defined in the
+ header file include/syslog.h
. The primary interface to SYSLOG sub-system
+ is the function syslog()
and, to a lesser extent, its companion vsyslog()
:
+
+
+Function Prototypes:
+
+#include <syslog.h>
+int syslog(int priority, FAR const IPTR char *format, ...);
+int vsyslog(int priority, FAR const IPTR char *src, va_list ap);
+
+Description:
+ syslog()
generates a log message. The priority argument is formed by ORing the facility and the level values (see include/syslog.h
). The remaining arguments are a format, as in printf()
and any arguments to the format.
+
+
+ The NuttX implementation does not support any special formatting characters beyond those supported by printf()
.
+
+
+ The function vsyslog()
performs the same task as syslog()
with the difference that it takes a set of arguments which have been obtained using the stdarg
variable argument list macros.
+
+
+
+
+ The additional setlogmask()
interface can use use to filter SYSLOG output:
+
+Function Prototype:
+
+#include <syslog.h>
+int setlogmask(int mask);
+
+Description:
+ The setlogmask()
function sets the logmask and returns the previous mask. If the mask argument is zerio, the current logmask is not modified.
+
+
+ The SYSLOG priorities are: LOG_EMERG
, LOG_ALERT
, LOG_CRIT
, LOG_ERR
, LOG_WARNING
, LOG_NOTICE
, LOG_INFO
, and LOG_DEBUG
. The bit corresponding to a priority p
is LOG_MASK(p)
; LOG_UPTO(p)
provides the mask of all priorities in the above list up to and including p
.
+
+
+ Per OpenGroup.org "If the maskpri argument is 0, the current log mask is not modified." In this implementation, the value zero is permitted in order to disable all SYSLOG levels.
+
+
+ REVISIT: Per POSIX the SYSLOG mask should be a per-process value but in NuttX, the scope of the mask is dependent on the nature of the build:
+
+
+
+ -
+
+ Flat Build: There is one, global SYSLOG mask that controls all output.
+
+ -
+
+ Protected Build: There are two SYSLOG masks. One within the kernel that controls only kernel output. And one in user-space that controls only user SYSLOG output.
+
+ -
+
+ Kernel Build: The kernel build is compliant with the POSIX requirement: There will be one mask for for each user process, controlling the SYSLOG output only form that process. There will be a separate mask accessable only in the kernel code to control kernel SYSLOG output.
+
+
+ The above are all standard interfaces as defined at OpenGroup.org. Those interfaces are available for use by application software. The remaining interfaces discussed in this section are non-standard, OS-internal interfaces.
+
+
+
+
+ In NuttX, syslog output is really synonymous to debug output and, herefore, the debugging interface macros defined in the header file
+ include/debug.h
are also syslogging interfaces. Those macros are simply wrappers around syslog()
. The debugging interfaces differ from the syslog interfaces in that:
+
+
+
+ -
+
+ They do not take a priority parameter; the priority is inherent in the
+ debug macro name.
+
+ -
+
+ They decorate the output stream with information such as the file name
+
+ -
+
+ They can each be disabled via configuration options.
+
+
+
+ Each debug macro has a base name that represents the priority and a prefix that represents the sub-system. Each macro is individually initialized by both priority and sub-system. For example, uerr()
is the macro used for error level messages from the USB subsystem and is enabled with CONFIG_DEBUG_USB_ERROR
.
+
+
+ The base debug macro names, their priority, and configuration variable are summarized below:
+
+
+
+ -
+
+ info()
. The info()
macro is the lowest priority (LOG_INFO
) and is intended to provide general information about the flow of program execution so that you can get an overview of the behavior of the program. info()
is often very chatty and voluminous and usually more information than you may want to see. The info()
macro is controlled via CONFIG_DEBUG_subsystem_INFO
+
+ -
+
+ warn()
. The warn()
macro has medium priority (LOG_WARN
) and is controlled by CONFIG_DEBUG_subsystem_WARN
. The warn()
is intended to
+ note exceptional or unexpected conditions that meigh be potential
+ errors or, perhaps, minor errors that easily recovered.
+
+ -
+
+ err()
. This is a high priority debug macro (LOG_ERROR
) and controlled by CONFIG_DEBUG_subsystem_ERROR
. The err()
is reserved to indicate important error conditions.
+
+ -
+
+ alert()
. The highest priority debug macro (LOG_EMERG
) and is controlled by CONFIG_DEBUG_ALERT
. The alert()
macro is reserved for use solely by assertion and crash handling logic. It also differs from the other macros in that it cannot be enabled or disabled per subsystem.
+
+
+
+
+
+
+ In the NuttX SYSLOG implementation, the underlying device logic the supports the SYSLOG output is referred to as a SYSLOG channel. Each SYSLOG channel is represented by an interface defined in include/nuttx/syslog/syslog.h
:
+
+
+ /* This structure provides the interface to a SYSLOG device */
+
+ typedef CODE int (*syslog_putc_t)(int ch);
+ typedef CODE int (*syslog_flush_t)(void);
+
+ struct syslog_channel_s
+ {
+ /* I/O redirection methods */
+
+ syslog_putc_t sc_putc; /* Normal buffered output */
+ syslog_putc_t sc_force; /* Low-level output for interrupt handlers */
+ syslog_flush_t sc_flush; /* Flush buffered output (on crash) */
+
+ /* Implementation specific logic may follow */
+ };
+
+
+ The channel interface is instantiated by calling syslog_channel()
:
+
+
+
+Function Prototype:
+
+#include <nuttx/syslog/syslog.h>
+int syslog_channel(FAR const struct syslog_channel_s *channel);
+
+Description:
+ Configure the SYSLOG function to use the provided channel to generate SYSLOG output.
+
+
+ syslog_channel()
is a non-standard, internal OS interface and is not available to applications. It may be called numerous times as necessary to change channel interfaces.
+ By default, all system log output goes to console (/dev/console
).
+
+Input Parmeters:
+
+Returned Value:
+
+
+
+
+ The initial, default SYSLOG channel is established with statically initialized global variables so that some level of SYSLOG output may be available immediately upon reset. This initialized data is in the file drivers/syslog/syslog_channel.c
. The initial SYSLOG capability is determined by the selected SYSLOG channel:
+
+
+ -
+
+ In-Memory Buffer (RAMLOG). Full SYSLOG capability as available at reset.
+
+ -
+
+ Serial Console. If the serial implementation provides the low-level character output function up_putc()
, then that low level serial output is available as soon as the serial device has been configured.
+
+ -
+
+ For all other SYSLOG channels, all SYSLOG output goes to the bit-
+ bucket until the SYSLOG channel device has been initialized.
+
+
+
+ The syslog channel device is initialized when the bring-up logic calls syslog_initialize()
:
+
+
+
+Function Prototype:
+
+#include <nuttx/syslog/syslog.h>
+#ifndef CONFIG_ARCH_SYSLOG
+int syslog_initialize(enum syslog_init_e phase);
+#else
+# define syslog_initialize(phase)
+#endif
+
+Description:
+ One power up, the SYSLOG facility is non-existent or limited to very low-level output. This function is called later in the initialization sequence after full driver support has been initialized. It installs the configured SYSLOG drivers and enables full SYSLOG capability.
+
+
+ This function performs these basic operations:
+
+
+ -
+
+ Initialize the SYSLOG device
+
+ -
+
+ Call syslog_channel()
to begin using that device.
+
+ -
+
+ If CONFIG_ARCH_SYSLOG
is selected, then the architecture-specific logic will provide its own SYSLOG device initialize which must include as a minimum a call to syslog_channel()
to use the device.
+
+
+Input Parameters:
+
+Returned Value:
+ Zero (OK
) is returned on success; a negated errno
value is returned on any failure.
+
+
+ Different types of SYSLOG devices have different OS initialization
+ requirements. Some are available immediately at reset, some are available
+ after some basic OS initialization, and some only after OS is fully
+ initialized. In order to satisfy these different initialization
+ requirements, syslog_initialize()
is called twice from the boot-up logic:
+
+
+ -
+
+ syslog_initialize()
is called from the architecture-specific up_initialize()
function as some as basic hardware resources have been initialized: Timers, interrupts, etc. In this case, syslog_initialize()
is called with the argument SYSLOG_INIT_EARLY
.
+
+ -
+
+ syslog_initialize()
is called again from os_start()
when the full OS initialization has completed, just before the application main entry point is spawned. In this case, syslog_initialize()
is called with the argument SYSLOG_INIT_LATE
.
+
+
+
+ There are other types of SYSLOG channel devices that may require even further initialization. For example, the file SYSLOG channel (described below) cannot be initialized until the necessary file systems have been mounted.
+
+
+
+
+ As a general statement, SYSLOG output only supports //normal// output from NuttX tasks. However, for debugging purposes, it is also useful to get SYSLOG output from interrupt level logic. In an embedded system, that is often where the most critical operations are performed.
+
+
+ There are three conditions under which SYSLOG output generated from interrupt level processing can a included the SYSLOG output stream:
+
+
+ -
+
Low-Level Serial Output.
+ If you are using a SYSLOG console channel (CONFIG_SYSLOG_CONSOLE
) with a serial console (CONFIG_SYSLOG_SERIAL_CONSOLE
) and if the underlying architecture supports the low-level up_putc()
interface(CONFIG_ARCH_LOWPUTC
), then the SYLOG logic will direct the output to up_putc()
which is capable of generating the serial output within the context of an interrupt handler.
+
+
+ There are a few issues in doing this however:
+
+
+ -
+
+ up_putc()
is able to generate debug output in any context because it disables serial interrupts and polls the hardware directly. These polls may take many milliseconds and during that time, all interrupts are disable within the interrupt handler. This, of course, interferes with the real-time behavior of the RTOS.
+
+
+ -
+
+ The output generated by up_putc()
is immediate and in real-time. The normal SYSLOG output, on the other hand, is buffered in the serial driver and may be delayed with respect to the immediate output by many lines. Therefore, the interrupt level SYSLOG ouput provided throug up_putc()
is grossly out of synchronization with other debug output
+
+
+
+
+
+-
+
In-Memory Buffering.
+ If the RAMLOG SYSLOG channel is supported, then all SYSLOG output is buffered in memory. Interrupt level SYSLOG output is no different than normal SYSLOG output in this case.
+
+
+-
+
Serialization Buffer.
+ A final option is the use the an interrupt buffer to buffer the interrupt level SYSLOG output. In this case:
+
+
+ -
+
+ SYSLOG output generated from interrupt level process in not sent to the SYSLOG channel immediately. Rather, it is buffered in the interrupt serialization buffer.
+
+
+ -
+
+ Later, when the next normal syslog output is generated, it will first empty the content of the interrupt buffer to the SYSLOG device in the proper context. It will then be followed by the normal syslog output. In this case, the interrupt level SYSLOG output will interrupt the normal output stream and the interrupt level SYSLOG output will be inserted into the correct position in the SYSLOG output when the next normal SYLOG output is generated.
+
+
+
+
+ The SYSLOG interrupt buffer is enabled with CONFIG_SYSLOG_INTBUFFER
. When the interrupt buffer is enabled, you must also provide the size of the interrupt buffer with CONFIG_SYSLOG_INTBUFSIZE
.
+
+
+
+
+
+
+
+ The typical SYSLOG device is the system console. If you are using a serial console, for example, then the SYSLOG output will appear on that serial port.
+
+
+ This SYSLOG channel is automatically selected by syslog_initialize()
in the LATE initialization phase based on configuration options. The configuration options that affect this channel selection include:
+
+
+ -
+
+ CONFIG_DEV_CONSOLE
. This setting indicates that the system supports a console device, i.e., that the character device /dev/console
exists.
+
+ -
+
+ CONFIG_SERIAL_CONSOLE
. This configuration option is automatically selected when a UART or USART is configured as the system console. There is no user selection.
+
+ -
+
+ CONFIG_SYSLOG_CONSOLE
. This configuration option is manually selected from the SYSLOG menu. This is the option that acutally enables the SYSLOG console device. It depends on CONFIG_DEV_CONSOLE
and it will automatically select CONFIG_SYSLOG_SERIAL_CONSOLE
if CONFIG_SERIAL_CONSOLE
is selected.
+
+ -
+
+ CONFIG_ARCH_LOWPUTC
. This is an indication from the architecture configuration that the platform supports the up_putc()
interface. up_putc()
is a very low level UART interface that can even be used from interrupt handling.
+
+ -
+
+ CONFIG_SYSLOG_SERIAL_CONSOLE
. This enables certain features of the SYSLOG operation that depend on a serial console. If CONFIG_ARCH_LOWPUTC
is also selected, for example, then up_putc()
will be used for the forced SYSLOG output.
+
+
+
+ Interrupt level SYSLOG output will be lost unless: (1) the interrupt buffer
+ is enabled to support serialization, or (2) a serial console is used and
+ up_putc()
is supported.
+
+
+ NOTE: The console channel uses the fixed character device at /dev/console
. The console channel is not synonymous with stdout
(or file descriptor 1). stdout
is the current output from a task when, say, printf()
if used. Initially, stdout
does, indeed, use the /dev/console
device. However, stdout
may subsequently be redirected to some other device or file. This is always the case, for example, when a transient device is used for a console -- such as a USB console or a Telnet console. The SYSLOG channel is not redirected as stdout
is; the SYSLOG channel will stayed fixed (unless it is explicitly changed via syslog_channel()
).
+
+
+ References: drivers/syslog/syslog_consolechannel.c
and
+ drivers/syslog/syslog_device.c
+
+
+
+
+ The system console device, /dev/console
, is a character driver with some special properties. However, any character driver may be used as the SYSLOG output channel. For example, suppose you have a serial console on /dev/ttyS0
and you want SYSLOG output on /dev/ttyS1
. Or suppose you support only a Telnet console but want to capture debug output /dev/ttyS0
.
+
+
+ This SYSLOG device channel is selected with CONFIG_SYSLOG_CHAR
and has no other dependencies. Differences fromthe SYSLOG console channel include:
+
+
+ -
+
+ CONFIG_SYSLOG_DEVPATH
. This configuration option string must be set provide the full path to the character device to be used.
+
+ -
+
+ The forced SYSLOG output always goes to the bit-bucket. This means that interrupt level SYSLOG output will be lost unless the interrupt buffer is enabled to support serialization.
+
+ -
+
+ CONFIG_SYSLOG_CHAR_CRLF
. If CONFIG_SYSLOG_CHAR_CRLF
is selected, then linefeeds in the SYSLOG output will be expanded to Carriage Return plus Linefeed. Since the character device is not a console device, the addition of carriage returns to line feeds would not be performed otherwise. You would probably want this expansion if you use a serial terminal program with the character device output.
+
+
+
+ References: drivers/syslog/syslog_devchannel.c
and drivers/syslog/syslog_device.c
+
+
+
+
+ Files can also be used as the sink for SYSLOG output. There is, however, a very fundamental difference in using a file as opposed the system console, a RAM buffer, or character device: You must first mount the file system that supports the SYSLOG file. That difference means that the file SYSLOG channel cannot be supported during the boot-up phase but can be instantiated later when board level logic configures the application environment, including mounting of the file systems.
+
+
+ The interface syslog_file_channel()
is used to configure the SYSLOG file channel:
+
+
+
+Function Prototype:
+
+#include <nuttx/syslog/syslog.h>
+#ifdef CONFIG_SYSLOG_FILE
+int syslog_file_channel(FAR const char *devpath);
+#endif
+
+Description:
+ Configure to use a file in a mounted file system at devpath
as the SYSLOG channel.
+
+
+ This tiny function is simply a wrapper around syslog_dev_initialize()
and syslog_channel()
. It calls syslog_dev_initialize()
to configure the character file at devpath
then calls syslog_channel()
to use that device as the SYSLOG output channel.
+
+
+ File SYSLOG channels differ from other SYSLOG channels in that they cannot be established until after fully booting and mounting the target file system. This function would need to be called from board-specific bring-up logic AFTER mounting the file system containing devpath
.
+
+
+ SYSLOG data generated prior to calling syslog_file_channel()
will, of course, not be included in the file.
+
+
+ NOTE interrupt level SYSLOG output will be lost in this case unless the interrupt buffer is used.
+
+
+Input Parameters:
+
+ -
+
+ devpath
: The full path to the file to be used for SYSLOG output. This may be an existing file or not. If the file exists,
+ syslog_file_channel()
will append new SYSLOG data to the end of the file. If it does not, then syslog_file_channel()
will create the file.
+
+
+Returned Value:
+ Zero (OK
) is returned on success; a negated errno
value is returned on any failure.
+
+
+ References: drivers/syslog/syslog_filechannel.c
, drivers/syslog/syslog_device.c
, and include/nuttx/syslog/syslog.h
.
+
+
+
+
+ The RAMLOG is a standalone feature that can be used to buffer any
+ character data in memory. There are, however, special configurations
+ that can be used to configure the RAMLOG as a SYSLOG channel. The RAMLOG
+ functionality is described in a more general way in the following
+ paragraphs.
+
+
+
+
+ The RAM logging driver is a driver that was intended to support debugging output (SYSLOG) when the normal serial output is not available. For example, if you are using a Telnet or USB serial console, the debug output will get lost -- or worse. For example, what if you want to debug the network over Telnet?
+
+
+ The RAM logging driver can also accept debug output data from interrupt handler with no special serialization buffering. As an added benefit, the RAM logging driver is much less invasive. Since no actual I/O is performed with the debug output is generated, the RAM logger tends to be much faster and will interfere much less when used with time critical drivers.
+
+
+ The RAM logging driver is similar to a pipe in that it saves the debugging output in a circular buffer in RAM. It differs from a pipe in numerous details as needed to support logging.
+
+
+ This driver is built when CONFIG_RAMLOG
is defined in the Nuttx configuration.
+
+
+
+
+ When the RAMLOG (with SYSLOG) is enabled, a new NuttShell (NSH) command will appear: dmesg
. The dmesg
command will dump the contents of the circular buffer to the console (and also clear the circular buffer).
+
+
+
+
+ -
+
+ CONFIG_RAMLOG
: Enables the RAM logging feature
+
+ -
+
+ CONFIG_RAMLOG_CONSOLE
: Use the RAM logging device as a system console. If this feature is enabled (along with CONFIG_DEV_CONSOLE
), then all console output will be re-directed to a circular buffer in RAM. This might be useful, for example, if the only console is a Telnet console. Then in that case, console output from non-Telnet threads will go to the circular buffer and can be viewed using the NSH dmesg
command. This optional is not useful in other scenarios.
+
+ -
+
+ CONFIG_RAMLOG_SYSLOG
: Use the RAM logging device for the SYSLOG interface. If this feature is enabled, then all debug output will be re-directed to the circular buffer in RAM. This RAM log can be viewed from NSH using the dmesg
command. NOTE: Unlike the limited, generic character driver SYSLOG device, the RAMLOG can be used to capture debug output from
+ interrupt level handlers.
+
+ -
+
+ CONFIG_RAMLOG_NPOLLWAITERS
: The number of threads than can be waiting for this driver on poll()
. Default: 4
+
+
+
+ If CONFIG_RAMLOG_CONSOLE
or CONFIG_RAMLOG_SYSLOG
is selected, then the following must also be provided:
+
+
+
+ Other miscellaneous settings
+
+
+ -
+
+ CONFIG_RAMLOG_CRLF
: Pre-pend a carriage return before every linefeed that goes into the RAM log.
+
+ -
+
+ CONFIG_RAMLOG_NONBLOCKING
: Reading from the RAMLOG will never block if the RAMLOG is empty. If the RAMLOG is empty, then zero is returned (usually interpreted as end-of-file). If you do not define this, the NSH dmesg
command will lock up when called! So you probably do want this!
+
+ -
+
+ CONFIG_RAMLOG_NPOLLWAITERS
: The maximum number of threads that may be waiting on the poll method.
+
+
+
+
-
+
Power Management (PM) Sub-System.
NuttX supports a simple power management (PM) sub-system. This sub-system:
@@ -5633,12 +6137,12 @@ int kbd_decode(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *sta
Multiple PM domains might be useful, for example, if you would want to control power states associated with a network separately from power states associated with a user interface.
-
+
All PM interfaces are declared in the file include/nuttx/power/pm.h
.
-
+
Function Prototype:
#include <nuttx/power/pm.h>
@@ -5655,7 +6159,7 @@ None
None
-
+
Function Prototype:
#include <nuttx/power/pm.h>
@@ -5675,7 +6179,7 @@ int pm_register(FAR struct pm_callback_s *callbacks);
Zero (OK
) on success; otherwise a negated errno
value is returned.
-
+
Function Prototype:
#include <nuttx/power/pm.h>
@@ -5704,7 +6208,7 @@ void pm_activity(int domain, int priority);
This function may be called from an interrupt handler (this is the ONLY PM function that may be called from an interrupt handler!).
-
+
Function Prototype:
#include <nuttx/power/pm.h>
@@ -5734,7 +6238,7 @@ enum pm_state_e pm_checkstate(int domain);
The recommended power management state.
-
+
Function Prototype:
#include <nuttx/power/pm.h>
@@ -5764,14 +6268,14 @@ enum pm_state_e pm_checkstate(int domain);
suspend the IDLE thread before it completes the entire state change unless interrupts are disabled throughout the state change.
-
+
The struct pm_callback_s
includes the pointers to the driver callback functions.
This structure is defined include/nuttx/power/pm.h
.
These callback functions can be used to provide power management information to the driver.
-
+
Function Prototype:
int (*prepare)(FAR struct pm_callback_s *cb, int domain, enum pm_state_e pmstate);
@@ -5801,7 +6305,7 @@ int (*prepare)(FAR struct pm_callback_s *cb, int domain, enum pm_state_e pmstate
consumption modes!
-
+
Function Prototype:
#include <nuttx/power/pm.h>
diff --git a/Documentation/NuttxUserGuide.html b/Documentation/NuttxUserGuide.html
index a91959e198d41fb126e6397e5865d4efe39135df..3766eba646fda9464e641f870b44ecacf44972e0 100644
--- a/Documentation/NuttxUserGuide.html
+++ b/Documentation/NuttxUserGuide.html
@@ -8755,9 +8755,8 @@ FAR void *mmap(FAR void *start, size_t length, int prot, int flags, int fd, off_
- NuttX includes a simple interface layer based on uIP (see http://www.sics.se).
- NuttX supports subset of a standard socket interface to uIP.
- These network feature can be enabled by settings in the architecture configuration file.
+ NuttX supports a BSD-compatible socket interface layer.
+ These socket interface can be enabled by settings in the architecture configuration file.
Those socket APIs are discussed in the following paragraphs.
diff --git a/Documentation/UsbTrace.html b/Documentation/UsbTrace.html
index 7efb7ebccbae864f39babfe12d882a25209fa3e4..a6800983d5bcb272c099f6bfba24de374b9a707a 100644
--- a/Documentation/UsbTrace.html
+++ b/Documentation/UsbTrace.html
@@ -125,7 +125,7 @@
CONFIG_USBDEV_TRACE
, or
- CONFIG_DEBUG and CONFIG_DEBUG_USB
+ CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_USB
Log Data Sink.
The logged data itself may go to either (1) an internal circular buffer, or (2) may be provided on the console.
@@ -137,7 +137,7 @@
Here is an example of USB trace output using apps/examples/usbserial
for an LPC1768 platform with the following NuttX configuration settings:
- CONFIG_DEBUG
, CONFIG_DEBUG_VERBOSE
, CONFIG_USB
+ CONFIG_DEBUG_FEATURES
, CONFIG_DEBUG_INFO
, CONFIG_USB
CONFIG_EXAMPLES_USBSERIAL_TRACEINIT
, CONFIG_EXAMPLES_USBSERIAL_TRACECLASS
,
CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS
, CONFIG_EXAMPLES_USBSERIAL_TRACECONTROLLER
,
CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS
diff --git a/FlatLibs.mk b/FlatLibs.mk
index 13dcc6c3400f0b24f52fe5bfd140265af0a8c6f3..69fe6a9fa067419996c597ec493e4273d519c0a8 100644
--- a/FlatLibs.mk
+++ b/FlatLibs.mk
@@ -45,6 +45,12 @@
NUTTXLIBS = lib$(DELIM)libsched$(LIBEXT)
USERLIBS =
+# Driver support. Generally depends on file descriptor support but there
+# are some components in the drivers directory that are needed even if file
+# descriptors are not supported.
+
+NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
+
# Add libraries for board support
NUTTXLIBS += lib$(DELIM)libconfigs$(LIBEXT)
@@ -89,11 +95,8 @@ ifeq ($(CONFIG_NFILE_DESCRIPTORS),0)
ifneq ($(CONFIG_NSOCKET_DESCRIPTORS),0)
NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT)
endif
-ifeq ($(CONFIG_NET),y)
-NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
-endif
else
-NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libdrivers$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
+NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
endif
# Add libraries for the NX graphics sub-system
diff --git a/Kconfig b/Kconfig
index 17d6e351f9eb96bb6f72fe51044c4780d9a375a1..c174c16e4cb5e97417909295eeb92d7bd829ba79 100644
--- a/Kconfig
+++ b/Kconfig
@@ -395,9 +395,14 @@ endmenu # Customize Header Files
menu "Debug Options"
-config DEBUG
+config DEBUG_ALERT
+ bool
+ default n
+
+config DEBUG_FEATURES
bool "Enable Debug Features"
default n
+ select DEBUG_ALERT
---help---
Enables built-in debug features. Selecting this option will (1) Enable
debug assertions in the code, (2) enable extended parameter testing in
@@ -405,71 +410,270 @@ config DEBUG
Note that enabling this option by itself does not produce debug output.
Debug output must also be selected on a subsystem-by-subsystem basis.
-config ARCH_HAVE_HEAPCHECK
- bool
+if DEBUG_FEATURES
+
+comment "Debug SYSLOG Output Controls"
+
+config DEBUG_ERROR
+ bool "Enable Error Output"
default n
+ ---help---
+ Enables output from [a-z]err() statements. Errors are significant system
+ exceptions that require immediate attention.
-if DEBUG
+config DEBUG_WARN
+ bool "Enable Warnings Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enables output from [a-z]warn() statements. Warnings are considered to
+ be various unexpected conditions, potential errors or errors that will
+ not have serious consequences.
-config DEBUG_VERBOSE
- bool "Enable Debug Verbose Output"
+config DEBUG_INFO
+ bool "Enable Informational Debug Output"
default n
+ depends on DEBUG_WARN
---help---
- Enables verbose debug output (assuming debug features are enabled).
- As a general rule, when DEBUG is enabled only errors will be
- reported in the debug SYSLOG output. But if you also enable
- DEBUG_VERBOSE, then very chatty (and often annoying) output will be
- generated. This means there are two levels of debug output:
- errors-only and everything.
+ Enables verbose "informational" debug output. If you enable
+ CONFIG_DEBUG_INFO, then very chatty (and often annoying) output
+ will be generated.
+
+config DEBUG_ASSERTIONS
+ bool "Enable Debug Assertions"
+ default n
+ ---help---
+ Enables the DEBUGASSERT() macro. When CONFIG_DEBUG_ASSERTIONS is
+ defined, DEBUGASSERT() will cause the system to halt if the
+ assertion fails. If CONFIG_DEBUG_ASSERTIONS is not defined
+ DEBUGASSERT() compiled out of the system. In general, you would
+ set CONFIG_DEBUG_ASSERTIONS=y during debug, but disable the
+ assertions on a final, buckled up system.
comment "Subsystem Debug Options"
config DEBUG_AUDIO
- bool "Audio Device Debug Output"
+ bool "Audio Device Debug Features"
default n
depends on AUDIO
---help---
- Enable low level debug SYSLOG output from the audio subsystem and
+ Enable audio device debug features.
+ Enable low level debug featurs for the audio subsystem and for audio
device drivers. (disabled by default). Support for this debug option
is architecture-specific and may not be available for some MCUs.
+if DEBUG_AUDIO
+
+config DEBUG_AUDIO_ERROR
+ bool "Audio Device Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable audio device error output to SYSLOG.
+
+config DEBUG_AUDIO_WARN
+ bool "Audio Device Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable audio device warning output to SYSLOG.
+
+config DEBUG_AUDIO_INFO
+ bool "Audio Device Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable audio device informational output to SYSLOG.
+
+endif # DEBUG_AUDIO
+
config DEBUG_BINFMT
- bool "Binary Loader Debug Output"
+ bool "Binary Loader Debug Features"
default n
depends on !BINFMT_DISABLE
---help---
- Enable binary loader debug SYSLOG output (disabled by default)
+ Enable binary loader debug features.
+
+if DEBUG_BINFMT
+
+config DEBUG_BINFMT_ERROR
+ bool "Binary Loader Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable binary loader error output to SYSLOG.
+
+config DEBUG_BINFMT_WARN
+ bool "Binary Loader Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable binary loader warning output to SYSLOG.
+
+config DEBUG_BINFMT_INFO
+ bool "Binary Loader Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable binary loader informational output to SYSLOG.
+
+endif # DEBUG_BINFMT
config DEBUG_CRYPTO
- bool "Crypto Debug Output"
+ bool "Crypto Debug Features"
default n
depends on CRYPTO
---help---
- Enable Crypto debug SYSLOG output (disabled by default)
+ Enable cryptographic debug features.
+
+if DEBUG_CRYPTO
+
+config DEBUG_CRYPTO_ERROR
+ bool "Crypto Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable cryptographic error output to SYSLOG.
+
+config DEBUG_CRYPTO_WARN
+ bool "Crypto Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable cryptographic warning output to SYSLOG.
+
+config DEBUG_CRYPTO_INFO
+ bool "Crypto Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable cryptographic informational output to SYSLOG.
+
+endif # DEBUG_CRYPTO
config DEBUG_FS
- bool "File System Debug Output"
+ bool "File System Debug Features"
default n
---help---
- Enable file system debug SYSLOG output (disabled by default)
+ Enable file system debug features.
+
+if DEBUG_FS
+
+config DEBUG_FS_ERROR
+ bool "File System Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable file system error output to SYSLOG.
+
+config DEBUG_FS_WARN
+ bool "File System Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable file system warning output to SYSLOG.
+
+config DEBUG_FS_INFO
+ bool "File System Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable file system informational output to SYSLOG.
+
+endif # DEBUG_FS
config DEBUG_GRAPHICS
- bool "Graphics Debug Output"
+ bool "Graphics Debug Features"
default n
---help---
- Enable NX graphics debug SYSLOG output (disabled by default)
+ Enable NX graphics subsystem debug features.
+
+if DEBUG_GRAPHICS
+
+config DEBUG_GRAPHICS_ERROR
+ bool "Graphics Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable NX graphics subsystem error output to SYSLOG.
+
+config DEBUG_GRAPHICS_WARN
+ bool "Graphics Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable NX graphics subsystem warning output to SYSLOG.
+
+config DEBUG_GRAPHICS_INFO
+ bool "Graphics Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable NX graphics subsystem informational output to SYSLOG.
+
+endif # DEBUG_GRAPHICS
config DEBUG_LIB
- bool "C Library Debug Output"
+ bool "C Library Debug Features"
+ default n
+ ---help---
+ Enable C library debug features.
+
+if DEBUG_LIB
+
+config DEBUG_LIB_ERROR
+ bool "C Library Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable C library error output to SYSLOG.
+
+config DEBUG_LIB_WARN
+ bool "C Library Warnings Output"
default n
+ depends on DEBUG_WARN
---help---
- Enable C library debug SYSLOG output (disabled by default)
+ Enable C library warning output to SYSLOG.
+
+config DEBUG_LIB_INFO
+ bool "C Library Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable C library informational output to SYSLOG.
+
+endif # DEBUG_LIB
config DEBUG_MM
- bool "Memory Manager Debug Output"
+ bool "Memory Manager Debug Features"
default n
---help---
- Enable memory management debug SYSLOG output (disabled by default)
+ Enable memory management debug features.
+
+if DEBUG_MM
+
+config DEBUG_MM_ERROR
+ bool "Memory Manager Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable memory management error output to SYSLOG.
+
+config DEBUG_MM_WARN
+ bool "Memory Manager Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable memory management warning output to SYSLOG.
+
+config DEBUG_MM_INFO
+ bool "Memory Manager Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable memory management informational output to SYSLOG.
+
+endif # DEBUG_MM
config DEBUG_SHM
bool "Shared Memory Debug Output"
@@ -479,25 +683,101 @@ config DEBUG_SHM
Enable shared memory management debug SYSLOG output (disabled by default)
config DEBUG_NET
- bool "Network Debug Output"
+ bool "Network Debug Features"
default n
depends on ARCH_HAVE_NET
---help---
- Enable network debug SYSLOG output (disabled by default)
+ Enable network debug features.
+
+if DEBUG_NET
+
+config DEBUG_NET_ERROR
+ bool "Network Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable network error output to SYSLOG.
+
+config DEBUG_NET_WARN
+ bool "Network Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable network warning output to SYSLOG.
+
+config DEBUG_NET_INFO
+ bool "Network Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable network informational output to SYSLOG.
+
+endif # DEBUG_NET
config DEBUG_SCHED
- bool "Scheduler Debug Output"
+ bool "Scheduler Debug Features"
default n
---help---
- Enable OS debug SYSLOG output (disabled by default)
+ Enable OS scheduler debug features.
+
+if DEBUG_SCHED
+
+config DEBUG_SCHED_ERROR
+ bool "Scheduler Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable OS scheduler error output to SYSLOG.
+
+config DEBUG_SCHED_WARN
+ bool "Scheduler Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable OS scheduler warning output to SYSLOG.
+
+config DEBUG_SCHED_INFO
+ bool "Scheduler Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable OS scheduler informational output to SYSLOG.
+
+endif # DEBUG_SCHED
config DEBUG_SYSCALL
- bool "SYSCALL Debug Output"
+ bool "SYSCALL Debug Features"
default n
depends on LIB_SYSCALL
---help---
- Enable very low level output related to system calls. This gives
- you basically a poor man's version of strace.
+ Enable very low level features related to system calls. If SYSCAL
+ output is enabled, this gives you basically a poor man's version of
+ strace.
+
+if DEBUG_SYSCALL
+
+config DEBUG_SYSCALL_ERROR
+ bool "SYSCALL Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable OS SYSCALL error output to SYSLOG.
+
+config DEBUG_SYSCALL_WARN
+ bool "SYSCALL Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable OS SYSCALL warning output to SYSLOG.
+
+config DEBUG_SYSCALL_INFO
+ bool "SYSCALL Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable OS SYSCALL informational output to SYSLOG.
+
+endif # DEBUG_SYSCALL
config DEBUG_WIRELESS
bool "Wireless Device Debug Output"
@@ -511,25 +791,46 @@ config DEBUG_WIRELESS
comment "OS Function Debug Options"
config DEBUG_DMA
- bool "DMA Debug Output"
+ bool "DMA Debug Features"
default n
depends on ARCH_DMA
---help---
- Enable DMA-releated debug SYSLOG output (disabled by default).
+ Enable DMA debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
-config DEBUG_HEAP
- bool "Heap usage debug hooks"
+if DEBUG_DMA
+
+config DEBUG_DMA_ERROR
+ bool "DMA Error Output"
default n
- depends on ARCH_HAVE_HEAPCHECK
+ depends on DEBUG_ERROR
---help---
- Enable hooks to check heap usage. Only supported by a few architectures.
+ Enable DMA error output to SYSLOG.
+
+config DEBUG_DMA_WARN
+ bool "DMA Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable DMA warning output to SYSLOG.
+
+config DEBUG_DMA_INFO
+ bool "DMA Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable DMA informational output to SYSLOG.
+
+endif # DEBUG_DMA
config DEBUG_IRQ
- bool "Interrupt Controller Debug Output"
+ bool "Interrupt Controller Debug Features"
default n
---help---
+ Enable interrupt controller debug features.
+
Some (but not all) architectures support debug output to verify
interrupt controller logic. If supported, then option will enable
that output. This may interfere with normal operations! You
@@ -537,158 +838,634 @@ config DEBUG_IRQ
that here is a problem with that logic. On some platforms, this
option may even cause crashes! Use with care!
+if DEBUG_IRQ
+
+config DEBUG_IRQ_ERROR
+ bool "DMA Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable interrupt controller error output to SYSLOG.
+
+config DEBUG_IRQ_WARN
+ bool "DMA Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable interrupt controller warning output to SYSLOG.
+
+config DEBUG_IRQ_INFO
+ bool "DMA Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable interrupt controller informational output to SYSLOG.
+
+endif # DEBUG_IRQ
+
config DEBUG_PAGING
- bool "Demand Paging Debug Output"
+ bool "Paging Debug Features"
default n
depends on PAGING
---help---
- Enable demand paging debug SYSLOG output (disabled by default)
+ Enable OS demand paging debug features.
+
+if DEBUG_PAGING
+
+config DEBUG_PAGING_ERROR
+ bool "Paging Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable OS demand paging error output to SYSLOG.
+
+config DEBUG_PAGING_WARN
+ bool "Paging Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable OS demand paging warning output to SYSLOG.
+
+config DEBUG_PAGING_INFO
+ bool "Paging Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable OS demand paging informational output to SYSLOG.
+
+endif # DEBUG_PAGING
comment "Driver Debug Options"
config DEBUG_LCD
- bool "Low-level LCD Debug Output"
+ bool "Low-level LCD Debug Features"
default n
depends on LCD
---help---
- Enable low level debug SYSLOG output from the LCD driver (disabled
- by default). Support for this debug option is board-specific and
- may not be available for some boards.
+ Enable LCD driver debug features.
+
+ Support for this debug option is board-specific and may not
+ be available for some boards.
+if DEBUG_LCD
+
+config DEBUG_LCD_ERROR
+ bool "LCD Driver Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable LCD driver error output to SYSLOG.
+
+config DEBUG_LCD_WARN
+ bool "LCD Driver Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable LCD driver warning output to SYSLOG.
+
+config DEBUG_LCD_INFO
+ bool "LCD Driver Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable LCD driver informational output to SYSLOG.
+
+endif # DEBUG_LCD
config DEBUG_LEDS
- bool "Low-level LED Debug Output"
+ bool "Low-level LED Debug Features"
default n
depends on ARCH_HAVE_LEDS
---help---
- Enable low level debug from board-specific LED logic. Support for
- this debug option is board-specific and may not be available for
- some boards.
+ Enable LED driver debug features.
+
+ Support for this debug option is board-specific and may not
+ be available for some boards.
+
+if DEBUG_LEDS
+
+config DEBUG_LEDS_ERROR
+ bool "LED Driver Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable LED driver error output to SYSLOG.
+
+config DEBUG_LEDS_WARN
+ bool "LED Driver Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable LED driver warning output to SYSLOG.
+
+config DEBUG_LEDS_INFO
+ bool "LED Driver Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable LED driver informational output to SYSLOG.
+
+endif # DEBUG_LEDS
config DEBUG_INPUT
- bool "Input Device Debug Output"
+ bool "Input Device Debug Features"
default n
depends on INPUT
---help---
- Enable low level debug SYSLOG output from the input device drivers
+ Enable input d.
+ Enable low level evice debug features for the input device drivers
such as mice and touchscreens (disabled by default). Support for
this debug option is board-specific and may not be available for
some boards.
+if DEBUG_INPUT
+
+config DEBUG_INPUT_ERROR
+ bool "Input Device Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable input device error output to SYSLOG.
+
+config DEBUG_INPUT_WARN
+ bool "Input Device Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable input device warning output to SYSLOG.
+
+config DEBUG_INPUT_INFO
+ bool "Input Device Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable input device informational output to SYSLOG.
+
+endif # DEBUG_INPUT
+
config DEBUG_ANALOG
- bool "Analog Device Debug Output"
+ bool "Analog Device Debug Features"
default n
+ depends on ANALOG
---help---
- Enable low level debug SYSLOG output from the analog device drivers
- such as A/D and D/A converters (disabled by default). Support for
- this debug option is architecture-specific and may not be available
- for some MCUs.
+ Enable analog device debug features.
+ Enable low level debug features the analog device drivers such as
+ A/D and D/A converters (disabled by default). Support for this
+ debug option is architecture-specific and may not be available for
+ some MCUs.
+
+if DEBUG_ANALOG
+
+config DEBUG_ANALOG_ERROR
+ bool "Analog Device Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable analog device error output to SYSLOG.
+
+config DEBUG_ANALOG_WARN
+ bool "Analog Device Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable analog device warning output to SYSLOG.
+
+config DEBUG_ANALOG_INFO
+ bool "Analog Device Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable CAN driver informational output to SYSLOG.
+
+endif # DEBUG_ANALOG
config DEBUG_CAN
- bool "CAN Debug Output"
+ bool "CAN Debug Features"
default n
depends on CAN
---help---
- Enable CAN driver debug SYSLOG output (disabled by default).
+ Enable CAN driver debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
+if DEBUG_CAN
+
+config DEBUG_CAN_ERROR
+ bool "CAN Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable CAN driver error output to SYSLOG.
+
+config DEBUG_CAN_WARN
+ bool "CAN Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable CAN driver warning output to SYSLOG.
+
+config DEBUG_CAN_INFO
+ bool "CAN Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable CAN driver informational output to SYSLOG.
+
+endif # DEBUG_CAN
+
config DEBUG_GPIO
- bool "GPIO Debug Output"
+ bool "GPIO Debug Features"
default n
---help---
- Enable GPIO-releated debug SYSLOG output (disabled by default).
+ Enable GPIO debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
+if DEBUG_GPIO
+
+config DEBUG_GPIO_ERROR
+ bool "GPIO Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable GPIO error output to SYSLOG.
+
+config DEBUG_GPIO_WARN
+ bool "GPIO Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable GPIO warning output to SYSLOG.
+
+config DEBUG_GPIO_INFO
+ bool "GPIO Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable GPIO informational output to SYSLOG.
+
+endif # DEBUG_GPIO
+
config DEBUG_I2C
- bool "I2C Debug Output"
+ bool "I2C Debug Features"
default n
depends on I2C
---help---
- Enable I2C driver debug SYSLOG output (disabled by default).
+ Enable I2C debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
+if DEBUG_I2C
+
+config DEBUG_I2C_ERROR
+ bool "I2C Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable I2C driver error output to SYSLOG.
+
+config DEBUG_I2C_WARN
+ bool "I2C Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable I2C driver warning output to SYSLOG.
+
+config DEBUG_I2C_INFO
+ bool "I2C Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable I2C driver informational output to SYSLOG.
+
+endif # DEBUG_I2C
+
config DEBUG_I2S
- bool "I2S Debug Output"
+ bool "I2S Debug Features"
default n
depends on I2S
---help---
- Enable I2S driver debug SYSLOG output (disabled by default).
+ Enable I2S debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
+if DEBUG_I2S
+
+config DEBUG_I2S_ERROR
+ bool "I2S Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable I2S driver error output to SYSLOG.
+
+ Support for this debug option is architecture-specific and may not
+ be available for some MCUs.
+
+config DEBUG_I2S_WARN
+ bool "I2S Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable I2S driver warning output to SYSLOG.
+
+config DEBUG_I2S_INFO
+ bool "I2S Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable I2S driver informational output to SYSLOG.
+
+endif # DEBUG_I2S
+
config DEBUG_PWM
- bool "PWM Debug Output"
+ bool "PWM Debug Features"
default n
depends on PWM
---help---
- Enable PWM driver debug SYSLOG output (disabled by default).
+ Enable PWM debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
+if DEBUG_PWM
+
+config DEBUG_PWM_ERROR
+ bool "PWM Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable PWM driver error output to SYSLOG.
+
+ Support for this debug option is architecture-specific and may not
+ be available for some MCUs.
+
+config DEBUG_PWM_WARN
+ bool "PWM Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable PWM driver warning output to SYSLOG.
+
+config DEBUG_PWM_INFO
+ bool "PWM Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable PWM driver informational output to SYSLOG.
+
+endif # DEBUG_PWM
+
config DEBUG_RTC
- bool "RTC Debug Output"
+ bool "RTC Debug Features"
default n
depends on RTC
---help---
- Enable RTC driver debug SYSLOG output (disabled by default).
+ Enable RTC debug features.
+
+ Support for this debug option is architecture-specific and may not
+ be available for some MCUs.
+
+if DEBUG_RTC
+
+config DEBUG_RTC_ERROR
+ bool "RTC Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable RTC driver error output to SYSLOG.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
-config DEBUG_SDIO
- bool "SDIO Debug Output"
+config DEBUG_RTC_WARN
+ bool "RTC Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable RTC driver warning output to SYSLOG.
+
+config DEBUG_RTC_INFO
+ bool "RTC Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable RTC driver informational output to SYSLOG.
+
+endif # DEBUG_RTC
+
+config DEBUG_MEMCARD
+ bool "Memory Card Driver Debug Features"
default n
depends on MMCSD_SDIO
---help---
- Enable SDIO driver debug SYSLOG output (disabled by default).
+ Enable MMC/SD memory card Driver debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
+if DEBUG_MEMCARD
+
+config DEBUG_MEMCARD_ERROR
+ bool "Memory Card Driver Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable MMC/SD memory card driver error output to SYSLOG.
+
+ Support for this debug option is architecture-specific and may not
+ be available for some MCUs.
+
+config DEBUG_MEMCARD_WARN
+ bool "Memory Card Driver Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable MMC/SD memory card driver warning output to SYSLOG.
+
+config DEBUG_MEMCARD_INFO
+ bool "Memory Card Driver Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable MMC/SD memory card driver informational output to SYSLOG.
+
+endif # DEBUG_MEMCARD
+
config DEBUG_SENSORS
- bool "Sensor Debug Output"
+ bool "Sensor Debug Features"
default n
depends on SENSORS
---help---
- Enable sensor driver debug SYSLOG output (disabled by default).
+ Enable sensor driver debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
+if DEBUG_SENSORS
+
+config DEBUG_SENSORS_ERROR
+ bool "Sensor Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable sensor driver error output to SYSLOG.
+
+config DEBUG_SENSORS_WARN
+ bool "Sensor Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable sensor driver warning output to SYSLOG.
+
+config DEBUG_SENSORS_INFO
+ bool "Sensor Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable sensor driver informational output to SYSLOG.
+
+endif # DEBUG_SENSORS
+
config DEBUG_SPI
- bool "SPI Debug Output"
+ bool "SPI Debug Features"
default n
depends on SPI
---help---
- Enable I2C driver debug SYSLOG output (disabled by default).
+ Enable SPI debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
+if DEBUG_SPI
+
+config DEBUG_SPI_ERROR
+ bool "SPI Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable SPI error output to SYSLOG.
+
+config DEBUG_SPI_WARN
+ bool "SPI Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable SPI warning output to SYSLOG.
+
+config DEBUG_SPI_INFO
+ bool "SPI Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable SPI informational output to SYSLOG.
+
+endif # DEBUG_SPI
+
config DEBUG_TIMER
- bool "Timer Debug Output"
+ bool "Timer Debug Features"
default n
depends on TIMER
---help---
- Enable timer debug SYSLOG output (disabled by default).
+ Enable timer debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
+if DEBUG_TIMER
+
+config DEBUG_TIMER_ERROR
+ bool "Timer Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable timer error output to SYSLOG.
+
+config DEBUG_TIMER_WARN
+ bool "Timer Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable timer warning output to SYSLOG.
+
+config DEBUG_TIMER_INFO
+ bool "Timer Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable timer informational output to SYSLOG.
+
+endif # DEBUG_TIMER
+
config DEBUG_USB
- bool "USB Debug Output"
+ bool "USB Debug Features"
default n
depends on USBDEV || USBHOST
---help---
- Enable usb debug SYSLOG output (disabled by default)
+ Enable USB debug features.
+
+if DEBUG_USB
+
+config DEBUG_USB_ERROR
+ bool "USB Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable USB error output to SYSLOG.
+
+config DEBUG_USB_WARN
+ bool "USB Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable USB warning output to SYSLOG.
+
+config DEBUG_USB_INFO
+ bool "USB Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable USB informational output to SYSLOG.
+
+endif # DEBUG_USB
config DEBUG_WATCHDOG
- bool "Watchdog Timer Debug Output"
+ bool "Watchdog Timer Debug Features"
default n
depends on WATCHDOG
---help---
- Enable watchdog timer debug SYSLOG output (disabled by default).
+ Enable watchdog timer debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
-endif # DEBUG
+if DEBUG_WATCHDOG
+
+config DEBUG_WATCHDOG_ERROR
+ bool "Watchdog Timer Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable watchdog time error output to SYSLOG.
+
+config DEBUG_WATCHDOG_WARN
+ bool "Watchdog Timer Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable watchdog time warning output to SYSLOG.
+
+config DEBUG_WATCHDOG_INFO
+ bool "Watchdog Timer Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable watchdog time informational output to SYSLOG.
+
+endif # DEBUG_WATCHDOG
+endif # DEBUG_FEATURES
config ARCH_HAVE_STACKCHECK
bool
@@ -705,6 +1482,18 @@ config STACK_COLORATION
Only supported by a few architectures.
+config ARCH_HAVE_HEAPCHECK
+ bool
+ default n
+
+config HEAP_COLORATION
+ bool "Heap coloration"
+ default n
+ depends on ARCH_HAVE_HEAPCHECK
+ ---help---
+ Enable heap coloration to check heap usage. Only supported by a few
+ architectures.
+
config DEBUG_SYMBOLS
bool "Generate Debug Symbols"
default n
diff --git a/KernelLibs.mk b/KernelLibs.mk
index a7888d714dceec8e15641311fc2fe46a6886d748..719430b6c9be4d435f414d62813dd4b87022f35b 100644
--- a/KernelLibs.mk
+++ b/KernelLibs.mk
@@ -45,6 +45,12 @@
NUTTXLIBS = lib$(DELIM)libsched$(LIBEXT)
USERLIBS =
+# Driver support. Generally depends on file descriptor support but there
+# are some components in the drivers directory that are needed even if file
+# descriptors are not supported.
+
+NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
+
# Add libraries for board support
NUTTXLIBS += lib$(DELIM)libconfigs$(LIBEXT)
@@ -83,11 +89,8 @@ ifeq ($(CONFIG_NFILE_DESCRIPTORS),0)
ifneq ($(CONFIG_NSOCKET_DESCRIPTORS),0)
NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT)
endif
-ifeq ($(CONFIG_NET),y)
-NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
-endif
else
-NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libdrivers$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
+NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
endif
# Add libraries for the NX graphics sub-system
diff --git a/Makefile.unix b/Makefile.unix
index 022c7962169728566385ea3666e8b05b01815b47..a6913ad672a7a87a9b5887a426ab5303a328f8ec 100644
--- a/Makefile.unix
+++ b/Makefile.unix
@@ -480,22 +480,22 @@ pass2dep: context tools/mkdeps$(HOSTEXEEXT) tools/cnvwindeps$(HOSTEXEEXT)
# location: http://ymorin.is-a-geek.org/projects/kconfig-frontends. See
# README.txt file in the NuttX tools GIT repository for additional information.
-config: apps_preconfig
+config: context apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf Kconfig
-oldconfig: apps_preconfig
+oldconfig: context apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf --oldconfig Kconfig
-olddefconfig: apps_preconfig
+olddefconfig: context apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf --olddefconfig Kconfig
-menuconfig: apps_preconfig
+menuconfig: context apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-mconf Kconfig
-qconfig: apps_preconfig
+qconfig: context apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-qconf Kconfig
-gconfig: apps_preconfig
+gconfig: context apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-gconf Kconfig
# export
diff --git a/Makefile.win b/Makefile.win
index 5a71a42122b76d51fa96d2422549c6f45480c04a..5556efb79ff28a9a4d183bab6dc7b3ba1bd4c4e9 100644
--- a/Makefile.win
+++ b/Makefile.win
@@ -480,16 +480,16 @@ pass2dep: context tools\mkdeps$(HOSTEXEEXT)
# location: http://ymorin.is-a-geek.org/projects/kconfig-frontends. See
# misc\tools\README.txt for additional information.
-config: apps_preconfig
+config: context apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf Kconfig
-oldconfig: apps_preconfig
- $(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf --oldconfig Kconfig
+oldconfig: context apps_preconfig
+ $(Q) context set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf --oldconfig Kconfig
-olddefconfig: apps_preconfig
+olddefconfig: context apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf --olddefconfig Kconfig
-menuconfig: configenv apps_preconfig
+menuconfig: context configenv apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-mconf Kconfig
# export
diff --git a/ProtectedLibs.mk b/ProtectedLibs.mk
index 70185eacf47162a4f850a36919d398786f3f97b2..4f2e2c6072d35fc34030967de75fa7fe93434c5d 100644
--- a/ProtectedLibs.mk
+++ b/ProtectedLibs.mk
@@ -45,6 +45,12 @@
NUTTXLIBS = lib$(DELIM)libsched$(LIBEXT)
USERLIBS =
+# Driver support. Generally depends on file descriptor support but there
+# are some components in the drivers directory that are needed even if file
+# descriptors are not supported.
+
+NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
+
# Add libraries for board support
NUTTXLIBS += lib$(DELIM)libconfigs$(LIBEXT)
@@ -89,11 +95,8 @@ ifeq ($(CONFIG_NFILE_DESCRIPTORS),0)
ifneq ($(CONFIG_NSOCKET_DESCRIPTORS),0)
NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT)
endif
-ifeq ($(CONFIG_NET),y)
-NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
-endif
else
-NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libdrivers$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
+NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
endif
# Add libraries for the NX graphics sub-system
diff --git a/README.txt b/README.txt
index db0e5e6c10b2e3f515978c38b7a3223be767639c..b3cb19a407d1186cd21c99a0e3c7c5ec67d60efc 100644
--- a/README.txt
+++ b/README.txt
@@ -960,10 +960,13 @@ Native Windows Build
In this build, you cannot use a Cygwin or MSYS shell. Rather the build must
be performed in a Windows console window. Here is a better terminal than the
standard issue, CMD.exe terminal: ConEmu which can be downloaded from:
- http://code.google.com/p/conemu-maximus5/
+ https://sourceforge.net/projects/conemu/ or https://conemu.github.io/ .
Build Tools. The build still relies on some Unix-like commands. I use
- the GNUWin32 tools that can be downloaded from http://gnuwin32.sourceforge.net/.
+ the GNUWin32 tools that can be downloaded from http://gnuwin32.sourceforge.net/
+ using the 'Download all' selection. Individual packages can be download
+ instead if you know what you are doing and want a faster download (No, I
+ can't tell you which packages you should or should not download).
Host Compiler: I use the MingGW GCC compiler which can be downloaded from
http://www.mingw.org/. If you are using GNUWin32, then it is recommended
@@ -971,12 +974,13 @@ Native Windows Build
This capability should still be considered a work in progress because:
- (1) It has not been verified on all targets and tools, and
- (2) it still lacks some of the creature-comforts of the more mature environments.
+ (1) It has not been verified on all targets and tools, and
+ (2) it still lacks some of the creature-comforts of the more mature
+ environments.
- There is an alternative to the setenv.sh script available for the Windows
- native environment: tools/configure.bat. See tools/README.txt for additional
- information.
+ There is an alternative to the setenv.sh script available for the Windows
+ native environment: tools/configure.bat. See tools/README.txt for additional
+ information.
Installing GNUWin32
-------------------
diff --git a/ReleaseNotes b/ReleaseNotes
index 89cf4119a4d6c8e6d8c3d67735711e75b99d81fd..c760fca73723f71cf5a0ac0ae51f45a043ffefad 100644
--- a/ReleaseNotes
+++ b/ReleaseNotes
@@ -5303,7 +5303,8 @@ Additional new features and extended functionality:
can be re-enabled if needed via configuration option.
- NXFFS: Make the start up scan of the media a configuration option.
It just takes to long and is not really necessary! Those rare cases
- where the scan was helpful can be fixed using flash_eraseall().
+ where the scan was helpful can be fixed using MDIOC_BULKERASE IOCTL
+ command.
* General Drivers:
@@ -10716,3 +10717,365 @@ detailed bugfix information):
- Moved C++ initialization logic out of the RTOS and into the
application space, specifically to apps/platform/board, where it
belongs.
+
+NuttX-7.16 Release Notes
+------------------------
+
+The 116th release of NuttX, Version 7.16, was made on June 1, 2016,
+and is available for download from the Bitbucket.org website. Note
+that release consists of two tarballs: nuttx-7.16.tar.gz and
+apps-7.16.tar.gz. These are available from:
+
+ https://bitbucket.org/nuttx/nuttx/downloads
+ https://bitbucket.org/nuttx/apps/downloads
+
+Both may be needed (see the top-level nuttx/README.txt file for build
+information).
+
+Additional new features and extended functionality:
+
+ * Core OS:
+
+ - Power Management: Add activity domain to all PM interfaces and
+ driver callbacks. If CONFIG_PM_NDOMAINS == 1, then the legacy
+ behavior is preserved. If CONFIG_PM_NDOMAINS > 1, then multiple
+ PM domains are supported. This will allow separate control for
+ certain power management groups. For example, a network can be
+ shut down without affect an ongoing UI (and vice versa).
+ - board_app_initialize(): board_app_initialize() now accepts an
+ argument that may be used to support initialization in different
+ configurations.
+
+ * File System and Block and MTD Drivers:
+
+ - N25Qxxx: Add MTD support for Micron N25Qxxx family of QSPI flash.
+ From Dave (ziggurat29).
+ - SST26F: Add an MTD driver for SST26F spi/qspi flash devices (SPI
+ mode only). From Sebastien Lorquet.
+ - File Descriptor Detach: Add logic to detach a file structure from a
+ file descriptor. This is for use only within the OS. It permits an
+ open file or driver to be used across multiple threads.
+
+ * Networking and Network Drivers:
+
+ - listen()/accept(): Separate out psock_listen() and psock_accepti()
+ for internal, thread independent OS usage (i.e., without a socket
+ descriptor).
+ - VNC Server: Add support for a VNC server. This logic is code
+ complete and functional, but not well tested.
+
+ * Graphics and Graphic Drivers:
+
+ - Framebuffer driver: Add a display number to each interface in order
+ to support multiple display devices.
+ - VNC Server: Add support for a VNC server. This logic is code
+ complete and functional, but not well tested.
+ - LCD Backpack: Add support for PCF8574 LCD Backpack driver. This
+ driver supports an interface board that is based on the PCF8574 I/O
+ expander and supports the HD44780-based (or compatible) LCD modules.
+ There are a myriad of different vendors of such, but they are
+ principally the same, save wiring and minor features like jumpers
+ for I2C addresses. This driver supports known and unknown variants.
+ From Dave (ziggurat29).
+
+ * Common Device Drivers:
+
+ - RTC: Simplify the RTC interface. The old interface was way too
+ complex and was not fully implemented anywhere.
+ - BH1750FVI: Add a character driver for Rohm Ambient Light Sensor
+ BH1750FVI. From Alan Carvalho de Assis.
+ - CAN: Improve CAN error reporting. From Frank Benkert.
+ - aes.h: Modifications to the crypto API needed for LPC43xx. From
+ Alexander Vasiljev.
+ - ADC: Interface no longer uses global adc_receive() call. Added a
+ new bind() method to the ADC interface. Now the ADC upper half
+ driver will register its receipt-of-data callback. This change
+ allows the ADC lower half driver to be used with a differ ADC upper
+ half.
+
+ * Simulation Platform:
+
+ - Linux Host Networking: Enhance networking support for the
+ simulation under Linux. Includes updated support for Linux TUN/TAP,
+ and the addition of support for Linux bridge devices. From Steve.
+
+ * ARMv7-A, ARMv7-R, and ARMv7-M:
+
+ - ARMv7-M: Convert more assembly language files for use with the IAR
+ toolchain. From Kha Vo.
+ - ARMv7-A: Complete re-design of SMP-related logic to initialize each
+ CPUn, n > 0, when CONFIG_SMP=y.
+
+ * Atmel SAMV7:
+
+ - Add a JTAG config and ERASE config to Kconfig to set the
+ CCFG_SYSIO SYSIO Pins. From David Sidrane.
+ - System Reset: Add the up_systemreset interface to the samv7 arch. The
+ approach is slightly different in that: 1) It enables ARCH_HAVE_RESET
+ and allows the user to set if, and for how long, to drive External
+ nRST signal. It also does not contain a default board_reset, as that
+ really should be done in the config's src if CONFIG_BOARDCTL_RESET
+ is defined. From David Sidrane.
+
+ * Atmel SAMV7 Boards:
+
+ - SAMV71-XULT: Add configuration(s) that were be used to verify VNC
+ graphics output as well as mouse and keyboard input.
+
+ * NXP Freescale i.MX6 Boards:
+
+ - Sabre-6Quad: The basic i.MX6 port is complete. This is a minimal
+ port at present and probably still has some as-of-yet-undiscovered
+ issues.
+ - Sabre-6Quad: Basic SMP NSH configuration is now working. But this
+ is probably only because the SMP test case does not stress the
+ logic. There are know outstanding SMP issues as noted in the
+ Sabre-6Quad README.txt file.
+
+ * NXP Freescale LPC43xx:
+
+ - LPC4337jet100: Add definitions for the LPC4337jet100 chip. From
+ Alexander Vasiljev.
+
+ * NXP Freescale LPC43xx Drivers:
+
+ - AES: Add AES support. From Alexander Vasiljev.
+
+ * STMicro STM32:
+
+ - STM32 L4: Add configuration options to allow SRAM2 to be used for
+ heap, or not at all, and to zero-initialize it on OS start, or not
+ at all. From Dave dev@ziggurat29.com.
+ - STM32 L4: Add support for HSE and MSI clocks, and auto trim of MSI
+ to LSE (needed for USB). From Dave (ziggurat29)
+ - STM32 L4: Add support for unique id function to arch; modified board
+ to support unique id boardctl. From Dave (ziggurat29)
+
+ * STMicro STM32 Drivers:
+
+ - STM32 F4 RTC: Add a custom RTC driver with support for alarms. From
+ Neil Hancock.
+ - STM32 L4 QSPI: Add a QSPI driver with DMA support and (optional
+ memory mapped mode support. From Dave ziggurat29).
+ - STM32, STM32 L4, and STM32 F7 Serial: Add support for compliant
+ SD-style breaks. From David Sidrane.
+ - STM32 L4 CAN: Add CAN support for STM32L4. From Sebastien Lorquet.
+ - STM32 1-Wire: Add support for a custom 1-wire driver. The serial
+ driver already supports a 1-wire interface, but this driver uses the
+ same serial logic to implement a lower half driver much like the
+ I2C lower half driver. From Aleksandr Vyhovanec.
+ - STM32 L4 SPI: Add support for SPI 4 and 5 on stm32f411 chips. From
+ Konstantin Berezenko.
+ - STM32 ADC: Allow omitting use of channels in a lower part of PWM.
+ From Pierre-noel Bouteville.
+ - STM32 L4 I2C: Get I2C working for STM32L4. From Dave (ziggurat29).
+
+ * STMicro STM32 Boards:
+
+ - STM3220G-EVAL: Add support for both the IAR and uVision GCC IDEs.
+ From Kha Vo.
+ - STM32F429I Discovery: Add support for the uVision GCC IDE. From
+ Kha Vo.
+ - STM32F4 Discovery: Integrate BH1750FVI driver in the STM32F4 Discovery
+ board. From Alan Carvalho de Assis.
+ - STM32L476VG Discovery: Add support for QSPI based N25Qxxx flash.
+ From Dave (ziggurat29)
+ - STM32L476VG Discovery: Add board ioctls for allowing user application
+ to cause QSPI memory mapped mode to be engaged and disengaged. Also
+ partitioned QSPI flash for file system and other (eventually xip).
+ From Dave (ziggurat29)
+ - Nucleo-144: Basic port for the Nucleo-144 board with the STM32F746ZG
+ MCU. From Kconstantin Berezenko.
+ - STM32F103 Minimum: Add support for this minimual STM32F103CBT6 "blue"
+ board. From Alan Carvalho de Assis.
+ - STM32F411E Discovery: Add basic configuration for stm32f411e-disco
+ board with STM32F411VE chip. From Konstantin Berezenko.
+
+ * Build/Configuration System:
+
+ - Moved NuttX repository to https://bitbucket.org/nuttx/nuttx.
+ Eliminated use of sub-modules.
+ - Add support for the IAR toolchain for the limited case of the ARMv7-M
+ architecture and the STM32 chip. From Aleksandr Vyhovanec.
+ - make export: Pass top-level make to the script to allow -j greater
+ than 1. From David Sidrane.
+ - fs/Kconfig: Allow CONFIG_FS_WRITABLE to be manually selectable. This
+ is needed when there are no writable file systems, but write support
+ is still needed in BCH or FTL.
+ - arch/*/Makefile: Add definitions that can be overrided to use GCC
+ instead of LD in the final link. From Paul Alexander Patience .
+
+ * Applications: apps/netutils:
+
+ - apps/netutils/esp8266: ESP8266 driver application. From Pierre-noel
+ Bouteville.
+
+ * Applications: apps/examples:
+
+ - apps/examples/alarm: Add a simple test of the ALARM iotcl calls of
+ the RTC driver.
+ - apps/examples/nximage: Add a configuration option to select
+ greyscale.
+
+ * Platforms: apps/platform:
+
+ - apps/platform/nucleo-144: Add platform files for NUCLEO-144
+ (NUCLEO-F746ZG). From Mark Olsson.
+ - apps/examples/media: You can now override the default device driver
+ path by providing an alternal path on the command line. From
+ Sbastien Lorquet.
+
+Works-In-Progress:
+
+ * IEEE802.14.5/6LowPAN. Hooks and framework for this effort were
+ introduced in NuttX-7.15. Work has continued on this effort on
+ forks from the main repositories, albeit with many interruptions.
+ The completion of this wireless feature will postponed until at
+ least NuttX-7.17.
+
+ * i.MX6 SMP. Partially functional, but there is more that still
+ needs to be done.
+
+Bugfixes. Only the most critical bugfixes are listed here (see the
+ChangeLog for the complete list of bugfixes and for additional, more
+detailed bugfix information):
+
+ * Core OS:
+
+ - Various places: Search for places where a stray semicolon following
+ an if condition cause the if body to be executed unconditionally.
+ Fixes in all SAM DMA logic, unionfs, OS signalling logic, and others.
+ - enter/leave_critical_section() may attempt to access task lists
+ before they have been initialized in the SMP configuration.
+
+ * File System/Block Drivers:
+
+ - SMART MTD: Return code of smart_scan not checked, can cause success
+ result in failure case, leading to 'dev' pointer being invalid. From
+ Dave (ziggurat29)
+ - mount: Fix a backward debug assertion. Noted by David Sidrane.
+
+ * Common Drivers:
+
+ - NRF24L01: Fix backward calculation of relative frequency. Noted by
+ Henry Zhang.
+ - PCA9555 I/O expander: Fix an error in the PCA9555 driver: Under
+ certain error conditions, interrupts were not being re-enabled.
+ Sebastien Lorquet.
+ - ADS1255: Must not do SPI access from interrupt handler. Use the
+ worker thread instead. Must also lock the SPI bus before using it.
+ - Several SPI-based drivers modified. All drivers that use SPI must
+ call SPI_LOCK and SPI_UNLOCK. This is not optional.
+ - MS583730: Fix a bug in crc computation for ms583730. Implement
+ POSIX read.
+
+ * Atmel SAMV7:
+
+ - Fix typo in MATRIX register definitions. From Stefan Kolb.
+ - SAMV7 Tickless Mode: This is a fix to a problem in the handling of
+ the oneshot timer. Due to a wrong assumption concerning the behavior
+ directly after the start of the timer/counter the function
+ sam_oneshot_cancel() calculates the wrong remaining time. The code
+ assumes that the counter register is zero directly after the start
+ of the timer, but this is not true. To start the time/counter a
+ software trigger is invoked, this trigger starts the timer/count and
+ sets the counter register to zero, but the reset of the counter
+ register is not performed instantly. According to the datasheet:
+ "The counter can be reset by a trigger. In this case, the counter
+ value passes to zero on the next valid edge of the selected clock."
+ Thus the counter is set to zero between 0 and USEC_PER_TICK
+ microseconds after the clock was started.
+ In my fix I use the freerun count value to determine if at least one
+ tick passed since the start of the timer and thus if the value of
+ the oneshot counter is correct. I also tried to use the function
+ up_timer_gettime() to achieve this but, at least if compiled with
+ no optimization the problem vanishes without using the value of the
+ function, the function call takes too long.
+ Another problem treated in the fix is that if the oneshot timer/counter
+ is canceled, we only know the remaining time with a precision of
+ USEC_PER_TICK microseconds. This means the calculated remaining time
+ is between 0 and USEC_PER_TICK microseconds too long. To fix this I
+ subtract one tick if the calculated remaining time is greater than
+ one tick and otherwise set the remaining time to zero. By doing so
+ the measured times are much more precise as without it. From Stefan
+ Kolb.
+
+ * Atmel SAMA5:
+
+ - SAMA5: Stefan Kolb's change to the SAMV7 Oneshot Timer should also
+ be applied to the SAMA5 oneshot time since the drivers are identical.
+
+ * Atmel SAM3/4:
+
+ - SAM3/4: Stefan Kolb's change to the SAMV7 Oneshot Timer should also
+ be applied to the SAM3/4 oneshot time since the drivers are identical.
+
+ * Atmel SAMV7 Drivers:
+
+ - SAMV7 TWIHS (as well as SAM3/4 and SAMA5: Ensure that the TWIHS
+ (i2c) hw get's its clock set when the sequence of
+ sam_i2cbus_initialize(), sam_i2cbus_uninitialize(), then
+ sam_i2cbus_initialize() or twi_reset() is called. I found this a
+ while back in the stm32 family, so there may be more arch-es with
+ this sort of bug. I suppose any driver that has the notion of "do
+ not set the freq if it is already set" could be suspect. From David
+ Sidrane.
+ - USBHS Device: Remove disabling of whole USB on suspend of USBHS.
+ This fix removes the disabling of the whole USB peripheral on
+ suspend interrupt. Its enough to freeze the clock instead. When
+ disabling the whole peripheral, the next wakeup-interrupt comes up
+ with an disabled clocking. The unfreeze clock has no effect, because
+ the master clock is disabled. This makes all registers, including
+ the IDR unwriteable and the IRQ falls in an endless loop blocking
+ the whole system. Furthermore the disabling of the peripheral clock
+ prevents hotplugging or reconnecting the USB. From Frank Benkert.
+ - MCAN: Fix missing unlock of device in MCAN mcan_txempty(). From
+ Frank Benkert.
+
+ * STMicro STM32:
+
+ - STM32 L4 Clocking: Problem with resetting backup domain clears
+ clocking options set up before in *rcc.c use INITS flag to avoid
+ magic reg value to detect power up reset state of RTC correct a
+ problem clearing interrupt flags (they weren't) which prevented an
+ alarm from ever being used more than once per reset cycle. From
+ Dave (ziggurat29)
+
+ * STMicro STM32 Drivers:
+
+ - STM32L4 SPI: That STM32Lr SPI driver is quite different. They now
+ handle frames of arbitrary size between 4 and 16 bits. It was broken
+ before a new bit has to be set (RX fifo threshold) to handle <= 8-bit
+ transactions. If not set, the default is 16-bit packed >=8-bit
+ frames and the RXNE bit is never set (it is set when 16-bits are
+ received). weird things as always. This also add 8-bit access
+ routines to the data register, because a 16-bit access to the data
+ register when the frame size is below 9 bits is interpreted as a
+ packed dual frame exchange. Sebastien Lorquet.
+ - STM32: Correct some bad commits that broke the LTDC display example.
+ From Marco Krahl.
+ - STM32 F4 RTC: Fix logic in F4 RTCC driver that prevent ALARM
+ interrupt. From Neil Hancock.
+ - STM32 F1 ADC: Fix STM32 ValueLine ADC IRQ number selection. From
+ David Sidrane.
+
+ * STMicro STM32 Boards:
+
+ - STM32F429I Discovery: Correct some bad commits that broke the LTDC
+ display example. From Marco Krahl.
+
+ * TI Tiva:
+
+ - GPIO Interrupts: Fix a bug of GPIO falling-edge interrupt for tiva.
+ From Young.
+
+ * C Library:
+
+ - math: Add a NAN test on 'x' in asin function of lib_asin.c. Suggested
+ by Pierre-noel Bouteville.
+
+ * Build/Configuration System:
+
+ - Several Makefiles: Add .PHONY definitions to prevent 'clean up to date'
+ message weirdness when 'make clean' is done with no .config or
+ Make.defs file.
diff --git a/TODO b/TODO
index eeb3e6d29dd90561c3bde9a85ba40df051df2874..a4c960e2e18b5004b1242728731a7c3ee3caa424 100644
--- a/TODO
+++ b/TODO
@@ -1,4 +1,4 @@
-NuttX TODO List (Last updated May 28, 2016)
+NuttX TODO List (Last updated June 6, 2016)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -23,7 +23,7 @@ nuttx/:
(11) Libraries (libc/, libm/)
(11) File system/Generic drivers (fs/, drivers/)
(8) Graphics subsystem (graphics/)
- (1) Build system / Toolchains
+ (2) Build system / Toolchains
(3) Linux/Cywgin simulation (arch/sim)
(4) ARM (arch/arm/)
@@ -599,6 +599,12 @@ o Kernel/Protected Build
For a truly secure system. Privileges need to be checked in
every interface that permits one thread to modify the
properties of another thread.
+
+ NOTE: It would be a simple matter to simply disable user
+ threads from modifying privileged threads. However, you
+ might also want to be able to modify privileged threads from
+ user tasks with certain permissions. Permissions is a much
+ more complex issue.
Status: Open
Priority: Low for most embedded systems but would be a critical need if
NuttX were used in a secure system.
@@ -1595,6 +1601,19 @@ o Build system
Status: Open
Priority: Low.
+ Title: NATIVE WINDOWS BUILD BROKEN
+ Description: The way that apps/ no generates Kmenu files depends on changes added
+ to apps/tools/mkkconfig.sh. Similar changes need to be made to
+ apps/tools/mkkconfig.bat to restore the Windows Native build.
+ UPDATE: The mkkconfig.bat script has been updated and appears to work.
+ A native build has still not been attempted and there could likely be
+ issues the carriage returns in Kconfig files. There are also some
+ issues the interpreters/ficl and bas directories during 'make menuconfig'
+ that still need to be investigated.
+ Status: Open
+ Priority: Low, since I am not aware of anyone using the Windows Native build.
+ But, of course, very high if you want to use it.
+
o Other drivers (drivers/)
^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/arch/Kconfig b/arch/Kconfig
index fd61f2fbf55f96b6af107d6dc625c9454d389d94..fa5bf48edaac40ba39ebdad7f7ad75fc5d50b770 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -58,6 +58,7 @@ config ARCH_SIM
select ARCH_HAVE_TLS
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_POWEROFF
+ select SERIAL_CONSOLE
---help---
Linux/Cywgin user-mode simulation.
@@ -525,6 +526,7 @@ config ARCH_IRQPRIO
config ARCH_STACKDUMP
bool "Dump stack on assertions"
default n
+ select DEBUG_ALERT
---help---
Enable to do stack dumps after assertions
diff --git a/arch/README.txt b/arch/README.txt
index df34133df9c310d0555b4c7a0c033cbe5946d062..114f2f6f1e7e430067cf244458edbc5a37ffada5 100644
--- a/arch/README.txt
+++ b/arch/README.txt
@@ -134,6 +134,8 @@ src/Makefile
Supported Architectures
^^^^^^^^^^^^^^^^^^^^^^^
+NOTE: nuttx/Documentation/NuttX.html for current information about the
+state of these MCU ports.
arch/sim - Linux/Cygwin simulation
A user-mode port of NuttX to the x86 Linux platform is available.
@@ -145,135 +147,68 @@ arch/arm - ARM-based micro-controllers
This directory holds common ARM architectures. At present, this includes
the following subdirectories:
- arch/arm/include and arch/arm/src/common
- Common ARM/Cortex-M3 logic.
-
- arch/arm/src/arm and arch/arm/include/arm
- Common ARM-specific logic
-
- arch/arm/src/armv7-m and arch/arm/include/armv7-m
- Common ARMv7-M logic (Cortex-M3 and Cortex-M4)
-
- arch/arm/include/c5471 and arch/arm/src/c5471
- TI TMS320C5471 (also called TMS320DM180 or just C5471).
- NuttX operates on the ARM7 of this dual core processor. This port
- complete, verified, and included in the NuttX release 0.1.1.
-
- arch/arm/include/calypso and arch/arm/src/calypso
- TI "Calypso" MCU used in various cell phones (and, in particular,
- by the Osmocom-bb project). Like the c5471, NuttX operates on the
- ARM7 of this dual core processor. This port was contributed by
- Denis Carilki and includes the work of Denis, Alan Carvalho de Assis,
- and Stefan Richter. Calypso support first appeared in NuttX-6.17.
-
- arch/arm/include/dm320 and arch/arm/src/dm320
- TI TMS320DM320 (also called just DM320).
- NuttX operates on the ARM9EJS of this dual core processor. This port
- complete, verified, and included in the NuttX release 0.2.1.
-
- arch/arm/include/imx and arch/arm/src/imx
- Freescale MC9328MX1 or i.MX1. This port uses the Freescale MX1ADS
- development board with a GNU arm-elf toolchain* under either Linux or Cygwin.
- STATUS: This port has stalled because of development tool issues. Coding
- is complete on the basic port (timer, serial console, SPI).
-
- arch/arm/include/lm and arch/arm/src/lm
- These directories contain support for the Luminary LM3S/4F family. The
- initial, release of this port was included in NuttX version 0.4.6. The
- current port includes timer, serial console, Ethernet, SSI, and microSD
- support. There are working configurations the NuttX OS test, to run the
- NuttShell (NSH), the NuttX networking test, and the uIP web server.
-
- arch/arm/include/lpc214x and arch/arm/src/lpc214x
- These directories provide support for NXP LPC214x family of
- ARM7TDMI processors. This port boots and passes the OS test (examples/ostest).
- The port is complete and verifed. As of NuttX 0.3.17, the port includes:
- timer interrupts, serial console, USB driver, and SPI-based MMC/SD card
- support. A verifed NuttShell (NSH) configuration is also available.
-
- arch/arm/include/lpc2378 and arch/arm/src/lpc2378.
- NXP LPC2378. Support is provided for the NXP LPC2378 MCU. This port was
- contributed by Rommel Marcelo is was first released in NuttX-5.3.
- STATUS: This port boots and passes the OS test (examples/ostest) and
- includes a working implementation of the NuttShell (NSH). The port is
- complete and verified. As of NuttX 5.3, the port includes only basic
- timer interrupts and serial console support.
-
- arch/arm/include/lpc31xx and arch/arm/src/lpc31xx
- These directories provide support for NXP LPC31xx family of
- ARM926EJ-S processors. The port for the NXP LPC3131 was first
- released in NuttX-5.1 (but was not functional until NuttX-5.2).
- STATUS: The basic EA3131 port is complete and verified in NuttX-5.2
- This basic port includes basic boot-up, serial console, and timer
- interrupts. This port was extended in NuttX 5.3 with a USB high
- speed driver contributed by David Hewson. This port has been
- verified using the NuttX OS test, USB serial and mass storage tests
- and includes a working implementation of the NuttShell ((NSH)).
-
- This port was later extended to support additional members of the
- LPC31xx family including, specifically, the LPC3152.
-
- arch/arm/include/sam3u and arch/arm/src/sam3u
- Atmel AT91SAM3U. This port is for Atmel AT91SAM3U4E MCU.
- STATUS: The basic AT91SAM3U port was released in NuttX version 5.1.
- The basic port includes boot-up logic, interrupt driven serial
- console, and system timer interrupts. That release passes the
- NuttX OS test and is proven to have a valid OS implementation. A
- onfiguration to support the NuttShell is also included.
-
- arch/arm/include/stm32 and arch/arm/src/stm32
- These directories contain support for the STMicro STM32 F1, F2, and
- F4 families.
-
- STATUS: The basic STM32 F1 port was released in NuttX version 0.4.12.
- and has continued to develop consistently over time. It now includes
- support for the F2 and F4 families and a rich offering of peripheral
- drivers.
-
- arch/arm/include/str71x and arch/arm/src/str71x
- These directories provide support for the STMicro STR71x processors.
- Coding is complete on the basic port (boot logic, system time, serial console),
- but no testing has been performed due to some problems I am having with my
- JTAG wiggler and OpenOCD on Linux.
+ Architecture Support
+ arch/arm/include and arch/arm/src/common
+ arch/arm/src/arm and arch/arm/include/arm
+ arch/arm/src/armv7-a and arch/arm/include/armv7-a
+ arch/arm/src/armv7-m and arch/arm/include/armv7-m
+ arch/arm/src/armv7-r and arch/arm/include/armv7-4
+
+ MCU support
+ arch/arm/include/c5471 and arch/arm/src/c5471
+ arch/arm/include/calypso and arch/arm/src/calypso
+ arch/arm/include/dm320 and arch/arm/src/dm320
+ arch/arm/include/efm32 and arch/arm/src/efm32
+ arch/arm/include/imx1 and arch/arm/src/imx1
+ arch/arm/include/imx6 and arch/arm/src/imx6
+ arch/arm/include/kinetis and arch/arm/src/kinetis
+ arch/arm/include/kl and arch/arm/src/kl
+ arch/arm/include/lpc11xx and arch/arm/src/lpc11xx
+ arch/arm/include/lpc17xx and arch/arm/src/lpc17xx
+ arch/arm/include/lpc214x and arch/arm/src/lpc214x
+ arch/arm/include/lpc2378 and arch/arm/src/lpc2378.
+ arch/arm/include/lpc31xx and arch/arm/src/lpc31xx
+ arch/arm/include/lpc43xx and arch/arm/src/lpc43xx
+ arch/arm/include/moxart and arch/arm/src/moxart
+ arch/arm/include/nuc1xx and arch/arm/src/nuc1xx
+ arch/arm/include/sam34 and arch/arm/src/sam34
+ arch/arm/include/sama45 and arch/arm/src/sama5
+ arch/arm/include/samdl and arch/arm/src/samdl
+ arch/arm/include/samv7 and arch/arm/src/samv7
+ arch/arm/include/stm32 and arch/arm/src/stm32
+ arch/arm/include/stm32f7 and arch/arm/src/stm32f7
+ arch/arm/include/stm32l4 and arch/arm/src/stm32l4
+ arch/arm/include/str71x and arch/arm/src/str71x
+ arch/arm/include/tiva and arch/arm/src/tiva
+ arch/arm/include/tms570 and arch/arm/src/tms570
arch/avr
This directory is dedicated to ports to the Atmel AVR (8-bit) and AVR32 (32-bit)
MCU families. STATUS: Under development.
- arch/avr/include/avr and arch/avr/src/avr
- Common support for all 8-bit AVR MCUs
+ Architecture Support
+ arch/avr/include/avr and arch/avr/src/avr
+ arch/avr/include/avr32 and arch/avr/src/avr32
- arch/avr/include/atmega and arch/avr/src/atmega
- Support specifically for the AVR ATMega family (specifically only for
- the ATMega128 at the moment).
-
- arch/avr/include/at90usb and arch/avr/src/at90usb
- Support specifically for the AVR AT90USB646, 647, 1286, and 1287 family.
-
- arch/avr/include/avr32 and arch/avr/src/avr32
- Common support for all AVR32 MCUs
-
- arch/avr/include/at32uc3 and arch/avr/src/at32uc3
- Support specifically for the AT32UC3Bxxx family (specifically only for
- the AT32UC3B0256 at the moment).
+ MCU support
+ arch/avr/include/atmega and arch/avr/src/atmega
+ arch/avr/include/at90usb and arch/avr/src/at90usb
+ arch/avr/include/at32uc3 and arch/avr/src/at32uc3
arch/hc
This directory is dedicated to ports to the Freescale HC family.
arch/arm/include/m9s12 and arch/arm/src/m9s12
- These directories provide support for the Freescale mc9s12x family.
- STATUS: Fragments of this port were first released in nuttx-5.0 and
- the port was "code-complete" as nuttx-5.18. However, the final
- verification effort has been stalled because of higher priority tasks.
arch/mips
This directory is dedicated to ports to the MIPS family.
- arch/mips/include/mips32 and arch/mips/src/mips32
- Common support for all MIPS32 architectures
+ Architecture Support
+ arch/mips/include/mips32 and arch/mips/src/mips32
- arch/mips/include/pic32mx and arch/mips/src/pic32mx
- Support for all MicroChip PIC32MX architectures
+ MCU support
+ arch/mips/include/pic32mx and arch/mips/src/pic32mx
+ arch/mips/include/pic32mz and arch/mips/src/pic32mz
arch/rgmp
@@ -288,52 +223,42 @@ arch/rgmp
arch/sh - SuperH and related Hitachi/Renesas microcontrollers
- arch/sh/include and arch/sh/src/common
- Common SuperH logic.
+ Architecture Support
+ arch/sh/include and arch/sh/src/common
- arch/sh/include/shs and arch/sh/src/sh1
- Support for the SH-1 processor.
+ MCU support
+ arch/sh/include/m16c and arch/sh/src/m16c
+ arch/sh/include/sh1 and arch/sh/src/sh1
arch/x86 - Intel x86 architectures
This directory holds related, 32- and 64-bit architectures from Intel.
At present, this includes the following subdirectories:
- arch/x86/include and arch/x86/src/common
- Common x86 logic.
+ Architecture Support
+ arch/x86/include and arch/x86/src/common
- arch/x86/include/i486 and arch/x86/src/i486
- These directories hold definitions and logic appropriate for any
- instantiation of the 32-bit i486 architecture.
-
- arch/x86/include/qemu and arch/x86/src/qemu
- This is the implementation of NuttX on the QEMU x86 simulation.
+ MCU support
+ arch/x86/include/i486 and arch/x86/src/i486
+ arch/x86/include/qemu and arch/x86/src/qemu
arch/z16 - ZiLOG 16-bit processors
This directory holds related, 16-bit architectures from ZiLOG. At
present, this includes the following subdirectories:
- arch/z16/include and arch/z16/src/common
- Common microcontroller logic.
+ Architecture Support
+ arch/z16/include and arch/z16/src/common
- arch/z16/include/z16f and arch/z16/src/z16f
- ZiLOG z16f Microcontroller.
- STATUS: Released in nuttx-0.3.7. Fully functional other than issues
- addressed in ${TOPDIR}/TODO.
+ MCU support
+ arch/z16/include/z16f and arch/z16/src/z16f
arch/z80 - ZiLOG 8-bit microcontrollers
This directory holds related, 8-bit architectures from ZiLOG. At
present, this includes the following subdirectories:
- arch/z80/include and arch/z80/src/common
- Common microcontroller logic.
-
- arch/z80/include/z80 and arch/z80/src/z80
- Classic ZiLOG z80 Microcontroller.
- STATUS: Functional with no known defects. There are still several
- OS features that have not yet been tested (e.g., networking).
-
- arch/z80/include/z8 and arch/z80/src/z8
- ZiLOG Z8Encore! Microcontroller
+ Architecture Support
+ arch/z80/include and arch/z80/src/common
- arch/z80/include/ez80 and arch/z80/src/ez80
- ZiLOG ez80 Acclaim! Microcontroller
+ MCU support
+ arch/z80/include/z80 and arch/z80/src/z80
+ arch/z80/include/z8 and arch/z80/src/z8
+ arch/z80/include/ez80 and arch/z80/src/ez80
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6b6c046060d4e3ba2d7233c2a90d9f18b1c401f0..fcc1c9ce9821b82dbbfc1f61b1bf29523a391529 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -213,6 +213,7 @@ config ARCH_CHIP_SAMV7
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_TICKLESS
select ARMV7M_HAVE_STACKCHECK
+ select ARCH_HAVE_I2CRESET
---help---
Atmel SAMV7 (ARM Cortex-M7) architectures
@@ -588,7 +589,7 @@ config ARCH_ROMPGTABLE
config DEBUG_HARDFAULT
bool "Verbose Hard-Fault Debug"
default n
- depends on DEBUG && (ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7)
+ depends on DEBUG_FEATURES && (ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7)
---help---
Enables verbose debug output when a hard fault is occurs. This verbose
output is sometimes helpful when debugging difficult hard fault problems,
diff --git a/arch/arm/include/efm32/irq.h b/arch/arm/include/efm32/irq.h
index 7bd0449d621d225ad6408ea8d6422c28f71e4781..a5f2eff8e47850dc2826a75f7887f0bbe7461022 100644
--- a/arch/arm/include/efm32/irq.h
+++ b/arch/arm/include/efm32/irq.h
@@ -60,7 +60,7 @@
/* Processor Exceptions (vectors 0-15) */
-#define EFM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define EFM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define EFM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/kinetis/irq.h b/arch/arm/include/kinetis/irq.h
index 3355f29b02cf2dcaa2570722632ddea9bd1c57a9..16b59ab8ae96fc4054e91e16ac849c0cb2f2293f 100644
--- a/arch/arm/include/kinetis/irq.h
+++ b/arch/arm/include/kinetis/irq.h
@@ -58,7 +58,7 @@
/* Processor Exceptions (vectors 0-15) */
-#define KINETIS_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define KINETIS_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define KINETIS_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/kl/irq.h b/arch/arm/include/kl/irq.h
index 27ba8575f52d023f7c9324244a967c05075b6d1c..93021827300d09f52eb1c91b7518cbe43a6d123c 100644
--- a/arch/arm/include/kl/irq.h
+++ b/arch/arm/include/kl/irq.h
@@ -58,7 +58,7 @@
/* Processor Exceptions (vectors 0-15) */
-#define KL_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define KL_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define KL_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/lpc11xx/irq.h b/arch/arm/include/lpc11xx/irq.h
index caac7c3e170c1d858882bbf13a32ae10bb6741fd..46ff7d27cac9225a98bca731e1a287dff5beb9ab 100644
--- a/arch/arm/include/lpc11xx/irq.h
+++ b/arch/arm/include/lpc11xx/irq.h
@@ -59,7 +59,7 @@
/* Common Processor Exceptions (vectors 0-15) */
-#define LPC11_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define LPC11_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define LPC11_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/lpc17xx/irq.h b/arch/arm/include/lpc17xx/irq.h
index 6af683225ca64dbcad3a639e1f64714018f68976..99bffe17ebbd38510bc10b734fcd1623d480e010 100644
--- a/arch/arm/include/lpc17xx/irq.h
+++ b/arch/arm/include/lpc17xx/irq.h
@@ -59,7 +59,7 @@
/* Common Processor Exceptions (vectors 0-15) */
-#define LPC17_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define LPC17_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define LPC17_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/lpc43xx/chip.h b/arch/arm/include/lpc43xx/chip.h
index a88559df21b6055a38e815e52b0ff040b9412125..4592117de184bb059bacd774145714233b1c4e17 100644
--- a/arch/arm/include/lpc43xx/chip.h
+++ b/arch/arm/include/lpc43xx/chip.h
@@ -322,8 +322,8 @@
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4337JBD144)
-# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
-# define LPC43_FLASH_BANKB_SIZE (512*1025)
+# define LPC43_FLASH_BANKA_SIZE (512*1024) /* 1024Kb FLASH */
+# define LPC43_FLASH_BANKB_SIZE (512*1024)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
@@ -426,8 +426,8 @@
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4353FBD208)
-# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
-# define LPC43_FLASH_BANKB_SIZE (256*1025)
+# define LPC43_FLASH_BANKA_SIZE (256*1024) /* 512Kb FLASH */
+# define LPC43_FLASH_BANKB_SIZE (256*1024)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
@@ -452,8 +452,8 @@
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4353FET180)
-# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
-# define LPC43_FLASH_BANKB_SIZE (256*1025)
+# define LPC43_FLASH_BANKA_SIZE (256*1024) /* 512Kb FLASH */
+# define LPC43_FLASH_BANKB_SIZE (256*1024)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
@@ -478,8 +478,8 @@
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4353FET256)
-# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
-# define LPC43_FLASH_BANKB_SIZE (256*1025)
+# define LPC43_FLASH_BANKA_SIZE (256*1024) /* 512Kb FLASH */
+# define LPC43_FLASH_BANKB_SIZE (256*1024)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
@@ -504,8 +504,8 @@
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4357FET180)
-# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
-# define LPC43_FLASH_BANKB_SIZE (512*1025)
+# define LPC43_FLASH_BANKA_SIZE (512*1024) /* 1024Kb FLASH */
+# define LPC43_FLASH_BANKB_SIZE (512*1024)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
@@ -530,8 +530,8 @@
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4357FBD208)
-# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
-# define LPC43_FLASH_BANKB_SIZE (512*1025)
+# define LPC43_FLASH_BANKA_SIZE (512*1024) /* 1024Kb FLASH */
+# define LPC43_FLASH_BANKB_SIZE (512*1024)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
@@ -556,8 +556,8 @@
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4357FET256)
-# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
-# define LPC43_FLASH_BANKB_SIZE (512*1025)
+# define LPC43_FLASH_BANKA_SIZE (512*1024) /* 1024Kb FLASH */
+# define LPC43_FLASH_BANKB_SIZE (512*1024)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
diff --git a/arch/arm/include/lpc43xx/irq.h b/arch/arm/include/lpc43xx/irq.h
index 9b103e97185005d00d3e254fee0d6ca03ccf3fce..dd9790ab10774093de24bfce479ecf4ee39f4103 100644
--- a/arch/arm/include/lpc43xx/irq.h
+++ b/arch/arm/include/lpc43xx/irq.h
@@ -59,7 +59,7 @@
/* Processor Exceptions (vectors 0-15) */
-#define LPC43_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define LPC43_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define LPC43_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/nuc1xx/irq.h b/arch/arm/include/nuc1xx/irq.h
index 0db0379d1b4b4360b1ba4fe68491c546afcdf1d5..26b0d8125f510f055abdc400f8e08a8e66e52a44 100644
--- a/arch/arm/include/nuc1xx/irq.h
+++ b/arch/arm/include/nuc1xx/irq.h
@@ -58,7 +58,7 @@
/* Processor Exceptions (vectors 0-15) */
-#define NUC_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define NUC_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define NUC_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/sam34/irq.h b/arch/arm/include/sam34/irq.h
index 521cd5a93cd71b10d8f5076fb8283a0bd4fbc423..a0f5de604f78b1455b2e72f10108a31f4c8efd42 100644
--- a/arch/arm/include/sam34/irq.h
+++ b/arch/arm/include/sam34/irq.h
@@ -58,7 +58,7 @@
/* Common Processor Exceptions (vectors 0-15) */
-#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define SAM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/samdl/irq.h b/arch/arm/include/samdl/irq.h
index d74584fb298cc557b03dfe5dfb2804d0a811152c..7da8c7b21e6282b70b4645c57fb806645ef07fc2 100644
--- a/arch/arm/include/samdl/irq.h
+++ b/arch/arm/include/samdl/irq.h
@@ -58,7 +58,7 @@
/* Processor Exceptions (vectors 0-15) */
-#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define SAM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/samv7/irq.h b/arch/arm/include/samv7/irq.h
index 4c33f3dbec0bb4b61b846958c7226f274b549b84..eec3d12e054038332fe20043930130db88ed1820 100644
--- a/arch/arm/include/samv7/irq.h
+++ b/arch/arm/include/samv7/irq.h
@@ -58,7 +58,7 @@
/* Common Processor Exceptions (vectors 0-15) */
-#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define SAM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h
index 98d0073c50617e9ab25a7cb6ddf2e99f0ffb3586..e476bff892e5eaa37ba673c01d64096eb2359b22 100644
--- a/arch/arm/include/stm32/chip.h
+++ b/arch/arm/include/stm32/chip.h
@@ -903,6 +903,43 @@
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
+#elif defined(CONFIG_ARCH_CHIP_STM32F105RB)
+# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
+# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
+# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
+# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
+# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
+# undef CONFIG_STM32_VALUELINE /* STM32F100x */
+# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
+# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
+# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
+# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
+# define STM32_NFSMC 1 /* FSMC */
+# define STM32_NATIM 1 /* One advanced timers TIM1 */
+# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
+# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
+# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define STM32_NDMA 2 /* DMA1-2 */
+# define STM32_NSPI 3 /* SPI1-3 */
+# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define STM32_NUSART 5 /* USART1-3, UART 4-5 */
+# define STM32_NI2C 2 /* I2C1-2 */
+# define STM32_NCAN 2 /* CAN1-2 */
+# define STM32_NSDIO 0 /* No SDIO */
+# define STM32_NLCD 0 /* No LCD */
+# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
+# define STM32_NGPIO 51 /* GPIOA-E */
+# define STM32_NADC 2 /* ADC1-2 */
+# define STM32_NDAC 2 /* DAC1-2 */
+# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define STM32_NCRC 1 /* CRC */
+# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */
+# define STM32_NRNG 0 /* No random number generator (RNG) */
+# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
+
#elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
@@ -2430,7 +2467,7 @@
# if defined(CONFIG_ARCH_CHIP_STM32F469A)
# define STM32_NETHERNET 0 /* No Ethernet MAC */
# elif defined(CONFIG_ARCH_CHIP_STM32F469I) || \
-# defined(CONFIG_ARCH_CHIP_STM32F469B) || \
+ defined(CONFIG_ARCH_CHIP_STM32F469B) || \
defined(CONFIG_ARCH_CHIP_STM32F469N)
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# endif
diff --git a/arch/arm/include/stm32/irq.h b/arch/arm/include/stm32/irq.h
index 1d57bc3e500147c86db55809a6c4cad1aca92c5e..2c9b188f0258348928741b88bba8f1a61546d46a 100644
--- a/arch/arm/include/stm32/irq.h
+++ b/arch/arm/include/stm32/irq.h
@@ -59,7 +59,7 @@
/* Processor Exceptions (vectors 0-15) */
-#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/stm32/stm32f10xxx_irq.h b/arch/arm/include/stm32/stm32f10xxx_irq.h
index 29f07b0fd8837e37be3182765bbe25130ef752e3..beed4952541de0e89a5f46c27ed19cb22ec47ba7 100644
--- a/arch/arm/include/stm32/stm32f10xxx_irq.h
+++ b/arch/arm/include/stm32/stm32f10xxx_irq.h
@@ -199,7 +199,7 @@
# define STM32_IRQ_ETH (77) /* 61: Ethernet global interrupt */
# define STM32_IRQ_ETHWKUP (78) /* 62: Ethernet Wakeup through EXTI line interrupt */
# define STM32_IRQ_CAN2TX (79) /* 63: CAN2 TX interrupts */
-# define STM32_IRQ_CAN2RX0 (70) /* 64: CAN2 RX0 interrupts */
+# define STM32_IRQ_CAN2RX0 (80) /* 64: CAN2 RX0 interrupts */
# define STM32_IRQ_CAN2RX1 (81) /* 65: CAN2 RX1 interrupt */
# define STM32_IRQ_CAN2SCE (82) /* 66: CAN2 SCE interrupt */
# define STM32_IRQ_OTGFS (83) /* 67: USB On The Go FS global interrupt */
diff --git a/arch/arm/include/stm32f7/chip.h b/arch/arm/include/stm32f7/chip.h
index 372bd1143f4529271932312ce75e3bd89919a2f8..b3beb4e09e8697413a363f70b74df38caed19bb9 100644
--- a/arch/arm/include/stm32f7/chip.h
+++ b/arch/arm/include/stm32f7/chip.h
@@ -1,8 +1,9 @@
/************************************************************************************
* arch/arm/include/stm32f7/chip.h
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
+ * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ * David Sidrane
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -45,99 +46,272 @@
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
-/* STM32F745xx, STM32F746xx, and STM32F56xx. Differences between family members:
- *
- * ----------- ---------------- ----- -------- ------------ --------
- * PART PACKAGE GPIOs SPI/I2S ADC CHANNELS LCD-TFT?
- * ----------- ---------------- ----- -------- ------------ --------
- * STM32F745Vx LQFP100 82 4/3 16 No
- * STM32F745Zx WLCSP143/LQFP144 114 6/3 24 No
- * STM32F745Ix UFBGA176/LQFP176 140 6/3 24 No
- * STM32F745Bx LQFP208 168 6/3 24 No
- * STM32F745Nx TFBGA216 68 6/3 24 No
- *
- * STM32F746Vx LQFP100 82 4/3 16 Yes
- * STM32F746Zx WLCSP143/LQFP144 114 6/3 24 Yes
- * STM32F746Ix UFBGA176/LQFP176 140 6/3 24 Yes
- * STM32F746Bx LQFP208 168 6/3 24 Yes
- * STM32F746Nx TFBGA216 168 6/3 24 Yes
- *
- * STM32F756Vx LQFP100 82 4/3 16 Yes
- * STM32F756Zx WLCSP143/LQFP144 114 6/3 24 Yes
- * STM32F756Ix UFBGA176/LQFP176 140 6/3 24 Yes
- * STM32F756Bx LQFP208 168 6/3 24 Yes
- * STM32F756Nx TFBGA216 168 6/3 24 Yes
- * ----------- ---------------- ----- -------- ------------ --------
+/* STM32F745xx, STM32F746xx, STM32F756xx, STM32F765xx, STM32F767xx, STM32F768xx,
+ * STM32F769xx, STM32F777xx and STM32F779xx Differences between family members:
+ *
+ * ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
+ * SPI ADC LCD
+ * PART PACKAGE GPIOs I2S CHAN TFT MIPI JPEG CAN ETH DFSDM CRYPTO FPU RAM L1
+ * ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
+ * STM32F745Vx LQFP100 82 4/3 16 No No No 2 Yes No No SFPU (240+16+64) 4+4
+ * STM32F745Zx WLCSP143/LQFP144 114 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
+ * STM32F745Ix UFBGA176/LQFP176 140 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
+ * STM32F745Bx LQFP208 168 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
+ * STM32F745Nx TFBGA216 68 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
+ *
+ * STM32F746Vx LQFP100 82 4/3 16 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
+ * STM32F746Zx WLCSP143/LQFP144 114 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
+ * STM32F746Ix UFBGA176/LQFP176 140 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
+ * STM32F746Bx LQFP208 168 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
+ * STM32F746Nx TFBGA216 168 6/3 24 Yes No No 2 Yes No No SFPU
+ *
+ * STM32F756Vx LQFP100 82 4/3 16 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
+ * STM32F756Zx WLCSP143/LQFP144 114 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
+ * STM32F756Ix UFBGA176/LQFP176 140 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
+ * STM32F756Bx LQFP208 168 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
+ * STM32F756Nx TFBGA216 168 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
+ *
+ * STM32F765Vx LQFP100 82 4/3 16 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F765Zx WLCSP143/LQFP144 114 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F765Ix UFBGA176/LQFP176 140 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F765Bx LQFP208 168 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F765Nx TFBGA216 168 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
+ *
+ * STM32F767Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F767Zx WLCSP143/LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F767Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F767Bx LQFP208 168 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F767Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ *
+ * STM32F768Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes No DFPU (368+16+128) 16+16
+ *
+ * STM32F769Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F769Zx LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F769Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F769Bx LQFP208 168 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F769Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ *
+ * STM32F769Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes No DFPU (368+16+128) 16+16
+ *
+ * STM32F777Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
+ * STM32F777Zx LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
+ * STM32F777Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
+ * STM32F777Bx LQFP208 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
+ * STM32F777Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
+ *
+ * STM32F778Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes Yes DFPU (368+16+128) 16+16
+ *
+ * STM32F779Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
+ * STM32F779Bx LQFP208 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
+ * STM32F779Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
+
+ * STM32F779Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes Yes DFPU (368+16+128) 16+16
+ * ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
*
* Parts STM32F74xxE have 512Kb of FLASH
* Parts STM32F74xxG have 1024Kb of FLASH
+ * Parts STM32F74xxI have 2048Kb of FLASH
+ *
+ * The correct FLASH size will be set CONFIG_STM32F7_FLASH_CONFIG_x or overridden
+ * with CONFIG_STM32F7_FLASH_OVERRIDE_x
*
- * The correct FLASH size must be set with a CONFIG_STM32F7_FLASH_*KB
- * selection.
*/
+#if defined(CONFIG_ARCH_CHIP_STM32F745VG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F745VE) || \
+ defined(CONFIG_ARCH_CHIP_STM32F745IG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F745IE) || \
+ defined(CONFIG_ARCH_CHIP_STM32F745ZE) || \
+ defined(CONFIG_ARCH_CHIP_STM32F745ZG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746BG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746VG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746VE) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746BE) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746ZG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746IE) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746NG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746NE) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746ZE) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746IG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F756NG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F756BG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F756IG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F756VG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F756ZG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765NI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765VI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765VG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765BI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765NG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765ZG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765ZI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765IG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765BG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765II) || \
+ defined(CONFIG_ARCH_CHIP_STM32F767NG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F767IG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F767VG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F767ZG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F767NI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F767VI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F767BG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F767ZI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F767II) || \
+ defined(CONFIG_ARCH_CHIP_STM32F769BI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F769II) || \
+ defined(CONFIG_ARCH_CHIP_STM32F769BG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F769NI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F769AI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F769NG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F769IG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F777ZI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F777VI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F777NI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F777BI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F777II) || \
+ defined(CONFIG_ARCH_CHIP_STM32F778AI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F779II) || \
+ defined(CONFIG_ARCH_CHIP_STM32F779NI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F779BI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F779AI)
+#else
+# error STM32 F7 chip not identified
+#endif
-#if defined(CONFIG_ARCH_CHIP_STM32F745) || defined(CONFIG_ARCH_CHIP_STM32F746) || \
- defined(CONFIG_ARCH_CHIP_STM32F756)
-
-#if defined(CONFIG_ARCH_CHIP_STM32F745)
-# define STM32F7_STM32F745XX 1 /* STM32F745xx family */
-# undef STM32F7_STM32F746XX /* Not STM32F746xx family */
-# undef STM32F7_STM32F756XX /* Not STM32F756xx family */
-
-# define STM32F7_NLCDTFT 0 /* No LCD-TFT */
-
-#elif defined(CONFIG_ARCH_CHIP_STM32F746)
-
-# undef STM32F7_STM32F745XX /* Not STM32F745xx family */
-# define STM32F7_STM32F746XX 1 /* STM32F746xx family */
-# undef STM32F7_STM32F756XX /* Not STM32F756xx family */
-
-# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
-
-#else /* if defined(CONFIG_ARCH_CHIP_STM32F746) */
-
-# undef STM32F7_STM32F745XX /* Not STM32F745xx family */
-# undef STM32F7_STM32F746XX /* Not STM32F746xx family */
-# define STM32F7_STM32F756XX 1 /* STM32F756xx family */
+/* Size SRAM */
-# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
+#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
+# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */
+# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
+# if defined(CONFIG_ARMV7M_HAVE_DTCM)
+# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */
+# else
+# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
+# endif
+# if defined(CONFIG_ARMV7M_HAVE_ITCM)
+# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */
+# else
+# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
+# endif
+#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77X)
+# define STM32F7_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */
+# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
+# if defined(CONFIG_ARMV7M_HAVE_DTCM)
+# define STM32F7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */
+# else
+# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
+# endif
+# if defined(CONFIG_ARMV7M_HAVE_ITCM)
+# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */
+# else
+# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
+# endif
+#else
+# error STM32 F7 chip Family not identified
#endif
-# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */
-# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
-# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM inerface */
-# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM inerface */
+/* Common to all Family members */
-# define STM32F7_NFSMC 1 /* Have FSMC memory controller */
-# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32F7_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32F7_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
# define STM32F7_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
# define STM32F7_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define STM32F7_NBTIM 2 /* Two basic timers, TIM6-7 */
-# define STM32F7_NRNG 1 /* Random number generator (RNG) */
# define STM32F7_NUART 4 /* UART 4-5 and 7-8 */
# define STM32F7_NUSART 4 /* USART1-3 and 6 */
-# define STM32F7_NSPI 6 /* SPI1-6 (Except V series) */
# define STM32F7_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */
# define STM32F7_NI2C 4 /* I2C1-4 */
# define STM32F7_NUSBOTGFS 1 /* USB OTG FS */
# define STM32F7_NUSBOTGHS 1 /* USB OTG HS */
-# define STM32F7_NCAN 2 /* CAN1-2 */
# define STM32F7_NSAI 2 /* SAI1-2 */
# define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */
-# define STM32F7_NSDMMC 1 /* SDMMC interface */
-# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */
# define STM32F7_NDMA 2 /* DMA1-2 */
-# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */
# define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */
# define STM32F7_NADC 3 /* 12-bit ADC1-3, 24 channels *except V series) */
# define STM32F7_NDAC 2 /* 12-bit DAC1-2 */
# define STM32F7_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32F7_NCRC 1 /* CRC */
+/* TBD FPU Configuration */
+
+#if defined(CONFIG_ARCH_HAVE_FPU)
#else
-# error STM32 F7 chip not identified
+#endif
+
+#if defined(CONFIG_ARCH_HAVE_DPFPU)
+#else
+#endif
+
+/* Diversification based on Family and package */
+
+#if defined(CONFIG_STM32F7_HAVE_FSMC)
+# define STM32F7_NFSMC 1 /* Have FSMC memory controller */
+#else
+# define STM32F7_NFSMC 0 /* No FSMC memory controller */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_ETHRNET)
+# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */
+#else
+# define STM32F7_NETHERNET 0 /* No 100/100 Ethernet MAC */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_RNG)
+# define STM32F7_NRNG 1 /* Random number generator (RNG) */
+#else
+# define STM32F7_NRNG 0 /* No Random number generator (RNG) */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_SPI5) && defined(CONFIG_STM32F7_HAVE_SPI6)
+# define STM32F7_NSPI 6 /* SPI1-6 (Except V series) */
+#else
+# define STM32F7_NSPI 4 /* SPI1-4 V series */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_SDMMC2)
+# define STM32F7_NSDMMC 2 /* 2 SDMMC interfaces */
+#else
+# define STM32F7_NSDMMC 1 /* 1 SDMMC interface */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_CAN3)
+# define STM32F7_NCAN 3 /* CAN1-3 */
+#else
+# define STM32F7_NCAN 2 /* CAN1-2 */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_DCMI)
+# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */
+#else
+# define STM32F7_NDCMI 0 /* No Digital camera interface (DCMI) */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_DSIHOST)
+# define STM32F7_NDSIHOST 1 /* Have MIPI DSI Host */
+#else
+# define STM32F7_NDSIHOST 0 /* No MIPI DSI Host */
+#endif
+#if defined (CONFIG_STM32F7_HAVE_LTDC)
+# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
+#else
+# define STM32F7_NLCDTFT 0 /* No LCD-TFT */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_DMA2D)
+# define STM32F7_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */
+#else
+# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_JPEG)
+#define STM32F7_NJPEG 1 /* One JPEG Converter */
+#else
+#define STM32F7_NJPEG 0 /* No JPEG Converter */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_CRYP)
+#define STM32F7_NCRYP 1 /* One CRYP engine */
+#else
+#define STM32F7_NCRYP 0 /* No CRYP engine */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_HASH)
+#define STM32F7_NHASH 1 /* One HASH engine */
+#else
+#define STM32F7_NHASH 0 /* No HASH engine */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_DFSDM)
+#define STM32F7_NDFSDM 4 /* One set of 4 Digital filters */
+#else
+#define STM32F7_NDFSDM 0 /* No Digital filters */
#endif
/* NVIC priority levels *************************************************************/
diff --git a/arch/arm/include/stm32f7/irq.h b/arch/arm/include/stm32f7/irq.h
index 5a5c710803668cca2b371ceaca5c60d89b510c5a..f09659190b74a2f4078b0c0df1f5f31cbcfe2389 100644
--- a/arch/arm/include/stm32f7/irq.h
+++ b/arch/arm/include/stm32f7/irq.h
@@ -57,7 +57,7 @@
/* Processor Exceptions (vectors 0-15) */
-#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
@@ -78,6 +78,8 @@
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# include
+#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+# include
#else
# error "Unsupported STM32 F7 chip"
#endif
diff --git a/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h b/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h
new file mode 100644
index 0000000000000000000000000000000000000000..6c0461f9ef22bb07ef8381ebdcb1cc86c28eaee8
--- /dev/null
+++ b/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h
@@ -0,0 +1,215 @@
+/****************************************************************************************************
+ * arch/arm/include/stm32f7/stm32f76xx77xx_irq.h.h
+ *
+ * Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ * David Sidrane
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly through arch/irq.h */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to bits in the
+ * NVIC. This does, however, waste several words of memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15). These common definitions can be found in the file
+ * nuttx/arch/arm/include/stm32f7/irq.h which includes this file
+ *
+ * External interrupts (vectors >= 16)
+ */
+
+#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
+#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
+#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
+#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
+#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
+#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
+#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
+#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
+#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
+#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
+#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
+#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
+#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
+#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
+#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
+#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
+#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
+#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
+#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
+#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
+#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
+#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
+#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
+#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
+#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
+#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
+#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
+#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
+#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
+#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
+#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
+#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
+#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
+#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
+#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
+#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
+#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
+#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
+#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
+#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
+#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
+#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
+#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
+#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
+#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
+#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
+#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
+#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
+#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
+#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
+#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
+#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
+#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
+#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
+#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
+#define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */
+#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */
+#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
+#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
+#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
+#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
+#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
+#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
+#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
+#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
+#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
+#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
+#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
+#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
+#define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */
+#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */
+#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
+#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
+#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
+#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
+#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
+#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
+#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
+#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
+#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
+#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
+#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
+#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
+#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
+#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
+#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
+#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */
+#define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */
+#define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
+#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
+#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
+#define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 global interrupt */
+#define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 global interrupt */
+#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */
+#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 global interrupt */
+#define STM32_IRQ_SPI6 (STM32_IRQ_FIRST+86) /* 86: SPI6 global interrupt */
+#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 global interrupt */
+#define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST+88) /* 88: LCD-TFT global interrupt */
+#define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST+89) /* 89: LCD-TFT global Error interrupt */
+#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST+90) /* 90: DMA2D global interrupt */
+#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 global interrupt */
+#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI global interrupt */
+#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST+93) /* 93: LP Timer1 global interrupt */
+#define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+94) /* 94: HDMI-CEC global interrupt */
+#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST+95) /* 95: I2C4 event interrupt */
+#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST+96) /* 96: I2C4 Error interrupt */
+#define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+97) /* 97: SPDIFRX global interrupt */
+#define STM32_IRQ_DSIHOST (STM32_IRQ_FIRST+98) /* 98: DSI host global interrupt */
+#define STM32_IRQ_DFSDM1FLT0 (STM32_IRQ_FIRST+99) /* 99: DFSDM1 Filter 0 global interrupt */
+#define STM32_IRQ_DFSDM1FLT1 (STM32_IRQ_FIRST+100) /* 100: DFSDM1 Filter 1 global interrupt */
+#define STM32_IRQ_DFSDM1FLT2 (STM32_IRQ_FIRST+101) /* 101: DFSDM1 Filter 2 global interrupt */
+#define STM32_IRQ_DFSDM1FLT3 (STM32_IRQ_FIRST+102) /* 102: DFSDM1 Filter 3 global interrupt */
+#define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST+103) /* 103: SDMMC2 global interrupt */
+#define STM32_IRQ_CAN3TX (STM32_IRQ_FIRST+104) /* 104: CAN3 TX interrupt */
+#define STM32_IRQ_CAN3RX0 (STM32_IRQ_FIRST+105) /* 105: CAN3 RX0 interrupt */
+#define STM32_IRQ_CAN3RX1 (STM32_IRQ_FIRST+106) /* 106: CAN3 RX1 interrupt */
+#define STM32_IRQ_CAN3SCE (STM32_IRQ_FIRST+107) /* 107: CAN3 SCE interrupt */
+#define STM32_IRQ_JPEG (STM32_IRQ_FIRST+108) /* 108: JPEG global interrupt */
+#define STM32_IRQ_MDIOS (STM32_IRQ_FIRST+109) /* 109: MDIO slave global interrupt */
+
+#define NR_INTERRUPTS 110
+#define NR_VECTORS (STM32_IRQ_FIRST+NR_INTERRUPTS)
+
+/* EXTI interrupts (Do not use IRQ numbers) */
+
+#define NR_IRQS NR_VECTORS
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H */
diff --git a/arch/arm/include/stm32l4/irq.h b/arch/arm/include/stm32l4/irq.h
index ebfb22667891d9084a91b3b87ee0afed7db0a55f..89e74c1760bedd01330ff9062de2016f0542782f 100644
--- a/arch/arm/include/stm32l4/irq.h
+++ b/arch/arm/include/stm32l4/irq.h
@@ -57,7 +57,7 @@
/* Processor Exceptions (vectors 0-15) */
-#define STM32L4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define STM32L4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32L4_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/tiva/irq.h b/arch/arm/include/tiva/irq.h
index 17c73a254de4d8f121593187ba0b4c62fad42a41..d6a3216da96da623e67e666ee3a606e9b7ea630b 100644
--- a/arch/arm/include/tiva/irq.h
+++ b/arch/arm/include/tiva/irq.h
@@ -162,7 +162,7 @@
/* Processor Exceptions (vectors 0-15) */
-#define TIVA_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define TIVA_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define TIVA_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/src/a1x/a1x_irq.c b/arch/arm/src/a1x/a1x_irq.c
index 65e18ffd73bb5b9e53291d548221da072f50368f..ecabb5ff4d66b77df5f7bab603d6866da245a18f 100644
--- a/arch/arm/src/a1x/a1x_irq.c
+++ b/arch/arm/src/a1x/a1x_irq.c
@@ -77,7 +77,7 @@ volatile uint32_t *g_current_regs[1];
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_IRQ)
+#if defined(CONFIG_DEBUG_IRQ_INFO)
static void a1x_dumpintc(const char *msg, int irq)
{
irqstate_t flags;
@@ -85,40 +85,42 @@ static void a1x_dumpintc(const char *msg, int irq)
/* Dump some relevant ARMv7 register contents */
flags = enter_critical_section();
- lldbg("ARMv7 (%s, irq=%d):\n", msg, irq);
- lldbg(" CPSR: %08x SCTLR: %08x\n", flags, cp15_rdsctlr());
+
+ irqinfo("ARMv7 (%s, irq=%d):\n", msg, irq);
+ irqinfo(" CPSR: %08x SCTLR: %08x\n", flags, cp15_rdsctlr());
/* Dump all of the (readable) INTC register contents */
- lldbg("INTC (%s, irq=%d):\n", msg, irq);
- lldbg(" VECTOR: %08x BASE: %08x PROTECT: %08x NMICTRL: %08x\n",
- getreg32(A1X_INTC_VECTOR), getreg32(A1X_INTC_BASEADDR),
- getreg32(A1X_INTC_PROTECT), getreg32(A1X_INTC_NMICTRL));
- lldbg(" IRQ PEND: %08x %08x %08x\n",
- getreg32(A1X_INTC_IRQ_PEND0), getreg32(A1X_INTC_IRQ_PEND1),
- getreg32(A1X_INTC_IRQ_PEND2));
- lldbg(" FIQ PEND: %08x %08x %08x\n",
- getreg32(A1X_INTC_FIQ_PEND0), getreg32(A1X_INTC_FIQ_PEND1),
- getreg32(A1X_INTC_FIQ_PEND2));
- lldbg(" SEL: %08x %08x %08x\n",
- getreg32(A1X_INTC_IRQ_SEL0), getreg32(A1X_INTC_IRQ_SEL1),
- getreg32(A1X_INTC_IRQ_SEL2));
- lldbg(" EN: %08x %08x %08x\n",
- getreg32(A1X_INTC_EN0), getreg32(A1X_INTC_EN1),
- getreg32(A1X_INTC_EN2));
- lldbg(" MASK: %08x %08x %08x\n",
- getreg32(A1X_INTC_MASK0), getreg32(A1X_INTC_MASK1),
- getreg32(A1X_INTC_MASK2));
- lldbg(" RESP: %08x %08x %08x\n",
- getreg32(A1X_INTC_RESP0), getreg32(A1X_INTC_RESP1),
- getreg32(A1X_INTC_RESP2));
- lldbg(" FF: %08x %08x %08x\n",
- getreg32(A1X_INTC_FF0), getreg32(A1X_INTC_FF1),
- getreg32(A1X_INTC_FF2));
- lldbg(" PRIO: %08x %08x %08x %08x %08x\n",
- getreg32(A1X_INTC_PRIO0), getreg32(A1X_INTC_PRIO1),
- getreg32(A1X_INTC_PRIO2), getreg32(A1X_INTC_PRIO3),
- getreg32(A1X_INTC_PRIO4));
+ irqinfo("INTC (%s, irq=%d):\n", msg, irq);
+ irqinfo(" VECTOR: %08x BASE: %08x PROTECT: %08x NMICTRL: %08x\n",
+ getreg32(A1X_INTC_VECTOR), getreg32(A1X_INTC_BASEADDR),
+ getreg32(A1X_INTC_PROTECT), getreg32(A1X_INTC_NMICTRL));
+ irqinfo(" IRQ PEND: %08x %08x %08x\n",
+ getreg32(A1X_INTC_IRQ_PEND0), getreg32(A1X_INTC_IRQ_PEND1),
+ getreg32(A1X_INTC_IRQ_PEND2));
+ irqinfo(" FIQ PEND: %08x %08x %08x\n",
+ getreg32(A1X_INTC_FIQ_PEND0), getreg32(A1X_INTC_FIQ_PEND1),
+ getreg32(A1X_INTC_FIQ_PEND2));
+ irqinfo(" SEL: %08x %08x %08x\n",
+ getreg32(A1X_INTC_IRQ_SEL0), getreg32(A1X_INTC_IRQ_SEL1),
+ getreg32(A1X_INTC_IRQ_SEL2));
+ irqinfo(" EN: %08x %08x %08x\n",
+ getreg32(A1X_INTC_EN0), getreg32(A1X_INTC_EN1),
+ getreg32(A1X_INTC_EN2));
+ irqinfo(" MASK: %08x %08x %08x\n",
+ getreg32(A1X_INTC_MASK0), getreg32(A1X_INTC_MASK1),
+ getreg32(A1X_INTC_MASK2));
+ irqinfo(" RESP: %08x %08x %08x\n",
+ getreg32(A1X_INTC_RESP0), getreg32(A1X_INTC_RESP1),
+ getreg32(A1X_INTC_RESP2));
+ irqinfo(" FF: %08x %08x %08x\n",
+ getreg32(A1X_INTC_FF0), getreg32(A1X_INTC_FF1),
+ getreg32(A1X_INTC_FF2));
+ irqinfo(" PRIO: %08x %08x %08x %08x %08x\n",
+ getreg32(A1X_INTC_PRIO0), getreg32(A1X_INTC_PRIO1),
+ getreg32(A1X_INTC_PRIO2), getreg32(A1X_INTC_PRIO3),
+ getreg32(A1X_INTC_PRIO4));
+
leave_critical_section(flags);
}
#else
diff --git a/arch/arm/src/a1x/a1x_serial.c b/arch/arm/src/a1x/a1x_serial.c
index b6e536fdc601ecc0f79ec321a8eeb0f09258f4d4..7dae40aa997d827feaba429f65fb27fef106f7cb 100644
--- a/arch/arm/src/a1x/a1x_serial.c
+++ b/arch/arm/src/a1x/a1x_serial.c
@@ -1156,7 +1156,7 @@ static int uart_interrupt(struct uart_dev_s *dev)
/* Read the modem status register (MSR) to clear */
status = up_serialin(priv, A1X_UART_MSR_OFFSET);
- vdbg("MSR: %02x\n", status);
+ _info("MSR: %02x\n", status);
break;
}
@@ -1167,7 +1167,7 @@ static int uart_interrupt(struct uart_dev_s *dev)
/* Read the line status register (LSR) to clear */
status = up_serialin(priv, A1X_UART_LSR_OFFSET);
- vdbg("LSR: %02x\n", status);
+ _info("LSR: %02x\n", status);
break;
}
@@ -1192,7 +1192,7 @@ static int uart_interrupt(struct uart_dev_s *dev)
default:
{
- lldbg("Unexpected IIR: %02x\n", status);
+ _err("ERROR: Unexpected IIR: %02x\n", status);
break;
}
}
diff --git a/arch/arm/src/arm/up_assert.c b/arch/arm/src/arm/up_assert.c
index 336a76c8613862c4bcea2c7b559eb727c947360e..3d188174b3d3ea661b7d508ef738cbef6fb73761 100644
--- a/arch/arm/src/arm/up_assert.c
+++ b/arch/arm/src/arm/up_assert.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/arm/up_assert.c
*
- * Copyright (C) 2007-2010, 2012-2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2007-2010, 2012-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -77,23 +66,6 @@
# undef CONFIG_ARCH_USBDUMP
#endif
-/* The following is just intended to keep some ugliness out of the mainline
- * code. We are going to print the task name if:
- *
- * CONFIG_TASK_NAME_SIZE > 0 && <-- The task has a name
- * (defined(CONFIG_DEBUG) || <-- And the debug is enabled (lldbg used)
- * defined(CONFIG_ARCH_STACKDUMP) <-- Or lowsyslog() is used
- */
-
-#undef CONFIG_PRINT_TASKNAME
-#if CONFIG_TASK_NAME_SIZE > 0 && (defined(CONFIG_DEBUG) || defined(CONFIG_ARCH_STACKDUMP))
-# define CONFIG_PRINT_TASKNAME 1
-#endif
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -127,7 +99,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base)
for (stack = sp & ~0x1f; stack < stack_base; stack += 32)
{
uint32_t *ptr = (uint32_t *)stack;
- lldbg("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
stack, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
@@ -154,12 +126,12 @@ static inline void up_registerdump(void)
for (regs = REG_R0; regs <= REG_R15; regs += 8)
{
uint32_t *ptr = (uint32_t *)&CURRENT_REGS[regs];
- lldbg("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
- lldbg("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]);
+ _alert("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]);
}
}
#else
@@ -179,7 +151,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
/* Let vsyslog do the real work */
va_start(ap, fmt);
- ret = lowvsyslog(LOG_INFO, fmt, ap);
+ ret = vsyslog(LOG_EMERG, fmt, ap);
va_end(ap);
return ret;
}
@@ -228,12 +200,12 @@ static void up_dumpstate(void)
/* Show interrupt stack info */
- lldbg("sp: %08x\n", sp);
- lldbg("IRQ stack:\n");
- lldbg(" base: %08x\n", istackbase);
- lldbg(" size: %08x\n", istacksize);
+ _alert("sp: %08x\n", sp);
+ _alert("IRQ stack:\n");
+ _alert(" base: %08x\n", istackbase);
+ _alert(" size: %08x\n", istacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_intstack());
+ _alert(" used: %08x\n", up_check_intstack());
#endif
/* Does the current stack pointer lie within the interrupt
@@ -251,24 +223,24 @@ static void up_dumpstate(void)
*/
sp = g_intstackbase;
- lldbg("sp: %08x\n", sp);
+ _alert("sp: %08x\n", sp);
}
/* Show user stack info */
- lldbg("User stack:\n");
- lldbg(" base: %08x\n", ustackbase);
- lldbg(" size: %08x\n", ustacksize);
+ _alert("User stack:\n");
+ _alert(" base: %08x\n", ustackbase);
+ _alert(" size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_tcbstack(rtcb));
+ _alert(" used: %08x\n", up_check_tcbstack(rtcb));
#endif
#else
- lldbg("sp: %08x\n", sp);
- lldbg("stack base: %08x\n", ustackbase);
- lldbg("stack size: %08x\n", ustacksize);
+ _alert("sp: %08x\n", sp);
+ _alert("stack base: %08x\n", ustackbase);
+ _alert("stack size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg("stack used: %08x\n", up_check_tcbstack(rtcb));
+ _alert("stack used: %08x\n", up_check_tcbstack(rtcb));
#endif
#endif
@@ -279,7 +251,7 @@ static void up_dumpstate(void)
if (sp > ustackbase || sp <= ustackbase - ustacksize)
{
#if !defined(CONFIG_ARCH_INTERRUPTSTACK) || CONFIG_ARCH_INTERRUPTSTACK < 4
- lldbg("ERROR: Stack pointer is not within allocated stack\n");
+ _alert("ERROR: Stack pointer is not within allocated stack\n");
#endif
}
else
@@ -339,17 +311,17 @@ static void _up_assert(int errorcode)
void up_assert(const uint8_t *filename, int lineno)
{
-#ifdef CONFIG_PRINT_TASKNAME
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
struct tcb_s *rtcb = this_task();
#endif
board_autoled_on(LED_ASSERTION);
-#ifdef CONFIG_PRINT_TASKNAME
- lldbg("Assertion failed at file:%s line: %d task: %s\n",
+#if CONFIG_TASK_NAME_SIZE > 0
+ _alert("Assertion failed at file:%s line: %d task: %s\n",
filename, lineno, rtcb->name);
#else
- lldbg("Assertion failed at file:%s line: %d\n",
+ _alert("Assertion failed at file:%s line: %d\n",
filename, lineno);
#endif
diff --git a/arch/arm/src/arm/up_dataabort.c b/arch/arm/src/arm/up_dataabort.c
index 2ab00b15c9403b3e349288ef734b3c48f68a37f9..318c59232c46ab0464c2a6c3be1ec2885247cdf7 100644
--- a/arch/arm/src/arm/up_dataabort.c
+++ b/arch/arm/src/arm/up_dataabort.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/arm/up_dataabort.c
*
- * Copyright (C) 2007-2011, 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2007-2011, 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
@@ -63,18 +52,6 @@
# include "arm.h"
#endif
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -112,7 +89,6 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
* for register dumps and possibly context switching.
*/
-
savestate = (uint32_t *)CURRENT_REGS;
#endif
CURRENT_REGS = regs;
@@ -131,7 +107,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
* fatal error.
*/
- pglldbg("FSR: %08x FAR: %08x\n", fsr, far);
+ pginfo("FSR: %08x FAR: %08x\n", fsr, far);
if ((fsr & FSR_MASK) != FSR_PAGE)
{
goto segfault;
@@ -142,7 +118,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
* (It has not yet been saved in the register context save area).
*/
- pgllvdbg("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
+ pginfo("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
if (far < PG_PAGED_VBASE || far >= PG_PAGED_VEND)
{
goto segfault;
@@ -180,7 +156,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
segfault:
#endif
- lldbg("Data abort. PC: %08x FAR: %08x FSR: %08x\n", regs[REG_PC], far, fsr);
+ _alert("Data abort. PC: %08x FAR: %08x FSR: %08x\n", regs[REG_PC], far, fsr);
PANIC();
}
@@ -196,7 +172,7 @@ void up_dataabort(uint32_t *regs)
/* Crash -- possibly showing diagnost debug information. */
- lldbg("Data abort. PC: %08x\n", regs[REG_PC]);
+ _alert("Data abort. PC: %08x\n", regs[REG_PC]);
PANIC();
}
diff --git a/arch/arm/src/arm/up_elf.c b/arch/arm/src/arm/up_elf.c
index 07eba7341d9a85a59703fbc936ad87510eb586c4..c6d88bdc325c8f40f57191b5c145444a90579e70 100644
--- a/arch/arm/src/arm/up_elf.c
+++ b/arch/arm/src/arm/up_elf.c
@@ -86,7 +86,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_machine != EM_ARM)
{
- bdbg("Not for ARM: e_machine=%04x\n", ehdr->e_machine);
+ berr("ERROR: Not for ARM: e_machine=%04x\n", ehdr->e_machine);
return -ENOEXEC;
}
@@ -94,7 +94,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_ident[EI_CLASS] != ELFCLASS32)
{
- bdbg("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
+ berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
return -ENOEXEC;
}
@@ -106,7 +106,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB)
#endif
{
- bdbg("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
+ berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
return -ENOEXEC;
}
@@ -114,7 +114,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if ((ehdr->e_entry & 3) != 0)
{
- bdbg("Entry point is not properly aligned: %08x\n", ehdr->e_entry);
+ berr("ERROR: Entry point is not properly aligned: %08x\n", ehdr->e_entry);
return -ENOEXEC
}
@@ -172,7 +172,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_CALL:
case R_ARM_JUMP24:
{
- bvdbg("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
+ binfo("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@@ -185,7 +185,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
offset += sym->st_value - addr;
if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000)
{
- bdbg(" ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
+ berr("ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
ELF32_R_TYPE(rel->r_info), offset);
return -EINVAL;
@@ -201,7 +201,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_ABS32:
case R_ARM_TARGET1: /* New ABI: TARGET1 always treated as ABS32 */
{
- bvdbg("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ binfo("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
*(uint32_t *)addr += sym->st_value;
@@ -210,7 +210,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_V4BX:
{
- bvdbg("Performing V4BX link at addr=%08lx [%08lx]\n",
+ binfo("Performing V4BX link at addr=%08lx [%08lx]\n",
(long)addr, (long)(*(uint32_t *)addr));
/* Preserve only Rm and the condition code */
@@ -225,7 +225,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_PREL31:
{
- bvdbg("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ binfo("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
offset = *(uint32_t *)addr + sym->st_value - addr;
@@ -236,7 +236,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_MOVW_ABS_NC:
case R_ARM_MOVT_ABS:
{
- bvdbg("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ binfo("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@@ -256,7 +256,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
break;
default:
- bdbg("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
+ berr("ERROR: Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
return -EINVAL;
}
@@ -266,6 +266,6 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
int up_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym,
uintptr_t addr)
{
- bdbg("RELA relocation not supported\n");
+ berr("ERROR: RELA relocation not supported\n");
return -ENOSYS;
}
diff --git a/arch/arm/src/arm/up_head.S b/arch/arm/src/arm/up_head.S
index 53f94a2e0faf31dd1cb2c73141c0c8c89bfa571f..da317c12f978c740dc6472bdbcdbfb19e7411b4f 100644
--- a/arch/arm/src/arm/up_head.S
+++ b/arch/arm/src/arm/up_head.S
@@ -208,7 +208,7 @@
/* This macro will modify r0, r1, r2 and r14 */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
.macro showprogress, code
mov r0, #\code
bl up_lowputc
diff --git a/arch/arm/src/arm/up_nommuhead.S b/arch/arm/src/arm/up_nommuhead.S
index 04c5205efe057ee58a52286f961e40e3a65624ad..d8689d85bd6ee0d893a2e8f7040a44422d0787ae 100644
--- a/arch/arm/src/arm/up_nommuhead.S
+++ b/arch/arm/src/arm/up_nommuhead.S
@@ -49,7 +49,7 @@
/* This macro will modify r0, r1, r2 and r14 */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
.macro showprogress, code
mov r0, #\code
bl up_lowputc
@@ -115,7 +115,7 @@ __start:
bl up_earlyserialinit
#endif
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
mov r0, #'C'
bl up_putc
mov r0, #'\n'
diff --git a/arch/arm/src/arm/up_prefetchabort.c b/arch/arm/src/arm/up_prefetchabort.c
index ed2bfb1bf9db8035dfb43915edf2ca23ad37051a..ab97efd5737264712b8b8e4b20e68e35d7ad9f00 100644
--- a/arch/arm/src/arm/up_prefetchabort.c
+++ b/arch/arm/src/arm/up_prefetchabort.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/arm/up_prefetchabort.c
*
- * Copyright (C) 2007-2011, 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2007-2011, 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
@@ -110,8 +99,8 @@ void up_prefetchabort(uint32_t *regs)
* virtual addresses.
*/
- pglldbg("VADDR: %08x VBASE: %08x VEND: %08x\n",
- regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
+ pginfo("VADDR: %08x VBASE: %08x VEND: %08x\n",
+ regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
if (regs[REG_R15] >= PG_PAGED_VBASE && regs[REG_R15] < PG_PAGED_VEND)
{
@@ -148,7 +137,7 @@ void up_prefetchabort(uint32_t *regs)
else
#endif
{
- lldbg("Prefetch abort. PC: %08x\n", regs[REG_PC]);
+ _alert("Prefetch abort. PC: %08x\n", regs[REG_PC]);
PANIC();
}
}
diff --git a/arch/arm/src/arm/up_releasepending.c b/arch/arm/src/arm/up_releasepending.c
index 4defb895e00e0398df6d95c135f521300e313211..c0ee7e6e727051e418f6e8638db3f8e9cbafe3ef 100644
--- a/arch/arm/src/arm/up_releasepending.c
+++ b/arch/arm/src/arm/up_releasepending.c
@@ -67,7 +67,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
- slldbg("From TCB=%p\n", rtcb);
+ sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */
diff --git a/arch/arm/src/arm/up_reprioritizertr.c b/arch/arm/src/arm/up_reprioritizertr.c
index 8f6b739d08dc5cb7265c9234dcc93cb9b1faebe1..95679e31dd7276d9b11c1c24d8a8dfa25e7c1e1c 100644
--- a/arch/arm/src/arm/up_reprioritizertr.c
+++ b/arch/arm/src/arm/up_reprioritizertr.c
@@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
- slldbg("TCB=%p PRI=%d\n", tcb, priority);
+ sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just
diff --git a/arch/arm/src/arm/up_schedulesigaction.c b/arch/arm/src/arm/up_schedulesigaction.c
index 3972b7792120a9ebe55b3ae569862e5b259c90cd..f6f0c655e8fe2cd623e84ea9e487b6c0af15ac33 100644
--- a/arch/arm/src/arm/up_schedulesigaction.c
+++ b/arch/arm/src/arm/up_schedulesigaction.c
@@ -94,7 +94,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
{
irqstate_t flags;
- sdbg("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+ sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
/* Make sure that interrupts are disabled */
@@ -108,7 +108,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* being delivered to the currently executing task.
*/
- sdbg("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
+ sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
if (tcb == this_task())
{
diff --git a/arch/arm/src/arm/up_sigdeliver.c b/arch/arm/src/arm/up_sigdeliver.c
index c03511d4df485c2648ae567bcbdb43656196e8d7..29176429f3cecd284f677bb9f74cb46be9570aeb 100644
--- a/arch/arm/src/arm/up_sigdeliver.c
+++ b/arch/arm/src/arm/up_sigdeliver.c
@@ -95,7 +95,7 @@ void up_sigdeliver(void)
board_autoled_on(LED_SIGNAL);
- sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
+ sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
ASSERT(rtcb->xcp.sigdeliver != NULL);
@@ -126,7 +126,7 @@ void up_sigdeliver(void)
* errno that is needed by the user logic (it is probably EINTR).
*/
- sdbg("Resuming\n");
+ sinfo("Resuming\n");
(void)up_irq_save();
rtcb->pterrno = saved_errno;
diff --git a/arch/arm/src/arm/up_syscall.c b/arch/arm/src/arm/up_syscall.c
index 07d8ac26d229a90eff58544e4349008ffde9a7d4..c52b036951920870dff3fc4882d72e63f17a07cb 100644
--- a/arch/arm/src/arm/up_syscall.c
+++ b/arch/arm/src/arm/up_syscall.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/arm/up_syscall.c
*
- * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2007-2009, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
@@ -58,22 +47,6 @@
#include "up_arch.h"
#include "up_internal.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * vectors
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -82,8 +55,8 @@
* Name: up_syscall
*
* Description:
- * SWI interrupts will vection here with insn=the SWI
- * instruction and xcp=the interrupt context
+ * SWI interrupts will vector here with insn=the SWI instruction and
+ * xcp=the interrupt context
*
* The handler may get the SWI number be de-referencing
* the return address saved in the xcp and decoding
@@ -93,7 +66,7 @@
void up_syscall(uint32_t *regs)
{
- lldbg("Syscall from 0x%x\n", regs[REG_PC]);
+ _alert("Syscall from 0x%x\n", regs[REG_PC]);
CURRENT_REGS = regs;
PANIC();
}
diff --git a/arch/arm/src/arm/up_undefinedinsn.c b/arch/arm/src/arm/up_undefinedinsn.c
index 99b1e3fc66b1bca83ed545f1f9e6442f24d65ad2..364b072acdef98754b6e72d7921904c05576427b 100644
--- a/arch/arm/src/arm/up_undefinedinsn.c
+++ b/arch/arm/src/arm/up_undefinedinsn.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/arm/up_undefinedinsn.c
*
- * Copyright (C) 2007-2009, 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2007-2009, 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -58,18 +47,6 @@
#include "up_internal.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -80,7 +57,7 @@
void up_undefinedinsn(uint32_t *regs)
{
- lldbg("Undefined instruction at 0x%x\n", regs[REG_PC]);
+ _alert("Undefined instruction at 0x%x\n", regs[REG_PC]);
CURRENT_REGS = regs;
PANIC();
}
diff --git a/arch/arm/src/armv6-m/nvic.h b/arch/arm/src/armv6-m/nvic.h
index 945d5c4338f27eddd05964437a3989e5459fbce5..b6f4391a4a68466c299e149d152d83d0ad48f284 100644
--- a/arch/arm/src/armv6-m/nvic.h
+++ b/arch/arm/src/armv6-m/nvic.h
@@ -41,6 +41,7 @@
****************************************************************************************************/
#include
+#include
/****************************************************************************************************
* Pre-processor Definitions
@@ -386,7 +387,7 @@ extern "C"
*
****************************************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
void up_dumpnvic(FAR const char *msg);
#else
# define up_dumpnvic(m)
diff --git a/arch/arm/src/armv6-m/up_assert.c b/arch/arm/src/armv6-m/up_assert.c
index dcb71392696ac255d524318c661bc8d5c0b136df..f218cd477b028866ec07d179ca4daeedda62f1a7 100644
--- a/arch/arm/src/armv6-m/up_assert.c
+++ b/arch/arm/src/armv6-m/up_assert.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv6-m/up_assert.c
*
- * Copyright (C) 2013-2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013-2015, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -76,23 +65,6 @@
# undef CONFIG_ARCH_USBDUMP
#endif
-/* The following is just intended to keep some ugliness out of the mainline
- * code. We are going to print the task name if:
- *
- * CONFIG_TASK_NAME_SIZE > 0 && <-- The task has a name
- * (defined(CONFIG_DEBUG) || <-- And the debug is enabled (lldbg used)
- * defined(CONFIG_ARCH_STACKDUMP) <-- Or lowsyslog() is used
- */
-
-#undef CONFIG_PRINT_TASKNAME
-#if CONFIG_TASK_NAME_SIZE > 0 && (defined(CONFIG_DEBUG) || defined(CONFIG_ARCH_STACKDUMP))
-# define CONFIG_PRINT_TASKNAME 1
-#endif
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -126,7 +98,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base)
for (stack = sp & ~0x1f; stack < stack_base; stack += 32)
{
uint32_t *ptr = (uint32_t *)stack;
- lldbg("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
stack, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
@@ -144,12 +116,12 @@ static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg)
{
/* Dump interesting properties of this task */
-#ifdef CONFIG_PRINT_TASKNAME
- lldbg("%s: PID=%d Stack Used=%lu of %lu\n",
+#if CONFIG_TASK_NAME_SIZE > 0
+ _alert("%s: PID=%d Stack Used=%lu of %lu\n",
tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#else
- lldbg("PID: %d Stack Used=%lu of %lu\n",
+ _alert("PID: %d Stack Used=%lu of %lu\n",
tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#endif
@@ -184,22 +156,22 @@ static inline void up_registerdump(void)
{
/* Yes.. dump the interrupt registers */
- lldbg("R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
- lldbg("R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
#ifdef CONFIG_BUILD_PROTECTED
- lldbg("xPSR: %08x PRIMASK: %08x EXEC_RETURN: %08x\n",
+ _alert("xPSR: %08x PRIMASK: %08x EXEC_RETURN: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
CURRENT_REGS[REG_EXC_RETURN]);
#else
- lldbg("xPSR: %08x PRIMASK: %08x\n",
+ _alert("xPSR: %08x PRIMASK: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
#endif
}
@@ -221,7 +193,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
/* Let vsyslog do the real work */
va_start(ap, fmt);
- ret = lowvsyslog(LOG_INFO, fmt, ap);
+ ret = vsyslog(LOG_EMERG, fmt, ap);
va_end(ap);
return ret;
}
@@ -270,12 +242,12 @@ static void up_dumpstate(void)
/* Show interrupt stack info */
- lldbg("sp: %08x\n", sp);
- lldbg("IRQ stack:\n");
- lldbg(" base: %08x\n", istackbase);
- lldbg(" size: %08x\n", istacksize);
+ _alert("sp: %08x\n", sp);
+ _alert("IRQ stack:\n");
+ _alert(" base: %08x\n", istackbase);
+ _alert(" size: %08x\n", istacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_intstack());
+ _alert(" used: %08x\n", up_check_intstack());
#endif
/* Does the current stack pointer lie within the interrupt
@@ -297,14 +269,14 @@ static void up_dumpstate(void)
if (CURRENT_REGS)
{
sp = CURRENT_REGS[REG_R13];
- lldbg("sp: %08x\n", sp);
+ _alert("sp: %08x\n", sp);
}
- lldbg("User stack:\n");
- lldbg(" base: %08x\n", ustackbase);
- lldbg(" size: %08x\n", ustacksize);
+ _alert("User stack:\n");
+ _alert(" base: %08x\n", ustackbase);
+ _alert(" size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_tcbstack(rtcb));
+ _alert(" used: %08x\n", up_check_tcbstack(rtcb));
#endif
/* Dump the user stack if the stack pointer lies within the allocated user
@@ -317,11 +289,11 @@ static void up_dumpstate(void)
}
#else
- lldbg("sp: %08x\n", sp);
- lldbg("stack base: %08x\n", ustackbase);
- lldbg("stack size: %08x\n", ustacksize);
+ _alert("sp: %08x\n", sp);
+ _alert("stack base: %08x\n", ustackbase);
+ _alert("stack size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg("stack used: %08x\n", up_check_tcbstack(rtcb));
+ _alert("stack used: %08x\n", up_check_tcbstack(rtcb));
#endif
/* Dump the user stack if the stack pointer lies within the allocated user
@@ -330,7 +302,7 @@ static void up_dumpstate(void)
if (sp > ustackbase || sp <= ustackbase - ustacksize)
{
- lldbg("ERROR: Stack pointer is not within allocated stack\n");
+ _alert("ERROR: Stack pointer is not within allocated stack\n");
}
else
{
@@ -394,17 +366,17 @@ static void _up_assert(int errorcode)
void up_assert(const uint8_t *filename, int lineno)
{
-#ifdef CONFIG_PRINT_TASKNAME
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
struct tcb_s *rtcb = this_task();
#endif
board_autoled_on(LED_ASSERTION);
-#ifdef CONFIG_PRINT_TASKNAME
- lldbg("Assertion failed at file:%s line: %d task: %s\n",
+#if CONFIG_TASK_NAME_SIZE > 0
+ _alert("Assertion failed at file:%s line: %d task: %s\n",
filename, lineno, rtcb->name);
#else
- lldbg("Assertion failed at file:%s line: %d\n",
+ _alert("Assertion failed at file:%s line: %d\n",
filename, lineno);
#endif
diff --git a/arch/arm/src/armv6-m/up_dumpnvic.c b/arch/arm/src/armv6-m/up_dumpnvic.c
index 36c2fdf21682cf9e24b417aa83da5bcd60ae845c..8439ac6a2a91f7005ea86a5fe762fdf560dbce8b 100644
--- a/arch/arm/src/armv6-m/up_dumpnvic.c
+++ b/arch/arm/src/armv6-m/up_dumpnvic.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv6-m/up_dumpnvic.c
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -48,19 +48,7 @@
#include "nvic.h"
-#ifdef CONFIG_DEBUG
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
+#ifdef CONFIG_DEBUG_FEATURES
/****************************************************************************
* Public Functions
@@ -76,6 +64,7 @@
void up_dumpnvic(FAR const char *msg)
{
+#ifdef CONFIG_DEBUG_INFO
irqstate_t flags;
int i;
@@ -83,29 +72,30 @@ void up_dumpnvic(FAR const char *msg)
flags = enter_critical_section();
- lldbg("NVIC: %s\n", msg);
- lldbg(" ISER: %08x ICER: %08x ISPR: %08x ICPR: %08x\n",
- getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER),
- getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
+ _info("NVIC: %s\n", msg);
+ _info(" ISER: %08x ICER: %08x ISPR: %08x ICPR: %08x\n",
+ getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER),
+ getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
for (i = 0 ; i < 8; i += 4)
{
- lldbg(" IPR%d: %08x IPR%d: %08x IPR%d: %08x IPR%d: %08x\n",
- i, getreg32(ARMV6M_NVIC_IPR(i)),
- i+1, getreg32(ARMV6M_NVIC_IPR(i+1)),
- i+2, getreg32(ARMV6M_NVIC_IPR(i+2)),
- i+3, getreg32(ARMV6M_NVIC_IPR(i+3)));
+ _info(" IPR%d: %08x IPR%d: %08x IPR%d: %08x IPR%d: %08x\n",
+ i, getreg32(ARMV6M_NVIC_IPR(i)),
+ i+1, getreg32(ARMV6M_NVIC_IPR(i+1)),
+ i+2, getreg32(ARMV6M_NVIC_IPR(i+2)),
+ i+3, getreg32(ARMV6M_NVIC_IPR(i+3)));
}
- lldbg("SYSCON:\n");
- lldbg(" CPUID: %08x ICSR: %08x AIRCR: %08x SCR: %08x\n",
- getreg32(ARMV6M_SYSCON_CPUID), getreg32(ARMV6M_SYSCON_ICSR),
- getreg32(ARMV6M_SYSCON_AIRCR), getreg32(ARMV6M_SYSCON_SCR));
- lldbg(" CCR: %08x SHPR2: %08x SHPR3: %08x\n",
- getreg32(ARMV6M_SYSCON_CCR), getreg32(ARMV6M_SYSCON_SHPR2),
- getreg32(ARMV6M_SYSCON_SHPR3));
+ _info("SYSCON:\n");
+ _info(" CPUID: %08x ICSR: %08x AIRCR: %08x SCR: %08x\n",
+ getreg32(ARMV6M_SYSCON_CPUID), getreg32(ARMV6M_SYSCON_ICSR),
+ getreg32(ARMV6M_SYSCON_AIRCR), getreg32(ARMV6M_SYSCON_SCR));
+ _info(" CCR: %08x SHPR2: %08x SHPR3: %08x\n",
+ getreg32(ARMV6M_SYSCON_CCR), getreg32(ARMV6M_SYSCON_SHPR2),
+ getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
+#endif
}
-#endif /* CONFIG_DEBUG */
+#endif /* CONFIG_DEBUG_FEATURES */
diff --git a/arch/arm/src/armv6-m/up_elf.c b/arch/arm/src/armv6-m/up_elf.c
index dbe002cbb1a97419821aa7b3d2821a12e029ae97..7bde5d01106c3086b361c9bdab48d2aaa2186593 100644
--- a/arch/arm/src/armv6-m/up_elf.c
+++ b/arch/arm/src/armv6-m/up_elf.c
@@ -86,7 +86,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_machine != EM_ARM)
{
- bdbg("Not for ARM: e_machine=%04x\n", ehdr->e_machine);
+ berr("ERROR: Not for ARM: e_machine=%04x\n", ehdr->e_machine);
return -ENOEXEC;
}
@@ -94,7 +94,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_ident[EI_CLASS] != ELFCLASS32)
{
- bdbg("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
+ berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
return -ENOEXEC;
}
@@ -106,7 +106,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB)
#endif
{
- bdbg("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
+ berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
return -ENOEXEC;
}
@@ -168,7 +168,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_CALL:
case R_ARM_JUMP24:
{
- bvdbg("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
+ binfo("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@@ -181,7 +181,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
offset += sym->st_value - addr;
if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000)
{
- bdbg(" ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
+ berr("ERROR: ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
ELF32_R_TYPE(rel->r_info), offset);
return -EINVAL;
@@ -197,7 +197,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_ABS32:
case R_ARM_TARGET1: /* New ABI: TARGET1 always treated as ABS32 */
{
- bvdbg("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ binfo("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
*(uint32_t *)addr += sym->st_value;
@@ -245,7 +245,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
upper_insn = (uint32_t)(*(uint16_t *)addr);
lower_insn = (uint32_t)(*(uint16_t *)(addr + 2));
- bvdbg("Performing THM_JUMP24 [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
+ binfo("Performing THM_JUMP24 [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (int)upper_insn, (int)lower_insn,
sym, (long)sym->st_value);
@@ -279,7 +279,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
/* And perform the relocation */
- bvdbg(" S=%d J1=%d J2=%d offset=%08lx branch target=%08lx\n",
+ binfo(" S=%d J1=%d J2=%d offset=%08lx branch target=%08lx\n",
S, J1, J2, (long)offset, offset + sym->st_value - addr);
offset += sym->st_value - addr;
@@ -290,7 +290,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
if (ELF32_ST_TYPE(sym->st_info) == STT_FUNC && (offset & 1) == 0)
{
- bdbg(" ERROR: JUMP24 [%d] requires odd offset, offset=%08lx\n",
+ berr("ERROR: ERROR: JUMP24 [%d] requires odd offset, offset=%08lx\n",
ELF32_R_TYPE(rel->r_info), offset);
return -EINVAL;
@@ -300,7 +300,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
if (offset <= (int32_t)0xff000000 || offset >= (int32_t)0x01000000)
{
- bdbg(" ERROR: JUMP24 [%d] relocation out of range, branch taget=%08lx\n",
+ berr("ERROR: ERROR: JUMP24 [%d] relocation out of range, branch taget=%08lx\n",
ELF32_R_TYPE(rel->r_info), offset);
return -EINVAL;
@@ -320,14 +320,14 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
lower_insn = ((lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | ((offset >> 1) & 0x07ff));
*(uint16_t *)(addr + 2) = (uint16_t)lower_insn;
- bvdbg(" S=%d J1=%d J2=%d insn [%04x %04x]\n",
+ binfo(" S=%d J1=%d J2=%d insn [%04x %04x]\n",
S, J1, J2, (int)upper_insn, (int)lower_insn);
}
break;
case R_ARM_V4BX:
{
- bvdbg("Performing V4BX link at addr=%08lx [%08lx]\n",
+ binfo("Performing V4BX link at addr=%08lx [%08lx]\n",
(long)addr, (long)(*(uint32_t *)addr));
/* Preserve only Rm and the condition code */
@@ -342,7 +342,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_PREL31:
{
- bvdbg("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ binfo("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
offset = *(uint32_t *)addr + sym->st_value - addr;
@@ -353,7 +353,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_MOVW_ABS_NC:
case R_ARM_MOVT_ABS:
{
- bvdbg("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ binfo("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@@ -408,7 +408,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
upper_insn = (uint32_t)(*(uint16_t *)addr);
lower_insn = (uint32_t)(*(uint16_t *)(addr + 2));
- bvdbg("Performing THM_MOVx [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
+ binfo("Performing THM_MOVx [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (int)upper_insn, (int)lower_insn,
sym, (long)sym->st_value);
@@ -425,7 +425,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
/* And perform the relocation */
- bvdbg(" offset=%08lx branch target=%08lx\n",
+ binfo(" offset=%08lx branch target=%08lx\n",
(long)offset, offset + sym->st_value);
offset += sym->st_value;
@@ -445,13 +445,13 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
lower_insn = ((lower_insn & 0x8f00) | ((offset & 0x0700) << 4) | (offset & 0x00ff));
*(uint16_t *)(addr + 2) = (uint16_t)lower_insn;
- bvdbg(" insn [%04x %04x]\n",
+ binfo(" insn [%04x %04x]\n",
(int)upper_insn, (int)lower_insn);
}
break;
default:
- bdbg("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
+ berr("ERROR: Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
return -EINVAL;
}
@@ -461,6 +461,6 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
int up_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym,
uintptr_t addr)
{
- bdbg("RELA relocation not supported\n");
+ berr("ERROR: RELA relocation not supported\n");
return -ENOSYS;
}
diff --git a/arch/arm/src/armv6-m/up_hardfault.c b/arch/arm/src/armv6-m/up_hardfault.c
index edd1bab6a23606f93397d4c85bd62494de83cf90..b3c24d885151cf63fd6dd50179bc890c622dea98 100644
--- a/arch/arm/src/armv6-m/up_hardfault.c
+++ b/arch/arm/src/armv6-m/up_hardfault.c
@@ -55,25 +55,13 @@
****************************************************************************/
#ifdef CONFIG_DEBUG_HARDFAULT
-# define hfdbg(format, ...) lldbg(format, ##__VA_ARGS__)
+# define hfinfo(format, ...) _alert(format, ##__VA_ARGS__)
#else
-# define hfdbg(x...)
+# define hfinfo(x...)
#endif
#define INSN_SVC0 0xdf00 /* insn: svc 0 */
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -118,7 +106,7 @@ int up_hardfault(int irq, FAR void *context)
/* Fetch the instruction that caused the Hard fault */
uint16_t insn = *pc;
- hfdbg(" PC: %p INSN: %04x\n", pc, insn);
+ hfinfo(" PC: %p INSN: %04x\n", pc, insn);
/* If this was the instruction 'svc 0', then forward processing
* to the SVCall handler
@@ -126,7 +114,7 @@ int up_hardfault(int irq, FAR void *context)
if (insn == INSN_SVC0)
{
- hfdbg("Forward SVCall\n");
+ hfinfo("Forward SVCall\n");
return up_svcall(irq, context);
}
}
@@ -134,22 +122,22 @@ int up_hardfault(int irq, FAR void *context)
#if defined(CONFIG_DEBUG_HARDFAULT)
/* Dump some hard fault info */
- hfdbg("\nHard Fault:\n");
- hfdbg(" IRQ: %d regs: %p\n", irq, regs);
- hfdbg(" PRIMASK: %08x IPSR: %08x\n",
- getprimask(), getipsr());
- hfdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- hfdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
- hfdbg(" xPSR: %08x PRIMASK: %08x (saved)\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
+ _alert("\nHard Fault:\n");
+ _alert(" IRQ: %d regs: %p\n", irq, regs);
+ _alert(" PRIMASK: %08x IPSR: %08x\n",
+ getprimask(), getipsr());
+ _alert(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ _alert(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ _alert(" xPSR: %08x PRIMASK: %08x (saved)\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
#endif
(void)up_irq_save();
- lldbg("PANIC!!! Hard fault\n");
+ _alert("PANIC!!! Hard fault\n");
PANIC();
return OK; /* Won't get here */
}
diff --git a/arch/arm/src/armv6-m/up_releasepending.c b/arch/arm/src/armv6-m/up_releasepending.c
index c3e2d02ea70c64ed4323136e48f3dff423627322..3c925a02b816280902308c6f314ef8baadc8dc9c 100644
--- a/arch/arm/src/armv6-m/up_releasepending.c
+++ b/arch/arm/src/armv6-m/up_releasepending.c
@@ -66,7 +66,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
- slldbg("From TCB=%p\n", rtcb);
+ sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */
diff --git a/arch/arm/src/armv6-m/up_reprioritizertr.c b/arch/arm/src/armv6-m/up_reprioritizertr.c
index bd50b88b70c2d8c05e5f29b410eeff6af135ac88..41f0c8700d33b9b6859c372b6a134087d4ed89e7 100644
--- a/arch/arm/src/armv6-m/up_reprioritizertr.c
+++ b/arch/arm/src/armv6-m/up_reprioritizertr.c
@@ -94,7 +94,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
- slldbg("TCB=%p PRI=%d\n", tcb, priority);
+ sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just removed the head
diff --git a/arch/arm/src/armv6-m/up_schedulesigaction.c b/arch/arm/src/armv6-m/up_schedulesigaction.c
index be9505a9c2c9ae74404f0cf8edd4d215b42cc432..5040582bacf59d2c87c8f27501cb454fd648b357 100644
--- a/arch/arm/src/armv6-m/up_schedulesigaction.c
+++ b/arch/arm/src/armv6-m/up_schedulesigaction.c
@@ -107,7 +107,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
{
irqstate_t flags;
- sdbg("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+ sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
/* Make sure that interrupts are disabled */
@@ -121,7 +121,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* to the currently executing task.
*/
- sdbg("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
+ sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
if (tcb == this_task())
{
diff --git a/arch/arm/src/armv6-m/up_sigdeliver.c b/arch/arm/src/armv6-m/up_sigdeliver.c
index 84b89542a207aff8cceb519d51bd8e0ac47ce0ff..c2b3e8675e0ee606060d2872254b66607aa5a354 100644
--- a/arch/arm/src/armv6-m/up_sigdeliver.c
+++ b/arch/arm/src/armv6-m/up_sigdeliver.c
@@ -100,7 +100,7 @@ void up_sigdeliver(void)
board_autoled_on(LED_SIGNAL);
- sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
+ sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
ASSERT(rtcb->xcp.sigdeliver != NULL);
@@ -135,7 +135,7 @@ void up_sigdeliver(void)
* errno that is needed by the user logic (it is probably EINTR).
*/
- sdbg("Resuming\n");
+ sinfo("Resuming\n");
(void)up_irq_save();
rtcb->pterrno = saved_errno;
diff --git a/arch/arm/src/armv6-m/up_svcall.c b/arch/arm/src/armv6-m/up_svcall.c
index b5cec07937933cdc12a47165f980057554c8b0e2..1cd7e3a33b058a55747d143080c9610ae4fbc779 100644
--- a/arch/arm/src/armv6-m/up_svcall.c
+++ b/arch/arm/src/armv6-m/up_svcall.c
@@ -55,33 +55,6 @@
#include "exc_return.h"
#include "up_internal.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-/* Configuration ************************************************************/
-
-/* Debug ********************************************************************/
-/* Debug output from this file may interfere with context switching! To get
- * debug output you must enabled the following in your NuttX configuration:
- *
- * - CONFIG_DEBUG and CONFIG_DEBUG_SYSCALL (shows only syscalls)
- * - CONFIG_DEBUG and CONFIG_DEBUG_SVCALL (shows everything)
- */
-
-#if defined(CONFIG_DEBUG_SYSCALL) || defined(CONFIG_DEBUG_SVCALL)
-# define svcdbg(format, ...) lldbg(format, ##__VA_ARGS__)
-#else
-# define svcdbg(x...)
-#endif
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -169,24 +142,24 @@ int up_svcall(int irq, FAR void *context)
* and R1..R7 = variable number of arguments depending on the system call.
*/
-#if defined(CONFIG_DEBUG_SYSCALL) || defined(CONFIG_DEBUG_SVCALL)
+#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# endif
{
- svcdbg("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
- svcdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- svcdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
# ifdef CONFIG_BUILD_PROTECTED
- svcdbg(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
- regs[REG_XPSR], regs[REG_PRIMASK], regs[REG_EXC_RETURN]);
+ svcinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
+ regs[REG_XPSR], regs[REG_PRIMASK], regs[REG_EXC_RETURN]);
# else
- svcdbg(" PSR: %08x PRIMASK: %08x\n",
- regs[REG_XPSR], regs[REG_PRIMASK]);
+ svcinfo(" PSR: %08x PRIMASK: %08x\n",
+ regs[REG_XPSR], regs[REG_PRIMASK]);
# endif
}
#endif
@@ -471,7 +444,7 @@ int up_svcall(int irq, FAR void *context)
regs[REG_R0] -= CONFIG_SYS_RESERVED;
#else
- slldbg("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
+ svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
#endif
}
break;
@@ -479,37 +452,37 @@ int up_svcall(int irq, FAR void *context)
/* Report what happened. That might difficult in the case of a context switch */
-#if defined(CONFIG_DEBUG_SYSCALL) || defined(CONFIG_DEBUG_SVCALL)
+#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# else
if (regs != CURRENT_REGS)
# endif
{
- svcdbg("SVCall Return:\n");
- svcdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
- CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
- CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
- CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
- svcdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
- CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
- CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
- CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
+ svcinfo("SVCall Return:\n");
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
+ CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
+ CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
+ CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
+ CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
+ CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
+ CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
#ifdef CONFIG_BUILD_PROTECTED
- svcdbg(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
- CURRENT_REGS[REG_EXC_RETURN]);
+ svcinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
+ CURRENT_REGS[REG_EXC_RETURN]);
#else
- svcdbg(" PSR: %08x PRIMASK: %08x\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
+ svcinfo(" PSR: %08x PRIMASK: %08x\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
#endif
}
# ifdef CONFIG_DEBUG_SVCALL
else
{
- svcdbg("SVCall Return: %d\n", regs[REG_R0]);
+ svcinfo("SVCall Return: %d\n", regs[REG_R0]);
}
# endif
#endif
diff --git a/arch/arm/src/armv7-a/arm_addrenv.c b/arch/arm/src/armv7-a/arm_addrenv.c
index 2bd1f886cecc08fa8ea163c382416c38cbe64375..7d2818283dca2d1148ea3ecb01c9c4b66fae85a0 100644
--- a/arch/arm/src/armv7-a/arm_addrenv.c
+++ b/arch/arm/src/armv7-a/arm_addrenv.c
@@ -257,7 +257,7 @@ int up_addrenv_create(size_t textsize, size_t datasize, size_t heapsize,
{
int ret;
- bvdbg("addrenv=%p textsize=%lu datasize=%lu\n",
+ binfo("addrenv=%p textsize=%lu datasize=%lu\n",
addrenv, (unsigned long)textsize, (unsigned long)datasize);
DEBUGASSERT(addrenv);
@@ -278,7 +278,7 @@ int up_addrenv_create(size_t textsize, size_t datasize, size_t heapsize,
MMU_L2_UTEXTFLAGS);
if (ret < 0)
{
- bdbg("ERROR: Failed to create .text region: %d\n", ret);
+ berr("ERROR: Failed to create .text region: %d\n", ret);
goto errout;
}
@@ -293,7 +293,7 @@ int up_addrenv_create(size_t textsize, size_t datasize, size_t heapsize,
MMU_L2_UDATAFLAGS);
if (ret < 0)
{
- bdbg("ERROR: Failed to create .bss/.data region: %d\n", ret);
+ berr("ERROR: Failed to create .bss/.data region: %d\n", ret);
goto errout;
}
@@ -305,7 +305,7 @@ int up_addrenv_create(size_t textsize, size_t datasize, size_t heapsize,
ret = up_addrenv_initdata((uintptr_t)addrenv->data[0] & PMD_PTE_PADDR_MASK);
if (ret < 0)
{
- bdbg("ERROR: Failed to initialize .bss/.data region: %d\n", ret);
+ berr("ERROR: Failed to initialize .bss/.data region: %d\n", ret);
goto errout;
}
#endif
@@ -318,7 +318,7 @@ int up_addrenv_create(size_t textsize, size_t datasize, size_t heapsize,
MMU_L2_UDATAFLAGS);
if (ret < 0)
{
- bdbg("ERROR: Failed to create heap region: %d\n", ret);
+ berr("ERROR: Failed to create heap region: %d\n", ret);
goto errout;
}
@@ -353,7 +353,7 @@ errout:
int up_addrenv_destroy(FAR group_addrenv_t *addrenv)
{
- bvdbg("addrenv=%p\n", addrenv);
+ binfo("addrenv=%p\n", addrenv);
DEBUGASSERT(addrenv);
/* Destroy the .text region */
@@ -405,7 +405,7 @@ int up_addrenv_destroy(FAR group_addrenv_t *addrenv)
int up_addrenv_vtext(FAR group_addrenv_t *addrenv, FAR void **vtext)
{
- bvdbg("return=%p\n", (FAR void *)CONFIG_ARCH_TEXT_VBASE);
+ binfo("return=%p\n", (FAR void *)CONFIG_ARCH_TEXT_VBASE);
/* Not much to do in this case */
@@ -439,7 +439,7 @@ int up_addrenv_vtext(FAR group_addrenv_t *addrenv, FAR void **vtext)
int up_addrenv_vdata(FAR group_addrenv_t *addrenv, uintptr_t textsize,
FAR void **vdata)
{
- bvdbg("return=%p\n",
+ binfo("return=%p\n",
(FAR void *)(CONFIG_ARCH_DATA_VBASE + ARCH_DATA_RESERVE_SIZE));
/* Not much to do in this case */
@@ -636,7 +636,7 @@ int up_addrenv_restore(FAR const save_addrenv_t *oldenv)
uintptr_t vaddr;
int i;
- bvdbg("oldenv=%p\n", oldenv);
+ binfo("oldenv=%p\n", oldenv);
DEBUGASSERT(oldenv);
for (vaddr = CONFIG_ARCH_TEXT_VBASE, i = 0;
@@ -752,7 +752,7 @@ int up_addrenv_coherent(FAR const group_addrenv_t *addrenv)
int up_addrenv_clone(FAR const group_addrenv_t *src,
FAR group_addrenv_t *dest)
{
- bvdbg("src=%p dest=%p\n", src, dest);
+ binfo("src=%p dest=%p\n", src, dest);
DEBUGASSERT(src && dest);
/* Just copy the address environment from the source to the destination */
@@ -784,7 +784,7 @@ int up_addrenv_clone(FAR const group_addrenv_t *src,
int up_addrenv_attach(FAR struct task_group_s *group, FAR struct tcb_s *tcb)
{
- bvdbg("group=%p tcb=%p\n", group, tcb);
+ binfo("group=%p tcb=%p\n", group, tcb);
/* Nothing needs to be done in this implementation */
@@ -817,7 +817,7 @@ int up_addrenv_attach(FAR struct task_group_s *group, FAR struct tcb_s *tcb)
int up_addrenv_detach(FAR struct task_group_s *group, FAR struct tcb_s *tcb)
{
- bvdbg("group=%p tcb=%p\n", group, tcb);
+ binfo("group=%p tcb=%p\n", group, tcb);
/* Nothing needs to be done in this implementation */
diff --git a/arch/arm/src/armv7-a/arm_addrenv_kstack.c b/arch/arm/src/armv7-a/arm_addrenv_kstack.c
index da2a474126edce8306937c48ce5202bb016f14b7..5bb2b688b541cc09b477555ac879010dd39f7d06 100644
--- a/arch/arm/src/armv7-a/arm_addrenv_kstack.c
+++ b/arch/arm/src/armv7-a/arm_addrenv_kstack.c
@@ -144,7 +144,7 @@
int up_addrenv_kstackalloc(FAR struct tcb_s *tcb)
{
- bvdbg("tcb=%p stacksize=%u\n", tcb, ARCH_KERNEL_STACKSIZE);
+ binfo("tcb=%p stacksize=%u\n", tcb, ARCH_KERNEL_STACKSIZE);
DEBUGASSERT(tcb && tcb->xcp.kstack == 0);
@@ -153,7 +153,7 @@ int up_addrenv_kstackalloc(FAR struct tcb_s *tcb)
tcb->xcp.kstack = (FAR uint32_t *)kmm_memalign(8, ARCH_KERNEL_STACKSIZE);
if (!tcb->xcp.kstack)
{
- bdbg("ERROR: Failed to allocate the kernel stack\n");
+ berr("ERROR: Failed to allocate the kernel stack\n");
return -ENOMEM;
}
@@ -177,7 +177,7 @@ int up_addrenv_kstackalloc(FAR struct tcb_s *tcb)
int up_addrenv_kstackfree(FAR struct tcb_s *tcb)
{
- bvdbg("tcb=%p\n", tcb);
+ binfo("tcb=%p\n", tcb);
DEBUGASSERT(tcb);
/* Does the exiting thread have a kernel stack? */
diff --git a/arch/arm/src/armv7-a/arm_addrenv_shm.c b/arch/arm/src/armv7-a/arm_addrenv_shm.c
index 9a05b9f7b92997542052a72156a2b7c1dab6cbb2..cc9c9440d802dba65a345c74e6c7ebbb98e108c6 100644
--- a/arch/arm/src/armv7-a/arm_addrenv_shm.c
+++ b/arch/arm/src/armv7-a/arm_addrenv_shm.c
@@ -92,7 +92,7 @@ int up_shmat(FAR uintptr_t *pages, unsigned int npages, uintptr_t vaddr)
unsigned int nmapped;
unsigned int shmndx;
- shmvdbg("pages=%p npages=%d vaddr=%08lx\n",
+ shminfo("pages=%p npages=%d vaddr=%08lx\n",
pages, npages, (unsigned long)vaddr);
/* Sanity checks */
@@ -241,7 +241,7 @@ int up_shmdt(uintptr_t vaddr, unsigned int npages)
unsigned int nunmapped;
unsigned int shmndx;
- shmvdbg("npages=%d vaddr=%08lx\n", npages, (unsigned long)vaddr);
+ shminfo("npages=%d vaddr=%08lx\n", npages, (unsigned long)vaddr);
/* Sanity checks */
diff --git a/arch/arm/src/armv7-a/arm_addrenv_ustack.c b/arch/arm/src/armv7-a/arm_addrenv_ustack.c
index 206d517ef3810f7190d84bc1d0241328b851ddf9..4b7be01bd6d73e4c8df83412385790799d7ed909 100644
--- a/arch/arm/src/armv7-a/arm_addrenv_ustack.c
+++ b/arch/arm/src/armv7-a/arm_addrenv_ustack.c
@@ -143,7 +143,7 @@ int up_addrenv_ustackalloc(FAR struct tcb_s *tcb, size_t stacksize)
{
int ret;
- bvdbg("tcb=%p stacksize=%lu\n", tcb, (unsigned long)stacksize);
+ binfo("tcb=%p stacksize=%lu\n", tcb, (unsigned long)stacksize);
DEBUGASSERT(tcb);
@@ -163,7 +163,7 @@ int up_addrenv_ustackalloc(FAR struct tcb_s *tcb, size_t stacksize)
MMU_L2_UDATAFLAGS);
if (ret < 0)
{
- bdbg("ERROR: Failed to create stack region: %d\n", ret);
+ berr("ERROR: Failed to create stack region: %d\n", ret);
up_addrenv_ustackfree(tcb);
return ret;
}
@@ -190,7 +190,7 @@ int up_addrenv_ustackalloc(FAR struct tcb_s *tcb, size_t stacksize)
int up_addrenv_ustackfree(FAR struct tcb_s *tcb)
{
- bvdbg("tcb=%p\n", tcb);
+ binfo("tcb=%p\n", tcb);
DEBUGASSERT(tcb);
/* Destroy the stack region */
@@ -221,7 +221,7 @@ int up_addrenv_ustackfree(FAR struct tcb_s *tcb)
int up_addrenv_vustack(FAR const struct tcb_s *tcb, FAR void **vstack)
{
- bvdbg("Return=%p\n", (FAR void *)CONFIG_ARCH_STACK_VBASE);
+ binfo("Return=%p\n", (FAR void *)CONFIG_ARCH_STACK_VBASE);
/* Not much to do in this case */
diff --git a/arch/arm/src/armv7-a/arm_addrenv_utils.c b/arch/arm/src/armv7-a/arm_addrenv_utils.c
index f3147918f26e5f32c8d749b19eb6be06a1b1aee0..2eb58623afaa55e5da925232879a620c256823c5 100644
--- a/arch/arm/src/armv7-a/arm_addrenv_utils.c
+++ b/arch/arm/src/armv7-a/arm_addrenv_utils.c
@@ -84,7 +84,7 @@ int arm_addrenv_create_region(FAR uintptr_t **list, unsigned int listlen,
unsigned int i;
unsigned int j;
- bvdbg("listlen=%d vaddr=%08lx regionsize=%ld, mmuflags=%08x\n",
+ binfo("listlen=%d vaddr=%08lx regionsize=%ld, mmuflags=%08x\n",
listlen, (unsigned long)vaddr, (unsigned long)regionsize,
(unsigned int)mmuflags);
@@ -98,7 +98,7 @@ int arm_addrenv_create_region(FAR uintptr_t **list, unsigned int listlen,
npages = MM_NPAGES(regionsize);
if (npages > (listlen << (20 - MM_PGSHIFT)))
{
- bdbg("ERROR: npages=%u listlen=%u\n", npages, listlen);
+ berr("ERROR: npages=%u listlen=%u\n", npages, listlen);
return -E2BIG;
}
@@ -201,7 +201,7 @@ void arm_addrenv_destroy_region(FAR uintptr_t **list, unsigned int listlen,
int i;
int j;
- bvdbg("listlen=%d vaddr=%08lx\n", listlen, (unsigned long)vaddr);
+ binfo("listlen=%d vaddr=%08lx\n", listlen, (unsigned long)vaddr);
for (i = 0; i < listlen; vaddr += SECTION_SIZE, list++, i++)
{
diff --git a/arch/arm/src/armv7-a/arm_assert.c b/arch/arm/src/armv7-a/arm_assert.c
index ab3bd4c90819c9eea4377d7116f9a111cf366c31..3c798d33a0d832f98753fb80496b695c51969b03 100644
--- a/arch/arm/src/armv7-a/arm_assert.c
+++ b/arch/arm/src/armv7-a/arm_assert.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-a/arm_assert.c
*
- * Copyright (C) 2013-2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -75,19 +64,6 @@
# undef CONFIG_ARCH_USBDUMP
#endif
-/* The following is just intended to keep some ugliness out of the mainline
- * code. We are going to print the task name if:
- *
- * CONFIG_TASK_NAME_SIZE > 0 && <-- The task has a name
- * (defined(CONFIG_DEBUG) || <-- And the debug is enabled (lldbg used)
- * defined(CONFIG_ARCH_STACKDUMP) <-- Or lowsyslog() is used
- */
-
-#undef CONFIG_PRINT_TASKNAME
-#if CONFIG_TASK_NAME_SIZE > 0 && (defined(CONFIG_DEBUG) || defined(CONFIG_ARCH_STACKDUMP))
-# define CONFIG_PRINT_TASKNAME 1
-#endif
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -121,7 +97,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base)
for (stack = sp & ~0x1f; stack < stack_base; stack += 32)
{
uint32_t *ptr = (uint32_t *)stack;
- lldbg("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
stack, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
@@ -139,12 +115,12 @@ static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg)
{
/* Dump interesting properties of this task */
-#ifdef CONFIG_PRINT_TASKNAME
- lldbg("%s: PID=%d Stack Used=%lu of %lu\n",
+#if CONFIG_TASK_NAME_SIZE > 0
+ _alert("%s: PID=%d Stack Used=%lu of %lu\n",
tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#else
- lldbg("PID: %d Stack Used=%lu of %lu\n",
+ _alert("PID: %d Stack Used=%lu of %lu\n",
tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#endif
@@ -184,12 +160,12 @@ static inline void up_registerdump(void)
for (regs = REG_R0; regs <= REG_R15; regs += 8)
{
uint32_t *ptr = (uint32_t *)&CURRENT_REGS[regs];
- lldbg("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
- lldbg("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]);
+ _alert("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]);
}
}
#else
@@ -209,7 +185,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
/* Let vsyslog do the real work */
va_start(ap, fmt);
- ret = lowvsyslog(LOG_INFO, fmt, ap);
+ ret = vsyslog(LOG_EMERG, fmt, ap);
va_end(ap);
return ret;
}
@@ -253,7 +229,7 @@ static void up_dumpstate(void)
ustacksize = (uint32_t)rtcb->adj_stack_size;
}
- lldbg("Current sp: %08x\n", sp);
+ _alert("Current sp: %08x\n", sp);
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* Get the limits on the interrupt stack memory */
@@ -263,21 +239,21 @@ static void up_dumpstate(void)
/* Show interrupt stack info */
- lldbg("Interrupt stack:\n");
- lldbg(" base: %08x\n", istackbase);
- lldbg(" size: %08x\n", istacksize);
+ _alert("Interrupt stack:\n");
+ _alert(" base: %08x\n", istackbase);
+ _alert(" size: %08x\n", istacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_intstack());
+ _alert(" used: %08x\n", up_check_intstack());
#endif
#endif
/* Show user stack info */
- lldbg("User stack:\n");
- lldbg(" base: %08x\n", ustackbase);
- lldbg(" size: %08x\n", ustacksize);
+ _alert("User stack:\n");
+ _alert(" base: %08x\n", ustackbase);
+ _alert(" size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_tcbstack(rtcb));
+ _alert(" used: %08x\n", up_check_tcbstack(rtcb));
#endif
#ifdef CONFIG_ARCH_KERNEL_STACK
@@ -287,9 +263,9 @@ static void up_dumpstate(void)
{
kstackbase = (uint32_t)rtcb->xcp.kstack + CONFIG_ARCH_KERNEL_STACKSIZE - 4;
- lldbg("Kernel stack:\n");
- lldbg(" base: %08x\n", kstackbase);
- lldbg(" size: %08x\n", CONFIG_ARCH_KERNEL_STACKSIZE);
+ _alert("Kernel stack:\n");
+ _alert(" base: %08x\n", kstackbase);
+ _alert(" size: %08x\n", CONFIG_ARCH_KERNEL_STACKSIZE);
}
#endif
@@ -300,7 +276,7 @@ static void up_dumpstate(void)
{
/* Yes.. dump the interrupt stack */
- lldbg("Interrupt Stack\n", sp);
+ _alert("Interrupt Stack\n", sp);
up_stackdump(sp, istackbase);
/* Extract the user stack pointer which should lie
@@ -308,7 +284,7 @@ static void up_dumpstate(void)
*/
sp = g_intstackbase;
- lldbg("User sp: %08x\n", sp);
+ _alert("User sp: %08x\n", sp);
}
#endif
@@ -318,7 +294,7 @@ static void up_dumpstate(void)
if (sp > ustackbase - ustacksize && sp < ustackbase)
{
- lldbg("User Stack\n", sp);
+ _alert("User Stack\n", sp);
up_stackdump(sp, ustackbase);
}
@@ -329,7 +305,7 @@ static void up_dumpstate(void)
if (sp >= (uint32_t)rtcb->xcp.kstack && sp < kstackbase)
{
- lldbg("Kernel Stack\n", sp);
+ _alert("Kernel Stack\n", sp);
up_stackdump(sp, kstackbase);
}
#endif
@@ -337,7 +313,7 @@ static void up_dumpstate(void)
#ifdef CONFIG_SMP
/* Show the CPU number */
- lldbg("CPU%d:\n", up_cpu_index());
+ _alert("CPU%d:\n", up_cpu_index());
#endif
/* Then dump the CPU registers (if available) */
@@ -396,16 +372,16 @@ static void _up_assert(int errorcode)
void up_assert(const uint8_t *filename, int lineno)
{
-#ifdef CONFIG_PRINT_TASKNAME
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
struct tcb_s *rtcb = this_task();
#endif
board_autoled_on(LED_ASSERTION);
-#ifdef CONFIG_PRINT_TASKNAME
- lldbg("Assertion failed at file:%s line: %d task: %s\n",
+#if CONFIG_TASK_NAME_SIZE > 0
+ _alert("Assertion failed at file:%s line: %d task: %s\n",
filename, lineno, rtcb->name);
#else
- lldbg("Assertion failed at file:%s line: %d\n",
+ _alert("Assertion failed at file:%s line: %d\n",
filename, lineno);
#endif
up_dumpstate();
diff --git a/arch/arm/src/armv7-a/arm_cpustart.c b/arch/arm/src/armv7-a/arm_cpustart.c
index 1ec95da855a9122c37c018593feda1c0d9118b2b..88906a717ded5441a01f73310458fff480089ffc 100644
--- a/arch/arm/src/armv7-a/arm_cpustart.c
+++ b/arch/arm/src/armv7-a/arm_cpustart.c
@@ -64,19 +64,19 @@ static inline void arm_registerdump(FAR struct tcb_s *tcb)
{
int regndx;
- lldbg("CPU%d:\n", up_cpu_index());
+ _info("CPU%d:\n", up_cpu_index());
/* Dump the startup registers */
for (regndx = REG_R0; regndx <= REG_R15; regndx += 8)
{
uint32_t *ptr = (uint32_t *)&tcb->xcp.regs[regndx];
- lldbg("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regndx, ptr[0], ptr[1], ptr[2], ptr[3],
- ptr[4], ptr[5], ptr[6], ptr[7]);
+ _info("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regndx, ptr[0], ptr[1], ptr[2], ptr[3],
+ ptr[4], ptr[5], ptr[6], ptr[7]);
}
- lldbg("CPSR: %08x\n", tcb->xcp.regs[REG_CPSR]);
+ _info("CPSR: %08x\n", tcb->xcp.regs[REG_CPSR]);
}
#else
# define arm_registerdump(tcb)
@@ -106,7 +106,7 @@ int arm_start_handler(int irq, FAR void *context)
{
FAR struct tcb_s *tcb;
- sllvdbg("CPU%d Started\n", up_cpu_index());
+ sinfo("CPU%d Started\n", up_cpu_index());
/* Reset scheduler parameters */
@@ -155,7 +155,7 @@ int arm_start_handler(int irq, FAR void *context)
int up_cpu_start(int cpu)
{
- sllvdbg("Starting CPU%d\n", cpu);
+ sinfo("Starting CPU%d\n", cpu);
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
diff --git a/arch/arm/src/armv7-a/arm_dataabort.c b/arch/arm/src/armv7-a/arm_dataabort.c
index 818557c552abc99c82e0acde220c62afeb9ff910..50c95a20188001fd7013b49f8822ce9ec930d9bc 100644
--- a/arch/arm/src/armv7-a/arm_dataabort.c
+++ b/arch/arm/src/armv7-a/arm_dataabort.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-a/arm_dataabort.c
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
@@ -115,7 +104,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
* fatal error.
*/
- pglldbg("DFSR: %08x DFAR: %08x\n", dfsr, dfar);
+ pginfo("DFSR: %08x DFAR: %08x\n", dfsr, dfar);
if ((dfsr & FSR_MASK) != FSR_PAGE)
{
goto segfault;
@@ -126,7 +115,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
* (It has not yet been saved in the register context save area).
*/
- pgllvdbg("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
+ pginfo("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
if (dfar < PG_PAGED_VBASE || dfar >= PG_PAGED_VEND)
{
goto segfault;
@@ -163,7 +152,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
return regs;
segfault:
- lldbg("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n",
+ _alert("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n",
regs[REG_PC], dfar, dfsr);
PANIC();
return regs; /* To keep the compiler happy */
@@ -181,7 +170,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
/* Crash -- possibly showing diagnostic debug information. */
- lldbg("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n",
+ _alert("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n",
regs[REG_PC], dfar, dfsr);
PANIC();
return regs; /* To keep the compiler happy */
diff --git a/arch/arm/src/armv7-a/arm_elf.c b/arch/arm/src/armv7-a/arm_elf.c
index 57898e136af7a37afb95de9dcfe2af5b29056677..8b9528159ce2e27ba61b44b77f64d90b9c193773 100644
--- a/arch/arm/src/armv7-a/arm_elf.c
+++ b/arch/arm/src/armv7-a/arm_elf.c
@@ -74,7 +74,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_machine != EM_ARM)
{
- bdbg("Not for ARM: e_machine=%04x\n", ehdr->e_machine);
+ berr("ERROR: Not for ARM: e_machine=%04x\n", ehdr->e_machine);
return -ENOEXEC;
}
@@ -82,7 +82,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_ident[EI_CLASS] != ELFCLASS32)
{
- bdbg("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
+ berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
return -ENOEXEC;
}
@@ -94,7 +94,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB)
#endif
{
- bdbg("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
+ berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
return -ENOEXEC;
}
@@ -102,7 +102,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if ((ehdr->e_entry & 3) != 0)
{
- bdbg("Entry point is not properly aligned: %08x\n", ehdr->e_entry);
+ berr("ERROR: Entry point is not properly aligned: %08x\n", ehdr->e_entry);
return -ENOEXEC;
}
@@ -162,7 +162,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_CALL:
case R_ARM_JUMP24:
{
- bvdbg("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
+ binfo("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@@ -175,7 +175,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
offset += sym->st_value - addr;
if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000)
{
- bdbg(" ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
+ berr("ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
ELF32_R_TYPE(rel->r_info), offset);
return -EINVAL;
@@ -191,7 +191,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_ABS32:
case R_ARM_TARGET1: /* New ABI: TARGET1 always treated as ABS32 */
{
- bvdbg("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ binfo("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
*(uint32_t *)addr += sym->st_value;
@@ -200,7 +200,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_V4BX:
{
- bvdbg("Performing V4BX link at addr=%08lx [%08lx]\n",
+ binfo("Performing V4BX link at addr=%08lx [%08lx]\n",
(long)addr, (long)(*(uint32_t *)addr));
/* Preserve only Rm and the condition code */
@@ -215,7 +215,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_PREL31:
{
- bvdbg("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ binfo("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
offset = *(uint32_t *)addr + sym->st_value - addr;
@@ -226,7 +226,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_MOVW_ABS_NC:
case R_ARM_MOVT_ABS:
{
- bvdbg("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ binfo("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@@ -246,7 +246,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
break;
default:
- bdbg("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
+ berr("ERROR: Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
return -EINVAL;
}
@@ -256,6 +256,6 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
int up_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym,
uintptr_t addr)
{
- bdbg("RELA relocation not supported\n");
+ berr("ERROR: RELA relocation not supported\n");
return -ENOSYS;
}
diff --git a/arch/arm/src/armv7-a/arm_gicv2.c b/arch/arm/src/armv7-a/arm_gicv2.c
index 990a2c66dd3dd11ae2e9d58e6ab6dc020ecef858..e99eb540fdef6e55cd24f9c9cd30aeae5f380630 100644
--- a/arch/arm/src/armv7-a/arm_gicv2.c
+++ b/arch/arm/src/armv7-a/arm_gicv2.c
@@ -387,7 +387,7 @@ uint32_t *arm_decodeirq(uint32_t *regs)
regval = getreg32(GIC_ICCIAR);
irq = (regval & GIC_ICCIAR_INTID_MASK) >> GIC_ICCIAR_INTID_SHIFT;
- gicllvdbg("irq=%d\n", irq);
+ irqinfo("irq=%d\n", irq);
/* Ignore spurions IRQs. ICCIAR will report 1023 if there is no pending
* interrupt.
diff --git a/arch/arm/src/armv7-a/arm_gicv2_dump.c b/arch/arm/src/armv7-a/arm_gicv2_dump.c
index 9e4dfa340f1f97b25cdf3c55dce81d9f1610012e..23e43738da24a1716663f518a2294a08c1306a4f 100644
--- a/arch/arm/src/armv7-a/arm_gicv2_dump.c
+++ b/arch/arm/src/armv7-a/arm_gicv2_dump.c
@@ -40,12 +40,12 @@
#include
#include
-#include
+#include
#include "up_arch.h"
#include "gic.h"
-#if defined(CONFIG_ARMV7A_HAVE_GICv2) && defined(CONFIG_DEBUG_IRQ)
+#if defined(CONFIG_ARMV7A_HAVE_GICv2) && defined(CONFIG_DEBUG_IRQ_INFO)
/****************************************************************************
* Private Functions
@@ -69,22 +69,22 @@
static inline void arm_gic_dump_cpu(bool all, int irq, int nlines)
{
- lowsyslog(LOG_INFO, " CPU Interface Registers:\n");
- lowsyslog(LOG_INFO, " ICR: %08x PMR: %08x BPR: %08x IAR: %08x\n",
- getreg32(GIC_ICCICR), getreg32(GIC_ICCPMR),
- getreg32(GIC_ICCBPR), getreg32(GIC_ICCIAR));
- lowsyslog(LOG_INFO, " RPR: %08x HPIR: %08x ABPR: %08x\n",
- getreg32(GIC_ICCRPR), getreg32(GIC_ICCHPIR),
- getreg32(GIC_ICCABPR));
- lowsyslog(LOG_INFO, " AIAR: %08x AHPIR: %08x IDR: %08x\n",
- getreg32(GIC_ICCAIAR), getreg32(GIC_ICCAHPIR),
- getreg32(GIC_ICCIDR));
- lowsyslog(LOG_INFO, " APR1: %08x APR2: %08x APR3: %08x APR4: %08x\n",
- getreg32(GIC_ICCAPR1), getreg32(GIC_ICCAPR2),
- getreg32(GIC_ICCAPR3), getreg32(GIC_ICCAPR4));
- lowsyslog(LOG_INFO, " NSAPR1: %08x NSAPR2: %08x NSAPR3: %08x NSAPR4: %08x\n",
- getreg32(GIC_ICCNSAPR1), getreg32(GIC_ICCNSAPR2),
- getreg32(GIC_ICCNSAPR3), getreg32(GIC_ICCNSAPR4));
+ irqinfo(" CPU Interface Registers:\n");
+ irqinfo(" ICR: %08x PMR: %08x BPR: %08x IAR: %08x\n",
+ getreg32(GIC_ICCICR), getreg32(GIC_ICCPMR),
+ getreg32(GIC_ICCBPR), getreg32(GIC_ICCIAR));
+ irqinfo(" RPR: %08x HPIR: %08x ABPR: %08x\n",
+ getreg32(GIC_ICCRPR), getreg32(GIC_ICCHPIR),
+ getreg32(GIC_ICCABPR));
+ irqinfo(" AIAR: %08x AHPIR: %08x IDR: %08x\n",
+ getreg32(GIC_ICCAIAR), getreg32(GIC_ICCAHPIR),
+ getreg32(GIC_ICCIDR));
+ irqinfo(" APR1: %08x APR2: %08x APR3: %08x APR4: %08x\n",
+ getreg32(GIC_ICCAPR1), getreg32(GIC_ICCAPR2),
+ getreg32(GIC_ICCAPR3), getreg32(GIC_ICCAPR4));
+ irqinfo(" NSAPR1: %08x NSAPR2: %08x NSAPR3: %08x NSAPR4: %08x\n",
+ getreg32(GIC_ICCNSAPR1), getreg32(GIC_ICCNSAPR2),
+ getreg32(GIC_ICCNSAPR3), getreg32(GIC_ICCNSAPR4));
}
/****************************************************************************
@@ -110,9 +110,9 @@ static void arm_gic_dumpregs(uintptr_t regaddr, int nlines, int incr)
incr <<= 2;
for (i = 0; i < nlines; i += incr, regaddr += 16)
{
- lowsyslog(LOG_INFO, " %08x %08x %08x %08x\n",
- getreg32(regaddr), getreg32(regaddr + 4),
- getreg32(regaddr + 8), getreg32(regaddr + 12));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(regaddr), getreg32(regaddr + 4),
+ getreg32(regaddr + 8), getreg32(regaddr + 12));
}
}
@@ -135,7 +135,7 @@ static void arm_gic_dumpregs(uintptr_t regaddr, int nlines, int incr)
static inline void arm_gic_dump4(const char *name, uintptr_t regaddr,
int nlines)
{
- lowsyslog(LOG_INFO, " %s[%08lx]\n", name, (unsigned long)regaddr);
+ irqinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 4);
}
@@ -158,7 +158,7 @@ static inline void arm_gic_dump4(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump8(const char *name, uintptr_t regaddr,
int nlines)
{
- lowsyslog(LOG_INFO, " %s[%08lx]\n", name, (unsigned long)regaddr);
+ irqinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 8);
}
@@ -181,7 +181,7 @@ static inline void arm_gic_dump8(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump16(const char *name, uintptr_t regaddr,
int nlines)
{
- lowsyslog(LOG_INFO, " %s[%08lx]\n", name, (unsigned long)regaddr);
+ irqinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 16);
}
@@ -204,7 +204,7 @@ static inline void arm_gic_dump16(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump32(const char *name, uintptr_t regaddr,
int nlines)
{
- lowsyslog(LOG_INFO, " %s[%08lx]\n", name, (unsigned long)regaddr);
+ irqinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 32);
}
@@ -226,10 +226,10 @@ static inline void arm_gic_dump32(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump_distributor(bool all, int irq, int nlines)
{
- lowsyslog(LOG_INFO, " Distributor Registers:\n");
- lowsyslog(LOG_INFO, " DCR: %08x ICTR: %08x IIDR: %08x\n",
- getreg32(GIC_ICDDCR), getreg32(GIC_ICDICTR),
- getreg32(GIC_ICDIIDR));
+ irqinfo(" Distributor Registers:\n");
+ irqinfo(" DCR: %08x ICTR: %08x IIDR: %08x\n",
+ getreg32(GIC_ICDDCR), getreg32(GIC_ICDICTR),
+ getreg32(GIC_ICDIIDR));
if (all)
{
@@ -246,27 +246,27 @@ static inline void arm_gic_dump_distributor(bool all, int irq, int nlines)
}
else
{
- lowsyslog(LOG_INFO, " ISR: %08x ISER: %08x ISPR: %08x SAR: %08x\n",
- getreg32(GIC_ICDISR(irq)), getreg32(GIC_ICDISER(irq)),
- getreg32(GIC_ICDISPR(irq)), getreg32(GIC_ICDSAR(irq)));
- lowsyslog(LOG_INFO, " IPR: %08x IPTR: %08x ICFR: %08x SPISR: %08x\n",
- getreg32(GIC_ICDIPR(irq)), getreg32(GIC_ICDIPTR(irq)),
- getreg32(GIC_ICDICFR(irq)), getreg32(GIC_ICDSPISR(irq)));
- lowsyslog(LOG_INFO, " NSACR: %08x SCPR: %08x\n",
- getreg32(GIC_ICDNSACR(irq)), getreg32(GIC_ICDSCPR(irq)));
+ irqinfo(" ISR: %08x ISER: %08x ISPR: %08x SAR: %08x\n",
+ getreg32(GIC_ICDISR(irq)), getreg32(GIC_ICDISER(irq)),
+ getreg32(GIC_ICDISPR(irq)), getreg32(GIC_ICDSAR(irq)));
+ irqinfo(" IPR: %08x IPTR: %08x ICFR: %08x SPISR: %08x\n",
+ getreg32(GIC_ICDIPR(irq)), getreg32(GIC_ICDIPTR(irq)),
+ getreg32(GIC_ICDICFR(irq)), getreg32(GIC_ICDSPISR(irq)));
+ irqinfo(" NSACR: %08x SCPR: %08x\n",
+ getreg32(GIC_ICDNSACR(irq)), getreg32(GIC_ICDSCPR(irq)));
}
- lowsyslog(LOG_INFO, " PIDR[%08lx]:\n", (unsigned long)GIC_ICDPIDR(0));
- lowsyslog(LOG_INFO, " %08x %08x %08x %08x\n",
- getreg32(GIC_ICDPIDR(0)), getreg32(GIC_ICDPIDR(1)),
- getreg32(GIC_ICDPIDR(2)), getreg32(GIC_ICDPIDR(3)));
- lowsyslog(LOG_INFO, " %08x %08x %08x %08x\n",
- getreg32(GIC_ICDPIDR(4)), getreg32(GIC_ICDPIDR(5)),
- getreg32(GIC_ICDPIDR(6)));
- lowsyslog(LOG_INFO, " CIDR[%08lx]:\n", (unsigned long)GIC_ICDCIDR(0));
- lowsyslog(LOG_INFO, " %08x %08x %08x %08x\n",
- getreg32(GIC_ICDCIDR(0)), getreg32(GIC_ICDCIDR(1)),
- getreg32(GIC_ICDCIDR(2)), getreg32(GIC_ICDCIDR(3)));
+ irqinfo(" PIDR[%08lx]:\n", (unsigned long)GIC_ICDPIDR(0));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(GIC_ICDPIDR(0)), getreg32(GIC_ICDPIDR(1)),
+ getreg32(GIC_ICDPIDR(2)), getreg32(GIC_ICDPIDR(3)));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(GIC_ICDPIDR(4)), getreg32(GIC_ICDPIDR(5)),
+ getreg32(GIC_ICDPIDR(6)));
+ irqinfo(" CIDR[%08lx]:\n", (unsigned long)GIC_ICDCIDR(0));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(GIC_ICDCIDR(0)), getreg32(GIC_ICDCIDR(1)),
+ getreg32(GIC_ICDCIDR(2)), getreg32(GIC_ICDCIDR(3)));
}
/****************************************************************************
@@ -295,15 +295,15 @@ void arm_gic_dump(const char *msg, bool all, int irq)
if (all)
{
- lowsyslog(LOG_INFO, "GIC: %s NLINES=%u\n", msg, nlines);
+ irqinfo("GIC: %s NLINES=%u\n", msg, nlines);
}
else
{
- lowsyslog(LOG_INFO, "GIC: %s IRQ=%d\n", msg, irq);
+ irqinfo("GIC: %s IRQ=%d\n", msg, irq);
}
arm_gic_dump_cpu(all, irq, nlines);
arm_gic_dump_distributor(all, irq, nlines);
}
-#endif /* CONFIG_ARMV7A_HAVE_GICv2 && CONFIG_DEBUG_IRQ */
+#endif /* CONFIG_ARMV7A_HAVE_GICv2 && CONFIG_DEBUG_IRQ_INFO */
diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S
index 220026da340758619e11b7ec48c3b122957a5975..c98ab30719d5774314346cea3c4ab0ece6007022 100644
--- a/arch/arm/src/armv7-a/arm_head.S
+++ b/arch/arm/src/armv7-a/arm_head.S
@@ -169,7 +169,7 @@
/* This macro will modify r0, r1, r2 and r14 */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
.macro showprogress, code
mov r0, #\code
bl up_lowputc
diff --git a/arch/arm/src/armv7-a/arm_l2cc_pl310.c b/arch/arm/src/armv7-a/arm_l2cc_pl310.c
index 64aeaf3b8bc61cbec7dc990fee8011650c961de3..9d455e40d270d8daec5a960739716f01599fcbfe 100644
--- a/arch/arm/src/armv7-a/arm_l2cc_pl310.c
+++ b/arch/arm/src/armv7-a/arm_l2cc_pl310.c
@@ -411,7 +411,7 @@ void up_l2ccinitialize(void)
putreg32(L2CC_CR_L2CEN, L2CC_CR);
}
- lldbg("(%d ways) * (%d bytes/way) = %d bytes\n",
+ sinfo("(%d ways) * (%d bytes/way) = %d bytes\n",
PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE);
}
diff --git a/arch/arm/src/armv7-a/arm_pghead.S b/arch/arm/src/armv7-a/arm_pghead.S
index bc4c99ce26da187dc4508f79e9737b4663ca1fbf..1a546c813d4007ea2105fb0ae544df94dc469956 100644
--- a/arch/arm/src/armv7-a/arm_pghead.S
+++ b/arch/arm/src/armv7-a/arm_pghead.S
@@ -194,7 +194,7 @@
/* This macro will modify r0, r1, r2 and r14 */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
.macro showprogress, code
mov r0, #\code
bl up_lowputc
diff --git a/arch/arm/src/armv7-a/arm_prefetchabort.c b/arch/arm/src/armv7-a/arm_prefetchabort.c
index bdd28c4a3aa72505bd66d469e5d6bcf24dddeee5..0bb8cd37932f68ed9c101f5ad575b3a7f7f16f38 100644
--- a/arch/arm/src/armv7-a/arm_prefetchabort.c
+++ b/arch/arm/src/armv7-a/arm_prefetchabort.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-a/arm_prefetchabort.c
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
@@ -97,8 +86,8 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
* virtual addresses.
*/
- pglldbg("VADDR: %08x VBASE: %08x VEND: %08x\n",
- regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
+ pginfo("VADDR: %08x VBASE: %08x VEND: %08x\n",
+ regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
if (regs[REG_R15] >= PG_PAGED_VBASE && regs[REG_R15] < PG_PAGED_VEND)
{
@@ -134,7 +123,7 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
}
else
{
- lldbg("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n",
+ _alert("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n",
regs[REG_PC], ifar, ifsr);
PANIC();
}
@@ -154,7 +143,7 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
/* Crash -- possibly showing diagnostic debug information. */
- lldbg("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n",
+ _alert("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n",
regs[REG_PC], ifar, ifsr);
PANIC();
return regs; /* To keep the compiler happy */
diff --git a/arch/arm/src/armv7-a/arm_releasepending.c b/arch/arm/src/armv7-a/arm_releasepending.c
index 9696e931c0bdb7643535b0aa3e795eb237cb9c8c..7afc6989a75829f647ee14ba35e2a6b3ef991415 100644
--- a/arch/arm/src/armv7-a/arm_releasepending.c
+++ b/arch/arm/src/armv7-a/arm_releasepending.c
@@ -67,7 +67,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
- slldbg("From TCB=%p\n", rtcb);
+ sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */
diff --git a/arch/arm/src/armv7-a/arm_reprioritizertr.c b/arch/arm/src/armv7-a/arm_reprioritizertr.c
index d4b2699f6dd01f2a3cc0c3be38038f1961c18c6e..4381178e05b311e620c620b6d9465e10cec5a333 100644
--- a/arch/arm/src/armv7-a/arm_reprioritizertr.c
+++ b/arch/arm/src/armv7-a/arm_reprioritizertr.c
@@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
- slldbg("TCB=%p PRI=%d\n", tcb, priority);
+ sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just
diff --git a/arch/arm/src/armv7-a/arm_schedulesigaction.c b/arch/arm/src/armv7-a/arm_schedulesigaction.c
index 3dfe5fc285f7c9a5f4de4a519107067c5ca1bb34..89df348ba039c8942f4c76ac3692b48be245482f 100644
--- a/arch/arm/src/armv7-a/arm_schedulesigaction.c
+++ b/arch/arm/src/armv7-a/arm_schedulesigaction.c
@@ -94,7 +94,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
{
irqstate_t flags;
- sdbg("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+ sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
/* Make sure that interrupts are disabled */
@@ -108,7 +108,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* to the currently executing task.
*/
- sdbg("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
+ sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
if (tcb == this_task())
{
diff --git a/arch/arm/src/armv7-a/arm_sigdeliver.c b/arch/arm/src/armv7-a/arm_sigdeliver.c
index 32f1e0b40d1219f98a282c6ca98fa5c7070bcc6a..be720a464c3550d648b6c4ec52f9de108bc54ba8 100644
--- a/arch/arm/src/armv7-a/arm_sigdeliver.c
+++ b/arch/arm/src/armv7-a/arm_sigdeliver.c
@@ -83,7 +83,7 @@ void up_sigdeliver(void)
board_autoled_on(LED_SIGNAL);
- sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
+ sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
ASSERT(rtcb->xcp.sigdeliver != NULL);
@@ -114,7 +114,7 @@ void up_sigdeliver(void)
* errno that is needed by the user logic (it is probably EINTR).
*/
- sdbg("Resuming\n");
+ sinfo("Resuming\n");
(void)up_irq_save();
rtcb->pterrno = saved_errno;
diff --git a/arch/arm/src/armv7-a/arm_syscall.c b/arch/arm/src/armv7-a/arm_syscall.c
index 854ece3de2cdf789db4e59069a03236733dd78da..77b33b45f4be7954bc50389d3c3d8ccade7776eb 100644
--- a/arch/arm/src/armv7-a/arm_syscall.c
+++ b/arch/arm/src/armv7-a/arm_syscall.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-a/arm_syscall.c
*
- * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013-2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -65,17 +54,6 @@
#include "addrenv.h"
#include "up_internal.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-/* Debug ********************************************************************/
-
-#if defined(CONFIG_DEBUG_SYSCALL)
-# define svcdbg(format, ...) lldbg(format, ##__VA_ARGS__)
-#else
-# define svcdbg(x...)
-#endif
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -178,16 +156,14 @@ uint32_t *arm_syscall(uint32_t *regs)
* and R1..R7 = variable number of arguments depending on the system call.
*/
-#if defined(CONFIG_DEBUG_SYSCALL)
- svcdbg("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
- svcdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- svcdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
- svcdbg("CPSR: %08x\n", regs[REG_CPSR]);
-#endif
+ svcinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
/* Handle the SVCall according to the command in R0 */
@@ -480,7 +456,7 @@ uint32_t *arm_syscall(uint32_t *regs)
regs[REG_R0] -= CONFIG_SYS_RESERVED;
#else
- svcdbg("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
+ svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
#endif
#ifdef CONFIG_ARCH_KERNEL_STACK
@@ -501,18 +477,16 @@ uint32_t *arm_syscall(uint32_t *regs)
break;
}
-#if defined(CONFIG_DEBUG_SYSCALL)
/* Report what happened */
- svcdbg("SYSCALL Exit: regs: %p\n", regs);
- svcdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- svcdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ svcinfo("SYSCALL Exit: regs: %p\n", regs);
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
- svcdbg("CPSR: %08x\n", regs[REG_CPSR]);
-#endif
+ svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
/* Return the last value of curent_regs. This supports context switches
* on return from the exception. That capability is only used with the
@@ -526,7 +500,7 @@ uint32_t *arm_syscall(uint32_t *regs)
uint32_t *arm_syscall(uint32_t *regs)
{
- lldbg("SYSCALL from 0x%x\n", regs[REG_PC]);
+ _alert("SYSCALL from 0x%x\n", regs[REG_PC]);
CURRENT_REGS = regs;
PANIC();
}
diff --git a/arch/arm/src/armv7-a/arm_undefinedinsn.c b/arch/arm/src/armv7-a/arm_undefinedinsn.c
index 0c051d9dd916accbf64c8e0d35fb5a5ad801071d..54dbcc25b8a2aa0ce2da4506083a11934f1fef5e 100644
--- a/arch/arm/src/armv7-a/arm_undefinedinsn.c
+++ b/arch/arm/src/armv7-a/arm_undefinedinsn.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-a/arm_undefinedinsn.c
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -68,7 +57,7 @@
uint32_t *arm_undefinedinsn(uint32_t *regs)
{
- lldbg("Undefined instruction at 0x%x\n", regs[REG_PC]);
+ _alert("Undefined instruction at 0x%x\n", regs[REG_PC]);
CURRENT_REGS = regs;
PANIC();
return regs; /* To keep the compiler happy */
diff --git a/arch/arm/src/armv7-a/gic.h b/arch/arm/src/armv7-a/gic.h
index cc6ee4833004f661ec96a5f9d248d23944a7ff6b..8774065135069c3cc747a2eeca47d89e8e876e6e 100644
--- a/arch/arm/src/armv7-a/gic.h
+++ b/arch/arm/src/armv7-a/gic.h
@@ -590,21 +590,6 @@
#define GIC_IRQ_SPI 32 /* First SPI interrupt ID */
-/* General Macro Definitions ************************************************/
-/* Debug */
-
-#ifdef CONFIG_DEBUG_IRQ
-# define gicdbg(format, ...) dbg(format, ##__VA_ARGS__)
-# define giclldbg(format, ...) lldbg(format, ##__VA_ARGS__)
-# define gicvdbg(format, ...) vdbg(format, ##__VA_ARGS__)
-# define gicllvdbg(format, ...) llvdbg(format, ##__VA_ARGS__)
-#else
-# define gicdbg(x...)
-# define giclldbg(x...)
-# define gicvdbg(x...)
-# define gicllvdbg(x...)
-#endif
-
/****************************************************************************
* Inline Functions
****************************************************************************/
@@ -817,7 +802,7 @@ int arm_pause_handler(int irq, FAR void *context);
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_IRQ
+#ifdef CONFIG_DEBUG_IRQ_INFO
void arm_gic_dump(const char *msg, bool all, int irq);
#else
# define arm_gic_dump(m,a,i)
diff --git a/arch/arm/src/armv7-m/Kconfig b/arch/arm/src/armv7-m/Kconfig
index 406e2e46624be926494b130312a91d539bc3c02b..404dce07538ef771a6b176e8109dedf20fc6313e 100644
--- a/arch/arm/src/armv7-m/Kconfig
+++ b/arch/arm/src/armv7-m/Kconfig
@@ -160,6 +160,7 @@ config ARMV7M_STACKCHECK
config ARMV7M_ITMSYSLOG
bool "ITM SYSLOG support"
default n
+ select ARCH_SYSLOG
select SYSLOG
---help---
Enable hooks to support ITM syslog output. This requires additional
diff --git a/arch/arm/src/armv7-m/itm_syslog.h b/arch/arm/src/armv7-m/itm_syslog.h
index 1b42be2ea8e442ee412ebf9169103b7c8fa9f289..40f71624f57dad9714603f428ef48e839f0d843d 100644
--- a/arch/arm/src/armv7-m/itm_syslog.h
+++ b/arch/arm/src/armv7-m/itm_syslog.h
@@ -57,7 +57,7 @@
*
****************************************************************************/
-#if defined(CONFIG_SYSLOG) || defined(CONFIG_ARMV7M_ITMSYSLOG)
+#ifdef CONFIG_ARMV7M_ITMSYSLOG
void itm_syslog_initialize(void);
#else
# define itm_syslog_initialize()
diff --git a/arch/arm/src/armv7-m/mpu.h b/arch/arm/src/armv7-m/mpu.h
index 310c21a90912303363435c59a6dbf1f348386ca2..22348a23a685653a1555b14728ab37c30596f9e1 100644
--- a/arch/arm/src/armv7-m/mpu.h
+++ b/arch/arm/src/armv7-m/mpu.h
@@ -219,12 +219,13 @@ uint32_t mpu_subregion(uintptr_t base, size_t size, uint8_t l2size);
static inline void mpu_showtype(void)
{
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_SCHED_INFO
uint32_t regval = getreg32(MPU_TYPE);
- dbg("%s MPU Regions: data=%d instr=%d\n",
- (regval & MPU_TYPE_SEPARATE) != 0 ? "Separate" : "Unified",
- (regval & MPU_TYPE_DREGION_MASK) >> MPU_TYPE_DREGION_SHIFT,
- (regval & MPU_TYPE_IREGION_MASK) >> MPU_TYPE_IREGION_SHIFT);
+
+ sinfo("%s MPU Regions: data=%d instr=%d\n",
+ (regval & MPU_TYPE_SEPARATE) != 0 ? "Separate" : "Unified",
+ (regval & MPU_TYPE_DREGION_MASK) >> MPU_TYPE_DREGION_SHIFT,
+ (regval & MPU_TYPE_IREGION_MASK) >> MPU_TYPE_IREGION_SHIFT);
#endif
}
diff --git a/arch/arm/src/armv7-m/up_assert.c b/arch/arm/src/armv7-m/up_assert.c
index 0f6fa00d219488401220dc6d35a5d469786f66d8..b34cfc73950343db2ab09940953f55a9daf14fab 100644
--- a/arch/arm/src/armv7-m/up_assert.c
+++ b/arch/arm/src/armv7-m/up_assert.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-m/up_assert.c
*
- * Copyright (C) 2009-2010, 2012-2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009-2010, 2012-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -75,23 +64,6 @@
# undef CONFIG_ARCH_USBDUMP
#endif
-/* The following is just intended to keep some ugliness out of the mainline
- * code. We are going to print the task name if:
- *
- * CONFIG_TASK_NAME_SIZE > 0 && <-- The task has a name
- * (defined(CONFIG_DEBUG) || <-- And the debug is enabled (lldbg used)
- * defined(CONFIG_ARCH_STACKDUMP) <-- Or lowsyslog() is used
- */
-
-#undef CONFIG_PRINT_TASKNAME
-#if CONFIG_TASK_NAME_SIZE > 0 && (defined(CONFIG_DEBUG) || defined(CONFIG_ARCH_STACKDUMP))
-# define CONFIG_PRINT_TASKNAME 1
-#endif
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -125,7 +97,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base)
for (stack = sp & ~0x1f; stack < stack_base; stack += 32)
{
uint32_t *ptr = (uint32_t *)stack;
- lldbg("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
stack, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
@@ -143,12 +115,12 @@ static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg)
{
/* Dump interesting properties of this task */
-#ifdef CONFIG_PRINT_TASKNAME
- lldbg("%s: PID=%d Stack Used=%lu of %lu\n",
+#if CONFIG_TASK_NAME_SIZE > 0
+ _alert("%s: PID=%d Stack Used=%lu of %lu\n",
tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#else
- lldbg("PID: %d Stack Used=%lu of %lu\n",
+ _alert("PID: %d Stack Used=%lu of %lu\n",
tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#endif
@@ -183,29 +155,29 @@ static inline void up_registerdump(void)
{
/* Yes.. dump the interrupt registers */
- lldbg("R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
- lldbg("R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
#ifdef CONFIG_ARMV7M_USEBASEPRI
- lldbg("xPSR: %08x BASEPRI: %08x CONTROL: %08x\n",
+ _alert("xPSR: %08x BASEPRI: %08x CONTROL: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI],
getcontrol());
#else
- lldbg("xPSR: %08x PRIMASK: %08x CONTROL: %08x\n",
+ _alert("xPSR: %08x PRIMASK: %08x CONTROL: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
getcontrol());
#endif
#ifdef REG_EXC_RETURN
- lldbg("EXC_RETURN: %08x\n", CURRENT_REGS[REG_EXC_RETURN]);
+ _alert("EXC_RETURN: %08x\n", CURRENT_REGS[REG_EXC_RETURN]);
#endif
}
}
@@ -226,7 +198,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
/* Let vsyslog do the real work */
va_start(ap, fmt);
- ret = lowvsyslog(LOG_INFO, fmt, ap);
+ ret = vsyslog(LOG_EMERG, fmt, ap);
va_end(ap);
return ret;
}
@@ -275,12 +247,12 @@ static void up_dumpstate(void)
/* Show interrupt stack info */
- lldbg("sp: %08x\n", sp);
- lldbg("IRQ stack:\n");
- lldbg(" base: %08x\n", istackbase);
- lldbg(" size: %08x\n", istacksize);
+ _alert("sp: %08x\n", sp);
+ _alert("IRQ stack:\n");
+ _alert(" base: %08x\n", istackbase);
+ _alert(" size: %08x\n", istacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_intstack());
+ _alert(" used: %08x\n", up_check_intstack());
#endif
/* Does the current stack pointer lie within the interrupt
@@ -302,14 +274,14 @@ static void up_dumpstate(void)
if (CURRENT_REGS)
{
sp = CURRENT_REGS[REG_R13];
- lldbg("sp: %08x\n", sp);
+ _alert("sp: %08x\n", sp);
}
- lldbg("User stack:\n");
- lldbg(" base: %08x\n", ustackbase);
- lldbg(" size: %08x\n", ustacksize);
+ _alert("User stack:\n");
+ _alert(" base: %08x\n", ustackbase);
+ _alert(" size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_tcbstack(rtcb));
+ _alert(" used: %08x\n", up_check_tcbstack(rtcb));
#endif
/* Dump the user stack if the stack pointer lies within the allocated user
@@ -325,11 +297,11 @@ static void up_dumpstate(void)
/* Show user stack info */
- lldbg("sp: %08x\n", sp);
- lldbg("stack base: %08x\n", ustackbase);
- lldbg("stack size: %08x\n", ustacksize);
+ _alert("sp: %08x\n", sp);
+ _alert("stack base: %08x\n", ustackbase);
+ _alert("stack size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg("stack used: %08x\n", up_check_tcbstack(rtcb));
+ _alert("stack used: %08x\n", up_check_tcbstack(rtcb));
#endif
/* Dump the user stack if the stack pointer lies within the allocated user
@@ -338,7 +310,7 @@ static void up_dumpstate(void)
if (sp > ustackbase || sp <= ustackbase - ustacksize)
{
- lldbg("ERROR: Stack pointer is not within the allocated stack\n");
+ _alert("ERROR: Stack pointer is not within the allocated stack\n");
}
else
{
@@ -403,17 +375,17 @@ static void _up_assert(int errorcode)
void up_assert(const uint8_t *filename, int lineno)
{
-#ifdef CONFIG_PRINT_TASKNAME
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
struct tcb_s *rtcb = this_task();
#endif
board_autoled_on(LED_ASSERTION);
-#ifdef CONFIG_PRINT_TASKNAME
- lldbg("Assertion failed at file:%s line: %d task: %s\n",
+#if CONFIG_TASK_NAME_SIZE > 0
+ _alert("Assertion failed at file:%s line: %d task: %s\n",
filename, lineno, rtcb->name);
#else
- lldbg("Assertion failed at file:%s line: %d\n",
+ _alert("Assertion failed at file:%s line: %d\n",
filename, lineno);
#endif
diff --git a/arch/arm/src/armv7-m/up_elf.c b/arch/arm/src/armv7-m/up_elf.c
index bf492f1acaa5ac25ac8a7c1a0aec6fd73f49866f..f2e0cdd97925d84fb99f1479a22b4cb980019bfe 100644
--- a/arch/arm/src/armv7-m/up_elf.c
+++ b/arch/arm/src/armv7-m/up_elf.c
@@ -82,7 +82,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_machine != EM_ARM)
{
- bdbg("Not for ARM: e_machine=%04x\n", ehdr->e_machine);
+ berr("ERROR: Not for ARM: e_machine=%04x\n", ehdr->e_machine);
return -ENOEXEC;
}
@@ -90,7 +90,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_ident[EI_CLASS] != ELFCLASS32)
{
- bdbg("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
+ berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
return -ENOEXEC;
}
@@ -102,7 +102,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB)
#endif
{
- bdbg("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
+ berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
return -ENOEXEC;
}
@@ -164,7 +164,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_CALL:
case R_ARM_JUMP24:
{
- bvdbg("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
+ binfo("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@@ -177,7 +177,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
offset += sym->st_value - addr;
if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000)
{
- bdbg(" ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
+ berr("ERROR: ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
ELF32_R_TYPE(rel->r_info), offset);
return -EINVAL;
@@ -193,7 +193,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_ABS32:
case R_ARM_TARGET1: /* New ABI: TARGET1 always treated as ABS32 */
{
- bvdbg("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ binfo("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
*(uint32_t *)addr += sym->st_value;
@@ -204,7 +204,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_TARGET2: /* TARGET2 is a platform-specific relocation: gcc-arm-none-eabi
* performs a self relocation */
{
- bvdbg("Performing TARGET2 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ binfo("Performing TARGET2 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
*(uint32_t *)addr += sym->st_value - addr;
@@ -253,7 +253,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
upper_insn = (uint32_t)(*(uint16_t *)addr);
lower_insn = (uint32_t)(*(uint16_t *)(addr + 2));
- bvdbg("Performing THM_JUMP24 [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
+ binfo("Performing THM_JUMP24 [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (int)upper_insn, (int)lower_insn,
sym, (long)sym->st_value);
@@ -287,7 +287,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
/* And perform the relocation */
- bvdbg(" S=%d J1=%d J2=%d offset=%08lx branch target=%08lx\n",
+ binfo(" S=%d J1=%d J2=%d offset=%08lx branch target=%08lx\n",
S, J1, J2, (long)offset, offset + sym->st_value - addr);
offset += sym->st_value - addr;
@@ -298,7 +298,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
if (ELF32_ST_TYPE(sym->st_info) == STT_FUNC && (offset & 1) == 0)
{
- bdbg(" ERROR: JUMP24 [%d] requires odd offset, offset=%08lx\n",
+ berr("ERROR: ERROR: JUMP24 [%d] requires odd offset, offset=%08lx\n",
ELF32_R_TYPE(rel->r_info), offset);
return -EINVAL;
@@ -308,7 +308,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
if (offset <= (int32_t)0xff000000 || offset >= (int32_t)0x01000000)
{
- bdbg(" ERROR: JUMP24 [%d] relocation out of range, branch taget=%08lx\n",
+ berr("ERROR: ERROR: JUMP24 [%d] relocation out of range, branch taget=%08lx\n",
ELF32_R_TYPE(rel->r_info), offset);
return -EINVAL;
@@ -328,14 +328,14 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
lower_insn = ((lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | ((offset >> 1) & 0x07ff));
*(uint16_t *)(addr + 2) = (uint16_t)lower_insn;
- bvdbg(" S=%d J1=%d J2=%d insn [%04x %04x]\n",
+ binfo(" S=%d J1=%d J2=%d insn [%04x %04x]\n",
S, J1, J2, (int)upper_insn, (int)lower_insn);
}
break;
case R_ARM_V4BX:
{
- bvdbg("Performing V4BX link at addr=%08lx [%08lx]\n",
+ binfo("Performing V4BX link at addr=%08lx [%08lx]\n",
(long)addr, (long)(*(uint32_t *)addr));
/* Preserve only Rm and the condition code */
@@ -350,7 +350,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_PREL31:
{
- bvdbg("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ binfo("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
offset = *(uint32_t *)addr + sym->st_value - addr;
@@ -361,7 +361,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_MOVW_ABS_NC:
case R_ARM_MOVT_ABS:
{
- bvdbg("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ binfo("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@@ -416,7 +416,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
upper_insn = (uint32_t)(*(uint16_t *)addr);
lower_insn = (uint32_t)(*(uint16_t *)(addr + 2));
- bvdbg("Performing THM_MOVx [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
+ binfo("Performing THM_MOVx [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (int)upper_insn, (int)lower_insn,
sym, (long)sym->st_value);
@@ -433,7 +433,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
/* And perform the relocation */
- bvdbg(" offset=%08lx branch target=%08lx\n",
+ binfo(" offset=%08lx branch target=%08lx\n",
(long)offset, offset + sym->st_value);
offset += sym->st_value;
@@ -455,13 +455,13 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
(offset & 0x00ff));
*(uint16_t *)(addr + 2) = (uint16_t)lower_insn;
- bvdbg(" insn [%04x %04x]\n",
+ binfo(" insn [%04x %04x]\n",
(int)upper_insn, (int)lower_insn);
}
break;
default:
- bdbg("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
+ berr("ERROR: Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
return -EINVAL;
}
@@ -471,7 +471,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
int up_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym,
uintptr_t addr)
{
- bdbg("RELA relocation not supported\n");
+ berr("ERROR: RELA relocation not supported\n");
return -ENOSYS;
}
diff --git a/arch/arm/src/armv7-m/up_hardfault.c b/arch/arm/src/armv7-m/up_hardfault.c
index 807d45cc43922595c1dbb7a3c92a0235acbf76e9..fe133cc4f3782fe2e96aadbac49daf970f32f9b3 100644
--- a/arch/arm/src/armv7-m/up_hardfault.c
+++ b/arch/arm/src/armv7-m/up_hardfault.c
@@ -60,25 +60,13 @@
*/
#ifdef CONFIG_DEBUG_HARDFAULT
-# define hfdbg(format, ...) lldbg(format, ##__VA_ARGS__)
+# define hfalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
-# define hfdbg(x...)
+# define hfalert(x...)
#endif
#define INSN_SVC0 0xdf00 /* insn: svc 0 */
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -127,7 +115,7 @@ int up_hardfault(int irq, FAR void *context)
/* Fetch the instruction that caused the Hard fault */
uint16_t insn = *pc;
- hfdbg(" PC: %p INSN: %04x\n", pc, insn);
+ hfalert(" PC: %p INSN: %04x\n", pc, insn);
/* If this was the instruction 'svc 0', then forward processing
* to the SVCall handler
@@ -135,7 +123,7 @@ int up_hardfault(int irq, FAR void *context)
if (insn == INSN_SVC0)
{
- hfdbg("Forward SVCall\n");
+ hfalert("Forward SVCall\n");
return up_svcall(irq, context);
}
}
@@ -143,43 +131,43 @@ int up_hardfault(int irq, FAR void *context)
/* Dump some hard fault info */
- hfdbg("Hard Fault:\n");
- hfdbg(" IRQ: %d regs: %p\n", irq, regs);
- hfdbg(" BASEPRI: %08x PRIMASK: %08x IPSR: %08x CONTROL: %08x\n",
- getbasepri(), getprimask(), getipsr(), getcontrol());
- hfdbg(" CFAULTS: %08x HFAULTS: %08x DFAULTS: %08x BFAULTADDR: %08x AFAULTS: %08x\n",
- getreg32(NVIC_CFAULTS), getreg32(NVIC_HFAULTS),
- getreg32(NVIC_DFAULTS), getreg32(NVIC_BFAULT_ADDR),
- getreg32(NVIC_AFAULTS));
- hfdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- hfdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ hfalert("Hard Fault:\n");
+ hfalert(" IRQ: %d regs: %p\n", irq, regs);
+ hfalert(" BASEPRI: %08x PRIMASK: %08x IPSR: %08x CONTROL: %08x\n",
+ getbasepri(), getprimask(), getipsr(), getcontrol());
+ hfalert(" CFAULTS: %08x HFAULTS: %08x DFAULTS: %08x BFAULTADDR: %08x AFAULTS: %08x\n",
+ getreg32(NVIC_CFAULTS), getreg32(NVIC_HFAULTS),
+ getreg32(NVIC_DFAULTS), getreg32(NVIC_BFAULT_ADDR),
+ getreg32(NVIC_AFAULTS));
+ hfalert(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ hfalert(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
#ifdef CONFIG_ARMV7M_USEBASEPRI
# ifdef REG_EXC_RETURN
- hfdbg(" xPSR: %08x BASEPRI: %08x EXC_RETURN: %08x (saved)\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI],
- CURRENT_REGS[REG_EXC_RETURN]);
+ hfalert(" xPSR: %08x BASEPRI: %08x EXC_RETURN: %08x (saved)\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI],
+ CURRENT_REGS[REG_EXC_RETURN]);
# else
- hfdbg(" xPSR: %08x BASEPRI: %08x (saved)\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI]);
+ hfalert(" xPSR: %08x BASEPRI: %08x (saved)\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI]);
# endif
#else
# ifdef REG_EXC_RETURN
- hfdbg(" xPSR: %08x PRIMASK: %08x EXC_RETURN: %08x (saved)\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
- CURRENT_REGS[REG_EXC_RETURN]);
+ hfalert(" xPSR: %08x PRIMASK: %08x EXC_RETURN: %08x (saved)\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
+ CURRENT_REGS[REG_EXC_RETURN]);
# else
- hfdbg(" xPSR: %08x PRIMASK: %08x (saved)\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
+ hfalert(" xPSR: %08x PRIMASK: %08x (saved)\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
# endif
#endif
(void)up_irq_save();
- lldbg("PANIC!!! Hard fault: %08x\n", getreg32(NVIC_HFAULTS));
+ _alert("PANIC!!! Hard fault: %08x\n", getreg32(NVIC_HFAULTS));
PANIC();
return OK;
}
diff --git a/arch/arm/src/armv7-m/up_itm_syslog.c b/arch/arm/src/armv7-m/up_itm_syslog.c
index 94b499879a79b9111a9225f50f6990a66e6059fb..d63fed09adb238e571c2cdd74f731759cb67e848 100644
--- a/arch/arm/src/armv7-m/up_itm_syslog.c
+++ b/arch/arm/src/armv7-m/up_itm_syslog.c
@@ -2,7 +2,7 @@
* arch/arm/src/armv7-m/up_itm_syslog.c
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- * Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
* Authors: Pierre-noel Bouteville
* Gregory Nutt
*
@@ -52,7 +52,7 @@
#include "up_arch.h"
#include "itm_syslog.h"
-#if defined(CONFIG_SYSLOG) || defined(CONFIG_ARMV7M_ITMSYSLOG)
+#ifdef CONFIG_ARMV7M_ITMSYSLOG
/****************************************************************************
* Pre-processor Definitions
@@ -72,6 +72,73 @@
# define CONFIG_ARMV7M_ITMSYSLOG_PORT 0
#endif
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* SYSLOG channel methods */
+
+static int itm_putc(int ch);
+static int itm_flush(void);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* This structure describes the ITM SYSLOG channel */
+
+static const struct syslog_channel_s g_itm_channel =
+{
+ .sc_putc = itm_putc,
+ .sc_force = itm_putc,
+ .sc_flush = itm_flush,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: itm_putc
+ *
+ * Description:
+ * This is the low-level system logging interface.
+ *
+ ****************************************************************************/
+
+static int itm_putc(int ch)
+{
+ /* ITM enabled */
+
+ if ((getreg32(ITM_TCR) & ITM_TCR_ITMENA_Msk) == 0)
+ {
+ return EOF;
+ }
+
+ /* ITM Port "CONFIG_ARMV7M_ITMSYSLOG_PORT" enabled */
+
+ if (getreg32(ITM_TER) & (1 << CONFIG_ARMV7M_ITMSYSLOG_PORT))
+ {
+ while (getreg32(ITM_PORT(CONFIG_ARMV7M_ITMSYSLOG_PORT)) == 0);
+ putreg8((uint8_t)ch, ITM_PORT(CONFIG_ARMV7M_ITMSYSLOG_PORT));
+ }
+
+ return ch;
+}
+
+/****************************************************************************
+ * Name: itm_flush
+ *
+ * Description:
+ * A dummy FLUSH method
+ *
+ ****************************************************************************/
+
+static int itm_flush(void)
+{
+ return OK;
+}
+
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -116,38 +183,10 @@ void itm_syslog_initialize(void)
putreg32(0x0001000d, ITM_TCR);
putreg32(0x00000100, TPI_FFCR);
putreg32(0xffffffff, ITM_TER); /* Enable 32 Ports */
-}
-/****************************************************************************
- * Name: syslog_putc
- *
- * Description:
- * This is the low-level system logging interface. The debugging/syslogging
- * interfaces are syslog() and lowsyslog(). The difference is that
- * the syslog() internface writes to fd=1 (stdout) whereas lowsyslog() uses
- * a lower level interface that works from interrupt handlers. This
- * function is the low-level interface used to implement lowsyslog().
- *
- ****************************************************************************/
+ /* Setup the SYSLOG channel */
-int syslog_putc(int ch)
-{
- /* ITM enabled */
-
- if ((getreg32(ITM_TCR) & ITM_TCR_ITMENA_Msk) == 0)
- {
- return EOF;
- }
-
- /* ITM Port "CONFIG_ARMV7M_ITMSYSLOG_PORT" enabled */
-
- if (getreg32(ITM_TER) & (1 << CONFIG_ARMV7M_ITMSYSLOG_PORT))
- {
- while (getreg32(ITM_PORT(CONFIG_ARMV7M_ITMSYSLOG_PORT)) == 0);
- putreg8((uint8_t)ch, ITM_PORT(CONFIG_ARMV7M_ITMSYSLOG_PORT));
- }
-
- return ch;
+ (void)syslog_channel(&g_itm_channel);
}
-#endif /* CONFIG_SYSLOG && CONFIG_ARMV7M_ITMSYSLOG */
+#endif /* CONFIG_ARMV7M_ITMSYSLOG */
diff --git a/arch/arm/src/armv7-m/up_memfault.c b/arch/arm/src/armv7-m/up_memfault.c
index 145dba531d0d788fc61d212c3f9ec860f0e2da35..f883209b769ed75e256c320e25a81fb513c0f7bd 100644
--- a/arch/arm/src/armv7-m/up_memfault.c
+++ b/arch/arm/src/armv7-m/up_memfault.c
@@ -55,23 +55,13 @@
#undef DEBUG_MEMFAULTS /* Define to debug memory management faults */
#ifdef DEBUG_MEMFAULTS
-# define mfdbg(format, ...) lldbg(format, ##__VA_ARGS__)
+# define mferr(format, ...) _alert(format, ##__VA_ARGS__)
+# define mfinfo(format, ...) _alert(format, ##__VA_ARGS__)
#else
-# define mfdbg(x...)
+# define mferr(x...)
+# define mfinfo(x...)
#endif
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -92,36 +82,36 @@ int up_memfault(int irq, FAR void *context)
/* Dump some memory management fault info */
(void)up_irq_save();
- lldbg("PANIC!!! Memory Management Fault:\n");
- mfdbg(" IRQ: %d context: %p\n", irq, regs);
- lldbg(" CFAULTS: %08x MMFAR: %08x\n",
+ _alert("PANIC!!! Memory Management Fault:\n");
+ mfinfo(" IRQ: %d context: %p\n", irq, regs);
+ _alert(" CFAULTS: %08x MMFAR: %08x\n",
getreg32(NVIC_CFAULTS), getreg32(NVIC_MEMMANAGE_ADDR));
- mfdbg(" BASEPRI: %08x PRIMASK: %08x IPSR: %08x CONTROL: %08x\n",
- getbasepri(), getprimask(), getipsr(), getcontrol());
- mfdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- mfdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ mfinfo(" BASEPRI: %08x PRIMASK: %08x IPSR: %08x CONTROL: %08x\n",
+ getbasepri(), getprimask(), getipsr(), getcontrol());
+ mfinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ mfinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
#ifdef CONFIG_ARMV7M_USEBASEPRI
# ifdef REG_EXC_RETURN
- mfdbg(" xPSR: %08x BASEPRI: %08x EXC_RETURN: %08x (saved)\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI],
- CURRENT_REGS[REG_EXC_RETURN]);
+ mfinfo(" xPSR: %08x BASEPRI: %08x EXC_RETURN: %08x (saved)\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI],
+ CURRENT_REGS[REG_EXC_RETURN]);
# else
- mfdbg(" xPSR: %08x BASEPRI: %08x (saved)\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI]);
+ mfinfo(" xPSR: %08x BASEPRI: %08x (saved)\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI]);
# endif
#else
# ifdef REG_EXC_RETURN
- mfdbg(" xPSR: %08x PRIMASK: %08x EXC_RETURN: %08x (saved)\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
- CURRENT_REGS[REG_EXC_RETURN]);
+ mfinfo(" xPSR: %08x PRIMASK: %08x EXC_RETURN: %08x (saved)\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
+ CURRENT_REGS[REG_EXC_RETURN]);
# else
- mfdbg(" xPSR: %08x PRIMASK: %08x (saved)\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
+ mfinfo(" xPSR: %08x PRIMASK: %08x (saved)\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
# endif
#endif
diff --git a/arch/arm/src/armv7-m/up_ramvec_attach.c b/arch/arm/src/armv7-m/up_ramvec_attach.c
index 3700cdb00bc1542ff0b44e29585e3363475cded5..6b954803e03db95599e75c5d3066d61c2cd80b36 100644
--- a/arch/arm/src/armv7-m/up_ramvec_attach.c
+++ b/arch/arm/src/armv7-m/up_ramvec_attach.c
@@ -49,39 +49,6 @@
#ifdef CONFIG_ARCH_RAMVECTORS
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing the interrupt
- * config. NOTE: that only lldbg types are used so that the output is
- * immediately available.
- */
-
-#ifdef CONFIG_DEBUG_IRQ
-# define intdbg lldbg
-# define intvdbg llvdbg
-#else
-# define intdbg(x...)
-# define intvdbg(x...)
-#endif
-
-/****************************************************************************
- * Private Type Declarations
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -103,7 +70,7 @@ int up_ramvec_attach(int irq, up_vector_t vector)
{
int ret = -EINVAL;
- intvdbg("%s IRQ%d\n", vector ? "Attaching" : "Detaching", irq);
+ irqinfo("%s IRQ%d\n", vector ? "Attaching" : "Detaching", irq);
if ((unsigned)irq < NR_VECTORS)
{
diff --git a/arch/arm/src/armv7-m/up_ramvec_initialize.c b/arch/arm/src/armv7-m/up_ramvec_initialize.c
index 80b176d67403d0eaf8d14cb880ac1b3e99946bc7..277862bcf36db15d4528da6121089e614c9c1ac2 100644
--- a/arch/arm/src/armv7-m/up_ramvec_initialize.c
+++ b/arch/arm/src/armv7-m/up_ramvec_initialize.c
@@ -71,24 +71,6 @@
#define RAMVEC_ALIGN ((~NVIC_VECTAB_TBLOFF_MASK & 0xffff) + 1)
-/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing the interrupt
- * config. NOTE: that only lldbg types are used so that the output is
- * immediately available.
- */
-
-#ifdef CONFIG_DEBUG_IRQ
-# define intdbg lldbg
-# define intvdbg llvdbg
-#else
-# define intdbg(x...)
-# define intvdbg(x...)
-#endif
-
-/****************************************************************************
- * Private Type Declarations
- ****************************************************************************/
-
/****************************************************************************
* Public Data
****************************************************************************/
@@ -147,7 +129,7 @@ void up_ramvec_initialize(void)
src = (const CODE up_vector_t *)getreg32(NVIC_VECTAB);
dest = g_ram_vectors;
- intvdbg("src=%p dest=%p\n", src, dest);
+ irqinfo("src=%p dest=%p\n", src, dest);
for (i = 0; i < ARMV7M_VECTAB_SIZE; i++)
{
@@ -163,7 +145,7 @@ void up_ramvec_initialize(void)
* the table alignment is insufficient.
*/
- intvdbg("NVIC_VECTAB=%08x\n", getreg32(NVIC_VECTAB));
+ irqinfo("NVIC_VECTAB=%08x\n", getreg32(NVIC_VECTAB));
DEBUGASSERT(getreg32(NVIC_VECTAB) == (uint32_t)g_ram_vectors);
}
diff --git a/arch/arm/src/armv7-m/up_releasepending.c b/arch/arm/src/armv7-m/up_releasepending.c
index e9f4cceb33cdf2181f3273caa7bc473d0ea4201d..83be88094e75072d3bc5c8020673c247465829cf 100644
--- a/arch/arm/src/armv7-m/up_releasepending.c
+++ b/arch/arm/src/armv7-m/up_releasepending.c
@@ -66,7 +66,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
- slldbg("From TCB=%p\n", rtcb);
+ sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */
diff --git a/arch/arm/src/armv7-m/up_reprioritizertr.c b/arch/arm/src/armv7-m/up_reprioritizertr.c
index d3415e77414246695490bb00e54bb912dbb6dac7..5e65a3d33837b16d3928614b6fbd726d2009b34d 100644
--- a/arch/arm/src/armv7-m/up_reprioritizertr.c
+++ b/arch/arm/src/armv7-m/up_reprioritizertr.c
@@ -94,7 +94,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
- slldbg("TCB=%p PRI=%d\n", tcb, priority);
+ sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just removed the head
diff --git a/arch/arm/src/armv7-m/up_schedulesigaction.c b/arch/arm/src/armv7-m/up_schedulesigaction.c
index c44298c14ece181a4a7033324d600a2258b752c8..cf70662510c47a0515ee4825353446af5a522c66 100644
--- a/arch/arm/src/armv7-m/up_schedulesigaction.c
+++ b/arch/arm/src/armv7-m/up_schedulesigaction.c
@@ -95,7 +95,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
{
irqstate_t flags;
- sdbg("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+ sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
DEBUGASSERT(tcb != NULL && sigdeliver != NULL);
/* Make sure that interrupts are disabled */
@@ -110,7 +110,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* to the currently executing task.
*/
- sdbg("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
+ sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
if (tcb == this_task())
{
diff --git a/arch/arm/src/armv7-m/up_sigdeliver.c b/arch/arm/src/armv7-m/up_sigdeliver.c
index bfa672aa7acf3d154b2169869a9c9166149ea4bc..6169b512796e839588dfaee8b2dd40c5ff8d6b1c 100644
--- a/arch/arm/src/armv7-m/up_sigdeliver.c
+++ b/arch/arm/src/armv7-m/up_sigdeliver.c
@@ -95,7 +95,7 @@ void up_sigdeliver(void)
board_autoled_on(LED_SIGNAL);
- sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
+ sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
ASSERT(rtcb->xcp.sigdeliver != NULL);
@@ -138,7 +138,7 @@ void up_sigdeliver(void)
* errno that is needed by the user logic (it is probably EINTR).
*/
- sdbg("Resuming\n");
+ sinfo("Resuming\n");
(void)up_irq_save();
rtcb->pterrno = saved_errno;
diff --git a/arch/arm/src/armv7-m/up_svcall.c b/arch/arm/src/armv7-m/up_svcall.c
index 4d28224fd7eba41837ef4b49a91a4381733c4af4..8e78de3a4329cfbb117dab28455b2f94922882ce 100644
--- a/arch/arm/src/armv7-m/up_svcall.c
+++ b/arch/arm/src/armv7-m/up_svcall.c
@@ -56,33 +56,6 @@
#include "exc_return.h"
#include "up_internal.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-/* Configuration ************************************************************/
-
-/* Debug ********************************************************************/
-/* Debug output from this file may interfere with context switching! To get
- * debug output you must enabled the following in your NuttX configuration:
- *
- * - CONFIG_DEBUG and CONFIG_DEBUG_SYSCALL (shows only syscalls)
- * - CONFIG_DEBUG and CONFIG_DEBUG_SVCALL (shows everything)
- */
-
-#if defined(CONFIG_DEBUG_SYSCALL) || defined(CONFIG_DEBUG_SVCALL)
-# define svcdbg(format, ...) lldbg(format, ##__VA_ARGS__)
-#else
-# define svcdbg(x...)
-#endif
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -164,23 +137,23 @@ int up_svcall(int irq, FAR void *context)
* and R1..R7 = variable number of arguments depending on the system call.
*/
-#if defined(CONFIG_DEBUG_SYSCALL) || defined(CONFIG_DEBUG_SVCALL)
+#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# endif
{
- svcdbg("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
- svcdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- svcdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
# ifdef REG_EXC_RETURN
- svcdbg(" PSR: %08x EXC_RETURN: %08x\n",
- regs[REG_XPSR], regs[REG_EXC_RETURN]);
+ svcinfo(" PSR: %08x EXC_RETURN: %08x\n",
+ regs[REG_XPSR], regs[REG_EXC_RETURN]);
# else
- svcdbg(" PSR: %08x\n", regs[REG_XPSR]);
+ svcinfo(" PSR: %08x\n", regs[REG_XPSR]);
# endif
}
#endif
@@ -473,7 +446,7 @@ int up_svcall(int irq, FAR void *context)
regs[REG_R0] -= CONFIG_SYS_RESERVED;
#else
- slldbg("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
+ svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
#endif
}
break;
@@ -481,35 +454,35 @@ int up_svcall(int irq, FAR void *context)
/* Report what happened. That might difficult in the case of a context switch */
-#if defined(CONFIG_DEBUG_SYSCALL) || defined(CONFIG_DEBUG_SVCALL)
+#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# else
if (regs != CURRENT_REGS)
# endif
{
- svcdbg("SVCall Return:\n");
- svcdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
- CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
- CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
- CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
- svcdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
- CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
- CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
- CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
+ svcinfo("SVCall Return:\n");
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
+ CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
+ CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
+ CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
+ CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
+ CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
+ CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
# ifdef REG_EXC_RETURN
- svcdbg(" PSR: %08x EXC_RETURN: %08x\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_EXC_RETURN]);
+ svcinfo(" PSR: %08x EXC_RETURN: %08x\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_EXC_RETURN]);
# else
- svcdbg(" PSR: %08x\n", CURRENT_REGS[REG_XPSR]);
+ svcinfo(" PSR: %08x\n", CURRENT_REGS[REG_XPSR]);
# endif
}
# ifdef CONFIG_DEBUG_SVCALL
else
{
- svcdbg("SVCall Return: %d\n", regs[REG_R0]);
+ svcinfo("SVCall Return: %d\n", regs[REG_R0]);
}
# endif
#endif
diff --git a/arch/arm/src/armv7-r/arm_assert.c b/arch/arm/src/armv7-r/arm_assert.c
index 11dd9fad09be9e339bb896a1767a819ff7e0583a..b841416450be9d4b20e612b6d2fea91c4d305c6a 100644
--- a/arch/arm/src/armv7-r/arm_assert.c
+++ b/arch/arm/src/armv7-r/arm_assert.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_assert.c
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -69,25 +58,13 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* USB trace dumping */
#ifndef CONFIG_USBDEV_TRACE
# undef CONFIG_ARCH_USBDUMP
#endif
-/* The following is just intended to keep some ugliness out of the mainline
- * code. We are going to print the task name if:
- *
- * CONFIG_TASK_NAME_SIZE > 0 && <-- The task has a name
- * (defined(CONFIG_DEBUG) || <-- And the debug is enabled (lldbg used)
- * defined(CONFIG_ARCH_STACKDUMP) <-- Or lowsyslog() is used
- */
-
-#undef CONFIG_PRINT_TASKNAME
-#if CONFIG_TASK_NAME_SIZE > 0 && (defined(CONFIG_DEBUG) || defined(CONFIG_ARCH_STACKDUMP))
-# define CONFIG_PRINT_TASKNAME 1
-#endif
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -121,7 +98,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base)
for (stack = sp & ~0x1f; stack < stack_base; stack += 32)
{
uint32_t *ptr = (uint32_t *)stack;
- lldbg("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
stack, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
@@ -139,12 +116,12 @@ static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg)
{
/* Dump interesting properties of this task */
-#ifdef CONFIG_PRINT_TASKNAME
- lldbg("%s: PID=%d Stack Used=%lu of %lu\n",
+#if CONFIG_TASK_NAME_SIZE > 0
+ _alert("%s: PID=%d Stack Used=%lu of %lu\n",
tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#else
- lldbg("PID: %d Stack Used=%lu of %lu\n",
+ _alert("PID: %d Stack Used=%lu of %lu\n",
tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#endif
@@ -184,12 +161,12 @@ static inline void up_registerdump(void)
for (regs = REG_R0; regs <= REG_R15; regs += 8)
{
uint32_t *ptr = (uint32_t *)&CURRENT_REGS[regs];
- lldbg("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
- lldbg("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]);
+ _alert("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]);
}
}
#else
@@ -209,7 +186,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
/* Let vsyslog do the real work */
va_start(ap, fmt);
- ret = lowvsyslog(LOG_INFO, fmt, ap);
+ ret = vsyslog(LOG_EMERG, fmt, ap);
va_end(ap);
return ret;
}
@@ -253,7 +230,7 @@ static void up_dumpstate(void)
ustacksize = (uint32_t)rtcb->adj_stack_size;
}
- lldbg("Current sp: %08x\n", sp);
+ _alert("Current sp: %08x\n", sp);
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* Get the limits on the interrupt stack memory */
@@ -263,21 +240,21 @@ static void up_dumpstate(void)
/* Show interrupt stack info */
- lldbg("Interrupt stack:\n");
- lldbg(" base: %08x\n", istackbase);
- lldbg(" size: %08x\n", istacksize);
+ _alert("Interrupt stack:\n");
+ _alert(" base: %08x\n", istackbase);
+ _alert(" size: %08x\n", istacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_intstack());
+ _alert(" used: %08x\n", up_check_intstack());
#endif
#endif
/* Show user stack info */
- lldbg("User stack:\n");
- lldbg(" base: %08x\n", ustackbase);
- lldbg(" size: %08x\n", ustacksize);
+ _alert("User stack:\n");
+ _alert(" base: %08x\n", ustackbase);
+ _alert(" size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_tcbstack(rtcb));
+ _alert(" used: %08x\n", up_check_tcbstack(rtcb));
#endif
#ifdef CONFIG_ARCH_KERNEL_STACK
@@ -287,9 +264,9 @@ static void up_dumpstate(void)
{
kstackbase = (uint32_t)rtcb->xcp.kstack + CONFIG_ARCH_KERNEL_STACKSIZE - 4;
- lldbg("Kernel stack:\n");
- lldbg(" base: %08x\n", kstackbase);
- lldbg(" size: %08x\n", CONFIG_ARCH_KERNEL_STACKSIZE);
+ _alert("Kernel stack:\n");
+ _alert(" base: %08x\n", kstackbase);
+ _alert(" size: %08x\n", CONFIG_ARCH_KERNEL_STACKSIZE);
}
#endif
@@ -300,7 +277,7 @@ static void up_dumpstate(void)
{
/* Yes.. dump the interrupt stack */
- lldbg("Interrupt Stack\n", sp);
+ _alert("Interrupt Stack\n", sp);
up_stackdump(sp, istackbase);
/* Extract the user stack pointer which should lie
@@ -308,7 +285,7 @@ static void up_dumpstate(void)
*/
sp = g_intstackbase;
- lldbg("User sp: %08x\n", sp);
+ _alert("User sp: %08x\n", sp);
}
#endif
@@ -318,7 +295,7 @@ static void up_dumpstate(void)
if (sp > ustackbase - ustacksize && sp < ustackbase)
{
- lldbg("User Stack\n", sp);
+ _alert("User Stack\n", sp);
up_stackdump(sp, ustackbase);
}
@@ -329,7 +306,7 @@ static void up_dumpstate(void)
if (sp >= (uint32_t)rtcb->xcp.kstack && sp < kstackbase)
{
- lldbg("Kernel Stack\n", sp);
+ _alert("Kernel Stack\n", sp);
up_stackdump(sp, kstackbase);
}
#endif
@@ -390,16 +367,16 @@ static void _up_assert(int errorcode)
void up_assert(const uint8_t *filename, int lineno)
{
-#ifdef CONFIG_PRINT_TASKNAME
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
struct tcb_s *rtcb = this_task();
#endif
board_autoled_on(LED_ASSERTION);
-#ifdef CONFIG_PRINT_TASKNAME
- lldbg("Assertion failed at file:%s line: %d task: %s\n",
+#if CONFIG_TASK_NAME_SIZE > 0
+ _alert("Assertion failed at file:%s line: %d task: %s\n",
filename, lineno, rtcb->name);
#else
- lldbg("Assertion failed at file:%s line: %d\n",
+ _alert("Assertion failed at file:%s line: %d\n",
filename, lineno);
#endif
up_dumpstate();
diff --git a/arch/arm/src/armv7-r/arm_dataabort.c b/arch/arm/src/armv7-r/arm_dataabort.c
index 789fb0f5adae6e62bc6be4e1b919da3f9b56abcc..52f5d124365dbe84f502b6f133721e76e174faa2 100644
--- a/arch/arm/src/armv7-r/arm_dataabort.c
+++ b/arch/arm/src/armv7-r/arm_dataabort.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_dataabort.c
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
@@ -86,7 +75,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
/* Crash -- possibly showing diagnostic debug information. */
- lldbg("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n",
+ _alert("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n",
regs[REG_PC], dfar, dfsr);
PANIC();
return regs; /* To keep the compiler happy */
diff --git a/arch/arm/src/armv7-r/arm_elf.c b/arch/arm/src/armv7-r/arm_elf.c
index 698ecd0084fc3c80ebf5ab99b927d3a810ee4762..4ab4713b62e1998fe39dd575e0a93f1b5c6dee1e 100644
--- a/arch/arm/src/armv7-r/arm_elf.c
+++ b/arch/arm/src/armv7-r/arm_elf.c
@@ -86,7 +86,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_machine != EM_ARM)
{
- bdbg("Not for ARM: e_machine=%04x\n", ehdr->e_machine);
+ berr("ERROR: Not for ARM: e_machine=%04x\n", ehdr->e_machine);
return -ENOEXEC;
}
@@ -94,7 +94,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_ident[EI_CLASS] != ELFCLASS32)
{
- bdbg("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
+ berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
return -ENOEXEC;
}
@@ -106,7 +106,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB)
#endif
{
- bdbg("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
+ berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
return -ENOEXEC;
}
@@ -114,7 +114,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if ((ehdr->e_entry & 3) != 0)
{
- bdbg("Entry point is not properly aligned: %08x\n", ehdr->e_entry);
+ berr("ERROR: Entry point is not properly aligned: %08x\n", ehdr->e_entry);
return -ENOEXEC;
}
@@ -174,7 +174,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_CALL:
case R_ARM_JUMP24:
{
- bvdbg("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
+ binfo("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@@ -187,8 +187,8 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
offset += sym->st_value - addr;
if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000)
{
- bdbg(" ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
- ELF32_R_TYPE(rel->r_info), offset);
+ berr("ERROR: ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
+ ELF32_R_TYPE(rel->r_info), offset);
return -EINVAL;
}
@@ -203,7 +203,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_ABS32:
case R_ARM_TARGET1: /* New ABI: TARGET1 always treated as ABS32 */
{
- bvdbg("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ binfo("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
*(uint32_t *)addr += sym->st_value;
@@ -212,7 +212,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_V4BX:
{
- bvdbg("Performing V4BX link at addr=%08lx [%08lx]\n",
+ binfo("Performing V4BX link at addr=%08lx [%08lx]\n",
(long)addr, (long)(*(uint32_t *)addr));
/* Preserve only Rm and the condition code */
@@ -227,7 +227,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_PREL31:
{
- bvdbg("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ binfo("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
offset = *(uint32_t *)addr + sym->st_value - addr;
@@ -238,7 +238,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_MOVW_ABS_NC:
case R_ARM_MOVT_ABS:
{
- bvdbg("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ binfo("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@@ -258,7 +258,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
break;
default:
- bdbg("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
+ berr("ERROR: Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
return -EINVAL;
}
@@ -268,6 +268,6 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
int up_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym,
uintptr_t addr)
{
- bdbg("RELA relocation not supported\n");
+ berr("ERROR: RELA relocation not supported\n");
return -ENOSYS;
}
diff --git a/arch/arm/src/armv7-r/arm_l2cc_pl310.c b/arch/arm/src/armv7-r/arm_l2cc_pl310.c
index e019e70e95f2e95d4a1581da09d3f350585c29d1..18c3d224a2c6cbfb6e10d62007f55c42f3c0709f 100644
--- a/arch/arm/src/armv7-r/arm_l2cc_pl310.c
+++ b/arch/arm/src/armv7-r/arm_l2cc_pl310.c
@@ -411,8 +411,8 @@ void up_l2ccinitialize(void)
putreg32(L2CC_CR_L2CEN, L2CC_CR);
}
- lldbg("(%d ways) * (%d bytes/way) = %d bytes\n",
- PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE);
+ sinfo("(%d ways) * (%d bytes/way) = %d bytes\n",
+ PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE);
}
/****************************************************************************
diff --git a/arch/arm/src/armv7-r/arm_prefetchabort.c b/arch/arm/src/armv7-r/arm_prefetchabort.c
index bf16d194676ce28f4402db9c4330a28c73c90c6a..74713f5ad3eae3be527be24885bab7aaea3df460 100644
--- a/arch/arm/src/armv7-r/arm_prefetchabort.c
+++ b/arch/arm/src/armv7-r/arm_prefetchabort.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_prefetchabort.c
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
@@ -82,7 +71,7 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
/* Crash -- possibly showing diagnostic debug information. */
- lldbg("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n",
+ _alert("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n",
regs[REG_PC], ifar, ifsr);
PANIC();
return regs; /* To keep the compiler happy */
diff --git a/arch/arm/src/armv7-r/arm_releasepending.c b/arch/arm/src/armv7-r/arm_releasepending.c
index 89827085907498d7edaab83db8dd1fab47e3c817..a66de941356278880015b60eeeec25132b261cdf 100644
--- a/arch/arm/src/armv7-r/arm_releasepending.c
+++ b/arch/arm/src/armv7-r/arm_releasepending.c
@@ -67,7 +67,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
- slldbg("From TCB=%p\n", rtcb);
+ sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */
diff --git a/arch/arm/src/armv7-r/arm_reprioritizertr.c b/arch/arm/src/armv7-r/arm_reprioritizertr.c
index 4fed13e8f272ca7b43fd90e1e65109e3bc18ae63..db96424eb2f4d6042c672334f327784d4fcecbee 100644
--- a/arch/arm/src/armv7-r/arm_reprioritizertr.c
+++ b/arch/arm/src/armv7-r/arm_reprioritizertr.c
@@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
- slldbg("TCB=%p PRI=%d\n", tcb, priority);
+ sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just
diff --git a/arch/arm/src/armv7-r/arm_schedulesigaction.c b/arch/arm/src/armv7-r/arm_schedulesigaction.c
index 692debff2f0590db39b0d6d12d8c716cdf210c9f..a51d660cb4c686297671874d892868d1d91d266d 100644
--- a/arch/arm/src/armv7-r/arm_schedulesigaction.c
+++ b/arch/arm/src/armv7-r/arm_schedulesigaction.c
@@ -94,7 +94,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
{
irqstate_t flags;
- sdbg("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+ sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
/* Make sure that interrupts are disabled */
@@ -108,7 +108,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* to the currently executing task.
*/
- sdbg("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
+ sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
if (tcb == this_task())
{
diff --git a/arch/arm/src/armv7-r/arm_sigdeliver.c b/arch/arm/src/armv7-r/arm_sigdeliver.c
index f638b35bfd64aec670f86dca54c1a23ebe4ad4c3..280a5ef9c71b0bb360fc444edb21675d85c72eab 100644
--- a/arch/arm/src/armv7-r/arm_sigdeliver.c
+++ b/arch/arm/src/armv7-r/arm_sigdeliver.c
@@ -83,7 +83,7 @@ void up_sigdeliver(void)
board_autoled_on(LED_SIGNAL);
- sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
+ sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
ASSERT(rtcb->xcp.sigdeliver != NULL);
@@ -114,7 +114,7 @@ void up_sigdeliver(void)
* errno that is needed by the user logic (it is probably EINTR).
*/
- sdbg("Resuming\n");
+ sinfo("Resuming\n");
(void)up_irq_save();
rtcb->pterrno = saved_errno;
diff --git a/arch/arm/src/armv7-r/arm_syscall.c b/arch/arm/src/armv7-r/arm_syscall.c
index 3e41a3484344f1dafbbfa8258f892f3986c125b8..49290d5509ef138578d1f52f66b62982f21f17cf 100644
--- a/arch/arm/src/armv7-r/arm_syscall.c
+++ b/arch/arm/src/armv7-r/arm_syscall.c
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -64,18 +53,7 @@
#include "up_internal.h"
/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-/* Debug ********************************************************************/
-
-#if defined(CONFIG_DEBUG_SYSCALL)
-# define svcdbg(format, ...) lldbg(format, ##__VA_ARGS__)
-#else
-# define svcdbg(x...)
-#endif
-
-/****************************************************************************
- * Private Data
+ * Private Functions
****************************************************************************/
/****************************************************************************
@@ -176,16 +154,14 @@ uint32_t *arm_syscall(uint32_t *regs)
* and R1..R7 = variable number of arguments depending on the system call.
*/
-#if defined(CONFIG_DEBUG_SYSCALL)
- svcdbg("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
- svcdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- svcdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
- svcdbg("CPSR: %08x\n", regs[REG_CPSR]);
-#endif
+ svcinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
/* Handle the SVCall according to the command in R0 */
@@ -478,7 +454,7 @@ uint32_t *arm_syscall(uint32_t *regs)
regs[REG_R0] -= CONFIG_SYS_RESERVED;
#else
- svcdbg("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
+ svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
#endif
#ifdef CONFIG_ARCH_KERNEL_STACK
@@ -499,18 +475,16 @@ uint32_t *arm_syscall(uint32_t *regs)
break;
}
-#if defined(CONFIG_DEBUG_SYSCALL)
/* Report what happened */
- svcdbg("SYSCALL Exit: regs: %p\n", regs);
- svcdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- svcdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
- svcdbg("CPSR: %08x\n", regs[REG_CPSR]);
-#endif
+ svcinfo("SYSCALL Exit: regs: %p\n", regs);
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
/* Return the last value of curent_regs. This supports context switches
* on return from the exception. That capability is only used with the
@@ -524,7 +498,7 @@ uint32_t *arm_syscall(uint32_t *regs)
uint32_t *arm_syscall(uint32_t *regs)
{
- lldbg("SYSCALL from 0x%x\n", regs[REG_PC]);
+ _alert("SYSCALL from 0x%x\n", regs[REG_PC]);
CURRENT_REGS = regs;
PANIC();
}
diff --git a/arch/arm/src/armv7-r/arm_undefinedinsn.c b/arch/arm/src/armv7-r/arm_undefinedinsn.c
index b1db4f88686c6f35d98ef625c8e3a50a1b4af2dc..733fb06cb2b4ec245e40aa0fcf3e96ab73a5f5bc 100644
--- a/arch/arm/src/armv7-r/arm_undefinedinsn.c
+++ b/arch/arm/src/armv7-r/arm_undefinedinsn.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_undefinedinsn.c
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -58,18 +47,6 @@
#include "up_internal.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -80,7 +57,7 @@
uint32_t *arm_undefinedinsn(uint32_t *regs)
{
- lldbg("Undefined instruction at 0x%x\n", regs[REG_PC]);
+ _alert("Undefined instruction at 0x%x\n", regs[REG_PC]);
CURRENT_REGS = regs;
PANIC();
return regs; /* To keep the compiler happy */
diff --git a/arch/arm/src/armv7-r/mpu.h b/arch/arm/src/armv7-r/mpu.h
index 67aeb2e94a240db6b6f00282643b4590dca98065..e9e29cf13f853807c66f99c72cd8497a0f8c175b 100644
--- a/arch/arm/src/armv7-r/mpu.h
+++ b/arch/arm/src/armv7-r/mpu.h
@@ -359,12 +359,12 @@ static inline void mpu_set_rgnr(unsigned int rgnr)
static inline void mpu_showtype(void)
{
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_SCHED_INFO
uint32_t regval = mpu_get_mpuir();
- dbg("%s MPU Regions: data=%d instr=%d\n",
- (regval & MPUIR_SEPARATE) != 0 ? "Separate" : "Unified",
- (regval & MPUIR_DREGION_MASK) >> MPUIR_DREGION_SHIFT,
- (regval & MPUIR_IREGION_MASK) >> MPUIR_IREGION_SHIFT);
+ sinfo("%s MPU Regions: data=%d instr=%d\n",
+ (regval & MPUIR_SEPARATE) != 0 ? "Separate" : "Unified",
+ (regval & MPUIR_DREGION_MASK) >> MPUIR_DREGION_SHIFT,
+ (regval & MPUIR_IREGION_MASK) >> MPUIR_IREGION_SHIFT);
#endif
}
diff --git a/arch/arm/src/c5471/c5471_ethernet.c b/arch/arm/src/c5471/c5471_ethernet.c
index 11c157f35f41c7f5d401235a16308c4b3d9d0d7b..b7563aa0545b5909eb66f29080f050120a840245 100644
--- a/arch/arm/src/c5471/c5471_ethernet.c
+++ b/arch/arm/src/c5471/c5471_ethernet.c
@@ -331,9 +331,9 @@ struct c5471_driver_s
uint32_t c_rxdropped; /* Packets dropped because of size */
#endif
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s c_dev; /* Interface understood by uIP */
+ struct net_driver_s c_dev; /* Interface understood by the network */
};
/****************************************************************************
@@ -413,11 +413,11 @@ static void c5471_macassign(struct c5471_driver_s *c5471);
#ifdef CONFIG_C5471_NET_DUMPBUFFER
static inline void c5471_dumpbuffer(const char *msg, const uint8_t *buffer, unsigned int nbytes)
{
- /* CONFIG_DEBUG, CONFIG_DEBUG_VERBOSE, and CONFIG_DEBUG_NET have to be
+ /* CONFIG_DEBUG_FEATURES, CONFIG_DEBUG_INFO, and CONFIG_DEBUG_NET have to be
* defined or the following does nothing.
*/
- nvdbgdumpbuffer(msg, buffer, nbytes);
+ ninfodumpbuffer(msg, buffer, nbytes);
}
#else
# define c5471_dumpbuffer(msg, buffer,nbytes)
@@ -737,22 +737,22 @@ static int c5471_phyinit (void)
phyid = (c5471_mdread(0, MD_PHY_MSB_REG) << 16) | c5471_mdread(0, MD_PHY_LSB_REG);
if (phyid != LU3X31_T64_PHYID)
{
- ndbg("Unrecognized PHY ID: %08x\n", phyid);
+ nerr("ERROR: Unrecognized PHY ID: %08x\n", phyid);
return ERROR;
}
/* Next, Set desired network rate, 10BaseT, 100BaseT, or auto. */
#ifdef CONFIG_C5471_AUTONEGOTIATION
- ndbg("Setting PHY Transceiver for Autonegotiation\n");
+ ninfo("Setting PHY Transceiver for Autonegotiation\n");
c5471_mdwrite(0, MD_PHY_CONTROL_REG, MODE_AUTONEG);
#endif
#ifdef CONFIG_C5471_BASET100
- ndbg("Setting PHY Transceiver for 100BaseT FullDuplex\n");
+ ninfo("Setting PHY Transceiver for 100BaseT FullDuplex\n");
c5471_mdwrite(0, MD_PHY_CONTROL_REG, MODE_100MBIT_FULLDUP);
#endif
#ifdef CONFIG_C5471_BASET10
- ndbg("Setting PHY Transceiver for 10BaseT FullDuplex\n");
+ ninfo("Setting PHY Transceiver for 10BaseT FullDuplex\n");
c5471_mdwrite(0, MD_PHY_CONTROL_REG, MODE_10MBIT_FULLDUP);
#endif
@@ -802,7 +802,7 @@ static inline void c5471_inctxcpu(struct c5471_driver_s *c5471)
c5471->c_txcpudesc += 2*sizeof(uint32_t);
}
- nvdbg("TX CPU desc: %08x\n", c5471->c_txcpudesc);
+ ninfo("TX CPU desc: %08x\n", c5471->c_txcpudesc);
}
/****************************************************************************
@@ -825,7 +825,7 @@ static inline void c5471_incrxcpu(struct c5471_driver_s *c5471)
c5471->c_rxcpudesc += 2*sizeof(uint32_t);
}
- nvdbg("RX CPU desc: %08x\n", c5471->c_rxcpudesc);
+ ninfo("RX CPU desc: %08x\n", c5471->c_rxcpudesc);
}
/****************************************************************************
@@ -861,7 +861,7 @@ static int c5471_transmit(struct c5471_driver_s *c5471)
bfirstframe = true;
c5471->c_lastdescstart = c5471->c_rxcpudesc;
- nvdbg("Packet size: %d RX CPU desc: %08x\n", nbytes, c5471->c_rxcpudesc);
+ ninfo("Packet size: %d RX CPU desc: %08x\n", nbytes, c5471->c_rxcpudesc);
c5471_dumpbuffer("Transmit packet", dev->d_buf, dev->d_len);
while (nbytes)
@@ -918,7 +918,7 @@ static int c5471_transmit(struct c5471_driver_s *c5471)
putreg32(((getreg32(c5471->c_rxcpudesc) & ~EIM_RXDESC_BYTEMASK) | framelen), c5471->c_rxcpudesc);
nbytes -= framelen;
- nvdbg("Wrote framelen: %d nbytes: %d nshorts: %d\n", framelen, nbytes, nshorts);
+ ninfo("Wrote framelen: %d nbytes: %d nshorts: %d\n", framelen, nbytes, nshorts);
if (0 == nbytes)
{
@@ -960,7 +960,7 @@ static int c5471_transmit(struct c5471_driver_s *c5471)
* Function: c5471_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -1092,43 +1092,43 @@ static void c5471_rxstatus(struct c5471_driver_s *c5471)
if ((rxstatus & EIM_TXDESC_RETRYERROR) != 0)
{
c5471->c_rxretries++;
- nvdbg("c_rxretries: %d\n", c5471->c_rxretries);
+ ninfo("c_rxretries: %d\n", c5471->c_rxretries);
}
if ((rxstatus & EIM_TXDESC_HEARTBEAT) != 0)
{
c5471->c_rxheartbeat++;
- nvdbg("c_rxheartbeat: %d\n", c5471->c_rxheartbeat);
+ ninfo("c_rxheartbeat: %d\n", c5471->c_rxheartbeat);
}
if ((rxstatus & EIM_TXDESC_LCOLLISON) != 0)
{
c5471->c_rxlcollision++;
- nvdbg("c_rxlcollision: %d\n", c5471->c_rxlcollision);
+ ninfo("c_rxlcollision: %d\n", c5471->c_rxlcollision);
}
if ((rxstatus & EIM_TXDESC_COLLISION) != 0)
{
c5471->c_rxcollision++;
- nvdbg("c_rxcollision: %d\n", c5471->c_rxcollision);
+ ninfo("c_rxcollision: %d\n", c5471->c_rxcollision);
}
if ((rxstatus & EIM_TXDESC_CRCERROR) != 0)
{
c5471->c_rxcrc++;
- nvdbg("c_rxcrc: %d\n", c5471->c_rxcrc);
+ ninfo("c_rxcrc: %d\n", c5471->c_rxcrc);
}
if ((rxstatus & EIM_TXDESC_UNDERRUN) != 0)
{
c5471->c_rxunderrun++;
- nvdbg("c_rxunderrun: %d\n", c5471->c_rxunderrun);
+ ninfo("c_rxunderrun: %d\n", c5471->c_rxunderrun);
}
if ((rxstatus & EIM_TXDESC_LOC) != 0)
{
c5471->c_rxloc++;
- nvdbg("c_rxloc: %d\n", c5471->c_rxloc);
+ ninfo("c_rxloc: %d\n", c5471->c_rxloc);
}
}
}
@@ -1162,11 +1162,11 @@ static void c5471_receive(struct c5471_driver_s *c5471)
int j = 0;
/* Walk the newly received packet contained within the EIM and transfer
- * its contents to the uIP buffer. This frees up the memory contained within
+ * its contents to the network buffer. This frees up the memory contained within
* the EIM for additional packets that might be received later from the network.
*/
- nvdbg("Reading TX CPU desc: %08x\n", c5471->c_txcpudesc);
+ ninfo("Reading TX CPU desc: %08x\n", c5471->c_txcpudesc);
while (bmore)
{
/* Words #0 and #1 of descriptor */
@@ -1185,7 +1185,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
framelen = (getreg32(c5471->c_txcpudesc) & EIM_TXDESC_BYTEMASK);
packetlen += framelen;
- /* Check if the received packet will fit within the uIP packet buffer */
+ /* Check if the received packet will fit within the network packet buffer */
if (packetlen < (CONFIG_NET_ETH_MTU + 4))
{
@@ -1196,7 +1196,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
/* Divide by 2 with round up to get the number of 16-bit words. */
nshorts = (framelen + 1) >> 1;
- nvdbg("Reading framelen: %d packetlen: %d nshorts: %d packetmen: %p\n",
+ ninfo("Reading framelen: %d packetlen: %d nshorts: %d packetmen: %p\n",
framelen, packetlen, nshorts, packetmem);
for (i = 0 ; i < nshorts; i++, j++)
@@ -1210,7 +1210,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
}
else
{
- nvdbg("Discarding framelen: %d packetlen\n", framelen, packetlen);
+ ninfo("Discarding framelen: %d packetlen\n", framelen, packetlen);
}
if (getreg32(c5471->c_txcpudesc) & EIM_TXDESC_LIF)
@@ -1234,7 +1234,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
c5471_inctxcpu(c5471);
}
- /* Adjust the packet length to remove the CRC bytes that uIP doesn't care about. */
+ /* Adjust the packet length to remove the CRC bytes that the network doesn't care about. */
packetlen -= 4;
@@ -1244,8 +1244,8 @@ static void c5471_receive(struct c5471_driver_s *c5471)
c5471->c_rxpackets++;
#endif
- /* If we successfully transferred the data into the uIP buffer, then pass it on
- * to uIP for processing.
+ /* If we successfully transferred the data into the network buffer, then pass it on
+ * to the network for processing.
*/
if (packetlen > 0 && packetlen < CONFIG_NET_ETH_MTU)
@@ -1253,7 +1253,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
/* Set amount of data in c5471->c_dev.d_len. */
dev->d_len = packetlen;
- nvdbg("Received packet, packetlen: %d type: %02x\n", packetlen, ntohs(BUF->type));
+ ninfo("Received packet, packetlen: %d type: %02x\n", packetlen, ntohs(BUF->type));
c5471_dumpbuffer("Received packet", dev->d_buf, dev->d_len);
#ifdef CONFIG_NET_PKT
@@ -1267,7 +1267,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
- nllvdbg("IPv4 frame\n");
+ ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@@ -1310,7 +1310,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
- nllvdbg("Iv6 frame\n");
+ ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@@ -1371,7 +1371,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
{
/* Increment the count of dropped packets */
- ndbg("Too big! packetlen: %d\n", packetlen);
+ nwarn("WARNING: Too big! packetlen: %d\n", packetlen);
c5471->c_rxdropped++;
}
#endif
@@ -1432,43 +1432,43 @@ static void c5471_txstatus(struct c5471_driver_s *c5471)
if ((txstatus & EIM_RXDESC_MISS) != 0)
{
c5471->c_txmiss++;
- nvdbg("c_txmiss: %d\n", c5471->c_txmiss);
+ ninfo("c_txmiss: %d\n", c5471->c_txmiss);
}
if ((txstatus & EIM_RXDESC_VLAN) != 0)
{
c5471->c_txvlan++;
- nvdbg("c_txvlan: %d\n", c5471->c_txvlan);
+ ninfo("c_txvlan: %d\n", c5471->c_txvlan);
}
if ((txstatus & EIM_RXDESC_LFRAME) != 0)
{
c5471->c_txlframe++;
- nvdbg("c_txlframe: %d\n", c5471->c_txlframe);
+ ninfo("c_txlframe: %d\n", c5471->c_txlframe);
}
if ((txstatus & EIM_RXDESC_SFRAME) != 0)
{
c5471->c_txsframe++;
- nvdbg("c_txsframe: %d\n", c5471->c_txsframe);
+ ninfo("c_txsframe: %d\n", c5471->c_txsframe);
}
if ((txstatus & EIM_RXDESC_CRCERROR) != 0)
{
c5471->c_txcrc++;
- nvdbg("c_txcrc: %d\n", c5471->c_txcrc);
+ ninfo("c_txcrc: %d\n", c5471->c_txcrc);
}
if ((txstatus & EIM_RXDESC_OVERRUN) != 0)
{
c5471->c_txoverrun++;
- nvdbg("c_txoverrun: %d\n", c5471->c_txoverrun);
+ ninfo("c_txoverrun: %d\n", c5471->c_txoverrun);
}
if ((txstatus & EIM_RXDESC_OVERRUN) != 0)
{
c5471->c_txalign++;
- nvdbg("c_txalign: %d\n", c5471->c_txalign);
+ ninfo("c_txalign: %d\n", c5471->c_txalign);
}
}
}
@@ -1496,7 +1496,7 @@ static void c5471_txdone(struct c5471_driver_s *c5471)
wd_cancel(c5471->c_txtimeout);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&c5471->c_dev, c5471_txpoll);
}
@@ -1607,7 +1607,7 @@ static void c5471_txtimeout(int argc, uint32_t arg, ...)
#ifdef CONFIG_C5471_NET_STATS
c5471->c_txtimeouts++;
- nvdbg("c_txtimeouts: %d\n", c5471->c_txtimeouts);
+ ninfo("c_txtimeouts: %d\n", c5471->c_txtimeouts);
#endif
/* Then try to restart the hardware */
@@ -1615,7 +1615,7 @@ static void c5471_txtimeout(int argc, uint32_t arg, ...)
c5471_ifdown(&c5471->c_dev);
c5471_ifup(&c5471->c_dev);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&c5471->c_dev, c5471_txpoll);
}
@@ -1647,7 +1647,7 @@ static void c5471_polltimer(int argc, uint32_t arg, ...)
if ((EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) == 0)
{
- /* If so, update TCP timing states and poll uIP for new XMIT data */
+ /* If so, update TCP timing states and poll the network for new XMIT data */
(void)devif_timer(&c5471->c_dev, c5471_txpoll);
}
@@ -1680,9 +1680,9 @@ static int c5471_ifup(struct net_driver_s *dev)
struct c5471_driver_s *c5471 = (struct c5471_driver_s *)dev->d_private;
volatile uint32_t clearbits;
- ndbg("Bringing up: %d.%d.%d.%d\n",
- dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
- (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+ ninfo("Bringing up: %d.%d.%d.%d\n",
+ dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+ (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
/* Initilize Ethernet interface */
@@ -1742,7 +1742,7 @@ static int c5471_ifdown(struct net_driver_s *dev)
struct c5471_driver_s *c5471 = (struct c5471_driver_s *)dev->d_private;
irqstate_t flags;
- ndbg("Stopping\n");
+ ninfo("Stopping\n");
/* Disable the Ethernet interrupt */
@@ -1798,7 +1798,7 @@ static int c5471_txavail(struct net_driver_s *dev)
struct c5471_driver_s *c5471 = (struct c5471_driver_s *)dev->d_private;
irqstate_t flags;
- ndbg("Polling\n");
+ ninfo("Polling\n");
flags = enter_critical_section();
/* Ignore the notification if the interface is not yet up */
@@ -1811,7 +1811,7 @@ static int c5471_txavail(struct net_driver_s *dev)
if ((EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) == 0)
{
- /* If so, then poll uIP for new XMIT data */
+ /* If so, then poll the network for new XMIT data */
(void)devif_poll(&c5471->c_dev, c5471_txpoll);
}
@@ -1951,7 +1951,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471)
/* TX ENET 0 */
- ndbg("TX ENET0 desc: %08x pbuf: %08x\n", desc, pbuf);
+ ninfo("TX ENET0 desc: %08x pbuf: %08x\n", desc, pbuf);
putreg32((desc & 0x0000ffff), ENET0_TDBA); /* 16-bit offset address */
for (i = NUM_DESC_TX-1; i >= 0; i--)
{
@@ -1978,7 +1978,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471)
/* RX ENET 0 */
- ndbg("RX ENET0 desc: %08x pbuf: %08x\n", desc, pbuf);
+ ninfo("RX ENET0 desc: %08x pbuf: %08x\n", desc, pbuf);
putreg32((desc & 0x0000ffff), ENET0_RDBA); /* 16-bit offset address */
for (i = NUM_DESC_RX-1; i >= 0; i--)
{
@@ -2005,7 +2005,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471)
/* TX CPU */
- ndbg("TX CPU desc: %08x pbuf: %08x\n", desc, pbuf);
+ ninfo("TX CPU desc: %08x pbuf: %08x\n", desc, pbuf);
c5471->c_txcpudesc = desc;
putreg32((desc & 0x0000ffff), EIM_CPU_TXBA); /* 16-bit offset address */
for (i = NUM_DESC_TX-1; i >= 0; i--)
@@ -2035,7 +2035,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471)
/* RX CPU */
- ndbg("RX CPU desc: %08x pbuf: %08x\n", desc, pbuf);
+ ninfo("RX CPU desc: %08x pbuf: %08x\n", desc, pbuf);
c5471->c_rxcpudesc = desc;
putreg32((desc & 0x0000ffff), EIM_CPU_RXBA); /* 16-bit offset address */
for (i = NUM_DESC_RX-1; i >= 0; i--)
@@ -2063,7 +2063,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471)
pbuf += sizeof(uint32_t); /* Ether Module's "Buffer Usage Word" */
}
- ndbg("END desc: %08x pbuf: %08x\n", desc, pbuf);
+ ninfo("END desc: %08x pbuf: %08x\n", desc, pbuf);
/* Save the descriptor packet size */
@@ -2150,13 +2150,13 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471)
static void c5471_reset(struct c5471_driver_s *c5471)
{
#if defined(CONFIG_C5471_PHY_LU3X31T_T64)
- ndbg("EIM reset\n");
+ ninfo("EIM reset\n");
c5471_eimreset(c5471);
#endif
- ndbg("PHY init\n");
+ ninfo("PHY init\n");
c5471_phyinit();
- ndbg("EIM config\n");
+ ninfo("EIM config\n");
c5471_eimconfig(c5471);
}
@@ -2178,7 +2178,7 @@ static void c5471_macassign(struct c5471_driver_s *c5471)
uint8_t *mptr = dev->d_mac.ether_addr_octet;
register uint32_t tmp;
- ndbg("MAC: %0x:%0x:%0x:%0x:%0x:%0x\n",
+ ninfo("MAC: %0x:%0x:%0x:%0x:%0x:%0x\n",
mptr[0], mptr[1], mptr[2], mptr[3], mptr[4], mptr[5]);
/* Set CPU port MAC address. S/W will only see incoming packets that match
@@ -2241,7 +2241,7 @@ void up_netinitialize(void)
{
/* We could not attach the ISR to the ISR */
- nlldbg("irq_attach() failed\n");
+ nerr("ERROR: irq_attach() failed\n");
return;
}
diff --git a/arch/arm/src/c5471/c5471_watchdog.c b/arch/arm/src/c5471/c5471_watchdog.c
index 2143246d6e7597754d6716eb259808b946a17af4..d1381f45d46d217e635fe48cfc751bf6a1c2fc65 100644
--- a/arch/arm/src/c5471/c5471_watchdog.c
+++ b/arch/arm/src/c5471/c5471_watchdog.c
@@ -155,7 +155,7 @@ static inline unsigned int wdt_prescaletoptv(unsigned int prescale)
}
}
- dbg("prescale=%d -> ptv=%d\n", prescale, ptv);
+ wdinfo("prescale=%d -> ptv=%d\n", prescale, ptv);
return ptv;
}
@@ -173,7 +173,7 @@ static int wdt_setusec(uint32_t usec)
uint32_t divisor = 1;
uint32_t mode;
- dbg("usec=%d\n", usec);
+ wdinfo("usec=%d\n", usec);
/* Calculate a value of prescaler and divisor that will be able
* to count to the usec. It may not be exact or the best
@@ -186,7 +186,7 @@ static int wdt_setusec(uint32_t usec)
do
{
divisor = (CLOCK_MHZx2 * usec) / (prescaler * 2);
- dbg("divisor=0x%x prescaler=0x%x\n", divisor, prescaler);
+ wdinfo("divisor=0x%x prescaler=0x%x\n", divisor, prescaler);
if (divisor >= 0x10000)
{
@@ -194,7 +194,7 @@ static int wdt_setusec(uint32_t usec)
{
/* This is the max possible ~2.5 seconds. */
- dbg("prescaler=0x%x too big!\n", prescaler);
+ wderr("ERROR: prescaler=0x%x too big!\n", prescaler);
return ERROR;
}
@@ -207,19 +207,19 @@ static int wdt_setusec(uint32_t usec)
}
while (divisor >= 0x10000);
- dbg("prescaler=0x%x divisor=0x%x\n", prescaler, divisor);
+ wdinfo("prescaler=0x%x divisor=0x%x\n", prescaler, divisor);
mode = wdt_prescaletoptv(prescaler);
mode &= ~C5471_TIMER_AUTORELOAD; /* One shot mode. */
mode |= divisor << 5;
- dbg("mode=0x%x\n", mode);
+ wdinfo("mode=0x%x\n", mode);
c5471_wdt_cntl = mode;
/* Now start the watchdog */
c5471_wdt_cntl |= C5471_TIMER_STARTBIT;
- dbg("cntl_timer=0x%x\n", c5471_wdt_cntl);
+ wdinfo("cntl_timer=0x%x\n", c5471_wdt_cntl);
return 0;
}
@@ -234,17 +234,17 @@ static int wdt_setusec(uint32_t usec)
static int wdt_interrupt(int irq, void *context)
{
- dbg("expired\n");
+ wdinfo("expired\n");
#if defined(CONFIG_SOFTWARE_REBOOT)
# if defined(CONFIG_SOFTWARE_TEST)
- dbg(" Test only\n");
+ wdinfo(" Test only\n");
# else
- dbg(" Re-booting\n");
+ wdinfo(" Re-booting\n");
# warning "Add logic to reset CPU here"
# endif
#else
- dbg(" No reboot\n");
+ wdinfo(" No reboot\n");
#endif
return OK;
}
@@ -259,7 +259,7 @@ static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen)
* not work if the user provides a buffer smaller than 18 bytes.
*/
- dbg("buflen=%d\n", buflen);
+ wdinfo("buflen=%d\n", buflen);
if (buflen >= 18)
{
sprintf(buffer, "%08x %08x\n", c5471_wdt_cntl, c5471_wdt_count);
@@ -274,7 +274,7 @@ static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen)
static ssize_t wdt_write(struct file *filep, const char *buffer, size_t buflen)
{
- dbg("buflen=%d\n", buflen);
+ wdinfo("buflen=%d\n", buflen);
if (buflen)
{
/* Reset the timer to the maximum delay */
@@ -292,7 +292,7 @@ static ssize_t wdt_write(struct file *filep, const char *buffer, size_t buflen)
static int wdt_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
{
- dbg("ioctl Call: cmd=0x%x arg=0x%x", cmd, arg);
+ wdinfo("ioctl Call: cmd=0x%x arg=0x%x", cmd, arg);
/* Process the IOCTL command (see arch/watchdog.h) */
@@ -315,8 +315,6 @@ static int wdt_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
static int wdt_open(struct file *filep)
{
- dbg("");
-
if (g_wdtopen)
{
return -EBUSY;
@@ -339,11 +337,8 @@ static int wdt_open(struct file *filep)
static int wdt_close(struct file *filep)
{
- dbg("");
-
/* The task controlling the watchdog has terminated. Take the timer
- * the
- * watchdog in interrupt mode -- we are going to reset unless the
+ * the watchdog in interrupt mode -- we are going to reset unless the
* reopened again soon.
*/
@@ -367,7 +362,7 @@ int up_wdtinit(void)
{
int ret;
- dbg("C547x Watchdog Driver\n");
+ wdinfo("C547x Watchdog Driver\n");
/* Register as /dev/wdt */
@@ -379,7 +374,7 @@ int up_wdtinit(void)
/* Register for an interrupt level callback through wdt_interrupt */
- dbg("Attach to IRQ=%d\n", C5471_IRQ_WATCHDOG);
+ wdinfo("Attach to IRQ=%d\n", C5471_IRQ_WATCHDOG);
/* Make sure that the timer is stopped */
diff --git a/arch/arm/src/calypso/calypso_spi.c b/arch/arm/src/calypso/calypso_spi.c
index e3b063a559d671f504750e3bf711c16c479be0ec..36727927c43680dfb23f20f173a80efeb0b14822 100644
--- a/arch/arm/src/calypso/calypso_spi.c
+++ b/arch/arm/src/calypso/calypso_spi.c
@@ -216,8 +216,8 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din)
tmp <<= (32-bitlen); /* align to MSB */
}
- dbg("spi_xfer(dev_idx=%u, bitlen=%u, data_out=0x%08x): ",
- dev_idx, bitlen, tmp);
+ spiinfo("spi_xfer(dev_idx=%u, bitlen=%u, data_out=0x%08x): ",
+ dev_idx, bitlen, tmp);
/* fill transmit registers */
@@ -236,14 +236,14 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din)
}
putreg16(reg_ctrl, SPI_REG(REG_CTRL));
- dbg("reg_ctrl=0x%04x ", reg_ctrl);
+ spiinfo("reg_ctrl=0x%04x ", reg_ctrl);
/* wait until the transfer is complete */
while (1)
{
reg_status = getreg16(SPI_REG(REG_STATUS));
- dbg("status=0x%04x ", reg_status);
+ spiinfo("status=0x%04x ", reg_status);
if (din && (reg_status & SPI_STATUS_RE))
{
break;
@@ -262,7 +262,7 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din)
{
tmp = getreg16(SPI_REG(REG_RX_MSB)) << 16;
tmp |= getreg16(SPI_REG(REG_RX_LSB));
- dbg("data_in=0x%08x ", tmp);
+ spiinfo("data_in=0x%08x ", tmp);
if (bitlen <= 8)
{
@@ -278,7 +278,7 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din)
}
}
- dbg("\n");
+ spiinfo("\n");
return 0;
}
diff --git a/arch/arm/src/calypso/calypso_uwire.c b/arch/arm/src/calypso/calypso_uwire.c
index d837a7abdc249ac67c300fcfe566aa575c28f6ac..fe2c33b7cc152392786c3e19cd7890b0c42b8c9f 100644
--- a/arch/arm/src/calypso/calypso_uwire.c
+++ b/arch/arm/src/calypso/calypso_uwire.c
@@ -112,7 +112,7 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
/* FIXME uwire_init always selects CS0 for now */
- dbg("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen);
+ _info("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen);
/* select the chip */
@@ -128,7 +128,7 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
tmp <<= 16 - bitlen; /* align to MSB */
putreg16(tmp, UWIRE_REG(REG_DATA));
- dbg(", data_out=0x%04hx", tmp);
+ _info(", data_out=0x%04hx", tmp);
}
tmp = (dout ? UWIRE_CSR_BITS_WR(bitlen) : 0) |
@@ -142,7 +142,7 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
_uwire_wait(UWIRE_CSR_RDRB, UWIRE_CSR_RDRB);
tmp = getreg16(UWIRE_REG(REG_DATA));
- dbg(", data_in=0x%08x", tmp);
+ _info(", data_in=0x%08x", tmp);
if (bitlen <= 8)
*(uint8_t *)din = tmp & 0xff;
@@ -155,7 +155,7 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
putreg16(UWIRE_CSR_IDX(0) | 0, UWIRE_REG(REG_CSR));
_uwire_wait(UWIRE_CSR_CSRB, 0);
- dbg(")\n");
+ _info(")\n");
return 0;
}
diff --git a/arch/arm/src/common/up_createstack.c b/arch/arm/src/common/up_createstack.c
index c3aa9d7adb917d16f1e2c8c2c2e64402bbd8a26d..70d83a83a58ac63a42569869836ba0f42f3f07f3 100644
--- a/arch/arm/src/common/up_createstack.c
+++ b/arch/arm/src/common/up_createstack.c
@@ -205,12 +205,12 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
}
#endif /* CONFIG_TLS */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
/* Was the allocation successful? */
if (!tcb->stack_alloc_ptr)
{
- sdbg("ERROR: Failed to allocate stack, size %d\n", stack_size);
+ serr("ERROR: Failed to allocate stack, size %d\n", stack_size);
}
#endif
}
diff --git a/arch/arm/src/common/up_exit.c b/arch/arm/src/common/up_exit.c
index 57137a60def127946b8ed5079c442e2433bd85d6..4d16f2a8a55c2c0fe8ebf12b55c6fe61118f316c 100644
--- a/arch/arm/src/common/up_exit.c
+++ b/arch/arm/src/common/up_exit.c
@@ -52,6 +52,14 @@
#include "group/group.h"
#include "up_internal.h"
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef CONFIG_DEBUG_SCHED_INFO
+# undef CONFIG_DUMP_ON_EXIT
+#endif
+
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -66,7 +74,7 @@
*
****************************************************************************/
-#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_DUMP_ON_EXIT
static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
{
#if CONFIG_NFILE_DESCRIPTORS > 0
@@ -77,8 +85,8 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
int i;
#endif
- sdbg(" TCB=%p name=%s pid=%d\n", tcb, tcb->argv[0], tcb->pid);
- sdbg(" priority=%d state=%d\n", tcb->sched_priority, tcb->task_state);
+ sinfo(" TCB=%p name=%s pid=%d\n", tcb, tcb->argv[0], tcb->pid);
+ sinfo(" priority=%d state=%d\n", tcb->sched_priority, tcb->task_state);
#if CONFIG_NFILE_DESCRIPTORS > 0
filelist = tcb->group->tg_filelist;
@@ -87,8 +95,8 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
struct inode *inode = filelist->fl_files[i].f_inode;
if (inode)
{
- sdbg(" fd=%d refcount=%d\n",
- i, inode->i_crefs);
+ sinfo(" fd=%d refcount=%d\n",
+ i, inode->i_crefssinfo);
}
}
#endif
@@ -101,11 +109,11 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
if (filep->fs_fd >= 0)
{
#if CONFIG_STDIO_BUFFER_SIZE > 0
- sdbg(" fd=%d nbytes=%d\n",
- filep->fs_fd,
- filep->fs_bufpos - filep->fs_bufstart);
+ sinfo(" fd=%d nbytes=%d\n",
+ filep->fs_fd,
+ filep->fs_bufpos - filep->fs_bufstart);
#else
- sdbg(" fd=%d\n", filep->fs_fd);
+ sinfo(" fd=%d\n", filep->fs_fd);
#endif
}
}
@@ -138,10 +146,10 @@ void _exit(int status)
(void)up_irq_save();
- slldbg("TCB=%p exiting\n", this_task());
+ sinfo("TCB=%p exiting\n", this_task());
-#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG)
- slldbg("Other tasks:\n");
+#ifdef CONFIG_DUMP_ON_EXIT
+ sinfo("Other tasks:\n");
sched_foreach(_up_dumponexit, NULL);
#endif
diff --git a/arch/arm/src/common/up_initialize.c b/arch/arm/src/common/up_initialize.c
index 511138e4f51640de6328d0d1019d6241ca2c2898..6b5117adf1bdd83745c35827a377856d400288cd 100644
--- a/arch/arm/src/common/up_initialize.c
+++ b/arch/arm/src/common/up_initialize.c
@@ -49,7 +49,7 @@
#include
#include
#include
-#include
+#include
#include
#include
@@ -72,18 +72,18 @@
*
****************************************************************************/
-#if defined(CONFIG_ARCH_CALIBRATION) && defined(CONFIG_DEBUG)
+#if defined(CONFIG_ARCH_CALIBRATION) && defined(CONFIG_DEBUG_FEATURES)
static void up_calibratedelay(void)
{
int i;
- lldbg("Beginning 100s delay\n");
+ _warn("Beginning 100s delay\n");
for (i = 0; i < 100; i++)
{
up_mdelay(1000);
}
- lldbg("End 100s delay\n");
+ _warn("End 100s delay\n");
}
#else
# define up_calibratedelay()
@@ -222,7 +222,7 @@ void up_initialize(void)
#if defined(CONFIG_DEV_LOWCONSOLE)
lowconsole_init();
-#elif defined(CONFIG_SYSLOG_CONSOLE)
+#elif defined(CONFIG_CONSOLE_SYSLOG)
syslog_console_init();
#elif defined(CONFIG_RAMLOG_CONSOLE)
ramlog_consoleinit();
@@ -246,14 +246,12 @@ void up_initialize(void)
up_rnginitialize();
#endif
- /* Initialize the system logging device */
+ /* Early initialization of the system logging device. Some SYSLOG channel
+ * can be initialized early in the initialization sequence because they
+ * depend on only minimal OS initialization.
+ */
-#ifdef CONFIG_SYSLOG_CHAR
- syslog_initialize();
-#endif
-#ifdef CONFIG_RAMLOG_SYSLOG
- ramlog_sysloginit();
-#endif
+ syslog_initialize(SYSLOG_INIT_EARLY);
#ifndef CONFIG_NETDEV_LATEINIT
/* Initialize the network */
diff --git a/arch/arm/src/common/up_internal.h b/arch/arm/src/common/up_internal.h
index 8dccf8a1ef073639233fe062dd9d35990332f3d9..feec433355893d006eeb7494a730fa865f06f03d 100644
--- a/arch/arm/src/common/up_internal.h
+++ b/arch/arm/src/common/up_internal.h
@@ -63,6 +63,10 @@
#undef CONFIG_SUPPRESS_UART_CONFIG /* DEFINED: Do not reconfig UART */
#undef CONFIG_DUMP_ON_EXIT /* DEFINED: Dump task state on exit */
+#ifndef CONFIG_DEBUG_SCHED_INFO
+# undef CONFIG_DUMP_ON_EXIT /* Needs CONFIG_DEBUG_SCHED_INFO */
+#endif
+
/* Determine which (if any) console driver to use. If a console is enabled
* and no other console device is specified, then a serial console is
* assumed.
@@ -97,13 +101,6 @@
# define USE_SERIALDRIVER 1
#endif
-/* Determine which device to use as the system logging device */
-
-#ifndef CONFIG_SYSLOG
-# undef CONFIG_SYSLOG_CHAR
-# undef CONFIG_RAMLOG_SYSLOG
-#endif
-
/* Check if an interrupt stack size is configured */
#ifndef CONFIG_ARCH_INTERRUPTSTACK
diff --git a/arch/arm/src/common/up_vfork.c b/arch/arm/src/common/up_vfork.c
index b902ccba7b9f93dcbd8e6f22181f472bd97a5f26..e655ab15b43c1648777e5f454ddcf04faec162f5 100644
--- a/arch/arm/src/common/up_vfork.c
+++ b/arch/arm/src/common/up_vfork.c
@@ -130,12 +130,12 @@ pid_t up_vfork(const struct vfork_s *context)
uint32_t stackutil;
int ret;
- svdbg("vfork context [%p]:\n", context);
- svdbg(" r4:%08x r5:%08x r6:%08x r7:%08x\n",
+ sinfo("vfork context [%p]:\n", context);
+ sinfo(" r4:%08x r5:%08x r6:%08x r7:%08x\n",
context->r4, context->r5, context->r6, context->r7);
- svdbg(" r8:%08x r9:%08x r10:%08x\n",
+ sinfo(" r8:%08x r9:%08x r10:%08x\n",
context->r8, context->r9, context->r10);
- svdbg(" fp:%08x sp:%08x lr:%08x\n",
+ sinfo(" fp:%08x sp:%08x lr:%08x\n",
context->fp, context->sp, context->lr);
/* Allocate and initialize a TCB for the child task. */
@@ -143,11 +143,11 @@ pid_t up_vfork(const struct vfork_s *context)
child = task_vforksetup((start_t)(context->lr & ~1));
if (!child)
{
- sdbg("ERROR: task_vforksetup failed\n");
+ serr("ERROR: task_vforksetup failed\n");
return (pid_t)ERROR;
}
- svdbg("TCBs: Parent=%p Child=%p\n", parent, child);
+ sinfo("TCBs: Parent=%p Child=%p\n", parent, child);
/* Get the size of the parent task's stack. Due to alignment operations,
* the adjusted stack size may be smaller than the stack size originally
@@ -162,7 +162,7 @@ pid_t up_vfork(const struct vfork_s *context)
parent->flags & TCB_FLAG_TTYPE_MASK);
if (ret != OK)
{
- sdbg("ERROR: up_create_stack failed: %d\n", ret);
+ serr("ERROR: up_create_stack failed: %d\n", ret);
task_vforkabort(child, -ret);
return (pid_t)ERROR;
}
@@ -176,7 +176,7 @@ pid_t up_vfork(const struct vfork_s *context)
DEBUGASSERT((uint32_t)parent->adj_stack_ptr > context->sp);
stackutil = (uint32_t)parent->adj_stack_ptr - context->sp;
- svdbg("Parent: stacksize:%d stackutil:%d\n", stacksize, stackutil);
+ sinfo("Parent: stacksize:%d stackutil:%d\n", stacksize, stackutil);
/* Make some feeble effort to preserve the stack contents. This is
* feeble because the stack surely contains invalid pointers and other
@@ -201,9 +201,9 @@ pid_t up_vfork(const struct vfork_s *context)
newfp = context->fp;
}
- svdbg("Parent: stack base:%08x SP:%08x FP:%08x\n",
+ sinfo("Parent: stack base:%08x SP:%08x FP:%08x\n",
parent->adj_stack_ptr, context->sp, context->fp);
- svdbg("Child: stack base:%08x SP:%08x FP:%08x\n",
+ sinfo("Child: stack base:%08x SP:%08x FP:%08x\n",
child->cmn.adj_stack_ptr, newsp, newfp);
/* Update the stack pointer, frame pointer, and volatile registers. When
diff --git a/arch/arm/src/dm320/dm320_decodeirq.c b/arch/arm/src/dm320/dm320_decodeirq.c
index 5d36a6bdc65685f41bc4bdb50e6710b3d82b6071..5d7e709588192ac5e9ad2f0dd0b3aa61e2cbf64e 100644
--- a/arch/arm/src/dm320/dm320_decodeirq.c
+++ b/arch/arm/src/dm320/dm320_decodeirq.c
@@ -51,22 +51,6 @@
#include "group/group.h"
-/********************************************************************************
- * Pre-processor Definitions
- ********************************************************************************/
-
-/********************************************************************************
- * Public Data
- ********************************************************************************/
-
-/********************************************************************************
- * Private Data
- ********************************************************************************/
-
-/********************************************************************************
- * Private Functions
- ********************************************************************************/
-
/********************************************************************************
* Public Functions
********************************************************************************/
@@ -74,8 +58,8 @@
void up_decodeirq(uint32_t *regs)
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
- lowsyslog(LOG_ERR, "Unexpected IRQ\n");
CURRENT_REGS = regs;
+ err("ERROR: Unexpected IRQ\n");
PANIC();
#else
/* Decode the interrupt. First, fetch the interrupt id register. */
diff --git a/arch/arm/src/dm320/dm320_framebuffer.c b/arch/arm/src/dm320/dm320_framebuffer.c
index 8fd4ec44634f3890f2a9c883ed49a99fa9d48738..dcedcb62e5d277cd46d2280e1055017ef09db437 100644
--- a/arch/arm/src/dm320/dm320_framebuffer.c
+++ b/arch/arm/src/dm320/dm320_framebuffer.c
@@ -768,15 +768,15 @@ static void dm320_disable(void)
{
/* Disable all planes */
- gvdbg("Inactivate OSD:\n");
+ ginfo("Inactivate OSD:\n");
putreg16(0, DM320_OSD_OSDWIN0MD); /* Win0 mode = 0 (1:active) */
putreg16(0, DM320_OSD_OSDWIN1MD); /* Win1 mode = 0 (1:active) */
putreg16(0, DM320_OSD_RECTCUR); /* Rectangular cursor mode = 0 (1:active) */
- gvdbg("DM320_OSD_OSDWIN0MD: %04x\n", getreg16(DM320_OSD_OSDWIN0MD));
- gvdbg("DM320_OSD_OSDWIN1MD: %04x\n", getreg16(DM320_OSD_OSDWIN1MD));
- gvdbg("DM320_OSD_RECTCUR: %04x\n", getreg16(DM320_OSD_RECTCUR));
+ ginfo("DM320_OSD_OSDWIN0MD: %04x\n", getreg16(DM320_OSD_OSDWIN0MD));
+ ginfo("DM320_OSD_OSDWIN1MD: %04x\n", getreg16(DM320_OSD_OSDWIN1MD));
+ ginfo("DM320_OSD_RECTCUR: %04x\n", getreg16(DM320_OSD_RECTCUR));
}
/****************************************************************************
@@ -791,17 +791,17 @@ static void dm320_hwinitialize(void)
/* Initialize the main video to correct the origin */
- gvdbg("Setup main video origin:\n");
+ ginfo("Setup main video origin:\n");
putreg16(CONFIG_DM320_BASEX, DM320_OSD_BASEPX);
putreg16(CONFIG_DM320_BASEY, DM320_OSD_BASEPY);
- gvdbg("DM320_OSD_BASEPX: %04x\n", getreg16(DM320_OSD_BASEPX));
- gvdbg("DM320_OSD_BASEPY: %04x\n", getreg16(DM320_OSD_BASEPY));
+ ginfo("DM320_OSD_BASEPX: %04x\n", getreg16(DM320_OSD_BASEPX));
+ ginfo("DM320_OSD_BASEPY: %04x\n", getreg16(DM320_OSD_BASEPY));
/* Set up the frame buffer address registers */
- gvdbg("Setup framebuffer addresses:\n");
+ ginfo("Setup framebuffer addresses:\n");
putreg16(((dm320_osd1upperoffset() << 8) |
@@ -809,9 +809,9 @@ static void dm320_hwinitialize(void)
putreg16(dm320_osd0loweroffset(), DM320_OSD_OSDWIN0ADL);
putreg16(dm320_osd1loweroffset(), DM320_OSD_OSDWIN1ADL);
- gvdbg("DM320_OSD_OSDWINADH: %04x\n", getreg16(DM320_OSD_OSDWINADH));
- gvdbg("DM320_OSD_OSDWIN0ADL: %04x\n", getreg16(DM320_OSD_OSDWIN0ADL));
- gvdbg("DM320_OSD_OSDWIN1ADL: %04x\n", getreg16(DM320_OSD_OSDWIN1ADL));
+ ginfo("DM320_OSD_OSDWINADH: %04x\n", getreg16(DM320_OSD_OSDWINADH));
+ ginfo("DM320_OSD_OSDWIN0ADL: %04x\n", getreg16(DM320_OSD_OSDWIN0ADL));
+ ginfo("DM320_OSD_OSDWIN1ADL: %04x\n", getreg16(DM320_OSD_OSDWIN1ADL));
/* Set up VID WIN0 */
@@ -820,19 +820,19 @@ static void dm320_hwinitialize(void)
#endif
#ifndef CONFIG_DM320_VID0_DISABLE
- gvdbg("Initialize video win0:\n");
+ ginfo("Initialize video win0:\n");
putreg16(dm320_vid0loweroffset(), DM320_OSD_VIDWIN0ADL);
- gvdbg("DM320_OSD_VIDWINADH: %04x\n", getreg16(DM320_OSD_VIDWINADH));
- gvdbg("DM320_OSD_VIDWIN0ADL: %04x\n", getreg16(DM320_OSD_VIDWIN0ADL));
+ ginfo("DM320_OSD_VIDWINADH: %04x\n", getreg16(DM320_OSD_VIDWINADH));
+ ginfo("DM320_OSD_VIDWIN0ADL: %04x\n", getreg16(DM320_OSD_VIDWIN0ADL));
dm320_blankscreen((uint8_t *)g_vid0base, DM320_VID0_FBLEN);
#ifndef CONFIG_DM320_DISABLE_PINGPONG
putreg16(dm320_vid0ppupperoffset(), DM320_OSD_PPVWIN0ADH);
putreg16(dm320_vid0pploweroffset(), DM320_OSD_PPVWIN0ADL);
- gvdbg("DM320_OSD_PPVWIN0ADH: %04x\n", getreg16(DM320_OSD_PPVWIN0ADH));
- gvdbg("DM320_OSD_PPVWIN0ADL: %04x\n", getreg16(DM320_OSD_PPVWIN0ADL));
+ ginfo("DM320_OSD_PPVWIN0ADH: %04x\n", getreg16(DM320_OSD_PPVWIN0ADH));
+ ginfo("DM320_OSD_PPVWIN0ADL: %04x\n", getreg16(DM320_OSD_PPVWIN0ADL));
dm320_blankscreen((uint8_t *)g_vid0ppbase, DM320_VID0_FBLEN);
#endif
@@ -842,21 +842,21 @@ static void dm320_hwinitialize(void)
putreg16(CONFIG_DM320_VID0_XRES, DM320_OSD_VIDWIN0XL);
putreg16(CONFIG_DM320_VID0_YRES, DM320_OSD_VIDWIN0YL);
- gvdbg("DM320_OSD_VIDWIN0XP: %04x\n", getreg16(DM320_OSD_VIDWIN0XP));
- gvdbg("DM320_OSD_VIDWIN0YP: %04x\n", getreg16(DM320_OSD_VIDWIN0YP));
- gvdbg("DM320_OSD_VIDWIN0OFST: %04x\n", getreg16(DM320_OSD_VIDWIN0OFST));
- gvdbg("DM320_OSD_VIDWIN0XL: %04x\n", getreg16(DM320_OSD_VIDWIN0XL));
- gvdbg("DM320_OSD_VIDWIN0YL: %04x\n", getreg16(DM320_OSD_VIDWIN0YL));
+ ginfo("DM320_OSD_VIDWIN0XP: %04x\n", getreg16(DM320_OSD_VIDWIN0XP));
+ ginfo("DM320_OSD_VIDWIN0YP: %04x\n", getreg16(DM320_OSD_VIDWIN0YP));
+ ginfo("DM320_OSD_VIDWIN0OFST: %04x\n", getreg16(DM320_OSD_VIDWIN0OFST));
+ ginfo("DM320_OSD_VIDWIN0XL: %04x\n", getreg16(DM320_OSD_VIDWIN0XL));
+ ginfo("DM320_OSD_VIDWIN0YL: %04x\n", getreg16(DM320_OSD_VIDWIN0YL));
#endif
/* Set up VID WIN1 */
#ifndef CONFIG_DM320_VID1_DISABLE
- gvdbg("Initialize video win1:\n");
+ ginfo("Initialize video win1:\n");
putreg16(dm320_vid1loweroffset(), DM320_OSD_VIDWIN1ADL);
- gvdbg("DM320_OSD_VIDWINADH: %04x\n", getreg16(DM320_OSD_VIDWINADH));
- gvdbg("DM320_OSD_VIDWIN1ADL: %04x\n", getreg16(DM320_OSD_VIDWIN1ADL));
+ ginfo("DM320_OSD_VIDWINADH: %04x\n", getreg16(DM320_OSD_VIDWINADH));
+ ginfo("DM320_OSD_VIDWIN1ADL: %04x\n", getreg16(DM320_OSD_VIDWIN1ADL));
dm320_blankscreen((uint8_t *)g_vid1base, DM320_VID1_FBLEN);
putreg16(CONFIG_DM320_VID1_XPOS, DM320_OSD_VIDWIN1XP);
@@ -865,20 +865,20 @@ static void dm320_hwinitialize(void)
putreg16(CONFIG_DM320_VID1_XRES, DM320_OSD_VIDWIN1XL);
putreg16(CONFIG_DM320_VID1_YRES, DM320_OSD_VIDWIN1YL);
- gvdbg("DM320_OSD_VIDWIN1XP: %04x\n", getreg16(DM320_OSD_VIDWIN1XP));
- gvdbg("DM320_OSD_VIDWIN1YP: %04x\n", getreg16(DM320_OSD_VIDWIN1YP));
- gvdbg("DM320_OSD_VIDWIN1OFST: %04x\n", getreg16(DM320_OSD_VIDWIN1OFST));
- gvdbg("DM320_OSD_VIDWIN1XL: %04x\n", getreg16(DM320_OSD_VIDWIN1XL));
- gvdbg("DM320_OSD_VIDWIN1YL: %04x\n", getreg16(DM320_OSD_VIDWIN1YL));
+ ginfo("DM320_OSD_VIDWIN1XP: %04x\n", getreg16(DM320_OSD_VIDWIN1XP));
+ ginfo("DM320_OSD_VIDWIN1YP: %04x\n", getreg16(DM320_OSD_VIDWIN1YP));
+ ginfo("DM320_OSD_VIDWIN1OFST: %04x\n", getreg16(DM320_OSD_VIDWIN1OFST));
+ ginfo("DM320_OSD_VIDWIN1XL: %04x\n", getreg16(DM320_OSD_VIDWIN1XL));
+ ginfo("DM320_OSD_VIDWIN1YL: %04x\n", getreg16(DM320_OSD_VIDWIN1YL));
#endif
putreg16(DM320_VIDMODE, DM320_OSD_VIDWINMD);
- gvdbg("DM320_OSD_VIDWINMD: %04x\n", getreg16(DM320_OSD_VIDWINMD));
+ ginfo("DM320_OSD_VIDWINMD: %04x\n", getreg16(DM320_OSD_VIDWINMD));
/* Set up OSD WIN0 */
#ifndef CONFIG_DM320_OSD0_DISABLE
- gvdbg("Initialize OSD win0:\n");
+ ginfo("Initialize OSD win0:\n");
dm320_blankscreen((uint8_t *)g_osd0base, DM320_OSD0_FBLEN);
putreg16(CONFIG_DM320_OSD0_XPOS, DM320_OSD_OSDWIN0XP);
@@ -892,18 +892,18 @@ static void dm320_hwinitialize(void)
putreg16(CONFIG_DM320_OSD0_YRES, DM320_OSD_OSDWIN0YL);
putreg16(INITIAL_OSD0MODE, DM320_OSD_OSDWIN0MD);
- gvdbg("DM320_OSD_OSDWIN0XP: %04x\n", getreg16(DM320_OSD_OSDWIN0XP));
- gvdbg("DM320_OSD_OSDWIN0YP: %04x\n", getreg16(DM320_OSD_OSDWIN0YP));
- gvdbg("DM320_OSD_OSDWIN0OFST: %04x\n", getreg16(DM320_OSD_OSDWIN0OFST));
- gvdbg("DM320_OSD_OSDWIN0XL: %04x\n", getreg16(DM320_OSD_OSDWIN0XL));
- gvdbg("DM320_OSD_OSDWIN0YL: %04x\n", getreg16(DM320_OSD_OSDWIN0YL));
- gvdbg("DM320_OSD_OSDWIN0MD: %04x\n", getreg16(DM320_OSD_OSDWIN0MD));
+ ginfo("DM320_OSD_OSDWIN0XP: %04x\n", getreg16(DM320_OSD_OSDWIN0XP));
+ ginfo("DM320_OSD_OSDWIN0YP: %04x\n", getreg16(DM320_OSD_OSDWIN0YP));
+ ginfo("DM320_OSD_OSDWIN0OFST: %04x\n", getreg16(DM320_OSD_OSDWIN0OFST));
+ ginfo("DM320_OSD_OSDWIN0XL: %04x\n", getreg16(DM320_OSD_OSDWIN0XL));
+ ginfo("DM320_OSD_OSDWIN0YL: %04x\n", getreg16(DM320_OSD_OSDWIN0YL));
+ ginfo("DM320_OSD_OSDWIN0MD: %04x\n", getreg16(DM320_OSD_OSDWIN0MD));
#endif
/* Set up OSD WIN1 */
#ifndef CONFIG_DM320_OSD1_DISABLE
- gvdbg("Initialize OSD win1\n");
+ ginfo("Initialize OSD win1\n");
dm320_blankscreen((uint8_t *)g_osd1base, DM320_OSD1_FBLEN);
putreg16(CONFIG_DM320_OSD1_XPOS, DM320_OSD_OSDWIN1XP);
@@ -917,18 +917,18 @@ static void dm320_hwinitialize(void)
putreg16(CONFIG_DM320_OSD1_YRES, DM320_OSD_OSDWIN1YL);
putreg16(INITIAL_OSD1MODE, DM320_OSD_OSDWIN1MD);
- gvdbg("DM320_OSD_OSDWIN1XP: %04x\n", getreg16(DM320_OSD_OSDWIN1XP));
- gvdbg("DM320_OSD_OSDWIN1YP: %04x\n", getreg16(DM320_OSD_OSDWIN1YP));
- gvdbg("DM320_OSD_OSDWIN1OFST: %04x\n", getreg16(DM320_OSD_OSDWIN1OFST));
- gvdbg("DM320_OSD_OSDWIN1XL: %04x\n", getreg16(DM320_OSD_OSDWIN1XL));
- gvdbg("DM320_OSD_OSDWIN1YL: %04x\n", getreg16(DM320_OSD_OSDWIN1YL));
- gvdbg("DM320_OSD_OSDWIN1MD: %04x\n", getreg16(DM320_OSD_OSDWIN1MD));
+ ginfo("DM320_OSD_OSDWIN1XP: %04x\n", getreg16(DM320_OSD_OSDWIN1XP));
+ ginfo("DM320_OSD_OSDWIN1YP: %04x\n", getreg16(DM320_OSD_OSDWIN1YP));
+ ginfo("DM320_OSD_OSDWIN1OFST: %04x\n", getreg16(DM320_OSD_OSDWIN1OFST));
+ ginfo("DM320_OSD_OSDWIN1XL: %04x\n", getreg16(DM320_OSD_OSDWIN1XL));
+ ginfo("DM320_OSD_OSDWIN1YL: %04x\n", getreg16(DM320_OSD_OSDWIN1YL));
+ ginfo("DM320_OSD_OSDWIN1MD: %04x\n", getreg16(DM320_OSD_OSDWIN1MD));
#endif
/* Set up the rectangular cursor with defaults */
#ifdef CONFIG_FB_HWCURSOR
- gdbg("Initialize rectangular cursor\n");
+ lcdinfo("Initialize rectangular cursor\n");
putreg16(0, DM320_OSD_CURXP);
putreg16(0, DM320_OSD_CURYP);
@@ -946,11 +946,11 @@ static void dm320_hwinitialize(void)
putreg16(DM320_RECTCURSOR_SETUP, DM320_OSD_RECTCUR);
- gvdbg("DM320_OSD_CURXP: %04x\n", getreg16(DM320_OSD_CURXP));
- gvdbg("DM320_OSD_CURYP: %04x\n", getreg16(DM320_OSD_CURYP));
- gvdbg("DM320_OSD_CURXL: %04x\n", getreg16(DM320_OSD_CURXL));
- gvdbg("DM320_OSD_CURYL: %04x\n", getreg16(DM320_OSD_CURYL));
- gvdbg("DM320_OSD_RECTCUR: %04x\n", getreg16(DM320_OSD_RECTCUR));
+ ginfo("DM320_OSD_CURXP: %04x\n", getreg16(DM320_OSD_CURXP));
+ ginfo("DM320_OSD_CURYP: %04x\n", getreg16(DM320_OSD_CURYP));
+ ginfo("DM320_OSD_CURXL: %04x\n", getreg16(DM320_OSD_CURXL));
+ ginfo("DM320_OSD_CURYL: %04x\n", getreg16(DM320_OSD_CURYL));
+ ginfo("DM320_OSD_RECTCUR: %04x\n", getreg16(DM320_OSD_RECTCUR));
#endif
/* Set main window to the hardware default state. That initial
@@ -969,7 +969,7 @@ static void dm320_hwinitialize(void)
*/
putreg16(CONFIG_DM320_BKGDCLUT, DM320_OSD_OSDMODE);
- gvdbg("DM320_OSD_OSDMODE: %04x\n", getreg16(DM320_OSD_OSDMODE));
+ ginfo("DM320_OSD_OSDMODE: %04x\n", getreg16(DM320_OSD_OSDMODE));
}
/****************************************************************************
@@ -980,7 +980,7 @@ static void dm320_hwinitialize(void)
static int dm320_getvid0videoinfo(FAR struct fb_vtable_s *vtable,
FAR struct fb_videoinfo_s *vinfo)
{
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!vtable || !vinfo)
{
return -EINVAL;
@@ -1003,7 +1003,7 @@ static int dm320_getvid0videoinfo(FAR struct fb_vtable_s *vtable,
static int dm320_getvid0planeinfo(FAR struct fb_vtable_s *vtable, int planeno,
FAR struct fb_planeinfo_s *pinfo)
{
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!vtable || !pinfo)
{
return -EINVAL;
@@ -1027,7 +1027,7 @@ static int dm320_getvid0planeinfo(FAR struct fb_vtable_s *vtable, int planeno,
static int dm320_getvid1videoinfo(FAR struct fb_vtable_s *vtable,
FAR struct fb_videoinfo_s *vinfo)
{
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!vtable || !vinfo)
{
return -EINVAL;
@@ -1050,7 +1050,7 @@ static int dm320_getvid1videoinfo(FAR struct fb_vtable_s *vtable,
static int dm320_getvid1planeinfo(FAR struct fb_vtable_s *vtable, int planeno,
FAR struct fb_planeinfo_s *pinfo)
{
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!vtable || !pinfo)
{
return -EINVAL;
@@ -1074,7 +1074,7 @@ static int dm320_getvid1planeinfo(FAR struct fb_vtable_s *vtable, int planeno,
static int dm320_getosd0videoinfo(FAR struct fb_vtable_s *vtable,
FAR struct fb_videoinfo_s *vinfo)
{
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!vtable || !vinfo)
{
return -EINVAL;
@@ -1101,7 +1101,7 @@ static int dm320_getosd0videoinfo(FAR struct fb_vtable_s *vtable,
static int dm320_getosd0planeinfo(FAR struct fb_vtable_s *vtable, int planeno,
FAR struct fb_planeinfo_s *pinfo)
{
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!vtable || !pinfo)
{
return -EINVAL;
@@ -1125,7 +1125,7 @@ static int dm320_getosd0planeinfo(FAR struct fb_vtable_s *vtable, int planeno,
static int dm320_getosd1videoinfo(FAR struct fb_vtable_s *vtable,
FAR struct fb_videoinfo_s *vinfo)
{
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!vtable || !vinfo)
{
return -EINVAL;
@@ -1152,7 +1152,7 @@ static int dm320_getosd1videoinfo(FAR struct fb_vtable_s *vtable,
static int dm320_getosd1planeinfo(FAR struct fb_vtable_s *vtable, int planeno,
FAR struct fb_planeinfo_s *pinfo)
{
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!vtable || !pinfo)
{
return -EINVAL;
@@ -1196,7 +1196,7 @@ static int dm320_putcmap(FAR struct fb_vtable_s *vtable, FAR struct fb_cmap_s *c
int len
int i;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!vtable || !cmap || !cmap->read || !cmap->green || !cmap->blue)
{
return -EINVAL;
@@ -1245,7 +1245,7 @@ static int dm320_getcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_cursora
{
irqstate_t flags;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!vtable || !attrib)
{
return -EINVAL;
@@ -1265,16 +1265,16 @@ static int dm320_getcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_cursora
attrib->mxsize.w = MAX_XRES;
attrib->mxsize.h = MAX_YRES;
- gvdbg("DM320_OSD_CURXP: %04x\n", attrib->pos.x);
- gvdbg("DM320_OSD_CURYP: %04x\n", attrib->pos.y);
+ ginfo("DM320_OSD_CURXP: %04x\n", attrib->pos.x);
+ ginfo("DM320_OSD_CURYP: %04x\n", attrib->pos.y);
#ifdef CONFIG_FB_HWCURSORSIZE
- gvdbg("DM320_OSD_CURXL: %04x\n", attrib->size.w);
- gvdbg("DM320_OSD_CURYL: %04x\n", attrib->size.h);
+ ginfo("DM320_OSD_CURXL: %04x\n", attrib->size.w);
+ ginfo("DM320_OSD_CURYL: %04x\n", attrib->size.h);
#else
- gvdbg("DM320_OSD_CURXL: %04x\n", getreg16(DM320_OSD_CURXL));
- gvdbg("DM320_OSD_CURYL: %04x\n", getreg16(DM320_OSD_CURYL));
+ ginfo("DM320_OSD_CURXL: %04x\n", getreg16(DM320_OSD_CURXL));
+ ginfo("DM320_OSD_CURYL: %04x\n", getreg16(DM320_OSD_CURYL));
#endif
- gvdbg("DM320_OSD_RECTCUR: %04x\n", getreg16(DM320_OSD_RECTCUR));
+ ginfo("DM320_OSD_RECTCUR: %04x\n", getreg16(DM320_OSD_RECTCUR));
}
#endif
@@ -1288,7 +1288,7 @@ static int dm320_setcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_setcurs
irqstate_t flags;
uint16_t regval;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!vtable || !settings)
{
return -EINVAL;
@@ -1300,7 +1300,7 @@ static int dm320_setcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_setcurs
flags = enter_critical_section();
if ((settings->flags & FB_CUR_SETPOSITION) != 0)
{
- gvdbg("x=%d y=%d\n", settings->pos.x, settings->pos.y);
+ ginfo("x=%d y=%d\n", settings->pos.x, settings->pos.y);
if (settings->pos.x > MAX_YRES)
{
@@ -1319,7 +1319,7 @@ static int dm320_setcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_setcurs
#ifdef CONFIG_FB_HWCURSORSIZE
if ((settings->flags & FB_CUR_SETSIZE) != 0)
{
- gvdbg("h=%d w=%d\n", settings->size.h, settings->size.w);
+ ginfo("h=%d w=%d\n", settings->size.h, settings->size.w);
if (settings->size.w > MAX_YRES)
{
@@ -1349,11 +1349,11 @@ static int dm320_setcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_setcurs
putreg16(regval, DM320_OSD_RECTCUR);
leave_critical_section(flags);
- gvdbg("DM320_OSD_CURXP: %04x\n", getreg16(DM320_OSD_CURXP));
- gvdbg("DM320_OSD_CURYP: %04x\n", getreg16(DM320_OSD_CURYP));
- gvdbg("DM320_OSD_CURXL: %04x\n", getreg16(DM320_OSD_CURXL));
- gvdbg("DM320_OSD_CURYL: %04x\n", getreg16(DM320_OSD_CURYL));
- gvdbg("DM320_OSD_RECTCUR: %04x\n", getreg16(DM320_OSD_RECTCUR));
+ ginfo("DM320_OSD_CURXP: %04x\n", getreg16(DM320_OSD_CURXP));
+ ginfo("DM320_OSD_CURYP: %04x\n", getreg16(DM320_OSD_CURYP));
+ ginfo("DM320_OSD_CURXL: %04x\n", getreg16(DM320_OSD_CURXL));
+ ginfo("DM320_OSD_CURYL: %04x\n", getreg16(DM320_OSD_CURYL));
+ ginfo("DM320_OSD_RECTCUR: %04x\n", getreg16(DM320_OSD_RECTCUR));
}
#endif
@@ -1381,17 +1381,17 @@ int up_fbinitialize(int display)
{
int ret;
- gvdbg("Allocating framebuffers\n");
+ ginfo("Allocating framebuffers\n");
ret = dm320_allocvideomemory();
if (ret != 0)
{
- gdbg("Failed to allocate video buffers\n");
+ lcderr("ERROR: Failed to allocate video buffers\n");
return ret;
}
/* Initialize the hardware */
- gvdbg("Initializing hardware\n");
+ ginfo("Initializing hardware\n");
dm320_hwinitialize();
return 0;
}
diff --git a/arch/arm/src/dm320/dm320_usbdev.c b/arch/arm/src/dm320/dm320_usbdev.c
index f0f87b7f584c88cbe5ca18d1eac7ebf1bc4b2102..df25123b09ec08ed7062a6572bd1448877386802 100644
--- a/arch/arm/src/dm320/dm320_usbdev.c
+++ b/arch/arm/src/dm320/dm320_usbdev.c
@@ -268,7 +268,7 @@ struct dm320_epinfo_s
/* Register operations */
-#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_DM320_USBDEV_REGDEBUG
static uint32_t dm320_getreg8(uint32_t addr);
static uint32_t dm320_getreg16(uint32_t addr);
static uint32_t dm320_getreg32(uint32_t addr);
@@ -422,7 +422,7 @@ static const struct dm320_epinfo_s g_epinfo[DM320_NENDPOINTS] =
*
****************************************************************************/
-#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_DM320_USBDEV_REGDEBUG
static uint8_t dm320_getreg8(uint32_t addr)
{
static uint32_t prevaddr = 0;
@@ -443,7 +443,7 @@ static uint8_t dm320_getreg8(uint32_t addr)
{
if (count == 4)
{
- lldbg("...\n");
+ uinfo("...\n");
}
return val;
@@ -460,7 +460,7 @@ static uint8_t dm320_getreg8(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -472,7 +472,7 @@ static uint8_t dm320_getreg8(uint32_t addr)
/* Show the register value read */
- lldbg("%08x->%02x\n", addr, val);
+ uinfo("%08x->%02x\n", addr, val);
return val;
}
#endif
@@ -485,7 +485,7 @@ static uint8_t dm320_getreg8(uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_DM320_USBDEV_REGDEBUG
static uint32_t dm320_getreg16(uint32_t addr)
{
static uint32_t prevaddr = 0;
@@ -506,7 +506,7 @@ static uint32_t dm320_getreg16(uint32_t addr)
{
if (count == 4)
{
- lldbg("...\n");
+ uinfo("...\n");
}
return val;
@@ -523,7 +523,7 @@ static uint32_t dm320_getreg16(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -535,7 +535,7 @@ static uint32_t dm320_getreg16(uint32_t addr)
/* Show the register value read */
- lldbg("%08x->%04x\n", addr, val);
+ uinfo("%08x->%04x\n", addr, val);
return val;
}
#endif
@@ -548,7 +548,7 @@ static uint32_t dm320_getreg16(uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_DM320_USBDEV_REGDEBUG
static uint32_t dm320_getreg32(uint32_t addr)
{
static uint32_t prevaddr = 0;
@@ -569,7 +569,7 @@ static uint32_t dm320_getreg32(uint32_t addr)
{
if (count == 4)
{
- lldbg("...\n");
+ uinfo("...\n");
}
return val;
@@ -586,7 +586,7 @@ static uint32_t dm320_getreg32(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -598,7 +598,7 @@ static uint32_t dm320_getreg32(uint32_t addr)
/* Show the register value read */
- lldbg("%08x->%08x\n", addr, val);
+ uinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@@ -611,12 +611,12 @@ static uint32_t dm320_getreg32(uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_DM320_USBDEV_REGDEBUG
static void dm320_putreg8(uint8_t val, uint32_t addr)
{
/* Show the register value being written */
- lldbg("%08x<-%02x\n", addr, val);
+ uinfo("%08x<-%02x\n", addr, val);
/* Write the value */
@@ -632,12 +632,12 @@ static void dm320_putreg8(uint8_t val, uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_DM320_USBDEV_REGDEBUG
static void dm320_putreg16(uint16_t val, uint32_t addr)
{
/* Show the register value being written */
- lldbg("%08x<-%04x\n", addr, val);
+ uinfo("%08x<-%04x\n", addr, val);
/* Write the value */
@@ -653,12 +653,12 @@ static void dm320_putreg16(uint16_t val, uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_DM320_USBDEV_REGDEBUG
static void dm320_putreg32(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- lldbg("%08x<-%08x\n", addr, val);
+ uinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@@ -1216,8 +1216,8 @@ static inline void dm320_ep0setup(struct dm320_usbdev_s *priv)
value = GETUINT16(ctrl.value);
len = GETUINT16(ctrl.len);
- ullvdbg("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- ctrl.type, ctrl.req, value, index, len);
+ uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ ctrl.type, ctrl.req, value, index, len);
/* Dispatch any non-standard requests */
@@ -1618,7 +1618,7 @@ static int dm320_ctlrinterrupt(int irq, FAR void *context)
}
else
{
- ullvdbg("Pending data on OUT endpoint\n");
+ uinfo("Pending data on OUT endpoint\n");
priv->rxpending = 1;
}
}
@@ -1943,7 +1943,7 @@ static int dm320_epdisable(FAR struct usbdev_ep_s *ep)
FAR struct dm320_ep_s *privep = (FAR struct dm320_ep_s *)ep;
irqstate_t flags;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep)
{
usbtrace(TRACE_DEVERROR(DM320_TRACEERR_INVALIDPARMS), 0);
@@ -1974,7 +1974,7 @@ static FAR struct usbdev_req_s *dm320_epallocreq(FAR struct usbdev_ep_s *ep)
{
FAR struct dm320_req_s *privreq;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep)
{
return NULL;
@@ -2005,7 +2005,7 @@ static void dm320_epfreereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s
{
FAR struct dm320_req_s *privreq = (FAR struct dm320_req_s *)req;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(DM320_TRACEERR_INVALIDPARMS), 0);
@@ -2075,7 +2075,7 @@ static int dm320_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
irqstate_t flags;
int ret = OK;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(DM320_TRACEERR_INVALIDPARMS), 0);
@@ -2170,7 +2170,7 @@ static int dm320_epcancel(struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req)
FAR struct dm320_usbdev_s *priv;
irqstate_t flags;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(DM320_TRACEERR_INVALIDPARMS), 0);
@@ -2293,7 +2293,7 @@ static int dm320_getframe(struct usbdev_s *dev)
usbtrace(TRACE_DEVGETFRAME, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!dev)
{
usbtrace(TRACE_DEVERROR(DM320_TRACEERR_INVALIDPARMS), 0);
@@ -2345,7 +2345,7 @@ static int dm320_selfpowered(struct usbdev_s *dev, bool selfpowered)
usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!dev)
{
usbtrace(TRACE_DEVERROR(DM320_TRACEERR_INVALIDPARMS), 0);
@@ -2415,9 +2415,9 @@ void up_usbinitialize(void)
memset(priv, 0, sizeof(struct dm320_usbdev_s));
priv->usbdev.ops = &g_devops;
-#ifdef CONFIG_DEBUG_USB
+#ifdef CONFIG_DEBUG_USB_INFO
chiprev = dm320_getreg16(DM320_BUSC_REVR);
- ulldbg("DM320 revision : %d.%d\n", chiprev >> 4, chiprev & 0x0f);
+ uinfo("DM320 revision : %d.%d\n", chiprev >> 4, chiprev & 0x0f);
#endif
/* Enable USB clock & GIO clock */
@@ -2544,7 +2544,7 @@ int usbdev_register(FAR struct usbdevclass_driver_s *driver)
usbtrace(TRACE_DEVREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!driver || (driver->speed != USB_SPEED_FULL) || !driver->ops->bind ||
!driver->ops->unbind || !driver->ops->setup)
{
@@ -2602,7 +2602,7 @@ int usbdev_unregister(FAR struct usbdevclass_driver_s *driver)
{
usbtrace(TRACE_DEVUNREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (driver != g_usbdev.driver)
{
usbtrace(TRACE_DEVERROR(DM320_TRACEERR_INVALIDPARMS), 0);
diff --git a/arch/arm/src/efm32/Kconfig b/arch/arm/src/efm32/Kconfig
index ad1abfbfa06550a44aeb96d644df6eed23467004..877cca10740d2309d6d0830c87e6d79f490e2eb9 100644
--- a/arch/arm/src/efm32/Kconfig
+++ b/arch/arm/src/efm32/Kconfig
@@ -140,7 +140,7 @@ config EFM32_FLASHPROG
config EFM32_RMU_DEBUG
bool "Reset Management Unit (RMU) DEBUG "
default n
- depends on EFM32_RMU && DEBUG
+ depends on EFM32_RMU && DEBUG_FEATURES
config EFM32_I2C0
bool "I2C0"
diff --git a/arch/arm/src/efm32/efm32_adc.c b/arch/arm/src/efm32/efm32_adc.c
index 53cb731ad6091b64e8682a580d9b2779f81d5bfc..c9e339e6ea27e8495b2eafddd16892bb0cf14873 100644
--- a/arch/arm/src/efm32/efm32_adc.c
+++ b/arch/arm/src/efm32/efm32_adc.c
@@ -716,23 +716,23 @@ endif /* defined(ADC_COUNT) && (ADC_COUNT > 0) */
#ifdef ADC_HAVE_TIMER
static void adc_tim_dumpregs(struct efm32_dev_s *priv, FAR const char *msg)
{
-#if defined(CONFIG_DEBUG_ANALOG) && defined(CONFIG_DEBUG_VERBOSE)
- avdbg("%s:\n", msg);
- avdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
+#if defined(CONFIG_DEBUG_ANALOG) && defined(CONFIG_DEBUG_INFO)
+ ainfo("%s:\n", msg);
+ ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
tim_getreg(priv, EFM32_GTIM_CR1_OFFSET),
tim_getreg(priv, EFM32_GTIM_CR2_OFFSET),
tim_getreg(priv, EFM32_GTIM_SMCR_OFFSET),
tim_getreg(priv, EFM32_GTIM_DIER_OFFSET));
- avdbg(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n",
+ ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n",
tim_getreg(priv, EFM32_GTIM_SR_OFFSET),
tim_getreg(priv, EFM32_GTIM_CCMR1_OFFSET),
tim_getreg(priv, EFM32_GTIM_CCMR2_OFFSET));
- avdbg(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
+ ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
tim_getreg(priv, EFM32_GTIM_CCER_OFFSET),
tim_getreg(priv, EFM32_GTIM_CNT_OFFSET),
tim_getreg(priv, EFM32_GTIM_PSC_OFFSET),
tim_getreg(priv, EFM32_GTIM_ARR_OFFSET));
- avdbg(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
+ ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
tim_getreg(priv, EFM32_GTIM_CCR1_OFFSET),
tim_getreg(priv, EFM32_GTIM_CCR2_OFFSET),
tim_getreg(priv, EFM32_GTIM_CCR3_OFFSET),
@@ -740,7 +740,7 @@ static void adc_tim_dumpregs(struct efm32_dev_s *priv, FAR const char *msg)
if (priv->tbase == EFM32_TIM1_BASE || priv->tbase == EFM32_TIM8_BASE)
{
- avdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
+ ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
tim_getreg(priv, EFM32_ATIM_RCR_OFFSET),
tim_getreg(priv, EFM32_ATIM_BDTR_OFFSET),
tim_getreg(priv, EFM32_ATIM_DCR_OFFSET),
@@ -748,7 +748,7 @@ static void adc_tim_dumpregs(struct efm32_dev_s *priv, FAR const char *msg)
}
else
{
- avdbg(" DCR: %04x DMAR: %04x\n",
+ ainfo(" DCR: %04x DMAR: %04x\n",
tim_getreg(priv, EFM32_GTIM_DCR_OFFSET),
tim_getreg(priv, EFM32_GTIM_DMAR_OFFSET));
}
@@ -775,7 +775,7 @@ static void adc_startconv(struct efm32_dev_s *priv, bool enable)
{
uint32_t regval;
- avdbg("enable: %d\n", enable);
+ ainfo("enable: %d\n", enable);
regval = adc_getreg(priv, EFM32_ADC_CR2_OFFSET);
if (enable)
@@ -864,7 +864,7 @@ static void adc_enable(FAR struct efm32_dev_s *priv, bool enable)
{
uint32_t regval;
- avdbg("enable: %d\n", enable);
+ ainfo("enable: %d\n", enable);
regval = adc_getreg(priv, EFM32_ADC_CR2_OFFSET);
if (enable)
@@ -922,7 +922,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
int ret;
#endif
- avdbg("intf: ADC%d\n", priv->intf);
+ ainfo("intf: ADC%d\n", priv->intf);
flags = enter_critical_section();
/* Enable ADC reset state */
@@ -1040,11 +1040,11 @@ static void adc_reset(FAR struct adc_dev_s *dev)
leave_critical_section(flags);
- avdbg("SR: 0x%08x CR1: 0x%08x CR2: 0x%08x\n",
+ ainfo("SR: 0x%08x CR1: 0x%08x CR2: 0x%08x\n",
adc_getreg(priv, EFM32_ADC_SR_OFFSET),
adc_getreg(priv, EFM32_ADC_CR1_OFFSET),
adc_getreg(priv, EFM32_ADC_CR2_OFFSET));
- avdbg("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n",
+ ainfo("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n",
adc_getreg(priv, EFM32_ADC_SQR1_OFFSET),
adc_getreg(priv, EFM32_ADC_SQR2_OFFSET),
adc_getreg(priv, EFM32_ADC_SQR3_OFFSET));
@@ -1081,7 +1081,7 @@ static int adc_setup(FAR struct adc_dev_s *dev)
/* Enable the ADC interrupt */
- avdbg("Enable the ADC interrupt: irq=%d\n", priv->irq);
+ ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq);
up_enable_irq(priv->irq);
}
@@ -1132,7 +1132,7 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
FAR struct efm32_dev_s *priv = (FAR struct efm32_dev_s *)dev->ad_priv;
uint32_t regval;
- avdbg("intf: %d enable: %d\n", priv->intf, enable);
+ ainfo("intf: %d enable: %d\n", priv->intf, enable);
regval = adc_getreg(priv, EFM32_ADC_CR1_OFFSET);
if (enable)
@@ -1191,7 +1191,7 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
adcsr = adc_getreg(priv, EFM32_ADC_SR_OFFSET);
if ((adcsr & ADC_SR_AWD) != 0)
{
- alldbg("WARNING: Analog Watchdog, Value converted out of range!\n");
+ awarn("WARNING: Analog Watchdog, Value converted out of range!\n");
}
/* EOC: End of conversion */
@@ -1271,12 +1271,12 @@ struct adc_dev_s *efm32_adcinitialize(int intf, const uint8_t *chanlist, int nch
FAR struct adc_dev_s *dev;
FAR struct efm32_dev_s *priv;
- avdbg("intf: %d nchannels: %d\n", intf, nchannels);
+ ainfo("intf: %d nchannels: %d\n", intf, nchannels);
#ifdef CONFIG_EFM32_ADC1
if (intf == 1)
{
- avdbg("ADC1 Selected\n");
+ ainfo("ADC1 Selected\n");
dev = &g_adcdev1;
}
else
@@ -1284,7 +1284,7 @@ struct adc_dev_s *efm32_adcinitialize(int intf, const uint8_t *chanlist, int nch
#ifdef CONFIG_EFM32_ADC2
if (intf == 2)
{
- avdbg("ADC2 Selected\n");
+ ainfo("ADC2 Selected\n");
dev = &g_adcdev2;
}
else
@@ -1292,13 +1292,13 @@ struct adc_dev_s *efm32_adcinitialize(int intf, const uint8_t *chanlist, int nch
#ifdef CONFIG_EFM32_ADC3
if (intf == 3)
{
- avdbg("ADC3 Selected\n");
+ ainfo("ADC3 Selected\n");
dev = &g_adcdev3;
}
else
#endif
{
- adbg("No ADC interface defined\n");
+ aerr("ERROR: No ADC interface defined\n");
return NULL;
}
diff --git a/arch/arm/src/efm32/efm32_clockconfig.c b/arch/arm/src/efm32/efm32_clockconfig.c
index e2f0d3b5df7fc7530b39e467470ce7f587dc56d0..5ecdf03c12fe5f2c9adc043093ef2c81a937560e 100644
--- a/arch/arm/src/efm32/efm32_clockconfig.c
+++ b/arch/arm/src/efm32/efm32_clockconfig.c
@@ -450,7 +450,7 @@ static inline uint32_t efm32_hfclk_config(uint32_t hfclksel, uint32_t hfclkdiv)
}
break;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
default:
PANIC();
#endif
@@ -884,7 +884,7 @@ static inline void efm32_gpioclock(void)
*
****************************************************************************/
-#if defined(CONFIG_SYSLOG) || defined(CONFIG_ARMV7M_ITMSYSLOG)
+#ifdef CONFIG_ARMV7M_ITMSYSLOG
static inline void efm32_itm_syslog(void)
{
int regval;
diff --git a/arch/arm/src/efm32/efm32_config.h b/arch/arm/src/efm32/efm32_config.h
index b60c3a60e4dcb267198c7bd710df888e5c5937fe..f0bf6335d96aa4f9eb6171cc499352bec686af34 100644
--- a/arch/arm/src/efm32/efm32_config.h
+++ b/arch/arm/src/efm32/efm32_config.h
@@ -127,7 +127,7 @@
#undef HAVE_UART_CONSOLE
#undef HAVE_LEUART_CONSOLE
-#if defined(CONFIG_SYSLOG_CONSOLE)
+#if defined(CONFIG_CONSOLE_SYSLOG)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_UART0_SERIAL_CONSOLE
diff --git a/arch/arm/src/efm32/efm32_dma.c b/arch/arm/src/efm32/efm32_dma.c
index a96bc160c0de6a072f6d9b4e3227ff576f5eec97..4bf901500b604b5498b2f9bdbef98625c4dc0f97 100644
--- a/arch/arm/src/efm32/efm32_dma.c
+++ b/arch/arm/src/efm32/efm32_dma.c
@@ -270,7 +270,7 @@ void weak_function up_dmainitialize(void)
uint32_t regval;
int i;
- dmallvdbg("Initialize XDMAC0\n");
+ dmainfo("Initialize XDMAC0\n");
/* Initialize the channel list */
@@ -416,7 +416,7 @@ void efm32_dmafree(DMA_HANDLE handle)
struct dma_channel_s *dmach = (struct dma_channel_s *)handle;
DEBUGASSERT(dmach != NULL && dmach->inuse);
- dmavdbg("DMA channel %d\n", dmach->chan);
+ dmainfo("DMA channel %d\n", dmach->chan);
/* Disable the channel */
@@ -745,7 +745,7 @@ void efm32_dmastop(DMA_HANDLE handle)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void efm32_dmasample(DMA_HANDLE handle, struct efm32_dmaregs_s *regs)
{
struct dma_channel_s *dmach = (struct dma_channel_s *)handle;
@@ -798,35 +798,35 @@ void efm32_dmasample(DMA_HANDLE handle, struct efm32_dmaregs_s *regs)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void efm32_dmadump(DMA_HANDLE handle, const struct efm32_dmaregs_s *regs,
const char *msg)
{
struct dma_channel_s *dmach = (struct dma_channel_s *)handle;
- dmadbg("%s\n", msg);
- dmadbg(" DMA Registers:\n");
- dmadbg(" STATUS: %08x\n", regs->status);
- dmadbg(" CTRLBASE: %08x\n", regs->ctrlbase);
- dmadbg(" ALTCTRLBASE: %08x\n", regs->altctrlbase);
- dmadbg(" CHWAITSTATUS: %08x\n", regs->chwaitstatus);
- dmadbg(" CHUSEBURSTS: %08x\n", regs->chusebursts);
- dmadbg(" CHREQMASKS: %08x\n", regs->chreqmasks);
- dmadbg(" CHENS: %08x\n", regs->chens);
- dmadbg(" CHALTS: %08x\n", regs->chalts);
- dmadbg(" CHPRIS: %08x\n", regs->chpris);
- dmadbg(" ERRORC: %08x\n", regs->errorc);
- dmadbg(" CHREQSTATUS: %08x\n", regs->chreqstatus);
- dmadbg(" CHSREQSTATUS: %08x\n", regs->chsreqstatus);
- dmadbg(" IEN: %08x\n", regs->ien);
+ dmainfo("%s\n", msg);
+ dmainfo(" DMA Registers:\n");
+ dmainfo(" STATUS: %08x\n", regs->status);
+ dmainfo(" CTRLBASE: %08x\n", regs->ctrlbase);
+ dmainfo(" ALTCTRLBASE: %08x\n", regs->altctrlbase);
+ dmainfo(" CHWAITSTATUS: %08x\n", regs->chwaitstatus);
+ dmainfo(" CHUSEBURSTS: %08x\n", regs->chusebursts);
+ dmainfo(" CHREQMASKS: %08x\n", regs->chreqmasks);
+ dmainfo(" CHENS: %08x\n", regs->chens);
+ dmainfo(" CHALTS: %08x\n", regs->chalts);
+ dmainfo(" CHPRIS: %08x\n", regs->chpris);
+ dmainfo(" ERRORC: %08x\n", regs->errorc);
+ dmainfo(" CHREQSTATUS: %08x\n", regs->chreqstatus);
+ dmainfo(" CHSREQSTATUS: %08x\n", regs->chsreqstatus);
+ dmainfo(" IEN: %08x\n", regs->ien);
#if defined(CONFIG_EFM32_EFM32GG)
- dmadbg(" CTRL: %08x\n", regs->ctrl);
- dmadbg(" RDS: %08x\n", regs->rds);
- dmadbg(" LOOP0: %08x\n", regs->loop0);
- dmadbg(" LOOP1: %08x\n", regs->loop1);
- dmadbg(" RECT0: %08x\n", regs->rect0);
+ dmainfo(" CTRL: %08x\n", regs->ctrl);
+ dmainfo(" RDS: %08x\n", regs->rds);
+ dmainfo(" LOOP0: %08x\n", regs->loop0);
+ dmainfo(" LOOP1: %08x\n", regs->loop1);
+ dmainfo(" RECT0: %08x\n", regs->rect0);
#endif
- dmadbg(" DMA Channel %d Registers:\n", dmach->chan);
- dmadbg(" CHCTRL: %08x\n", regs->chnctrl);
+ dmainfo(" DMA Channel %d Registers:\n", dmach->chan);
+ dmainfo(" CHCTRL: %08x\n", regs->chnctrl);
}
#endif
diff --git a/arch/arm/src/efm32/efm32_dma.h b/arch/arm/src/efm32/efm32_dma.h
index 2cedb881f3822b3203365ba51a074c2747f0dfbb..011a7d987421d0ce823c77dfeb6b9890aecb000a 100644
--- a/arch/arm/src/efm32/efm32_dma.h
+++ b/arch/arm/src/efm32/efm32_dma.h
@@ -109,7 +109,7 @@ typedef FAR void *DMA_HANDLE;
typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
struct efm32_dmaregs_s
{
uint32_t status; /* DMA Status Register */
@@ -282,7 +282,7 @@ void efm32_dmastop(DMA_HANDLE handle);
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void efm32_dmasample(DMA_HANDLE handle, struct efm32_dmaregs_s *regs);
#else
# define efm32_dmasample(handle,regs)
@@ -299,7 +299,7 @@ void efm32_dmasample(DMA_HANDLE handle, struct efm32_dmaregs_s *regs);
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void efm32_dmadump(DMA_HANDLE handle, const struct efm32_dmaregs_s *regs,
const char *msg);
#else
diff --git a/arch/arm/src/efm32/efm32_flash.c b/arch/arm/src/efm32/efm32_flash.c
index a35422b73da9786785ef5b7f692b386b5a4f1031..1353bbbdb12f2cccec47425947f324cf1eb913c2 100644
--- a/arch/arm/src/efm32/efm32_flash.c
+++ b/arch/arm/src/efm32/efm32_flash.c
@@ -845,7 +845,7 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size)
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 0);
-#if (defined(CONFIG_EFM32_EFM32GG) || defined(CONFIG_EFM32_EFM32WG)) && (2==WORDS_PER_DATA_PHASE)
+#if (defined(CONFIG_EFM32_EFM32GG) || defined(CONFIG_EFM32_EFM32WG))
/* Turn off double word write cycle support. */
diff --git a/arch/arm/src/efm32/efm32_gpio.c b/arch/arm/src/efm32/efm32_gpio.c
index 77bc980481dd95c755d85472b73cf584915a8715..7ffc58cf3445f37d7522b8fffc1cec6129eb54eb 100644
--- a/arch/arm/src/efm32/efm32_gpio.c
+++ b/arch/arm/src/efm32/efm32_gpio.c
@@ -390,7 +390,7 @@ bool efm32_gpioread(gpio_pinset_t pinset)
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
int efm32_dumpgpio(uint32_t pinset, const char *msg)
{
#warning Missing logic
diff --git a/arch/arm/src/efm32/efm32_gpio.h b/arch/arm/src/efm32/efm32_gpio.h
index ed54bb5148c80f63ad81b579f1f91840e3933eac..7dc6624975e97b9260f446f6f50b2d7bd8ab7941 100644
--- a/arch/arm/src/efm32/efm32_gpio.h
+++ b/arch/arm/src/efm32/efm32_gpio.h
@@ -50,10 +50,6 @@
************************************************************************************/
/* Configuration ********************************************************************/
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_GPIO
-#endif
-
#define EFM32_NGPIO 5 /* (5) GPIOA-F */
/* Bit-encoded input to efm32_configgpio() *******************************************/
@@ -350,7 +346,7 @@ void efm32_gpioirqclear(int irq);
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
int efm32_dumpgpio(uint32_t pinset, const char *msg);
#else
# define efm32_dumpgpio(p,m)
diff --git a/arch/arm/src/efm32/efm32_i2c.c b/arch/arm/src/efm32/efm32_i2c.c
index 3f4638390e6b5871642d944b870a58353fe9680f..d05f9ae22a6ec6fc9446623a048559b540f1f8f3 100644
--- a/arch/arm/src/efm32/efm32_i2c.c
+++ b/arch/arm/src/efm32/efm32_i2c.c
@@ -134,16 +134,6 @@
/* Debug ****************************************************************************/
-/* CONFIG_DEBUG_I2C + CONFIG_DEBUG enables general I2C debug output. */
-
-#ifdef CONFIG_DEBUG_I2C
-# define i2cdbg dbg
-# define i2cvdbg vdbg
-#else
-# define i2cdbg(x...)
-# define i2cvdbg(x...)
-#endif
-
/* I2C event trace logic. NOTE: trace uses the internal, non-standard,
* low-level debug interface syslog() but does not require that any other debug
* is enabled.
@@ -605,7 +595,7 @@ static inline int efm32_i2c_sem_waitdone(FAR struct efm32_i2c_priv_s *priv)
while (priv->result == I2CRESULT_INPROGRESS);
- i2cvdbg("result: %s elapsed: %d threshold: %d i2c_state %s "
+ i2cinfo("result: %s elapsed: %d threshold: %d i2c_state %s "
"I2Cx_STATES: %08x I2Cx_IF: %08x\n",
efm32_i2c_result_str(priv->result), elapsed, timeout,
efm32_i2c_state_str(priv->i2c_state), priv->i2c_reg_state,
@@ -652,7 +642,7 @@ static inline int efm32_i2c_sem_waitdone(FAR struct efm32_i2c_priv_s *priv)
while ((priv->result == I2CRESULT_INPROGRESS) && elapsed < timeout);
- i2cvdbg("result: %s elapsed: %d threshold: %d i2c_state %s "
+ i2cinfo("result: %s elapsed: %d threshold: %d i2c_state %s "
"I2Cx_STATES: %08x I2Cx_IF: %08x\n",
efm32_i2c_result_str(priv->result), elapsed, timeout,
efm32_i2c_state_str(priv->i2c_state), priv->i2c_reg_state,
@@ -761,7 +751,7 @@ static void efm32_i2c_tracenew(FAR struct efm32_i2c_priv_s *priv)
if (priv->tndx >= (CONFIG_I2C_NTRACE - 1))
{
- i2cdbg("Trace table overflow\n");
+ i2cerr("ERROR: Trace table overflow\n");
return;
}
@@ -1536,9 +1526,9 @@ static int efm32_i2c_transfer(FAR struct i2c_master_s *dev,
{
ret = -ETIMEDOUT;
- i2cdbg("Timed out: I2Cx_STATE: 0x%04x I2Cx_STATUS: 0x%08x\n",
- efm32_i2c_getreg(priv, EFM32_I2C_STATE_OFFSET),
- efm32_i2c_getreg(priv, EFM32_I2C_STATUS_OFFSET));
+ i2cerr("ERROR: Timed out: I2Cx_STATE: 0x%04x I2Cx_STATUS: 0x%08x\n",
+ efm32_i2c_getreg(priv, EFM32_I2C_STATE_OFFSET),
+ efm32_i2c_getreg(priv, EFM32_I2C_STATUS_OFFSET));
/* Abort */
diff --git a/arch/arm/src/efm32/efm32_idle.c b/arch/arm/src/efm32/efm32_idle.c
index 62d4e6315ba8021e99b4390648d63b2dce98d3b6..9a6d9f7e155142fa1a099ec3627a862514c377cf 100644
--- a/arch/arm/src/efm32/efm32_idle.c
+++ b/arch/arm/src/efm32/efm32_idle.c
@@ -110,7 +110,7 @@ static void up_idlepm(void)
/* Perform board-specific, state-dependent logic here */
- llvdbg("newstate= %d oldstate=%d\n", newstate, oldstate);
+ _info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
diff --git a/arch/arm/src/efm32/efm32_irq.c b/arch/arm/src/efm32/efm32_irq.c
index 821d5cdc76d469b0538df013ede64f8509ddecff..63fa4b18ec7bc2e873cfeb0a8a91215691797480 100644
--- a/arch/arm/src/efm32/efm32_irq.c
+++ b/arch/arm/src/efm32/efm32_irq.c
@@ -109,44 +109,46 @@ extern uint32_t _vectors[];
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_IRQ)
+#if defined(CONFIG_DEBUG_IRQ_INFO)
static void efm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
- lldbg("NVIC (%s, irq=%d):\n", msg, irq);
- lldbg(" INTCTRL: %08x VECTAB: %08x\n",
- getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
- lldbg(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
- getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
- getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
- lldbg(" IRQ ENABLE: %08x %08x %08x\n",
- getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
- getreg32(NVIC_IRQ64_95_ENABLE));
- lldbg(" SYSH_PRIO: %08x %08x %08x\n",
- getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
- getreg32(NVIC_SYSH12_15_PRIORITY));
- lldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
- getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
- getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
+
+ irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
+ irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
+ getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
+ irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
+ getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
+ getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
+ irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
+ getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
+ getreg32(NVIC_IRQ64_95_ENABLE));
+ irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
+ getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
+ getreg32(NVIC_SYSH12_15_PRIORITY));
+ irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
+ getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
+ getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 32)
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
- getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
+ getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 48)
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
- getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
+ getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 64)
- lldbg(" %08x\n",
- getreg32(NVIC_IRQ64_67_PRIORITY));
+ irqinfo(" %08x\n",
+ getreg32(NVIC_IRQ64_67_PRIORITY));
#endif
#endif
#endif
+
leave_critical_section(flags);
}
#else
@@ -164,11 +166,11 @@ static void efm32_dumpnvic(const char *msg, int irq)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
static int efm32_nmi(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! NMI received\n");
+ _err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
@@ -176,7 +178,7 @@ static int efm32_nmi(int irq, FAR void *context)
static int efm32_busfault(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
+ _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
}
@@ -184,7 +186,7 @@ static int efm32_busfault(int irq, FAR void *context)
static int efm32_usagefault(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
+ _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
}
@@ -192,7 +194,7 @@ static int efm32_usagefault(int irq, FAR void *context)
static int efm32_pendsv(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! PendSV received\n");
+ _err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
@@ -200,7 +202,7 @@ static int efm32_pendsv(int irq, FAR void *context)
static int efm32_dbgmonitor(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Debug Monitor received\n");
+ _err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
}
@@ -208,7 +210,7 @@ static int efm32_dbgmonitor(int irq, FAR void *context)
static int efm32_reserved(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Reserved interrupt\n");
+ _err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
@@ -448,7 +450,7 @@ void up_irqinitialize(void)
/* Attach all other processor exceptions (except reset and sys tick) */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
irq_attach(EFM32_IRQ_NMI, efm32_nmi);
#ifndef CONFIG_ARM_MPU
irq_attach(EFM32_IRQ_MEMFAULT, up_memfault);
diff --git a/arch/arm/src/efm32/efm32_leserial.c b/arch/arm/src/efm32/efm32_leserial.c
index e57af783531a4c39980ec868be90b3534fed7043..8a5de9378880d1ccffa5f89d037a6b1165536a9f 100644
--- a/arch/arm/src/efm32/efm32_leserial.c
+++ b/arch/arm/src/efm32/efm32_leserial.c
@@ -119,7 +119,7 @@
#define EFM32_TXERR_INTS (LEUART_IEN_TXOF)
#define EFM32_RXERR_INTS (LEUART_IEN_RXOF | LEUART_IEN_PERR | \
LEUART_IEN_FERR)
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
# define EFM32_TX_INTS (LEUART_IEN_TXBL | EFM32_TXERR_INTS)
# define EFM32_RX_INTS (LEUART_IEN_RXDATAV | EFM32_RXERR_INTS)
#else
@@ -506,7 +506,7 @@ static int efm32_interrupt(struct uart_dev_s *dev)
uart_xmitchars(dev);
}
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
/* Check for receive errors */
if ((intflags & EFM32_RXERR_INTS) != 0)
@@ -518,7 +518,7 @@ static int efm32_interrupt(struct uart_dev_s *dev)
* FERR - Framing Error Interrupt Enable
*/
- lldbg("RX ERROR: %08x\n", intflags);
+ _err("RX ERROR: %08x\n", intflags);
}
/* Check for transmit errors */
@@ -527,7 +527,7 @@ static int efm32_interrupt(struct uart_dev_s *dev)
{
/* TXOF - TX Overflow Interrupt Enable */
- lldbg("RX ERROR: %08x\n", intflags);
+ _err("RX ERROR: %08x\n", intflags);
}
#endif
diff --git a/arch/arm/src/efm32/efm32_pwm.c b/arch/arm/src/efm32/efm32_pwm.c
index 04941d44344cae714da23e60e40ac909b4ec1937..b34d8aeb2ff9b1bd8ff5658898c25e49604252c2 100644
--- a/arch/arm/src/efm32/efm32_pwm.c
+++ b/arch/arm/src/efm32/efm32_pwm.c
@@ -75,29 +75,10 @@
/* The following definitions are used to identify the various time types */
/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing PWM */
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_PWM
-#endif
-
-#ifdef CONFIG_DEBUG_PWM
-# define pwmdbg dbg
-# define pwmlldbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define pwmvdbg vdbg
-# define pwmllvdbg llvdbg
-# define pwm_dumpgpio(p,m) efm32_dumpgpio(p,m)
-# else
-# define pwmlldbg(x...)
-# define pwmllvdbg(x...)
-# define pwm_dumpgpio(p,m)
-# endif
+
+#ifdef CONFIG_DEBUG_PWM_INFO
+# define pwm_dumpgpio(p,m) efm32_dumpgpio(p,m)
#else
-# define pwmdbg(x...)
-# define pwmlldbg(x...)
-# define pwmvdbg(x...)
-# define pwmllvdbg(x...)
# define pwm_dumpgpio(p,m)
#endif
@@ -136,7 +117,7 @@ static uint32_t pwm_getreg(struct efm32_pwmtimer_s *priv, int offset);
static void pwm_putreg(struct efm32_pwmtimer_s *priv, int offset,
uint32_t value);
-#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_PWM_INFO
static void pwm_dumpregs(struct efm32_pwmtimer_s *priv, FAR const char *msg);
#else
# define pwm_dumpregs(priv,msg)
@@ -323,29 +304,29 @@ static void pwm_putreg(struct efm32_pwmtimer_s *priv, int offset, uint32_t value
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_PWM_INFO
static void pwm_dumpregs(struct efm32_pwmtimer_s *priv, FAR const char *msg)
{
/* TODO debug pwm_dumpregs */
#if 0
- pwmvdbg("%s:\n", msg);
- pwmvdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
+ pwminfo("%s:\n", msg);
+ pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
pwm_getreg(priv, STM32_GTIM_CR1_OFFSET),
pwm_getreg(priv, STM32_GTIM_CR2_OFFSET),
pwm_getreg(priv, STM32_GTIM_SMCR_OFFSET),
pwm_getreg(priv, STM32_GTIM_DIER_OFFSET));
- pwmvdbg(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n",
+ pwminfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n",
pwm_getreg(priv, STM32_GTIM_SR_OFFSET),
pwm_getreg(priv, STM32_GTIM_EGR_OFFSET),
pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET),
pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET));
- pwmvdbg(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
+ pwminfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
pwm_getreg(priv, STM32_GTIM_CCER_OFFSET),
pwm_getreg(priv, STM32_GTIM_CNT_OFFSET),
pwm_getreg(priv, STM32_GTIM_PSC_OFFSET),
pwm_getreg(priv, STM32_GTIM_ARR_OFFSET));
- pwmvdbg(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
+ pwminfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET),
pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET),
pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET),
@@ -353,7 +334,7 @@ static void pwm_dumpregs(struct efm32_pwmtimer_s *priv, FAR const char *msg)
#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM)
if (priv->timtype == TIMTYPE_ADVANCED)
{
- pwmvdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
+ pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
pwm_getreg(priv, STM32_ATIM_RCR_OFFSET),
pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET),
pwm_getreg(priv, STM32_ATIM_DCR_OFFSET),
@@ -362,7 +343,7 @@ static void pwm_dumpregs(struct efm32_pwmtimer_s *priv, FAR const char *msg)
else
#endif
{
- pwmvdbg(" DCR: %04x DMAR: %04x\n",
+ pwminfo(" DCR: %04x DMAR: %04x\n",
pwm_getreg(priv, STM32_GTIM_DCR_OFFSET),
pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET));
}
@@ -396,11 +377,11 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
DEBUGASSERT(priv != NULL && info != NULL);
#ifdef CONFIG_PWM_PULSECOUNT
- pwmvdbg("TIMER%d channel: %d frequency: %d duty: %08x count: %d\n",
+ pwminfo("TIMER%d channel: %d frequency: %d duty: %08x count: %d\n",
priv->timid, priv->channel, info->frequency,
info->duty, info->count);
#else
- pwmvdbg("TIMER%d channel: %d frequency: %d duty: %08x\n",
+ pwminfo("TIMER%d channel: %d frequency: %d duty: %08x\n",
priv->timid, priv->channel, info->frequency, info->duty);
#endif
DEBUGASSERT(info->frequency > 0 && info->duty >= 0 &&
@@ -414,7 +395,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
if (efm32_timer_set_freq(priv->base, priv->pclk, info->frequency) < 0)
{
- pwmdbg("Cannot set TIMER frequency %dHz from clock %dHz\n",
+ pwmerr("ERROR: Cannot set TIMER frequency %dHz from clock %dHz\n",
info->frequency, priv->pclk);
return -EINVAL;
}
@@ -541,8 +522,8 @@ static int pwm_interrupt(struct efm32_pwmtimer_s *priv)
/* Now all of the time critical stuff is done so we can do some debug output */
- pwmllvdbg("Update interrupt SR: %04x prev: %d curr: %d count: %d\n",
- regval, priv->prev, priv->curr, priv->count);
+ pwminfo("Update interrupt SR: %04x prev: %d curr: %d count: %d\n",
+ regval, priv->prev, priv->curr, priv->count);
return OK;
#else
@@ -669,7 +650,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
{
FAR struct efm32_pwmtimer_s *priv = (FAR struct efm32_pwmtimer_s *)dev;
- pwmvdbg("TIMER%d pincfg: %08x\n", priv->timid, priv->pincfg);
+ pwminfo("TIMER%d pincfg: %08x\n", priv->timid, priv->pincfg);
pwm_dumpregs(priv, "Initially");
/* Configure the PWM output pin, but do not start the timer yet */
@@ -726,7 +707,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
FAR struct efm32_pwmtimer_s *priv = (FAR struct efm32_pwmtimer_s *)dev;
uint32_t pincfg;
- pwmvdbg("TIMER%d pincfg: %08x\n", priv->timid, priv->pincfg);
+ pwminfo("TIMER%d pincfg: %08x\n", priv->timid, priv->pincfg);
/* Make sure that the output has been stopped */
@@ -805,7 +786,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
FAR struct efm32_pwmtimer_s *priv = (FAR struct efm32_pwmtimer_s *)dev;
irqstate_t flags;
- pwmvdbg("TIMER%d\n", priv->timid);
+ pwminfo("TIMER%d\n", priv->timid);
/* Disable interrupts momentary to stop any ongoing timer processing and
* to prevent any concurrent access to the reset register.
@@ -843,12 +824,12 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg)
{
-#ifdef CONFIG_DEBUG_PWM
+#ifdef CONFIG_DEBUG_PWM_INFO
FAR struct efm32_pwmtimer_s *priv = (FAR struct efm32_pwmtimer_s *)dev;
/* There are no platform-specific ioctl commands */
- pwmvdbg("TIMER%d\n", priv->timid);
+ pwminfo("TIMER%d\n", priv->timid);
#endif
return -ENOTTY;
}
@@ -878,7 +859,7 @@ FAR struct pwm_lowerhalf_s *efm32_pwminitialize(int timer)
{
FAR struct efm32_pwmtimer_s *lower;
- pwmvdbg("TIMER%d\n", timer);
+ pwminfo("TIMER%d\n", timer);
switch (timer)
{
@@ -933,7 +914,7 @@ FAR struct pwm_lowerhalf_s *efm32_pwminitialize(int timer)
#endif
default:
- pwmdbg("No such timer configured\n");
+ pwmerr("ERROR: No such timer configured\n");
return NULL;
}
diff --git a/arch/arm/src/efm32/efm32_rmu.c b/arch/arm/src/efm32/efm32_rmu.c
index 6b77564b24d73e5ff3805a804e75bf11bb06edbd..57d7b0e02b76d82a03a67010b6d0da4a6f98163b 100644
--- a/arch/arm/src/efm32/efm32_rmu.c
+++ b/arch/arm/src/efm32/efm32_rmu.c
@@ -63,7 +63,7 @@
* Private Types
************************************************************************************/
-#ifdef CONFIG_EFM32_RMU_DEBUG
+#if defined(CONFIG_EFM32_RMU_DEBUG) && defined(CONFIG_DEBUG_WARN)
typedef struct
{
const uint32_t val;
@@ -76,7 +76,7 @@ typedef struct
* Private Data
************************************************************************************/
-#ifdef CONFIG_EFM32_RMU_DEBUG
+#if defined(CONFIG_EFM32_RMU_DEBUG) && defined(CONFIG_DEBUG_WARN)
static efm32_reset_cause_list_t efm32_reset_cause_list[] =
{
{
@@ -191,7 +191,7 @@ uint32_t g_efm32_rstcause;
*
************************************************************************************/
-#ifdef CONFIG_EFM32_RMU_DEBUG
+#if defined(CONFIG_EFM32_RMU_DEBUG) && defined(CONFIG_DEBUG_WARN)
const char *efm32_reset_cause_list_str(uint32_t reg, unsigned int *idx)
{
int len = sizeof(efm32_reset_cause_list)/sizeof(efm32_reset_cause_list[0]);
@@ -261,8 +261,8 @@ void efm32_rmu_initialize(void)
putreg32(EMU_LOCK_LOCKKEY_LOCK, EMU_LOCK_LOCKKEY_LOCK);
}
-#ifdef CONFIG_EFM32_RMU_DEBUG
- rmudbg("RMU => reg = 0x%08X\n", g_efm32_rstcause);
+#if defined(CONFIG_EFM32_RMU_DEBUG) && defined(CONFIG_DEBUG_WARN)
+ rmuwarn("RMU => reg = 0x%08X\n", g_efm32_rstcause);
for (; ; )
{
const char *str;
@@ -273,7 +273,7 @@ void efm32_rmu_initialize(void)
break;
}
- rmudbg("RMU => %s\n", str);
+ rmuwarn("RMU => %s\n", str);
}
#endif
}
diff --git a/arch/arm/src/efm32/efm32_rmu.h b/arch/arm/src/efm32/efm32_rmu.h
index 0aae6fbb0d97b34543af55153e1831a3a72ea1c4..1bcfec2d33f0952fbd1bc9753dcc1aec951dcda1 100644
--- a/arch/arm/src/efm32/efm32_rmu.h
+++ b/arch/arm/src/efm32/efm32_rmu.h
@@ -50,21 +50,18 @@
****************************************************************************/
/* Configuration ************************************************************/
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
+#ifndef CONFIG_DEBUG_ERROR
# undef CONFIG_EFM32_RMU_DEBUG
#endif
#ifdef CONFIG_EFM32_RMU_DEBUG
-# define rmudbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define rmuvdbg lldbg
-# else
-# define rmuvdbg(x...)
-# endif
+# define rmuerr _err
+# define rmuwarn _warn
+# define rmuinfo _info
#else
-# define rmudbg(x...)
-# define rmuvdbg(x...)
+# define rmuerr(x...)
+# define rmuwarn(x...)
+# define rmuinfo(x...)
#endif
/****************************************************************************
diff --git a/arch/arm/src/efm32/efm32_rtc_burtc.c b/arch/arm/src/efm32/efm32_rtc_burtc.c
index 914ebd03ff3b226f7ac48575f32d17596dcdbb71..52c8811ae50b1dd0ac3a07015339380e4d1a8f26 100644
--- a/arch/arm/src/efm32/efm32_rtc_burtc.c
+++ b/arch/arm/src/efm32/efm32_rtc_burtc.c
@@ -130,16 +130,6 @@
#define __CNT_CARRY_REG EFM32_BURTC_RET_REG(0)
#define __CNT_ZERO_REG EFM32_BURTC_RET_REG(1)
-#if defined CONFIG_DEBUG && defined CONFIG_RTC_DEBUG
-# define burtcdbg lldbg
-#else
-# define burtcdbg(x...)
-#endif
-
-/************************************************************************************
- * Private Types
- ************************************************************************************/
-
/************************************************************************************
* Private Data
************************************************************************************/
@@ -191,7 +181,7 @@ static int efm32_rtc_burtc_interrupt(int irq, void *context)
if (source & BURTC_IF_LFXOFAIL)
{
- burtcdbg("BURTC_IF_LFXOFAIL");
+ rtcerr("ERROR: BURTC_IF_LFXOFAIL");
}
#ifdef CONFIG_RTC_HIRES
@@ -245,7 +235,7 @@ static void efm32_rtc_burtc_init(void)
regval = g_efm32_rstcause;
regval2 = getreg32(EFM32_BURTC_CTRL);
- burtcdbg("BURTC RESETCAUSE=0x%08X BURTC_CTRL=0x%08X\n", regval, regval2);
+ rtcinfo("BURTC RESETCAUSE=0x%08X BURTC_CTRL=0x%08X\n", regval, regval2);
if (!(regval2 & BURTC_CTRL_RSTEN) &&
!(regval & RMU_RSTCAUSE_BUBODREG) &&
@@ -262,11 +252,11 @@ static void efm32_rtc_burtc_init(void)
/* restore saved base time */
- burtcdbg("BURTC OK\n");
+ rtcinfo("BURTC OK\n");
return;
}
- burtcdbg("BURTC RESETED\n");
+ rtcinfo("BURTC RESET\n");
/* Disable reset of BackupDomain */
@@ -358,7 +348,7 @@ static uint64_t efm32_get_burtc_tick(void)
val = (uint64_t)cnt_carry*__CNT_TOP + cnt + cnt_zero;
- burtcdbg("Get Tick carry %u zero %u reg %u\n", cnt_carry, cnt_carry,cnt);
+ rtcinfo("Get Tick carry %u zero %u reg %u\n", cnt_carry, cnt_carry,cnt);
return val;
}
@@ -449,7 +439,7 @@ int up_rtc_gettime(FAR struct timespec *tp)
tp->tv_sec = val / CONFIG_RTC_FREQUENCY;
tp->tv_nsec = (val % CONFIG_RTC_FREQUENCY)*(NSEC_PER_SEC/CONFIG_RTC_FREQUENCY);
- burtcdbg("Get RTC %u.%09u\n", tp->tv_sec, tp->tv_nsec);
+ rtcinfo("Get RTC %u.%09u\n", tp->tv_sec, tp->tv_nsec);
return OK;
}
@@ -499,7 +489,7 @@ int up_rtc_settime(FAR const struct timespec *tp)
cnt_carry = val / __CNT_TOP;
cnt = val % __CNT_TOP;
- burtcdbg("Set RTC %u.%09u carry %u zero %u reg %u\n",
+ rtcinfo("Set RTC %u.%09u carry %u zero %u reg %u\n",
tp->tv_sec, tp->tv_nsec, cnt_carry, cnt, cnt_reg);
putreg32(cnt_carry, __CNT_CARRY_REG);
diff --git a/arch/arm/src/efm32/efm32_serial.c b/arch/arm/src/efm32/efm32_serial.c
index fed33adcba28fc10f17177ba5fb58b8ecd775f47..52848fcd03d67af9589a519370860a9f4ed18dda 100644
--- a/arch/arm/src/efm32/efm32_serial.c
+++ b/arch/arm/src/efm32/efm32_serial.c
@@ -205,7 +205,7 @@
#define EFM32_TXERR_INTS (USART_IEN_TXOF)
#define EFM32_RXERR_INTS (USART_IEN_RXOF | USART_IEN_RXUF | \
USART_IEN_PERR | USART_IEN_FERR)
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
# define EFM32_TX_INTS (USART_IEN_TXBL | EFM32_TXERR_INTS)
# define EFM32_RX_INTS (USART_IEN_RXDATAV | EFM32_RXERR_INTS)
#else
@@ -768,7 +768,7 @@ static int efm32_rxinterrupt(struct uart_dev_s *dev)
uart_recvchars(dev);
}
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
/* Check for receive errors */
if ((intflags & EFM32_RXERR_INTS) != 0)
@@ -780,7 +780,7 @@ static int efm32_rxinterrupt(struct uart_dev_s *dev)
* FERR - Framing Error Interrupt Enable
*/
- lldbg("RX ERROR: %08x\n", intflags);
+ _err("RX ERROR: %08x\n", intflags);
}
#endif
@@ -856,14 +856,14 @@ static int efm32_txinterrupt(struct uart_dev_s *dev)
uart_xmitchars(dev);
}
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
/* Check for transmit errors */
if ((intflags & EFM32_TXERR_INTS) != 0)
{
/* TXOF - TX Overflow Interrupt Enable */
- lldbg("RX ERROR: %08x\n", intflags);
+ _err("RX ERROR: %08x\n", intflags);
}
#endif
diff --git a/arch/arm/src/efm32/efm32_spi.c b/arch/arm/src/efm32/efm32_spi.c
index 05c0ab7c5197bf77625fd22f03f0889d8f70c4c2..c4dbb3b282d9cf926688eae0b9d0a30e8946095b 100644
--- a/arch/arm/src/efm32/efm32_spi.c
+++ b/arch/arm/src/efm32/efm32_spi.c
@@ -91,26 +91,6 @@
#define SPI_DMA16_CONFIG (EFM32_DMA_XFERSIZE_HWORD | EFM32_DMA_MEMINCR)
#define SPI_DMA16NULL_CONFIG (EFM32_DMA_XFERSIZE_HWORD | EFM32_DMA_NOINCR)
-/* Debug ********************************************************************/
-/* Check if SPI debug is enabled */
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# undef CONFIG_DEBUG_SPI
-#endif
-
-#ifdef CONFIG_DEBUG_SPI
-# define spidbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define spivdbg lldbg
-# else
-# define spivdbg(x...)
-# endif
-#else
-# define spidbg(x...)
-# define spivdbg(x...)
-#endif
-
/****************************************************************************
* Private Types
****************************************************************************/
@@ -897,7 +877,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
*/
actual = (BOARD_HFPERCLK_FREQUENCY << 7) / (256 + clkdiv);
- spivdbg("frequency=%u actual=%u\n", frequency, actual);
+ spiinfo("frequency=%u actual=%u\n", frequency, actual);
/* Save the frequency selection so that subsequent reconfigurations
* will be faster.
@@ -932,7 +912,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
uint32_t setting;
uint32_t regval;
- spivdbg("mode=%d\n", mode);
+ spiinfo("mode=%d\n", mode);
DEBUGASSERT(priv && priv->config);
config = priv->config;
@@ -998,7 +978,7 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
uint32_t setting;
bool lsbfirst;
- spivdbg("nbits=%d\n", nbits);
+ spiinfo("nbits=%d\n", nbits);
DEBUGASSERT(priv && priv->config);
config = priv->config;
@@ -1222,7 +1202,7 @@ static uint16_t spi_send(struct spi_dev_s *dev, uint16_t wd)
spi_wait_status(config, _USART_STATUS_RXDATAV_MASK, USART_STATUS_RXDATAV);
ret = (uint16_t)spi_getreg(config, EFM32_USART_RXDATA_OFFSET);
- spivdbg("Sent: %04x Return: %04x \n", wd, ret);
+ spiinfo("Sent: %04x Return: %04x \n", wd, ret);
return ret;
}
@@ -1263,7 +1243,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
DEBUGASSERT(priv && priv->config);
config = priv->config;
- spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
+ spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
/* Flush any unread data */
@@ -1427,7 +1407,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
else
#endif
{
- spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n",
+ spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n",
txbuffer, rxbuffer, nwords);
/* Pre-calculate the timeout value */
@@ -1456,7 +1436,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
ret = wd_start(priv->wdog, (int)ticks, spi_dma_timeout, 1, (uint32_t)priv);
if (ret < 0)
{
- spidbg("ERROR: Failed to start timeout\n");
+ spierr("ERROR: Failed to start timeout\n");
}
/* Then wait for each to complete. TX should complete first */
@@ -1492,7 +1472,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
static void spi_sndblock(struct spi_dev_s *dev, const void *txbuffer,
size_t nwords)
{
- spivdbg("txbuffer=%p nwords=%d\n", txbuffer, nwords);
+ spiinfo("txbuffer=%p nwords=%d\n", txbuffer, nwords);
return spi_exchange(dev, txbuffer, NULL, nwords);
}
#endif
@@ -1521,7 +1501,7 @@ static void spi_sndblock(struct spi_dev_s *dev, const void *txbuffer,
static void spi_recvblock(struct spi_dev_s *dev, void *rxbuffer,
size_t nwords)
{
- spivdbg("rxbuffer=%p nwords=%d\n", rxbuffer, nwords);
+ spiinfo("rxbuffer=%p nwords=%d\n", rxbuffer, nwords);
return spi_exchange(dev, NULL, rxbuffer, nwords);
}
#endif
@@ -1594,7 +1574,7 @@ static int spi_portinitialize(struct efm32_spidev_s *priv)
priv->rxdmach = efm32_dmachannel();
if (!priv->rxdmach)
{
- spidbg("ERROR: Failed to allocate the RX DMA channel for SPI port: %d\n",
+ spierr("ERROR: Failed to allocate the RX DMA channel for SPI port: %d\n",
port);
goto errout;
}
@@ -1602,7 +1582,7 @@ static int spi_portinitialize(struct efm32_spidev_s *priv)
priv->txdmach = efm32_dmachannel();
if (!priv->txdmach)
{
- spidbg("ERROR: Failed to allocate the TX DMA channel for SPI port: %d\n",
+ spierr("ERROR: Failed to allocate the TX DMA channel for SPI port: %d\n",
port);
goto errout_with_rxdmach;
}
@@ -1612,7 +1592,7 @@ static int spi_portinitialize(struct efm32_spidev_s *priv)
priv->wdog = wd_create();
if (!priv->wdog)
{
- spidbg("ERROR: Failed to create a timer for SPI port: %d\n", port);
+ spierr("ERROR: Failed to create a timer for SPI port: %d\n", port);
goto errout_with_txdmach;
}
@@ -1709,7 +1689,7 @@ struct spi_dev_s *efm32_spibus_initialize(int port)
else
#endif
{
- spidbg("ERROR: Unsupported SPI port: %d\n", port);
+ spierr("ERROR: Unsupported SPI port: %d\n", port);
return NULL;
}
@@ -1731,7 +1711,7 @@ struct spi_dev_s *efm32_spibus_initialize(int port)
ret = spi_portinitialize(priv);
if (ret < 0)
{
- spidbg("ERROR: Failed to initialize SPI port %d\n", port);
+ spierr("ERROR: Failed to initialize SPI port %d\n", port);
leave_critical_section(flags);
return NULL;
}
diff --git a/arch/arm/src/efm32/efm32_start.c b/arch/arm/src/efm32/efm32_start.c
index ec0171f2307b17cc93b29c239364aedf98435788..f62e1461d51e9476adf440eae9634365b4e9e90c 100644
--- a/arch/arm/src/efm32/efm32_start.c
+++ b/arch/arm/src/efm32/efm32_start.c
@@ -85,7 +85,7 @@ static void go_os_start(void *pv, unsigned int nbytes)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
# if defined(CONFIG_ARMV7M_ITMSYSLOG)
# define showprogress(c) (void)syslog_putc(c)
# elif defined(HAVE_UART_CONSOLE) || defined(HAVE_LEUART_CONSOLE)
diff --git a/arch/arm/src/efm32/efm32_timer.c b/arch/arm/src/efm32/efm32_timer.c
index 19c50b56c20e7dd9de87526934eaf1344ded0de2..6264c3a378243369f4b713c9dae04b20982c787a 100644
--- a/arch/arm/src/efm32/efm32_timer.c
+++ b/arch/arm/src/efm32/efm32_timer.c
@@ -55,50 +55,18 @@
#include "efm32_config.h"
#include "efm32_gpio.h"
-
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing TIMER */
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_TIMER
-#endif
-#ifdef CONFIG_DEBUG_TIMER
-# define efm32_timerdbg dbg
-# define efm32_timerlldbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define efm32_timervdbg vdbg
-# define efm32_timerllvdbg llvdbg
-# define efm32_timer_dumpgpio(p,m) efm32_dumpgpio(p,m)
-# else
-# define efm32_timerlldbg(x...)
-# define efm32_timerllvdbg(x...)
-# define efm32_timer_dumpgpio(p,m)
-# endif
+#ifdef CONFIG_DEBUG_TIMER_INFO
+# define efm32_timer_dumpgpio(p,m) efm32_dumpgpio(p,m)
#else
-# define efm32_timerdbg(x...)
-# define efm32_timerlldbg(x...)
-# define efm32_timervdbg(x...)
-# define efm32_timerllvdbg(x...)
# define efm32_timer_dumpgpio(p,m)
#endif
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Static Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -119,48 +87,43 @@
void efm32_timer_dumpregs(uintptr_t base, FAR const char *msg)
{
+#ifdef CONFIG_DEBUG_TIMER_INFO
int i;
- efm32_timervdbg("%s:\n", msg);
- efm32_timervdbg(" CTRL: %04x STATUS: %04x IEN: %04x IF: %04x\n",
- getreg32(base + EFM32_TIMER_CTRL_OFFSET ),
- getreg32(base + EFM32_TIMER_STATUS_OFFSET ),
- getreg32(base + EFM32_TIMER_IEN_OFFSET ),
- getreg32(base + EFM32_TIMER_IF_OFFSET )
- );
- efm32_timervdbg(" TOP: %04x TOPB: %04x CNT: %04x ROUTE: %04x\n",
- getreg32(base + EFM32_TIMER_TOP_OFFSET ),
- getreg32(base + EFM32_TIMER_TOPB_OFFSET ),
- getreg32(base + EFM32_TIMER_CNT_OFFSET ),
- getreg32(base + EFM32_TIMER_ROUTE_OFFSET )
- );
+ tmrinfo("%s:\n", msg);
+ tmrinfo(" CTRL: %04x STATUS: %04x IEN: %04x IF: %04x\n",
+ getreg32(base + EFM32_TIMER_CTRL_OFFSET ),
+ getreg32(base + EFM32_TIMER_STATUS_OFFSET ),
+ getreg32(base + EFM32_TIMER_IEN_OFFSET ),
+ getreg32(base + EFM32_TIMER_IF_OFFSET ));
+ tmrinfo(" TOP: %04x TOPB: %04x CNT: %04x ROUTE: %04x\n",
+ getreg32(base + EFM32_TIMER_TOP_OFFSET ),
+ getreg32(base + EFM32_TIMER_TOPB_OFFSET ),
+ getreg32(base + EFM32_TIMER_CNT_OFFSET ),
+ getreg32(base + EFM32_TIMER_ROUTE_OFFSET ));
for (i = 0; i < EFM32_TIMER_NCC; i++)
{
-#if defined(CONFIG_DEBUG_TIMER) && defined(CONFIG_DEBUG_VERBOSE)
uintptr_t base_cc = base + EFM32_TIMER_CC_OFFSET(i);
-#endif
- efm32_timervdbg("CC%d => CTRL: %04x CCV: %04x CCVP: %04x CCVB: %04x\n",
- i
- getreg32(base_cc + EFM32_TIMER_CC_CTRL_OFFSET ),
- getreg32(base_cc + EFM32_TIMER_CC_CCV_OFFSET ),
- getreg32(base_cc + EFM32_TIMER_CC_CCVP_OFFSET ),
- getreg32(base_cc + EFM32_TIMER_CC_CCVB_OFFSET )
- );
+
+ tmrinfo("CC%d => CTRL: %04x CCV: %04x CCVP: %04x CCVB: %04x\n",
+ i
+ getreg32(base_cc + EFM32_TIMER_CC_CTRL_OFFSET ),
+ getreg32(base_cc + EFM32_TIMER_CC_CCV_OFFSET ),
+ getreg32(base_cc + EFM32_TIMER_CC_CCVP_OFFSET ),
+ getreg32(base_cc + EFM32_TIMER_CC_CCVB_OFFSET ));
}
- efm32_timervdbg("DTCTRL: %04x DTTIME: %04x DTFC: %04x DTOGEN: %04x\n",
- getreg32(base + EFM32_TIMER_CTRL_OFFSET ),
- getreg32(base + EFM32_TIMER_STATUS_OFFSET ),
- getreg32(base + EFM32_TIMER_IEN_OFFSET ),
- getreg32(base + EFM32_TIMER_IF_OFFSET )
- );
- efm32_timervdbg("DTFAULT: %04x DTFAULTC: %04x DTLOCK: %04x \n",
- getreg32(base + EFM32_TIMER_CTRL_OFFSET ),
- getreg32(base + EFM32_TIMER_STATUS_OFFSET ),
- getreg32(base + EFM32_TIMER_IEN_OFFSET ),
- getreg32(base + EFM32_TIMER_IF_OFFSET )
- );
+ tmrinfo("DTCTRL: %04x DTTIME: %04x DTFC: %04x DTOGEN: %04x\n",
+ getreg32(base + EFM32_TIMER_CTRL_OFFSET ),
+ getreg32(base + EFM32_TIMER_STATUS_OFFSET ),
+ getreg32(base + EFM32_TIMER_IEN_OFFSET ),
+ getreg32(base + EFM32_TIMER_IF_OFFSET ));
+ tmrinfo("DTFAULT: %04x DTFAULTC: %04x DTLOCK: %04x \n",
+ getreg32(base + EFM32_TIMER_CTRL_OFFSET ),
+ getreg32(base + EFM32_TIMER_STATUS_OFFSET ),
+ getreg32(base + EFM32_TIMER_IEN_OFFSET ),
+#endif
}
/****************************************************************************
@@ -238,6 +201,7 @@ void efm32_timer_reset(uintptr_t base)
* prescaler setted, -1 in case of error.
*
****************************************************************************/
+
int efm32_timer_set_freq(uintptr_t base, uint32_t clk_freq, uint32_t freq)
{
int prescaler = 0;
@@ -262,8 +226,7 @@ int efm32_timer_set_freq(uintptr_t base, uint32_t clk_freq, uint32_t freq)
reload = (clk_freq / prescaler / freq);
- efm32_timerdbg("Source: %4xHz Div: %4x Reload: %4x \n",
- clk_freq, prescaler, reload);
+ tmrinfo("Source: %4xHz Div: %4x Reload: %4x \n", clk_freq, prescaler, reload);
putreg32(reload, base + EFM32_TIMER_TOP_OFFSET);
diff --git a/arch/arm/src/efm32/efm32_usbdev.c b/arch/arm/src/efm32/efm32_usbdev.c
index fb20993657f4f926aa58d0d9f1cc6ee91a4dcd18..26753dd3ff4d64965a3cf95552148658e8c10c83 100644
--- a/arch/arm/src/efm32/efm32_usbdev.c
+++ b/arch/arm/src/efm32/efm32_usbdev.c
@@ -114,6 +114,10 @@
# error "FIFO allocations exceed FIFO memory size"
#endif
+#ifndef CONFIG_DEBUG_USB_INFO
+# undef CONFIG_EFM32_USBDEV_REGDEBUG
+#endif
+
/* The actual FIFO addresses that we use must be aligned to 4-byte boundaries;
* FIFO sizes must be provided in units of 32-bit words.
*/
@@ -474,7 +478,7 @@ struct efm32_usbdev_s
/* Register operations ********************************************************/
-#if defined(CONFIG_EFM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_EFM32_USBDEV_REGDEBUG
static uint32_t efm32_getreg(uint32_t addr);
static void efm32_putreg(uint32_t val, uint32_t addr);
#else
@@ -794,7 +798,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] =
*
****************************************************************************/
-#if defined(CONFIG_EFM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_EFM32_USBDEV_REGDEBUG
static uint32_t efm32_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@@ -815,7 +819,7 @@ static uint32_t efm32_getreg(uint32_t addr)
{
if (count == 4)
{
- lldbg("...\n");
+ uinfo("...\n");
}
return val;
@@ -832,7 +836,7 @@ static uint32_t efm32_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -844,7 +848,7 @@ static uint32_t efm32_getreg(uint32_t addr)
/* Show the register value read */
- lldbg("%08x->%08x\n", addr, val);
+ uinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@@ -857,12 +861,12 @@ static uint32_t efm32_getreg(uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_EFM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_EFM32_USBDEV_REGDEBUG
static void efm32_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- lldbg("%08x<-%08x\n", addr, val);
+ uinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@@ -1220,9 +1224,9 @@ static void efm32_epin_request(FAR struct efm32_usbdev_s *priv,
return;
}
- ullvdbg("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
- privep->epphy, privreq, privreq->req.len,
- privreq->req.xfrd, privep->zlp);
+ uinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
+ privep->epphy, privreq, privreq->req.len,
+ privreq->req.xfrd, privep->zlp);
/* Check for a special case: If we are just starting a request (xfrd==0) and
* the class driver is trying to send a zero-length packet (len==0). Then set
@@ -1486,8 +1490,8 @@ static void efm32_epout_complete(FAR struct efm32_usbdev_s *priv,
return;
}
- ullvdbg("EP%d: len=%d xfrd=%d\n",
- privep->epphy, privreq->req.len, privreq->req.xfrd);
+ uinfo("EP%d: len=%d xfrd=%d\n",
+ privep->epphy, privreq->req.len, privreq->req.xfrd);
/* Return the completed read request to the class driver and mark the state
* IDLE.
@@ -1521,7 +1525,7 @@ static inline void efm32_ep0out_receive(FAR struct efm32_ep_s *privep, int bcnt)
DEBUGASSERT(privep && privep->ep.priv);
priv = (FAR struct efm32_usbdev_s *)privep->ep.priv;
- ullvdbg("EP0: bcnt=%d\n", bcnt);
+ uinfo("EP0: bcnt=%d\n", bcnt);
usbtrace(TRACE_READ(EP0), bcnt);
/* Verify that an OUT SETUP request as received before this data was
@@ -1614,7 +1618,8 @@ static inline void efm32_epout_receive(FAR struct efm32_ep_s *privep, int bcnt)
return;
}
- ullvdbg("EP%d: len=%d xfrd=%d\n", privep->epphy, privreq->req.len, privreq->req.xfrd);
+ uinfo("EP%d: len=%d xfrd=%d\n",
+ privep->epphy, privreq->req.len, privreq->req.xfrd);
usbtrace(TRACE_READ(privep->epphy), bcnt);
/* Get the number of bytes to transfer from the RxFIFO */
@@ -1698,7 +1703,7 @@ static void efm32_epout_request(FAR struct efm32_usbdev_s *priv,
return;
}
- ullvdbg("EP%d: len=%d\n", privep->epphy, privreq->req.len);
+ uinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len);
/* Ignore any attempt to receive a zero length packet (this really
* should not happen.
@@ -2494,8 +2499,8 @@ static inline void efm32_ep0out_setup(struct efm32_usbdev_s *priv)
ctrlreq.index = GETUINT16(priv->ctrlreq.index);
ctrlreq.len = GETUINT16(priv->ctrlreq.len);
- ullvdbg("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len);
+ uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len);
/* Check for a standard request */
@@ -2629,7 +2634,7 @@ static inline void efm32_epout_interrupt(FAR struct efm32_usbdev_s *priv)
if ((daint & 1) != 0)
{
regval = efm32_getreg(EFM32_USB_DOEPINT(epno));
- ulldbg("DOEPINT(%d) = %08x\n", epno, regval);
+ uinfo("DOEPINT(%d) = %08x\n", epno, regval);
efm32_putreg(0xFF, EFM32_USB_DOEPINT(epno));
}
@@ -2859,8 +2864,8 @@ static inline void efm32_epin_interrupt(FAR struct efm32_usbdev_s *priv)
{
if ((daint & 1) != 0)
{
- ulldbg("DIEPINT(%d) = %08x\n",
- epno, efm32_getreg(EFM32_USB_DIEPINT(epno)));
+ uinfo("DIEPINT(%d) = %08x\n",
+ epno, efm32_getreg(EFM32_USB_DIEPINT(epno)));
efm32_putreg(0xFF, EFM32_USB_DIEPINT(epno));
}
@@ -3799,7 +3804,7 @@ static int efm32_epout_configure(FAR struct efm32_ep_s *privep, uint8_t eptype,
break;
default:
- udbg("Unsupported maxpacket: %d\n", maxpacket);
+ uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket);
return -EINVAL;
}
}
@@ -3894,7 +3899,7 @@ static int efm32_epin_configure(FAR struct efm32_ep_s *privep, uint8_t eptype,
break;
default:
- udbg("Unsupported maxpacket: %d\n", maxpacket);
+ uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket);
return -EINVAL;
}
}
@@ -4184,7 +4189,7 @@ static int efm32_ep_disable(FAR struct usbdev_ep_s *ep)
{
FAR struct efm32_ep_s *privep = (FAR struct efm32_ep_s *)ep;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep)
{
usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_INVALIDPARMS), 0);
@@ -4224,7 +4229,7 @@ static FAR struct usbdev_req_s *efm32_ep_allocreq(FAR struct usbdev_ep_s *ep)
{
FAR struct efm32_req_s *privreq;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep)
{
usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_INVALIDPARMS), 0);
@@ -4257,7 +4262,7 @@ static void efm32_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s
{
FAR struct efm32_req_s *privreq = (FAR struct efm32_req_s *)req;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_INVALIDPARMS), 0);
@@ -4329,11 +4334,12 @@ static int efm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
/* Some sanity checking */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_INVALIDPARMS), 0);
- ullvdbg("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+ uinfo("req=%p callback=%p buf=%p ep=%p\n",
+ req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
@@ -4341,7 +4347,7 @@ static int efm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
usbtrace(TRACE_EPSUBMIT, privep->epphy);
priv = privep->dev;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!priv->driver)
{
usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
@@ -4418,7 +4424,7 @@ static int efm32_ep_cancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
FAR struct efm32_ep_s *privep = (FAR struct efm32_ep_s *)ep;
irqstate_t flags;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_INVALIDPARMS), 0);
@@ -4876,7 +4882,7 @@ static int efm32_selfpowered(struct usbdev_s *dev, bool selfpowered)
usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!dev)
{
usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_INVALIDPARMS), 0);
@@ -5482,7 +5488,7 @@ void up_usbinitialize(void)
ret = irq_attach(EFM32_IRQ_USB, efm32_usbinterrupt);
if (ret < 0)
{
- udbg("irq_attach failed\n", ret);
+ uerr("ERROR: irq_attach failed\n", ret);
goto errout;
}
@@ -5605,7 +5611,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
usbtrace(TRACE_DEVREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!driver || !driver->ops->bind || !driver->ops->unbind ||
!driver->ops->disconnect || !driver->ops->setup)
{
@@ -5676,7 +5682,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
usbtrace(TRACE_DEVUNREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (driver != priv->driver)
{
usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_INVALIDPARMS), 0);
diff --git a/arch/arm/src/efm32/efm32_usbhost.c b/arch/arm/src/efm32/efm32_usbhost.c
index cc9fe1c7d8d0a3037c98b0b74bfa2e488578ab1b..19f80bc43d4322b130e47cf29eb866d7dd65f0fc 100644
--- a/arch/arm/src/efm32/efm32_usbhost.c
+++ b/arch/arm/src/efm32/efm32_usbhost.c
@@ -92,9 +92,9 @@
* CONFIG_EFM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever
* want to do that?
* CONFIG_EFM32_USBHOST_REGDEBUG - Enable very low-level register access
- * debug. Depends on CONFIG_DEBUG.
+ * debug. Depends on CONFIG_DEBUG_FEATURES.
* CONFIG_EFM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB
- * packets. Depends on CONFIG_DEBUG.
+ * packets. Depends on CONFIG_DEBUG_FEATURES.
*/
/* Default RxFIFO size */
@@ -121,9 +121,9 @@
# define CONFIG_EFM32_OTGFS_DESCSIZE 128
#endif
-/* Register/packet debug depends on CONFIG_DEBUG */
+/* Register/packet debug depends on CONFIG_DEBUG_FEATURES */
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_USB_INFO
# undef CONFIG_EFM32_USBHOST_REGDEBUG
# undef CONFIG_EFM32_USBHOST_PKTDUMP
#endif
@@ -582,7 +582,7 @@ static const struct efm32_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] =
#ifdef CONFIG_EFM32_USBHOST_REGDEBUG
static void efm32_printreg(uint32_t addr, uint32_t val, bool iswrite)
{
- lldbg("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
+ uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
}
#endif
@@ -632,7 +632,7 @@ static void efm32_checkreg(uint32_t addr, uint32_t val, bool iswrite)
{
/* No.. More than one. */
- lldbg("[repeats %d more times]\n", count);
+ uinfo("[repeats %d more times]\n", count);
}
}
@@ -1362,7 +1362,7 @@ static int efm32_ctrlep_alloc(FAR struct efm32_usbhost_s *priv,
ctrlep = (FAR struct efm32_ctrlinfo_s *)kmm_malloc(sizeof(struct efm32_ctrlinfo_s));
if (ctrlep == NULL)
{
- udbg("ERROR: Failed to allocate control endpoint container\n");
+ uerr("ERROR: Failed to allocate control endpoint container\n");
return -ENOMEM;
}
@@ -1372,7 +1372,7 @@ static int efm32_ctrlep_alloc(FAR struct efm32_usbhost_s *priv,
hport->funcaddr, hport->speed, ctrlep);
if (ret < 0)
{
- udbg("ERROR: efm32_ctrlchan_alloc failed: %d\n", ret);
+ uerr("ERROR: efm32_ctrlchan_alloc failed: %d\n", ret);
kmm_free(ctrlep);
return ret;
}
@@ -1424,7 +1424,7 @@ static int efm32_xfrep_alloc(FAR struct efm32_usbhost_s *priv,
chidx = efm32_chan_alloc(priv);
if (chidx < 0)
{
- udbg("ERROR: Failed to allocate a host channel\n");
+ uerr("ERROR: Failed to allocate a host channel\n");
return -ENOMEM;
}
@@ -1934,7 +1934,7 @@ static ssize_t efm32_in_transfer(FAR struct efm32_usbhost_s *priv, int chidx,
ret = efm32_in_setup(priv, chidx);
if (ret < 0)
{
- udbg("ERROR: efm32_in_setup failed: %d\n", ret);
+ uerr("ERROR: efm32_in_setup failed: %d\n", ret);
return (ssize_t)ret;
}
@@ -1965,7 +1965,7 @@ static ssize_t efm32_in_transfer(FAR struct efm32_usbhost_s *priv, int chidx,
{
/* Break out and return the error */
- udbg("ERROR: efm32_chan_wait failed: %d\n", ret);
+ uerr("ERROR: efm32_chan_wait failed: %d\n", ret);
return (ssize_t)ret;
}
}
@@ -2010,13 +2010,13 @@ static void efm32_in_next(FAR struct efm32_usbhost_s *priv,
return;
}
- udbg("ERROR: efm32_in_setup failed: %d\n", ret);
+ uerr("ERROR: efm32_in_setup failed: %d\n", ret);
result = ret;
}
/* The transfer is complete, with or without an error */
- uvdbg("Transfer complete: %d\n", result);
+ uinfo("Transfer complete: %d\n", result);
/* Extract the callback information */
@@ -2068,7 +2068,7 @@ static int efm32_in_asynch(FAR struct efm32_usbhost_s *priv, int chidx,
ret = efm32_chan_asynchsetup(priv, chan, callback, arg);
if (ret < 0)
{
- udbg("ERROR: efm32_chan_asynchsetup failed: %d\n", ret);
+ uerr("ERROR: efm32_chan_asynchsetup failed: %d\n", ret);
return ret;
}
@@ -2077,7 +2077,7 @@ static int efm32_in_asynch(FAR struct efm32_usbhost_s *priv, int chidx,
ret = efm32_in_setup(priv, chidx);
if (ret < 0)
{
- udbg("ERROR: efm32_in_setup failed: %d\n", ret);
+ uerr("ERROR: efm32_in_setup failed: %d\n", ret);
}
/* And return with the transfer pending */
@@ -2203,7 +2203,7 @@ static ssize_t efm32_out_transfer(FAR struct efm32_usbhost_s *priv, int chidx,
ret = efm32_out_setup(priv, chidx);
if (ret < 0)
{
- udbg("ERROR: efm32_out_setup failed: %d\n", ret);
+ uerr("ERROR: efm32_out_setup failed: %d\n", ret);
return (ssize_t)ret;
}
@@ -2231,7 +2231,7 @@ static ssize_t efm32_out_transfer(FAR struct efm32_usbhost_s *priv, int chidx,
{
/* Break out and return the error */
- udbg("ERROR: efm32_chan_wait failed: %d\n", ret);
+ uerr("ERROR: efm32_chan_wait failed: %d\n", ret);
return (ssize_t)ret;
}
@@ -2296,13 +2296,13 @@ static void efm32_out_next(FAR struct efm32_usbhost_s *priv,
return;
}
- udbg("ERROR: efm32_out_setup failed: %d\n", ret);
+ uerr("ERROR: efm32_out_setup failed: %d\n", ret);
result = ret;
}
/* The transfer is complete, with or without an error */
- uvdbg("Transfer complete: %d\n", result);
+ uinfo("Transfer complete: %d\n", result);
/* Extract the callback information */
@@ -2354,7 +2354,7 @@ static int efm32_out_asynch(FAR struct efm32_usbhost_s *priv, int chidx,
ret = efm32_chan_asynchsetup(priv, chan, callback, arg);
if (ret < 0)
{
- udbg("ERROR: efm32_chan_asynchsetup failed: %d\n", ret);
+ uerr("ERROR: efm32_chan_asynchsetup failed: %d\n", ret);
return ret;
}
@@ -2363,7 +2363,7 @@ static int efm32_out_asynch(FAR struct efm32_usbhost_s *priv, int chidx,
ret = efm32_out_setup(priv, chidx);
if (ret < 0)
{
- udbg("ERROR: efm32_out_setup failed: %d\n", ret);
+ uerr("ERROR: efm32_out_setup failed: %d\n", ret);
}
/* And return with the transfer pending */
@@ -2448,7 +2448,7 @@ static inline void efm32_gint_hcinisr(FAR struct efm32_usbhost_s *priv,
/* AND the two to get the set of enabled, pending HC interrupts */
pending &= regval;
- ullvdbg("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
+ uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
@@ -2709,7 +2709,7 @@ static inline void efm32_gint_hcoutisr(FAR struct efm32_usbhost_s *priv,
/* AND the two to get the set of enabled, pending HC interrupts */
pending &= regval;
- ullvdbg("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
+ uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
@@ -3012,7 +3012,7 @@ static inline void efm32_gint_rxflvlisr(FAR struct efm32_usbhost_s *priv)
/* Read and pop the next status from the Rx FIFO */
grxsts = efm32_getreg(EFM32_USB_GRXSTSP);
- ullvdbg("GRXSTS: %08x\n", grxsts);
+ uinfo("GRXSTS: %08x\n", grxsts);
/* Isolate the channel number/index in the status word */
@@ -3166,8 +3166,8 @@ static inline void efm32_gint_nptxfeisr(FAR struct efm32_usbhost_s *priv)
/* Write the next group of packets into the Tx FIFO */
- ullvdbg("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
- regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
+ uinfo("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
+ regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
efm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize);
}
@@ -3254,8 +3254,8 @@ static inline void efm32_gint_ptxfeisr(FAR struct efm32_usbhost_s *priv)
/* Write the next group of packets into the Tx FIFO */
- ullvdbg("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
- regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
+ uinfo("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
+ regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
efm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize);
}
@@ -3827,7 +3827,7 @@ static int efm32_wait(FAR struct usbhost_connection_s *conn,
*hport = connport;
leave_critical_section(flags);
- uvdbg("RHport Connected: %s\n", connport->connected ? "YES" : "NO");
+ uinfo("RHport Connected: %s\n", connport->connected ? "YES" : "NO");
return OK;
}
@@ -3844,7 +3844,7 @@ static int efm32_wait(FAR struct usbhost_connection_s *conn,
*hport = connport;
leave_critical_section(flags);
- uvdbg("Hub port Connected: %s\n", connport->connected ? "YES" : "NO");
+ uinfo("Hub port Connected: %s\n", connport->connected ? "YES" : "NO");
return OK;
}
#endif
@@ -3932,7 +3932,7 @@ static int efm32_rh_enumerate(FAR struct efm32_usbhost_s *priv,
ret = efm32_ctrlchan_alloc(priv, 0, 0, priv->rhport.hport.speed, &priv->ep0);
if (ret < 0)
{
- udbg("ERROR: Failed to allocate a control endpoint: %d\n", ret);
+ uerr("ERROR: Failed to allocate a control endpoint: %d\n", ret);
}
return ret;
@@ -3964,7 +3964,7 @@ static int efm32_enumerate(FAR struct usbhost_connection_s *conn,
/* Then let the common usbhost_enumerate do the real enumeration. */
- uvdbg("Enumerate the device\n");
+ uinfo("Enumerate the device\n");
priv->smstate = SMSTATE_ENUM;
ret = usbhost_enumerate(hport, &hport->devclass);
@@ -3978,7 +3978,7 @@ static int efm32_enumerate(FAR struct usbhost_connection_s *conn,
{
/* Return to the disconnected state */
- udbg("ERROR: Enumeration failed: %d\n", ret);
+ uerr("ERROR: Enumeration failed: %d\n", ret);
efm32_gint_disconnected(priv);
}
@@ -4380,7 +4380,7 @@ static int efm32_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL);
usbhost_vtrace2(USBHOST_VTRACE2_CTRLIN, req->type, req->req);
- uvdbg("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
+ uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
req->type, req->req, req->value[1], req->value[0],
req->index[1], req->index[0], req->len[1], req->len[0]);
@@ -4465,7 +4465,7 @@ static int efm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL);
usbhost_vtrace2(USBHOST_VTRACE2_CTRLOUT, req->type, req->req);
- uvdbg("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
+ uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
req->type, req->req, req->value[1], req->value[0],
req->index[1], req->index[0], req->len[1], req->len[0]);
@@ -4583,7 +4583,7 @@ static ssize_t efm32_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep
unsigned int chidx = (unsigned int)ep;
ssize_t nbytes;
- uvdbg("chidx: %d buflen: %d\n", (unsigned int)ep, buflen);
+ uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen);
DEBUGASSERT(priv && buffer && chidx < EFM32_MAX_TX_FIFOS && buflen > 0);
@@ -4650,7 +4650,7 @@ static int efm32_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
unsigned int chidx = (unsigned int)ep;
int ret;
- uvdbg("chidx: %d buflen: %d\n", (unsigned int)ep, buflen);
+ uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen);
DEBUGASSERT(priv && buffer && chidx < EFM32_MAX_TX_FIFOS && buflen > 0);
@@ -4700,7 +4700,7 @@ static int efm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
unsigned int chidx = (unsigned int)ep;
irqstate_t flags;
- uvdbg("chidx: %u: %d\n", chidx);
+ uinfo("chidx: %u: %d\n", chidx);
DEBUGASSERT(priv && chidx < EFM32_MAX_TX_FIFOS);
chan = &priv->chan[chidx];
@@ -4795,7 +4795,8 @@ static int efm32_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
- ullvdbg("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+ uinfo("Hub port %d connected: %s\n",
+ hport->port, connected ? "YES" : "NO");
/* Report the connection event */
diff --git a/arch/arm/src/imx1/imx_decodeirq.c b/arch/arm/src/imx1/imx_decodeirq.c
index 5c35e68fab2dbc619aeea11cc6146698c74a09b4..48164d9099c465561c9cb65e30b0b14c140c5404 100644
--- a/arch/arm/src/imx1/imx_decodeirq.c
+++ b/arch/arm/src/imx1/imx_decodeirq.c
@@ -74,8 +74,8 @@
void up_decodeirq(uint32_t *regs)
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
- lowsyslog(LOG_ERR, "Unexpected IRQ\n");
CURRENT_REGS = regs;
+ err("ERROR: Unexpected IRQ\n");
PANIC();
#else
uint32_t regval;
diff --git a/arch/arm/src/imx6/Make.defs b/arch/arm/src/imx6/Make.defs
index 3f949158e360ccc1203c49de51db70ddbac7aea3..4870aa1d1de74e3aa0b92853040c9931c3357ed0 100644
--- a/arch/arm/src/imx6/Make.defs
+++ b/arch/arm/src/imx6/Make.defs
@@ -83,7 +83,7 @@ ifeq ($(CONFIG_SMP),y)
CMN_CSRCS += arm_cpuindex.c arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c
endif
-ifeq ($(CONFIG_DEBUG_IRQ),y)
+ifeq ($(CONFIG_DEBUG_IRQ_INFO),y)
CMN_CSRCS += arm_gicv2_dump.c
endif
@@ -150,3 +150,7 @@ CHIP_CSRCS += imx_serial.c imx_lowputc.c
ifeq ($(CONFIG_SMP),y)
CHIP_CSRCS += imx_cpuboot.c
endif
+
+ifeq ($(CONFIG_IMX6_ECSPI),y)
+CHIP_CSRCS += imx_ecspi.c
+endif
diff --git a/arch/arm/src/imx6/imx_gpio.h b/arch/arm/src/imx6/imx_gpio.h
index 2c3acd9abe28c35dc8baad9849f46c6fc9394e48..23ca29c318714cb886c366ae4b585b3e61684ef5 100644
--- a/arch/arm/src/imx6/imx_gpio.h
+++ b/arch/arm/src/imx6/imx_gpio.h
@@ -288,7 +288,7 @@ void imx_gpioirq_disable(int irq);
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
int imx_dump_gpio(uint32_t pinset, const char *msg);
#else
# define imx_dumpgpio(p,m)
diff --git a/arch/arm/src/imx6/imx_lowputc.c b/arch/arm/src/imx6/imx_lowputc.c
index a6387e732168c2b2bda1cb45c3b4ab04fb0077a0..8bfabf7085641fb359bfd3555ebe96265224df57 100644
--- a/arch/arm/src/imx6/imx_lowputc.c
+++ b/arch/arm/src/imx6/imx_lowputc.c
@@ -584,7 +584,7 @@ int imx_uart_configure(uint32_t base, FAR const struct uart_config_s *config)
*
************************************************************************************/
-#if defined(IMX_HAVE_UART) && defined(CONFIG_DEBUG)
+#if defined(IMX_HAVE_UART) && defined(CONFIG_DEBUG_FEATURES)
void imx_lowputc(int ch)
{
/* Poll the TX fifo trigger level bit of the UART status register. When the TXFE
diff --git a/arch/arm/src/imx6/imx_lowputc.h b/arch/arm/src/imx6/imx_lowputc.h
index d487931dc63362a429f80b953a7255e818a04312..081f366ea7cb6e7ed1265001fedc0ff6800bffdb 100644
--- a/arch/arm/src/imx6/imx_lowputc.h
+++ b/arch/arm/src/imx6/imx_lowputc.h
@@ -105,7 +105,7 @@ int imx_uart_configure(uint32_t base, FAR const struct uart_config_s *config);
*
************************************************************************************/
-#if defined(IMX_HAVE_UART) && defined(CONFIG_DEBUG)
+#if defined(IMX_HAVE_UART) && defined(CONFIG_DEBUG_FEATURES)
void imx_lowputc(int ch);
#else
# define imx_lowputc(ch)
diff --git a/arch/arm/src/kinetis/Kconfig b/arch/arm/src/kinetis/Kconfig
index fdf54e1941c65fe4445f3d303201eba7b1f58ea2..5710c2d32ce6c7e4067fcc53e430f3aa734dde0b 100644
--- a/arch/arm/src/kinetis/Kconfig
+++ b/arch/arm/src/kinetis/Kconfig
@@ -383,6 +383,69 @@ config KINETIS_PIT
endmenu
+config KINETIS_FTM0_PWM
+ bool "FTM0 PWM"
+ default n
+ depends on KINETIS_FTM0
+ ---help---
+ Reserve timer 0 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If KINETIS_FTM0
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+config KINETIS_FTM0_CHANNEL
+ int "FTM0 PWM Output Channel"
+ default 0
+ range 0 7
+ depends on KINETIS_FTM0_PWM
+ ---help---
+ If FTM0 is enabled for PWM usage, you also need specifies the timer output
+ channel {0,..,7}
+
+config KINETIS_FTM1_PWM
+ bool "FTM1 PWM"
+ default n
+ depends on KINETIS_FTM1
+ ---help---
+ Reserve timer 1 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If KINETIS_FTM1
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+config KINETIS_FTM1_CHANNEL
+ int "FTM1 PWM Output Channel"
+ default 0
+ range 0 1
+ depends on KINETIS_FTM1_PWM
+ ---help---
+ If FTM1 is enabled for PWM usage, you also need specifies the timer output
+ channel {0,..,1}
+
+config KINETIS_FTM2_PWM
+ bool "FTM2 PWM"
+ default n
+ depends on KINETIS_FTM2
+ ---help---
+ Reserve timer 2 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If KINETIS_FTM2
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+config KINETIS_FTM2_CHANNEL
+ int "FTM2 PWM Output Channel"
+ default 0
+ range 0 1
+ depends on KINETIS_FTM2_PWM
+ ---help---
+ If FTM2 is enabled for PWM usage, you also need specifies the timer output
+ channel {0,..,1}
+
comment "Kinetis GPIO Interrupt Configuration"
config GPIO_IRQ
diff --git a/arch/arm/src/kinetis/Make.defs b/arch/arm/src/kinetis/Make.defs
index c9c5ec6ca802c979bb4f056e4a6ff9b8e95ff2fd..662dd618737f74b868560d730be62f3c6e6a209a 100644
--- a/arch/arm/src/kinetis/Make.defs
+++ b/arch/arm/src/kinetis/Make.defs
@@ -107,8 +107,8 @@ ifeq ($(CONFIG_GPIO_IRQ),y)
CHIP_CSRCS += kinetis_pinirq.c
endif
-ifeq ($(CONFIG_DEBUG_GPIO),y)
-CHIP_CSRCS += kinetis_pindbg.c
+ifeq ($(CONFIG_DEBUG_GPIO_INFO),y)
+CHIP_CSRCS += kinetis_pindump.c
endif
ifeq ($(CONFIG_KINETIS_SDHC),y)
@@ -127,6 +127,10 @@ ifeq ($(CONFIG_KINETIS_DMA),y)
CHIP_CSRCS += kinetis_dma.c kinetis_pindma.c
endif
+ifeq ($(CONFIG_PWM),y)
+CHIP_CSRCS += kinetis_pwm.c
+endif
+
ifeq ($(CONFIG_NET),y)
ifeq ($(CONFIG_KINETIS_ENET),y)
CHIP_CSRCS += kinetis_enet.c
diff --git a/arch/arm/src/kinetis/kinetis.h b/arch/arm/src/kinetis/kinetis.h
index b0c016d22a1dfea6f7077175d8a2b03f0e8c08e6..ae02ce7e4f81aae52892db227f2874b25d47dd0b 100644
--- a/arch/arm/src/kinetis/kinetis.h
+++ b/arch/arm/src/kinetis/kinetis.h
@@ -566,8 +566,8 @@ void kinetis_pindmadisable(uint32_t pinset);
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_GPIO
-int kinetis_pindump(uint32_t pinset, const char *msg);
+#ifdef CONFIG_DEBUG_GPIO_INFO
+void kinetis_pindump(uint32_t pinset, const char *msg);
#else
# define kinetis_pindump(p,m)
#endif
diff --git a/arch/arm/src/kinetis/kinetis_clockconfig.c b/arch/arm/src/kinetis/kinetis_clockconfig.c
index dc2fe0482bf893b6fda5a199785dfbb3ae184c41..7221b9dc6e76416e6edc83b1ef9b1ddac09e7f34 100644
--- a/arch/arm/src/kinetis/kinetis_clockconfig.c
+++ b/arch/arm/src/kinetis/kinetis_clockconfig.c
@@ -1,8 +1,7 @@
/****************************************************************************
* arch/arm/src/kinetis/kinetis_clockconfig.c
- * arch/arm/src/chip/kinetis_clockconfig.c
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -66,14 +65,6 @@
void __ramfunc__
kinesis_setdividers(uint32_t div1, uint32_t div2, uint32_t div3, uint32_t div4);
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -133,7 +124,11 @@ void kinetis_pllconfig(void)
* RANGE = 2 (Oscillator of 8 MHz to 32 MHz)
*/
+#ifdef BOARD_EXTAL_LP
+ putreg8(MCG_C2_EREFS | MCG_C2_RANGE_VHIGH, KINETIS_MCG_C2);
+#else
putreg8(MCG_C2_EREFS | MCG_C2_HGO | MCG_C2_RANGE_VHIGH, KINETIS_MCG_C2);
+#endif /* BOARD_EXTAL_LP */
#endif
/* Released latched state of oscillator and GPIO */
@@ -156,7 +151,11 @@ void kinetis_pllconfig(void)
* CLKS = 2 (Clock Source Select, External reference clock)
*/
+#ifdef BOARD_FRDIV
+ putreg8(BOARD_FRDIV | MCG_C1_CLKS_EXTREF, KINETIS_MCG_C1);
+#else
putreg8(MCG_C1_FRDIV_DIV256 | MCG_C1_CLKS_EXTREF, KINETIS_MCG_C1);
+#endif
/* If we aren't using an oscillator input we don't need to wait for the
* oscillator to initialize
diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c
index 95e511546ff441ae6d5b9ca11b842b8f7d9bccbb..aa4b3cf10165271bcfb3acb4dd3e1817f8692d4f 100644
--- a/arch/arm/src/kinetis/kinetis_enet.c
+++ b/arch/arm/src/kinetis/kinetis_enet.c
@@ -165,9 +165,9 @@ struct kinetis_driver_s
struct enet_desc_s *txdesc; /* A pointer to the list of TX descriptor */
struct enet_desc_s *rxdesc; /* A pointer to the list of RX descriptors */
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
/* The DMA descriptors. A unaligned uint8_t is used to allocate the
* memory; 16 is added to assure that we can meet the descriptor alignment
@@ -435,7 +435,7 @@ static int kinetis_transmit(FAR struct kinetis_driver_s *priv)
* Function: kinetis_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -557,7 +557,7 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
- nllvdbg("IPv4 frame\n");
+ ninfo("IPv4 frame\n");
NETDEV_RXIPV4(&priv->dev);
/* Handle ARP on input then give the IPv4 packet to the network
@@ -598,7 +598,7 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
- nllvdbg("Iv6 frame\n");
+ ninfo("Iv6 frame\n");
NETDEV_RXIPV6(&priv->dev);
/* Give the IPv6 packet to the network layer */
@@ -731,7 +731,7 @@ static void kinetis_txdone(FAR struct kinetis_driver_s *priv)
putreg32(regval, KINETIS_ENET_EIMR);
}
- /* There should be space for a new TX in any event. Poll uIP for new XMIT
+ /* There should be space for a new TX in any event. Poll the network for new XMIT
* data
*/
@@ -848,7 +848,7 @@ static void kinetis_txtimeout(int argc, uint32_t arg, ...)
(void)kinetis_ifdown(&priv->dev);
(void)kinetis_ifup(&priv->dev);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&priv->dev, kinetis_txpoll);
}
@@ -881,7 +881,7 @@ static void kinetis_polltimer(int argc, uint32_t arg, ...)
if (!kinetics_txringfull(priv))
{
- /* If so, update TCP timing states and poll uIP for new XMIT data. Hmmm..
+ /* If so, update TCP timing states and poll the network for new XMIT data. Hmmm..
* might be bug here. Does this mean if there is a transmit in progress,
* we will missing TCP time state updates?
*/
@@ -918,9 +918,9 @@ static int kinetis_ifup(struct net_driver_s *dev)
uint8_t *mac = dev->d_mac.ether_addr_octet;
uint32_t regval;
- ndbg("Bringing up: %d.%d.%d.%d\n",
- dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
- (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+ ninfo("Bringing up: %d.%d.%d.%d\n",
+ dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+ (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
/* Initialize ENET buffers */
@@ -1112,7 +1112,7 @@ static int kinetis_txavail(struct net_driver_s *dev)
if (!kinetics_txringfull(priv))
{
- /* No, there is space for another transfer. Poll uIP for new
+ /* No, there is space for another transfer. Poll the network for new
* XMIT data.
*/
@@ -1695,7 +1695,7 @@ int kinetis_netinitialize(int intf)
{
/* We could not attach the ISR to the interrupt */
- ndbg("Failed to attach EMACTMR IRQ\n");
+ nerr("ERROR: Failed to attach EMACTMR IRQ\n");
return -EAGAIN;
}
#endif
@@ -1706,7 +1706,7 @@ int kinetis_netinitialize(int intf)
{
/* We could not attach the ISR to the interrupt */
- ndbg("Failed to attach EMACTX IRQ\n");
+ nerr("ERROR: Failed to attach EMACTX IRQ\n");
return -EAGAIN;
}
@@ -1716,7 +1716,7 @@ int kinetis_netinitialize(int intf)
{
/* We could not attach the ISR to the interrupt */
- ndbg("Failed to attach EMACRX IRQ\n");
+ nerr("ERROR: Failed to attach EMACRX IRQ\n");
return -EAGAIN;
}
@@ -1726,7 +1726,7 @@ int kinetis_netinitialize(int intf)
{
/* We could not attach the ISR to the interrupt */
- ndbg("Failed to attach EMACMISC IRQ\n");
+ nerr("ERROR: Failed to attach EMACMISC IRQ\n");
return -EAGAIN;
}
diff --git a/arch/arm/src/kinetis/kinetis_irq.c b/arch/arm/src/kinetis/kinetis_irq.c
index 44f21af47d611f546d8c80d9c2c13bc2b6aedcb5..d2a04de3ae6c1e9e6fe51f345fa9ee18774e5b05 100644
--- a/arch/arm/src/kinetis/kinetis_irq.c
+++ b/arch/arm/src/kinetis/kinetis_irq.c
@@ -105,50 +105,51 @@ extern uint32_t _vectors[];
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_IRQ)
+#if defined(CONFIG_DEBUG_IRQ_INFO)
static void kinetis_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
- lldbg("NVIC (%s, irq=%d):\n", msg, irq);
- lldbg(" INTCTRL: %08x VECTAB: %08x\n",
- getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
+
+ irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
+ irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
+ getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
- lldbg(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
- getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
- getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
+ irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
+ getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
+ getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
- lldbg(" IRQ ENABLE: %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
- getreg32(NVIC_IRQ64_95_ENABLE), getreg32(NVIC_IRQ96_127_ENABLE));
- lldbg(" SYSH_PRIO: %08x %08x %08x\n",
- getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
- getreg32(NVIC_SYSH12_15_PRIORITY));
- lldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
- getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
- getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
- getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
- getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
- getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ80_83_PRIORITY), getreg32(NVIC_IRQ84_87_PRIORITY),
- getreg32(NVIC_IRQ88_91_PRIORITY), getreg32(NVIC_IRQ92_95_PRIORITY));
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY),
- getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY));
+ irqinfo(" IRQ ENABLE: %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
+ getreg32(NVIC_IRQ64_95_ENABLE), getreg32(NVIC_IRQ96_127_ENABLE));
+ irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
+ getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
+ getreg32(NVIC_SYSH12_15_PRIORITY));
+ irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
+ getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
+ getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
+ getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
+ getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
+ getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ80_83_PRIORITY), getreg32(NVIC_IRQ84_87_PRIORITY),
+ getreg32(NVIC_IRQ88_91_PRIORITY), getreg32(NVIC_IRQ92_95_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY),
+ getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY));
#if NR_VECTORS > 111
- lldbg(" %08x %08x\n",
- getreg32(NVIC_IRQ112_115_PRIORITY), getreg32(NVIC_IRQ116_119_PRIORITY));
+ irqinfo(" %08x %08x\n",
+ getreg32(NVIC_IRQ112_115_PRIORITY), getreg32(NVIC_IRQ116_119_PRIORITY));
#endif
leave_critical_section(flags);
@@ -168,11 +169,11 @@ static void kinetis_dumpnvic(const char *msg, int irq)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
static int kinetis_nmi(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! NMI received\n");
+ _err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
@@ -180,7 +181,7 @@ static int kinetis_nmi(int irq, FAR void *context)
static int kinetis_busfault(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Bus fault recived\n");
+ _err("PANIC!!! Bus fault recived\n");
PANIC();
return 0;
}
@@ -188,7 +189,7 @@ static int kinetis_busfault(int irq, FAR void *context)
static int kinetis_usagefault(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Usage fault received\n");
+ _err("PANIC!!! Usage fault received\n");
PANIC();
return 0;
}
@@ -196,7 +197,7 @@ static int kinetis_usagefault(int irq, FAR void *context)
static int kinetis_pendsv(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! PendSV received\n");
+ _err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
@@ -204,7 +205,7 @@ static int kinetis_pendsv(int irq, FAR void *context)
static int kinetis_dbgmonitor(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Debug Monitor received\n");
+ _err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
}
@@ -212,7 +213,7 @@ static int kinetis_dbgmonitor(int irq, FAR void *context)
static int kinetis_reserved(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Reserved interrupt\n");
+ _err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
@@ -420,7 +421,7 @@ void up_irqinitialize(void)
/* Attach all other processor exceptions (except reset and sys tick) */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
irq_attach(KINETIS_IRQ_NMI, kinetis_nmi);
#ifndef CONFIG_ARM_MPU
irq_attach(KINETIS_IRQ_MEMFAULT, up_memfault);
diff --git a/arch/arm/src/kinetis/kinetis_pindump.c b/arch/arm/src/kinetis/kinetis_pindump.c
new file mode 100644
index 0000000000000000000000000000000000000000..579c01bb4d2c9d1752e29d6002664b4d9e910500
--- /dev/null
+++ b/arch/arm/src/kinetis/kinetis_pindump.c
@@ -0,0 +1,128 @@
+/****************************************************************************
+ * arch/arm/src/kinetis/kinetis_pindump.c
+ *
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+
+#include
+#include "up_arch.h"
+
+#include "kinetis.h"
+#include "kinetis_gpio.h"
+#include "kinetis_port.h"
+
+#ifdef CONFIG_DEBUG_GPIO_INFO
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Port letters for prettier debug output */
+
+static const char g_portchar[KINETIS_NPORTS] =
+{
+#if KINETIS_NPORTS > 9
+# error "Additional support required for this number of GPIOs"
+#elif KINETIS_NPORTS > 8
+ 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I'
+#elif KINETIS_NPORTS > 7
+ 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H'
+#elif KINETIS_NPORTS > 6
+ 'A', 'B', 'C', 'D', 'E', 'F', 'G'
+#elif KINETIS_NPORTS > 5
+ 'A', 'B', 'C', 'D', 'E', 'F'
+#elif KINETIS_NPORTS > 4
+ 'A', 'B', 'C', 'D', 'E'
+#elif KINETIS_NPORTS > 3
+ 'A', 'B', 'C', 'D'
+#elif KINETIS_NPORTS > 2
+ 'A', 'B', 'C'
+#elif KINETIS_NPORTS > 1
+ 'A', 'B'
+#elif KINETIS_NPORTS > 0
+ 'A'
+#else
+# error "Bad number of GPIOs"
+#endif
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function: kinetis_pindump
+ *
+ * Description:
+ * Dump all GPIO registers associated with the provided pin description
+ * along with a descriptive messasge.
+ *
+ ****************************************************************************/
+
+void kinetis_pindump(uint32_t pinset, const char *msg)
+{
+ irqstate_t flags;
+ uintptr_t base;
+ int port;
+
+ /* Decode the port and pin. Use the port number to get the GPIO base
+ * address.
+ */
+
+ port = (pinset & _PIN_PORT_MASK) >> _PIN_PORT_SHIFT;
+ DEBUGASSERT((unsigned)port < KINETIS_NPORTS);
+ base = KINETIS_GPIO_BASE(port);
+
+ /* The following requires exclusive access to the GPIO registers */
+
+ flags = enter_critical_section();
+
+ gpioinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
+ g_portchar[port], pinset, base, msg);
+ gpioinfo(" PDOR: %08x PDIR: %08x PDDR: %08x\n",
+ getreg32(base + KINETIS_GPIO_PDOR_OFFSET),
+ getreg32(base + KINETIS_GPIO_PDIR_OFFSET),
+ getreg32(base + KINETIS_GPIO_PDDR_OFFSET));
+
+ leave_critical_section(flags);
+}
+
+#endif /* CONFIG_DEBUG_GPIO_INFO */
diff --git a/arch/arm/src/kinetis/kinetis_pwm.c b/arch/arm/src/kinetis/kinetis_pwm.c
new file mode 100644
index 0000000000000000000000000000000000000000..0730bf8dd835beb841ae70c14eea92e4f0ced95f
--- /dev/null
+++ b/arch/arm/src/kinetis/kinetis_pwm.c
@@ -0,0 +1,789 @@
+/****************************************************************************
+ * arch/arm/src/kinetis/kinetis_pwm.c
+ *
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ * Alan Carvalho de Assis
+ * Ken Fazzone
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+
+#include "kinetis.h"
+#include "kinetis_pwm.h"
+#include "kinetis_gpio.h"
+#include "kinetis_ftm.h"
+#include "kinetis_sim.h"
+
+/* This module then only compiles if there is at least one enabled timer
+ * intended for use with the PWM upper half driver.
+ */
+
+#if defined(CONFIG_KINETIS_FTM0_PWM) || defined(CONFIG_KINETIS_FTM1_PWM) || \
+ defined(CONFIG_KINETIS_FTM2_PWM)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* PWM/Timer Definitions ****************************************************/
+
+/* Debug ********************************************************************/
+
+#ifdef CONFIG_DEBUG_PWM_INFO
+# define pwm_dumpgpio(p,m) kinetis_pindump(p,m)
+#else
+# define pwm_dumpgpio(p,m)
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+/* This structure represents the state of one PWM timer */
+
+struct kinetis_pwmtimer_s
+{
+ FAR const struct pwm_ops_s *ops; /* PWM operations */
+ uint8_t tpmid; /* Timer/PWM Module ID {0,..,2} */
+ uint8_t channel; /* Timer/PWM Module channel: {0,..5} */
+ uint32_t base; /* The base address of the timer */
+ uint32_t pincfg; /* Output pin configuration */
+ uint32_t pclk; /* The frequency of the peripheral clock */
+};
+
+/****************************************************************************
+ * Static Function Prototypes
+ ****************************************************************************/
+
+/* Register access */
+
+static uint32_t pwm_getreg(struct kinetis_pwmtimer_s *priv, int offset);
+static void pwm_putreg(struct kinetis_pwmtimer_s *priv, int offset, uint32_t value);
+
+#ifdef CONFIG_DEBUG_PWM_INFO
+static void pwm_dumpregs(struct kinetis_pwmtimer_s *priv, FAR const char *msg);
+#else
+# define pwm_dumpregs(priv,msg)
+#endif
+
+/* Timer management */
+
+static int pwm_timer(FAR struct kinetis_pwmtimer_s *priv,
+ FAR const struct pwm_info_s *info);
+
+/* PWM driver methods */
+
+static int pwm_setup(FAR struct pwm_lowerhalf_s *dev);
+static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev);
+
+static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
+ FAR const struct pwm_info_s *info);
+
+static int pwm_stop(FAR struct pwm_lowerhalf_s *dev);
+static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev,
+ int cmd, unsigned long arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* This is the list of lower half PWM driver methods used by the upper half
+ * driver.
+ */
+
+static const struct pwm_ops_s g_pwmops =
+{
+ .setup = pwm_setup,
+ .shutdown = pwm_shutdown,
+ .start = pwm_start,
+ .stop = pwm_stop,
+ .ioctl = pwm_ioctl,
+};
+
+#ifdef CONFIG_KINETIS_FTM0_PWM
+static struct kinetis_pwmtimer_s g_pwm0dev =
+{
+ .ops = &g_pwmops,
+ .tpmid = 0,
+ .channel = CONFIG_KINETIS_FTM0_CHANNEL,
+ .base = KINETIS_FTM0_BASE,
+ .pincfg = PWM_FTM0_PINCFG,
+ .pclk = BOARD_CORECLK_FREQ,
+};
+#endif
+
+#ifdef CONFIG_KINETIS_FTM1_PWM
+static struct kinetis_pwmtimer_s g_pwm1dev =
+{
+ .ops = &g_pwmops,
+ .tpmid = 1,
+ .channel = CONFIG_KINETIS_FTM1_CHANNEL,
+ .base = KINETIS_FTM1_BASE,
+ .pincfg = PWM_FTM1_PINCFG,
+ .pclk = BOARD_CORECLK_FREQ,
+};
+#endif
+
+#ifdef CONFIG_KINETIS_FTM2_PWM
+static struct kinetis_pwmtimer_s g_pwm2dev =
+{
+ .ops = &g_pwmops,
+ .tpmid = 2,
+ .channel = CONFIG_KINETIS_FTM2_CHANNEL,
+ .base = KINETIS_FTM2_BASE,
+ .pincfg = PWM_FTM2_PINCFG,
+ .pclk = BOARD_CORECLK_FREQ,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: pwm_getreg
+ *
+ * Description:
+ * Read the value of an PWM timer register.
+ *
+ * Input Parameters:
+ * priv - A reference to the PWM block status
+ * offset - The offset to the register to read
+ *
+ * Returned Value:
+ * The current contents of the specified register
+ *
+ ****************************************************************************/
+
+static uint32_t pwm_getreg(struct kinetis_pwmtimer_s *priv, int offset)
+{
+ return getreg32(priv->base + offset);
+}
+
+/****************************************************************************
+ * Name: pwm_putreg
+ *
+ * Description:
+ * Read the value of an PWM timer register.
+ *
+ * Input Parameters:
+ * priv - A reference to the PWM block status
+ * offset - The offset to the register to read
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void pwm_putreg(struct kinetis_pwmtimer_s *priv, int offset, uint32_t value)
+{
+ putreg32(value, priv->base + offset);
+}
+
+/****************************************************************************
+ * Name: pwm_dumpregs
+ *
+ * Description:
+ * Dump all timer registers.
+ *
+ * Input parameters:
+ * priv - A reference to the PWM block status
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_PWM_INFO
+static void pwm_dumpregs(struct kinetis_pwmtimer_s *priv, FAR const char *msg)
+{
+ int nchannels = (priv->tpmid == 0) ? 8 : 2;
+
+ pwminfo("%s:\n", msg);
+ pwminfo(" FTM%d_SC: %04x FTM%d_CNT: %04x FTM%d_MOD: %04x\n",
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_SC_OFFSET),
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_CNT_OFFSET),
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_MOD_OFFSET));
+ pwminfo(" FTM%d_STATUS: %04x FTM%d_CONF: %04x\n",
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_STATUS_OFFSET),
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_CONF_OFFSET));
+ pwminfo(" FTM%d_C0SC: %04x FTM%d_C0V: %04x\n",
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_C0SC_OFFSET),
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_C0V_OFFSET));
+ pwminfo(" FTM%d_C1SC: %04x FTM%d_C1V: %04x\n",
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_C1SC_OFFSET),
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_C1V_OFFSET));
+
+ if (nchannels >= 3)
+ {
+ pwminfo(" FTM%d_C2SC: %04x FTM%d_C2V: %04x\n",
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_C2SC_OFFSET),
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_C2V_OFFSET));
+ }
+
+ if (nchannels >= 4)
+ {
+ pwminfo(" FTM%d_C3SC: %04x FTM%d_C3V: %04x\n",
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_C3SC_OFFSET),
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_C3V_OFFSET));
+ }
+
+ if (nchannels >= 5)
+ {
+ pwminfo(" FTM%d_C4SC: %04x FTM%d_C4V: %04x\n",
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_C4SC_OFFSET),
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_C4V_OFFSET));
+ }
+
+ if (nchannels >= 6)
+ {
+ pwminfo(" FTM%d_C5SC: %04x FTM%d_C5V: %04x\n",
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_C5SC_OFFSET),
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_C5V_OFFSET));
+ }
+ if (nchannels >= 7)
+ {
+ pwminfo(" FTM%d_C6SC: %04x FTM%d_C6V: %04x\n",
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_C6SC_OFFSET),
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_C6V_OFFSET));
+ }
+ if (nchannels >= 8)
+ {
+ pwminfo(" FTM%d_C7SC: %04x FTM%d_C7V: %04x\n",
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_C7SC_OFFSET),
+ priv->tpmid,
+ pwm_getreg(priv, KINETIS_FTM_C7V_OFFSET));
+ }
+}
+#endif
+
+/****************************************************************************
+ * Name: pwm_timer
+ *
+ * Description:
+ * (Re-)initialize the timer resources and start the pulsed output
+ *
+ * Input parameters:
+ * priv - A reference to the lower half PWM driver state structure
+ * info - A reference to the characteristics of the pulsed output
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_timer(FAR struct kinetis_pwmtimer_s *priv,
+ FAR const struct pwm_info_s *info)
+{
+ /* Calculated values */
+
+ uint32_t prescaler;
+ uint32_t tpmclk;
+ uint32_t modulo;
+ uint32_t regval;
+ uint32_t cv;
+ uint8_t i;
+
+ static const uint8_t presc_values[8] = {1, 2, 4, 8, 16, 32, 64, 128};
+
+ /* Register contents */
+
+ DEBUGASSERT(priv != NULL && info != NULL);
+
+ pwminfo("FTM%d channel: %d frequency: %d duty: %08x\n",
+ priv->tpmid, priv->channel, info->frequency, info->duty);
+
+ DEBUGASSERT(info->frequency > 0 && info->duty > 0 &&
+ info->duty < uitoub16(100));
+
+ /* Calculate optimal values for the timer prescaler and for the timer modulo
+ * register. If' frequency' is the desired frequency, then
+ *
+ * modulo = tpmclk / frequency
+ * tpmclk = pclk / presc
+ *
+ * Or,
+ *
+ * modulo = pclk / presc / frequency
+ *
+ * There are many solutions to do this, but the best solution will be the
+ * one that has the largest modulo value and the smallest prescaler value.
+ * That is the solution that should give us the most accuracy in the timer
+ * control. Subject to:
+ *
+ * 1 <= presc <= 128 (need to be 1, 2, 4, 8, 16, 32, 64, 128)
+ * 1 <= modulo <= 65535
+ *
+ * So presc = pclk / 65535 / frequency would be optimal.
+ *
+ * Example:
+ *
+ * pclk = 24 MHz
+ * frequency = 100 Hz
+ *
+ * prescaler = 24,000,000 / 65,535 / 100
+ * = 3.6 (or 4 -- taking the ceiling always)
+ * timclk = 24,000,000 / 4
+ * = 6,000,000
+ * modulo = 6,000,000 / 100
+ * = 60,000
+ */
+
+ prescaler = (priv->pclk / info->frequency + 65534) / 65535;
+
+ for (i = 0; i < 7; i++)
+ {
+ if (prescaler <= presc_values[i])
+ {
+ break;
+ }
+ }
+
+ prescaler = i;
+
+ tpmclk = priv->pclk / presc_values[prescaler];
+
+ modulo = tpmclk / info->frequency;
+ if (modulo < 1)
+ {
+ modulo = 1;
+ }
+ else if (modulo > 65535)
+ {
+ modulo = 65535;
+ }
+
+ /* Duty cycle:
+ *
+ * duty cycle = cv / modulo (fractional value)
+ */
+
+ cv = b16toi(info->duty * modulo + b16HALF);
+
+ pwminfo("FTM%d PCLK: %d frequency: %d FTMCLK: %d prescaler: %d modulo: %d c0v: %d\n",
+ priv->tpmid, priv->pclk, info->frequency, tpmclk,
+ presc_values[prescaler], modulo, cv);
+
+ /* Disable FTM and reset CNT before writing MOD and PS */
+
+ pwm_putreg(priv, KINETIS_FTM_SC_OFFSET, FTM_SC_CLKS_NONE);
+ pwm_putreg(priv, KINETIS_FTM_CNT_OFFSET, 0);
+
+ /* Set the modulo value */
+
+ pwm_putreg(priv, KINETIS_FTM_MOD_OFFSET, (uint16_t)modulo);
+
+ /* Set the duty cycle for channel specific */
+
+ switch (priv->channel)
+ {
+ case 0: /* PWM Mode configuration: Channel 0 */
+ {
+ pwm_putreg(priv, KINETIS_FTM_C0SC_OFFSET, FTM_CSC_MSB | FTM_CSC_ELSB);
+ pwm_putreg(priv, KINETIS_FTM_C0V_OFFSET, (uint16_t) cv);
+ }
+ break;
+
+ case 1: /* PWM Mode configuration: Channel 1 */
+ {
+ pwm_putreg(priv, KINETIS_FTM_C1SC_OFFSET, FTM_CSC_MSB | FTM_CSC_ELSB);
+ pwm_putreg(priv, KINETIS_FTM_C1V_OFFSET, (uint16_t) cv);
+ }
+ break;
+
+ case 2: /* PWM Mode configuration: Channel 2 */
+ {
+ pwm_putreg(priv, KINETIS_FTM_C2SC_OFFSET, FTM_CSC_MSB | FTM_CSC_ELSB);
+ pwm_putreg(priv, KINETIS_FTM_C2V_OFFSET, (uint16_t) cv);
+ }
+ break;
+
+ case 3: /* PWM Mode configuration: Channel 3 */
+ {
+ pwm_putreg(priv, KINETIS_FTM_C3SC_OFFSET, FTM_CSC_MSB | FTM_CSC_ELSB);
+ pwm_putreg(priv, KINETIS_FTM_C3V_OFFSET, (uint16_t) cv);
+ }
+ break;
+
+ case 4: /* PWM Mode configuration: Channel 4 */
+ {
+ pwm_putreg(priv, KINETIS_FTM_C4SC_OFFSET, FTM_CSC_MSB | FTM_CSC_ELSB);
+ pwm_putreg(priv, KINETIS_FTM_C4V_OFFSET, (uint16_t) cv);
+ }
+ break;
+
+ case 5: /* PWM Mode configuration: Channel 5 */
+ {
+ pwm_putreg(priv, KINETIS_FTM_C5SC_OFFSET, FTM_CSC_MSB | FTM_CSC_ELSB);
+ pwm_putreg(priv, KINETIS_FTM_C5V_OFFSET, (uint16_t) cv);
+ }
+ break;
+
+ case 6: /* PWM Mode configuration: Channel 6 */
+ {
+ pwm_putreg(priv, KINETIS_FTM_C6SC_OFFSET, FTM_CSC_MSB | FTM_CSC_ELSB);
+ pwm_putreg(priv, KINETIS_FTM_C6V_OFFSET, (uint16_t) cv);
+ }
+ break;
+ case 7: /* PWM Mode configuration: Channel 7 */
+ {
+ pwm_putreg(priv, KINETIS_FTM_C7SC_OFFSET, FTM_CSC_MSB | FTM_CSC_ELSB);
+ pwm_putreg(priv, KINETIS_FTM_C7V_OFFSET, (uint16_t) cv);
+ }
+ break;
+
+ default:
+ pwmerr("ERROR: No such channel: %d\n", priv->channel);
+ return -EINVAL;
+ }
+
+ /* Set prescaler and enable clock */
+
+ regval = pwm_getreg(priv, KINETIS_FTM_SC_OFFSET);
+ regval &= ~(FTM_SC_PS_MASK);
+ regval &= ~(FTM_SC_CLKS_MASK);
+ regval |= prescaler | FTM_SC_CLKS_SYSCLK;
+ pwm_putreg(priv, KINETIS_FTM_SC_OFFSET, (uint16_t)regval);
+
+ pwm_dumpregs(priv, "After starting");
+ return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_setup
+ *
+ * Description:
+ * This method is called when the driver is opened. The lower half driver
+ * should configure and initialize the device so that it is ready for use.
+ * It should not, however, output pulses until the start method is called.
+ *
+ * Input parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ * Assumptions:
+ * AHB1 or 2 clocking for the GPIOs and timer has already been configured
+ * by the RCC logic at power up.
+ *
+ ****************************************************************************/
+
+static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
+{
+ uint32_t regval;
+ FAR struct kinetis_pwmtimer_s *priv = (FAR struct kinetis_pwmtimer_s *)dev;
+
+ /* Enable access to FTM modules */
+
+ regval = getreg32(KINETIS_SIM_SCGC6);
+ regval |= SIM_SCGC6_FTM0 | SIM_SCGC6_FTM1;
+ putreg32(regval, KINETIS_SIM_SCGC6);
+
+ regval = getreg32(KINETIS_SIM_SCGC3);
+ regval |= SIM_SCGC3_FTM2;
+ putreg32(regval, KINETIS_SIM_SCGC3);
+
+ pwminfo("FTM%d pincfg: %08x\n", priv->tpmid, priv->pincfg);
+ pwm_dumpregs(priv, "Initially");
+
+ /* Configure the PWM output pin, but do not start the timer yet */
+
+ kinetis_pinconfig(priv->pincfg);
+ pwm_dumpgpio(priv->pincfg, "PWM setup");
+ return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_shutdown
+ *
+ * Description:
+ * This method is called when the driver is closed. The lower half driver
+ * stop pulsed output, free any resources, disable the timer hardware, and
+ * put the system into the lowest possible power usage state
+ *
+ * Input parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
+{
+ FAR struct kinetis_pwmtimer_s *priv = (FAR struct kinetis_pwmtimer_s *)dev;
+ uint32_t pincfg;
+
+ pwminfo("FTM%d pincfg: %08x\n", priv->tpmid, priv->pincfg);
+
+ /* Make sure that the output has been stopped */
+
+ pwm_stop(dev);
+
+ /* Then put the GPIO pin back to the default state */
+
+ pincfg = (priv->pincfg & ~(_PIN_MODE_MASK));
+ pincfg |= GPIO_INPUT;
+ kinetis_pinconfig(pincfg);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_start
+ *
+ * Description:
+ * (Re-)initialize the timer resources and start the pulsed output
+ *
+ * Input parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ * info - A reference to the characteristics of the pulsed output
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
+ FAR const struct pwm_info_s *info)
+{
+ FAR struct kinetis_pwmtimer_s *priv = (FAR struct kinetis_pwmtimer_s *)dev;
+ return pwm_timer(priv, info);
+}
+
+/****************************************************************************
+ * Name: pwm_stop
+ *
+ * Description:
+ * Stop the pulsed output and reset the timer resources
+ *
+ * Input parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ * Assumptions:
+ * This function is called to stop the pulsed output at anytime. This
+ * method is also called from the timer interrupt handler when a repetition
+ * count expires... automatically stopping the timer.
+ *
+ ****************************************************************************/
+
+static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
+{
+ FAR struct kinetis_pwmtimer_s *priv = (FAR struct kinetis_pwmtimer_s *)dev;
+ irqstate_t flags;
+
+ pwminfo("FTM%d\n", priv->tpmid);
+
+ /* Disable interrupts momentary to stop any ongoing timer processing and
+ * to prevent any concurrent access to the reset register.
+ */
+
+ flags = enter_critical_section();
+
+ /* Disable further interrupts and stop the timer */
+
+ pwm_putreg(priv, KINETIS_FTM_SC_OFFSET, FTM_SC_CLKS_NONE);
+ pwm_putreg(priv, KINETIS_FTM_CNT_OFFSET, 0);
+
+ /* Determine which timer channel to clear */
+
+ switch (priv->channel)
+ {
+ case 0:
+ pwm_putreg(priv, KINETIS_FTM_C0V_OFFSET, 0);
+ break;
+
+ case 1:
+ pwm_putreg(priv, KINETIS_FTM_C1V_OFFSET, 0);
+ break;
+
+ case 2:
+ pwm_putreg(priv, KINETIS_FTM_C2V_OFFSET, 0);
+ break;
+
+ case 3:
+ pwm_putreg(priv, KINETIS_FTM_C3V_OFFSET, 0);
+ break;
+
+ case 4:
+ pwm_putreg(priv, KINETIS_FTM_C4V_OFFSET, 0);
+ break;
+
+ case 5:
+ pwm_putreg(priv, KINETIS_FTM_C5V_OFFSET, 0);
+ break;
+
+ case 6:
+ pwm_putreg(priv, KINETIS_FTM_C6V_OFFSET, 0);
+ break;
+
+ case 7:
+ pwm_putreg(priv, KINETIS_FTM_C7V_OFFSET, 0);
+ break;
+
+ default:
+ pwmerr("ERROR: No such channel: %d\n", priv->channel);
+ return -EINVAL;
+ }
+
+ leave_critical_section(flags);
+
+ pwm_dumpregs(priv, "After stop");
+ return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_ioctl
+ *
+ * Description:
+ * Lower-half logic may support platform-specific ioctl commands
+ *
+ * Input parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ * cmd - The ioctl command
+ * arg - The argument accompanying the ioctl command
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg)
+{
+#ifdef CONFIG_DEBUG_PWM_INFO
+ FAR struct kinetis_pwmtimer_s *priv = (FAR struct kinetis_pwmtimer_s *)dev;
+
+ /* There are no platform-specific ioctl commands */
+
+ pwminfo("FTM%d\n", priv->tpmid);
+#endif
+ return -ENOTTY;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: kinetis_pwminitialize
+ *
+ * Description:
+ * Initialize one timer for use with the upper_level PWM driver.
+ *
+ * Input Parameters:
+ * timer - A number identifying the timer use.
+ *
+ * Returned Value:
+ * On success, a pointer to the kinetis lower half PWM driver is returned.
+ * NULL is returned on any failure.
+ *
+ ****************************************************************************/
+
+FAR struct pwm_lowerhalf_s *kinetis_pwminitialize(int timer)
+{
+ FAR struct kinetis_pwmtimer_s *lower;
+
+ pwminfo("FTM%d\n", timer);
+
+ switch (timer)
+ {
+#ifdef CONFIG_KINETIS_FTM0_PWM
+ case 0:
+ lower = &g_pwm0dev;
+
+ break;
+#endif
+
+#ifdef CONFIG_KINETIS_FTM1_PWM
+ case 1:
+ lower = &g_pwm1dev;
+
+ break;
+#endif
+
+#ifdef CONFIG_KINETIS_FTM2_PWM
+ case 2:
+ lower = &g_pwm2dev;
+
+ break;
+#endif
+
+ default:
+ pwmerr("ERROR: No such timer configured\n");
+ return NULL;
+ }
+
+ return (FAR struct pwm_lowerhalf_s *)lower;
+}
+
+#endif /* CONFIG_KINETIS_FTMn_PWM, n = 0,...,2 */
diff --git a/arch/arm/src/kinetis/kinetis_pwm.h b/arch/arm/src/kinetis/kinetis_pwm.h
new file mode 100644
index 0000000000000000000000000000000000000000..09508d4bfea7a1433bb7865600a1d924c4fa4e63
--- /dev/null
+++ b/arch/arm/src/kinetis/kinetis_pwm.h
@@ -0,0 +1,198 @@
+/************************************************************************************
+ * arch/arm/src/kinetis/kinetis_pwm.h
+ *
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ * Alan Carvalho de Assis
+ * Ken Fazzone
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_PWM_H
+#define __ARCH_ARM_SRC_KINETIS_KINETIS_PWM_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Configuration ********************************************************************/
+/* Timer devices may be used for different purposes. One special purpose is
+ * to generate modulated outputs for such things as motor control. If CONFIG_KINETIS_FTMn
+ * is defined then the CONFIG_KINETIS_FTMn_PWM must also be defined to indicate that
+ * timer "n" is intended to be used for pulsed output signal generation.
+ */
+
+#ifndef CONFIG_KINETIS_FTM0
+# undef CONFIG_KINETIS_FTM0_PWM
+#endif
+#ifndef CONFIG_KINETIS_FTM1
+# undef CONFIG_KINETIS_FTM1_PWM
+#endif
+#ifndef CONFIG_KINETIS_FTM2
+# undef CONFIG_KINETIS_FTM2_PWM
+#endif
+
+/* Check if PWM support for any channel is enabled. */
+
+#if defined(CONFIG_KINETIS_FTM0_PWM) || defined(CONFIG_KINETIS_FTM1_PWM) || \
+ defined(CONFIG_KINETIS_FTM2_PWM)
+
+#include
+#include "kinetis_pinmux.h"
+
+/* For each timer that is enabled for PWM usage, we need the following additional
+ * configuration settings:
+ *
+ * CONFIG_KINETIS_FTMx_CHANNEL - Specifies the timer output channel {1,..,4}
+ * PWM_FTMx_CHn - One of the values defined in kinetis*_pinmap.h. In the case
+ * where there are multiple pin selections, the correct setting must be provided
+ * in the arch/board/board.h file.
+ */
+
+#ifdef CONFIG_KINETIS_FTM0_PWM
+# if !defined(CONFIG_KINETIS_FTM0_CHANNEL)
+# error "CONFIG_KINETIS_FTM0_CHANNEL must be provided"
+# elif CONFIG_KINETIS_FTM0_CHANNEL == 0
+# define PWM_FTM0_PINCFG GPIO_FTM0_CH0OUT
+# elif CONFIG_KINETIS_FTM0_CHANNEL == 1
+# define PWM_FTM0_PINCFG GPIO_FTM0_CH1OUT
+# elif CONFIG_KINETIS_FTM0_CHANNEL == 2
+# define PWM_FTM0_PINCFG GPIO_FTM0_CH2OUT
+# elif CONFIG_KINETIS_FTM0_CHANNEL == 3
+# define PWM_FTM0_PINCFG GPIO_FTM0_CH3OUT
+# elif CONFIG_KINETIS_FTM0_CHANNEL == 4
+# define PWM_FTM0_PINCFG GPIO_FTM0_CH4OUT
+# elif CONFIG_KINETIS_FTM0_CHANNEL == 5
+# define PWM_FTM0_PINCFG GPIO_FTM0_CH5OUT
+# elif CONFIG_KINETIS_FTM0_CHANNEL == 6
+# define PWM_FTM0_PINCFG GPIO_FTM0_CH6OUT
+# elif CONFIG_KINETIS_FTM0_CHANNEL == 7
+# define PWM_FTM0_PINCFG GPIO_FTM0_CH7OUT
+# else
+# error "Unsupported value of CONFIG_KINETIS_FTM1_CHANNEL"
+# endif
+#endif
+
+#ifdef CONFIG_KINETIS_FTM1_PWM
+# if !defined(CONFIG_KINETIS_FTM1_CHANNEL)
+# error "CONFIG_KINETIS_FTM1_CHANNEL must be provided"
+# elif CONFIG_KINETIS_FTM1_CHANNEL == 0
+# define PWM_FTM1_PINCFG GPIO_FTM1_CH0OUT
+# elif CONFIG_KINETIS_FTM1_CHANNEL == 1
+# define PWM_FTM1_PINCFG GPIO_FTM1_CH1OUT
+# elif CONFIG_KINETIS_FTM1_CHANNEL == 2
+# define PWM_FTM1_PINCFG GPIO_FTM1_CH2OUT
+# elif CONFIG_KINETIS_FTM1_CHANNEL == 3
+# define PWM_FTM1_PINCFG GPIO_FTM1_CH3OUT
+# elif CONFIG_KINETIS_FTM1_CHANNEL == 4
+# define PWM_FTM1_PINCFG GPIO_FTM1_CH4OUT
+# elif CONFIG_KINETIS_FTM1_CHANNEL == 5
+# define PWM_FTM1_PINCFG GPIO_FTM1_CH5OUT
+# else
+# error "Unsupported value of CONFIG_KINETIS_FTM2_CHANNEL"
+# endif
+#endif
+
+#ifdef CONFIG_KINETIS_FTM2_PWM
+# if !defined(CONFIG_KINETIS_FTM2_CHANNEL)
+# error "CONFIG_KINETIS_FTM2_CHANNEL must be provided"
+# elif CONFIG_KINETIS_FTM2_CHANNEL == 0
+# define PWM_FTM2_PINCFG GPIO_FTM2_CH0OUT
+# elif CONFIG_KINETIS_FTM2_CHANNEL == 1
+# define PWM_FTM2_PINCFG GPIO_FTM2_CH1OUT
+# elif CONFIG_KINETIS_FTM2_CHANNEL == 2
+# define PWM_FTM2_PINCFG GPIO_FTM2_CH2OUT
+# elif CONFIG_KINETIS_FTM2_CHANNEL == 3
+# define PWM_FTM2_PINCFG GPIO_FTM2_CH3OUT
+# elif CONFIG_KINETIS_FTM2_CHANNEL == 4
+# define PWM_FTM2_PINCFG GPIO_FTM2_CH4OUT
+# elif CONFIG_KINETIS_FTM2_CHANNEL == 5
+# define PWM_FTM2_PINCFG GPIO_FTM2_CH5OUT
+# else
+# error "Unsupported value of CONFIG_KINETIS_FTM3_CHANNEL"
+# endif
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: kinetis_pwminitialize
+ *
+ * Description:
+ * Initialize one timer for use with the upper_level PWM driver.
+ *
+ * Input Parameters:
+ * timer - A number identifying the timer use.
+ *
+ * Returned Value:
+ * On success, a pointer to the kinetis lower half PWM driver is returned.
+ * NULL is returned on any failure.
+ *
+ ************************************************************************************/
+
+FAR struct pwm_lowerhalf_s *kinetis_pwminitialize(int timer);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_KINETIS_FTMx_PWM */
+#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_PWM_H */
diff --git a/arch/arm/src/kinetis/kinetis_sdhc.c b/arch/arm/src/kinetis/kinetis_sdhc.c
index 7841cc1ad59e7e3ec842515f39fcc8f61d2aa709..aff35be9b4d8fc82346d9c92666c3b7ff8fce837 100644
--- a/arch/arm/src/kinetis/kinetis_sdhc.c
+++ b/arch/arm/src/kinetis/kinetis_sdhc.c
@@ -89,7 +89,7 @@
# define CONFIG_KINETIS_SDHC_DMAPRIO DMA_CCR_PRIMED
#endif
-#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_VERBOSE)
+#ifndef CONFIG_DEBUG_MEMCARD_INFO
# undef CONFIG_SDIO_XFRDEBUG
#endif
@@ -574,29 +574,29 @@ static void kinetis_sample(struct kinetis_dev_s *priv, int index)
static void kinetis_dumpsample(struct kinetis_dev_s *priv,
struct kinetis_sdhcregs_s *regs, const char *msg)
{
- fdbg("SDHC Registers: %s\n", msg);
- fdbg(" DSADDR[%08x]: %08x\n", KINETIS_SDHC_DSADDR, regs->dsaddr);
- fdbg(" BLKATTR[%08x]: %08x\n", KINETIS_SDHC_BLKATTR, regs->blkattr);
- fdbg(" CMDARG[%08x]: %08x\n", KINETIS_SDHC_CMDARG, regs->cmdarg);
- fdbg(" XFERTY[%08x]: %08x\n", KINETIS_SDHC_XFERTYP, regs->xferty);
- fdbg(" CMDRSP0[%08x]: %08x\n", KINETIS_SDHC_CMDRSP0, regs->cmdrsp0);
- fdbg(" CMDRSP1[%08x]: %08x\n", KINETIS_SDHC_CMDRSP1, regs->cmdrsp1);
- fdbg(" CMDRSP2[%08x]: %08x\n", KINETIS_SDHC_CMDRSP2, regs->cmdrsp2);
- fdbg(" CMDRSP3[%08x]: %08x\n", KINETIS_SDHC_CMDRSP3, regs->cmdrsp3);
- fdbg(" PRSSTAT[%08x]: %08x\n", KINETIS_SDHC_PRSSTAT, regs->prsstat);
- fdbg(" PROCTL[%08x]: %08x\n", KINETIS_SDHC_PROCTL, regs->proctl);
- fdbg(" SYSCTL[%08x]: %08x\n", KINETIS_SDHC_SYSCTL, regs->sysctl);
- fdbg(" IRQSTAT[%08x]: %08x\n", KINETIS_SDHC_IRQSTAT, regs->irqstat);
- fdbg("IRQSTATEN[%08x]: %08x\n", KINETIS_SDHC_IRQSTATEN, regs->irqstaten);
- fdbg(" IRQSIGEN[%08x]: %08x\n", KINETIS_SDHC_IRQSIGEN, regs->irqsigen);
- fdbg(" AC12ERR[%08x]: %08x\n", KINETIS_SDHC_AC12ERR, regs->ac12err);
- fdbg(" HTCAPBLT[%08x]: %08x\n", KINETIS_SDHC_HTCAPBLT, regs->htcapblt);
- fdbg(" WML[%08x]: %08x\n", KINETIS_SDHC_WML, regs->wml);
- fdbg(" ADMAES[%08x]: %08x\n", KINETIS_SDHC_ADMAES, regs->admaes);
- fdbg(" ADSADDR[%08x]: %08x\n", KINETIS_SDHC_ADSADDR, regs->adsaddr);
- fdbg(" VENDOR[%08x]: %08x\n", KINETIS_SDHC_VENDOR, regs->vendor);
- fdbg(" MMCBOOT[%08x]: %08x\n", KINETIS_SDHC_MMCBOOT, regs->mmcboot);
- fdbg(" HOSTVER[%08x]: %08x\n", KINETIS_SDHC_HOSTVER, regs->hostver);
+ mcinfo("SDHC Registers: %s\n", msg);
+ mcinfo(" DSADDR[%08x]: %08x\n", KINETIS_SDHC_DSADDR, regs->dsaddr);
+ mcinfo(" BLKATTR[%08x]: %08x\n", KINETIS_SDHC_BLKATTR, regs->blkattr);
+ mcinfo(" CMDARG[%08x]: %08x\n", KINETIS_SDHC_CMDARG, regs->cmdarg);
+ mcinfo(" XFERTY[%08x]: %08x\n", KINETIS_SDHC_XFERTYP, regs->xferty);
+ mcinfo(" CMDRSP0[%08x]: %08x\n", KINETIS_SDHC_CMDRSP0, regs->cmdrsp0);
+ mcinfo(" CMDRSP1[%08x]: %08x\n", KINETIS_SDHC_CMDRSP1, regs->cmdrsp1);
+ mcinfo(" CMDRSP2[%08x]: %08x\n", KINETIS_SDHC_CMDRSP2, regs->cmdrsp2);
+ mcinfo(" CMDRSP3[%08x]: %08x\n", KINETIS_SDHC_CMDRSP3, regs->cmdrsp3);
+ mcinfo(" PRSSTAT[%08x]: %08x\n", KINETIS_SDHC_PRSSTAT, regs->prsstat);
+ mcinfo(" PROCTL[%08x]: %08x\n", KINETIS_SDHC_PROCTL, regs->proctl);
+ mcinfo(" SYSCTL[%08x]: %08x\n", KINETIS_SDHC_SYSCTL, regs->sysctl);
+ mcinfo(" IRQSTAT[%08x]: %08x\n", KINETIS_SDHC_IRQSTAT, regs->irqstat);
+ mcinfo("IRQSTATEN[%08x]: %08x\n", KINETIS_SDHC_IRQSTATEN, regs->irqstaten);
+ mcinfo(" IRQSIGEN[%08x]: %08x\n", KINETIS_SDHC_IRQSIGEN, regs->irqsigen);
+ mcinfo(" AC12ERR[%08x]: %08x\n", KINETIS_SDHC_AC12ERR, regs->ac12err);
+ mcinfo(" HTCAPBLT[%08x]: %08x\n", KINETIS_SDHC_HTCAPBLT, regs->htcapblt);
+ mcinfo(" WML[%08x]: %08x\n", KINETIS_SDHC_WML, regs->wml);
+ mcinfo(" ADMAES[%08x]: %08x\n", KINETIS_SDHC_ADMAES, regs->admaes);
+ mcinfo(" ADSADDR[%08x]: %08x\n", KINETIS_SDHC_ADSADDR, regs->adsaddr);
+ mcinfo(" VENDOR[%08x]: %08x\n", KINETIS_SDHC_VENDOR, regs->vendor);
+ mcinfo(" MMCBOOT[%08x]: %08x\n", KINETIS_SDHC_MMCBOOT, regs->mmcboot);
+ mcinfo(" HOSTVER[%08x]: %08x\n", KINETIS_SDHC_HOSTVER, regs->hostver);
}
#endif
@@ -791,8 +791,8 @@ static void kinetis_transmit(struct kinetis_dev_s *priv)
* ready (BWR)
*/
- fllvdbg("Entry: remaining: %d IRQSTAT: %08x\n",
- priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
+ mcinfo("Entry: remaining: %d IRQSTAT: %08x\n",
+ priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
while (priv->remaining > 0 &&
(getreg32(KINETIS_SDHC_IRQSTAT) & SDHC_INT_BWR) != 0)
@@ -837,9 +837,8 @@ static void kinetis_transmit(struct kinetis_dev_s *priv)
putreg32(data.w, KINETIS_SDHC_DATPORT);
}
- fllvdbg("Exit: remaining: %d IRQSTAT: %08x\n",
- priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
-
+ mcinfo("Exit: remaining: %d IRQSTAT: %08x\n",
+ priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
}
#endif
@@ -877,8 +876,8 @@ static void kinetis_receive(struct kinetis_dev_s *priv)
* ready (BRR)
*/
- fllvdbg("Entry: remaining: %d IRQSTAT: %08x\n",
- priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
+ mcinfo("Entry: remaining: %d IRQSTAT: %08x\n",
+ priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
while (priv->remaining > 0 &&
(getreg32(KINETIS_SDHC_IRQSTAT) & SDHC_INT_BRR) != 0)
@@ -929,10 +928,9 @@ static void kinetis_receive(struct kinetis_dev_s *priv)
putreg32(watermark << SDHC_WML_RD_SHIFT, KINETIS_SDHC_WML);
- fllvdbg("Exit: remaining: %d IRQSTAT: %08x WML: %08x\n",
- priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT),
- getreg32(KINETIS_SDHC_WML));
-
+ mcinfo("Exit: remaining: %d IRQSTAT: %08x WML: %08x\n",
+ priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT),
+ getreg32(KINETIS_SDHC_WML));
}
#endif
@@ -973,7 +971,7 @@ static void kinetis_eventtimeout(int argc, uint32_t arg)
/* Wake up any waiting threads */
kinetis_endwait(priv, SDIOWAIT_TIMEOUT);
- flldbg("Timeout: remaining: %d\n", priv->remaining);
+ mcerr("ERROR: Timeout: remaining: %d\n", priv->remaining);
}
}
@@ -1105,8 +1103,8 @@ static int kinetis_interrupt(int irq, void *context)
regval = getreg32(KINETIS_SDHC_IRQSIGEN);
enabled = getreg32(KINETIS_SDHC_IRQSTAT) & regval;
- fllvdbg("IRQSTAT: %08x IRQSIGEN %08x enabled: %08x\n",
- getreg32(KINETIS_SDHC_IRQSTAT), regval, enabled);
+ mcinfo("IRQSTAT: %08x IRQSIGEN %08x enabled: %08x\n",
+ getreg32(KINETIS_SDHC_IRQSTAT), regval, enabled);
/* Disable card interrupts to clear the card interrupt to the host system. */
@@ -1162,7 +1160,7 @@ static int kinetis_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
- flldbg("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
+ mcerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
kinetis_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
@@ -1172,7 +1170,7 @@ static int kinetis_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
- flldbg("ERROR: Data timeout, remaining: %d\n", priv->remaining);
+ mcerr("ERROR: Data timeout, remaining: %d\n", priv->remaining);
kinetis_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT);
}
}
@@ -1289,9 +1287,9 @@ static void kinetis_reset(FAR struct sdio_dev_s *dev)
putreg32(SDHC_INT_ALL, KINETIS_SDHC_IRQSTATEN);
- fvdbg("SYSCTL: %08x PRSSTAT: %08x IRQSTATEN: %08x\n",
- getreg32(KINETIS_SDHC_SYSCTL), getreg32(KINETIS_SDHC_PRSSTAT),
- getreg32(KINETIS_SDHC_IRQSTATEN));
+ mcinfo("SYSCTL: %08x PRSSTAT: %08x IRQSTATEN: %08x\n",
+ getreg32(KINETIS_SDHC_SYSCTL), getreg32(KINETIS_SDHC_PRSSTAT),
+ getreg32(KINETIS_SDHC_IRQSTATEN));
/* The next phase of the hardware reset would be to set the SYSCTRL INITA
* bit to send 80 clock ticks for card to power up and then reset the card
@@ -1504,7 +1502,7 @@ static void kinetis_frequency(FAR struct sdio_dev_s *dev, uint32_t frequency)
regval |= (SDHC_SYSCTL_SDCLKEN | SDHC_SYSCTL_PEREN | SDHC_SYSCTL_HCKEN |
SDHC_SYSCTL_IPGEN);
putreg32(regval, KINETIS_SDHC_SYSCTL);
- fvdbg("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
+ mcinfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
}
#endif
@@ -1538,7 +1536,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
regval = getreg32(KINETIS_SDHC_SYSCTL);
regval &= ~SDHC_SYSCTL_SDCLKEN;
putreg32(regval, KINETIS_SDHC_SYSCTL);
- fvdbg("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
+ mcinfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
switch (rate)
{
@@ -1552,7 +1550,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
regval &= ~(SDHC_SYSCTL_IPGEN | SDHC_SYSCTL_HCKEN | SDHC_SYSCTL_PEREN |
SDHC_SYSCTL_SDCLKFS_MASK | SDHC_SYSCTL_DVS_MASK);
putreg32(regval, KINETIS_SDHC_SYSCTL);
- fvdbg("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
+ mcinfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
return;
}
@@ -1593,7 +1591,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
regval = getreg32(KINETIS_SDHC_SYSCTL);
regval &= ~SDHC_SYSCTL_SDCLKEN;
putreg32(regval, KINETIS_SDHC_SYSCTL);
- fvdbg("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
+ mcinfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
/* Clear the old prescaler and divisor values so that new ones can be ORed
* in.
@@ -1619,7 +1617,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
regval &= ~(SDHC_SYSCTL_IPGEN | SDHC_SYSCTL_HCKEN | SDHC_SYSCTL_PEREN);
putreg32(regval, KINETIS_SDHC_SYSCTL);
- fvdbg("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
+ mcinfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
return;
}
@@ -1653,7 +1651,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
}
putreg32(regval, KINETIS_SDHC_SYSCTL);
- fvdbg("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
+ mcinfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL));
}
#endif
@@ -1824,7 +1822,7 @@ static int kinetis_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t ar
/* Other bits? What about CMDTYP? */
- fvdbg("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
+ mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
/* The Command Inhibit (CIHB) bit is set in the PRSSTAT bit immediately
* after the transfer type register is written. This bit is cleared when
@@ -1840,8 +1838,8 @@ static int kinetis_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t ar
{
if (--timeout <= 0)
{
- fdbg("ERROR: Timeout cmd: %08x PRSSTAT: %08x\n",
- cmd, getreg32(KINETIS_SDHC_PRSSTAT));
+ mcerr("ERROR: Timeout cmd: %08x PRSSTAT: %08x\n",
+ cmd, getreg32(KINETIS_SDHC_PRSSTAT));
return -EBUSY;
}
@@ -2079,8 +2077,8 @@ static int kinetis_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
{
if (--timeout <= 0)
{
- fdbg("ERROR: Timeout cmd: %08x IRQSTAT: %08x\n",
- cmd, getreg32(KINETIS_SDHC_IRQSTAT));
+ mcerr("ERROR: Timeout cmd: %08x IRQSTAT: %08x\n",
+ cmd, getreg32(KINETIS_SDHC_IRQSTAT));
return -ETIMEDOUT;
}
@@ -2090,8 +2088,8 @@ static int kinetis_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
if ((getreg32(KINETIS_SDHC_IRQSTAT) & errors) != 0)
{
- fdbg("ERROR: cmd: %08x errors: %08x IRQSTAT: %08x\n",
- cmd, errors, getreg32(KINETIS_SDHC_IRQSTAT));
+ mcerr("ERROR: cmd: %08x errors: %08x IRQSTAT: %08x\n",
+ cmd, errors, getreg32(KINETIS_SDHC_IRQSTAT));
ret = -EIO;
}
@@ -2152,10 +2150,10 @@ static int kinetis_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd,
*/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!rshort)
{
- fdbg("ERROR: rshort=NULL\n");
+ mcerr("ERROR: rshort=NULL\n");
ret = -EINVAL;
}
@@ -2165,7 +2163,7 @@ static int kinetis_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd,
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1B_RESPONSE &&
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE)
{
- fdbg("ERROR: Wrong response CMD=%08x\n", cmd);
+ mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
ret = -EINVAL;
}
else
@@ -2176,12 +2174,12 @@ static int kinetis_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd,
regval = getreg32(KINETIS_SDHC_IRQSTAT);
if ((regval & SDHC_INT_CTOE) != 0)
{
- fdbg("ERROR: Command timeout: %08x\n", regval);
+ mcerr("ERROR: Command timeout: %08x\n", regval);
ret = -ETIMEDOUT;
}
else if ((regval & SDHC_INT_CCE) != 0)
{
- fdbg("ERROR: CRC failure: %08x\n", regval);
+ mcerr("ERROR: CRC failure: %08x\n", regval);
ret = -EIO;
}
}
@@ -2209,12 +2207,12 @@ static int kinetis_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t r
* 0 1 End bit
*/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
/* Check that R1 is the correct response to this command */
if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE)
{
- fdbg("ERROR: Wrong response CMD=%08x\n", cmd);
+ mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
ret = -EINVAL;
}
else
@@ -2225,12 +2223,12 @@ static int kinetis_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t r
regval = getreg32(KINETIS_SDHC_IRQSTAT);
if (regval & SDHC_INT_CTOE)
{
- fdbg("ERROR: Timeout IRQSTAT: %08x\n", regval);
+ mcerr("ERROR: Timeout IRQSTAT: %08x\n", regval);
ret = -ETIMEDOUT;
}
else if (regval & SDHC_INT_CCE)
{
- fdbg("ERROR: CRC fail IRQSTAT: %08x\n", regval);
+ mcerr("ERROR: CRC fail IRQSTAT: %08x\n", regval);
ret = -EIO;
}
}
@@ -2263,11 +2261,11 @@ static int kinetis_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
/* Check that this is the correct response to this command */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE &&
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE)
{
- fdbg("ERROR: Wrong response CMD=%08x\n", cmd);
+ mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
ret = -EINVAL;
}
else
@@ -2280,7 +2278,7 @@ static int kinetis_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
regval = getreg32(KINETIS_SDHC_IRQSTAT);
if (regval & SDHC_INT_CTOE)
{
- fdbg("ERROR: Timeout IRQSTAT: %08x\n", regval);
+ mcerr("ERROR: Timeout IRQSTAT: %08x\n", regval);
ret = -ETIMEDOUT;
}
}
@@ -2416,7 +2414,7 @@ static sdio_eventset_t kinetis_eventwait(FAR struct sdio_dev_s *dev,
1, (uint32_t)priv);
if (ret != OK)
{
- fdbg("ERROR: wd_start failed: %d\n", ret);
+ mcerr("ERROR: wd_start failed: %d\n", ret);
}
}
@@ -2486,7 +2484,7 @@ static void kinetis_callbackenable(FAR struct sdio_dev_s *dev,
{
struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev;
- fvdbg("eventset: %02x\n", eventset);
+ mcinfo("eventset: %02x\n", eventset);
DEBUGASSERT(priv != NULL);
priv->cbevents = eventset;
@@ -2522,7 +2520,7 @@ static int kinetis_registercallback(FAR struct sdio_dev_s *dev,
/* Disable callbacks and register this callback and is argument */
- fvdbg("Register %p(%p)\n", callback, arg);
+ mcinfo("Register %p(%p)\n", callback, arg);
DEBUGASSERT(priv != NULL);
priv->cbevents = 0;
@@ -2694,8 +2692,8 @@ static void kinetis_callback(void *arg)
/* Is a callback registered? */
DEBUGASSERT(priv != NULL);
- fvdbg("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
- priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
+ mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
+ priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
if (priv->callback)
{
@@ -2739,14 +2737,14 @@ static void kinetis_callback(void *arg)
{
/* Yes.. queue it */
- fvdbg("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
+ mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
(void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
}
else
{
/* No.. then just call the callback here */
- fvdbg("Callback to %p(%p)\n", priv->callback, priv->cbarg);
+ mcinfo("Callback to %p(%p)\n", priv->callback, priv->cbarg);
priv->callback(priv->cbarg);
}
}
@@ -2792,7 +2790,7 @@ FAR struct sdio_dev_s *sdhc_initialize(int slotno)
regval = getreg32(KINETIS_SIM_SCGC3);
regval |= SIM_SCGC3_SDHC;
putreg32(regval, KINETIS_SIM_SCGC3);
- fvdbg("SIM_SCGC3: %08x\n", regval);
+ mcinfo("SIM_SCGC3: %08x\n", regval);
/* In addition to the system clock, the SDHC module needs a clock for the
* base for the external card clock. There are four possible sources for
@@ -2808,7 +2806,7 @@ FAR struct sdio_dev_s *sdhc_initialize(int slotno)
regval &= ~SIM_SOPT2_SDHCSRC_MASK;
regval |= SIM_SOPT2_SDHCSRC_CORE;
putreg32(regval, KINETIS_SIM_SOPT2);
- fvdbg("SIM_SOPT2: %08x\n", regval);
+ mcinfo("SIM_SOPT2: %08x\n", regval);
/* Configure pins for 1 or 4-bit, wide-bus operation (the chip is capable
* of 8-bit wide bus operation but D4-D7 are not configured).
@@ -2892,7 +2890,7 @@ void sdhc_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
priv->cdstatus &= ~SDIO_STATUS_PRESENT;
}
- fvdbg("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
+ mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
/* Perform any requested callback if the status has changed */
@@ -2937,7 +2935,7 @@ void sdhc_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED;
}
- fvdbg("cdstatus: %02x\n", priv->cdstatus);
+ mcinfo("cdstatus: %02x\n", priv->cdstatus);
leave_critical_section(flags);
}
#endif /* CONFIG_KINETIS_SDHC */
diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c
index 550ff55917d5a613f893164ea9a74ba147e4f219..d47235ba90b8055f2217be0b0b18b3293e3a2b3b 100644
--- a/arch/arm/src/kinetis/kinetis_serial.c
+++ b/arch/arm/src/kinetis/kinetis_serial.c
@@ -232,7 +232,7 @@ struct up_dev_s
uintptr_t uartbase; /* Base address of UART registers */
uint32_t baud; /* Configured baud */
uint32_t clock; /* Clocking frequency of the UART module */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
uint8_t irqe; /* Error IRQ associated with this UART (for enable) */
#endif
uint8_t irqs; /* Status IRQ associated with this UART (for enable) */
@@ -250,8 +250,8 @@ static int up_setup(struct uart_dev_s *dev);
static void up_shutdown(struct uart_dev_s *dev);
static int up_attach(struct uart_dev_s *dev);
static void up_detach(struct uart_dev_s *dev);
-#ifdef CONFIG_DEBUG
-static int up_interrupte(int irq, void *context);
+#ifdef CONFIG_DEBUG_FEATURES
+static int up_interrupt(int irq, void *context);
#endif
static int up_interrupts(int irq, void *context);
static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
@@ -327,7 +327,7 @@ static struct up_dev_s g_uart0priv =
.uartbase = KINETIS_UART0_BASE,
.clock = BOARD_CORECLK_FREQ,
.baud = CONFIG_UART0_BAUD,
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
.irqe = KINETIS_IRQ_UART0E,
#endif
.irqs = KINETIS_IRQ_UART0S,
@@ -361,7 +361,7 @@ static struct up_dev_s g_uart1priv =
.uartbase = KINETIS_UART1_BASE,
.clock = BOARD_CORECLK_FREQ,
.baud = CONFIG_UART1_BAUD,
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
.irqe = KINETIS_IRQ_UART1E,
#endif
.irqs = KINETIS_IRQ_UART1S,
@@ -395,7 +395,7 @@ static struct up_dev_s g_uart2priv =
.uartbase = KINETIS_UART2_BASE,
.clock = BOARD_BUS_FREQ,
.baud = CONFIG_UART2_BAUD,
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
.irqe = KINETIS_IRQ_UART2E,
#endif
.irqs = KINETIS_IRQ_UART2S,
@@ -429,7 +429,7 @@ static struct up_dev_s g_uart3priv =
.uartbase = KINETIS_UART3_BASE,
.clock = BOARD_BUS_FREQ,
.baud = CONFIG_UART3_BAUD,
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
.irqe = KINETIS_IRQ_UART3E,
#endif
.irqs = KINETIS_IRQ_UART3S,
@@ -463,7 +463,7 @@ static struct up_dev_s g_uart4priv =
.uartbase = KINETIS_UART4_BASE,
.clock = BOARD_BUS_FREQ,
.baud = CONFIG_UART4_BAUD,
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
.irqe = KINETIS_IRQ_UART4E,
#endif
.irqs = KINETIS_IRQ_UART4S,
@@ -497,7 +497,7 @@ static struct up_dev_s g_uart5priv =
.uartbase = KINETIS_UART5_BASE,
.clock = BOARD_BUS_FREQ,
.baud = CONFIG_UART5_BAUD,
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
.irqe = KINETIS_IRQ_UART5E,
#endif
.irqs = KINETIS_IRQ_UART5S,
@@ -626,7 +626,7 @@ static int up_setup(struct uart_dev_s *dev)
/* Set up the interrupt priority */
up_prioritize_irq(priv->irqs, priv->irqprio);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
up_prioritize_irq(priv->irqe, priv->irqprio);
#endif
#endif
@@ -681,16 +681,16 @@ static int up_attach(struct uart_dev_s *dev)
*/
ret = irq_attach(priv->irqs, up_interrupts);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (ret == OK)
{
- ret = irq_attach(priv->irqe, up_interrupte);
+ ret = irq_attach(priv->irqe, up_interrupt);
}
#endif
if (ret == OK)
{
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
up_enable_irq(priv->irqe);
#endif
up_enable_irq(priv->irqs);
@@ -716,7 +716,7 @@ static void up_detach(struct uart_dev_s *dev)
/* Disable interrupts */
up_restoreuartint(priv, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
up_disable_irq(priv->irqe);
#endif
up_disable_irq(priv->irqs);
@@ -724,13 +724,13 @@ static void up_detach(struct uart_dev_s *dev)
/* Detach from the interrupt(s) */
irq_detach(priv->irqs);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
irq_detach(priv->irqe);
#endif
}
/****************************************************************************
- * Name: up_interrupte
+ * Name: up_interrupt
*
* Description:
* This is the UART error interrupt handler. It will be invoked when an
@@ -738,8 +738,8 @@ static void up_detach(struct uart_dev_s *dev)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
-static int up_interrupte(int irq, void *context)
+#ifdef CONFIG_DEBUG_FEATURES
+static int up_interrupt(int irq, void *context)
{
struct uart_dev_s *dev = NULL;
struct up_dev_s *priv;
@@ -790,6 +790,7 @@ static int up_interrupte(int irq, void *context)
{
PANIC();
}
+
priv = (struct up_dev_s *)dev->priv;
DEBUGASSERT(priv);
@@ -804,11 +805,15 @@ static int up_interrupte(int irq, void *context)
*/
regval = up_serialin(priv, KINETIS_UART_S1_OFFSET);
- lldbg("S1: %02x\n", regval);
+ _info("S1: %02x\n", regval);
+ UNUSED(regval);
+
regval = up_serialin(priv, KINETIS_UART_D_OFFSET);
+ UNUSED(regval);
+
return OK;
}
-#endif /* CONFIG_DEBUG */
+#endif /* CONFIG_DEBUG_FEATURES */
/****************************************************************************
* Name: up_interrupts
@@ -1064,7 +1069,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
}
else
{
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
# warning "Revisit: How are errors enabled?"
priv->ie |= UART_C2_RIE;
#else
diff --git a/arch/arm/src/kinetis/kinetis_start.c b/arch/arm/src/kinetis/kinetis_start.c
index f686e77915cedb8a48cf085dbec960fe039c2b26..8de2524ef5600670e156c6369017d490dac20016 100644
--- a/arch/arm/src/kinetis/kinetis_start.c
+++ b/arch/arm/src/kinetis/kinetis_start.c
@@ -156,8 +156,8 @@ void __start(void)
/* Show reset status */
- dbg("Reset status: %02x:%02x\n",
- getreg8(KINETIS_SMC_SRSH), getreg8(KINETIS_SMC_SRSL));
+ _warn("Reset status: %02x:%02x\n",
+ getreg8(KINETIS_SMC_SRSH), getreg8(KINETIS_SMC_SRSL));
/* Then start NuttX */
diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c
new file mode 100644
index 0000000000000000000000000000000000000000..8deedb7603c99ecbd06bf8bd25c39ff9ea4abf85
--- /dev/null
+++ b/arch/arm/src/kinetis/kinetis_usbdev.c
@@ -0,0 +1,4677 @@
+/****************************************************************************
+ * arch/arm/src/kinetis/kinetis_usbdev.c
+ *
+ * Copyright (C) 2011-2014, 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * References:
+ * This file derives from the STM32 USB device driver with modifications
+ * based on additional information from:
+ *
+ * - "USB On-The-Go (OTG)", DS61126E, Microchip Technology Inc., 2009
+ * - Sample code provided with the Sure Electronics PIC32 board
+ * (which seems to have derived from Microchip PICDEM PIC18 code).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "up_arch.h"
+#include "kinetis.h"
+#include "kinetis_usbotg.h"
+#include "kinetis_sim.h"
+#include "kinetis_fmc.h"
+
+#if defined(CONFIG_USBDEV) && defined(CONFIG_KINETIS_USBOTG)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#ifndef CONFIG_USBDEV_EP0_MAXSIZE
+# define CONFIG_USBDEV_EP0_MAXSIZE 64
+#endif
+
+/* Extremely detailed register/BDT debug that you would normally never want
+ * enabled.
+ */
+
+#ifndef CONFIG_DEBUG_USB_INFO
+# undef CONFIG_KHCI_USBDEV_REGDEBUG
+# undef CONFIG_KHCI_USBDEV_BDTDEBUG
+#endif
+
+/* Disable this logic because it is buggy. It works most of the time but
+ * has some lurking issues that keep this higher performance solution from
+ * being usable.
+ */
+
+#undef CONFIG_USBDEV_NOREADAHEAD /* Makes no difference */
+
+#undef CONFIG_USBDEV_NOWRITEAHEAD
+#define CONFIG_USBDEV_NOWRITEAHEAD 1 /* Fixes some problems with IN transfers */
+
+/* Interrupts ***************************************************************/
+/* Initial interrupt sets */
+
+#ifdef CONFIG_USB_SOFINTS
+# define USB_SOF_INTERRUPT USB_INT_SOFTOK
+#else
+# define USB_SOF_INTERRUPT 0
+#endif
+
+#define ERROR_INTERRUPTS (USB_ERRSTAT_PIDERR | USB_ERRSTAT_CRC5EOF | \
+ USB_ERRSTAT_CRC16 | USB_ERRSTAT_DFN8 | USB_ERRSTAT_BTOERR | \
+ USB_ERRSTAT_BTSERR)
+
+#define NORMAL_INTERRUPTS (USB_INT_USBRST | USB_INT_ERROR | USB_SOF_INTERRUPT | \
+ USB_INT_TOKDNE | USB_INT_SLEEP | USB_INT_STALL)
+
+/* Endpoints ****************************************************************/
+
+#define USB_STAT_ENDPT(n) ((n) << USB_STAT_ENDP_SHIFT) /* Endpoint n, n=0..15 */
+
+#define USB_STAT_ODD_ODD USB_STAT_ODD /* The last transaction was to the ODD BD bank */
+#define USB_STAT_ODD_EVEN 0 /* The last transaction was to the EVEN BD bank */
+
+#define USB_STAT_TX_IN USB_STAT_TX /* Last transaction was a transmit transfer (TX) */
+#define USB_STAT_TX_OUT 0 /* Last transaction was a receive transfer (RX) */
+
+#define KHCI_NENDPOINTS (16)
+#define EP0 (0)
+
+#define KHCI_ENDP_BIT(ep) (1 << (ep))
+#define KHCI_ENDP_ALLSET 0xffff
+
+#define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1)
+
+/* BDT Table Indexing. The BDT is addressed in the hardware as follows:
+ *
+ * Bits 9-31: These come the BDT address bits written into the BDTP3,
+ * BDTP2, and BDTP1 registers
+ * Bits 5-8: The endpoint number
+ * Bit 4: Direction:
+ * 1 = Transmit: SETUP/OUT for host, IN for function
+ * 0 = Receive: IN for host, SETUP/OUT for function
+ * Bit 3: PPBI, the ping point buffer index bit (0=EVEN, 1=ODD)
+ * Bits 0-2: Supports 8-byte BDT entries
+ */
+
+#define EP0_OUT_EVEN (0)
+#define EP0_OUT_ODD (1)
+#define EP0_IN_EVEN (2)
+#define EP0_IN_ODD (3)
+#define EP_OUT_EVEN(ep) ((int)(ep) << 2)
+#define EP_OUT_ODD(ep) (((int)(ep) << 2) + 1)
+#define EP_IN_EVEN(ep) (((int)(ep) << 2) + 2)
+#define EP_IN_ODD(ep) (((int)(ep) << 2) + 3)
+
+#define EP(ep,dir,pp) (((int)(ep) << 2) + ((int)(dir) << 1) + (int)(pp))
+#define EP_DIR_OUT 0
+#define EP_DIR_IN 1
+#define EP_PP_EVEN 0
+#define EP_PP_ODD 1
+
+/* Packet sizes. We use a fixed 64 max packet size for all endpoint types */
+
+#define KHCI_MAXPACKET_SHIFT (6)
+#define KHCI_MAXPACKET_SIZE (1 << (KHCI_MAXPACKET_SHIFT))
+
+#define KHCI_EP0MAXPACKET KHCI_MAXPACKET_SIZE
+
+/* Endpoint register initialization parameters */
+
+#define KHCI_EP_CONTROL (USB_ENDPT_EPHSHK | USB_ENDPT_EPTXEN | USB_ENDPT_EPRXEN)
+#define KHCI_EP_BULKIN (USB_ENDPT_EPTXEN | USB_ENDPT_EPCTLDIS | USB_ENDPT_EPHSHK)
+#define KHCI_EP_BULKOUT (USB_ENDPT_EPRXEN | USB_ENDPT_EPCTLDIS | USB_ENDPT_EPHSHK)
+#define KHCI_EP_INTIN (USB_ENDPT_EPTXEN | USB_ENDPT_EPCTLDIS | USB_ENDPT_EPHSHK)
+#define KHCI_EP_INTOUT (USB_ENDPT_EPRXEN | USB_ENDPT_EPCTLDIS | USB_ENDPT_EPHSHK)
+#define KHCI_EP_ISOCIN (USB_ENDPT_EPTXEN | USB_ENDPT_EPCTLDIS)
+#define KHCI_EP_ISOCOUT (USB_ENDPT_EPRXEN | USB_ENDPT_EPCTLDIS)
+
+/* USB-related masks */
+
+#define REQRECIPIENT_MASK (USB_REQ_TYPE_MASK | USB_REQ_RECIPIENT_MASK)
+
+/* Request queue operations *************************************************/
+
+#define khci_rqempty(q) ((q)->head == NULL)
+#define khci_rqhead(q) ((q)->head)
+#define khci_rqtail(q) ((q)->tail)
+
+#define RESTART_DELAY (150 * CLOCKS_PER_SEC / 1000)
+
+/* USB trace ****************************************************************/
+/* Trace error codes */
+
+#define KHCI_TRACEERR_ALLOCFAIL 0x0001
+#define KHCI_TRACEERR_BADCLEARFEATURE 0x0002
+#define KHCI_TRACEERR_BADDEVGETSTATUS 0x0003
+#define KHCI_TRACEERR_BADEPGETSTATUS 0x0004
+#define KHCI_TRACEERR_BADEPNO 0x0005
+#define KHCI_TRACEERR_BADEPTYPE 0x0006
+#define KHCI_TRACEERR_BADGETCONFIG 0x0007
+#define KHCI_TRACEERR_BADGETSETDESC 0x0008
+#define KHCI_TRACEERR_BADGETSTATUS 0x0009
+#define KHCI_TRACEERR_BADSETADDRESS 0x000a
+#define KHCI_TRACEERR_BADSETCONFIG 0x000b
+#define KHCI_TRACEERR_BADSETFEATURE 0x000c
+#define KHCI_TRACEERR_BINDFAILED 0x000d
+#define KHCI_TRACEERR_DISPATCHSTALL 0x000e
+#define KHCI_TRACEERR_DRIVER 0x000f
+#define KHCI_TRACEERR_DRIVERREGISTERED 0x0010
+#define KHCI_TRACEERR_EP0SETUPSTALLED 0x0011
+#define KHCI_TRACEERR_EPDISABLED 0x0012
+#define KHCI_TRACEERR_EPOUTNULLPACKET 0x0013
+#define KHCI_TRACEERR_EPRESERVE 0x0014
+#define KHCI_TRACEERR_INVALIDCTRLREQ 0x0015
+#define KHCI_TRACEERR_INVALIDPARMS 0x0016
+#define KHCI_TRACEERR_IRQREGISTRATION 0x0017
+#define KHCI_TRACEERR_NOTCONFIGURED 0x0018
+#define KHCI_TRACEERR_REQABORTED 0x0019
+#define KHCI_TRACEERR_INVALIDSTATE 0x001a
+
+/* Trace interrupt codes */
+
+#define KHCI_TRACEINTID_CLEARFEATURE 0x0001
+#define KHCI_TRACEINTID_DEVGETSTATUS 0x0002
+#define KHCI_TRACEINTID_DISPATCH 0x0003
+#define KHCI_TRACEINTID_EP0IN 0x0004
+#define KHCI_TRACEINTID_EP0INDONE 0x0005
+#define KHCI_TRACEINTID_EP0OUTDONE 0x0006
+#define KHCI_TRACEINTID_EP0SETUPDONE 0x0007
+#define KHCI_TRACEINTID_EP0SETUPSETADDRESS 0x0008
+#define KHCI_TRACEINTID_EP0ADDRESSSET 0x0009
+#define KHCI_TRACEINTID_EPGETSTATUS 0x000a
+#define KHCI_TRACEINTID_EPINDONE 0x000b
+#define KHCI_TRACEINTID_EPINQEMPTY 0x000c
+#define KHCI_TRACEINTID_EPOUTDONE 0x000d
+#define KHCI_TRACEINTID_EPOUTQEMPTY 0x000e
+#define KHCI_TRACEINTID_SOF 0x000f
+#define KHCI_TRACEINTID_GETCONFIG 0x0010
+#define KHCI_TRACEINTID_GETSETDESC 0x0011
+#define KHCI_TRACEINTID_GETSETIF 0x0012
+#define KHCI_TRACEINTID_GETSTATUS 0x0013
+#define KHCI_TRACEINTID_IFGETSTATUS 0x0014
+#define KHCI_TRACEINTID_TRNC 0x0015
+#define KHCI_TRACEINTID_TRNCS 0x0016
+#define KHCI_TRACEINTID_INTERRUPT 0x0017
+#define KHCI_TRACEINTID_NOSTDREQ 0x0018
+#define KHCI_TRACEINTID_RESET 0x0019
+#define KHCI_TRACEINTID_SETCONFIG 0x001a
+#define KHCI_TRACEINTID_SETFEATURE 0x001b
+#define KHCI_TRACEINTID_IDLE 0x001c
+#define KHCI_TRACEINTID_SYNCHFRAME 0x001d
+#define KHCI_TRACEINTID_WKUP 0x001e
+#define KHCI_TRACEINTID_T1MSEC 0x001f
+#define KHCI_TRACEINTID_OTGID 0x0020
+#define KHCI_TRACEINTID_STALL 0x0021
+#define KHCI_TRACEINTID_UERR 0x0022
+#define KHCI_TRACEINTID_SUSPENDED 0x0023
+#define KHCI_TRACEINTID_WAITRESET 0x0024
+
+#ifdef CONFIG_USBDEV_TRACE_STRINGS
+const struct trace_msg_t g_usb_trace_strings_intdecode[] =
+{
+ TRACE_STR(KHCI_TRACEINTID_CLEARFEATURE ), /* 0x0001 */
+ TRACE_STR(KHCI_TRACEINTID_DEVGETSTATUS ), /* 0x0002 */
+ TRACE_STR(KHCI_TRACEINTID_DISPATCH ), /* 0x0003 */
+ TRACE_STR(KHCI_TRACEINTID_EP0IN ), /* 0x0004 */
+ TRACE_STR(KHCI_TRACEINTID_EP0INDONE ), /* 0x0005 */
+ TRACE_STR(KHCI_TRACEINTID_EP0OUTDONE ), /* 0x0006 */
+ TRACE_STR(KHCI_TRACEINTID_EP0SETUPDONE ), /* 0x0007 */
+ TRACE_STR(KHCI_TRACEINTID_EP0SETUPSETADDRESS ), /* 0x0008 */
+ TRACE_STR(KHCI_TRACEINTID_EP0ADDRESSSET ), /* 0x0009 */
+ TRACE_STR(KHCI_TRACEINTID_EPGETSTATUS ), /* 0x000a */
+ TRACE_STR(KHCI_TRACEINTID_EPINDONE ), /* 0x000b */
+ TRACE_STR(KHCI_TRACEINTID_EPINQEMPTY ), /* 0x000c */
+ TRACE_STR(KHCI_TRACEINTID_EPOUTDONE ), /* 0x000d */
+ TRACE_STR(KHCI_TRACEINTID_EPOUTQEMPTY ), /* 0x000e */
+ TRACE_STR(KHCI_TRACEINTID_SOF ), /* 0x000f */
+ TRACE_STR(KHCI_TRACEINTID_GETCONFIG ), /* 0x0010 */
+ TRACE_STR(KHCI_TRACEINTID_GETSETDESC ), /* 0x0011 */
+ TRACE_STR(KHCI_TRACEINTID_GETSETIF ), /* 0x0012 */
+ TRACE_STR(KHCI_TRACEINTID_GETSTATUS ), /* 0x0013 */
+ TRACE_STR(KHCI_TRACEINTID_IFGETSTATUS ), /* 0x0014 */
+ TRACE_STR(KHCI_TRACEINTID_TRNC ), /* 0x0015 */
+ TRACE_STR(KHCI_TRACEINTID_TRNCS ), /* 0x0016 */
+ TRACE_STR(KHCI_TRACEINTID_INTERRUPT ), /* 0x0017 */
+ TRACE_STR(KHCI_TRACEINTID_NOSTDREQ ), /* 0x0018 */
+ TRACE_STR(KHCI_TRACEINTID_RESET ), /* 0x0019 */
+ TRACE_STR(KHCI_TRACEINTID_SETCONFIG ), /* 0x001a */
+ TRACE_STR(KHCI_TRACEINTID_SETFEATURE ), /* 0x001b */
+ TRACE_STR(KHCI_TRACEINTID_IDLE ), /* 0x001c */
+ TRACE_STR(KHCI_TRACEINTID_SYNCHFRAME ), /* 0x001d */
+ TRACE_STR(KHCI_TRACEINTID_WKUP ), /* 0x001e */
+ TRACE_STR(KHCI_TRACEINTID_T1MSEC ), /* 0x001f */
+ TRACE_STR(KHCI_TRACEINTID_OTGID ), /* 0x0020 */
+ TRACE_STR(KHCI_TRACEINTID_STALL ), /* 0x0021 */
+ TRACE_STR(KHCI_TRACEINTID_UERR ), /* 0x0022 */
+ TRACE_STR(KHCI_TRACEINTID_SUSPENDED ), /* 0x0023 */
+ TRACE_STR(KHCI_TRACEINTID_WAITRESET ), /* 0x0024 */
+ TRACE_STR_END
+};
+#endif
+
+#ifdef CONFIG_USBDEV_TRACE_STRINGS
+const struct trace_msg_t g_usb_trace_strings_deverror[] =
+{
+ TRACE_STR(KHCI_TRACEERR_ALLOCFAIL ), /* 0x0001 */
+ TRACE_STR(KHCI_TRACEERR_BADCLEARFEATURE ), /* 0x0002 */
+ TRACE_STR(KHCI_TRACEERR_BADDEVGETSTATUS ), /* 0x0003 */
+ TRACE_STR(KHCI_TRACEERR_BADEPGETSTATUS ), /* 0x0004 */
+ TRACE_STR(KHCI_TRACEERR_BADEPNO ), /* 0x0005 */
+ TRACE_STR(KHCI_TRACEERR_BADEPTYPE ), /* 0x0006 */
+ TRACE_STR(KHCI_TRACEERR_BADGETCONFIG ), /* 0x0007 */
+ TRACE_STR(KHCI_TRACEERR_BADGETSETDESC ), /* 0x0008 */
+ TRACE_STR(KHCI_TRACEERR_BADGETSTATUS ), /* 0x0009 */
+ TRACE_STR(KHCI_TRACEERR_BADSETADDRESS ), /* 0x000a */
+ TRACE_STR(KHCI_TRACEERR_BADSETCONFIG ), /* 0x000b */
+ TRACE_STR(KHCI_TRACEERR_BADSETFEATURE ), /* 0x000c */
+ TRACE_STR(KHCI_TRACEERR_BINDFAILED ), /* 0x000d */
+ TRACE_STR(KHCI_TRACEERR_DISPATCHSTALL ), /* 0x000e */
+ TRACE_STR(KHCI_TRACEERR_DRIVER ), /* 0x000f */
+ TRACE_STR(KHCI_TRACEERR_DRIVERREGISTERED ), /* 0x0010 */
+ TRACE_STR(KHCI_TRACEERR_EP0SETUPSTALLED ), /* 0x0011 */
+ TRACE_STR(KHCI_TRACEERR_EPDISABLED ), /* 0x0012 */
+ TRACE_STR(KHCI_TRACEERR_EPOUTNULLPACKET ), /* 0x0013 */
+ TRACE_STR(KHCI_TRACEERR_EPRESERVE ), /* 0x0014 */
+ TRACE_STR(KHCI_TRACEERR_INVALIDCTRLREQ ), /* 0x0015 */
+ TRACE_STR(KHCI_TRACEERR_INVALIDPARMS ), /* 0x0016 */
+ TRACE_STR(KHCI_TRACEERR_IRQREGISTRATION ), /* 0x0017 */
+ TRACE_STR(KHCI_TRACEERR_NOTCONFIGURED ), /* 0x0018 */
+ TRACE_STR(KHCI_TRACEERR_REQABORTED ), /* 0x0019 */
+ TRACE_STR(KHCI_TRACEERR_INVALIDSTATE ), /* 0x001a */
+ TRACE_STR_END
+};
+#endif
+
+/* Misc Helper Macros *******************************************************/
+
+/* Ever-present MIN and MAX macros */
+
+#ifndef MIN
+# define MIN(a,b) (a < b ? a : b)
+#endif
+
+#ifndef MAX
+# define MAX(a,b) (a > b ? a : b)
+#endif
+
+/* Byte ordering in host-based values */
+
+#ifdef CONFIG_ENDIAN_BIG
+# define LSB 1
+# define MSB 0
+#else
+# define LSB 0
+# define MSB 1
+#endif
+
+/* Debug ********************************************************************/
+/* CONFIG_KHCI_USBDEV_REGDEBUG enables dumping of all low-level register
+ * access and BDT accesses. Normally, this generates so much debug output
+ * that USB may not even be functional.
+ */
+
+#ifdef CONFIG_KHCI_USBDEV_REGDEBUG
+# undef CONFIG_KHCI_USBDEV_BDTDEBUG
+# define CONFIG_KHCI_USBDEV_BDTDEBUG 1
+#else
+# define khci_getreg(addr) getreg8(addr)
+# define khci_putreg(val,addr) putreg8(val,addr)
+#endif
+
+/* CONFIG_KHCI_USBDEV_BDTDEBUG dumps most BDT settings */
+
+#ifdef CONFIG_KHCI_USBDEV_BDTDEBUG
+# define bdterr uerr
+# define bdtinfo uinfo
+#else
+# define bdterr(x...)
+# define bdtinfo(x...)
+#endif
+
+/****************************************************************************
+ * Private Type Definitions
+ ****************************************************************************/
+
+/* Overvall device state */
+
+enum khci_devstate_e
+{
+ DEVSTATE_DETACHED = 0, /* Not connected to a host */
+ DEVSTATE_ATTACHED, /* Connected to a host */
+ DEVSTATE_POWERED, /* Powered */
+ DEVSTATE_DEFAULT, /* Default state */
+ DEVSTATE_ADDRPENDING, /* Waiting for an address */
+ DEVSTATE_ADDRESS, /* Address received */
+ DEVSTATE_CONFIGURED, /* Configuration received */
+};
+
+/* The various states of the control pipe */
+
+enum khci_ctrlstate_e
+{
+ CTRLSTATE_WAITSETUP = 0, /* No request in progress, waiting for setup */
+ CTRLSTATE_RDREQUEST, /* Read request (OUT) in progress */
+ CTRLSTATE_WRREQUEST, /* Write request (IN) in progress */
+ CTRLSTATE_STALL, /* EP0 stall requested */
+ CTRLSTATE_STALLED /* EP0 is stalled */
+};
+
+union wb_u
+{
+ uint16_t w;
+ uint8_t b[2];
+};
+
+/* A container for a request so that the request make be retained in a
+ * singly-linked list.
+ */
+
+struct khci_req_s
+{
+ struct usbdev_req_s req; /* Standard USB request */
+#ifdef CONFIG_USBDEV_NOWRITEAHEAD
+ uint16_t inflight[1]; /* The number of bytes "in-flight" */
+#else
+ uint16_t inflight[2]; /* The number of bytes "in-flight" */
+#endif
+ struct khci_req_s *flink; /* Supports a singly linked list */
+};
+
+/* This structure represents the 'head' of a singly linked list of requests */
+
+struct khci_queue_s
+{
+ struct khci_req_s *head; /* Head of the request queue */
+ struct khci_req_s *tail; /* Tail of the request queue */
+};
+
+/* This is the internal representation of an endpoint */
+
+struct khci_ep_s
+{
+ /* Common endpoint fields. This must be the first thing defined in the
+ * structure so that it is possible to simply cast from struct usbdev_ep_s
+ * to struct khci_ep_s.
+ */
+
+ struct usbdev_ep_s ep; /* Standard endpoint structure */
+
+ /* KHCI-specific fields */
+
+ struct khci_usbdev_s *dev; /* Reference to private driver data */
+ struct khci_queue_s pend; /* List of pending (inactive) requests for this endpoint */
+ struct khci_queue_s active; /* List of active requests for this endpoint */
+ uint8_t stalled:1; /* true: Endpoint is stalled */
+ uint8_t halted:1; /* true: Endpoint feature halted */
+ uint8_t txnullpkt:1; /* Null packet needed at end of TX transfer */
+ uint8_t txdata1:1; /* Data0/1 of next TX transfer */
+ uint8_t rxdata1:1; /* Data0/1 of next RX transfer */
+ volatile struct usbotg_bdtentry_s *bdtin; /* BDT entry for the IN transaction */
+ volatile struct usbotg_bdtentry_s *bdtout; /* BDT entry for the OUT transaction */
+};
+
+struct khci_usbdev_s
+{
+ /* Common device fields. This must be the first thing defined in the
+ * structure so that it is possible to simply cast from struct usbdev_s
+ * to structkhci_usbdev_s.
+ */
+
+ struct usbdev_s usbdev;
+
+ /* The bound device class driver */
+
+ struct usbdevclass_driver_s *driver;
+
+ /* KHCI-specific fields */
+
+ struct usb_ctrlreq_s ctrl; /* Last EP0 request */
+ uint8_t devstate; /* Driver state (see enum khci_devstate_e) */
+ uint8_t ctrlstate; /* Control EP state (see enum khci_ctrlstate_e) */
+ uint8_t selfpowered:1; /* 1: Device is self powered */
+ uint8_t rwakeup:1; /* 1: Device supports remote wakeup */
+ uint8_t attached:1; /* Device is attached to the host */
+ uint8_t ep0done:1; /* EP0 OUT already prepared */
+ uint8_t rxbusy:1; /* EP0 OUT data transfer in progress */
+ uint16_t epavail; /* Bitset of available endpoints */
+ uint16_t epstalled; /* Bitset of stalled endpoints */
+ WDOG_ID wdog; /* Supports the restart delay */
+
+ /* The endpoint list */
+
+ struct khci_ep_s eplist[KHCI_NENDPOINTS];
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Register operations ******************************************************/
+
+#ifdef CONFIG_KHCI_USBDEV_REGDEBUG
+static uint16_t khci_getreg(uint32_t addr);
+static void khci_putreg(uint32_t val, uint32_t addr);
+#endif
+
+/* Suspend/Resume Helpers ***************************************************/
+
+static void khci_suspend(struct khci_usbdev_s *priv);
+static void khci_resume(struct khci_usbdev_s *priv);
+
+/* Request Queue Management *************************************************/
+
+static struct khci_req_s *khci_remfirst(struct khci_queue_s *queue);
+static struct khci_req_s *khci_remlast(struct khci_queue_s *queue);
+static void khci_addlast(struct khci_queue_s *queue,
+ struct khci_req_s *req);
+static void khci_addfirst(struct khci_queue_s *queue,
+ struct khci_req_s *req);
+
+/* Request Helpers **********************************************************/
+
+static void khci_reqreturn(struct khci_ep_s *privep,
+ struct khci_req_s *privreq, int16_t result);
+static void khci_reqcomplete(struct khci_ep_s *privep,
+ int16_t result);
+static void khci_epwrite(struct khci_ep_s *privep,
+ volatile struct usbotg_bdtentry_s *bdt,
+ const uint8_t *src, uint32_t nbytes);
+static void khci_wrcomplete(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep);
+static void khci_rqrestart(int argc, uint32_t arg1, ...);
+static void khci_delayedrestart(struct khci_usbdev_s *priv,
+ uint8_t epno);
+static void khci_rqstop(struct khci_ep_s *privep);
+static int khci_wrstart(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep);
+static int khci_wrrequest(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep);
+static int khci_rdcomplete(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep);
+static int khci_ep0rdsetup(struct khci_usbdev_s *priv,
+ uint8_t *dest, int readlen);
+static int khci_rdsetup(struct khci_ep_s *privep, uint8_t *dest,
+ int readlen);
+static int khci_rdrequest(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep);
+static void khci_cancelrequests(struct khci_ep_s *privep,
+ int16_t result);
+
+/* Interrupt level processing ***********************************************/
+
+static void khci_dispatchrequest(struct khci_usbdev_s *priv);
+static void khci_ep0stall(struct khci_usbdev_s *priv);
+static void khci_eptransfer(struct khci_usbdev_s *priv, uint8_t epno,
+ uint16_t ustat);
+static void khci_ep0nextsetup(struct khci_usbdev_s *priv);
+static void khci_ep0rdcomplete(struct khci_usbdev_s *priv);
+static void khci_ep0setup(struct khci_usbdev_s *priv);
+static void khci_ep0outcomplete(struct khci_usbdev_s *priv);
+static void khci_ep0incomplete(struct khci_usbdev_s *priv);
+static void khci_ep0transfer(struct khci_usbdev_s *priv,
+ uint16_t ustat);
+static int khci_interrupt(int irq, void *context);
+
+/* Endpoint helpers *********************************************************/
+
+static inline struct khci_ep_s *
+ khci_epreserve(struct khci_usbdev_s *priv, uint8_t epset);
+static inline void
+ khci_epunreserve(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep);
+static inline bool
+ khci_epreserved(struct khci_usbdev_s *priv, int epno);
+static void khci_ep0configure(struct khci_usbdev_s *priv);
+
+/* Endpoint operations ******************************************************/
+
+static int khci_epconfigure(struct usbdev_ep_s *ep,
+ const struct usb_epdesc_s *desc, bool last);
+static int khci_epdisable(struct usbdev_ep_s *ep);
+static struct usbdev_req_s *
+ khci_epallocreq(struct usbdev_ep_s *ep);
+static void khci_epfreereq(struct usbdev_ep_s *ep,
+ struct usbdev_req_s *);
+static int khci_epsubmit(struct usbdev_ep_s *ep,
+ struct usbdev_req_s *req);
+static int khci_epcancel(struct usbdev_ep_s *ep,
+ struct usbdev_req_s *req);
+static int khci_epbdtstall(struct usbdev_ep_s *ep, bool resume,
+ bool epin);
+static int khci_epstall(struct usbdev_ep_s *ep, bool resume);
+
+/* USB device controller operations *****************************************/
+
+static struct usbdev_ep_s *
+ khci_allocep(struct usbdev_s *dev, uint8_t epno, bool in,
+ uint8_t eptype);
+static void khci_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep);
+static int khci_getframe(struct usbdev_s *dev);
+static int khci_wakeup(struct usbdev_s *dev);
+static int khci_selfpowered(struct usbdev_s *dev, bool selfpowered);
+
+/* Initialization/Reset *****************************************************/
+
+static void khci_reset(struct khci_usbdev_s *priv);
+static void khci_attach(struct khci_usbdev_s *priv);
+static void khci_detach(struct khci_usbdev_s *priv);
+static void khci_swreset(struct khci_usbdev_s *priv);
+static void khci_hwreset(struct khci_usbdev_s *priv);
+static void khci_stateinit(struct khci_usbdev_s *priv);
+static void khci_hwshutdown(struct khci_usbdev_s *priv);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Since there is only a single USB interface, all status information can be
+ * be simply retained in a single global instance.
+ */
+
+static struct khci_usbdev_s g_usbdev;
+
+static const struct usbdev_epops_s g_epops =
+{
+ .configure = khci_epconfigure,
+ .disable = khci_epdisable,
+ .allocreq = khci_epallocreq,
+ .freereq = khci_epfreereq,
+ .submit = khci_epsubmit,
+ .cancel = khci_epcancel,
+ .stall = khci_epstall,
+};
+
+static const struct usbdev_ops_s g_devops =
+{
+ .allocep = khci_allocep,
+ .freeep = khci_freeep,
+ .getframe = khci_getframe,
+ .wakeup = khci_wakeup,
+ .selfpowered = khci_selfpowered,
+ .pullup = kinetis_usbpullup,
+};
+
+/* Buffer Descriptor Table. Four BDT entries per endpoint
+ *
+ * The BDT is addressed in the hardware as follows:
+ *
+ * Bits 9-31: These come the BDT address bits written into the BDTP3, BDTP2
+ * and BDTP1 registers
+ * Bits 5-8: The endpoint number
+ * Bit 4: Direction (0=IN/Tx, 1 = OUT/Rx)
+ * Bit 3: PPBI, the ping point buffer index bit.
+ * Bits 0-2: Supports 8-byte BDT entries
+ */
+
+static volatile struct usbotg_bdtentry_s g_bdt[4*KHCI_NENDPOINTS]
+ __attribute__ ((aligned(512)));
+
+/****************************************************************************
+ * Private Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Register Operations
+ ****************************************************************************/
+
+ /****************************************************************************
+ * Name: khci_getreg
+ ****************************************************************************/
+
+#ifdef CONFIG_KHCI_USBDEV_REGDEBUG
+static uint16_t khci_getreg(uint32_t addr)
+{
+ static uint32_t prevaddr = 0;
+ static uint32_t preval = 0;
+ static uint32_t count = 0;
+
+ /* Read the value from the register */
+
+ uint16_t val = getreg8(addr);
+
+ /* Is this the same value that we read from the same register last time?
+ * Are we polling the register? If so, suppress some of the output.
+ */
+
+ if (addr == prevaddr && val == preval)
+ {
+ if (count == 0xffffffff || ++count > 3)
+ {
+ if (count == 4)
+ {
+ uinfo("...\n");
+ }
+ return val;
+ }
+ }
+
+ /* No this is a new address or value */
+
+ else
+ {
+ /* Did we print "..." for the previous value? */
+
+ if (count > 3)
+ {
+ /* Yes.. then show how many times the value repeated */
+
+ uinfo("[repeats %d more times]\n", count-3);
+ }
+
+ /* Save the new address, value, and count */
+
+ prevaddr = addr;
+ preval = val;
+ count = 1;
+ }
+
+ /* Show the register value read */
+
+ uinfo("%08x->%04x\n", addr, val);
+ return val;
+}
+#endif
+
+/****************************************************************************
+ * Name: khci_putreg
+ ****************************************************************************/
+
+#ifdef CONFIG_KHCI_USBDEV_REGDEBUG
+static void khci_putreg(uint32_t val, uint32_t addr)
+{
+ /* Show the register value being written */
+
+ uinfo("%08x<-%04x\n", addr, val);
+
+ /* Write the value */
+
+ putreg8(val, addr);
+}
+#endif
+
+/****************************************************************************
+ * Request Helpers
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: khci_remfirst
+ ****************************************************************************/
+
+static struct khci_req_s *khci_remfirst(struct khci_queue_s *queue)
+{
+ struct khci_req_s *ret = queue->head;
+
+ if (ret)
+ {
+ queue->head = ret->flink;
+ if (!queue->head)
+ {
+ queue->tail = NULL;
+ }
+
+ ret->flink = NULL;
+ }
+
+ return ret;
+}
+
+
+/****************************************************************************
+ * Name: khci_remlast
+ ****************************************************************************/
+
+static struct khci_req_s *khci_remlast(struct khci_queue_s *queue)
+{
+ struct khci_req_s *prev;
+ struct khci_req_s *ret = queue->tail;
+
+ ret = queue->tail;
+ if (ret)
+ {
+ if (queue->head == queue->tail)
+ {
+ queue->head = NULL;
+ queue->tail = NULL;
+ }
+ else
+ {
+ for (prev = queue->head;
+ prev && prev->flink != ret;
+ prev = prev->flink);
+
+ if (prev)
+ {
+ prev->flink = NULL;
+ queue->tail = prev;
+ }
+ }
+
+ ret->flink = NULL;
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: khci_addlast
+ ****************************************************************************/
+
+static void khci_addlast(struct khci_queue_s *queue, struct khci_req_s *req)
+{
+ req->flink = NULL;
+ if (!queue->head)
+ {
+ queue->head = req;
+ queue->tail = req;
+ }
+ else
+ {
+ queue->tail->flink = req;
+ queue->tail = req;
+ }
+}
+
+/****************************************************************************
+ * Name: khci_addfirst
+ ****************************************************************************/
+
+static void khci_addfirst(struct khci_queue_s *queue, struct khci_req_s *req)
+{
+ req->flink = queue->head;
+ if (!queue->head)
+ {
+ queue->tail = req;
+ }
+
+ queue->head = req;
+}
+
+/****************************************************************************
+ * Name: khci_reqreturn
+ ****************************************************************************/
+
+static void khci_reqreturn(struct khci_ep_s *privep,
+ struct khci_req_s *privreq, int16_t result)
+{
+ /* If endpoint 0, temporarily reflect the state of protocol stalled
+ * in the callback.
+ */
+
+ bool stalled = privep->stalled;
+ if (USB_EPNO(privep->ep.eplog) == EP0)
+ {
+ privep->stalled = (privep->dev->ctrlstate == CTRLSTATE_STALLED);
+ }
+
+ /* Save the result in the request structure */
+
+ privreq->req.result = result;
+
+ /* Callback to the request completion handler */
+
+ privreq->flink = NULL;
+ privreq->req.callback(&privep->ep, &privreq->req);
+
+ /* Restore the stalled indication */
+
+ privep->stalled = stalled;
+}
+
+/****************************************************************************
+ * Name: khci_reqcomplete
+ ****************************************************************************/
+
+static void khci_reqcomplete(struct khci_ep_s *privep, int16_t result)
+{
+ struct khci_req_s *privreq;
+ irqstate_t flags;
+
+ /* Remove the completed request at the head of the endpoint's active
+ * request list.
+ */
+
+ flags = enter_critical_section();
+ privreq = khci_remfirst(&privep->active);
+ leave_critical_section(flags);
+
+ if (privreq)
+ {
+ /* Return the request to the class driver */
+
+ khci_reqreturn(privep, privreq, result);
+ }
+}
+
+/****************************************************************************
+ * Name: khci_epwrite
+ ****************************************************************************/
+
+static void khci_epwrite(struct khci_ep_s *privep,
+ volatile struct usbotg_bdtentry_s *bdt,
+ const uint8_t *src, uint32_t nbytes)
+{
+ uint32_t status;
+
+ usbtrace(TRACE_WRITE(USB_EPNO(privep->ep.eplog)), nbytes);
+
+ /* Clear all bits in the status (assuring that we own the BDT) */
+
+ bdt->status = 0;
+
+ /* Get the correct data toggle (as well as other BDT bits) */
+
+ if (privep->txdata1)
+ {
+ status = (USB_BDT_UOWN | USB_BDT_DATA1 | USB_BDT_DTS);
+ privep->txdata1 = 0;
+ }
+ else
+ {
+ status = (USB_BDT_UOWN | USB_BDT_DATA0 | USB_BDT_DTS);
+ privep->txdata1 = 1;
+ }
+
+ /* Set the data pointer and data length */
+
+ bdt->addr = (uint8_t *)src;
+ status |= (nbytes << USB_BDT_BYTECOUNT_SHIFT) | USB_BDT_DTS;
+
+ /* And, finally, give the BDT to the USB */
+
+ bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n",
+ USB_EPNO(privep->ep.eplog), bdt, status, bdt->addr);
+
+ bdt->status = status;
+}
+
+/****************************************************************************
+ * Name: khci_wrcomplete
+ ****************************************************************************/
+
+static void khci_wrcomplete(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep)
+{
+ volatile struct usbotg_bdtentry_s *bdtin;
+ struct khci_req_s *privreq;
+ int bytesleft;
+ int epno;
+
+ /* Check the request at the head of the endpoint's active request queue.
+ * Since we got here from a write completion event, the active request queue
+ * should not be empty.
+ */
+
+ privreq = khci_rqhead(&privep->active);
+ DEBUGASSERT(privreq != NULL);
+
+ /* An outgoing IN packet has completed. bdtin should point to the BDT
+ * that just completed.
+ */
+
+ bdtin = privep->bdtin;
+ epno = USB_EPNO(privep->ep.eplog);
+
+#ifdef CONFIG_USBDEV_NOWRITEAHEAD
+ uinfo("EP%d: len=%d xfrd=%d inflight=%d\n",
+ epno, privreq->req.len, privreq->req.xfrd, privreq->inflight[0]);
+#else
+ uinfo("EP%d: len=%d xfrd=%d inflight={%d, %d}\n",
+ epno, privreq->req.len, privreq->req.xfrd,
+ privreq->inflight[0], privreq->inflight[1]);
+#endif
+ bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n",
+ epno, bdtin, bdtin->status, bdtin->addr);
+
+ /* We should own the BDT that just completed. But NULLify the entire BDT IN.
+ * Why? So that we can tell later that the BDT available. No, it is not
+ * sufficient to look at the UOWN bit. If UOWN==0, then the transfer has
+ * been completed BUT it may not yet have been processed. But a completely
+ * NULLified BDT is a sure indication
+ */
+
+ DEBUGASSERT((bdtin->status & USB_BDT_UOWN) == USB_BDT_COWN);
+ bdtin->status = 0;
+ bdtin->addr = 0;
+
+ /* Toggle bdtin to the other BDT. Is the current bdtin the EVEN bdt? */
+
+ privep->bdtin = &g_bdt[EP_IN_EVEN(epno)];
+ if (bdtin == privep->bdtin)
+ {
+ /* Yes.. Then the other BDT is the ODD BDT */
+
+ privep->bdtin++;
+ }
+
+ /* Update the number of bytes transferred. */
+
+ privreq->req.xfrd += privreq->inflight[0];
+#ifdef CONFIG_USBDEV_NOWRITEAHEAD
+ privreq->inflight[0] = 0;
+#else
+ privreq->inflight[0] = privreq->inflight[1];
+ privreq->inflight[1] = 0;
+#endif
+ bytesleft = privreq->req.len - privreq->req.xfrd;
+
+ /* If all of the bytes were sent (bytesleft == 0) and no NULL packet is
+ * needed (!txnullpkt), then we are finished with the transfer
+ */
+
+ if (bytesleft == 0 && !privep->txnullpkt)
+ {
+ /* The transfer is complete. Give the completed request back to
+ * the class driver.
+ */
+
+ usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd);
+ khci_reqcomplete(privep, OK);
+
+ /* Special case writes to endpoint zero. If there is no transfer in
+ * progress, then we need to configure to received the next SETUP packet.
+ */
+
+ if (USB_EPNO(privep->ep.eplog) == 0)
+ {
+ priv->ctrlstate = CTRLSTATE_WAITSETUP;
+ }
+ }
+}
+
+/****************************************************************************
+ * Name: khci_rqrestart
+ ****************************************************************************/
+
+static void khci_rqrestart(int argc, uint32_t arg1, ...)
+{
+ struct khci_usbdev_s *priv;
+ struct khci_ep_s *privep;
+ struct khci_req_s *privreq;
+ uint16_t epstalled;
+ uint16_t mask;
+ int epno;
+
+ /* Recover the pointer to the driver structure */
+
+ priv = (struct khci_usbdev_s *)((uintptr_t)arg1);
+ DEBUGASSERT(priv != NULL);
+
+ /* Sample and clear the set of endpoints that have recovered from a stall */
+
+ epstalled = priv->epstalled;
+ priv->epstalled = 0;
+
+ /* Loop, checking each bit in the epstalled bit set */
+
+ for (epno = 0; epstalled && epno < KHCI_NENDPOINTS; epno++)
+ {
+ /* Has this encpoint recovered from a stall? */
+
+ mask = (1 << epno);
+ if ((epstalled & mask) != 0)
+ {
+ /* Yes, this endpoint needs to be restarteed */
+
+ epstalled &= ~mask;
+ privep = &priv->eplist[epno];
+
+ /* Reset some endpoint state variables */
+
+ privep->stalled = false;
+ privep->txnullpkt = false;
+
+ /* Check the request at the head of the endpoint's pending request queue */
+
+ privreq = khci_rqhead(&privep->pend);
+ if (privreq)
+ {
+ /* Restart transmission after we have recovered from a stall */
+
+ privreq->req.xfrd = 0;
+ privreq->inflight[0] = 0;
+#ifndef CONFIG_USBDEV_NOWRITEAHEAD
+ privreq->inflight[1] = 0;
+#endif
+ (void)khci_wrrequest(priv, privep);
+ }
+ }
+ }
+}
+
+/****************************************************************************
+ * Name: khci_delayedrestart
+ ****************************************************************************/
+
+static void khci_delayedrestart(struct khci_usbdev_s *priv, uint8_t epno)
+{
+ /* Add endpoint to the set of endpoints that need to be restarted */
+
+ priv->epstalled |= (1 << epno);
+
+ /* And start (or re-start) the watchdog timer */
+
+ wd_start(priv->wdog, RESTART_DELAY, khci_rqrestart, 1, (uint32_t)priv);
+}
+
+/****************************************************************************
+ * Name: khci_rqstop
+ ****************************************************************************/
+
+static void khci_rqstop(struct khci_ep_s *privep)
+{
+ struct khci_req_s *privreq;
+
+ /* Move all of the active requests back to the pending request queue */
+
+ while ((privreq = khci_remlast(&privep->active)))
+ {
+ /* Move the request back to the head of the pending list */
+
+ khci_addfirst(&privep->pend, privreq);
+ }
+}
+
+/****************************************************************************
+ * Name: khci_wrstart
+ ****************************************************************************/
+
+static int khci_wrstart(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep)
+{
+ volatile struct usbotg_bdtentry_s *bdt;
+ struct khci_req_s *privreq;
+ uint8_t *buf;
+ uint8_t epno;
+ int nbytes;
+ int bytesleft;
+ int xfrd;
+ int index;
+
+ /* We get here when either (1) an IN endpoint completion interrupt occurs,
+ * or (2) a new write request is reqeived from the class.
+ */
+
+ /* Get the endpoint number that we are servicing */
+
+ epno = USB_EPNO(privep->ep.eplog);
+
+ /* Decide which BDT to use. bdtin points to the "current" BDT. That is,
+ * the one that either (1) available for next transfer, or (2) the one
+ * that is currently busy with the current transfer. If the current
+ * BDT is busy, we have the option of setting up the other BDT in advance
+ * in order to improve data transfer performance.
+ */
+
+ bdt = privep->bdtin;
+ index = 0;
+
+ if (bdt->status || bdt->addr)
+ {
+#ifdef CONFIG_USBDEV_NOWRITEAHEAD
+ /* The current BDT is not available and write ahead is disabled. There
+ * is nothing we can do now. Return -EBUSY to indicate this condition.
+ */
+
+ return -EBUSY;
+#else
+ /* The current BDT is not available, check the other BDT */
+
+ volatile struct usbotg_bdtentry_s *otherbdt;
+ otherbdt = &g_bdt[EP(epno, EP_DIR_IN, EP_PP_EVEN)];
+ if (otherbdt == bdt)
+ {
+ otherbdt++;
+ }
+
+ /* Is it available? */
+
+ if (otherbdt->status || otherbdt->addr)
+ {
+ /* No, neither are available. We cannot perform the transfer now.
+ * Return -EBUSY to indicate this condition.
+ */
+
+ return -EBUSY;
+ }
+
+ /* Yes... use the other BDT */
+
+ bdt = otherbdt;
+ index = 1;
+#endif
+ }
+
+ /* A BDT is available. Which request should we be operating on? The last
+ * incomplete, active request would be at the tail of the active list.
+ */
+
+ privreq = khci_rqtail(&privep->active);
+
+ /* This request would be NULL if there is no incomplete, active request. */
+
+ if (privreq)
+ {
+ /* Get the number of bytes left to be transferred in the request */
+
+ xfrd = privreq->req.xfrd;
+ bytesleft = privreq->req.len - xfrd;
+
+ /* Even if the request is incomplete, transfer of all the requested
+ * bytes may already been started. NOTE: inflight[1] should be zero
+ * because we know that there is a BDT available.
+ */
+
+#ifndef CONFIG_USBDEV_NOWRITEAHEAD
+ DEBUGASSERT(privreq->inflight[1] == 0);
+#endif
+ /* Has the transfer been initiated for all of the bytes? */
+
+ if (bytesleft > privreq->inflight[0])
+ {
+ /* No.. we have more work to do with this request */
+
+ xfrd += privreq->inflight[0];
+ bytesleft -= privreq->inflight[0];
+ }
+
+ /* Do we need to send a null packet after this packet? */
+
+ else if (privep->txnullpkt)
+ {
+ /* Yes... set up for the NULL packet transfer */
+
+ xfrd = privreq->req.len;
+ bytesleft = 0;
+ }
+ else
+ {
+ /* No.. We are finished with this request. We need to get the
+ * next request from the head of the pending request list.
+ */
+
+ privreq = NULL;
+ }
+ }
+
+ /* If privreq is NULL here then either (1) there is no active request, or
+ * (2) the (only) active request is fully queued. In either case, we need
+ * to get the next request from the head of the pending request list.
+ */
+
+ if (!privreq)
+ {
+ /* Remove the next request from the head of the pending request list */
+
+ privreq = khci_remfirst(&privep->pend);
+ if (!privreq)
+ {
+ /* The pending request list is empty. There are no queued TX
+ * requests to be sent.
+ */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPINQEMPTY), epno);
+
+ /* Return -ENODATA to indicate that there are no further requests
+ * to be processed.
+ */
+
+ return -ENODATA;
+ }
+
+ /* Add this request to the tail of the active request list */
+
+ khci_addlast(&privep->active, privreq);
+
+ /* Set up the first transfer for this request */
+
+ xfrd = 0;
+ bytesleft = privreq->req.len;
+ }
+
+ uinfo("epno=%d req=%p: len=%d xfrd=%d index=%d nullpkt=%d\n",
+ epno, privreq, privreq->req.len, xfrd, index, privep->txnullpkt);
+
+ /* Get the number of bytes left to be sent in the packet */
+
+ nbytes = bytesleft;
+ if (nbytes > 0 || privep->txnullpkt)
+ {
+ /* Either send the maxpacketsize or all of the remaining data in
+ * the request.
+ */
+
+ privep->txnullpkt = 0;
+ if (nbytes >= privep->ep.maxpacket)
+ {
+ nbytes = privep->ep.maxpacket;
+
+ /* Handle the case where this packet is exactly the
+ * maxpacketsize. Do we need to send a zero-length packet
+ * in this case?
+ */
+
+ if (bytesleft == privep->ep.maxpacket &&
+ (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0)
+ {
+ privep->txnullpkt = 1;
+ }
+ }
+ }
+
+ /* Send the packet (might be a null packet with nbytes == 0) */
+
+ buf = privreq->req.buf + xfrd;
+
+ /* Setup the writes to the endpoints */
+
+ khci_epwrite(privep, bdt, buf, nbytes);
+
+ /* Special case endpoint 0 state information. The write request is in
+ * progress.
+ */
+
+ if (epno == 0)
+ {
+ priv->ctrlstate = CTRLSTATE_WRREQUEST;
+ }
+
+ /* Update for the next data IN interrupt */
+
+ privreq->inflight[index] = nbytes;
+ return OK;
+}
+
+/****************************************************************************
+ * Name: khci_wrrequest
+ ****************************************************************************/
+
+static int khci_wrrequest(struct khci_usbdev_s *priv, struct khci_ep_s *privep)
+{
+ int ret;
+
+ /* Always try to start two transfers in order to take advantage of the
+ * KHCI's ping pong buffering.
+ */
+
+ ret = khci_wrstart(priv, privep);
+#ifndef CONFIG_USBDEV_NOWRITEAHEAD
+ if (ret == OK)
+ {
+ /* Note: We need to return the error condition only if nothing was
+ * queued
+ */
+
+ (void)khci_wrstart(priv, privep);
+ }
+#else
+ UNUSED(ret);
+#endif
+
+ /* We return OK to indicate that a write request is still in progress */
+
+ return khci_rqhead(&privep->active) == NULL ? -ENODATA : OK;
+}
+
+/****************************************************************************
+ * Name: khci_rdcomplete
+ ****************************************************************************/
+
+static int khci_rdcomplete(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep)
+{
+ volatile struct usbotg_bdtentry_s *bdtout;
+ struct khci_req_s *privreq;
+ int epno;
+
+ /* Check the request at the head of the endpoint's active request queue */
+
+ privreq = khci_rqhead(&privep->active);
+ if (!privreq)
+ {
+ /* There is no active packet waiting to receive any data. Then why are
+ * we here?
+ */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPOUTQEMPTY),
+ USB_EPNO(privep->ep.eplog));
+ return -EINVAL;
+ }
+
+ /* bdtout should point to the BDT that just completed */
+
+ bdtout = privep->bdtout;
+ epno = USB_EPNO(privep->ep.eplog);
+
+ uinfo("EP%d: len=%d xfrd=%d\n",
+ epno, privreq->req.len, privreq->req.xfrd);
+ bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n",
+ epno, bdtout, bdtout->status, bdtout->addr);
+
+ /* We should own the BDT that just completed */
+
+ DEBUGASSERT((bdtout->status & USB_BDT_UOWN) == USB_BDT_COWN);
+
+ /* Get the length of the data received from the BDT. */
+
+ privreq->req.xfrd = (bdtout->status & USB_BDT_BYTECOUNT_MASK) >> USB_BDT_BYTECOUNT_SHIFT;
+
+ /* Complete the transfer and return the request to the class driver. */
+
+ usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd);
+ khci_reqcomplete(privep, OK);
+
+ /* Nullify the BDT entry that just completed. Why? So that we can tell later
+ * that the BDT has been processed. No, it is not sufficient to look at the
+ * UOWN bit. If UOWN==0, then the transfer has been completed BUT it may not
+ * yet have been processed.
+ */
+
+ bdtout->status = 0;
+ bdtout->addr = 0;
+
+ /* Toggle bdtout to the other BDT. Is the current bdtout the EVEN bdt? */
+
+ privep->bdtout = &g_bdt[EP_OUT_EVEN(epno)];
+ if (bdtout == privep->bdtout)
+ {
+ /* Yes.. Then the other BDT is the ODD BDT */
+
+ privep->bdtout++;
+ }
+
+ /* Set up the next read operation */
+
+ return khci_rdrequest(priv, privep);
+}
+
+/****************************************************************************
+ * Name: khci_ep0rdsetup
+ ****************************************************************************/
+
+static int khci_ep0rdsetup(struct khci_usbdev_s *priv, uint8_t *dest,
+ int readlen)
+{
+ volatile struct usbotg_bdtentry_s *bdtout;
+ volatile struct usbotg_bdtentry_s *otherbdt;
+ struct khci_ep_s *privep;
+ uint32_t status;
+
+ /* bdtout refers to the next ping-pong BDT to use. */
+
+ privep = &priv->eplist[EP0];
+ bdtout = privep->bdtout;
+
+ /* Get the other BDT. Check if the current BDT the EVEN BDT? */
+
+ otherbdt = &g_bdt[EP_OUT_EVEN(EP0)];
+ if (bdtout == otherbdt)
+ {
+ /* Yes.. then the other BDT is the ODD BDT. */
+
+ otherbdt++;
+ }
+
+ /* If there is no RX transfer in progress, then the other BDT is setup
+ * to receive the next setup packet. There is a race condition here!
+ * Stop any setup packet.
+ */
+
+ if (!priv->rxbusy)
+ {
+ /* Nullify all BDT OUT entries. Why? So that we can tell later
+ * that the BDT available. No, it is not sufficient to look at the
+ * UOWN bit. If UOWN==0, then the transfer has been completed BUT
+ * it may not yet have been processed. But a completely NULLified
+ * BDT is a sure indication
+ */
+
+ bdtout->status = 0;
+ bdtout->addr = 0;
+ otherbdt->status = 0;
+ otherbdt->addr = 0;
+
+ /* Reset the other BDT to zero... this will cause any attempted use
+ * of the other BDT to be NAKed. Set the first DATA0/1 value to 1.
+ */
+
+ privep->rxdata1 = 1;
+ }
+
+ /* Otherwise, there are RX transfers in progress. bdtout may be
+ * unavailable now. In that case, we are free to setup the other BDT
+ * in order to improve performance. NOTE: That we check if the
+ * entire BDT has been NULLified. That is the only sure indication
+ * that the BDT is available (see above).
+ */
+
+ if (bdtout->status || bdtout->addr)
+ {
+#ifdef CONFIG_USBDEV_NOREADAHEAD
+ /* We will not try to read ahead */
+
+ return -EBUSY;
+#else
+ /* bdtout is not available. Is the other BDT available? */
+
+ if (otherbdt->status || otherbdt->addr)
+ {
+ /* Neither are available... we cannot accept the request now */
+
+ return -EBUSY;
+ }
+
+ /* Use the other BDT */
+
+ bdtout = otherbdt;
+#endif
+ }
+
+ usbtrace(TRACE_READ(EP0), readlen);
+
+ /* Get the correct data toggle (as well as other BDT bits) */
+
+ if (privep->rxdata1)
+ {
+ status = (USB_BDT_UOWN | USB_BDT_DATA1 | USB_BDT_DTS);
+ privep->rxdata1 = 0;
+ }
+ else
+ {
+ status = (USB_BDT_UOWN | USB_BDT_DATA0 | USB_BDT_DTS);
+ privep->rxdata1 = 1;
+ }
+
+ /* Set the data pointer, data length, and enable the endpoint */
+
+ bdtout->addr = (uint8_t *)dest;
+ status |= ((uint32_t)readlen << USB_BDT_BYTECOUNT_SHIFT);
+
+ /* Then give the BDT to the USB */
+
+ bdtinfo("EP0 BDT OUT [%p] {%08x, %08x}\n", bdtout, status, bdtout->addr);
+ bdtout->status = status;
+
+ priv->ctrlstate = CTRLSTATE_RDREQUEST;
+ priv->rxbusy = 1;
+ return OK;
+}
+
+/****************************************************************************
+ * Name: khci_rdsetup
+ ****************************************************************************/
+
+static int khci_rdsetup(struct khci_ep_s *privep, uint8_t *dest, int readlen)
+{
+ volatile struct usbotg_bdtentry_s *bdtout;
+ uint32_t status;
+ int epno;
+
+ /* Select a BDT. Check both the even and the ODD BDT and use the first one
+ * that we own.
+ */
+
+ epno = USB_EPNO(privep->ep.eplog);
+
+ /* bdtout refers to the next ping-pong BDT to use. However, bdtout may be
+ * unavailable now. But, in that case, we are free to setup the other BDT
+ * in order to improve performance.
+ *
+ * Note that we NULLify the BDT OUT entries. This is so that we can tell
+ * that the BDT readlly available. No, it is not sufficient to look at the
+ * UOWN bit. If UOWN==0, then the transfer has been completed BUT it may
+ * not yet have been processed. But a completely NULLified BDT is a sure
+ * indication
+ */
+
+ bdtout = privep->bdtout;
+ if (bdtout->status || bdtout->addr)
+ {
+#ifdef CONFIG_USBDEV_NOREADAHEAD
+ /* We will not try to read-ahead */
+
+ return -EBUSY;
+#else
+ volatile struct usbotg_bdtentry_s *otherbdt;
+
+ /* Is the current BDT the EVEN BDT? */
+
+ otherbdt = &g_bdt[EP_OUT_EVEN(epno)];
+ if (bdtout == otherbdt)
+ {
+ /* Yes.. select the ODD BDT */
+
+ otherbdt++;
+ }
+
+ /* Is the other BDT available? */
+
+ if (otherbdt->status || otherbdt->addr)
+ {
+ /* Neither are available... we cannot accept the request now */
+
+ return -EBUSY;
+ }
+
+ /* Use the other BDT */
+
+ bdtout = otherbdt;
+#endif
+ }
+
+ usbtrace(TRACE_READ(USB_EPNO(privep->ep.eplog)), readlen);
+
+ /* Clear status bits (making sure that UOWN is cleared before doing anything
+ * else).
+ */
+
+ bdtout->status = 0;
+
+ /* Set the data pointer, data length, and enable the endpoint */
+
+ bdtout->addr = (uint8_t *)dest;
+
+ /* Get the correct data toggle. */
+
+ if (privep->rxdata1)
+ {
+ status = (USB_BDT_UOWN | USB_BDT_DATA1 | USB_BDT_DTS);
+ privep->rxdata1 = 0;
+ }
+ else
+ {
+ status = (USB_BDT_UOWN | USB_BDT_DATA0 | USB_BDT_DTS);
+ privep->rxdata1 = 1;
+ }
+
+ /* Set the data length (preserving the data toggle). */
+
+ status |= ((uint32_t)readlen << USB_BDT_BYTECOUNT_SHIFT);
+
+ /* Then give the BDT to the USB */
+
+ bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n",
+ epno, bdtout, status, bdtout->addr);
+
+ bdtout->status = status;
+ return OK;
+}
+
+/****************************************************************************
+ * Name: khci_rdrequest
+ ****************************************************************************/
+
+static int khci_rdrequest(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep)
+{
+ struct khci_req_s *privreq;
+ int readlen;
+ int ret;
+
+ /* Check the request at the head of the endpoint request queue */
+
+ privreq = khci_rqhead(&privep->pend);
+ if (!privreq)
+ {
+ /* There is no packet to receive any data. */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPOUTQEMPTY),
+ USB_EPNO(privep->ep.eplog));
+
+ /* Special case reads from to endpoint zero. If there is no transfer in
+ * progress, then we need to configure to received the next SETUP packet.
+ */
+
+ if (USB_EPNO(privep->ep.eplog) == 0 &&
+ priv->ctrlstate == CTRLSTATE_RDREQUEST)
+ {
+ priv->ctrlstate = CTRLSTATE_WAITSETUP;
+ priv->rxbusy = 0;
+ }
+
+ return OK;
+ }
+
+ uinfo("EP%d: len=%d\n", USB_EPNO(privep->ep.eplog), privreq->req.len);
+
+ /* Ignore any attempt to receive a zero length packet */
+
+ if (privreq->req.len == 0)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_EPOUTNULLPACKET), 0);
+ khci_reqcomplete(privep, OK);
+ return OK;
+ }
+
+ /* Limit the size of the transfer to either the buffer size or the max
+ * packet size of the endpoint.
+ */
+
+ readlen = MIN(privreq->req.len, privep->ep.maxpacket);
+
+ /* Handle EP0 in a few special ways */
+
+ if (USB_EPNO(privep->ep.eplog) == EP0)
+ {
+ ret = khci_ep0rdsetup(priv, privreq->req.buf, readlen);
+ }
+ else
+ {
+ ret = khci_rdsetup(privep, privreq->req.buf, readlen);
+ }
+
+ /* If the read request was successfully setup, then move the request from
+ * the head of the pending request queue to the tail of the active request
+ * queue.
+ */
+
+ if (ret == OK)
+ {
+ privreq = khci_remfirst(&privep->pend);
+ DEBUGASSERT(privreq != NULL);
+ khci_addlast(&privep->active, privreq);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: khci_cancelrequests
+ ****************************************************************************/
+
+static void khci_cancelrequests(struct khci_ep_s *privep, int16_t result)
+{
+ struct khci_req_s *privreq;
+
+ while ((privreq = khci_remfirst(&privep->active)))
+ {
+ usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd);
+ khci_reqreturn(privep, privreq, result);
+ }
+
+ while ((privreq = khci_remfirst(&privep->pend)))
+ {
+ usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd);
+ khci_reqreturn(privep, privreq, result);
+ }
+}
+
+/****************************************************************************
+ * Interrupt Level Processing
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: khci_dispatchrequest
+ ****************************************************************************/
+
+static void khci_dispatchrequest(struct khci_usbdev_s *priv)
+{
+ int ret;
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_DISPATCH), 0);
+ if (priv && priv->driver)
+ {
+ /* Forward to the control request to the class driver implementation */
+
+ ret = CLASS_SETUP(priv->driver, &priv->usbdev, &priv->ctrl, NULL, 0);
+ if (ret < 0)
+ {
+ /* Stall on failure */
+
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_DISPATCHSTALL), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ }
+}
+
+/****************************************************************************
+ * Name: khci_ep0stall
+ ****************************************************************************/
+
+static void khci_ep0stall(struct khci_usbdev_s *priv)
+{
+ uint32_t regval;
+
+ /* Check if EP0 is stalled */
+
+ regval = khci_getreg(KINETIS_USB0_ENDPT0);
+ if ((regval & USB_ENDPT_EPSTALL) != 0)
+ {
+ /* If so, clear the EP0 stall status */
+
+ regval &= ~USB_ENDPT_EPSTALL;
+ khci_putreg(regval, KINETIS_USB0_ENDPT0);
+ }
+}
+
+/****************************************************************************
+ * Name: khci_eptransfer
+ ****************************************************************************/
+
+static void khci_eptransfer(struct khci_usbdev_s *priv, uint8_t epno,
+ uint16_t ustat)
+{
+ struct khci_ep_s *privep;
+ int ret;
+
+ /* Decode and service non control endpoints interrupt */
+
+ privep = &priv->eplist[epno];
+
+ /* Check if the last transaction was an EP0 OUT transaction */
+
+ if ((ustat & USB_STAT_TX) == USB_STAT_TX_OUT)
+ {
+ /* OUT: host-to-device */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPOUTDONE), ustat);
+
+ /* Handle read requests. Call khci_rdcomplete() to complete the OUT
+ * transfer and setup the next out transfer.
+ */
+
+ ret = khci_rdcomplete(priv, privep);
+#ifdef CONFIG_USBDEV_NOREADAHEAD
+ if (ret == OK)
+ {
+ /* If that succeeds, then try to set up another OUT transfer. */
+
+ (void)khci_rdrequest(priv, privep);
+ }
+#else
+ UNUSED(ret);
+#endif
+ }
+ else
+ {
+ /* IN: device-to-host */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPINDONE), ustat);
+
+ /* An outgoing IN packet has completed. Update the number of bytes transferred
+ * and check for completion of the transfer.
+ */
+
+ khci_wrcomplete(priv, privep);
+
+ /* Handle additional queued write requests */
+
+ (void)khci_wrrequest(priv, privep);
+ }
+}
+
+/****************************************************************************
+ * Name: khci_ep0nextsetup
+ *
+ * Description:
+ * This function is called (1) after sucessful completion of an EP0 Setup
+ * command, or (2) after receipt of the OUT complete event (for simple
+ * transfers). It simply sets up the single BDT to accept the next
+ * SETUP commend.
+ *
+ ****************************************************************************/
+
+static void khci_ep0nextsetup(struct khci_usbdev_s *priv)
+{
+ volatile struct usbotg_bdtentry_s *bdt = priv->eplist[EP0].bdtout;
+ uint32_t bytecount;
+
+ /* This operation should be performed no more than once per OUT transaction.
+ * priv->ep0done is set to zero at the beginning of processing of each EP0
+ * transfer. It is set the first time that this function runs after the EP0
+ * transfer.
+ */
+
+ if (!priv->ep0done)
+ {
+ bytecount = (USB_SIZEOF_CTRLREQ << USB_BDT_BYTECOUNT_SHIFT);
+ bdt->addr = (uint8_t *)&priv->ctrl;
+ bdt->status = (USB_BDT_UOWN | bytecount);
+ priv->ep0done = 1;
+ }
+}
+
+/****************************************************************************
+ * Name: khci_ep0rdcomplete
+ *
+ * Description:
+ * This function is called after a sequence of read sequence. In this
+ * context, only one BDT is used. Both BDTs must be prepared to receive
+ * SETUP packets.
+ *
+ ****************************************************************************/
+
+static void khci_ep0rdcomplete(struct khci_usbdev_s *priv)
+{
+ volatile struct usbotg_bdtentry_s *bdt;
+ struct khci_ep_s *ep0;
+ uint32_t physaddr;
+ uint32_t bytecount;
+
+ /* This operation should be performed no more than once per OUT transaction.
+ * priv->ep0done is set to zero at the beginning of processing of each EP0
+ * transfer. It is set the first time that this function runs after the EP0
+ * transfer.
+ */
+
+ if (!priv->ep0done)
+ {
+ bytecount = (USB_SIZEOF_CTRLREQ << USB_BDT_BYTECOUNT_SHIFT);
+ physaddr = (uint32_t)&priv->ctrl;
+
+ bdt = &g_bdt[EP0_OUT_EVEN];
+ bdt->addr = (uint8_t *)physaddr;
+ bdt->status = (USB_BDT_UOWN | bytecount);
+
+ bdt = &g_bdt[EP0_OUT_ODD];
+ bdt->addr = (uint8_t *)physaddr;
+ bdt->status = (USB_BDT_UOWN | bytecount);
+
+ priv->ep0done = 1;
+
+ /* Data toggling is not used on SETUP transfers. And IN transfer
+ * resulting from a SETUP command should begin with DATA1.
+ */
+
+ ep0 = &priv->eplist[EP0];
+ ep0->rxdata1 = 0;
+ ep0->txdata1 = 1;
+ }
+}
+
+/****************************************************************************
+ * Name: khci_ep0setup
+ ****************************************************************************/
+
+static void khci_ep0setup(struct khci_usbdev_s *priv)
+{
+ volatile struct usbotg_bdtentry_s *bdt;
+ struct khci_ep_s *ep0;
+ struct khci_ep_s *privep;
+ union wb_u value;
+ union wb_u index;
+ union wb_u len;
+ union wb_u response;
+ uint32_t regval;
+ bool dispatched = false;
+ uint8_t epno;
+ int nbytes = 0; /* Assume zero-length packet */
+ int ret;
+
+ /* Cancel any pending requests. */
+
+ ep0 = &priv->eplist[EP0];
+ khci_cancelrequests(ep0, -EPROTO);
+
+ /* Assume NOT stalled; no TX in progress; no RX overrun. Data 0/1 toggling
+ * is not used on SETUP packets, but any following EP0 IN transfer should
+ * beginning with DATA1.
+ */
+
+ ep0->stalled = false;
+ ep0->rxdata1 = 0;
+ ep0->txdata1 = 1;
+
+ /* Initialize for the SETUP */
+
+ priv->ctrlstate = CTRLSTATE_WAITSETUP;
+
+ /* And extract the little-endian 16-bit values to host order */
+
+ value.w = GETUINT16(priv->ctrl.value);
+ index.w = GETUINT16(priv->ctrl.index);
+ len.w = GETUINT16(priv->ctrl.len);
+
+ uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
+
+ /* Dispatch any non-standard requests */
+
+ if ((priv->ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_NOSTDREQ), priv->ctrl.type);
+
+ /* Let the class implementation handle all non-standar requests */
+
+ khci_dispatchrequest(priv);
+ dispatched = true;
+ goto resume_packet_processing; /* Sorry about the goto */
+ }
+
+ /* Handle standard request. Pick off the things of interest to the
+ * USB device controller driver; pass what is left to the class driver
+ */
+
+ switch (priv->ctrl.req)
+ {
+ case USB_REQ_GETSTATUS:
+ {
+ /* type: device-to-host; recipient = device, interface, endpoint
+ * value: 0
+ * index: zero interface endpoint
+ * len: 2; data = status
+ */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETSTATUS), priv->ctrl.type);
+ if (len.w != 2 || (priv->ctrl.type & USB_REQ_DIR_IN) == 0 ||
+ index.b[MSB] != 0 || value.w != 0)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADEPGETSTATUS), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ else
+ {
+ switch (priv->ctrl.type & USB_REQ_RECIPIENT_MASK)
+ {
+ case USB_REQ_RECIPIENT_ENDPOINT:
+ {
+ epno = USB_EPNO(index.b[LSB]);
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPGETSTATUS), epno);
+ if (epno >= KHCI_NENDPOINTS)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADEPGETSTATUS), epno);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ else
+ {
+ privep = &priv->eplist[epno];
+ response.w = 0; /* Not stalled */
+ nbytes = 2; /* Response size: 2 bytes */
+
+ if (USB_ISEPIN(index.b[LSB]))
+ {
+ /* IN endpoint */
+
+ bdt = privep->bdtin;
+ }
+ else
+ {
+ /* OUT endpoint */
+
+ bdt = privep->bdtout;
+ }
+
+ /* BSTALL set if stalled */
+
+ if ((bdt->status & USB_BDT_BSTALL) != 0)
+ {
+ response.b[LSB] = 1; /* Stalled, set bit 0 */
+ }
+ }
+ }
+ break;
+
+ case USB_REQ_RECIPIENT_DEVICE:
+ {
+ if (index.w == 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_DEVGETSTATUS), 0);
+
+ /* Features: Remote Wakeup=YES; selfpowered=? */
+
+ response.w = 0;
+ response.b[LSB] = (priv->selfpowered << USB_FEATURE_SELFPOWERED) |
+ (priv->rwakeup << USB_FEATURE_REMOTEWAKEUP);
+ nbytes = 2; /* Response size: 2 bytes */
+ }
+ else
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADDEVGETSTATUS), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ }
+ break;
+
+ case USB_REQ_RECIPIENT_INTERFACE:
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_IFGETSTATUS), 0);
+ response.w = 0;
+ nbytes = 2; /* Response size: 2 bytes */
+ }
+ break;
+
+ default:
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADGETSTATUS), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ break;
+ }
+ }
+ }
+ break;
+
+ case USB_REQ_CLEARFEATURE:
+ {
+ /* type: host-to-device; recipient = device, interface or endpoint
+ * value: feature selector
+ * index: zero interface endpoint;
+ * len: zero, data = none
+ */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_CLEARFEATURE), priv->ctrl.type);
+ if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE)
+ {
+ /* Disable B device from performing HNP */
+
+#ifdef CONFIG_USBOTG
+ if (value.w == USBOTG_FEATURE_B_HNP_ENABLE)
+ {
+ /* Disable HNP */
+#warning Missing Logic
+ }
+
+ /* Disable A device HNP support */
+
+ else if (value.w == USBOTG_FEATURE_A_HNP_SUPPORT)
+ {
+ /* Disable HNP support */
+#warning Missing Logic
+ }
+
+ /* Disable alternate HNP support */
+
+ else if (value.w == USBOTG_FEATURE_A_ALT_HNP_SUPPORT)
+ {
+ /* Disable alternate HNP */
+#warning Missing Logic
+ }
+ else
+#endif
+ /* Disable remote wakeup */
+
+ if (value.w == USB_FEATURE_REMOTEWAKEUP)
+ {
+ priv->rwakeup = 0;
+ }
+ else
+ {
+ /* Let the class implementation handle all other device features */
+
+ khci_dispatchrequest(priv);
+ dispatched = true;
+ }
+ }
+ else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_ENDPOINT)
+ {
+ epno = USB_EPNO(index.b[LSB]);
+ if (epno > 0 && epno < KHCI_NENDPOINTS && index.b[MSB] == 0 &&
+ value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0)
+ {
+ privep = &priv->eplist[epno];
+ privep->halted = false;
+ ret = khci_epstall(&privep->ep, true);
+ UNUSED(ret);
+ }
+ else
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADCLEARFEATURE), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ }
+ else
+ {
+ /* Let the class implementation handle all other recipients. */
+
+ khci_dispatchrequest(priv);
+ dispatched = true;
+ }
+ }
+ break;
+
+ case USB_REQ_SETFEATURE:
+ {
+ /* type: host-to-device; recipient = device, interface, endpoint
+ * value: feature selector
+ * index: zero interface endpoint;
+ * len: 0; data = none
+ */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SETFEATURE), priv->ctrl.type);
+
+ if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE)
+ {
+ /* Enable B device to perform HNP */
+
+#ifdef CONFIG_USBOTG
+ if (value.w == USBOTG_FEATURE_B_HNP_ENABLE)
+ {
+ /* Enable HNP */
+#warning "Missing logic"
+ }
+
+ /* Enable A device HNP supports */
+
+ else if (value.w == USBOTG_FEATURE_A_HNP_SUPPORT)
+ {
+ /* Enable HNP support */
+#warning "Missing logic"
+ }
+
+ /* Another port on the A device supports HNP */
+
+ else if (value.w == USBOTG_FEATURE_A_ALT_HNP_SUPPORT)
+ {
+ /* Enable alternate HNP */
+#warning "Missing logic"
+ }
+ else
+#endif
+
+ if (value.w == USB_FEATURE_REMOTEWAKEUP)
+ {
+ priv->rwakeup = 0;
+ }
+ else if (value.w == USB_FEATURE_TESTMODE)
+ {
+ /* Special case recipient=device test mode */
+
+ uinfo("test mode: %d\n", index.w);
+ }
+ else
+ {
+ /* Let the class implementation handle all other device features */
+
+ khci_dispatchrequest(priv);
+ dispatched = true;
+ }
+ }
+ else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_ENDPOINT)
+ {
+ /* Handler recipient=endpoint */
+
+ epno = USB_EPNO(index.b[LSB]);
+ if (epno < KHCI_NENDPOINTS && index.b[MSB] == 0 &&
+ value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0)
+ {
+ privep = &priv->eplist[epno];
+ privep->halted = true;
+ ret = khci_epstall(&privep->ep, false);
+ UNUSED(ret);
+ }
+ else
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADSETFEATURE), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ }
+ else
+ {
+ /* The class driver handles all recipients except recipient=endpoint */
+
+ khci_dispatchrequest(priv);
+ dispatched = true;
+ }
+ }
+ break;
+
+ case USB_REQ_SETADDRESS:
+ {
+ /* type: host-to-device; recipient = device
+ * value: device address
+ * index: 0
+ * len: 0; data = none
+ */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0SETUPSETADDRESS), value.w);
+ if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_DEVICE ||
+ index.w != 0 || len.w != 0 || value.w > 127)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADSETADDRESS), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ else
+ {
+ /* Note that setting of the device address will be deferred. A zero-length
+ * packet will be sent and the device address will be set when the zero-
+ * length packet transfer completes.
+ */
+
+ priv->devstate = DEVSTATE_ADDRPENDING;
+ }
+ }
+ break;
+
+ case USB_REQ_GETDESCRIPTOR:
+ /* type: device-to-host; recipient = device
+ * value: descriptor type and index
+ * index: 0 or language ID;
+ * len: descriptor len; data = descriptor
+ */
+ case USB_REQ_SETDESCRIPTOR:
+ /* type: host-to-device; recipient = device
+ * value: descriptor type and index
+ * index: 0 or language ID;
+ * len: descriptor len; data = descriptor
+ */
+
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETSETDESC), priv->ctrl.type);
+ if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE)
+ {
+ /* The request seems valid... let the class implementation handle it */
+
+ khci_dispatchrequest(priv);
+ dispatched = true;
+ }
+ else
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADGETSETDESC), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ }
+ break;
+
+ case USB_REQ_GETCONFIGURATION:
+ /* type: device-to-host; recipient = device
+ * value: 0;
+ * index: 0;
+ * len: 1; data = configuration value
+ */
+
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETCONFIG), priv->ctrl.type);
+ if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE &&
+ value.w == 0 && index.w == 0 && len.w == 1)
+ {
+ /* The request seems valid... let the class implementation handle it */
+
+ khci_dispatchrequest(priv);
+ dispatched = true;
+ }
+ else
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADGETCONFIG), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ }
+ break;
+
+ case USB_REQ_SETCONFIGURATION:
+ /* type: host-to-device; recipient = device
+ * value: configuration value
+ * index: 0;
+ * len: 0; data = none
+ */
+
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SETCONFIG), priv->ctrl.type);
+ if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE &&
+ index.w == 0 && len.w == 0)
+ {
+ /* The request seems valid... let the class implementation handle it */
+
+ khci_dispatchrequest(priv);
+ dispatched = true;
+ }
+ else
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADSETCONFIG), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ }
+ break;
+
+ case USB_REQ_GETINTERFACE:
+ /* type: device-to-host; recipient = interface
+ * value: 0
+ * index: interface;
+ * len: 1; data = alt interface
+ */
+ case USB_REQ_SETINTERFACE:
+ /* type: host-to-device; recipient = interface
+ * value: alternate setting
+ * index: interface;
+ * len: 0; data = none
+ */
+
+ {
+ /* Let the class implementation handle the request */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETSETIF), priv->ctrl.type);
+ khci_dispatchrequest(priv);
+ dispatched = true;
+ }
+ break;
+
+ case USB_REQ_SYNCHFRAME:
+ /* type: device-to-host; recipient = endpoint
+ * value: 0
+ * index: endpoint;
+ * len: 2; data = frame number
+ */
+
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SYNCHFRAME), 0);
+ }
+ break;
+
+ default:
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDCTRLREQ), priv->ctrl.req);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ break;
+ }
+
+ /* PKTDIS bit is set when a Setup Transaction is received. Clear to resume
+ * packet processing.
+ */
+
+resume_packet_processing:
+ regval = khci_getreg(KINETIS_USB0_CTL);
+ regval &= ~USB_CTL_TXSUSPENDTOKENBUSY;
+ khci_putreg(regval, KINETIS_USB0_CTL);
+
+ /* At this point, the request has been handled and there are three possible
+ * outcomes:
+ *
+ * 1. The setup request was successfully handled above and a response packet
+ * must be sent (may be a zero length packet).
+ * 2. The request was successfully handled by the class implementation. In
+ * case, the EP0 IN response has already been queued and the local variable
+ * 'dispatched' will be set to true and ctrlstate != CTRLSTATE_STALL;
+ * 3. An error was detected in either the above logic or by the class implementation
+ * logic. In either case, priv->state will be set CTRLSTATE_STALL
+ * to indicate this case.
+ *
+ * NOTE: Non-standard requests are a special case. They are handled by the
+ * class implementation and this function returned early above, skipping this
+ * logic altogether.
+ */
+
+ if (!dispatched && (priv->ctrlstate != CTRLSTATE_STALL))
+ {
+ /* The SETUP command was not dispatched to the class driver and the SETUP
+ * command did not cause a stall. We will respond. First, restrict the
+ * data length to the length requested in the setup packet
+ */
+
+ if (nbytes > len.w)
+ {
+ nbytes = len.w;
+ }
+
+ /* Send the EP0 SETUP response (might be a zero-length packet) */
+
+ khci_epwrite(ep0, ep0->bdtin, response.b, nbytes);
+ priv->ctrlstate = CTRLSTATE_WAITSETUP;
+ }
+
+ /* Did we stall? This might have occurred from the above logic OR the stall
+ * condition may have been set less obviously in khci_dispatchrequest().
+ * In either case, we handle the stall condition the same.
+ *
+ * However, bad things happen if we try to stall a SETUP packet. So lets
+ * not. If we wait a bit, things will recover. Hmmm.. If we completed
+ * the data phase (perhaps by sending a NULL packet), then I think we
+ * could stall the endpoint and perhaps speed things up a bit???.
+ */
+
+ /* Set up the BDT to accept the next setup commend. */
+
+ khci_ep0nextsetup(priv);
+ priv->ctrlstate = CTRLSTATE_WAITSETUP;
+}
+
+/****************************************************************************
+ * Name: khci_ep0incomplete
+ ****************************************************************************/
+
+static void khci_ep0incomplete(struct khci_usbdev_s *priv)
+{
+ struct khci_ep_s *ep0 = &priv->eplist[EP0];
+ volatile struct usbotg_bdtentry_s *bdtlast;
+ int ret;
+
+ /* Get the last BDT and make sure that we own it. */
+
+ bdtlast = ep0->bdtin;
+
+ /* Make sure that we own the last BDT. */
+
+ bdtlast->status = 0;
+ bdtlast->addr = 0;
+
+ /* Are we processing the completion of one packet of an outgoing request
+ * from the class driver?
+ */
+
+ if (priv->ctrlstate == CTRLSTATE_WRREQUEST)
+ {
+ /* An outgoing EP0 transfer has completed. Update the byte count and
+ * check for the completion of the transfer.
+ *
+ * NOTE: khci_wrcomplete() will toggle bdtin to the other buffer so
+ * we do not need to that for this case.
+ */
+
+ khci_wrcomplete(priv, &priv->eplist[EP0]);
+
+ /* Handle the next queue IN transfer. If there are no further queued
+ * IN transfers, khci_wrrequest will return -ENODATA and that is the
+ * only expected error return value in this context.
+ */
+
+ ret = khci_wrrequest(priv, &priv->eplist[EP0]);
+ if (ret < 0)
+ {
+ DEBUGASSERT(ret == -ENODATA);
+
+ /* If there is nothing to be sent, then we need to configure to
+ * receive the next SETUP packet.
+ */
+
+ priv->ctrlstate = CTRLSTATE_WAITSETUP;
+ }
+ }
+
+ /* No.. Are we processing the completion of a status response? */
+
+ else if (priv->ctrlstate == CTRLSTATE_WAITSETUP)
+ {
+ /* Get the next IN BDT */
+
+ if (bdtlast == &g_bdt[EP0_IN_EVEN])
+ {
+ ep0->bdtin = &g_bdt[EP0_IN_ODD];
+ }
+ else
+ {
+ DEBUGASSERT(bdtlast == &g_bdt[EP0_IN_ODD]);
+ ep0->bdtin = &g_bdt[EP0_IN_EVEN];
+ }
+
+ /* Look at the saved SETUP command. Was it a SET ADDRESS request?
+ * If so, then now is the time to set the address.
+ */
+
+ if (priv->devstate == DEVSTATE_ADDRPENDING)
+ {
+ uint16_t addr = GETUINT16(priv->ctrl.value);
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0ADDRESSSET), addr);
+
+ /* This should be the equivalent state */
+
+ DEBUGASSERT(priv->ctrl.req == USB_REQ_SETADDRESS &&
+ (priv->ctrl.type & REQRECIPIENT_MASK) ==
+ (USB_REQ_TYPE_STANDARD | USB_REQ_RECIPIENT_DEVICE));
+
+ /* Set (or clear) the address */
+
+ khci_putreg(addr, KINETIS_USB0_ADDR);
+ if (addr > 0)
+ {
+ priv->devstate = DEVSTATE_ADDRESS;
+ }
+ else
+ {
+ priv->devstate = DEVSTATE_DEFAULT;
+ }
+ }
+ }
+
+ /* No other state is expected in this context */
+
+ else
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDSTATE), priv->ctrlstate);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+}
+
+/****************************************************************************
+ * Name: khci_ep0outcomplete
+ ****************************************************************************/
+
+static void khci_ep0outcomplete(struct khci_usbdev_s *priv)
+{
+ struct khci_ep_s *ep0 = &priv->eplist[EP0];
+
+ switch (priv->ctrlstate)
+ {
+ /* Read request in progress */
+
+ case CTRLSTATE_RDREQUEST:
+
+ /* Process the next read request for EP0 */
+
+ khci_rdcomplete(priv, ep0);
+
+ /* Was this the end of the OUT transfer? */
+
+ if (priv->ctrlstate == CTRLSTATE_WAITSETUP)
+ {
+ /* Prepare EP0 OUT for the next SETUP transaction. */
+
+ khci_ep0rdcomplete(priv);
+ }
+ break;
+
+ /* No transfer in progress, waiting for SETUP */
+
+ case CTRLSTATE_WAITSETUP:
+ {
+ /* In this case the last OUT transaction must have been a status
+ * stage of a CTRLSTATE_WRREQUEST: Prepare EP0 OUT for the next SETUP
+ * transaction.
+ */
+
+ khci_ep0nextsetup(priv);
+ }
+ break;
+
+ /* Unexpected state OR host aborted the OUT transfer before it completed,
+ * STALL the endpoint in either case
+ */
+
+ default:
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDSTATE), priv->ctrlstate);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ break;
+ }
+}
+
+/****************************************************************************
+ * Name: khci_ep0transfer
+ ****************************************************************************/
+
+static void khci_ep0transfer(struct khci_usbdev_s *priv, uint16_t ustat)
+{
+ volatile struct usbotg_bdtentry_s *bdt;
+
+ /* The following information is available in the status register :
+ *
+ * ENDPT - The 4 bit endpoint number that cause the interrupt.
+ * DIR - The direction of the endpoint.
+ * PPBI - The ping-pong buffer used in the transaction.
+ */
+
+ priv->ep0done = 0;
+
+ /* Check if the last transaction was an EP0 OUT transaction */
+
+ if ((ustat & USB_STAT_TX) == USB_STAT_TX_OUT)
+ {
+ int index;
+
+ /* It was an EP0 OUT transaction. Get the index to the BDT. */
+
+ index = ((ustat & USB_STAT_ODD) == 0 ? EP0_OUT_EVEN : EP0_OUT_ODD);
+ bdt = &g_bdt[index];
+ priv->eplist[0].bdtout = bdt;
+
+ bdtinfo("EP0 BDT OUT [%p] {%08x, %08x}\n", bdt, bdt->status, bdt->addr);
+
+ /* Check the current EP0 OUT buffer contains a SETUP packet */
+
+ if (((bdt->status & USB_BDT_PID_MASK) >> USB_BDT_PID_SHIFT) == USB_PID_SETUP_TOKEN)
+ {
+ /* Check if the SETUP transaction data went into the priv->ctrl
+ * buffer. If not, then we will need to copy it.
+ */
+
+ if (bdt->addr != (uint8_t *)&priv->ctrl)
+ {
+ void *src = (void *)bdt->addr;
+ void *dest = &priv->ctrl;
+
+ memcpy(dest, src, USB_SIZEOF_CTRLREQ);
+ bdt->addr = (uint8_t *)&priv->ctrl;
+ }
+
+ /* Handle the control OUT transfer */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0SETUPDONE), bdt->status);
+ khci_ep0setup(priv);
+ }
+ else
+ {
+ /* Handle the data OUT transfer */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0OUTDONE), ustat);
+ khci_ep0outcomplete(priv);
+ }
+ }
+
+ /* No.. it was an EP0 IN transfer */
+
+ else /* if ((status & USB_STAT_TX) == USB_STAT_TX_IN) */
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0INDONE), ustat);
+
+ /* Handle the IN transfer complete */
+
+ khci_ep0incomplete(priv);
+ }
+
+ /* Check for a request to stall EP0 */
+
+ if (priv->ctrlstate == CTRLSTATE_STALL)
+ {
+ /* Stall EP0 */
+
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_EP0SETUPSTALLED), priv->ctrlstate);
+ (void)khci_epstall(&priv->eplist[EP0].ep, false);
+ }
+}
+
+/****************************************************************************
+ * Name: khci_interrupt
+ ****************************************************************************/
+
+static int khci_interrupt(int irq, void *context)
+{
+ /* For now there is only one USB controller, but we will always refer to
+ * it using a pointer to make any future ports to multiple USB controllers
+ * easier.
+ */
+
+ struct khci_usbdev_s *priv = &g_usbdev;
+ uint16_t usbir;
+ uint16_t otgir;
+ uint32_t regval;
+ int i;
+
+ /* Get the set of pending USB and OTG interrupts interrupts */
+
+ usbir = khci_getreg(KINETIS_USB0_ISTAT) & khci_getreg(KINETIS_USB0_INTEN);
+ otgir = khci_getreg(KINETIS_USB0_OTGISTAT) & khci_getreg(KINETIS_USB0_OTGICR);
+
+ usbtrace(TRACE_INTENTRY(KHCI_TRACEINTID_INTERRUPT), usbir | otgir);
+
+#ifdef CONFIG_USBOTG
+ /* Session Request Protocol (SRP) Time Out Check */
+
+ /* if USB OTG SRP is ready */
+# warning "Missing logic"
+ {
+ /* Check if the 1 millisecond timer has expired */
+
+ if ((otgir & USBOTG_INT_T1MSEC) != 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_T1MSEC), otgir);
+
+ /* Check for the USB OTG SRP timeout */
+# warning "Missing logic"
+ {
+ /* Handle OTG events of the SRP timeout has expired */
+# warning "Missing logic"
+ }
+
+ /* Clear Interrupt 1 msec timer Flag */
+
+ khci_putreg(USBOTG_INT_T1MSEC, KINETIS_USB0_ISTAT);
+ }
+ }
+#endif
+
+ /* Handle events while we are in the attached state */
+
+ if (priv->devstate == DEVSTATE_ATTACHED)
+ {
+ /* Clear all USB interrupts */
+
+ khci_putreg(USB_INT_ALL, KINETIS_USB0_ISTAT);
+
+ /* Make sure that the USE reset and IDLE detect interrupts are enabled */
+
+ regval = khci_getreg(KINETIS_USB0_INTEN);
+ regval |= (USB_INT_USBRST | USB_INT_SLEEP);
+ khci_putreg(regval, KINETIS_USB0_INTEN);
+
+ /* Now were are in the powered state */
+
+ priv->devstate = DEVSTATE_POWERED;
+ }
+
+#ifdef CONFIG_USBOTG
+ /* Check if the ID Pin Changed State */
+
+ if ((otgir & USBOTG_INT_ID) != 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_OTGID), otgir);
+
+ /* Re-detect and re-initialize */
+#warning "Missing logic"
+
+ khci_putreg(USBOTG_INT_ID, KINETIS_USB0_ISTAT);
+ }
+#endif
+#if 0
+ /* Service the USB Activity Interrupt */
+
+ if ((otgir & USBOTG_INT_ACTV) != 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_WKUP), otgir);
+
+ /* Wake-up from susepnd mode */
+
+ khci_putreg(USBOTG_INT_ACTV, KINETIS_USB0_ISTAT);
+ khci_resume(priv);
+ }
+
+ /* It is pointless to continue servicing if the device is in suspend mode. */
+x
+ if ((khci_getreg(KINETIS_USB0_CTL) & USB_USBCTRL_SUSP) != 0)
+ {
+ /* Just clear the interrupt and return */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SUSPENDED), khci_getreg(KINETIS_USB0_CTL));
+ goto interrupt_exit;
+ }
+#endif
+
+ /* Service USB Bus Reset Interrupt. When bus reset is received during
+ * suspend, ACTVIF will be set first, once the UCONbits.SUSPND is clear,
+ * then the URSTIF bit will be asserted. This is why URSTIF is checked
+ * after ACTVIF. The USB reset flag is masked when the USB state is in
+ * DEVSTATE_DETACHED or DEVSTATE_ATTACHED, and therefore cannot cause a
+ * USB reset event during these two states.
+ */
+
+ if ((usbir & USB_INT_USBRST) != 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_RESET), usbir);
+
+ /* Reset interrupt received. Restore our initial state. NOTE: the
+ * hardware automatically resets the USB address, so we really just
+ * need reset any existing configuration/transfer states.
+ */
+ khci_reset(priv);
+ priv->devstate = DEVSTATE_DEFAULT;
+
+#ifdef CONFIG_USBOTG
+ /* Disable and deactivate HNP */
+#warning Missing Logic
+#endif
+ /* Acknowlege the reset interrupt */
+
+ khci_putreg(USB_INT_USBRST, KINETIS_USB0_ISTAT);
+ goto interrupt_exit;
+ }
+
+ /* Service IDLE interrupts */
+
+ if ((usbir & USB_INT_SLEEP) != 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_IDLE), usbir);
+
+#ifdef CONFIG_USBOTG
+ /* If Suspended, Try to switch to Host */
+#warning "Missing logic"
+#else
+ khci_suspend(priv);
+
+#endif
+ khci_putreg(USB_INT_SLEEP, KINETIS_USB0_ISTAT);
+ }
+
+ /* Service SOF interrupts */
+
+#ifdef CONFIG_USB_SOFINTS
+ if ((usbir & USB_INT_SOFTOK) != 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SOF), 0);
+
+ /* I am not sure why you would ever enable SOF interrupts */
+
+ khci_putreg(USB_INT_SOFTOK, KINETIS_USB0_ISTAT);
+ }
+#endif
+
+ /* Service stall interrupts */
+
+ if ((usbir & USB_INT_STALL) != 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_STALL), usbir);
+
+ khci_ep0stall(priv);
+
+ /* Clear the pending STALL interrupt */
+
+ khci_putreg(USB_INT_STALL, KINETIS_USB0_ISTAT);
+ }
+
+ /* Service error interrupts */
+
+ if ((usbir & USB_INT_ERROR) != 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_UERR), usbir);
+ uerr("ERROR: EIR=%04x\n", khci_getreg(KINETIS_USB0_ERRSTAT));
+
+ /* Clear all pending USB error interrupts */
+
+ khci_putreg(USB_EINT_ALL, KINETIS_USB0_ERRSTAT);
+ }
+
+ /* There is no point in continuing if the host has not sent a bus reset.
+ * Once bus reset is received, the device transitions into the DEFAULT
+ * state and is ready for communication.
+ */
+
+#if 0
+ if (priv->devstate < DEVSTATE_DEFAULT)
+ {
+ /* Just clear the interrupt and return */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_WAITRESET), priv->devstate);
+ goto interrupt_exit;
+ }
+#endif
+
+ /* Service USB Transaction Complete Interrupt */
+
+ if ((usbir & USB_INT_TOKDNE) != 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_TRNC), usbir);
+
+ /* Drain the USAT FIFO entries. If the USB FIFO ever gets full, USB
+ * bandwidth utilization can be compromised, and the device won't be
+ * able to receive SETUP packets.
+ */
+
+ for (i = 0; i < 4; i++)
+ {
+ uint8_t epno;
+
+ /* Check the pending interrupt register. Is token processing complete. */
+
+ if ((khci_getreg(KINETIS_USB0_ISTAT) & USB_INT_TOKDNE) != 0)
+ {
+ regval = khci_getreg(KINETIS_USB0_STAT);
+ khci_putreg(USB_INT_TOKDNE, KINETIS_USB0_ISTAT);
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_TRNCS), regval);
+
+ /* Handle the endpoint transfer complete event. */
+
+ epno = (regval & USB_STAT_ENDP_MASK) >> USB_STAT_ENDP_SHIFT;
+ if (epno == 0)
+ {
+ khci_ep0transfer(priv, regval);
+ }
+ else
+ {
+ khci_eptransfer(priv, epno, regval);
+ }
+ }
+ else
+ {
+ /* USTAT FIFO must be empty. */
+
+ break;
+ }
+ }
+ }
+
+ /* Clear the pending USB interrupt. Goto is used in the above to assure
+ * that all interrupt exists pass through this logic.
+ */
+
+interrupt_exit:
+ kinetis_clrpend(KINETIS_IRQ_USBOTG);
+ usbtrace(TRACE_INTEXIT(KHCI_TRACEINTID_INTERRUPT), usbir | otgir);
+ return OK;
+}
+
+/****************************************************************************
+ * Suspend/Resume Helpers
+ ****************************************************************************/
+/****************************************************************************
+ * Name: khci_suspend
+ ****************************************************************************/
+
+static void khci_suspend(struct khci_usbdev_s *priv)
+{
+#if 0
+ uint32_t regval;
+#endif
+
+ /* Notify the class driver of the suspend event */
+
+ if (priv->driver)
+ {
+ CLASS_SUSPEND(priv->driver, &priv->usbdev);
+ }
+
+#if 0
+ /* Enable the ACTV interrupt.
+ *
+ * NOTE: Do not clear UIRbits.ACTVIF here! Reason: ACTVIF is only
+ * generated once an IDLEIF has been generated. This is a 1:1 ratio
+ * interrupt generation. For every IDLEIF, there will be only one ACTVIF
+ * regardless of the number of subsequent bus transitions. If the ACTIF
+ * is cleared here, a problem could occur. The driver services IDLEIF
+ * first because ACTIVIE=0. If this routine clears the only ACTIVIF,
+ * then it can never get out of the suspend mode.
+ */
+
+ regval = khci_getreg(KINETIS_USB0_OTGICR);
+ regval |= USBOTG_INT_ACTV;
+ khci_putreg(regval, KINETIS_USB0_OTGICR);
+
+ /* Disable further IDLE interrupts. Once is enough. */
+
+ regval = khci_getreg(KINETIS_USB0_INTEN);
+ regval &= ~USB_INT_SLEEP;
+ khci_putreg(regval, KINETIS_USB0_INTEN);
+#endif
+
+ /* Invoke a callback into board-specific logic. The board-specific logic
+ * may enter into sleep or idle modes or switch to a slower clock, etc.
+ */
+
+ kinetis_usbsuspend((struct usbdev_s *)priv, false);
+}
+
+/****************************************************************************
+ * Name: khci_resume
+ ****************************************************************************/
+
+static void khci_resume(struct khci_usbdev_s *priv)
+{
+ irqstate_t flags;
+ uint32_t regval;
+
+ flags = enter_critical_section();
+
+ /* Start RESUME signaling */
+
+ regval = khci_getreg(KINETIS_USB0_CTL);
+ regval |= USB_CTL_RESUME;
+ khci_putreg(regval, KINETIS_USB0_CTL);
+
+ /* Keep the RESUME line set for 1-13 ms */
+
+ up_mdelay(10);
+
+ regval &= ~USB_CTL_RESUME;
+ khci_putreg(regval, KINETIS_USB0_CTL);
+
+ /* This function is called when the USB activity interrupt occurs.
+ * If using clock switching, this is the place to call out to
+ * logic to restore the original MCU core clock frequency.
+ */
+
+ kinetis_usbsuspend((struct usbdev_s *)priv, true);
+
+ /* Disable further activity interrupts */
+#if 0
+ regval = khci_getreg(KINETIS_USB0_OTGICR);
+ regval &= ~USBOTG_INT_ACTV;
+ khci_putreg(regval, KINETIS_USB0_OTGICR);
+#endif
+
+ /* The ACTVIF bit cannot be cleared immediately after the USB module wakes
+ * up from Suspend or while the USB module is suspended. A few clock cycles
+ * are required to synchronize the internal hardware state machine before
+ * the ACTIVIF bit can be cleared by firmware. Clearing the ACTVIF bit
+ * before the internal hardware is synchronized may not have an effect on
+ * the value of ACTVIF. Additionally, if the USB module uses the clock from
+ * the 96 MHz PLL source, then after clearing the SUSPND bit, the USB
+ * module may not be immediately operational while waiting for the 96 MHz
+ * PLL to lock.
+ */
+
+ khci_putreg(USB_INT_SLEEP, KINETIS_USB0_ISTAT);
+
+ /* Notify the class driver of the resume event */
+
+ if (priv->driver)
+ {
+ CLASS_RESUME(priv->driver, &priv->usbdev);
+ }
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Endpoint Helpers
+ ****************************************************************************/
+/****************************************************************************
+ * Name: khci_epreserve
+ ****************************************************************************/
+
+static inline struct khci_ep_s *
+khci_epreserve(struct khci_usbdev_s *priv, uint8_t epset)
+{
+ struct khci_ep_s *privep = NULL;
+ irqstate_t flags;
+ int epndx = 0;
+
+ flags = enter_critical_section();
+ epset &= priv->epavail;
+ if (epset)
+ {
+ /* Select the lowest bit in the set of matching, available endpoints
+ * (skipping EP0)
+ */
+
+ for (epndx = 1; epndx < KHCI_NENDPOINTS; epndx++)
+ {
+ uint8_t bit = KHCI_ENDP_BIT(epndx);
+ if ((epset & bit) != 0)
+ {
+ /* Mark the endpoint no longer available */
+
+ priv->epavail &= ~bit;
+
+ /* And return the pointer to the standard endpoint structure */
+
+ privep = &priv->eplist[epndx];
+ break;
+ }
+ }
+ }
+
+ leave_critical_section(flags);
+ return privep;
+}
+
+/****************************************************************************
+ * Name: khci_epunreserve
+ ****************************************************************************/
+
+static inline void
+khci_epunreserve(struct khci_usbdev_s *priv, struct khci_ep_s *privep)
+{
+ irqstate_t flags = enter_critical_section();
+ priv->epavail |= KHCI_ENDP_BIT(USB_EPNO(privep->ep.eplog));
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: khci_epreserved
+ ****************************************************************************/
+
+static inline bool
+khci_epreserved(struct khci_usbdev_s *priv, int epno)
+{
+ return ((priv->epavail & KHCI_ENDP_BIT(epno)) == 0);
+}
+
+/****************************************************************************
+ * Name: khci_ep0configure
+ ****************************************************************************/
+
+static void khci_ep0configure(struct khci_usbdev_s *priv)
+{
+ volatile struct usbotg_bdtentry_s *bdt;
+ struct khci_ep_s *ep0;
+ uint32_t bytecount;
+
+ /* Enable the EP0 endpoint */
+
+ khci_putreg(KHCI_EP_CONTROL, KINETIS_USB0_ENDPT0);
+
+ /* Configure the OUT BDTs. We assume that the ping-poing buffer index has
+ * just been reset and we expect to receive on the EVEN BDT first. Data
+ * toggle synchronization is not needed for SETUP packets.
+ */
+
+ ep0 = &priv->eplist[EP0];
+ bytecount = (USB_SIZEOF_CTRLREQ << USB_BDT_BYTECOUNT_SHIFT);
+
+ bdt = &g_bdt[EP0_OUT_EVEN];
+ bdt->addr = (uint8_t *)&priv->ctrl;
+ bdt->status = (USB_BDT_UOWN | bytecount);
+ ep0->bdtout = bdt;
+
+ bdt++;
+ bdt->status = (USB_BDT_UOWN | bytecount);
+ bdt->addr = (uint8_t *)&priv->ctrl;
+
+ /* Configure the IN BDTs. */
+
+ bdt = &g_bdt[EP0_IN_EVEN];
+ bdt->status = 0;
+ bdt->addr = 0;
+ ep0->bdtin = bdt;
+
+ bdt++;
+ bdt->status = 0;
+ bdt->addr = 0;
+
+ /* Data toggling is not used on SETUP transfers. And IN transfer resulting
+ * from a SETUP command should begin with DATA1.
+ */
+
+ ep0->rxdata1 = 0;
+ ep0->txdata1 = 1;
+}
+
+/****************************************************************************
+ * Endpoint operations
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: khci_epconfigure
+ ****************************************************************************/
+
+static int khci_epconfigure(struct usbdev_ep_s *ep,
+ const struct usb_epdesc_s *desc,
+ bool last)
+{
+ struct khci_ep_s *privep = (struct khci_ep_s *)ep;
+ volatile struct usbotg_bdtentry_s *bdt;
+ uint16_t maxpacket;
+ uint32_t regval;
+ uint8_t epno;
+ bool epin;
+ bool bidi;
+ int index;
+
+#ifdef CONFIG_DEBUG_FEATURES
+ if (!ep || !desc)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ uerr("ERROR: ep=%p desc=%p\n");
+ return -EINVAL;
+ }
+#endif
+
+ /* Get the unadorned endpoint address */
+
+ epno = USB_EPNO(desc->addr);
+ epin = USB_ISEPIN(desc->addr);
+
+ usbtrace(TRACE_EPCONFIGURE, (uint16_t)epno);
+ DEBUGASSERT(epno == USB_EPNO(ep->eplog));
+
+ /* Set the requested type */
+
+ switch (desc->attr & USB_EP_ATTR_XFERTYPE_MASK)
+ {
+ case USB_EP_ATTR_XFER_INT: /* Interrupt endpoint */
+ regval = epin ? KHCI_EP_INTIN : KHCI_EP_INTOUT;
+ break;
+
+ case USB_EP_ATTR_XFER_BULK: /* Bulk endpoint */
+ regval = epin ? KHCI_EP_BULKIN : KHCI_EP_BULKOUT;
+ break;
+
+ case USB_EP_ATTR_XFER_ISOC: /* Isochronous endpoint */
+ regval = epin ? KHCI_EP_ISOCIN : KHCI_EP_ISOCOUT;
+ break;
+
+ case USB_EP_ATTR_XFER_CONTROL: /* Control endpoint */
+ regval = KHCI_EP_CONTROL;
+ bidi = true;
+ break;
+
+ default:
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADEPTYPE), (uint16_t)desc->type);
+ return -EINVAL;
+ }
+
+ /* Enable the endpoint */
+
+ khci_putreg(regval, KINETIS_USB0_ENDPT(epno));
+
+ /* Setup up buffer descriptor table (BDT) entry/ies for this endpoint */
+
+ if (epin || bidi)
+ {
+ /* Get the pointer to BDT entry */
+
+ index = EP(epno, EP_DIR_IN, EP_PP_EVEN);
+ bdt = &g_bdt[index];
+ privep->bdtin = bdt;
+
+ /* Mark that we own the entry */
+
+ bdt->status = 0;
+ bdt->addr = 0;
+
+ bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n",
+ epno, bdt, bdt->status, bdt->addr);
+
+ /* Now do the same for the other buffer. */
+
+ bdt++;
+ bdt->status = 0;
+ bdt->addr = 0;
+
+ bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n",
+ epno, bdt, bdt->status, bdt->addr);
+ }
+
+ if (!epin || bidi)
+ {
+ index = EP(epno, EP_DIR_OUT, EP_PP_EVEN);
+ bdt = &g_bdt[index];
+ privep->bdtout = bdt;
+
+ /* Mark that we own the entry */
+
+ bdt->status = 0;
+ bdt->addr = 0;
+
+ bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n",
+ epno, bdt, bdt->status, bdt->addr);
+
+ /* Now do the same for the other buffer. */
+
+ bdt++;
+ bdt->status = 0;
+ bdt->addr = 0;
+
+ bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n",
+ epno, bdt, bdt->status, bdt->addr);
+ }
+
+ /* Get the maxpacket size of the endpoint. */
+
+ maxpacket = GETUINT16(desc->mxpacketsize);
+ DEBUGASSERT(maxpacket <= KHCI_MAXPACKET_SIZE);
+ ep->maxpacket = maxpacket;
+
+ /* Set the full, logic EP number (that includes direction encoded in bit 7) */
+
+ if (epin)
+ {
+ ep->eplog = USB_EPIN(epno);
+ }
+ else
+ {
+ ep->eplog = USB_EPOUT(epno);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: khci_epdisable
+ ****************************************************************************/
+
+static int khci_epdisable(struct usbdev_ep_s *ep)
+{
+ struct khci_ep_s *privep;
+ volatile uint32_t *ptr;
+ int epno;
+ int i;
+ irqstate_t flags;
+
+#ifdef CONFIG_DEBUG_FEATURES
+ if (!ep)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ uerr("ERROR: ep=%p\n", ep);
+ return -EINVAL;
+ }
+#endif
+
+ privep = (struct khci_ep_s *)ep;
+ epno = USB_EPNO(ep->eplog);
+ usbtrace(TRACE_EPDISABLE, epno);
+
+ /* Cancel any ongoing activity */
+
+ flags = enter_critical_section();
+ khci_cancelrequests(privep, -ESHUTDOWN);
+
+ /* Disable the endpoint */
+
+ khci_putreg(0, KINETIS_USB0_ENDPT(epno));
+
+ /* Reset the BDTs for the endpoint. Four BDT entries per endpoint; Two
+ * 32-bit words per BDT.
+ */
+
+ ptr = (uint32_t *)&g_bdt[EP(epno, EP_DIR_OUT, EP_PP_EVEN)];
+ for (i = 0; i < USB_BDT_WORD_SIZE * USB_NBDTS_PER_EP; i++)
+ {
+ *ptr++ = 0;
+ }
+
+ leave_critical_section(flags);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: khci_epallocreq
+ ****************************************************************************/
+
+static struct usbdev_req_s *khci_epallocreq(struct usbdev_ep_s *ep)
+{
+ struct khci_req_s *privreq;
+
+#ifdef CONFIG_DEBUG_FEATURES
+ if (!ep)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return NULL;
+ }
+#endif
+
+ usbtrace(TRACE_EPALLOCREQ, USB_EPNO(ep->eplog));
+
+ privreq = (struct khci_req_s *)kmm_malloc(sizeof(struct khci_req_s));
+ if (!privreq)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_ALLOCFAIL), 0);
+ return NULL;
+ }
+
+ memset(privreq, 0, sizeof(struct khci_req_s));
+ return &privreq->req;
+}
+
+/****************************************************************************
+ * Name: khci_epfreereq
+ ****************************************************************************/
+
+static void khci_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
+{
+ struct khci_req_s *privreq = (struct khci_req_s *)req;
+
+#ifdef CONFIG_DEBUG_FEATURES
+ if (!ep || !req)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return;
+ }
+#endif
+
+ usbtrace(TRACE_EPFREEREQ, USB_EPNO(ep->eplog));
+
+ kmm_free(privreq);
+}
+
+/****************************************************************************
+ * Name: khci_epsubmit
+ ****************************************************************************/
+
+static int khci_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
+{
+ struct khci_req_s *privreq = (struct khci_req_s *)req;
+ struct khci_ep_s *privep = (struct khci_ep_s *)ep;
+ struct khci_usbdev_s *priv;
+ irqstate_t flags;
+ uint8_t epno;
+ int ret = OK;
+
+#ifdef CONFIG_DEBUG_FEATURES
+ if (!req || !req->callback || !req->buf || !ep)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n",
+ req, req->callback, req->buf, ep);
+ return -EINVAL;
+ }
+#endif
+
+ usbtrace(TRACE_EPSUBMIT, USB_EPNO(ep->eplog));
+ priv = privep->dev;
+
+#ifdef CONFIG_DEBUG_FEATURES
+ if (!priv->driver)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
+ uerr("ERROR: driver=%p\n", priv->driver);
+ return -ESHUTDOWN;
+ }
+#endif
+
+ /* Handle the request from the class driver */
+
+ epno = USB_EPNO(ep->eplog);
+ req->result = -EINPROGRESS;
+ req->xfrd = 0;
+ privreq->inflight[0] = 0;
+#ifndef CONFIG_USBDEV_NOWRITEAHEAD
+ privreq->inflight[1] = 0;
+#endif
+ flags = enter_critical_section();
+
+ /* Add the new request to the request queue for the OUT endpoint */
+
+ khci_addlast(&privep->pend, privreq);
+
+ /* Handle IN (device-to-host) requests. NOTE: If the class device is
+ * using the bi-directional EP0, then we assume that they intend the EP0
+ * IN functionality.
+ */
+
+ if (USB_ISEPIN(ep->eplog) || epno == EP0)
+ {
+ usbtrace(TRACE_INREQQUEUED(epno), req->len);
+
+ /* If the endpoint is not stalled and an IN endpoint BDT is available,
+ * then transfer the data now.
+ */
+
+ if (!privep->stalled)
+ {
+ (void)khci_wrrequest(priv, privep);
+ }
+ }
+
+ /* Handle OUT (host-to-device) requests */
+
+ else
+ {
+ usbtrace(TRACE_OUTREQQUEUED(epno), req->len);
+
+ /* Set up the read operation (unless the endpoint is stalled). Because
+ * the KHCI supports ping-pong* buffering. There may be two pending
+ * read requests. The following call will attempt to setup a read
+ * using this request for this endpoint. It is not harmful if this
+ * fails.
+ */
+
+ if (!privep->stalled)
+ {
+ (void)khci_rdrequest(priv, privep);
+ }
+ }
+
+ leave_critical_section(flags);
+ return ret;
+}
+
+/****************************************************************************
+ * Name: khci_epcancel
+ ****************************************************************************/
+
+static int khci_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
+{
+ struct khci_ep_s *privep = (struct khci_ep_s *)ep;
+ irqstate_t flags;
+
+#ifdef CONFIG_DEBUG_FEATURES
+ if (!ep || !req)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return -EINVAL;
+ }
+#endif
+
+ usbtrace(TRACE_EPCANCEL, USB_EPNO(ep->eplog));
+
+ flags = enter_critical_section();
+ khci_cancelrequests(privep, -EAGAIN);
+ leave_critical_section(flags);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: khci_epbdtstall
+ ****************************************************************************/
+
+static int khci_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin)
+{
+ struct khci_ep_s *privep;
+ struct khci_usbdev_s *priv;
+ volatile struct usbotg_bdtentry_s *bdt;
+ volatile struct usbotg_bdtentry_s *otherbdt;
+ uint32_t regaddr;
+ uint32_t regval;
+ uint8_t epno;
+
+ /* Recover pointers */
+
+ privep = (struct khci_ep_s *)ep;
+ priv = (struct khci_usbdev_s *)privep->dev;
+ epno = USB_EPNO(ep->eplog);
+
+ /* Check for an IN endpoint */
+
+ if (epin)
+ {
+ /* Get a pointer to the current IN BDT */
+
+ bdt = privep->bdtin;
+
+ /* Get the other BDT */
+
+ otherbdt = &g_bdt[EP(epno, EP_DIR_IN, EP_PP_EVEN)];
+ if (otherbdt == bdt)
+ {
+ otherbdt++;
+ }
+
+ /* Reset the data toggle */
+
+ privep->txdata1 = false;
+ }
+
+ /* Otherwise it is an an OUT endpoint. */
+
+ else
+ {
+ /* Get a pointer to the current OUT BDT */
+
+ bdt = privep->bdtout;
+
+ /* Get a pointer to the other BDT */
+
+ otherbdt = &g_bdt[EP(epno, EP_DIR_OUT, EP_PP_EVEN)];
+ if (otherbdt == bdt)
+ {
+ otherbdt++;
+ }
+
+ /* Reset the data toggle */
+
+ privep->rxdata1 = false;
+ }
+
+ /* Handle the resume condition */
+
+ if (resume)
+ {
+ /* Resuming a stalled endpoint */
+
+ usbtrace(TRACE_EPRESUME, epno);
+
+ /* Point to the appropriate EP register */
+
+ regaddr = KINETIS_USB0_ENDPT(epno);
+
+ /* Clear the STALL bit in the UEP register */
+
+ regval = khci_getreg(regaddr);
+ regval &= ~USB_ENDPT_EPSTALL;
+ khci_putreg(regval, regaddr);
+
+ /* Check for the EP0 OUT endpoint. This is a special case because we
+ * need to set it up to receive the next setup packet (Hmmm... what
+ * if there are queued outgoing reponses. We need to revisit this.)
+ */
+
+ if (epno == 0 && !epin)
+ {
+ uint32_t bytecount = (USB_SIZEOF_CTRLREQ << USB_BDT_BYTECOUNT_SHIFT);
+ uint32_t physaddr = (uint32_t)&priv->ctrl;
+
+ /* Configure the other BDT to receive a SETUP command. */
+
+ otherbdt->addr = (uint8_t *)physaddr;
+ otherbdt->status = (USB_BDT_UOWN | bytecount);
+
+ /* Configure the current BDT to receive a SETUP command. */
+
+ bdt->addr = (uint8_t *)physaddr;
+ bdt->status = (USB_BDT_UOWN | bytecount);
+
+ bdtinfo("EP0 BDT IN [%p] {%08x, %08x}\n",
+ bdt, bdt->status, bdt->addr);
+ bdtinfo("EP0 BDT IN [%p] {%08x, %08x}\n",
+ otherbdt, otherbdt->status, otherbdt->addr);
+ }
+ else
+ {
+ /* Return the other BDT to the CPU. */
+
+ otherbdt->addr = 0;
+ otherbdt->status = 0;
+
+ /* Return the current BDT to the CPU. */
+
+ bdt->addr = 0;
+ bdt->status = 0;
+
+ bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n",
+ epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr);
+ bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n",
+ epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, otherbdt->addr);
+
+ /* Restart any queued requests (after a delay so that we can be assured
+ * that the hardware has recovered from the stall -- I don't know of any
+ * other way to assure this.).
+ */
+
+ khci_delayedrestart(priv, epno);
+ }
+ }
+
+ /* Handle the stall condition */
+
+ else
+ {
+ usbtrace(TRACE_EPSTALL, epno);
+ privep->stalled = true;
+
+ /* Stall the other BDT. */
+
+ otherbdt->status = (USB_BDT_UOWN | USB_BDT_BSTALL);
+ otherbdt->addr = 0;
+
+ /* Stall the current BDT. */
+
+ bdt->status = (USB_BDT_UOWN | USB_BDT_BSTALL);
+ bdt->addr = 0;
+
+ /* Stop any queued requests. Hmmm.. is there a race condition here? */
+
+ khci_rqstop(privep);
+
+ bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n",
+ epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr);
+ bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n",
+ epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, otherbdt->addr);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: khci_epstall
+ ****************************************************************************/
+
+static int khci_epstall(struct usbdev_ep_s *ep, bool resume)
+{
+ struct khci_ep_s *privep;
+ irqstate_t flags;
+ int ret;
+
+#ifdef CONFIG_DEBUG_FEATURES
+ if (!ep)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return -EINVAL;
+ }
+#endif
+
+ /* Recover pointers */
+
+ privep = (struct khci_ep_s *)ep;
+
+ /* STALL or RESUME the endpoint */
+
+ flags = enter_critical_section();
+
+ /* Special case EP0. When we stall EP0 we have to stall both the IN and
+ * OUT BDTs.
+ */
+
+ if (USB_EPNO(ep->eplog) == 0)
+ {
+ ret = khci_epbdtstall(ep, resume, true);
+ if (ret == OK)
+ {
+ ret = khci_epbdtstall(ep, resume, false);
+ }
+
+ /* Set the EP0 control state appropriately */
+
+ privep->dev->ctrlstate = resume ? CTRLSTATE_WAITSETUP : CTRLSTATE_STALLED;
+ }
+
+ /* Otherwise, select the BDT for the endpoint direction */
+
+ else
+ {
+ /* It is a unidirectional endpoint */
+
+ ret = khci_epbdtstall(ep, resume, USB_ISEPIN(ep->eplog));
+ }
+
+ leave_critical_section(flags);
+ return ret;
+}
+
+/****************************************************************************
+ * Device Controller Operations
+ ****************************************************************************/
+/****************************************************************************
+ * Name: khci_allocep
+ ****************************************************************************/
+
+static struct usbdev_ep_s *khci_allocep(struct usbdev_s *dev, uint8_t epno,
+ bool epin, uint8_t eptype)
+{
+ struct khci_usbdev_s *priv = (struct khci_usbdev_s *)dev;
+ struct khci_ep_s *privep = NULL;
+ uint16_t epset = KHCI_ENDP_ALLSET;
+
+ usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno);
+#ifdef CONFIG_DEBUG_FEATURES
+ if (!dev)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return NULL;
+ }
+#endif
+
+ /* Ignore any direction bits in the logical address */
+
+ epno = USB_EPNO(epno);
+
+ /* A logical address of 0 means that any endpoint will do */
+
+ if (epno > 0)
+ {
+ /* Otherwise, we will return the endpoint structure only for the requested
+ * 'logical' endpoint. All of the other checks will still be performed.
+ *
+ * First, verify that the logical endpoint is in the range supported by
+ * by the hardware.
+ */
+
+ if (epno >= KHCI_NENDPOINTS)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADEPNO), (uint16_t)epno);
+ return NULL;
+ }
+
+ /* Convert the logical address to a physical OUT endpoint address and
+ * remove all of the candidate endpoints from the bitset except for the
+ * the IN/OUT pair for this logical address.
+ */
+
+ epset = KHCI_ENDP_BIT(epno);
+ }
+
+ /* Check if the selected endpoint number is available */
+
+ privep = khci_epreserve(priv, epset);
+ if (!privep)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_EPRESERVE), (uint16_t)epset);
+ return NULL;
+ }
+
+ return &privep->ep;
+}
+
+/****************************************************************************
+ * Name: khci_freeep
+ ****************************************************************************/
+
+static void khci_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep)
+{
+ struct khci_usbdev_s *priv;
+ struct khci_ep_s *privep;
+
+#ifdef CONFIG_DEBUG_FEATURES
+ if (!dev || !ep)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return;
+ }
+#endif
+
+ priv = (struct khci_usbdev_s *)dev;
+ privep = (struct khci_ep_s *)ep;
+ usbtrace(TRACE_DEVFREEEP, (uint16_t)USB_EPNO(ep->eplog));
+ DEBUGASSERT(priv && privep);
+
+ /* Disable the endpoint */
+
+ (void)khci_epdisable(ep);
+
+ /* Mark the endpoint as available */
+
+ khci_epunreserve(priv, privep);
+}
+
+/****************************************************************************
+ * Name: khci_getframe
+ ****************************************************************************/
+
+static int khci_getframe(struct usbdev_s *dev)
+{
+ uint16_t frml;
+ uint16_t frmh;
+ uint16_t tmp;
+
+#ifdef CONFIG_DEBUG_FEATURES
+ if (!dev)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return -EINVAL;
+ }
+#endif
+
+ /* Return the last frame number detected by the hardware. Thr FRMH/L
+ * registers are updated with the current frame number whenever a SOF
+ * TOKEN is received.
+ */
+
+ do
+ {
+ /* Loop until we can be sure that there was no wrap from the FRML
+ * to the FRMH register.
+ */
+
+ frmh = khci_getreg(KINETIS_USB0_FRMNUMH) & USB_FRMNUMH_MASK;
+ frml = khci_getreg(KINETIS_USB0_FRMNUML) & USB_FRMNUML_MASK;
+ tmp = khci_getreg(KINETIS_USB0_FRMNUMH) & USB_FRMNUMH_MASK;
+ }
+ while (frmh != tmp);
+
+ /* Combine to for the full 11-bit value */
+
+ tmp = (frmh) << 8 | frml;
+ usbtrace(TRACE_DEVGETFRAME, tmp);
+ return tmp;
+}
+
+/****************************************************************************
+ * Name: khci_wakeup
+ ****************************************************************************/
+
+static int khci_wakeup(struct usbdev_s *dev)
+{
+ struct khci_usbdev_s *priv = (struct khci_usbdev_s *)dev;
+
+ usbtrace(TRACE_DEVWAKEUP, 0);
+#ifdef CONFIG_DEBUG_FEATURES
+ if (!dev)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return -EINVAL;
+ }
+#endif
+
+ /* Resume normal operation. */
+
+ khci_resume(priv);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: khci_selfpowered
+ ****************************************************************************/
+
+static int khci_selfpowered(struct usbdev_s *dev, bool selfpowered)
+{
+ struct khci_usbdev_s *priv = (struct khci_usbdev_s *)dev;
+
+ usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered);
+
+#ifdef CONFIG_DEBUG_FEATURES
+ if (!dev)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return -ENODEV;
+ }
+#endif
+
+ priv->selfpowered = selfpowered;
+ return OK;
+}
+
+/****************************************************************************
+ * Initialization/Reset
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: khci_reset
+ *
+ * Description:
+ * Reset the software and hardware states. If the USB controller has been
+ * attached to a host, then connect to the bus as well. At the end of
+ * this reset, the hardware should be in the full up, ready-to-run state.
+ *
+ ****************************************************************************/
+
+static void khci_reset(struct khci_usbdev_s *priv)
+{
+ /* Reset the software configuration */
+
+ khci_swreset(priv);
+
+ /* Re-configure the USB controller in its initial, unconnected state */
+
+ khci_hwreset(priv);
+
+ /* khci_attach() was called, then the attach flag will be set and we
+ * should also attach to the USB bus.
+ */
+
+ if (priv->attached)
+ {
+ /* usbdev_attach() has already been called.. attach to the bus
+ * now
+ */
+
+ khci_attach(priv);
+ }
+}
+
+/****************************************************************************
+ * Name: khci_attach
+ ****************************************************************************/
+
+static void khci_attach(struct khci_usbdev_s *priv)
+{
+ uint32_t regval;
+
+ /* Check if we are in the detached state */
+
+ if (priv->devstate == DEVSTATE_DETACHED)
+ {
+ /* Disable USB interrupts at the interrupt controller */
+
+ up_disable_irq(KINETIS_IRQ_USBOTG);
+
+ /* Initialize registers to known states. */
+
+#if 1
+ khci_putreg(0x1,KINETIS_USB0_CTL);
+ khci_putreg(0,KINETIS_USB0_USBCTRL);
+#endif
+
+ /* Enable interrupts at the USB controller */
+
+ khci_putreg(ERROR_INTERRUPTS, KINETIS_USB0_ERREN);
+ khci_putreg(NORMAL_INTERRUPTS, KINETIS_USB0_INTEN);
+
+ /* Configure EP0 */
+
+ khci_ep0configure(priv);
+
+ /* Flush any pending transactions */
+#if 1
+ while ((khci_getreg(KINETIS_USB0_ISTAT) & USB_INT_TOKDNE) != 0)
+ {
+ khci_putreg(USB_INT_TOKDNE, KINETIS_USB0_ISTAT);
+ }
+
+ /* Make sure packet processing is enabled */
+
+ regval = khci_getreg(KINETIS_USB0_CTL);
+ regval &= ~USB_CTL_TXSUSPENDTOKENBUSY;
+ khci_putreg(regval, KINETIS_USB0_CTL);
+
+ /* Enable the USB module and attach to bus */
+
+ do
+ {
+ regval = khci_getreg(KINETIS_USB0_CTL);
+ if ((regval & USB_CTL_USBENSOFEN) == 0)
+ {
+ khci_putreg(regval | USB_CTL_USBENSOFEN, KINETIS_USB0_CTL);
+ }
+ }
+ while ((regval & USB_CTL_USBENSOFEN) == 0);
+
+ /* Enable OTG */
+
+#ifdef CONFIG_USBOTG
+ regval = khci_getreg(KINETIS_USB0_OTGCTL);
+ regval |= (USBOTG_CON_DPPULUP | USBOTG_CON_OTGEN);
+ khci_putreg(regval, KINETIS_USB0_OTGCTL);
+#endif
+
+ /* Transition to the attached state */
+
+ priv->devstate = DEVSTATE_ATTACHED;
+ priv->usbdev.speed = USB_SPEED_FULL;
+
+ /* Clear all pending USB interrupts */
+
+ khci_putreg(USB_EINT_ALL, KINETIS_USB0_ERRSTAT);
+ khci_putreg(USB_INT_ALL, KINETIS_USB0_ISTAT);
+#endif
+
+ /* Enable USB interrupts at the interrupt controller */
+
+ up_enable_irq(KINETIS_IRQ_USBOTG);
+
+ /* Enable pull-up to connect the device. The host should enumerate us
+ * some time after this
+ */
+
+ kinetis_usbpullup(&priv->usbdev, true);
+ }
+}
+
+/****************************************************************************
+ * Name: khci_detach
+ ****************************************************************************/
+
+static void khci_detach(struct khci_usbdev_s *priv)
+{
+#ifdef CONFIG_USBOTG
+ uint32_t regval;
+#endif
+
+ /* Disable USB interrupts at the interrupt controller */
+
+ up_disable_irq(KINETIS_IRQ_USBOTG);
+
+ /* Disable the USB controller and detach from the bus. */
+
+ khci_putreg(0, KINETIS_USB0_CTL);
+
+ /* Mask all USB interrupts */
+
+ khci_putreg(0, KINETIS_USB0_INTEN);
+
+ /* We are now in the detached state */
+
+ priv->attached = 0;
+ priv->devstate = DEVSTATE_DETACHED;
+
+#ifdef CONFIG_USBOTG
+ /* Disable the D+ Pullup */
+
+ regval = khci_getreg(KINETIS_USB0_OTGCTL);
+ regval &= ~USBOTG_CON_DPPULUP;
+ khci_putreg(regval, KINETIS_USB0_OTGCTL);
+
+ /* Disable and deactivate HNP */
+#warning Missing Logic
+
+ /* Check if the ID Pin Changed State */
+
+ if ((khci_getreg(KINETIS_USB0_ISTAT) & khci_getreg(KINETIS_USB0_OTGICR) & USBOTG_INT_ID) != 0)
+ {
+ /* Re-detect & Initialize */
+#warning "Missing logic"
+
+ /* Clear ID Interrupt Flag */
+
+ khci_putreg(USBOTG_INT_ID, KINETIS_USB0_ISTAT);
+ }
+#endif
+}
+
+/****************************************************************************
+ * Name: khci_swreset
+ ****************************************************************************/
+
+static void khci_swreset(struct khci_usbdev_s *priv)
+{
+ int epno;
+
+ /* Tell the class driver that we are disconnected. The class driver
+ * should then accept any new configurations.
+ */
+
+ if (priv->driver)
+ {
+ CLASS_DISCONNECT(priv->driver, &priv->usbdev);
+ }
+
+ /* Flush and reset endpoint states (except EP0) */
+
+ for (epno = 1; epno < KHCI_NENDPOINTS; epno++)
+ {
+ struct khci_ep_s *privep = &priv->eplist[epno];
+
+ /* Cancel any queued requests. Since they are canceled
+ * with status -ESHUTDOWN, then will not be requeued
+ * until the configuration is reset. NOTE: This should
+ * not be necessary... the CLASS_DISCONNECT above should
+ * result in the class implementation calling khci_epdisable
+ * for each of its configured endpoints.
+ */
+
+ khci_cancelrequests(privep, -EAGAIN);
+
+ /* Reset endpoint status */
+
+ privep->stalled = false;
+ privep->halted = false;
+ privep->txnullpkt = false;
+ }
+
+ /* Reset to the default address */
+
+ khci_putreg(0, KINETIS_USB0_ADDR);
+
+ /* Unconfigure each endpoint by clearing the endpoint control registers
+ * (except EP0)
+ */
+
+ for (epno = 1; epno < KHCI_NENDPOINTS; epno++)
+ {
+ khci_putreg(0, KINETIS_USB0_ENDPT(epno));
+ }
+
+ /* Reset the control state */
+
+ priv->ctrlstate = CTRLSTATE_WAITSETUP;
+ priv->rxbusy = 0;
+}
+
+/****************************************************************************
+ * Name: khci_hwreset
+ *
+ * Description:
+ * Reset the hardware and leave it in a known, unready state.
+ *
+ ****************************************************************************/
+
+static void khci_hwreset(struct khci_usbdev_s *priv)
+{
+ uint32_t regval;
+
+#define USB_FLASH_ACCESS
+#ifdef USB_FLASH_ACCESS
+ /* Allow USBOTG-FS Controller to Read from FLASH */
+
+ regval = getreg32(KINETIS_FMC_PFAPR);
+ regval &= ~(FMC_PFAPR_M4AP_MASK);
+ regval |= (FMC_PFAPR_RDONLY << FMC_PFAPR_M4AP_SHIFT);
+ putreg32(regval, KINETIS_FMC_PFAPR);
+#endif
+
+ /* Clear all of the buffer descriptor table (BDT) entries */
+
+ memset((void *)g_bdt, 0, sizeof(g_bdt));
+
+ /* Soft reset the USB Module */
+
+ regval = khci_getreg(KINETIS_USB0_USBTRC0);
+ regval |= USB_USBTRC0_USBRESET;
+ khci_putreg(regval,KINETIS_USB0_USBTRC0);
+
+ /* Is this really necessary? */
+
+ while (khci_getreg(KINETIS_USB0_USBTRC0) & USB_USBTRC0_USBRESET);
+
+ /* Set the address of the buffer descriptor table (BDT)
+ *
+ * BDTP1: Bit 1-7: Bits 9-15 of the BDT base address
+ * BDTP2: Bit 0-7: Bits 16-23 of the BDT base address
+ * BDTP3: Bit 0-7: Bits 24-31 of the BDT base address
+ */
+
+ khci_putreg((uint8_t)((uint32_t)g_bdt >> 24), KINETIS_USB0_BDTPAGE3);
+ khci_putreg((uint8_t)((uint32_t)g_bdt >> 16), KINETIS_USB0_BDTPAGE2);
+ khci_putreg((uint8_t)(((uint32_t)g_bdt >> 8) & USB_BDTPAGE1_MASK), KINETIS_USB0_BDTPAGE1);
+
+ uinfo("BDT Address %hhx \n" ,&g_bdt);
+ uinfo("BDTPAGE3 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE3));
+ uinfo("BDTPAGE2 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE2));
+ uinfo("BDTPAGE1 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE1));
+
+ /* Clear any pending interrupts */
+
+ khci_putreg(0xFF, KINETIS_USB0_ERRSTAT);
+ khci_putreg(0xFF, KINETIS_USB0_ISTAT);
+ khci_putreg(0xFF,KINETIS_USB0_OTGISTAT);
+
+#if 1
+ /* Assert reset request to all of the Ping Pong buffer pointers. This
+ * will reset all Even/Odd buffer pointers to the EVEN BD banks.
+ */
+
+ regval = khci_getreg(KINETIS_USB0_CTL);
+ regval |= USB_CTL_ODDRST;
+ khci_putreg(regval, KINETIS_USB0_CTL);
+
+ /* Bring the ping pong buffer pointers out of reset */
+
+ regval &= ~USB_CTL_ODDRST;
+ khci_putreg(regval, KINETIS_USB0_CTL);
+#endif
+
+#if 1
+ /* Undocumented bit */
+
+ regval = khci_getreg(KINETIS_USB0_USBTRC0);
+ regval |= 0x40;
+ khci_putreg(regval,KINETIS_USB0_USBTRC0);
+#endif
+
+ priv->devstate = DEVSTATE_DETACHED;
+}
+
+/****************************************************************************
+ * Name: khci_stateinit
+ ****************************************************************************/
+
+static void khci_stateinit(struct khci_usbdev_s *priv)
+{
+ int epno;
+
+ /* Disconnect the device / disable the pull-up. We don't want the
+ * host to enumerate us until the class driver is registered.
+ */
+
+ kinetis_usbpullup(&priv->usbdev, false);
+
+ /* Initialize the device state structure. NOTE: many fields
+ * have the initial value of zero and, hence, are not explicitly
+ * initialized here.
+ */
+
+ memset(priv, 0, sizeof(struct khci_usbdev_s));
+ priv->usbdev.ops = &g_devops;
+ priv->usbdev.ep0 = &priv->eplist[EP0].ep;
+ priv->epavail = KHCI_ENDP_ALLSET & ~KHCI_ENDP_BIT(EP0);
+ priv->rwakeup = 1;
+
+ /* Initialize the endpoint list */
+
+ for (epno = 0; epno < KHCI_NENDPOINTS; epno++)
+ {
+ struct khci_ep_s *privep = &priv->eplist[epno];
+
+ /* Set endpoint operations, reference to driver structure (not
+ * really necessary because there is only one controller), and
+ * the (physical) endpoint number which is just the index to the
+ * endpoint.
+ */
+
+ privep->ep.ops = &g_epops;
+ privep->dev = priv;
+ privep->ep.eplog = epno;
+
+ /* We will use a fixed maxpacket size for all endpoints (perhaps
+ * ISOC endpoints could have larger maxpacket???). A smaller
+ * packet size can be selected when the endpoint is configured.
+ */
+
+ privep->ep.maxpacket = KHCI_MAXPACKET_SIZE;
+ }
+
+ /* Select a smaller endpoint size for EP0 */
+
+#if KHCI_EP0MAXPACKET < KHCI_MAXPACKET_SIZE
+ priv->eplist[EP0].ep.maxpacket = KHCI_EP0MAXPACKET;
+#endif
+}
+
+/****************************************************************************
+ * Name: khci_hwshutdown
+ ****************************************************************************/
+
+static void khci_hwshutdown(struct khci_usbdev_s *priv)
+{
+#if 0
+ uint32_t regval;
+#endif
+
+ /* Put the hardware and driver in its initial, unconnected state */
+
+ khci_swreset(priv);
+ khci_hwreset(priv);
+ priv->usbdev.speed = USB_SPEED_UNKNOWN;
+
+ /* Disable all interrupts and force the USB controller into reset */
+
+ khci_putreg(0, KINETIS_USB0_ERREN);
+ khci_putreg(0, KINETIS_USB0_INTEN);
+
+ /* Clear any pending interrupts */
+
+ khci_putreg(USB_EINT_ALL, KINETIS_USB0_ERRSTAT);
+ khci_putreg(USB_INT_ALL, KINETIS_USB0_ISTAT);
+
+ /* Disconnect the device / disable the pull-up */
+
+ kinetis_usbpullup(&priv->usbdev, false);
+
+ /* Power down the USB controller */
+#warning FIXME powerdown USB Controller
+
+#if 0
+ regval = khci_getreg(KHCI_USB_PWRC);
+ regval &= ~USB_PWRC_USBPWR;
+ khci_putreg(regval, KHCI_USB_PWRC);
+#endif
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_usbinitialize
+ *
+ * Description:
+ * Initialize the USB driver
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void up_usbinitialize(void)
+{
+ struct khci_usbdev_s *priv = &g_usbdev;
+ uint32_t regval;
+
+ /* For now there is only one USB controller, but we will always refer to
+ * it using a pointer to make any future ports to multiple USB controllers
+ * easier.
+ */
+#if 1
+ /* 1: Select clock source */
+
+ regval = getreg32(KINETIS_SIM_SOPT2);
+ regval |= SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_USBSRC;
+ putreg32(regval, KINETIS_SIM_SOPT2);
+
+ regval = getreg32(KINETIS_SIM_CLKDIV2);
+#if defined(CONFIG_TEENSY_3X_OVERCLOCK)
+ /* (USBFRAC + 0)/(USBDIV + 1) = (1 + 0)/(1 + 1) = 1/2 for 96Mhz clock */
+
+ regval = SIM_CLKDIV2_USBDIV(1);
+#else
+ /* 72Mhz */
+
+ regval = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC;
+#endif
+ putreg32(regval, KINETIS_SIM_CLKDIV2);
+
+ /* 2: Gate USB clock */
+
+ regval = getreg32(KINETIS_SIM_SCGC4);
+ regval |= SIM_SCGC4_USBOTG;
+ putreg32(regval, KINETIS_SIM_SCGC4);
+
+#endif
+
+ usbtrace(TRACE_DEVINIT, 0);
+
+ /* Initialize the driver state structure */
+
+ khci_stateinit(priv);
+
+ /* Then perform a few one-time initialization operstions. First, initialize
+ * the watchdog timer that is used to perform a delayed queue restart
+ * after recovering from a stall.
+ */
+
+ priv->epstalled = 0;
+ priv->wdog = wd_create();
+
+ /* Attach USB controller interrupt handler. The hardware will not be
+ * initialized and interrupts will not be enabled until the class device
+ * driver is bound. Getting the IRQs here only makes sure that we have
+ * them when we need them later.
+ */
+
+ if (irq_attach(KINETIS_IRQ_USBOTG, khci_interrupt) != 0)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_IRQREGISTRATION),
+ (uint16_t)KINETIS_IRQ_USBOTG);
+ up_usbuninitialize();
+ }
+
+#ifdef CONFIG_ARCH_IRQPRIO
+ /* Set the interrupt priority */
+
+ up_prioritize_irq(KINETIS_IRQ_USBOTG, 112);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_usbuninitialize
+ * Description:
+ * Initialize the USB driver
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void up_usbuninitialize(void)
+{
+ /* For now there is only one USB controller, but we will always refer to
+ * it using a pointer to make any future ports to multiple USB controllers
+ * easier.
+ */
+
+ struct khci_usbdev_s *priv = &g_usbdev;
+ irqstate_t flags;
+
+ flags = enter_critical_section();
+ usbtrace(TRACE_DEVUNINIT, 0);
+
+ /* Disable and detach the USB IRQs */
+
+ up_disable_irq(KINETIS_IRQ_USBOTG);
+ irq_detach(KINETIS_IRQ_USBOTG);
+
+ if (priv->driver)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_DRIVERREGISTERED), 0);
+ usbdev_unregister(priv->driver);
+ }
+
+ /* Put the hardware in an inactive state */
+
+ khci_hwshutdown(priv);
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: usbdev_register
+ *
+ * Description:
+ * Register a USB device class driver. The class driver's bind() method
+ * will be called to bind it to a USB device driver.
+ *
+ ****************************************************************************/
+
+int usbdev_register(struct usbdevclass_driver_s *driver)
+{
+ /* For now there is only one USB controller, but we will always refer to
+ * it using a pointer to make any future ports to multiple USB controllers
+ * easier.
+ */
+
+ struct khci_usbdev_s *priv = &g_usbdev;
+ int ret;
+
+ usbtrace(TRACE_DEVREGISTER, 0);
+
+#ifdef CONFIG_DEBUG_FEATURES
+ if (!driver || !driver->ops->bind || !driver->ops->unbind ||
+ !driver->ops->disconnect || !driver->ops->setup)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return -EINVAL;
+ }
+
+ if (priv->driver)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_DRIVER), 0);
+ return -EBUSY;
+ }
+#endif
+
+ /* First hook up the driver */
+
+ priv->driver = driver;
+
+ /* Then bind the class driver */
+
+ ret = CLASS_BIND(driver, &priv->usbdev);
+ if (ret)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BINDFAILED), (uint16_t)-ret);
+ priv->driver = NULL;
+ }
+
+ /* The class driver has been successfully bound. */
+
+ else
+ {
+ /* Setup the USB controller in it initial ready-to-run state (might
+ * be connected or unconnected, depending on usbdev_attach() has
+ * been called).
+ */
+
+ DEBUGASSERT(priv->devstate == DEVSTATE_DETACHED);
+ khci_reset(priv);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: usbdev_unregister
+ *
+ * Description:
+ * Un-register usbdev class driver. If the USB device is connected to a
+ * USB host, it will first disconnect(). The driver is also requested to
+ * unbind() and clean up any device state, before this procedure finally
+ * returns.
+ *
+ ****************************************************************************/
+
+int usbdev_unregister(struct usbdevclass_driver_s *driver)
+{
+ /* For now there is only one USB controller, but we will always refer to
+ * it using a pointer to make any future ports to multiple USB controllers
+ * easier.
+ */
+
+ struct khci_usbdev_s *priv = &g_usbdev;
+ irqstate_t flags;
+
+ usbtrace(TRACE_DEVUNREGISTER, 0);
+
+#ifdef CONFIG_DEBUG_FEATURES
+ if (driver != priv->driver)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return -EINVAL;
+ }
+#endif
+
+ /* Reset the hardware and cancel all requests. All requests must be
+ * canceled while the class driver is still bound. This will put
+ * the hardware back into its initial, unconnected state.
+ */
+
+ flags = enter_critical_section();
+ khci_swreset(priv);
+ khci_hwreset(priv);
+
+ /* Unbind the class driver */
+
+ CLASS_UNBIND(driver, &priv->usbdev);
+
+ /* Disable USB controller interrupts (but keep them attached) */
+
+ up_disable_irq(KINETIS_IRQ_USBOTG);
+
+ /* Put the hardware in an inactive state. Then bring the hardware back up
+ * in the reset state (this is probably not necessary, the khci_hwreset()
+ * call above was probably sufficient).
+ */
+
+ khci_hwshutdown(priv);
+ khci_stateinit(priv);
+
+ /* Unhook the driver */
+
+ priv->driver = NULL;
+ leave_critical_section(flags);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: khci_usbattach and khci_usbdetach
+ *
+ * Description:
+ * The USB stack must be notified when the device is attached or detached
+ * by calling one of these functions.
+ *
+ ****************************************************************************/
+
+void khci_usbattach(void)
+{
+ /* For now there is only one USB controller, but we will always refer to
+ * it using a pointer to make any future ports to multiple USB controllers
+ * easier.
+ */
+
+ struct khci_usbdev_s *priv = &g_usbdev;
+
+ /* Mark that we are attached */
+
+ priv->attached = 1;
+
+ /* This API may be called asynchronously from other initialization
+ * interfaces. In particular, we may not want to attach the bus yet...
+ * that should only be done when the class driver is attached. Has
+ * the class driver been attached?
+ */
+
+ if (priv->driver)
+ {
+ /* Yes.. then attach to the bus */
+
+ khci_attach(priv);
+ }
+}
+
+void khci_usbdetach(void)
+{
+ /* For now there is only one USB controller, but we will always refer to
+ * it using a pointer to make any future ports to multiple USB controllers
+ * easier.
+ */
+
+ struct khci_usbdev_s *priv = &g_usbdev;
+
+ /* Detach from the bus */
+
+ khci_detach(priv);
+}
+
+#endif /* CONFIG_USBDEV && CONFIG_KHCI_USB */
diff --git a/arch/arm/src/kinetis/kinetis_usbotg.h b/arch/arm/src/kinetis/kinetis_usbotg.h
index 127c718312d629bc98bd5c45cb983f650a53f6e8..de53d512933301f567c5089c9276d7480d544b7d 100644
--- a/arch/arm/src/kinetis/kinetis_usbotg.h
+++ b/arch/arm/src/kinetis/kinetis_usbotg.h
@@ -1,7 +1,7 @@
/********************************************************************************************
* arch/arm/src/kinetis/kinetis_usbotg.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -217,6 +217,8 @@
#define USB_INT_ATTACH (1 << 6) /* Bit 6: Attach Interrupt */
#define USB_INT_STALL (1 << 7) /* Bit 7: Stall Interrupt */
+#define USB_INT_ALL 0xFF
+
/* Error Interrupt Status Register and Error Interrupt Enable Register (8-bit) */
#define USB_ERRSTAT_PIDERR (1 << 0) /* Bit 0: This bit is set when the PID check field fails */
@@ -228,6 +230,8 @@
/* Bit 6: Reserved */
#define USB_ERRSTAT_BTSERR (1 << 7) /* Bit 7: Bit stuff error is detected */
+#define USB_EINT_ALL 0xBF
+
/* Status Register (8-bit) */
/* Bits 0-1: Reserved */
@@ -259,6 +263,7 @@
#define USB_BDTPAGE1_MASK (0x7f << USB_BDTPAGE1_SHIFT)
/* Frame Number Register Low (8-bit, bits 0-7 of the 11 bit frame number) */
+#define USB_FRMNUML_MASK 0xFF
/* Frame Number Register High (8-bit) */
/* Bits 3-7: Reserved */
#define USB_FRMNUMH_SHIFT (0) /* Bits 0-2: Bits 8-10 of the 11-bit frame number */
@@ -313,16 +318,58 @@
#define USB_USBTRC0_SYNC_DET (1 << 1) /* Bit 1: Synchronous USB Interrupt Detect */
#define USB_USBTRC0_RESUME_INT (1 << 0) /* Bit 0: USB Asynchronous Interrupt */
-/********************************************************************************************
+/* Buffer Descriptor Table (BDT) ****************************************************/
+/* Offset 0: On write (software->hardware) */
+
+#define USB_BDT_STATUS_MASK 0xfc /* Bits 2-7: Status bits */
+#define USB_BDT_BSTALL (1 << 2) /* Bit 2: Buffer Stall Enable bit */
+#define USB_BDT_DTS (1 << 3) /* Bit 3: Data Toggle Synchronization Enable bit */
+#define USB_BDT_NINC (1 << 4) /* Bit 4: DMA Address Increment Disable bit */
+#define USB_BDT_KEEP (1 << 5) /* Bit 5: BD Keep Enable bit */
+#define USB_BDT_DATA01 (1 << 6) /* Bit 6: Data Toggle Packet bit */
+#define USB_BDT_UOWN (1 << 7) /* Bit 7: USB Own bit */
+#define USB_BDT_BYTECOUNT_SHIFT (16) /* Bits 16-25: Byte Count bits */
+#define USB_BDT_BYTECOUNT_MASK (0x3ff << USB_BDT_BYTECOUNT_SHIFT)
+
+#define USB_BDT_DATA0 0 /* DATA0 packet expected next */
+#define USB_BDT_DATA1 USB_BDT_DATA01 /* DATA1 packet expected next */
+#define USB_BDT_COWN 0 /* CPU owns the descriptor */
+
+/* Offset 0: On read (hardware->software) */
+
+#define USB_BDT_PID_SHIFT (2) /* Bits 2-5: Packet Identifier bits */
+#define USB_BDT_PID_MASK (15 << USB_BDT_PID_SHIFT)
+ /* Bit 7: USB Own bit (same) */
+ /* Bits 16-25: Byte Count bits (same) */
+
+/* Offset 4: BUFFER_ADDRESS, 32-bit Buffer Address bits */
+
+#define USB_BDT_BYTES_SIZE 8 /* Eight bytes per BDT */
+#define USB_BDT_WORD_SIZE 2 /* Two 32-bit words per BDT */
+#define USB_NBDTS_PER_EP 4 /* Number of BDTS per endpoint: IN/OUT and EVEN/ODD */
+
+/************************************************************************************
* Public Types
- ********************************************************************************************/
+ ************************************************************************************/
-/********************************************************************************************
- * Public Data
- ********************************************************************************************/
+#ifndef __ASSEMBLY__
+
+/* Buffer Descriptor Status Register layout. */
+
+struct usbotg_bdtentry_s
+{
+ uint32_t status; /* Status, byte count, and PID */
+ uint8_t *addr; /* Buffer address */
+};
+#endif
/********************************************************************************************
* Public Functions
********************************************************************************************/
+struct usbdev_s;
+int kinetis_usbpullup(FAR struct usbdev_s *dev, bool enable);
+void kinetis_usbsuspend(FAR struct usbdev_s *dev, bool resume);
+void khci_usbattach(void);
+
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_USBOTG_H */
diff --git a/arch/arm/src/kl/Make.defs b/arch/arm/src/kl/Make.defs
index 68c58af802e470f8a565a0b55728c4d57087bfa1..105d267a73ac32ea846f1d8b2e12103b7eb02e18 100644
--- a/arch/arm/src/kl/Make.defs
+++ b/arch/arm/src/kl/Make.defs
@@ -65,12 +65,12 @@ else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
-ifeq ($(CONFIG_DEBUG),y)
+ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += up_dumpnvic.c
endif
CHIP_ASRCS =
-CHIP_CSRCS = kl_clockconfig.c kl_gpio.c kl_idle.c kl_irq.c kl_lowgetc.c
+CHIP_CSRCS = kl_clockconfig.c kl_gpio.c kl_idle.c kl_irq.c kl_getc.c
CHIP_CSRCS += kl_lowputc.c kl_serial.c kl_start.c kl_cfmconfig.c
ifneq ($(CONFIG_SCHED_TICKLESS),y)
@@ -101,6 +101,6 @@ ifeq ($(CONFIG_PWM),y)
CHIP_CSRCS += kl_pwm.c
endif
-ifeq ($(CONFIG_DEBUG),y)
+ifeq ($(CONFIG_DEBUG_FEATURES),y)
CHIP_CSRCS += kl_dumpgpio.c
endif
diff --git a/arch/arm/src/kl/kl_dumpgpio.c b/arch/arm/src/kl/kl_dumpgpio.c
index b6ea6de628318495dd17d2f5a53cd459290b736d..0e6dadfd8ef0cdacd35a067bfe759828ece1a0e4 100644
--- a/arch/arm/src/kl/kl_dumpgpio.c
+++ b/arch/arm/src/kl/kl_dumpgpio.c
@@ -39,6 +39,11 @@
#include
+/* Output debug info even if debug output is not selected. */
+
+#undef CONFIG_DEBUG_INFO
+#define CONFIG_DEBUG_INFO 1
+
#include
#include
@@ -48,14 +53,13 @@
#include "chip.h"
#include "kl_gpio.h"
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
/****************************************************************************
* Private Data
****************************************************************************/
/* Port letters for prettier debug output */
-#ifdef CONFIG_DEBUG
static const char g_portchar[KL_GPIO_NPORTS] =
{
#if KL_GPIO_NPORTS > 9
@@ -82,15 +86,6 @@ static const char g_portchar[KL_GPIO_NPORTS] =
# error "Bad number of GPIOs"
#endif
};
-#endif
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
/****************************************************************************
* Public Functions
@@ -123,14 +118,14 @@ void kl_dumpgpio(gpio_cfgset_t pinset, const char *msg)
flags = enter_critical_section();
- lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
- g_portchar[port], pinset, base, msg);
- lldbg(" PDOR: %08x PDIR: %08x PDDR: %08x\n",
- getreg32(base + KL_GPIO_PDOR_OFFSET),
- getreg32(base + KL_GPIO_PDIR_OFFSET),
- getreg32(base + KL_GPIO_PDDR_OFFSET));
+ _info("GPIO%c pinset: %08x base: %08x -- %s\n",
+ g_portchar[port], pinset, base, msg);
+ _info(" PDOR: %08x PDIR: %08x PDDR: %08x\n",
+ getreg32(base + KL_GPIO_PDOR_OFFSET),
+ getreg32(base + KL_GPIO_PDIR_OFFSET),
+ getreg32(base + KL_GPIO_PDDR_OFFSET));
leave_critical_section(flags);
}
-#endif /* CONFIG_DEBUG */
+#endif /* CONFIG_DEBUG_FEATURES */
diff --git a/arch/arm/src/kl/kl_lowgetc.c b/arch/arm/src/kl/kl_getc.c
similarity index 63%
rename from arch/arm/src/kl/kl_lowgetc.c
rename to arch/arm/src/kl/kl_getc.c
index f1c02981d2cf95761b11cd37484f27e92fc2b8aa..8b63ec217d6fe8859fc8470d6ffa1c7b03102e0a 100644
--- a/arch/arm/src/kl/kl_lowgetc.c
+++ b/arch/arm/src/kl/kl_getc.c
@@ -1,7 +1,7 @@
/****************************************************************************
- * arch/arm/src/kl/kl_lowgetc.c
+ * arch/arm/src/kl/kl_getc.c
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -41,75 +41,42 @@
#include
-#include
-#include
-
-#include "up_internal.h"
#include "up_arch.h"
#include "kl_config.h"
-#include "kl_lowgetc.h"
-
-#include "chip/kl_uart.h"
+#include "kl_getc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* Select UART parameters for the selected console */
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
# define CONSOLE_BASE KL_UART0_BASE
-# define CONSOLE_FREQ BOARD_CORECLK_FREQ
-# define CONSOLE_BAUD CONFIG_UART0_BAUD
-# define CONSOLE_BITS CONFIG_UART0_BITS
-# define CONSOLE_PARITY CONFIG_UART0_PARITY
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
# define CONSOLE_BASE KL_UART1_BASE
-# define CONSOLE_FREQ BOARD_BUSCLK_FREQ
-# define CONSOLE_BAUD CONFIG_UART1_BAUD
-# define CONSOLE_BITS CONFIG_UART1_BITS
-# define CONSOLE_PARITY CONFIG_UART1_PARITY
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
# define CONSOLE_BASE KL_UART2_BASE
-# define CONSOLE_FREQ BOARD_BUSCLK_FREQ
-# define CONSOLE_BAUD CONFIG_UART2_BAUD
-# define CONSOLE_BITS CONFIG_UART2_BITS
-# define CONSOLE_PARITY CONFIG_UART2_PARITY
#endif
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: up_lowgetc
+ * Name: up_getc
*
* Description:
* Input one byte from the serial console
*
+ * REVIST: If used with the serial driver enabled, then this could
+ * interfere with the serial driver operations. Serial interrupts should
+ * be disabled when this function executes in that case.
+ *
****************************************************************************/
-int kl_lowgetc(void)
+int up_getc(void)
{
uint8_t ch = 0;
@@ -118,11 +85,11 @@ int kl_lowgetc(void)
* we have data in the buffer to read.
*/
- while ((getreg8(CONSOLE_BASE+KL_UART_S1_OFFSET) & UART_S1_RDRF) == 0);
+ while ((getreg8(CONSOLE_BASE + KL_UART_S1_OFFSET) & UART_S1_RDRF) == 0);
/* Then read a character from the UART data register */
- ch = getreg8(CONSOLE_BASE+KL_UART_D_OFFSET);
+ ch = getreg8(CONSOLE_BASE + KL_UART_D_OFFSET);
#endif
return (int)ch;
diff --git a/arch/arm/src/kl/kl_getc.h b/arch/arm/src/kl/kl_getc.h
new file mode 100644
index 0000000000000000000000000000000000000000..aff6b2a0b37890ca8efe8725caef0cb82ff08d4a
--- /dev/null
+++ b/arch/arm/src/kl/kl_getc.h
@@ -0,0 +1,48 @@
+/************************************************************************************
+ * arch/arm/src/kl/kl_getc.h
+ *
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KL_KINETIS_GETC_H
+#define __ARCH_ARM_SRC_KL_KINETIS_GETC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include "kl_config.h"
+#include "chip/kl_uart.h"
+
+#endif /* __ARCH_ARM_SRC_KL_KINETIS_GETC_H */
diff --git a/arch/arm/src/kl/kl_idle.c b/arch/arm/src/kl/kl_idle.c
index e711b39e3c51d92765be3de3576e98aa29e5364e..f7db42f276cc89e8a4d64f6ae9c6a08e5db869de 100644
--- a/arch/arm/src/kl/kl_idle.c
+++ b/arch/arm/src/kl/kl_idle.c
@@ -103,7 +103,7 @@ static void up_idlepm(void)
/* Perform board-specific, state-dependent logic here */
- llvdbg("newstate= %d oldstate=%d\n", newstate, oldstate);
+ _info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
diff --git a/arch/arm/src/kl/kl_irq.c b/arch/arm/src/kl/kl_irq.c
index 87d47ab35c0d9f2ce06874e42bdc131730332cde..b37f7afe1c99aa98cd2c7ad88a5ff247b5b86e01 100644
--- a/arch/arm/src/kl/kl_irq.c
+++ b/arch/arm/src/kl/kl_irq.c
@@ -90,34 +90,34 @@ volatile uint32_t *g_current_regs[1];
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_IRQ)
+#if defined(CONFIG_DEBUG_IRQ_INFO)
static void kl_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
- lldbg("NVIC (%s, irq=%d):\n", msg, irq);
- lldbg(" ISER: %08x ICER: %08x\n",
- getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
- lldbg(" ISPR: %08x ICPR: %08x\n",
- getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
- lldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
- getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
- getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
- getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
-
- lldbg("SYSCON:\n");
- lldbg(" CPUID: %08x\n",
- getreg32(ARMV6M_SYSCON_CPUID));
- lldbg(" ICSR: %08x AIRCR: %08x\n",
- getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
- lldbg(" SCR: %08x CCR: %08x\n",
- getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
- lldbg(" SHPR2: %08x SHPR3: %08x\n",
- getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
+ irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
+ irqinfo(" ISER: %08x ICER: %08x\n",
+ getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
+ irqinfo(" ISPR: %08x ICPR: %08x\n",
+ getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
+ irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
+ getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
+ getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
+ getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
+
+ irqinfo("SYSCON:\n");
+ irqinfo(" CPUID: %08x\n",
+ getreg32(ARMV6M_SYSCON_CPUID));
+ irqinfo(" ICSR: %08x AIRCR: %08x\n",
+ getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
+ irqinfo(" SCR: %08x CCR: %08x\n",
+ getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
+ irqinfo(" SHPR2: %08x SHPR3: %08x\n",
+ getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
}
@@ -137,11 +137,11 @@ static void kl_dumpnvic(const char *msg, int irq)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
static int kl_nmi(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! NMI received\n");
+ _err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
@@ -149,7 +149,7 @@ static int kl_nmi(int irq, FAR void *context)
static int kl_pendsv(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! PendSV received\n");
+ _err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
@@ -157,7 +157,7 @@ static int kl_pendsv(int irq, FAR void *context)
static int kl_reserved(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Reserved interrupt\n");
+ _err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
@@ -236,7 +236,7 @@ void up_irqinitialize(void)
/* Attach all other processor exceptions (except reset and sys tick) */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
irq_attach(KL_IRQ_NMI, kl_nmi);
irq_attach(KL_IRQ_PENDSV, kl_pendsv);
irq_attach(KL_IRQ_RESERVED, kl_reserved);
diff --git a/arch/arm/src/kl/kl_pwm.c b/arch/arm/src/kl/kl_pwm.c
index c4714178e4cb03dd65a17c42946ea661cf1b283b..6f3f6e40503b5ae149b55a772db9713e3827182e 100644
--- a/arch/arm/src/kl/kl_pwm.c
+++ b/arch/arm/src/kl/kl_pwm.c
@@ -73,29 +73,10 @@
/* PWM/Timer Definitions ****************************************************/
/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing PWM */
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_PWM
-#endif
-
-#ifdef CONFIG_DEBUG_PWM
-# define pwmdbg dbg
-# define pwmlldbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define pwmvdbg vdbg
-# define pwmllvdbg llvdbg
-# define pwm_dumpgpio(p,m) kl_dumpgpio(p,m)
-# else
-# define pwmlldbg(x...)
-# define pwmllvdbg(x...)
-# define pwm_dumpgpio(p,m)
-# endif
+#ifdef CONFIG_DEBUG_PWM_INFO
+# define pwm_dumpgpio(p,m) kl_dumpgpio(p,m)
#else
-# define pwmdbg(x...)
-# define pwmlldbg(x...)
-# define pwmvdbg(x...)
-# define pwmllvdbg(x...)
# define pwm_dumpgpio(p,m)
#endif
@@ -122,7 +103,7 @@ struct kl_pwmtimer_s
static uint32_t pwm_getreg(struct kl_pwmtimer_s *priv, int offset);
static void pwm_putreg(struct kl_pwmtimer_s *priv, int offset, uint32_t value);
-#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_PWM_INFO
static void pwm_dumpregs(struct kl_pwmtimer_s *priv, FAR const char *msg);
#else
# define pwm_dumpregs(priv,msg)
@@ -253,30 +234,30 @@ static void pwm_putreg(struct kl_pwmtimer_s *priv, int offset, uint32_t value)
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_PWM_INFO
static void pwm_dumpregs(struct kl_pwmtimer_s *priv, FAR const char *msg)
{
int nchannels = (priv->tpmid == 0) ? 6 : 2;
- pwmvdbg("%s:\n", msg);
- pwmvdbg(" TPM%d_SC: %04x TPM%d_CNT: %04x TPM%d_MOD: %04x\n",
+ pwminfo("%s:\n", msg);
+ pwminfo(" TPM%d_SC: %04x TPM%d_CNT: %04x TPM%d_MOD: %04x\n",
priv->tpmid,
pwm_getreg(priv, TPM_SC_OFFSET),
priv->tpmid,
pwm_getreg(priv, TPM_CNT_OFFSET),
priv->tpmid,
pwm_getreg(priv, TPM_MOD_OFFSET));
- pwmvdbg(" TPM%d_STATUS: %04x TPM%d_CONF: %04x\n",
+ pwminfo(" TPM%d_STATUS: %04x TPM%d_CONF: %04x\n",
priv->tpmid,
pwm_getreg(priv, TPM_STATUS_OFFSET),
priv->tpmid,
pwm_getreg(priv, TPM_CONF_OFFSET));
- pwmvdbg(" TPM%d_C0SC: %04x TPM%d_C0V: %04x\n",
+ pwminfo(" TPM%d_C0SC: %04x TPM%d_C0V: %04x\n",
priv->tpmid,
pwm_getreg(priv, TPM_C0SC_OFFSET),
priv->tpmid,
pwm_getreg(priv, TPM_C0V_OFFSET));
- pwmvdbg(" TPM%d_C1SC: %04x TPM%d_C1V: %04x\n",
+ pwminfo(" TPM%d_C1SC: %04x TPM%d_C1V: %04x\n",
priv->tpmid,
pwm_getreg(priv, TPM_C1SC_OFFSET),
priv->tpmid,
@@ -284,7 +265,7 @@ static void pwm_dumpregs(struct kl_pwmtimer_s *priv, FAR const char *msg)
if (nchannels >= 3)
{
- pwmvdbg(" TPM%d_C2SC: %04x TPM%d_C2V: %04x\n",
+ pwminfo(" TPM%d_C2SC: %04x TPM%d_C2V: %04x\n",
priv->tpmid,
pwm_getreg(priv, TPM_C2SC_OFFSET),
priv->tpmid,
@@ -293,7 +274,7 @@ static void pwm_dumpregs(struct kl_pwmtimer_s *priv, FAR const char *msg)
if (nchannels >= 4)
{
- pwmvdbg(" TPM%d_C3SC: %04x TPM%d_C3V: %04x\n",
+ pwminfo(" TPM%d_C3SC: %04x TPM%d_C3V: %04x\n",
priv->tpmid,
pwm_getreg(priv, TPM_C3SC_OFFSET),
priv->tpmid,
@@ -302,7 +283,7 @@ static void pwm_dumpregs(struct kl_pwmtimer_s *priv, FAR const char *msg)
if (nchannels >= 5)
{
- pwmvdbg(" TPM%d_C4SC: %04x TPM%d_C4V: %04x\n",
+ pwminfo(" TPM%d_C4SC: %04x TPM%d_C4V: %04x\n",
priv->tpmid,
pwm_getreg(priv, TPM_C4SC_OFFSET),
priv->tpmid,
@@ -311,7 +292,7 @@ static void pwm_dumpregs(struct kl_pwmtimer_s *priv, FAR const char *msg)
if (nchannels >= 6)
{
- pwmvdbg(" TPM%d_C5SC: %04x TPM%d_C5V: %04x\n",
+ pwminfo(" TPM%d_C5SC: %04x TPM%d_C5V: %04x\n",
priv->tpmid,
pwm_getreg(priv, TPM_C5SC_OFFSET),
priv->tpmid,
@@ -353,7 +334,7 @@ static int pwm_timer(FAR struct kl_pwmtimer_s *priv,
DEBUGASSERT(priv != NULL && info != NULL);
- pwmvdbg("TPM%d channel: %d frequency: %d duty: %08x\n",
+ pwminfo("TPM%d channel: %d frequency: %d duty: %08x\n",
priv->tpmid, priv->channel, info->frequency, info->duty);
DEBUGASSERT(info->frequency > 0 && info->duty > 0 &&
@@ -423,7 +404,7 @@ static int pwm_timer(FAR struct kl_pwmtimer_s *priv,
cv = b16toi(info->duty * modulo + b16HALF);
- pwmvdbg("TPM%d PCLK: %d frequency: %d TPMCLK: %d prescaler: %d modulo: %d c0v: %d\n",
+ pwminfo("TPM%d PCLK: %d frequency: %d TPMCLK: %d prescaler: %d modulo: %d c0v: %d\n",
priv->tpmid, priv->pclk, info->frequency, tpmclk,
presc_values[prescaler], modulo, cv);
@@ -483,7 +464,7 @@ static int pwm_timer(FAR struct kl_pwmtimer_s *priv,
break;
default:
- pwmdbg("No such channel: %d\n", priv->channel);
+ pwmerr("ERROR: No such channel: %d\n", priv->channel);
return -EINVAL;
}
@@ -530,7 +511,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
regval |= SIM_SCGC6_TPM0 | SIM_SCGC6_TPM1 | SIM_SCGC6_TPM2;
putreg32(regval, KL_SIM_SCGC6);
- pwmvdbg("TPM%d pincfg: %08x\n", priv->tpmid, priv->pincfg);
+ pwminfo("TPM%d pincfg: %08x\n", priv->tpmid, priv->pincfg);
pwm_dumpregs(priv, "Initially");
/* Configure the PWM output pin, but do not start the timer yet */
@@ -561,7 +542,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
FAR struct kl_pwmtimer_s *priv = (FAR struct kl_pwmtimer_s *)dev;
uint32_t pincfg;
- pwmvdbg("TPM%d pincfg: %08x\n", priv->tpmid, priv->pincfg);
+ pwminfo("TPM%d pincfg: %08x\n", priv->tpmid, priv->pincfg);
/* Make sure that the output has been stopped */
@@ -621,7 +602,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
FAR struct kl_pwmtimer_s *priv = (FAR struct kl_pwmtimer_s *)dev;
irqstate_t flags;
- pwmvdbg("TPM%d\n", priv->tpmid);
+ pwminfo("TPM%d\n", priv->tpmid);
/* Disable interrupts momentary to stop any ongoing timer processing and
* to prevent any concurrent access to the reset register.
@@ -663,7 +644,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
break;
default:
- pwmdbg("No such channel: %d\n", priv->channel);
+ pwmerr("ERROR: No such channel: %d\n", priv->channel);
return -EINVAL;
}
@@ -691,12 +672,12 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg)
{
-#ifdef CONFIG_DEBUG_PWM
+#ifdef CONFIG_DEBUG_PWM_INFO
FAR struct kl_pwmtimer_s *priv = (FAR struct kl_pwmtimer_s *)dev;
/* There are no platform-specific ioctl commands */
- pwmvdbg("TPM%d\n", priv->tpmid);
+ pwminfo("TPM%d\n", priv->tpmid);
#endif
return -ENOTTY;
}
@@ -724,7 +705,7 @@ FAR struct pwm_lowerhalf_s *kl_pwminitialize(int timer)
{
FAR struct kl_pwmtimer_s *lower;
- pwmvdbg("TPM%d\n", timer);
+ pwminfo("TPM%d\n", timer);
switch (timer)
{
@@ -750,7 +731,7 @@ FAR struct pwm_lowerhalf_s *kl_pwminitialize(int timer)
#endif
default:
- pwmdbg("No such timer configured\n");
+ pwmerr("ERROR: No such timer configured\n");
return NULL;
}
diff --git a/arch/arm/src/kl/kl_serial.c b/arch/arm/src/kl/kl_serial.c
index fb135ca79557b979872f8868c6bcc95db781a421..fab56a34d5eaeda4f1bb5b0fbcfaa3cf6787dbd1 100644
--- a/arch/arm/src/kl/kl_serial.c
+++ b/arch/arm/src/kl/kl_serial.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/kl/kl_serial.c
*
- * Copyright (C) 2013-2012 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013-2012, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -59,15 +59,14 @@
#include "kl_config.h"
#include "kl_lowputc.h"
-#include "kl_lowgetc.h"
#include "chip.h"
#include "kl_gpio.h"
#include "chip/kl_uart.h"
-
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* Some sanity checks *******************************************************/
/* Is there at least one UART enabled and configured as a RS-232 device? */
@@ -958,18 +957,4 @@ int up_putc(int ch)
return ch;
}
-/****************************************************************************
- * Name: up_getc
- *
- * Description:
- * Provide priority, low-level access to support OS debug writes
- *
- ****************************************************************************/
-
-int up_getc(void)
-{
- /* Check for LF */
-
- return kl_lowgetc();
-}
#endif /* USE_SERIALDRIVER */
diff --git a/arch/arm/src/kl/kl_spi.c b/arch/arm/src/kl/kl_spi.c
index 0b738aedf5ea7f135d36c638cd8959fe050ecff8..e9fb9947cd48b643006189d6f0bb32da1e230cd9 100644
--- a/arch/arm/src/kl/kl_spi.c
+++ b/arch/arm/src/kl/kl_spi.c
@@ -59,29 +59,6 @@
#if defined(CONFIG_KL_SPI0) || defined(CONFIG_KL_SPI1)
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-/* Debug ********************************************************************/
-/* The following enable debug output from this file:
- *
- * CONFIG_DEBUG - Define to enable general debug features
- * CONFIG_DEBUG_SPI - Define to enable basic SSP debug (needs CONFIG_DEBUG)
- * CONFIG_DEBUG_VERBOSE - Define to enable verbose SSP debug
- */
-
-#ifdef CONFIG_DEBUG_SPI
-# define spidbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define spivdbg lldbg
-# else
-# define spivdbg(x...)
-# endif
-#else
-# define spidbg(x...)
-# define spivdbg(x...)
-#endif
-
/****************************************************************************
* Private Types
****************************************************************************/
@@ -364,7 +341,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
priv->frequency = frequency;
priv->actual = actual;
- spidbg("Frequency %d->%d\n", frequency, actual);
+ spiinfo("Frequency %d->%d\n", frequency, actual);
return actual;
}
@@ -388,7 +365,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
FAR struct kl_spidev_s *priv = (FAR struct kl_spidev_s *)dev;
uint8_t regval;
- spivdbg("mode=%d\n", mode);
+ spiinfo("mode=%d\n", mode);
/* Has the mode changed? */
@@ -519,7 +496,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
FAR uint8_t *txptr = (FAR uint8_t *)txbuffer;
uint8_t data;
- spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
+ spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
/* Loop, sending each word in the user-provied data buffer. */
@@ -585,7 +562,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
size_t nwords)
{
- spivdbg("txbuffer=%p nwords=%d\n", txbuffer, nwords);
+ spiinfo("txbuffer=%p nwords=%d\n", txbuffer, nwords);
return spi_exchange(dev, txbuffer, NULL, nwords);
}
#endif
@@ -612,7 +589,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
#ifndef CONFIG_SPI_EXCHANGE
static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, size_t nwords)
{
- spivdbg("rxbuffer=%p nwords=%d\n", rxbuffer, nwords);
+ spiinfo("rxbuffer=%p nwords=%d\n", rxbuffer, nwords);
return spi_exchange(dev, NULL, rxbuffer, nwords);
}
#endif
@@ -687,7 +664,7 @@ FAR struct spi_dev_s *kl_spibus_initialize(int port)
else
#endif
{
- spidbg("ERROR: Port %d not configured\n", port);
+ spierr("ERROR: Port %d not configured\n", port);
return NULL;
}
diff --git a/arch/arm/src/kl/kl_start.c b/arch/arm/src/kl/kl_start.c
index 63491ac74d70503d749dfb32f01c9d59e55f0173..6e9970517f57854eb7cc18986237dccbd6bd50b7 100644
--- a/arch/arm/src/kl/kl_start.c
+++ b/arch/arm/src/kl/kl_start.c
@@ -94,7 +94,7 @@ const uint32_t g_idle_topstack = IDLE_STACK;
*
****************************************************************************/
-#if defined(CONFIG_DEBUG)
+#if defined(CONFIG_DEBUG_FEATURES)
# define showprogress(c) kl_lowputc((uint32_t)c)
#else
# define showprogress(c)
diff --git a/arch/arm/src/lpc11xx/Kconfig b/arch/arm/src/lpc11xx/Kconfig
index 45bb842a302f9c4706c1b9986899e4b4ba73fc81..31a9711cf078a719d6502a45c4f9e19a5f8cd708 100644
--- a/arch/arm/src/lpc11xx/Kconfig
+++ b/arch/arm/src/lpc11xx/Kconfig
@@ -229,10 +229,11 @@ config CAN_LOOPBACK
config CAN_REGDEBUG
bool "Register level debug"
- depends on DEBUG
+ depends on DEBUG_CAN_INFO
default n
---help---
- Output detailed register-level CAN debug information. Requires also DEBUG and DEBUG_CAN.
+ Output detailed register-level CAN debug information. Requires also
+ CONFIG_DEBUG_CAN_INFO.
endmenu
diff --git a/arch/arm/src/lpc11xx/Make.defs b/arch/arm/src/lpc11xx/Make.defs
index a40c14354551c34726aea625a64d500731fd607f..041419c2488e42776cb9ed6abd3270ec76e896c7 100644
--- a/arch/arm/src/lpc11xx/Make.defs
+++ b/arch/arm/src/lpc11xx/Make.defs
@@ -65,13 +65,13 @@ else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
-ifeq ($(CONFIG_DEBUG),y)
+ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += up_dumpnvic.c
endif
CHIP_ASRCS =
CHIP_CSRCS = lpc11_clockconfig.c lpc11_gpio.c lpc11_i2c.c lpc11_idle.c
-CHIP_CSRCS += lpc11_irq.c lpc11_lowputc.c lpc11_lowgetc.c lpc11_serial.c
+CHIP_CSRCS += lpc11_irq.c lpc11_lowputc.c lpc11_getc.c lpc11_serial.c
CHIP_CSRCS += lpc11_spi.c lpc11_ssp.c lpc11_start.c
# Configuration-dependent LPC11xx files
diff --git a/arch/arm/src/lpc11xx/lpc11_lowgetc.c b/arch/arm/src/lpc11xx/lpc11_getc.c
similarity index 65%
rename from arch/arm/src/lpc11xx/lpc11_lowgetc.c
rename to arch/arm/src/lpc11xx/lpc11_getc.c
index a0a12b6108021f4ba2bf1cc1755e7d6375959985..f809e9d3438b367fb60e0dc699adb74c3f8bbd17 100644
--- a/arch/arm/src/lpc11xx/lpc11_lowgetc.c
+++ b/arch/arm/src/lpc11xx/lpc11_getc.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/lpc11/lpc11_lowgetc.c
+ * arch/arm/src/lpc11/lpc11_getc.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -41,77 +41,41 @@
#include
-#include
-#include
-
-#include "up_internal.h"
#include "up_arch.h"
-#include "chip/lpc11_syscon.h"
-#include "chip/lpc11_uart.h"
-
-#include "lpc11_gpio.h"
-#include "lpc11_lowgetc.h"
-#include "lpc11_serial.h"
+#include "lpc11_getc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* Select UART parameters for the selected console */
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
# define CONSOLE_BASE LPC11_UART0_BASE
-# define CONSOLE_FREQ BOARD_CORECLK_FREQ
-# define CONSOLE_BAUD CONFIG_UART0_BAUD
-# define CONSOLE_BITS CONFIG_UART0_BITS
-# define CONSOLE_PARITY CONFIG_UART0_PARITY
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
# define CONSOLE_BASE LPC11_UART1_BASE
-# define CONSOLE_FREQ BOARD_BUSCLK_FREQ
-# define CONSOLE_BAUD CONFIG_UART1_BAUD
-# define CONSOLE_BITS CONFIG_UART1_BITS
-# define CONSOLE_PARITY CONFIG_UART1_PARITY
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
# define CONSOLE_BASE LPC11_UART2_BASE
-# define CONSOLE_FREQ BOARD_BUSCLK_FREQ
-# define CONSOLE_BAUD CONFIG_UART2_BAUD
-# define CONSOLE_BITS CONFIG_UART2_BITS
-# define CONSOLE_PARITY CONFIG_UART2_PARITY
#endif
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: up_lowgetc
+ * Name: up_getc
*
* Description:
- * Input one byte from the serial console
+ * Input one byte from the serial console.
+ *
+ * REVIST: If used with the serial driver enabled, then this could
+ * interfere with the serial driver operations. Serial interrupts should
+ * be disabled when this function executes in that case.
*
****************************************************************************/
-int lpc11_lowgetc(void)
+int up_getc(void)
{
uint8_t ch = 0;
diff --git a/arch/arm/src/lpc11xx/lpc11_getc.h b/arch/arm/src/lpc11xx/lpc11_getc.h
new file mode 100644
index 0000000000000000000000000000000000000000..e00864bfc48b573ef4cb6a97939473b6935b05ac
--- /dev/null
+++ b/arch/arm/src/lpc11xx/lpc11_getc.h
@@ -0,0 +1,47 @@
+/************************************************************************************
+ * arch/arm/src/lpc11/lpc11_getc.h
+ *
+ * Copyright (C) 2015, 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_GETC_H
+#define __ARCH_ARM_SRC_LPC11XX_LPC11_GETC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+#include "lpc11_serial.h"
+#include "chip/lpc11_uart.h"
+
+#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_GETC_H */
diff --git a/arch/arm/src/lpc11xx/lpc11_gpio.h b/arch/arm/src/lpc11xx/lpc11_gpio.h
index 3bff062e073d7b4a1c89b0a8e3917223daaf6b5f..a0e1c2d8990d8e2dc769ac30a97c71ed03789aaa 100644
--- a/arch/arm/src/lpc11xx/lpc11_gpio.h
+++ b/arch/arm/src/lpc11xx/lpc11_gpio.h
@@ -180,7 +180,7 @@ void lpc11_gpioirqdisable(int irq);
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
int lpc11_dumpgpio(lpc11_pinset_t pinset, const char *msg);
#else
# define lpc11_dumpgpio(p,m)
diff --git a/arch/arm/src/lpc11xx/lpc11_gpiodbg.c b/arch/arm/src/lpc11xx/lpc11_gpiodbg.c
index 6be8d9c55fee4b6b11c0177cc31cdf6c17cf08f2..86b3098dcda3f98a01bc9460811cf1784982c91d 100644
--- a/arch/arm/src/lpc11xx/lpc11_gpiodbg.c
+++ b/arch/arm/src/lpc11xx/lpc11_gpiodbg.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc11xx/lpc11_gpiodbg.c
*
- * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2010-2011, 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,6 +39,11 @@
#include
+/* Output debug info even if debug output is not selected. */
+
+#undef CONFIG_DEBUG_INFO
+#define CONFIG_DEBUG_INFO 1
+
#include
#include
#include
@@ -49,23 +54,7 @@
#include "chip.h"
#include "lpc11_gpio.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_GPIO
-#endif
-
-#ifdef CONFIG_DEBUG_GPIO
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
+#ifdef CONFIG_DEBUG_GPIO_INFO
/****************************************************************************
* Private Functions
@@ -157,34 +146,34 @@ int lpc11_dumpgpio(lpc11_pinset_t pinset, const char *msg)
/* The following requires exclusive access to the GPIO registers */
flags = enter_critical_section();
- lldbg("GPIO%c pin%d (pinset: %08x) -- %s\n",
- port + '0', pin, pinset, msg);
+ gpioinfo("GPIO%c pin%d (pinset: %08x) -- %s\n",
+ port + '0', pin, pinset, msg);
#if defined(LPC176x)
- lldbg(" PINSEL[%08x]: %08x PINMODE[%08x]: %08x ODMODE[%08x]: %08x\n",
- pinsel, pinsel ? getreg32(pinsel) : 0,
- pinmode, pinmode ? getreg32(pinmode) : 0,
- g_odmode[port], getreg32(g_odmode[port]));
+ gpioinfo(" PINSEL[%08x]: %08x PINMODE[%08x]: %08x ODMODE[%08x]: %08x\n",
+ pinsel, pinsel ? getreg32(pinsel) : 0,
+ pinmode, pinmode ? getreg32(pinmode) : 0,
+ g_odmode[port], getreg32(g_odmode[port]));
#elif defined(LPC178x)
- lldbg(" IOCON[%08x]: %08x\n", iocon, getreg32(iocon));
+ gpioinfo(" IOCON[%08x]: %08x\n", iocon, getreg32(iocon));
#endif
base = g_fiobase[port];
- lldbg(" FIODIR[%08x]: %08x FIOMASK[%08x]: %08x FIOPIN[%08x]: %08x\n",
- base+LPC11_FIO_DIR_OFFSET, getreg32(base+LPC11_FIO_DIR_OFFSET),
- base+LPC11_FIO_MASK_OFFSET, getreg32(base+LPC11_FIO_MASK_OFFSET),
- base+LPC11_FIO_PIN_OFFSET, getreg32(base+LPC11_FIO_PIN_OFFSET));
+ gpioinfo(" FIODIR[%08x]: %08x FIOMASK[%08x]: %08x FIOPIN[%08x]: %08x\n",
+ base+LPC11_FIO_DIR_OFFSET, getreg32(base+LPC11_FIO_DIR_OFFSET),
+ base+LPC11_FIO_MASK_OFFSET, getreg32(base+LPC11_FIO_MASK_OFFSET),
+ base+LPC11_FIO_PIN_OFFSET, getreg32(base+LPC11_FIO_PIN_OFFSET));
base = g_intbase[port];
- lldbg(" IOINTSTATUS[%08x]: %08x INTSTATR[%08x]: %08x INSTATF[%08x]: %08x\n",
- LPC11_GPIOINT_IOINTSTATUS, getreg32(LPC11_GPIOINT_IOINTSTATUS),
- base+LPC11_GPIOINT_INTSTATR_OFFSET, getreg32(base+LPC11_GPIOINT_INTSTATR_OFFSET),
- base+LPC11_GPIOINT_INTSTATF_OFFSET, getreg32(base+LPC11_GPIOINT_INTSTATF_OFFSET));
- lldbg(" INTENR[%08x]: %08x INTENF[%08x]: %08x\n",
- base+LPC11_GPIOINT_INTENR_OFFSET, getreg32(base+LPC11_GPIOINT_INTENR_OFFSET),
- base+LPC11_GPIOINT_INTENF_OFFSET, getreg32(base+LPC11_GPIOINT_INTENF_OFFSET));
+ gpioinfo(" IOINTSTATUS[%08x]: %08x INTSTATR[%08x]: %08x INSTATF[%08x]: %08x\n",
+ LPC11_GPIOINT_IOINTSTATUS, getreg32(LPC11_GPIOINT_IOINTSTATUS),
+ base+LPC11_GPIOINT_INTSTATR_OFFSET, getreg32(base+LPC11_GPIOINT_INTSTATR_OFFSET),
+ base+LPC11_GPIOINT_INTSTATF_OFFSET, getreg32(base+LPC11_GPIOINT_INTSTATF_OFFSET));
+ gpioinfo(" INTENR[%08x]: %08x INTENF[%08x]: %08x\n",
+ base+LPC11_GPIOINT_INTENR_OFFSET, getreg32(base+LPC11_GPIOINT_INTENR_OFFSET),
+ base+LPC11_GPIOINT_INTENF_OFFSET, getreg32(base+LPC11_GPIOINT_INTENF_OFFSET));
+
leave_critical_section(flags);
return OK;
}
-#endif /* CONFIG_DEBUG_GPIO */
-
+#endif /* CONFIG_DEBUG_GPIO_INFO */
diff --git a/arch/arm/src/lpc11xx/lpc11_i2c.c b/arch/arm/src/lpc11xx/lpc11_i2c.c
index f838629fb2e50c6c217eac3f6cec0a44d4b88128..184290a602fbc3a7dad9ab122cec2a5fa615ff40 100644
--- a/arch/arm/src/lpc11xx/lpc11_i2c.c
+++ b/arch/arm/src/lpc11xx/lpc11_i2c.c
@@ -485,7 +485,7 @@ struct i2c_master_s *lpc11_i2cbus_initialize(int port)
if (port > 1)
{
- dbg("lpc I2C Only support 0,1\n");
+ i2cerr("ERROR: LPC I2C only supports ports 0 and 1\n");
return NULL;
}
diff --git a/arch/arm/src/lpc11xx/lpc11_irq.c b/arch/arm/src/lpc11xx/lpc11_irq.c
index c6daaba380de3f4595ce7c7e7b304648c8746578..f861943bc0a111522e571bc9f75b917dde8cc2f0 100644
--- a/arch/arm/src/lpc11xx/lpc11_irq.c
+++ b/arch/arm/src/lpc11xx/lpc11_irq.c
@@ -86,34 +86,34 @@ volatile uint32_t *g_current_regs[1];
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_IRQ)
+#if defined(CONFIG_DEBUG_IRQ_INFO)
static void lpc11_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
- lldbg("NVIC (%s, irq=%d):\n", msg, irq);
- lldbg(" ISER: %08x ICER: %08x\n",
- getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
- lldbg(" ISPR: %08x ICPR: %08x\n",
- getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
- lldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
- getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
- getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
- getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
-
- lldbg("SYSCON:\n");
- lldbg(" CPUID: %08x\n",
- getreg32(ARMV6M_SYSCON_CPUID));
- lldbg(" ICSR: %08x AIRCR: %08x\n",
- getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
- lldbg(" SCR: %08x CCR: %08x\n",
- getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
- lldbg(" SHPR2: %08x SHPR3: %08x\n",
- getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
+ irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
+ irqinfo(" ISER: %08x ICER: %08x\n",
+ getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
+ irqinfo(" ISPR: %08x ICPR: %08x\n",
+ getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
+ irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
+ getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
+ getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
+ getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
+
+ irqinfo("SYSCON:\n");
+ irqinfo(" CPUID: %08x\n",
+ getreg32(ARMV6M_SYSCON_CPUID));
+ irqinfo(" ICSR: %08x AIRCR: %08x\n",
+ getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
+ irqinfo(" SCR: %08x CCR: %08x\n",
+ getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
+ irqinfo(" SHPR2: %08x SHPR3: %08x\n",
+ getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
}
@@ -133,11 +133,11 @@ static void lpc11_dumpnvic(const char *msg, int irq)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
static int lpc11_nmi(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! NMI received\n");
+ _err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
@@ -145,7 +145,7 @@ static int lpc11_nmi(int irq, FAR void *context)
static int lpc11_pendsv(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! PendSV received\n");
+ _err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
@@ -153,7 +153,7 @@ static int lpc11_pendsv(int irq, FAR void *context)
static int lpc11_reserved(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Reserved interrupt\n");
+ _err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
@@ -232,7 +232,7 @@ void up_irqinitialize(void)
/* Attach all other processor exceptions (except reset and sys tick) */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
irq_attach(LPC11_IRQ_NMI, lpc11_nmi);
irq_attach(LPC11_IRQ_PENDSV, lpc11_pendsv);
irq_attach(LPC11_IRQ_RESERVED, lpc11_reserved);
diff --git a/arch/arm/src/lpc11xx/lpc11_serial.c b/arch/arm/src/lpc11xx/lpc11_serial.c
index 6bbd488a3eeda0442442d4ff86c8410c9acf0077..55c05ac51724716cc7d38f9c99ee63263dfb6397 100644
--- a/arch/arm/src/lpc11xx/lpc11_serial.c
+++ b/arch/arm/src/lpc11xx/lpc11_serial.c
@@ -64,7 +64,6 @@
#include "chip.h"
#include "chip/lpc11_uart.h"
#include "lpc11_gpio.h"
-#include "lpc11_lowgetc.h"
#include "lpc11_serial.h"
/****************************************************************************
@@ -631,7 +630,7 @@ static int up_interrupt(int irq, void *context)
/* Read the line status register (LSR) to clear */
status = up_serialin(priv, LPC11_UART_LSR_OFFSET);
- vdbg("LSR: %02x\n", status);
+ _info("LSR: %02x\n", status);
break;
}
@@ -639,7 +638,7 @@ static int up_interrupt(int irq, void *context)
default:
{
- dbg("Unexpected IIR: %02x\n", status);
+ _err("ERROR: Unexpected IIR: %02x\n", status);
break;
}
}
@@ -1041,19 +1040,4 @@ int up_putc(int ch)
return ch;
}
-/****************************************************************************
- * Name: up_getc
- *
- * Description:
- * Provide priority, low-level access to support OS debug writes
- *
- ****************************************************************************/
-
-int up_getc(void)
-{
- /* Check for LF */
-
- return lpc11_lowgetc();
-}
-
#endif /* USE_SERIALDRIVER */
diff --git a/arch/arm/src/lpc11xx/lpc11_spi.c b/arch/arm/src/lpc11xx/lpc11_spi.c
index 178bd77c3604f635383b8c4647f2e0150db39ff6..c3f9157fe5246fe8eb1d4ef8077d9503a96d629f 100644
--- a/arch/arm/src/lpc11xx/lpc11_spi.c
+++ b/arch/arm/src/lpc11xx/lpc11_spi.c
@@ -71,26 +71,6 @@
# error "CONFIG_SPI_EXCHANGE must not be defined in the configuration"
#endif
-/* Debug ********************************************************************/
-/* The following enable debug output from this file:
- *
- * CONFIG_DEBUG - Define to enable general debug features
- * CONFIG_DEBUG_SPI - Define to enable basic SSP debug (needs CONFIG_DEBUG)
- * CONFIG_DEBUG_VERBOSE - Define to enable verbose SSP debug
- */
-
-#ifdef CONFIG_DEBUG_SPI
-# define spidbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define spivdbg lldbg
-# else
-# define spivdbg(x...)
-# endif
-#else
-# define spidbg(x...)
-# define spivdbg(x...)
-#endif
-
/* SSP Clocking *************************************************************/
/* The CPU clock by 1, 2, 4, or 8 to get the SPI peripheral clock (SPI_CLOCK).
* SPI_CLOCK may be further divided by 8-254 to get the SPI clock. If we
@@ -292,7 +272,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
priv->frequency = frequency;
priv->actual = actual;
- spidbg("Frequency %d->%d\n", frequency, actual);
+ spiinfo("Frequency %d->%d\n", frequency, actual);
return actual;
}
@@ -456,7 +436,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
FAR uint8_t *ptr = (FAR uint8_t *)buffer;
uint8_t data;
- spidbg("nwords: %d\n", nwords);
+ spiinfo("nwords: %d\n", nwords);
while (nwords)
{
/* Write the data to transmitted to the SPI Data Register */
@@ -503,7 +483,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
{
FAR uint8_t *ptr = (FAR uint8_t *)buffer;
- spidbg("nwords: %d\n", nwords);
+ spiinfo("nwords: %d\n", nwords);
while (nwords)
{
/* Write some dummy data to the SPI Data Register in order to clock the
diff --git a/arch/arm/src/lpc11xx/lpc11_ssp.c b/arch/arm/src/lpc11xx/lpc11_ssp.c
index c94eac7692d0198ff318afb9fbc950c2d9466331..a5a66d862a975c104b95b478642aff3778a87ca5 100644
--- a/arch/arm/src/lpc11xx/lpc11_ssp.c
+++ b/arch/arm/src/lpc11xx/lpc11_ssp.c
@@ -72,26 +72,6 @@
# error "CONFIG_SPI_EXCHANGE must not be defined in the configuration"
#endif
-/* Debug ********************************************************************/
-/* The following enable debug output from this file:
- *
- * CONFIG_DEBUG - Define to enable general debug features
- * CONFIG_DEBUG_SPI - Define to enable basic SSP debug (needs CONFIG_DEBUG)
- * CONFIG_DEBUG_VERBOSE - Define to enable verbose SSP debug
- */
-
-#ifdef CONFIG_DEBUG_SPI
-# define sspdbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define spivdbg lldbg
-# else
-# define spivdbg(x...)
-# endif
-#else
-# define sspdbg(x...)
-# define spivdbg(x...)
-#endif
-
/* SSP Clocking *************************************************************/
#if defined(LPC111x)
@@ -474,7 +454,7 @@ static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
priv->frequency = frequency;
priv->actual = actual;
- sspdbg("Frequency %d->%d\n", frequency, actual);
+ spiinfo("Frequency %d->%d\n", frequency, actual);
return actual;
}
@@ -525,7 +505,7 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
break;
default:
- sspdbg("Bad mode: %d\n", mode);
+ spierr("ERROR: Bad mode: %d\n", mode);
DEBUGASSERT(FALSE);
return;
}
@@ -613,7 +593,7 @@ static uint16_t ssp_send(FAR struct spi_dev_s *dev, uint16_t wd)
/* Get the value from the RX FIFO and return it */
regval = ssp_getreg(priv, LPC11_SSP_DR_OFFSET);
- sspdbg("%04x->%04x\n", wd, regval);
+ spiinfo("%04x->%04x\n", wd, regval);
return (uint16_t)regval;
}
@@ -651,7 +631,7 @@ static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
/* Loop while thre are bytes remaining to be sent */
- sspdbg("nwords: %d\n", nwords);
+ spiinfo("nwords: %d\n", nwords);
u.pv = buffer;
while (nwords > 0)
{
@@ -679,7 +659,7 @@ static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
/* Then discard all card responses until the RX & TX FIFOs are emptied. */
- sspdbg("discarding\n");
+ spiinfo("discarding\n");
do
{
/* Is there anything in the RX fifo? */
@@ -744,7 +724,7 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
* occurred).
*/
- sspdbg("nwords: %d\n", nwords);
+ spiinfo("nwords: %d\n", nwords);
u.pv = buffer;
while (nwords || rxpending)
{
@@ -754,7 +734,7 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
* and (3) there are more bytes to be sent.
*/
- spivdbg("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
+ spiinfo("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
while ((ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_TNF) &&
(rxpending < LPC11_SSP_FIFOSZ) && nwords)
{
@@ -767,7 +747,7 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
* empty.
*/
- spivdbg("RX: rxpending: %d\n", rxpending);
+ spiinfo("RX: rxpending: %d\n", rxpending);
while (ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_RNE)
{
data = (uint8_t)ssp_getreg(priv, LPC11_SSP_DR_OFFSET);
diff --git a/arch/arm/src/lpc11xx/lpc11_start.c b/arch/arm/src/lpc11xx/lpc11_start.c
index 78429691490d69c6284c9e1adb74fb1133fff331..917cdeae275e6a5ef705a3e14e67293309b684c6 100644
--- a/arch/arm/src/lpc11xx/lpc11_start.c
+++ b/arch/arm/src/lpc11xx/lpc11_start.c
@@ -86,7 +86,7 @@ const uint32_t g_idle_topstack = IDLE_STACK;
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) up_lowputc(c)
#else
# define showprogress(c)
diff --git a/arch/arm/src/lpc11xx/lpc11_timer.c b/arch/arm/src/lpc11xx/lpc11_timer.c
index b9106becbcc016f8f4cd7876b470546d85746389..e742dc2de0b97ad5690f9d544edc2264769709a2 100644
--- a/arch/arm/src/lpc11xx/lpc11_timer.c
+++ b/arch/arm/src/lpc11xx/lpc11_timer.c
@@ -80,31 +80,11 @@
#define TIMTYPE_TIM1 TIMTYPE_ADVANCED
-
/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing PWM */
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_PWM
-#endif
-#ifdef CONFIG_DEBUG_PWM
-# define pwmdbg dbg
-# define pwmlldbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define pwmvdbg vdbg
-# define pwmllvdbg llvdbg
-# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
-# else
-# define pwmlldbg(x...)
-# define pwmllvdbg(x...)
-# define pwm_dumpgpio(p,m)
-# endif
+#ifdef CONFIG_DEBUG_PWM_INFO
+# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
#else
-# define pwmdbg(x...)
-# define pwmlldbg(x...)
-# define pwmvdbg(x...)
-# define pwmllvdbg(x...)
# define pwm_dumpgpio(p,m)
#endif
@@ -133,7 +113,7 @@ struct lpc11_timer_s
static uint32_t timer_getreg(struct lpc11_timer_s *priv, int offset);
static void timer_putreg(struct lpc11_timer_s *priv, int offset, uint32_t value);
-#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_PWM_INFO
static void timer_dumpregs(struct lpc11_timer_s *priv, FAR const char *msg);
#else
# define timer_dumpregs(priv,msg)
@@ -242,11 +222,11 @@ static void timer_putreg(struct lpc11_timer_s *priv, int offset,
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_PWM_INFO
static void timer_dumpregs(struct lpc11_timer_s *priv, FAR const char *msg)
{
- pwmdbg("%s:\n", msg);
- pwmdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
+ pwminfo("%s:\n", msg);
+ pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
timer_getreg(priv, LPC11_PWM_MR0_OFFSET),
timer_getreg(priv, LPC11_PWM_MR1_OFFSET),
timer_getreg(priv, LPC11_PWM_MR2_OFFSET),
@@ -254,7 +234,7 @@ static void timer_dumpregs(struct lpc11_timer_s *priv, FAR const char *msg)
#if defined(CONFIG_LPC11_TMR0)
if (priv->timtype == TIMTYPE_ADVANCED)
{
- pwmdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
+ pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
timer_getreg(priv, LPC11_PWM_MR0_OFFSET),
timer_getreg(priv, LPC11_PWM_MR1_OFFSET),
timer_getreg(priv, LPC11_PWM_MR2_OFFSET),
@@ -263,7 +243,7 @@ static void timer_dumpregs(struct lpc11_timer_s *priv, FAR const char *msg)
else
#endif
{
- pwmdbg(" DCR: %04x DMAR: %04x\n",
+ pwminfo(" DCR: %04x DMAR: %04x\n",
timer_getreg(priv, LPC11_PWM_MR2_OFFSET),
timer_getreg(priv, LPC11_PWM_MR3_OFFSET));
}
@@ -469,7 +449,7 @@ static int timer_shutdown(FAR struct pwm_lowerhalf_s *dev)
FAR struct lpc11_timer_s *priv = (FAR struct lpc11_timer_s *)dev;
uint32_t pincfg;
- pwmdbg("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg);
+ pwminfo("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg);
/* Make sure that the output has been stopped */
@@ -525,7 +505,7 @@ static int timer_stop(FAR struct pwm_lowerhalf_s *dev)
uint32_t regval;
irqstate_t flags;
- pwmdbg("TIM%d\n", priv->timid);
+ pwminfo("TIM%d\n", priv->timid);
/* Disable interrupts momentary to stop any ongoing timer processing and
* to prevent any concurrent access to the reset register.
@@ -551,7 +531,7 @@ static int timer_stop(FAR struct pwm_lowerhalf_s *dev)
leave_critical_section(flags);
- pwmdbg("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
+ pwminfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
timer_dumpregs(priv, "After stop");
return OK;
}
@@ -575,12 +555,12 @@ static int timer_stop(FAR struct pwm_lowerhalf_s *dev)
static int timer_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd,
unsigned long arg)
{
-#ifdef CONFIG_DEBUG_TIMER
+#ifdef CONFIG_DEBUG_PWM_INFO
FAR struct lpc11_timer_s *priv = (FAR struct lpc11_timer_s *)dev;
/* There are no platform-specific ioctl commands */
- pwmdbg("TIM%d\n", priv->timid);
+ pwminfo("TIM%d\n", priv->timid);
#endif
return -ENOTTY;
}
@@ -610,7 +590,7 @@ FAR struct pwm_lowerhalf_s *lpc11_timerinitialize(int timer)
{
FAR struct lpc11_timer_s *lower;
- pwmdbg("TIM%d\n", timer);
+ pwminfo("TIM%d\n", timer);
switch (timer)
{
@@ -624,7 +604,7 @@ FAR struct pwm_lowerhalf_s *lpc11_timerinitialize(int timer)
#endif
default:
- pwmdbg("No such timer configured\n");
+ pwmerr("ERROR: No such timer configured\n");
return NULL;
}
diff --git a/arch/arm/src/lpc17xx/Kconfig b/arch/arm/src/lpc17xx/Kconfig
index 4bb53068bb687b6213aad7464bb4451b31479cfb..abfd205fedcbd26c96c252541a1794164a766e33 100644
--- a/arch/arm/src/lpc17xx/Kconfig
+++ b/arch/arm/src/lpc17xx/Kconfig
@@ -594,12 +594,13 @@ config CAN_LOOPBACK
---help---
Enable CAN loopback mode
-config CAN_REGDEBUG
+config LPC17_CAN_REGDEBUG
bool "Register level debug"
- depends on DEBUG
+ depends on DEBUG_CAN_INFO
default n
---help---
- Output detailed register-level CAN debug information. Requires also DEBUG and DEBUG_CAN.
+ Output detailed register-level CAN debug information. Requires also
+ CONFIG_DEBUG_CAN_INFO.
endmenu
@@ -703,12 +704,12 @@ config NET_WOL
---help---
Enable Wake-up on Lan (not fully implemented).
-config NET_REGDEBUG
+config LPC17_NET_REGDEBUG
bool "Ethernet register-level debug"
- depends on DEBUG
+ depends on DEBUG_NET_INFO
default n
---help---
- Enable low level register debug. Also needs DEBUG.
+ Enable low level register debug. Also needs CONFIG_DEBUG_NET_INFO.
config NET_HASH
bool "Hashing"
@@ -900,10 +901,11 @@ config LPC17_USBDEV_NOLED
config LPC17_USBDEV_REGDEBUG
bool "Register level debug"
- depends on DEBUG
+ depends on DEBUG_USB_INFO
default n
---help---
- Output detailed register-level USB device debug information. Requires also DEBUG.
+ Output detailed register-level USB device debug information. Requires
+ also CONFIG_DEBUG_USB_INFO.
endmenu
@@ -976,9 +978,10 @@ config USBHOST_ISOC_DISABLE
config LPC17_USBHOST_REGDEBUG
bool "Register level debug"
- depends on DEBUG
+ depends on DEBUG_USB_INFO
default n
---help---
- Output detailed register-level USB host debug information. Requires also DEBUG.
+ Output detailed register-level USB host debug information. Requires
+ also CONFIG_DEBUG_USB_INFO.
endmenu
diff --git a/arch/arm/src/lpc17xx/Make.defs b/arch/arm/src/lpc17xx/Make.defs
index 2d6193a41d7625b116086e1e7d91e808fd4059ac..919f70e75799a37d9fc011c04a80c7136aa74a25 100644
--- a/arch/arm/src/lpc17xx/Make.defs
+++ b/arch/arm/src/lpc17xx/Make.defs
@@ -137,7 +137,7 @@ ifeq ($(CONFIG_GPIO_IRQ),y)
CHIP_CSRCS += lpc17_gpioint.c
endif
-ifeq ($(CONFIG_DEBUG_GPIO),y)
+ifeq ($(CONFIG_DEBUG_GPIO_INFO),y)
CHIP_CSRCS += lpc17_gpiodbg.c
endif
diff --git a/arch/arm/src/lpc17xx/lpc176x_rtc.c b/arch/arm/src/lpc17xx/lpc176x_rtc.c
index a0aa525ff736ccd5d172ef4e8d5ac111a781014c..8e04d2f2eba7e41f674cf0326182c0bbeaf44251 100644
--- a/arch/arm/src/lpc17xx/lpc176x_rtc.c
+++ b/arch/arm/src/lpc17xx/lpc176x_rtc.c
@@ -72,30 +72,6 @@
# error "CONFIG_RTC_HIRES must NOT be set with this driver"
#endif
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_RTC
-#endif
-
-/* Constants ************************************************************************/
-
-/* Debug ****************************************************************************/
-
-#ifdef CONFIG_DEBUG_RTC
-# define rtcdbg dbg
-# define rtcvdbg vdbg
-# define rtclldbg lldbg
-# define rtcllvdbg llvdbg
-#else
-# define rtcdbg(x...)
-# define rtcvdbg(x...)
-# define rtclldbg(x...)
-# define rtcllvdbg(x...)
-#endif
-
-/************************************************************************************
- * Private Types
- ************************************************************************************/
-
/************************************************************************************
* Private Data
************************************************************************************/
@@ -131,12 +107,12 @@ volatile bool g_rtc_enabled = false;
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_RTC
+#ifdef CONFIG_DEBUG_RTC_INFO
static void rtc_dumpregs(FAR const char *msg)
{
- rtclldbg("%s:\n", msg);
- rtclldbg(" DOM : %08x\n", (getreg32(LPC17_RTC_DOM) & RTC_DOM_MASK));
- rtclldbg(" DOW : %08x\n", (getreg32(LPC17_RTC_DOW) & RTC_DOW_MASK));
+ rtcinfo("%s:\n", msg);
+ rtcinfo(" DOM : %08x\n", (getreg32(LPC17_RTC_DOM) & RTC_DOM_MASK));
+ rtcinfo(" DOW : %08x\n", (getreg32(LPC17_RTC_DOW) & RTC_DOW_MASK));
}
#else
# define rtc_dumpregs(msg)
@@ -156,16 +132,16 @@ static void rtc_dumpregs(FAR const char *msg)
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_RTC
+#ifdef CONFIG_DEBUG_RTC_INFO
static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg)
{
- rtclldbg("%s:\n", msg);
- rtclldbg(" tm_sec: %08x\n", tp->tm_sec);
- rtclldbg(" tm_min: %08x\n", tp->tm_min);
- rtclldbg(" tm_hour: %08x\n", tp->tm_hour);
- rtclldbg(" tm_mday: %08x\n", tp->tm_mday);
- rtclldbg(" tm_mon: %08x\n", tp->tm_mon);
- rtclldbg(" tm_year: %08x\n", tp->tm_year);
+ rtcinfo("%s:\n", msg);
+ rtcinfo(" tm_sec: %08x\n", tp->tm_sec);
+ rtcinfo(" tm_min: %08x\n", tp->tm_min);
+ rtcinfo(" tm_hour: %08x\n", tp->tm_hour);
+ rtcinfo(" tm_mday: %08x\n", tp->tm_mday);
+ rtcinfo(" tm_mon: %08x\n", tp->tm_mon);
+ rtcinfo(" tm_year: %08x\n", tp->tm_year);
}
#else
# define rtc_dumptime(tp, msg)
diff --git a/arch/arm/src/lpc17xx/lpc17_can.c b/arch/arm/src/lpc17xx/lpc17_can.c
index c3949f2778e0427b0de7aae20582dd6e5ccf223f..f25de325b9f8d9e22b1d9265b9427850f86403e2 100644
--- a/arch/arm/src/lpc17xx/lpc17_can.c
+++ b/arch/arm/src/lpc17xx/lpc17_can.c
@@ -160,25 +160,8 @@
/* Debug ********************************************************************/
/* Non-standard debug that may be enabled just for testing CAN */
-#if !defined(CONFIG_DEBUG) || !defined(CONFIG_DEBUG_CAN)
-# undef CONFIG_CAN_REGDEBUG
-#endif
-
-#ifdef CONFIG_DEBUG_CAN
-# ifdef CONFIG_CAN_REGDEBUG
-# define candbg lldbg
-# define canvdbg llvdbg
-# else
-# define candbg dbg
-# define canvdbg vdbg
-# endif
-# define canlldbg lldbg
-# define canllvdbg llvdbg
-#else
-# define candbg(x...)
-# define canvdbg(x...)
-# define canlldbg(x...)
-# define canllvdbg(x...)
+#ifndef CONFIG_DEBUG_CAN_INFO
+# undef CONFIG_LPC17_CAN_REGDEBUG
#endif
/* Timing *******************************************************************/
@@ -203,14 +186,14 @@ struct up_dev_s
****************************************************************************/
/* CAN Register access */
-#ifdef CONFIG_CAN_REGDEBUG
+#ifdef CONFIG_LPC17_CAN_REGDEBUG
static void can_printreg(uint32_t addr, uint32_t value);
#endif
static uint32_t can_getreg(struct up_dev_s *priv, int offset);
static void can_putreg(struct up_dev_s *priv, int offset, uint32_t value);
-#ifdef CONFIG_CAN_REGDEBUG
+#ifdef CONFIG_LPC17_CAN_REGDEBUG
static uint32_t can_getcommon(uint32_t addr);
static void can_putcommon(uint32_t addr, uint32_t value);
#else
@@ -308,7 +291,7 @@ static struct can_dev_s g_can2dev =
*
****************************************************************************/
-#ifdef CONFIG_CAN_REGDEBUG
+#ifdef CONFIG_LPC17_CAN_REGDEBUG
static void can_printreg(uint32_t addr, uint32_t value)
{
static uint32_t prevaddr = 0;
@@ -325,7 +308,7 @@ static void can_printreg(uint32_t addr, uint32_t value)
{
if (count == 4)
{
- lldbg("...\n");
+ caninfo("...\n");
}
return;
@@ -342,7 +325,7 @@ static void can_printreg(uint32_t addr, uint32_t value)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ caninfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -354,7 +337,7 @@ static void can_printreg(uint32_t addr, uint32_t value)
/* Show the register value read */
- lldbg("%08x->%08x\n", addr, value);
+ caninfo("%08x->%08x\n", addr, value);
}
#endif
@@ -372,7 +355,7 @@ static void can_printreg(uint32_t addr, uint32_t value)
*
****************************************************************************/
-#ifdef CONFIG_CAN_REGDEBUG
+#ifdef CONFIG_LPC17_CAN_REGDEBUG
static uint32_t can_getreg(struct up_dev_s *priv, int offset)
{
uint32_t addr;
@@ -408,14 +391,14 @@ static uint32_t can_getreg(struct up_dev_s *priv, int offset)
*
****************************************************************************/
-#ifdef CONFIG_CAN_REGDEBUG
+#ifdef CONFIG_LPC17_CAN_REGDEBUG
static void can_putreg(struct up_dev_s *priv, int offset, uint32_t value)
{
uint32_t addr = priv->base + offset;
/* Show the register value being written */
- lldbg("%08x<-%08x\n", addr, value);
+ caninfo("%08x<-%08x\n", addr, value);
/* Write the value */
@@ -442,7 +425,7 @@ static void can_putreg(struct up_dev_s *priv, int offset, uint32_t value)
*
****************************************************************************/
-#ifdef CONFIG_CAN_REGDEBUG
+#ifdef CONFIG_LPC17_CAN_REGDEBUG
static uint32_t can_getcommon(uint32_t addr)
{
uint32_t value;
@@ -470,12 +453,12 @@ static uint32_t can_getcommon(uint32_t addr)
*
****************************************************************************/
-#ifdef CONFIG_CAN_REGDEBUG
+#ifdef CONFIG_LPC17_CAN_REGDEBUG
static void can_putcommon(uint32_t addr, uint32_t value)
{
/* Show the register value being written */
- lldbg("%08x<-%08x\n", addr, value);
+ caninfo("%08x<-%08x\n", addr, value);
/* Write the value */
@@ -504,7 +487,7 @@ static void can_reset(FAR struct can_dev_s *dev)
irqstate_t flags;
int ret;
- canvdbg("CAN%d\n", priv->port);
+ caninfo("CAN%d\n", priv->port);
flags = enter_critical_section();
@@ -520,7 +503,7 @@ static void can_reset(FAR struct can_dev_s *dev)
ret = can_bittiming(priv);
if (ret != OK)
{
- candbg("ERROR: Failed to set bit timing: %d\n", ret);
+ canerr("ERROR: Failed to set bit timing: %d\n", ret);
}
/* Restart the CAN */
@@ -553,18 +536,19 @@ static void can_reset(FAR struct can_dev_s *dev)
static int can_setup(FAR struct can_dev_s *dev)
{
-#ifdef CONFIG_DEBUG_CAN
+#ifdef CONFIG_DEBUG_CAN_INFO
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->cd_priv;
#endif
int ret;
- canvdbg("CAN%d\n", priv->port);
+ caninfo("CAN%d\n", priv->port);
ret = irq_attach(LPC17_IRQ_CAN, can12_interrupt);
if (ret == OK)
{
up_enable_irq(LPC17_IRQ_CAN);
}
+
return ret;
}
@@ -585,10 +569,10 @@ static int can_setup(FAR struct can_dev_s *dev)
static void can_shutdown(FAR struct can_dev_s *dev)
{
-#ifdef CONFIG_DEBUG_CAN
+#ifdef CONFIG_DEBUG_CAN_INFO
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->cd_priv;
- canvdbg("CAN%d\n", priv->port);
+ caninfo("CAN%d\n", priv->port);
#endif
up_disable_irq(LPC17_IRQ_CAN);
@@ -615,7 +599,7 @@ static void can_rxint(FAR struct can_dev_s *dev, bool enable)
uint32_t regval;
irqstate_t flags;
- canvdbg("CAN%d enable: %d\n", priv->port, enable);
+ caninfo("CAN%d enable: %d\n", priv->port, enable);
/* The EIR register is also modifed from the interrupt handler, so we have
* to protect this code section.
@@ -656,7 +640,7 @@ static void can_txint(FAR struct can_dev_s *dev, bool enable)
uint32_t regval;
irqstate_t flags;
- canvdbg("CAN%d enable: %d\n", priv->port, enable);
+ caninfo("CAN%d enable: %d\n", priv->port, enable);
/* Only disabling of the TX interrupt is supported here. The TX interrupt
* is automatically enabled just before a message is sent in order to avoid
@@ -697,7 +681,7 @@ static void can_txint(FAR struct can_dev_s *dev, bool enable)
static int can_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg)
{
- dbg("Fix me:Not Implemented\n");
+ canerr("ERROR: Fix me -- Not Implemented\n");
return 0;
}
@@ -717,7 +701,7 @@ static int can_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg)
static int can_remoterequest(FAR struct can_dev_s *dev, uint16_t id)
{
- dbg("Fix me:Not Implemented\n");
+ canerr("ERROR: Fix me -- Not Implemented\n");
return 0;
}
@@ -753,7 +737,7 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
irqstate_t flags;
int ret = OK;
- canvdbg("CAN%d ID: %d DLC: %d\n",
+ caninfo("CAN%d ID: %d DLC: %d\n",
priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
if (msg->cm_hdr.ch_rtr)
@@ -878,7 +862,7 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
}
else
{
- candbg("No available transmission buffer, SR: %08x\n", regval);
+ canerr("ERROR: No available transmission buffer, SR: %08x\n", regval);
ret = -EBUSY;
}
@@ -958,7 +942,7 @@ static void can_interrupt(FAR struct can_dev_s *dev)
/* Read the interrupt and capture register (also clearing most status bits) */
regval = can_getreg(priv, LPC17_CAN_ICR_OFFSET);
- canllvdbg("CAN%d ICR: %08x\n", priv->port, regval);
+ caninfo("CAN%d ICR: %08x\n", priv->port, regval);
/* Check for a receive interrupt */
@@ -988,7 +972,7 @@ static void can_interrupt(FAR struct can_dev_s *dev)
if ((rfs & CAN_RFS_FF) != 0)
{
- canlldbg("ERROR: Received message with extended identifier. Dropped\n");
+ canerr("ERROR: Received message with extended identifier. Dropped\n");
}
else
#endif
@@ -1065,7 +1049,7 @@ static int can12_interrupt(int irq, void *context)
{
/* Handle CAN1/2 interrupts */
- canllvdbg("irq: %d\n", irq);
+ caninfo("irq: %d\n", irq);
#ifdef CONFIG_LPC17_CAN1
can_interrupt(&g_can1dev);
@@ -1142,8 +1126,8 @@ static int can_bittiming(struct up_dev_s *priv)
uint32_t ts2;
uint32_t sjw;
- canllvdbg("CAN%d PCLK: %d baud: %d\n", priv->port,
- CAN_CLOCK_FREQUENCY(priv->divisor), priv->baud);
+ caninfo("CAN%d PCLK: %d baud: %d\n", priv->port,
+ CAN_CLOCK_FREQUENCY(priv->divisor), priv->baud);
/* Try to get CAN_BIT_QUANTA quanta in one bit_time.
*
@@ -1195,7 +1179,7 @@ static int can_bittiming(struct up_dev_s *priv)
sjw = 1;
- canllvdbg("TS1: %d TS2: %d BRP: %d SJW= %d\n", ts1, ts2, brp, sjw);
+ caninfo("TS1: %d TS2: %d BRP: %d SJW= %d\n", ts1, ts2, brp, sjw);
/* Configure bit timing */
@@ -1212,7 +1196,7 @@ static int can_bittiming(struct up_dev_s *priv)
btr |= CAN_BTR_SAM;
#endif
- canllvdbg("Setting CANxBTR= 0x%08x\n", btr);
+ caninfo("Setting CANxBTR= 0x%08x\n", btr);
can_putreg(priv, LPC17_CAN_BTR_OFFSET, btr); /* Set bit timing */
return OK;
}
@@ -1240,7 +1224,7 @@ FAR struct can_dev_s *lpc17_caninitialize(int port)
irqstate_t flags;
uint32_t regval;
- canllvdbg("CAN%d\n", port);
+ caninfo("CAN%d\n", port);
flags = enter_critical_section();
@@ -1299,7 +1283,7 @@ FAR struct can_dev_s *lpc17_caninitialize(int port)
else
#endif
{
- candbg("Unsupported port: %d\n", port);
+ canerr("ERROR: Unsupported port: %d\n", port);
leave_critical_section(flags);
return NULL;
}
diff --git a/arch/arm/src/lpc17xx/lpc17_dac.c b/arch/arm/src/lpc17xx/lpc17_dac.c
index d5100c5e50a443eacd766e4b5508980de71201e3..003d6092664620401d2d9356ef201b915b0024ce 100644
--- a/arch/arm/src/lpc17xx/lpc17_dac.c
+++ b/arch/arm/src/lpc17xx/lpc17_dac.c
@@ -170,9 +170,9 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
/* All ioctl calls will be routed through this method */
-static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg)
+static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg)
{
- dbg("Fix me:Not Implemented\n");
+ aerr("ERROR: Fix me -- Not Implemented\n");
return 0;
}
diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.c b/arch/arm/src/lpc17xx/lpc17_ethernet.c
index 4bc992d2ce9cf440c3a38deeb694361a504ba149..13730506821648d46e4bcbbd6437d1ebf4a470f5 100644
--- a/arch/arm/src/lpc17xx/lpc17_ethernet.c
+++ b/arch/arm/src/lpc17xx/lpc17_ethernet.c
@@ -127,17 +127,17 @@
#endif
/* Debug Configuration *****************************************************/
-/* Register debug -- can only happen of CONFIG_DEBUG is selected */
+/* Register debug -- can only happen of CONFIG_DEBUG_NET_INFO is selected */
-#ifndef CONFIG_DEBUG
-# undef CONFIG_NET_REGDEBUG
+#ifndef CONFIG_DEBUG_NET_INFO
+# undef CONFIG_LPC17_NET_REGDEBUG
#endif
/* CONFIG_NET_DUMPPACKET will dump the contents of each packet to the
* console.
*/
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_NET_INFO
# undef CONFIG_NET_DUMPPACKET
#endif
@@ -301,7 +301,7 @@ static const uint16_t g_enetpins[GPIO_NENET_PINS] =
/* Register operations */
-#ifdef CONFIG_NET_REGDEBUG
+#ifdef CONFIG_LPC17_NET_REGDEBUG
static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite);
static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite);
static uint32_t lpc17_getreg(uint32_t addr);
@@ -365,7 +365,7 @@ static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac);
/* Initialization functions */
-#if defined(CONFIG_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO)
+#if defined(CONFIG_LPC17_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO)
static void lpc17_showpins(void);
#else
# define lpc17_showpins()
@@ -374,7 +374,7 @@ static void lpc17_showpins(void);
/* PHY initialization functions */
#ifdef LPC17_HAVE_PHY
-# ifdef CONFIG_NET_REGDEBUG
+# ifdef CONFIG_LPC17_NET_REGDEBUG
static void lpc17_showmii(uint8_t phyaddr, const char *msg);
# else
# define lpc17_showmii(phyaddr,msg)
@@ -412,10 +412,10 @@ static void lpc17_ethreset(struct lpc17_driver_s *priv);
*
****************************************************************************/
-#ifdef CONFIG_NET_REGDEBUG
+#ifdef CONFIG_LPC17_NET_REGDEBUG
static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite)
{
- dbg("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
+ ninfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
}
#endif
@@ -427,7 +427,7 @@ static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite)
*
****************************************************************************/
-#ifdef CONFIG_NET_REGDEBUG
+#ifdef CONFIG_LPC17_NET_REGDEBUG
static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite)
{
static uint32_t prevaddr = 0;
@@ -465,7 +465,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite)
{
/* No.. More than one. */
- dbg("[repeats %d more times]\n", count);
+ ninfo("[repeats %d more times]\n", count);
}
}
@@ -491,7 +491,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite)
*
****************************************************************************/
-#ifdef CONFIG_NET_REGDEBUG
+#ifdef CONFIG_LPC17_NET_REGDEBUG
static uint32_t lpc17_getreg(uint32_t addr)
{
/* Read the value from the register */
@@ -513,7 +513,7 @@ static uint32_t lpc17_getreg(uint32_t addr)
*
****************************************************************************/
-#ifdef CONFIG_NET_REGDEBUG
+#ifdef CONFIG_LPC17_NET_REGDEBUG
static void lpc17_putreg(uint32_t val, uint32_t addr)
{
/* Check if we need to print this value */
@@ -837,8 +837,8 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv)
if ((*rxstat & RXSTAT_INFO_ERROR) != 0)
{
- nlldbg("Error. considx: %08x prodidx: %08x rxstat: %08x\n",
- considx, prodidx, *rxstat);
+ nerr("ERROR: considx: %08x prodidx: %08x rxstat: %08x\n",
+ considx, prodidx, *rxstat);
NETDEV_RXERRORS(&priv->lp_dev);
}
@@ -850,21 +850,21 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv)
/* else */ if (pktlen > CONFIG_NET_ETH_MTU + CONFIG_NET_GUARDSIZE)
{
- nlldbg("Too big. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n",
- considx, prodidx, pktlen, *rxstat);
+ nwarn("WARNING: Too big. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n",
+ considx, prodidx, pktlen, *rxstat);
NETDEV_RXERRORS(&priv->lp_dev);
}
else if ((*rxstat & RXSTAT_INFO_LASTFLAG) == 0)
{
- nlldbg("Fragment. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n",
- considx, prodidx, pktlen, *rxstat);
+ ninfo("Fragment. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n",
+ considx, prodidx, pktlen, *rxstat);
NETDEV_RXFRAGMENTS(&priv->lp_dev);
fragment = true;
}
else if (fragment)
{
- nlldbg("Last fragment. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n",
- considx, prodidx, pktlen, *rxstat);
+ ninfo("Last fragment. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n",
+ considx, prodidx, pktlen, *rxstat);
NETDEV_RXFRAGMENTS(&priv->lp_dev);
fragment = false;
}
@@ -906,7 +906,7 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
- nllvdbg("IPv4 frame\n");
+ ninfo("IPv4 frame\n");
NETDEV_RXIPV4(&priv->lp_dev);
/* Handle ARP on input then give the IPv4 packet to the
@@ -948,7 +948,7 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
- nllvdbg("Iv6 frame\n");
+ ninfo("Iv6 frame\n");
NETDEV_RXIPV6(&priv->lp_dev);
/* Give the IPv6 packet to the network layer */
@@ -1202,13 +1202,13 @@ static int lpc17_interrupt(int irq, void *context)
{
if ((status & ETH_INT_RXOVR) != 0)
{
- nlldbg("RX Overrun. status: %08x\n", status);
+ nerr("ERROR: RX Overrun. status: %08x\n", status);
NETDEV_RXERRORS(&priv->lp_dev);
}
if ((status & ETH_INT_TXUNR) != 0)
{
- nlldbg("TX Underrun. status: %08x\n", status);
+ nerr("ERROR: TX Underrun. status: %08x\n", status);
NETDEV_TXERRORS(&priv->lp_dev);
}
@@ -1229,7 +1229,7 @@ static int lpc17_interrupt(int irq, void *context)
if ((status & ETH_INT_RXERR) != 0)
{
- nlldbg("RX Error. status: %08x\n", status);
+ nerr("ERROR: RX ERROR: status: %08x\n", status);
NETDEV_RXERRORS(&priv->lp_dev);
}
@@ -1281,7 +1281,7 @@ static int lpc17_interrupt(int irq, void *context)
if ((status & ETH_INT_TXERR) != 0)
{
- nlldbg("TX Error. status: %08x\n", status);
+ nerr("ERROR: TX ERROR: status: %08x\n", status);
NETDEV_TXERRORS(&priv->lp_dev);
}
@@ -1671,7 +1671,7 @@ static void lpc17_ipv6multicast(FAR struct lpc17_driver_s *priv)
mac[4] = tmp16 & 0xff;
mac[5] = tmp16 >> 8;
- nvdbg("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
(void)lpc17_addmac(dev, mac);
@@ -1720,9 +1720,9 @@ static int lpc17_ifup(struct net_driver_s *dev)
uint32_t regval;
int ret;
- ndbg("Bringing up: %d.%d.%d.%d\n",
- dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
- (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+ ninfo("Bringing up: %d.%d.%d.%d\n",
+ dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+ (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
/* Reset the Ethernet controller (again) */
@@ -1733,7 +1733,7 @@ static int lpc17_ifup(struct net_driver_s *dev)
ret = lpc17_phyinit(priv);
if (ret != 0)
{
- ndbg("lpc17_phyinit failed: %d\n", ret);
+ nerr("ERROR: lpc17_phyinit failed: %d\n", ret);
return ret;
}
@@ -2145,8 +2145,8 @@ static int lpc17_addmac(struct net_driver_s *dev, const uint8_t *mac)
uint32_t crc;
unsigned int ndx;
- nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Hash function:
*
@@ -2221,8 +2221,8 @@ static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac)
uint32_t crc;
unsigned int ndx;
- nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Hash function:
*
@@ -2292,7 +2292,7 @@ static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac)
*
****************************************************************************/
-#if defined(CONFIG_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO)
+#if defined(CONFIG_LPC17_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO)
static void lpc17_showpins(void)
{
lpc17_dumpgpio(GPIO_PORT1 | GPIO_PIN0, "P1[1-15]");
@@ -2316,17 +2316,17 @@ static void lpc17_showpins(void)
*
****************************************************************************/
-#if defined(CONFIG_NET_REGDEBUG) && defined(LPC17_HAVE_PHY)
+#if defined(CONFIG_LPC17_NET_REGDEBUG) && defined(LPC17_HAVE_PHY)
static void lpc17_showmii(uint8_t phyaddr, const char *msg)
{
- dbg("PHY " LPC17_PHYNAME ": %s\n", msg);
- dbg(" MCR: %04x\n", lpc17_phyread(phyaddr, MII_MCR));
- dbg(" MSR: %04x\n", lpc17_phyread(phyaddr, MII_MSR));
- dbg(" ADVERTISE: %04x\n", lpc17_phyread(phyaddr, MII_ADVERTISE));
- dbg(" LPA: %04x\n", lpc17_phyread(phyaddr, MII_LPA));
- dbg(" EXPANSION: %04x\n", lpc17_phyread(phyaddr, MII_EXPANSION));
+ ninfo("PHY " LPC17_PHYNAME ": %s\n", msg);
+ ninfo(" MCR: %04x\n", lpc17_phyread(phyaddr, MII_MCR));
+ ninfo(" MSR: %04x\n", lpc17_phyread(phyaddr, MII_MSR));
+ ninfo(" ADVERTISE: %04x\n", lpc17_phyread(phyaddr, MII_ADVERTISE));
+ ninfo(" LPA: %04x\n", lpc17_phyread(phyaddr, MII_LPA));
+ ninfo(" EXPANSION: %04x\n", lpc17_phyread(phyaddr, MII_EXPANSION));
#ifdef CONFIG_ETH0_PHY_KS8721
- dbg(" 10BTCR: %04x\n", lpc17_phyread(phyaddr, MII_KS8721_10BTCR));
+ ninfo(" 10BTCR: %04x\n", lpc17_phyread(phyaddr, MII_KS8721_10BTCR));
#endif
}
#endif
@@ -2462,7 +2462,7 @@ static inline int lpc17_phyreset(uint8_t phyaddr)
}
}
- ndbg("Reset failed. MCR: %04x\n", phyreg);
+ nerr("ERROR: Reset failed. MCR: %04x\n", phyreg);
return -ETIMEDOUT;
}
#endif
@@ -2509,7 +2509,7 @@ static inline int lpc17_phyautoneg(uint8_t phyaddr)
}
}
- ndbg("Auto-negotiation failed. MSR: %04x\n", phyreg);
+ nerr("ERROR: Auto-negotiation failed. MSR: %04x\n", phyreg);
return -ETIMEDOUT;
}
#endif
@@ -2593,7 +2593,7 @@ static int lpc17_phymode(uint8_t phyaddr, uint8_t mode)
#endif
}
- ndbg("Link failed. MSR: %04x\n", phyreg);
+ nerr("ERROR: Link failed. MSR: %04x\n", phyreg);
return -ETIMEDOUT;
}
#endif
@@ -2647,20 +2647,20 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
*/
phyreg = (unsigned int)lpc17_phyread(phyaddr, MII_PHYID1);
- nvdbg("Addr: %d PHY ID1: %04x\n", phyaddr, phyreg);
+ ninfo("Addr: %d PHY ID1: %04x\n", phyaddr, phyreg);
/* Compare OUI bits 3-18 */
if (phyreg == LPC17_PHYID1)
{
phyreg = lpc17_phyread(phyaddr, MII_PHYID2);
- nvdbg("Addr: %d PHY ID2: %04x\n", phyaddr, phyreg);
+ ninfo("Addr: %d PHY ID2: %04x\n", phyaddr, phyreg);
/* Compare OUI bits 19-24 and the 6-bit model number (ignoring the
* 4-bit revision number).
*/
- if ((phyreg & 0xfff0) == LPC17_PHYID2)
+ if ((phyreg & 0xfff0) == (LPC17_PHYID2 & 0xfff0))
{
break;
}
@@ -2673,10 +2673,10 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
{
/* Failed to find PHY at any location */
- ndbg("No PHY detected\n");
+ nerr("ERROR: No PHY detected\n");
return -ENODEV;
}
- nvdbg("phyaddr: %d\n", phyaddr);
+ ninfo("phyaddr: %d\n", phyaddr);
/* Save the discovered PHY device address */
@@ -2760,7 +2760,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
break;
default:
- ndbg("Unrecognized mode: %04x\n", phyreg);
+ nerr("ERROR: Unrecognized mode: %04x\n", phyreg);
return -ENODEV;
}
@@ -2788,7 +2788,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
break;
default:
- ndbg("Unrecognized mode: %04x\n", phyreg);
+ nerr("ERROR: Unrecognized mode: %04x\n", phyreg);
return -ENODEV;
}
@@ -2816,7 +2816,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
break;
default:
- ndbg("Unrecognized mode: %04x\n", phyreg);
+ nerr("ERROR: Unrecognized mode: %04x\n", phyreg);
return -ENODEV;
}
@@ -2862,7 +2862,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
}
else
{
- ndbg("Unrecognized mode: %04x\n", phyreg);
+ nerr("ERROR: Unrecognized mode: %04x\n", phyreg);
return -ENODEV;
}
}
@@ -2871,9 +2871,9 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
# warning "PHY Unknown: speed and duplex are bogus"
#endif
- ndbg("%dBase-T %s duplex\n",
- (priv->lp_mode & LPC17_SPEED_MASK) == LPC17_SPEED_100 ? 100 : 10,
- (priv->lp_mode & LPC17_DUPLEX_MASK) == LPC17_DUPLEX_FULL ?"full" : "half");
+ ninfo("%dBase-T %s duplex\n",
+ (priv->lp_mode & LPC17_SPEED_MASK) == LPC17_SPEED_100 ? 100 : 10,
+ (priv->lp_mode & LPC17_DUPLEX_MASK) == LPC17_DUPLEX_FULL ?"full" : "half");
/* Disable auto-configuration. Set the fixed speed/duplex mode.
* (probably more than little redundant).
diff --git a/arch/arm/src/lpc17xx/lpc17_gpdma.c b/arch/arm/src/lpc17xx/lpc17_gpdma.c
index 4a93267718d60943963442a9b5722f2aad35327b..2eb2edf16ab125ea0868f5ba8815ee92b5c465f8 100644
--- a/arch/arm/src/lpc17xx/lpc17_gpdma.c
+++ b/arch/arm/src/lpc17xx/lpc17_gpdma.c
@@ -654,7 +654,7 @@ void lpc17_dmastop(DMA_HANDLE handle)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG__DEBUG_DMA_INFO
void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs)
{
struct lpc17_dmach_s *dmach = (DMA_HANDLE)handle;
@@ -686,7 +686,7 @@ void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs)
regs->ch.control = getreg32(base + LPC17_DMACH_CONTROL_OFFSET);
regs->ch.config = getreg32(base + LPC17_DMACH_CONFIG_OFFSET);
}
-#endif /* CONFIG_DEBUG_DMA */
+#endif /* CONFIG__DEBUG_DMA_INFO */
/****************************************************************************
* Name: lpc17_dmadump
@@ -696,7 +696,7 @@ void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG__DEBUG_DMA_INFO
void lpc17_dmadump(DMA_HANDLE handle, const struct lpc17_dmaregs_s *regs,
const char *msg)
{
@@ -707,49 +707,49 @@ void lpc17_dmadump(DMA_HANDLE handle, const struct lpc17_dmaregs_s *regs,
/* Dump the sampled global DMA registers */
- dmadbg("Global GPDMA Registers: %s\n", msg);
- dmadbg(" INTST[%08x]: %08x\n",
- LPC17_DMA_INTST, regs->gbl.intst);
- dmadbg(" INTTCST[%08x]: %08x\n",
- LPC17_DMA_INTTCST, regs->gbl.inttcst);
- dmadbg(" INTERRST[%08x]: %08x\n",
- LPC17_DMA_INTERRST, regs->gbl.interrst);
- dmadbg(" RAWINTTCST[%08x]: %08x\n",
- LPC17_DMA_RAWINTTCST, regs->gbl.rawinttcst);
- dmadbg(" RAWINTERRST[%08x]: %08x\n",
- LPC17_DMA_RAWINTERRST, regs->gbl.rawinterrst);
- dmadbg(" ENBLDCHNS[%08x]: %08x\n",
- LPC17_DMA_ENBLDCHNS, regs->gbl.enbldchns);
- dmadbg(" SOFTBREQ[%08x]: %08x\n",
- LPC17_DMA_SOFTBREQ, regs->gbl.softbreq);
- dmadbg(" SOFTSREQ[%08x]: %08x\n",
- LPC17_DMA_SOFTSREQ, regs->gbl.softsreq);
- dmadbg(" SOFTLBREQ[%08x]: %08x\n",
- LPC17_DMA_SOFTLBREQ, regs->gbl.softlbreq);
- dmadbg(" SOFTLSREQ[%08x]: %08x\n",
- LPC17_DMA_SOFTLSREQ, regs->gbl.softlsreq);
- dmadbg(" CONFIG[%08x]: %08x\n",
- LPC17_DMA_CONFIG, regs->gbl.config);
- dmadbg(" SYNC[%08x]: %08x\n",
- LPC17_DMA_SYNC, regs->gbl.sync);
+ dmainfo("Global GPDMA Registers: %s\n", msg);
+ dmainfo(" INTST[%08x]: %08x\n",
+ LPC17_DMA_INTST, regs->gbl.intst);
+ dmainfo(" INTTCST[%08x]: %08x\n",
+ LPC17_DMA_INTTCST, regs->gbl.inttcst);
+ dmainfo(" INTERRST[%08x]: %08x\n",
+ LPC17_DMA_INTERRST, regs->gbl.interrst);
+ dmainfo(" RAWINTTCST[%08x]: %08x\n",
+ LPC17_DMA_RAWINTTCST, regs->gbl.rawinttcst);
+ dmainfo(" RAWINTERRST[%08x]: %08x\n",
+ LPC17_DMA_RAWINTERRST, regs->gbl.rawinterrst);
+ dmainfo(" ENBLDCHNS[%08x]: %08x\n",
+ LPC17_DMA_ENBLDCHNS, regs->gbl.enbldchns);
+ dmainfo(" SOFTBREQ[%08x]: %08x\n",
+ LPC17_DMA_SOFTBREQ, regs->gbl.softbreq);
+ dmainfo(" SOFTSREQ[%08x]: %08x\n",
+ LPC17_DMA_SOFTSREQ, regs->gbl.softsreq);
+ dmainfo(" SOFTLBREQ[%08x]: %08x\n",
+ LPC17_DMA_SOFTLBREQ, regs->gbl.softlbreq);
+ dmainfo(" SOFTLSREQ[%08x]: %08x\n",
+ LPC17_DMA_SOFTLSREQ, regs->gbl.softlsreq);
+ dmainfo(" CONFIG[%08x]: %08x\n",
+ LPC17_DMA_CONFIG, regs->gbl.config);
+ dmainfo(" SYNC[%08x]: %08x\n",
+ LPC17_DMA_SYNC, regs->gbl.sync);
/* Dump the DMA channel registers */
base = LPC17_DMACH_BASE((uint32_t)dmach->chn);
- dmadbg("Channel GPDMA Registers: %d\n", dmach->chn);
-
- dmadbg(" SRCADDR[%08x]: %08x\n",
- base + LPC17_DMACH_SRCADDR_OFFSET, regs->ch.srcaddr);
- dmadbg(" DESTADDR[%08x]: %08x\n",
- base + LPC17_DMACH_DESTADDR_OFFSET, regs->ch.destaddr);
- dmadbg(" LLI[%08x]: %08x\n",
- base + LPC17_DMACH_LLI_OFFSET, regs->ch.lli);
- dmadbg(" CONTROL[%08x]: %08x\n",
- base + LPC17_DMACH_CONTROL_OFFSET, regs->ch.control);
- dmadbg(" CONFIG[%08x]: %08x\n",
- base + LPC17_DMACH_CONFIG_OFFSET, regs->ch.config);
+ dmainfo("Channel GPDMA Registers: %d\n", dmach->chn);
+
+ dmainfo(" SRCADDR[%08x]: %08x\n",
+ base + LPC17_DMACH_SRCADDR_OFFSET, regs->ch.srcaddr);
+ dmainfo(" DESTADDR[%08x]: %08x\n",
+ base + LPC17_DMACH_DESTADDR_OFFSET, regs->ch.destaddr);
+ dmainfo(" LLI[%08x]: %08x\n",
+ base + LPC17_DMACH_LLI_OFFSET, regs->ch.lli);
+ dmainfo(" CONTROL[%08x]: %08x\n",
+ base + LPC17_DMACH_CONTROL_OFFSET, regs->ch.control);
+ dmainfo(" CONFIG[%08x]: %08x\n",
+ base + LPC17_DMACH_CONFIG_OFFSET, regs->ch.config);
}
-#endif /* CONFIG_DEBUG_DMA */
+#endif /* CONFIG__DEBUG_DMA_INFO */
#endif /* CONFIG_LPC17_GPDMA */
diff --git a/arch/arm/src/lpc17xx/lpc17_gpdma.h b/arch/arm/src/lpc17xx/lpc17_gpdma.h
index 4e1e499eb1c5e220e6083f40fe011e703c840ab1..a7c0d7009ccbdef0d522665bd9540cf6e3f25091 100644
--- a/arch/arm/src/lpc17xx/lpc17_gpdma.h
+++ b/arch/arm/src/lpc17xx/lpc17_gpdma.h
@@ -68,7 +68,7 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG__DEBUG_DMA_INFO
struct lpc17_dmaglobalregs_s
{
/* Global Registers */
@@ -109,7 +109,7 @@ struct lpc17_dmaregs_s
struct lpc17_dmachanregs_s ch;
};
-#endif /* CONFIG_DEBUG_DMA */
+#endif /* CONFIG__DEBUG_DMA_INFO */
/****************************************************************************
* Public Data
@@ -239,7 +239,7 @@ void lpc17_dmastop(DMA_HANDLE handle);
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG__DEBUG_DMA_INFO
void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs);
#else
# define lpc17_dmasample(handle,regs)
@@ -253,7 +253,7 @@ void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs);
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG__DEBUG_DMA_INFO
void lpc17_dmadump(DMA_HANDLE handle, const struct lpc17_dmaregs_s *regs,
const char *msg);
#else
diff --git a/arch/arm/src/lpc17xx/lpc17_gpio.h b/arch/arm/src/lpc17xx/lpc17_gpio.h
index e8ec13378992886ae53292bf0862d14e27274d23..1129a26235d02e5ce638b5a5be5bcaa56bbdace0 100644
--- a/arch/arm/src/lpc17xx/lpc17_gpio.h
+++ b/arch/arm/src/lpc17xx/lpc17_gpio.h
@@ -181,7 +181,7 @@ void lpc17_gpioirqdisable(int irq);
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
int lpc17_dumpgpio(lpc17_pinset_t pinset, const char *msg);
#else
# define lpc17_dumpgpio(p,m)
diff --git a/arch/arm/src/lpc17xx/lpc17_gpiodbg.c b/arch/arm/src/lpc17xx/lpc17_gpiodbg.c
index fc6ce33162bee1d163bfc36700c33bd38b848b74..00d0f8fade2c8fc1ad70203fcadbe6ad9754944f 100644
--- a/arch/arm/src/lpc17xx/lpc17_gpiodbg.c
+++ b/arch/arm/src/lpc17xx/lpc17_gpiodbg.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc17xx/lpc17_gpiodbg.c
*
- * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2010-2011, 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,6 +39,11 @@
#include
+/* Output debug info even if debug output is not selected. */
+
+#undef CONFIG_DEBUG_INFO
+#define CONFIG_DEBUG_INFO 1
+
#include
#include
#include
@@ -49,23 +54,7 @@
#include "chip.h"
#include "lpc17_gpio.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_GPIO
-#endif
-
-#ifdef CONFIG_DEBUG_GPIO
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
+#ifdef CONFIG_DEBUG_GPIO_INFO
/****************************************************************************
* Private Functions
@@ -157,34 +146,36 @@ int lpc17_dumpgpio(lpc17_pinset_t pinset, const char *msg)
/* The following requires exclusive access to the GPIO registers */
flags = enter_critical_section();
- lldbg("GPIO%c pin%d (pinset: %08x) -- %s\n",
- port + '0', pin, pinset, msg);
+
+ gpioinfo("GPIO%c pin%d (pinset: %08x) -- %s\n",
+ port + '0', pin, pinset, msg);
#if defined(LPC176x)
- lldbg(" PINSEL[%08x]: %08x PINMODE[%08x]: %08x ODMODE[%08x]: %08x\n",
- pinsel, pinsel ? getreg32(pinsel) : 0,
- pinmode, pinmode ? getreg32(pinmode) : 0,
- g_odmode[port], getreg32(g_odmode[port]));
+ gpioinfo(" PINSEL[%08x]: %08x PINMODE[%08x]: %08x ODMODE[%08x]: %08x\n",
+ pinsel, pinsel ? getreg32(pinsel) : 0,
+ pinmode, pinmode ? getreg32(pinmode) : 0,
+ g_odmode[port], getreg32(g_odmode[port]));
#elif defined(LPC178x)
- lldbg(" IOCON[%08x]: %08x\n", iocon, getreg32(iocon));
+ gpioinfo(" IOCON[%08x]: %08x\n", iocon, getreg32(iocon));
#endif
base = g_fiobase[port];
- lldbg(" FIODIR[%08x]: %08x FIOMASK[%08x]: %08x FIOPIN[%08x]: %08x\n",
- base+LPC17_FIO_DIR_OFFSET, getreg32(base+LPC17_FIO_DIR_OFFSET),
- base+LPC17_FIO_MASK_OFFSET, getreg32(base+LPC17_FIO_MASK_OFFSET),
- base+LPC17_FIO_PIN_OFFSET, getreg32(base+LPC17_FIO_PIN_OFFSET));
+ gpioinfo(" FIODIR[%08x]: %08x FIOMASK[%08x]: %08x FIOPIN[%08x]: %08x\n",
+ base+LPC17_FIO_DIR_OFFSET, getreg32(base+LPC17_FIO_DIR_OFFSET),
+ base+LPC17_FIO_MASK_OFFSET, getreg32(base+LPC17_FIO_MASK_OFFSET),
+ base+LPC17_FIO_PIN_OFFSET, getreg32(base+LPC17_FIO_PIN_OFFSET));
base = g_intbase[port];
- lldbg(" IOINTSTATUS[%08x]: %08x INTSTATR[%08x]: %08x INSTATF[%08x]: %08x\n",
- LPC17_GPIOINT_IOINTSTATUS, getreg32(LPC17_GPIOINT_IOINTSTATUS),
- base+LPC17_GPIOINT_INTSTATR_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATR_OFFSET),
- base+LPC17_GPIOINT_INTSTATF_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATF_OFFSET));
- lldbg(" INTENR[%08x]: %08x INTENF[%08x]: %08x\n",
- base+LPC17_GPIOINT_INTENR_OFFSET, getreg32(base+LPC17_GPIOINT_INTENR_OFFSET),
- base+LPC17_GPIOINT_INTENF_OFFSET, getreg32(base+LPC17_GPIOINT_INTENF_OFFSET));
+ gpioinfo(" IOINTSTATUS[%08x]: %08x INTSTATR[%08x]: %08x INSTATF[%08x]: %08x\n",
+ LPC17_GPIOINT_IOINTSTATUS, getreg32(LPC17_GPIOINT_IOINTSTATUS),
+ base+LPC17_GPIOINT_INTSTATR_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATR_OFFSET),
+ base+LPC17_GPIOINT_INTSTATF_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATF_OFFSET));
+ gpioinfo(" INTENR[%08x]: %08x INTENF[%08x]: %08x\n",
+ base+LPC17_GPIOINT_INTENR_OFFSET, getreg32(base+LPC17_GPIOINT_INTENR_OFFSET),
+ base+LPC17_GPIOINT_INTENF_OFFSET, getreg32(base+LPC17_GPIOINT_INTENF_OFFSET));
+
leave_critical_section(flags);
return OK;
}
-#endif /* CONFIG_DEBUG_GPIO */
+#endif /* CONFIG_DEBUG_GPIO_INFO */
diff --git a/arch/arm/src/lpc17xx/lpc17_i2c.c b/arch/arm/src/lpc17xx/lpc17_i2c.c
index 9b106fdda4e813e2c237fdb1f4f491befa1fc228..58bb2de8987b5d1218ba1b111eb9267a686578ad 100644
--- a/arch/arm/src/lpc17xx/lpc17_i2c.c
+++ b/arch/arm/src/lpc17xx/lpc17_i2c.c
@@ -485,7 +485,7 @@ struct i2c_master_s *lpc17_i2cbus_initialize(int port)
if (port > 1)
{
- dbg("lpc I2C Only support 0,1\n");
+ i2cerr("ERROR: LPC I2C Only supports ports 0 and 1\n");
return NULL;
}
diff --git a/arch/arm/src/lpc17xx/lpc17_irq.c b/arch/arm/src/lpc17xx/lpc17_irq.c
index d1f72be399a9bdd1a7c93424e19fe7e50eca7ed1..44d149c7342f6eb119a55d60e459e753da58972f 100644
--- a/arch/arm/src/lpc17xx/lpc17_irq.c
+++ b/arch/arm/src/lpc17xx/lpc17_irq.c
@@ -102,33 +102,35 @@ extern uint32_t _vectors[];
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_IRQ)
+#if defined(CONFIG_DEBUG_IRQ_INFO)
static void lpc17_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
- lldbg("NVIC (%s, irq=%d):\n", msg, irq);
- lldbg(" INTCTRL: %08x VECTAB: %08x\n",
- getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
+
+ irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
+ irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
+ getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
- lldbg(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
- getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
- getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
+ irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
+ getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
+ getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
- lldbg(" IRQ ENABLE: %08x\n", getreg32(NVIC_IRQ0_31_ENABLE));
- lldbg(" SYSH_PRIO: %08x %08x %08x\n",
- getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
- getreg32(NVIC_SYSH12_15_PRIORITY));
- lldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
- getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
- getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
- getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
+ irqinfo(" IRQ ENABLE: %08x\n", getreg32(NVIC_IRQ0_31_ENABLE));
+ irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
+ getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
+ getreg32(NVIC_SYSH12_15_PRIORITY));
+ irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
+ getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
+ getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
+ getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
+
leave_critical_section(flags);
}
#else
@@ -146,11 +148,11 @@ static void lpc17_dumpnvic(const char *msg, int irq)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
static int lpc17_nmi(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! NMI received\n");
+ _err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
@@ -158,7 +160,7 @@ static int lpc17_nmi(int irq, FAR void *context)
static int lpc17_busfault(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Bus fault recived\n");
+ _err("PANIC!!! Bus fault recived\n");
PANIC();
return 0;
}
@@ -166,7 +168,7 @@ static int lpc17_busfault(int irq, FAR void *context)
static int lpc17_usagefault(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Usage fault received\n");
+ _err("PANIC!!! Usage fault received\n");
PANIC();
return 0;
}
@@ -174,7 +176,7 @@ static int lpc17_usagefault(int irq, FAR void *context)
static int lpc17_pendsv(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! PendSV received\n");
+ _err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
@@ -182,7 +184,7 @@ static int lpc17_pendsv(int irq, FAR void *context)
static int lpc17_dbgmonitor(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Debug Monitor received\n");
+ _err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
}
@@ -190,7 +192,7 @@ static int lpc17_dbgmonitor(int irq, FAR void *context)
static int lpc17_reserved(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Reserved interrupt\n");
+ _err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
@@ -392,7 +394,7 @@ void up_irqinitialize(void)
/* Attach all other processor exceptions (except reset and sys tick) */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
irq_attach(LPC17_IRQ_NMI, lpc17_nmi);
#ifndef CONFIG_ARM_MPU
irq_attach(LPC17_IRQ_MEMFAULT, up_memfault);
diff --git a/arch/arm/src/lpc17xx/lpc17_lcd.c b/arch/arm/src/lpc17xx/lpc17_lcd.c
index 79be36191caab688dfce9ed204fdd0bb85dcfbf6..f8a6c6db6c9d6d6ed72a4759249132c2b9655498 100644
--- a/arch/arm/src/lpc17xx/lpc17_lcd.c
+++ b/arch/arm/src/lpc17xx/lpc17_lcd.c
@@ -202,14 +202,14 @@ struct fb_vtable_s g_fbobject =
static int lpc17_getvideoinfo(FAR struct fb_vtable_s *vtable,
FAR struct fb_videoinfo_s *vinfo)
{
- gvdbg("vtable=%p vinfo=%p\n", vtable, vinfo);
+ lcdinfo("vtable=%p vinfo=%p\n", vtable, vinfo);
if (vtable && vinfo)
{
memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s));
return OK;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -220,14 +220,14 @@ static int lpc17_getvideoinfo(FAR struct fb_vtable_s *vtable,
static int lpc17_getplaneinfo(FAR struct fb_vtable_s *vtable, int planeno,
FAR struct fb_planeinfo_s *pinfo)
{
- gvdbg("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo);
+ lcdinfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo);
if (vtable && planeno == 0 && pinfo)
{
memcpy(pinfo, &g_planeinfo, sizeof(struct fb_planeinfo_s));
return OK;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -244,8 +244,8 @@ static int lpc17_getcmap(FAR struct fb_vtable_s *vtable,
int last;
int i;
- gvdbg("vtable=%p cmap=%p first=%d len=%d\n",
- vtable, cmap, cmap->first, cmap->len);
+ lcdinfo("vtable=%p cmap=%p first=%d len=%d\n",
+ vtable, cmap, cmap->first, cmap->len);
DEBUGASSERT(vtable && cmap &&
cmap->first < 256 && (cmap->first + cmap->len) < 256);
@@ -319,8 +319,8 @@ static int lpc17_putcmap(FAR struct fb_vtable_s *vtable,
int last;
int i;
- gvdbg("vtable=%p cmap=%p first=%d len=%d\n",
- vtable, cmap, cmap->first, cmap->len);
+ lcdinfo("vtable=%p cmap=%p first=%d len=%d\n",
+ vtable, cmap, cmap->first, cmap->len);
DEBUGASSERT(vtable && cmap);
@@ -383,27 +383,27 @@ static int lpc17_putcmap(FAR struct fb_vtable_s *vtable,
static int lpc17_getcursor(FAR struct fb_vtable_s *vtable,
FAR struct fb_cursorattrib_s *attrib)
{
- gvdbg("vtable=%p attrib=%p\n", vtable, attrib);
+ lcdinfo("vtable=%p attrib=%p\n", vtable, attrib);
if (vtable && attrib)
{
#ifdef CONFIG_FB_HWCURSORIMAGE
attrib->fmt = LPC17_COLOR_FMT;
#endif
- gvdbg("pos: (x=%d, y=%d)\n", g_cpos.x, g_cpos.y);
+ lcdinfo("pos: (x=%d, y=%d)\n", g_cpos.x, g_cpos.y);
attrib->pos = g_cpos;
#ifdef CONFIG_FB_HWCURSORSIZE
attrib->mxsize.h = CONFIG_LPC17_LCD_VHEIGHT;
attrib->mxsize.w = CONFIG_LPC17_LCD_HWIDTH;
- gvdbg("size: (h=%d, w=%d)\n", g_csize.h, g_csize.w);
+ lcdinfo("size: (h=%d, w=%d)\n", g_csize.h, g_csize.w);
attrib->size = g_csize;
#endif
return OK;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
#endif
@@ -416,34 +416,34 @@ static int lpc17_getcursor(FAR struct fb_vtable_s *vtable,
static int lpc17_setcursor(FAR struct fb_vtable_s *vtable,
FAR struct fb_setcursor_s *setttings)
{
- gvdbg("vtable=%p setttings=%p\n", vtable, setttings);
+ lcdinfo("vtable=%p setttings=%p\n", vtable, setttings);
if (vtable && setttings)
{
- gvdbg("flags: %02x\n", settings->flags);
+ lcdinfo("flags: %02x\n", settings->flags);
if ((flags & FB_CUR_SETPOSITION) != 0)
{
g_cpos = settings->pos;
- gvdbg("pos: (h:%d, w:%d)\n", g_cpos.x, g_cpos.y);
+ lcdinfo("pos: (h:%d, w:%d)\n", g_cpos.x, g_cpos.y);
}
#ifdef CONFIG_FB_HWCURSORSIZE
if ((flags & FB_CUR_SETSIZE) != 0)
{
g_csize = settings->size;
- gvdbg("size: (h:%d, w:%d)\n", g_csize.h, g_csize.w);
+ lcdinfo("size: (h:%d, w:%d)\n", g_csize.h, g_csize.w);
}
#endif
#ifdef CONFIG_FB_HWCURSORIMAGE
if ((flags & FB_CUR_SETIMAGE) != 0)
{
- gvdbg("image: (h:%d, w:%d) @ %p\n",
- settings->img.height, settings->img.width,
- settings->img.image);
+ lcdinfo("image: (h:%d, w:%d) @ %p\n",
+ settings->img.height, settings->img.width,
+ settings->img.image);
}
#endif
return OK;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
#endif
@@ -473,7 +473,7 @@ int up_fbinitialize(int display)
uint32_t regval;
int i;
- gvdbg("Entry\n");
+ lcdinfo("Entry\n");
/* Give LCD bus priority */
@@ -485,7 +485,7 @@ int up_fbinitialize(int display)
/* Configure pins */
/* Video data */
- gvdbg("Configuring pins\n");
+ lcdinfo("Configuring pins\n");
lpc17_configgpio(GPIO_LCD_VD0);
lpc17_configgpio(GPIO_LCD_VD1);
@@ -528,7 +528,7 @@ int up_fbinitialize(int display)
modifyreg32(LPC17_SYSCON_PCONP, 0, SYSCON_PCONP_PCLCD);
- gvdbg("Configuring the LCD controller\n");
+ lcdinfo("Configuring the LCD controller\n");
/* Disable the cursor */
@@ -686,7 +686,7 @@ int up_fbinitialize(int display)
#endif
putreg32(0, LPC17_LCD_INTMSK);
- gvdbg("Enabling the display\n");
+ lcdinfo("Enabling the display\n");
for (i = LPC17_LCD_PWREN_DELAY; i; i--);
@@ -727,7 +727,7 @@ int up_fbinitialize(int display)
FAR struct fb_vtable_s *up_fbgetvplane(int display, int vplane)
{
- gvdbg("vplane: %d\n", vplane);
+ lcdinfo("vplane: %d\n", vplane);
if (vplane == 0)
{
return &g_fbobject;
@@ -801,16 +801,16 @@ void lpc17_lcdclear(nxgl_mxpixel_t color)
#if LPC17_BPP > 16
uint32_t *dest = (uint32_t *)CONFIG_LPC17_LCD_VRAMBASE;
- gvdbg("Clearing display: color=%08x VRAM=%08x size=%d\n",
- color, CONFIG_LPC17_LCD_VRAMBASE,
- CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT * sizeof(uint32_t));
+ lcdinfo("Clearing display: color=%08x VRAM=%08x size=%d\n",
+ color, CONFIG_LPC17_LCD_VRAMBASE,
+ CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT * sizeof(uint32_t));
#else
uint16_t *dest = (uint16_t *)CONFIG_LPC17_LCD_VRAMBASE;
- gvdbg("Clearing display: color=%08x VRAM=%08x size=%d\n",
- color, CONFIG_LPC17_LCD_VRAMBASE,
- CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT * sizeof(uint16_t));
+ lcdinfo("Clearing display: color=%08x VRAM=%08x size=%d\n",
+ color, CONFIG_LPC17_LCD_VRAMBASE,
+ CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT * sizeof(uint16_t));
#endif
for (i = 0; i < (CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT); i++)
diff --git a/arch/arm/src/lpc17xx/lpc17_mcpwm.c b/arch/arm/src/lpc17xx/lpc17_mcpwm.c
index f8d552941b04a34992b0d2a9898ad0c1b16b08f0..be526964c4a2356a98938a7a4cb107029ef3a750 100644
--- a/arch/arm/src/lpc17xx/lpc17_mcpwm.c
+++ b/arch/arm/src/lpc17xx/lpc17_mcpwm.c
@@ -81,29 +81,10 @@
#define TIMTYPE_TIM1 TIMTYPE_ADVANCED
/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing PWM */
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_PWM
-#endif
-
-#ifdef CONFIG_DEBUG_PWM
-# define pwmdbg dbg
-# define pwmlldbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define pwmvdbg vdbg
-# define pwmllvdbg llvdbg
-# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
-# else
-# define pwmlldbg(x...)
-# define pwmllvdbg(x...)
-# define pwm_dumpgpio(p,m)
-# endif
+#ifdef CONFIG_DEBUG_PWM_INFO
+# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
#else
-# define pwmdbg(x...)
-# define pwmlldbg(x...)
-# define pwmvdbg(x...)
-# define pwmllvdbg(x...)
# define pwm_dumpgpio(p,m)
#endif
@@ -132,7 +113,7 @@ struct lpc17_mcpwmtimer_s
static uint32_t mcpwm_getreg(struct lpc17_mcpwmtimer_s *priv, int offset);
static void mcpwm_putreg(struct lpc17_mcpwmtimer_s *priv, int offset, uint32_t value);
-#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_PWM_INFO
static void mcpwm_dumpregs(struct lpc17_mcpwmtimer_s *priv, FAR const char *msg);
#else
# define mcpwm_dumpregs(priv,msg)
@@ -242,12 +223,12 @@ static void mcpwm_putreg(struct lpc17_mcpwmtimer_s *priv, int offset, uint32_t v
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_PWM_INFO
static void mcpwm_dumpregs(FAR struct lpc17_mcpwmtimer_s *priv,
FAR const char *msg)
{
- pwmvdbg("%s:\n", msg);
- pwmvdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
+ pwminfo("%s:\n", msg);
+ pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
mcpwm_getreg(priv, LPC17_PWM_MR0_OFFSET),
mcpwm_getreg(priv, LPC17_PWM_MR1_OFFSET),
mcpwm_getreg(priv, LPC17_PWM_MR2_OFFSET),
@@ -255,7 +236,7 @@ static void mcpwm_dumpregs(FAR struct lpc17_mcpwmtimer_s *priv,
#if defined(CONFIG_LPC17_MCPWM)
if (priv->timtype == TIMTYPE_ADVANCED)
{
- pwmvdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
+ pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
mcpwm_getreg(priv, LPC17_PWM_MR0_OFFSET),
mcpwm_getreg(priv, LPC17_PWM_MR1_OFFSET),
mcpwm_getreg(priv, LPC17_PWM_MR2_OFFSET),
@@ -264,7 +245,7 @@ static void mcpwm_dumpregs(FAR struct lpc17_mcpwmtimer_s *priv,
else
#endif
{
- pwmvdbg(" DCR: %04x DMAR: %04x\n",
+ pwminfo(" DCR: %04x DMAR: %04x\n",
mcpwm_getreg(priv, LPC17_PWM_MR2_OFFSET),
mcpwm_getreg(priv, LPC17_PWM_MR3_OFFSET));
}
@@ -520,7 +501,7 @@ static int mcpwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
FAR struct lpc17_mcpwmtimer_s *priv = (FAR struct lpc17_mcpwmtimer_s *)dev;
uint32_t pincfg;
- pwmvdbg("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg);
+ pwminfo("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg);
/* Make sure that the output has been stopped */
@@ -576,7 +557,7 @@ static int mcpwm_stop(FAR struct pwm_lowerhalf_s *dev)
uint32_t regval;
irqstate_t flags;
- pwmvdbg("TIM%d\n", priv->timid);
+ pwminfo("TIM%d\n", priv->timid);
/* Disable interrupts momentary to stop any ongoing timer processing and
* to prevent any concurrent access to the reset register.
@@ -602,7 +583,7 @@ static int mcpwm_stop(FAR struct pwm_lowerhalf_s *dev)
leave_critical_section(flags);
- pwmvdbg("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
+ pwminfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
mcpwm_dumpregs(priv, "After stop");
return OK;
}
@@ -625,12 +606,12 @@ static int mcpwm_stop(FAR struct pwm_lowerhalf_s *dev)
static int mcpwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg)
{
-#ifdef CONFIG_DEBUG_PWM
+#ifdef CONFIG_DEBUG_PWM_INFO
FAR struct lpc17_mcpwmtimer_s *priv = (FAR struct lpc17_mcpwmtimer_s *)dev;
/* There are no platform-specific ioctl commands */
- pwmvdbg("TIM%d\n", priv->timid);
+ pwminfo("TIM%d\n", priv->timid);
#endif
return -ENOTTY;
}
@@ -660,7 +641,7 @@ FAR struct pwm_lowerhalf_s *lpc17_mcpwminitialize(int timer)
{
FAR struct lpc17_mcpwmtimer_s *lower;
- pwmvdbg("TIM%d\n", timer);
+ pwminfo("TIM%d\n", timer);
switch (timer)
{
@@ -674,7 +655,7 @@ FAR struct pwm_lowerhalf_s *lpc17_mcpwminitialize(int timer)
#endif
default:
- pwmdbg("No such timer configured\n");
+ pwmerr("ERROR: No such timer configured\n");
return NULL;
}
diff --git a/arch/arm/src/lpc17xx/lpc17_pwm.c b/arch/arm/src/lpc17xx/lpc17_pwm.c
index 4f8c79315c607a6735ed60a78c710389a909f2fb..dc073fc1a73dc36b943e0256eacf61bd42719888 100644
--- a/arch/arm/src/lpc17xx/lpc17_pwm.c
+++ b/arch/arm/src/lpc17xx/lpc17_pwm.c
@@ -99,29 +99,10 @@
#define TCR_PWM_EN (0x00000008)
/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing PWM */
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_PWM
-#endif
-
-#ifdef CONFIG_DEBUG_PWM
-# define pwmdbg dbg
-# define pwmlldbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define pwmvdbg vdbg
-# define pwmllvdbg llvdbg
-# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
-# else
-# define pwmlldbg(x...)
-# define pwmllvdbg(x...)
-# define pwm_dumpgpio(p,m)
-# endif
+#ifdef CONFIG_DEBUG_PWM_INFO
+# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
#else
-# define pwmdbg(x...)
-# define pwmlldbg(x...)
-# define pwmvdbg(x...)
-# define pwmllvdbg(x...)
# define pwm_dumpgpio(p,m)
#endif
@@ -150,7 +131,7 @@ struct lpc17_pwmtimer_s
static uint32_t pwm_getreg(struct lpc17_pwmtimer_s *priv, int offset);
static void pwm_putreg(struct lpc17_pwmtimer_s *priv, int offset, uint32_t value);
-#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_PWM_INFO
static void pwm_dumpregs(struct lpc17_pwmtimer_s *priv, FAR const char *msg);
#else
# define pwm_dumpregs(priv,msg)
@@ -258,11 +239,11 @@ static void pwm_putreg(struct lpc17_pwmtimer_s *priv, int offset, uint32_t value
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_PWM_INFO
static void pwm_dumpregs(struct lpc17_pwmtimer_s *priv, FAR const char *msg)
{
- pwmvdbg("%s:\n", msg);
- pwmvdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
+ pwminfo("%s:\n", msg);
+ pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
pwm_getreg(priv, LPC17_PWM_MR0_OFFSET),
pwm_getreg(priv, LPC17_PWM_MR1_OFFSET),
pwm_getreg(priv, LPC17_PWM_MR2_OFFSET),
@@ -270,7 +251,7 @@ static void pwm_dumpregs(struct lpc17_pwmtimer_s *priv, FAR const char *msg)
#if defined(CONFIG_LPC17_PWM1)
if (priv->timtype == TIMTYPE_ADVANCED)
{
- pwmvdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
+ pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
pwm_getreg(priv, LPC17_PWM_MR0_OFFSET),
pwm_getreg(priv, LPC17_PWM_MR1_OFFSET),
pwm_getreg(priv, LPC17_PWM_MR2_OFFSET),
@@ -279,7 +260,7 @@ static void pwm_dumpregs(struct lpc17_pwmtimer_s *priv, FAR const char *msg)
else
#endif
{
- pwmvdbg(" DCR: %04x DMAR: %04x\n",
+ pwminfo(" DCR: %04x DMAR: %04x\n",
pwm_getreg(priv, LPC17_PWM_MR2_OFFSET),
pwm_getreg(priv, LPC17_PWM_MR3_OFFSET));
}
@@ -491,7 +472,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
FAR struct lpc17_pwmtimer_s *priv = (FAR struct lpc17_pwmtimer_s *)dev;
uint32_t pincfg;
- pwmvdbg("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg);
+ pwminfo("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg);
/* Make sure that the output has been stopped */
@@ -547,7 +528,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
uint32_t regval;
irqstate_t flags;
- pwmvdbg("TIM%d\n", priv->timid);
+ pwminfo("TIM%d\n", priv->timid);
/* Disable interrupts momentary to stop any ongoing timer processing and
* to prevent any concurrent access to the reset register.
@@ -573,7 +554,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
leave_critical_section(flags);
- pwmvdbg("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
+ pwminfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
pwm_dumpregs(priv, "After stop");
return OK;
}
@@ -596,12 +577,12 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg)
{
-#ifdef CONFIG_DEBUG_PWM
+#ifdef CONFIG_DEBUG_PWM_INFO
FAR struct lpc17_pwmtimer_s *priv = (FAR struct lpc17_pwmtimer_s *)dev;
/* There are no platform-specific ioctl commands */
- pwmvdbg("TIM%d\n", priv->timid);
+ pwminfo("TIM%d\n", priv->timid);
#endif
return -ENOTTY;
}
@@ -631,7 +612,7 @@ FAR struct pwm_lowerhalf_s *lpc17_pwminitialize(int timer)
{
FAR struct lpc17_pwmtimer_s *lower;
- pwmvdbg("TIM%d\n", timer);
+ pwminfo("TIM%d\n", timer);
switch (timer)
{
@@ -645,7 +626,7 @@ FAR struct pwm_lowerhalf_s *lpc17_pwminitialize(int timer)
#endif
default:
- pwmdbg("No such timer configured\n");
+ pwmerr("ERROR: No such timer configured\n");
return NULL;
}
diff --git a/arch/arm/src/lpc17xx/lpc17_sdcard.c b/arch/arm/src/lpc17xx/lpc17_sdcard.c
index e6cb9fafd7e117537fe3b192aa14db5255c3601b..2ea6c17c45cc61c68cbd8751f759a36b88c6787a 100644
--- a/arch/arm/src/lpc17xx/lpc17_sdcard.c
+++ b/arch/arm/src/lpc17xx/lpc17_sdcard.c
@@ -93,8 +93,8 @@
* CONFIG_SDIO_WIDTH_D1_ONLY - This may be selected to force the driver
* operate with only a single data line (the default is to use all
* 4 SD data lines).
- * CONFIG_DEBUG_SDIO - Enables some very low-level debug output
- * This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_VERBOSE
+ * CONFIG_DEBUG_MEMCARD_* - Enables some very low-level debug output
+ * This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO
*/
#if defined(CONFIG_SDIO_DMA) && !defined(CONFIG_LPC17_GPDMA)
@@ -109,10 +109,6 @@
# error "Callback support requires CONFIG_SCHED_WORKQUEUE"
#endif
-#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG)
-# undef CONFIG_DEBUG_SDIO
-#endif
-
/* Friendly CLKCR bit re-definitions ****************************************/
/* Mode dependent settings. These depend on clock devisor settings that must
@@ -213,7 +209,7 @@
/* Register logging support */
-#ifdef CONFIG_DEBUG_SDIO
+#ifdef CONFIG_DEBUG_MEMCARD_INFO
# ifdef CONFIG_SDIO_DMA
# define SAMPLENDX_BEFORE_SETUP 0
# define SAMPLENDX_BEFORE_ENABLE 1
@@ -274,7 +270,7 @@ struct lpc17_dev_s
/* Register logging support */
-#ifdef CONFIG_DEBUG_SDIO
+#ifdef CONFIG_DEBUG_MEMCARD_INFO
struct lpc17_sdcard_regs_s
{
uint8_t pwr;
@@ -314,7 +310,7 @@ static inline uint32_t lpc17_getpwrctrl(void);
/* DMA Helpers **************************************************************/
-#ifdef CONFIG_DEBUG_SDIO
+#ifdef CONFIG_DEBUG_MEMCARD_INFO
static void lpc17_sampleinit(void);
static void lpc17_sdcard_sample(struct lpc17_sdcard_regs_s *regs);
static void lpc17_sample(struct lpc17_dev_s *priv, int index);
@@ -452,7 +448,7 @@ struct lpc17_dev_s g_scard_dev =
/* Register logging support */
-#ifdef CONFIG_DEBUG_SDIO
+#ifdef CONFIG_DEBUG_MEMCARD_INFO
static struct lpc17_sampleregs_s g_sampleregs[DEBUG_NSAMPLES];
#endif
@@ -529,8 +525,8 @@ static inline void lpc17_setclock(uint32_t clkcr)
regval |= clkcr;
putreg32(regval, LPC17_SDCARD_CLOCK);
- fvdbg("CLKCR: %08x PWR: %08x\n",
- getreg32(LPC17_SDCARD_CLOCK), getreg32(LPC17_SDCARD_PWR));
+ mcinfo("CLKCR: %08x PWR: %08x\n",
+ getreg32(LPC17_SDCARD_CLOCK), getreg32(LPC17_SDCARD_PWR));
}
/****************************************************************************
@@ -659,7 +655,7 @@ static inline uint32_t lpc17_getpwrctrl(void)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_SDIO
+#ifdef CONFIG_DEBUG_MEMCARD_INFO
static void lpc17_sampleinit(void)
{
memset(g_sampleregs, 0xff, DEBUG_NSAMPLES * sizeof(struct lpc17_sampleregs_s));
@@ -674,7 +670,7 @@ static void lpc17_sampleinit(void)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_SDIO
+#ifdef CONFIG_DEBUG_MEMCARD_INFO
static void lpc17_sdcard_sample(struct lpc17_sdcard_regs_s *regs)
{
regs->pwr = (uint8_t)getreg32(LPC17_SDCARD_PWR);
@@ -697,7 +693,7 @@ static void lpc17_sdcard_sample(struct lpc17_sdcard_regs_s *regs)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_SDIO
+#ifdef CONFIG_DEBUG_MEMCARD_INFO
static void lpc17_sample(struct lpc17_dev_s *priv, int index)
{
struct lpc17_sampleregs_s *regs = &g_sampleregs[index];
@@ -707,6 +703,7 @@ static void lpc17_sample(struct lpc17_dev_s *priv, int index)
lpc17_dmasample(priv->dma, ®s->dma);
}
#endif
+
lpc17_sdcard_sample(®s->sdcard);
}
#endif
@@ -719,19 +716,19 @@ static void lpc17_sample(struct lpc17_dev_s *priv, int index)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_SDIO
+#ifdef CONFIG_DEBUG_MEMCARD_INFO
static void lpc17_sdcard_dump(struct lpc17_sdcard_regs_s *regs, const char *msg)
{
- fdbg("SD Card Registers: %s\n", msg);
- fdbg(" POWER[%08x]: %08x\n", LPC17_SDCARD_PWR, regs->pwr);
- fdbg(" CLKCR[%08x]: %08x\n", LPC17_SDCARD_CLOCK, regs->clkcr);
- fdbg(" DCTRL[%08x]: %08x\n", LPC17_SDCARD_DCTRL, regs->dctrl);
- fdbg(" DTIMER[%08x]: %08x\n", LPC17_SDCARD_DTIMER, regs->dtimer);
- fdbg(" DLEN[%08x]: %08x\n", LPC17_SDCARD_DLEN, regs->dlen);
- fdbg(" DCOUNT[%08x]: %08x\n", LPC17_SDCARD_DCOUNT, regs->dcount);
- fdbg(" STA[%08x]: %08x\n", LPC17_SDCARD_STATUS, regs->sta);
- fdbg(" MASK[%08x]: %08x\n", LPC17_SDCARD_MASK0, regs->mask);
- fdbg("FIFOCNT[%08x]: %08x\n", LPC17_SDCARD_FIFOCNT, regs->fifocnt);
+ mcinfo("SD Card Registers: %s\n", msg);
+ mcinfo(" POWER[%08x]: %08x\n", LPC17_SDCARD_PWR, regs->pwr);
+ mcinfo(" CLKCR[%08x]: %08x\n", LPC17_SDCARD_CLOCK, regs->clkcr);
+ mcinfo(" DCTRL[%08x]: %08x\n", LPC17_SDCARD_DCTRL, regs->dctrl);
+ mcinfo(" DTIMER[%08x]: %08x\n", LPC17_SDCARD_DTIMER, regs->dtimer);
+ mcinfo(" DLEN[%08x]: %08x\n", LPC17_SDCARD_DLEN, regs->dlen);
+ mcinfo(" DCOUNT[%08x]: %08x\n", LPC17_SDCARD_DCOUNT, regs->dcount);
+ mcinfo(" STA[%08x]: %08x\n", LPC17_SDCARD_STATUS, regs->sta);
+ mcinfo(" MASK[%08x]: %08x\n", LPC17_SDCARD_MASK0, regs->mask);
+ mcinfo("FIFOCNT[%08x]: %08x\n", LPC17_SDCARD_FIFOCNT, regs->fifocnt);
}
#endif
@@ -743,7 +740,7 @@ static void lpc17_sdcard_dump(struct lpc17_sdcard_regs_s *regs, const char *msg)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_SDIO
+#ifdef CONFIG_DEBUG_MEMCARD_INFO
static void lpc17_dumpsample(struct lpc17_dev_s *priv,
struct lpc17_sampleregs_s *regs, const char *msg)
{
@@ -765,7 +762,7 @@ static void lpc17_dumpsample(struct lpc17_dev_s *priv,
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_SDIO
+#ifdef CONFIG_DEBUG_MEMCARD_INFO
static void lpc17_dumpsamples(struct lpc17_dev_s *priv)
{
lpc17_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup");
@@ -813,7 +810,7 @@ static void lpc17_dmacallback(DMA_HANDLE handle, void *arg, int status)
if (status < 0)
{
- flldbg("DMA error %d, remaining: %d\n", status, priv->remaining);
+ dmaerr("ERROR: DMA error %d, remaining: %d\n", status, priv->remaining);
result = SDIOWAIT_ERROR;
}
else
@@ -1080,7 +1077,7 @@ static void lpc17_eventtimeout(int argc, uint32_t arg)
/* Yes.. wake up any waiting threads */
lpc17_endwait(priv, SDIOWAIT_TIMEOUT);
- flldbg("Timeout: remaining: %d\n", priv->remaining);
+ mcerr("ERROR: Timeout: remaining: %d\n", priv->remaining);
}
}
@@ -1297,7 +1294,7 @@ static int lpc17_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
- flldbg("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
+ mcerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
@@ -1307,7 +1304,7 @@ static int lpc17_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
- flldbg("ERROR: Data timeout, remaining: %d\n", priv->remaining);
+ mcerr("ERROR: Data timeout, remaining: %d\n", priv->remaining);
lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT);
}
@@ -1317,7 +1314,7 @@ static int lpc17_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
- flldbg("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining);
+ mcerr("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining);
lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
@@ -1327,7 +1324,7 @@ static int lpc17_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
- flldbg("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining);
+ mcerr("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining);
lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
@@ -1337,7 +1334,7 @@ static int lpc17_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
- flldbg("ERROR: Start bit, remaining: %d\n", priv->remaining);
+ mcerr("ERROR: Start bit, remaining: %d\n", priv->remaining);
lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
}
@@ -1480,8 +1477,8 @@ static void lpc17_reset(FAR struct sdio_dev_s *dev)
lpc17_setpwrctrl(SDCARD_PWR_CTRL_ON);
leave_critical_section(flags);
- fvdbg("CLCKR: %08x POWER: %08x\n",
- getreg32(LPC17_SDCARD_CLOCK), getreg32(LPC17_SDCARD_PWR));
+ mcinfo("CLCKR: %08x POWER: %08x\n",
+ getreg32(LPC17_SDCARD_CLOCK), getreg32(LPC17_SDCARD_PWR));
}
/****************************************************************************
@@ -1689,7 +1686,7 @@ static int lpc17_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg)
cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT;
regval |= cmdidx | SDCARD_CMD_CPSMEN;
- fvdbg("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
+ mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
/* Write the SD card CMD */
@@ -1920,7 +1917,7 @@ static int lpc17_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
{
if (--timeout <= 0)
{
- fdbg("ERROR: Timeout cmd: %08x events: %08x STA: %08x\n",
+ mcerr("ERROR: Timeout cmd: %08x events: %08x STA: %08x\n",
cmd, events, getreg32(LPC17_SDCARD_STATUS));
return -ETIMEDOUT;
@@ -1955,7 +1952,7 @@ static int lpc17_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
static int lpc17_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort)
{
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
uint32_t respcmd;
#endif
uint32_t regval;
@@ -1984,10 +1981,10 @@ static int lpc17_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
*/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!rshort)
{
- fdbg("ERROR: rshort=NULL\n");
+ mcerr("ERROR: rshort=NULL\n");
ret = -EINVAL;
}
@@ -1997,7 +1994,7 @@ static int lpc17_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1B_RESPONSE &&
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE)
{
- fdbg("ERROR: Wrong response CMD=%08x\n", cmd);
+ mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
ret = -EINVAL;
}
else
@@ -2008,15 +2005,15 @@ static int lpc17_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
regval = getreg32(LPC17_SDCARD_STATUS);
if ((regval & SDCARD_STATUS_CTIMEOUT) != 0)
{
- fdbg("ERROR: Command timeout: %08x\n", regval);
+ mcerr("ERROR: Command timeout: %08x\n", regval);
ret = -ETIMEDOUT;
}
else if ((regval & SDCARD_STATUS_CCRCFAIL) != 0)
{
- fdbg("ERROR: CRC failure: %08x\n", regval);
+ mcerr("ERROR: CRC failure: %08x\n", regval);
ret = -EIO;
}
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
else
{
/* Check response received is of desired command */
@@ -2024,7 +2021,7 @@ static int lpc17_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
respcmd = getreg32(LPC17_SDCARD_RESPCMD);
if ((uint8_t)(respcmd & SDCARD_RESPCMD_MASK) != (cmd & MMCSD_CMDIDX_MASK))
{
- fdbg("ERROR: RESCMD=%02x CMD=%08x\n", respcmd, cmd);
+ mcerr("ERROR: RESCMD=%02x CMD=%08x\n", respcmd, cmd);
ret = -EINVAL;
}
}
@@ -2052,12 +2049,12 @@ static int lpc17_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo
* 0 1 End bit
*/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
/* Check that R1 is the correct response to this command */
if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE)
{
- fdbg("ERROR: Wrong response CMD=%08x\n", cmd);
+ mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
ret = -EINVAL;
}
else
@@ -2068,12 +2065,12 @@ static int lpc17_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo
regval = getreg32(LPC17_SDCARD_STATUS);
if (regval & SDCARD_STATUS_CTIMEOUT)
{
- fdbg("ERROR: Timeout STA: %08x\n", regval);
+ mcerr("ERROR: Timeout STA: %08x\n", regval);
ret = -ETIMEDOUT;
}
else if (regval & SDCARD_STATUS_CCRCFAIL)
{
- fdbg("ERROR: CRC fail STA: %08x\n", regval);
+ mcerr("ERROR: CRC fail STA: %08x\n", regval);
ret = -EIO;
}
}
@@ -2107,11 +2104,11 @@ static int lpc17_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r
/* Check that this is the correct response to this command */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE &&
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE)
{
- fdbg("ERROR: Wrong response CMD=%08x\n", cmd);
+ mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
ret = -EINVAL;
}
else
@@ -2124,7 +2121,7 @@ static int lpc17_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r
regval = getreg32(LPC17_SDCARD_STATUS);
if (regval & SDCARD_STATUS_CTIMEOUT)
{
- fdbg("ERROR: Timeout STA: %08x\n", regval);
+ mcerr("ERROR: Timeout STA: %08x\n", regval);
ret = -ETIMEDOUT;
}
}
@@ -2269,7 +2266,7 @@ static sdio_eventset_t lpc17_eventwait(FAR struct sdio_dev_s *dev,
1, (uint32_t)priv);
if (ret != OK)
{
- fdbg("ERROR: wd_start failed: %d\n", ret);
+ mcerr("ERROR: wd_start failed: %d\n", ret);
}
}
@@ -2341,7 +2338,7 @@ static void lpc17_callbackenable(FAR struct sdio_dev_s *dev,
{
struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev;
- fvdbg("eventset: %02x\n", eventset);
+ mcinfo("eventset: %02x\n", eventset);
DEBUGASSERT(priv != NULL);
priv->cbevents = eventset;
@@ -2377,7 +2374,7 @@ static int lpc17_registercallback(FAR struct sdio_dev_s *dev,
/* Disable callbacks and register this callback and is argument */
- fvdbg("Register %p(%p)\n", callback, arg);
+ mcinfo("Register %p(%p)\n", callback, arg);
DEBUGASSERT(priv != NULL);
priv->cbevents = 0;
@@ -2590,8 +2587,8 @@ static void lpc17_callback(void *arg)
/* Is a callback registered? */
DEBUGASSERT(priv != NULL);
- fvdbg("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
- priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
+ mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
+ priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
if (priv->callback)
{
@@ -2635,14 +2632,14 @@ static void lpc17_callback(void *arg)
{
/* Yes.. queue it */
- fvdbg("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
+ mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
(void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
}
else
{
/* No.. then just call the callback here */
- fvdbg("Callback to %p(%p)\n", priv->callback, priv->cbarg);
+ mcinfo("Callback to %p(%p)\n", priv->callback, priv->cbarg);
priv->callback(priv->cbarg);
}
}
@@ -2781,7 +2778,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
{
priv->cdstatus &= ~SDIO_STATUS_PRESENT;
}
- fvdbg("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
+ mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
/* Perform any requested callback if the status has changed */
@@ -2824,7 +2821,8 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
{
priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED;
}
- fvdbg("cdstatus: %02x\n", priv->cdstatus);
+
+ mcinfo("cdstatus: %02x\n", priv->cdstatus);
leave_critical_section(flags);
}
#endif /* CONFIG_LPC17_SDCARD */
diff --git a/arch/arm/src/lpc17xx/lpc17_serial.c b/arch/arm/src/lpc17xx/lpc17_serial.c
index d0e2ceeecf93c6379e7850339d11e8d4ee0dccac..7062c521f484b095a367934d9af96372b88aebcc 100644
--- a/arch/arm/src/lpc17xx/lpc17_serial.c
+++ b/arch/arm/src/lpc17xx/lpc17_serial.c
@@ -1134,7 +1134,7 @@ static int up_interrupt(int irq, void *context)
/* Read the modem status register (MSR) to clear */
status = up_serialin(priv, LPC17_UART_MSR_OFFSET);
- vdbg("MSR: %02x\n", status);
+ _info("MSR: %02x\n", status);
break;
}
@@ -1145,7 +1145,7 @@ static int up_interrupt(int irq, void *context)
/* Read the line status register (LSR) to clear */
status = up_serialin(priv, LPC17_UART_LSR_OFFSET);
- vdbg("LSR: %02x\n", status);
+ _info("LSR: %02x\n", status);
break;
}
@@ -1153,7 +1153,7 @@ static int up_interrupt(int irq, void *context)
default:
{
- dbg("Unexpected IIR: %02x\n", status);
+ _err("ERROR: Unexpected IIR: %02x\n", status);
break;
}
}
diff --git a/arch/arm/src/lpc17xx/lpc17_spi.c b/arch/arm/src/lpc17xx/lpc17_spi.c
index c915d1dfc2328944b2967d684523ff9c35abf9d2..6ddef3951fc28d26cce59ca4172516f3f3a7d219 100644
--- a/arch/arm/src/lpc17xx/lpc17_spi.c
+++ b/arch/arm/src/lpc17xx/lpc17_spi.c
@@ -71,26 +71,6 @@
# error "CONFIG_SPI_EXCHANGE must not be defined in the configuration"
#endif
-/* Debug ********************************************************************/
-/* The following enable debug output from this file:
- *
- * CONFIG_DEBUG - Define to enable general debug features
- * CONFIG_DEBUG_SPI - Define to enable basic SSP debug (needs CONFIG_DEBUG)
- * CONFIG_DEBUG_VERBOSE - Define to enable verbose SSP debug
- */
-
-#ifdef CONFIG_DEBUG_SPI
-# define spidbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define spivdbg lldbg
-# else
-# define spivdbg(x...)
-# endif
-#else
-# define spidbg(x...)
-# define spivdbg(x...)
-#endif
-
/* SSP Clocking *************************************************************/
/* The CPU clock by 1, 2, 4, or 8 to get the SPI peripheral clock (SPI_CLOCK).
* SPI_CLOCK may be further divided by 8-254 to get the SPI clock. If we
@@ -287,7 +267,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
priv->frequency = frequency;
priv->actual = actual;
- spidbg("Frequency %d->%d\n", frequency, actual);
+ spiinfo("Frequency %d->%d\n", frequency, actual);
return actual;
}
@@ -449,7 +429,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
FAR uint8_t *ptr = (FAR uint8_t *)buffer;
uint8_t data;
- spidbg("nwords: %d\n", nwords);
+ spiinfo("nwords: %d\n", nwords);
while (nwords)
{
/* Write the data to transmitted to the SPI Data Register */
@@ -494,7 +474,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
{
FAR uint8_t *ptr = (FAR uint8_t *)buffer;
- spidbg("nwords: %d\n", nwords);
+ spiinfo("nwords: %d\n", nwords);
while (nwords)
{
/* Write some dummy data to the SPI Data Register in order to clock the
diff --git a/arch/arm/src/lpc17xx/lpc17_ssp.c b/arch/arm/src/lpc17xx/lpc17_ssp.c
index 9cdee092423c8c8320d84242a56a8b5c8f7d5b58..d66abf4d9d7e6a2753ac1bbae8edbc2a789388bf 100644
--- a/arch/arm/src/lpc17xx/lpc17_ssp.c
+++ b/arch/arm/src/lpc17xx/lpc17_ssp.c
@@ -72,26 +72,6 @@
# error "CONFIG_SPI_EXCHANGE must not be defined in the configuration"
#endif
-/* Debug ********************************************************************/
-/* The following enable debug output from this file:
- *
- * CONFIG_DEBUG - Define to enable general debug features
- * CONFIG_DEBUG_SPI - Define to enable basic SSP debug (needs CONFIG_DEBUG)
- * CONFIG_DEBUG_VERBOSE - Define to enable verbose SSP debug
- */
-
-#ifdef CONFIG_DEBUG_SPI
-# define sspdbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define spivdbg lldbg
-# else
-# define spivdbg(x...)
-# endif
-#else
-# define sspdbg(x...)
-# define spivdbg(x...)
-#endif
-
/* SSP Clocking *************************************************************/
#if defined(LPC176x)
@@ -470,7 +450,7 @@ static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
priv->frequency = frequency;
priv->actual = actual;
- sspdbg("Frequency %d->%d\n", frequency, actual);
+ spiinfo("Frequency %d->%d\n", frequency, actual);
return actual;
}
@@ -521,7 +501,7 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
break;
default:
- sspdbg("Bad mode: %d\n", mode);
+ spierr("ERROR: Bad mode: %d\n", mode);
DEBUGASSERT(FALSE);
return;
}
@@ -609,7 +589,7 @@ static uint16_t ssp_send(FAR struct spi_dev_s *dev, uint16_t wd)
/* Get the value from the RX FIFO and return it */
regval = ssp_getreg(priv, LPC17_SSP_DR_OFFSET);
- sspdbg("%04x->%04x\n", wd, regval);
+ spiinfo("%04x->%04x\n", wd, regval);
return (uint16_t)regval;
}
@@ -646,7 +626,7 @@ static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
/* Loop while thre are bytes remaining to be sent */
- sspdbg("nwords: %d\n", nwords);
+ spiinfo("nwords: %d\n", nwords);
u.pv = buffer;
while (nwords > 0)
{
@@ -674,7 +654,7 @@ static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
/* Then discard all card responses until the RX & TX FIFOs are emptied. */
- sspdbg("discarding\n");
+ spiinfo("discarding\n");
do
{
/* Is there anything in the RX fifo? */
@@ -735,7 +715,7 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
/* While there is remaining to be sent (and no synchronization error has occurred) */
- sspdbg("nwords: %d\n", nwords);
+ spiinfo("nwords: %d\n", nwords);
u.pv = buffer;
while (nwords || rxpending)
{
@@ -745,7 +725,7 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
* and (3) there are more bytes to be sent.
*/
- spivdbg("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
+ spiinfo("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
while ((ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_TNF) &&
(rxpending < LPC17_SSP_FIFOSZ) && nwords)
{
@@ -756,7 +736,7 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
/* Now, read the RX data from the RX FIFO while the RX FIFO is not empty */
- spivdbg("RX: rxpending: %d\n", rxpending);
+ spiinfo("RX: rxpending: %d\n", rxpending);
while (ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_RNE)
{
data = (uint8_t)ssp_getreg(priv, LPC17_SSP_DR_OFFSET);
diff --git a/arch/arm/src/lpc17xx/lpc17_start.c b/arch/arm/src/lpc17xx/lpc17_start.c
index 8d95518d02d3db2e930b93ff0e956cb4e8eba1e2..3a0ae1d70554331623ad0447b8a4df2949941ed5 100644
--- a/arch/arm/src/lpc17xx/lpc17_start.c
+++ b/arch/arm/src/lpc17xx/lpc17_start.c
@@ -82,7 +82,7 @@
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) up_lowputc(c)
#else
# define showprogress(c)
diff --git a/arch/arm/src/lpc17xx/lpc17_timer.c b/arch/arm/src/lpc17xx/lpc17_timer.c
index b4a821ffc0b97e507b807ef877fc715e54b22249..9278578b6785d95f8f3f8ede2d760cc50f8165f6 100644
--- a/arch/arm/src/lpc17xx/lpc17_timer.c
+++ b/arch/arm/src/lpc17xx/lpc17_timer.c
@@ -82,29 +82,10 @@
/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing PWM */
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_PWM
-#endif
-
-#ifdef CONFIG_DEBUG_PWM
-# define pwmdbg dbg
-# define pwmlldbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define pwmvdbg vdbg
-# define pwmllvdbg llvdbg
-# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
-# else
-# define pwmlldbg(x...)
-# define pwmllvdbg(x...)
-# define pwm_dumpgpio(p,m)
-# endif
+#ifdef CONFIG_DEBUG_PWM_INFO
+# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
#else
-# define pwmdbg(x...)
-# define pwmlldbg(x...)
-# define pwmvdbg(x...)
-# define pwmllvdbg(x...)
# define pwm_dumpgpio(p,m)
#endif
@@ -133,7 +114,7 @@ struct lpc17_timer_s
static uint32_t timer_getreg(struct lpc17_timer_s *priv, int offset);
static void timer_putreg(struct lpc17_timer_s *priv, int offset, uint32_t value);
-#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_PWM_INFO
static void timer_dumpregs(struct lpc17_timer_s *priv, FAR const char *msg);
#else
# define timer_dumpregs(priv,msg)
@@ -242,11 +223,11 @@ static void timer_putreg(struct lpc17_timer_s *priv, int offset,
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_PWM_INFO
static void timer_dumpregs(struct lpc17_timer_s *priv, FAR const char *msg)
{
- pwmdbg("%s:\n", msg);
- pwmdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
+ pwminfo("%s:\n", msg);
+ pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
timer_getreg(priv, LPC17_PWM_MR0_OFFSET),
timer_getreg(priv, LPC17_PWM_MR1_OFFSET),
timer_getreg(priv, LPC17_PWM_MR2_OFFSET),
@@ -254,7 +235,7 @@ static void timer_dumpregs(struct lpc17_timer_s *priv, FAR const char *msg)
#if defined(CONFIG_LPC17_TMR0)
if (priv->timtype == TIMTYPE_ADVANCED)
{
- pwmdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
+ pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
timer_getreg(priv, LPC17_PWM_MR0_OFFSET),
timer_getreg(priv, LPC17_PWM_MR1_OFFSET),
timer_getreg(priv, LPC17_PWM_MR2_OFFSET),
@@ -263,7 +244,7 @@ static void timer_dumpregs(struct lpc17_timer_s *priv, FAR const char *msg)
else
#endif
{
- pwmdbg(" DCR: %04x DMAR: %04x\n",
+ pwminfo(" DCR: %04x DMAR: %04x\n",
timer_getreg(priv, LPC17_PWM_MR2_OFFSET),
timer_getreg(priv, LPC17_PWM_MR3_OFFSET));
}
@@ -469,7 +450,7 @@ static int timer_shutdown(FAR struct pwm_lowerhalf_s *dev)
FAR struct lpc17_timer_s *priv = (FAR struct lpc17_timer_s *)dev;
uint32_t pincfg;
- pwmdbg("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg);
+ pwminfo("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg);
/* Make sure that the output has been stopped */
@@ -525,7 +506,7 @@ static int timer_stop(FAR struct pwm_lowerhalf_s *dev)
uint32_t regval;
irqstate_t flags;
- pwmdbg("TIM%d\n", priv->timid);
+ pwminfo("TIM%d\n", priv->timid);
/* Disable interrupts momentary to stop any ongoing timer processing and
* to prevent any concurrent access to the reset register.
@@ -551,7 +532,7 @@ static int timer_stop(FAR struct pwm_lowerhalf_s *dev)
leave_critical_section(flags);
- pwmdbg("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
+ pwminfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
timer_dumpregs(priv, "After stop");
return OK;
}
@@ -574,12 +555,12 @@ static int timer_stop(FAR struct pwm_lowerhalf_s *dev)
static int timer_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg)
{
-#ifdef CONFIG_DEBUG_TIMER
+#ifdef CONFIG_DEBUG_PWM_INFO
FAR struct lpc17_timer_s *priv = (FAR struct lpc17_timer_s *)dev;
/* There are no platform-specific ioctl commands */
- pwmdbg("TIM%d\n", priv->timid);
+ pwminfo("TIM%d\n", priv->timid);
#endif
return -ENOTTY;
}
@@ -609,7 +590,7 @@ FAR struct pwm_lowerhalf_s *lpc17_timerinitialize(int timer)
{
FAR struct lpc17_timer_s *lower;
- pwmdbg("TIM%d\n", timer);
+ pwminfo("TIM%d\n", timer);
switch (timer)
{
@@ -623,7 +604,7 @@ FAR struct pwm_lowerhalf_s *lpc17_timerinitialize(int timer)
#endif
default:
- pwmdbg("No such timer configured\n");
+ pwmerr("ERROR: No such timer configured\n");
return NULL;
}
diff --git a/arch/arm/src/lpc17xx/lpc17_usbdev.c b/arch/arm/src/lpc17xx/lpc17_usbdev.c
index 9995e03cdaddbe25fae2b6051b41edeb0fe8cfc9..ca4d5f90d803456e10d95c415d41de0d3ed2eadd 100644
--- a/arch/arm/src/lpc17xx/lpc17_usbdev.c
+++ b/arch/arm/src/lpc17xx/lpc17_usbdev.c
@@ -99,20 +99,23 @@
# define USB_FRAME_INT 0
#endif
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
# define USB_ERROR_INT USBDEV_INT_ERRINT
#else
-# undef CONFIG_LPC17_USBDEV_REGDEBUG
# define USB_ERROR_INT 0
#endif
+#ifndef CONFIG_DEBUG_USB_INFO
+# undef CONFIG_LPC17_USBDEV_REGDEBUG
+#endif
+
/* CLKCTRL enable bits */
#define LPC17_CLKCTRL_ENABLES (USBDEV_CLK_DEVCLK|USBDEV_CLK_AHBCLK)
/* Dump GPIO registers */
-#if defined(CONFIG_LPC17_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_GPIO)
+#if defined(CONFIG_LPC17_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO)
# define usbdev_dumpgpio() \
do { \
lpc17_dumpgpio(GPIO_USB_DP, "D+ P0.29; D- P0.30"); \
@@ -531,7 +534,7 @@ static struct lpc17_dmadesc_s g_usbddesc[CONFIG_LPC17_USBDEV_NDMADESCRIPTORS];
#ifdef CONFIG_LPC17_USBDEV_REGDEBUG
static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite)
{
- lldbg("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
+ uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
}
#endif
@@ -581,7 +584,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite)
{
/* No.. More than one. */
- lldbg("[repeats %d more times]\n", count);
+ uinfo("[repeats %d more times]\n", count);
}
}
@@ -1076,8 +1079,9 @@ static int lpc17_wrrequest(struct lpc17_ep_s *privep)
return OK;
}
- ullvdbg("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
- privep->epphy, privreq, privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
+ uinfo("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
+ privep->epphy, privreq, privreq->req.len, privreq->req.xfrd,
+ privep->txnullpkt);
/* Ignore any attempt to send a zero length packet on anything but EP0IN */
@@ -1185,8 +1189,8 @@ static int lpc17_rdrequest(struct lpc17_ep_s *privep)
return OK;
}
- ullvdbg("len=%d xfrd=%d nullpkt=%d\n",
- privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
+ uinfo("len=%d xfrd=%d nullpkt=%d\n",
+ privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
/* Ignore any attempt to receive a zero length packet */
@@ -1593,8 +1597,8 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv)
index = GETUINT16(ctrl.index);
len = GETUINT16(ctrl.len);
- ullvdbg("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- ctrl.type, ctrl.req, value, index, len);
+ uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ ctrl.type, ctrl.req, value, index, len);
/* Dispatch any non-standard requests */
@@ -1739,7 +1743,7 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv)
if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
value == USB_FEATURE_TESTMODE)
{
- ullvdbg("test mode: %d\n", index);
+ uinfo("test mode: %d\n", index);
}
else if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@@ -2090,7 +2094,7 @@ static int lpc17_usbinterrupt(int irq, FAR void *context)
#endif
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
/* USB engine error interrupt */
if ((devintstatus & USBDEV_INT_ERRINT) != 0)
@@ -2321,7 +2325,7 @@ static int lpc17_usbinterrupt(int irq, FAR void *context)
}
else
{
- ullvdbg("Pending data on OUT endpoint\n");
+ uinfo("Pending data on OUT endpoint\n");
priv->rxpending = 1;
}
}
@@ -2412,7 +2416,7 @@ static int lpc17_dmasetup(struct lpc17_usbdev_s *priv, uint8_t epphy,
struct lpc17_dmadesc_s *dmadesc = priv;
uint32_t regval;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!priv || epphy < 2)
{
usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0);
@@ -2611,13 +2615,14 @@ static int lpc17_epdisable(FAR struct usbdev_ep_s *ep)
uint32_t mask = (1 << privep->epphy);
uint32_t regval;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!ep)
{
usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0);
return -EINVAL;
}
#endif
+
usbtrace(TRACE_EPDISABLE, privep->epphy);
/* Cancel any ongoing activity */
@@ -2653,13 +2658,14 @@ static FAR struct usbdev_req_s *lpc17_epallocreq(FAR struct usbdev_ep_s *ep)
{
FAR struct lpc17_req_s *privreq;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!ep)
{
usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0);
return NULL;
}
#endif
+
usbtrace(TRACE_EPALLOCREQ, ((FAR struct lpc17_ep_s *)ep)->epphy);
privreq = (FAR struct lpc17_req_s *)kmm_malloc(sizeof(struct lpc17_req_s));
@@ -2685,13 +2691,14 @@ static void lpc17_epfreereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s
{
FAR struct lpc17_req_s *privreq = (FAR struct lpc17_req_s *)req;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0);
return;
}
#endif
+
usbtrace(TRACE_EPFREEREQ, ((FAR struct lpc17_ep_s *)ep)->epphy);
kmm_free(privreq);
@@ -2793,11 +2800,12 @@ static int lpc17_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
irqstate_t flags;
int ret = OK;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0);
- ullvdbg("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+ uinfo("req=%p callback=%p buf=%p ep=%p\n",
+ req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
@@ -2878,7 +2886,7 @@ static int lpc17_epcancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
FAR struct lpc17_ep_s *privep = (FAR struct lpc17_ep_s *)ep;
irqstate_t flags;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0);
@@ -3142,7 +3150,7 @@ static int lpc17_selfpowered(struct usbdev_s *dev, bool selfpowered)
usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!dev)
{
usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0);
@@ -3406,7 +3414,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
usbtrace(TRACE_DEVREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!driver || !driver->ops->bind || !driver->ops->unbind ||
!driver->ops->disconnect || !driver->ops->setup)
{
@@ -3456,7 +3464,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
{
usbtrace(TRACE_DEVUNREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (driver != g_usbdev.driver)
{
usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0);
diff --git a/arch/arm/src/lpc17xx/lpc17_usbhost.c b/arch/arm/src/lpc17xx/lpc17_usbhost.c
index 94003be06d79178b5eb5ebb2299039e2c9e15713..d8d02f629c0ff563d385233701f8adbadc422b8d 100644
--- a/arch/arm/src/lpc17xx/lpc17_usbhost.c
+++ b/arch/arm/src/lpc17xx/lpc17_usbhost.c
@@ -88,6 +88,10 @@
# define CONFIG_LPC17_USBHOST_NPREALLOC 8
#endif
+#ifndef CONFIG_DEBUG_USB_INFO
+# undef CONFIG_LPC17_USBHOST_REGDEBUG
+#endif
+
/* OHCI Setup ******************************************************************/
/* Frame Interval / Periodic Start */
@@ -114,7 +118,7 @@
/* Dump GPIO registers */
-#if defined(CONFIG_LPC17_USBHOST_REGDEBUG) && defined(CONFIG_DEBUG_GPIO)
+#ifdef CONFIG_LPC17_USBHOST_REGDEBUG
# define usbhost_dumpgpio() \
do { \
lpc17_dumpgpio(GPIO_USB_DP, "D+ P0.29; D- P0.30"); \
@@ -456,7 +460,7 @@ static struct lpc17_xfrinfo_s g_xfrbuffers[CONFIG_LPC17_USBHOST_NPREALLOC];
#ifdef CONFIG_LPC17_USBHOST_REGDEBUG
static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite)
{
- lldbg("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
+ uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
}
#endif
@@ -506,7 +510,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite)
{
/* No.. More than one. */
- lldbg("[repeats %d more times]\n", count);
+ uinfo("[repeats %d more times]\n", count);
}
}
@@ -1192,7 +1196,7 @@ static inline int lpc17_addinted(struct lpc17_usbhost_s *priv,
interval = lpc17_getinterval(epdesc->interval);
ed->interval = interval;
- uvdbg("interval: %d->%d\n", epdesc->interval, interval);
+ uinfo("interval: %d->%d\n", epdesc->interval, interval);
/* Get the offset associated with the ED direction. IN EDs get the even
* entries, OUT EDs get the odd entries.
@@ -1225,7 +1229,7 @@ static inline int lpc17_addinted(struct lpc17_usbhost_s *priv,
interval = priv->outinterval;
}
}
- uvdbg("min interval: %d offset: %d\n", interval, offset);
+ uinfo("min interval: %d offset: %d\n", interval, offset);
/* Get the head of the first of the duplicated entries. The first offset
* entry is always guaranteed to contain the common ED list head.
@@ -1244,7 +1248,7 @@ static inline int lpc17_addinted(struct lpc17_usbhost_s *priv,
ed->hw.nexted = head;
lpc17_setinttab((uint32_t)ed, interval, offset);
- uvdbg("head: %08x next: %08x\n", ed, head);
+ uinfo("head: %08x next: %08x\n", ed, head);
/* Re-enabled periodic list processing */
@@ -1314,7 +1318,7 @@ static inline int lpc17_reminted(struct lpc17_usbhost_s *priv,
*/
head = (struct lpc17_ed_s *)HCCA->inttbl[offset];
- uvdbg("ed: %08x head: %08x next: %08x offset: %d\n",
+ uinfo("ed: %08x head: %08x next: %08x offset: %d\n",
ed, head, head ? head->hw.nexted : 0, offset);
/* Find the ED to be removed in the ED list */
@@ -1349,7 +1353,7 @@ static inline int lpc17_reminted(struct lpc17_usbhost_s *priv,
prev->hw.nexted = ed->hw.nexted;
}
- uvdbg("ed: %08x head: %08x next: %08x\n",
+ uinfo("ed: %08x head: %08x next: %08x\n",
ed, head, head ? head->hw.nexted : 0);
/* Calculate the new minimum interval for this list */
@@ -1363,7 +1367,7 @@ static inline int lpc17_reminted(struct lpc17_usbhost_s *priv,
}
}
- uvdbg("min interval: %d offset: %d\n", interval, offset);
+ uinfo("min interval: %d offset: %d\n", interval, offset);
/* Save the new minimum interval */
@@ -1547,7 +1551,7 @@ static int lpc17_ctrltd(struct lpc17_usbhost_s *priv, struct lpc17_ed_s *ed,
xfrinfo = lpc17_alloc_xfrinfo();
if (xfrinfo == NULL)
{
- udbg("ERROR: lpc17_alloc_xfrinfo failed\n");
+ uerr("ERROR: lpc17_alloc_xfrinfo failed\n");
return -ENOMEM;
}
@@ -1566,7 +1570,7 @@ static int lpc17_ctrltd(struct lpc17_usbhost_s *priv, struct lpc17_ed_s *ed,
ret = lpc17_wdhwait(priv, ed);
if (ret < 0)
{
- udbg("ERROR: Device disconnected\n");
+ uerr("ERROR: Device disconnected\n");
goto errout_with_xfrinfo;
}
@@ -1607,7 +1611,7 @@ static int lpc17_ctrltd(struct lpc17_usbhost_s *priv, struct lpc17_ed_s *ed,
}
else
{
- udbg("ERROR: Bad TD completion status: %d\n", xfrinfo->tdstatus);
+ uerr("ERROR: Bad TD completion status: %d\n", xfrinfo->tdstatus);
ret = xfrinfo->tdstatus == TD_CC_STALL ? -EPERM : -EIO;
}
}
@@ -1642,7 +1646,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
intst = lpc17_getreg(LPC17_USBHOST_INTST);
regval = lpc17_getreg(LPC17_USBHOST_INTEN);
- ullvdbg("INST: %08x INTEN: %08x\n", intst, regval);
+ uinfo("INST: %08x INTEN: %08x\n", intst, regval);
pending = intst & regval;
if (pending != 0)
@@ -1652,18 +1656,18 @@ static int lpc17_usbinterrupt(int irq, void *context)
if ((pending & OHCI_INT_RHSC) != 0)
{
uint32_t rhportst1 = lpc17_getreg(LPC17_USBHOST_RHPORTST1);
- ullvdbg("Root Hub Status Change, RHPORTST1: %08x\n", rhportst1);
+ uinfo("Root Hub Status Change, RHPORTST1: %08x\n", rhportst1);
if ((rhportst1 & OHCI_RHPORTST_CSC) != 0)
{
uint32_t rhstatus = lpc17_getreg(LPC17_USBHOST_RHSTATUS);
- ullvdbg("Connect Status Change, RHSTATUS: %08x\n", rhstatus);
+ uinfo("Connect Status Change, RHSTATUS: %08x\n", rhstatus);
/* If DRWE is set, Connect Status Change indicates a remote wake-up event */
if (rhstatus & OHCI_RHSTATUS_DRWE)
{
- ullvdbg("DRWE: Remote wake-up\n");
+ uinfo("DRWE: Remote wake-up\n");
}
/* Otherwise... Not a remote wake-up event */
@@ -1680,7 +1684,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
{
/* Yes.. connected. */
- ullvdbg("Connected\n");
+ uinfo("Connected\n");
priv->connected = true;
priv->change = true;
@@ -1694,7 +1698,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
}
else
{
- ulldbg("Spurious status change (connected)\n");
+ uwarn("WARNING: Spurious status change (connected)\n");
}
/* The LSDA (Low speed device attached) bit is valid
@@ -1710,7 +1714,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
priv->rhport.hport.speed = USB_SPEED_FULL;
}
- ullvdbg("Speed:%d\n", priv->rhport.hport.speed);
+ uinfo("Speed:%d\n", priv->rhport.hport.speed);
}
/* Check if we are now disconnected */
@@ -1719,7 +1723,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
{
/* Yes.. disconnect the device */
- ullvdbg("Disconnected\n");
+ uinfo("Disconnected\n");
priv->connected = false;
priv->change = true;
@@ -1750,7 +1754,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
}
else
{
- ulldbg("Spurious status change (disconnected)\n");
+ uwarn("WARNING: Spurious status change (disconnected)\n");
}
}
@@ -1830,9 +1834,9 @@ static int lpc17_usbinterrupt(int irq, void *context)
{
/* The transfer failed for some reason... dump some diagnostic info. */
- ulldbg("ERROR: ED xfrtype:%d TD CTRL:%08x/CC:%d RHPORTST1:%08x\n",
- ed->xfrtype, td->hw.ctrl, xfrinfo->tdstatus,
- lpc17_getreg(LPC17_USBHOST_RHPORTST1));
+ uerr("ERROR: ED xfrtype:%d TD CTRL:%08x/CC:%d RHPORTST1:%08x\n",
+ ed->xfrtype, td->hw.ctrl, xfrinfo->tdstatus,
+ lpc17_getreg(LPC17_USBHOST_RHPORTST1));
}
#endif
@@ -1894,7 +1898,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
#ifdef CONFIG_DEBUG_USB
if ((pending & LPC17_DEBUG_INTS) != 0)
{
- ulldbg("ERROR: Unhandled interrupts INTST:%08x\n", intst);
+ uerr("ERROR: Unhandled interrupts INTST:%08x\n", intst);
}
#endif
@@ -1967,8 +1971,8 @@ static int lpc17_wait(struct usbhost_connection_s *conn,
*hport = connport;
leave_critical_section(flags);
- udbg("RHport Connected: %s\n",
- connport->connected ? "YES" : "NO");
+ uinfo("RHport Connected: %s\n",
+ connport->connected ? "YES" : "NO");
return OK;
}
@@ -1987,7 +1991,7 @@ static int lpc17_wait(struct usbhost_connection_s *conn,
*hport = connport;
leave_critical_section(flags);
- udbg("Hub port Connected: %s\n", connport->connected ? "YES" : "NO");
+ uinfo("Hub port Connected: %s\n", connport->connected ? "YES" : "NO");
return OK;
}
#endif
@@ -2041,7 +2045,7 @@ static int lpc17_rh_enumerate(struct usbhost_connection_s *conn,
{
/* No, return an error */
- udbg("Not connected\n");
+ uwarn("WARNING: Not connected\n");
return -ENODEV;
}
@@ -2089,11 +2093,11 @@ static int lpc17_enumerate(FAR struct usbhost_connection_s *conn,
/* Then let the common usbhost_enumerate do the real enumeration. */
- uvdbg("Enumerate the device\n");
+ uinfo("Enumerate the device\n");
ret = usbhost_enumerate(hport, &hport->devclass);
if (ret < 0)
{
- udbg("ERROR: Enumeration failed: %d\n", ret);
+ uerr("ERROR: Enumeration failed: %d\n", ret);
}
return ret;
@@ -2155,7 +2159,7 @@ static int lpc17_ep0configure(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
lpc17_givesem(&priv->exclsem);
- uvdbg("EP0 CTRL:%08x\n", ed->hw.ctrl);
+ uinfo("EP0 CTRL:%08x\n", ed->hw.ctrl);
return OK;
}
@@ -2255,7 +2259,7 @@ static int lpc17_epalloc(struct usbhost_driver_s *drvr,
ed->hw.ctrl |= ED_CONTROL_F;
}
#endif
- uvdbg("EP%d CTRL:%08x\n", epdesc->addr, ed->hw.ctrl);
+ uinfo("EP%d CTRL:%08x\n", epdesc->addr, ed->hw.ctrl);
/* Initialize the semaphore that is used to wait for the endpoint
* WDH event.
@@ -2299,7 +2303,7 @@ static int lpc17_epalloc(struct usbhost_driver_s *drvr,
{
/* No.. destroy it and report the error */
- udbg("ERROR: Failed to queue ED for transfer type: %d\n", ed->xfrtype);
+ uerr("ERROR: Failed to queue ED for transfer type: %d\n", ed->xfrtype);
sem_destroy(&ed->wdhsem);
lpc17_edfree(ed);
}
@@ -2608,7 +2612,7 @@ static int lpc17_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
DEBUGASSERT(priv != NULL && ed != NULL && req != NULL);
- uvdbg("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
+ uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
req->type, req->req, req->value[1], req->value[0],
req->index[1], req->index[0], req->len[1], req->len[0]);
@@ -2646,7 +2650,7 @@ static int lpc17_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
DEBUGASSERT(priv != NULL && ed != NULL && req != NULL);
- uvdbg("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
+ uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
req->type, req->req, req->value[1], req->value[0],
req->index[1], req->index[0], req->len[1], req->len[0]);
@@ -2712,7 +2716,7 @@ static int lpc17_transfer_common(struct lpc17_usbhost_s *priv,
xfrinfo = ed->xfrinfo;
in = (ed->hw.ctrl & ED_CONTROL_D_MASK) == ED_CONTROL_D_IN;
- uvdbg("EP%u %s toggle:%u maxpacket:%u buflen:%lu\n",
+ uinfo("EP%u %s toggle:%u maxpacket:%u buflen:%lu\n",
(ed->hw.ctrl & ED_CONTROL_EN_MASK) >> ED_CONTROL_EN_SHIFT,
in ? "IN" : "OUT",
(ed->hw.headp & ED_HEADP_C) != 0 ? 1 : 0,
@@ -2790,7 +2794,7 @@ static int lpc17_dma_alloc(struct lpc17_usbhost_s *priv,
if (buflen > CONFIG_USBHOST_IOBUFSIZE)
{
- uvdbg("buflen (%d) > IO buffer size (%d)\n",
+ uinfo("buflen (%d) > IO buffer size (%d)\n",
buflen, CONFIG_USBHOST_IOBUFSIZE);
return -ENOMEM;
}
@@ -2800,7 +2804,7 @@ static int lpc17_dma_alloc(struct lpc17_usbhost_s *priv,
newbuffer = lpc17_allocio();
if (!newbuffer)
{
- uvdbg("IO buffer allocation failed\n");
+ uinfo("IO buffer allocation failed\n");
return -ENOMEM;
}
@@ -2947,7 +2951,7 @@ static ssize_t lpc17_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep,
xfrinfo = lpc17_alloc_xfrinfo();
if (xfrinfo == NULL)
{
- udbg("ERROR: lpc17_alloc_xfrinfo failed\n");
+ uerr("ERROR: lpc17_alloc_xfrinfo failed\n");
nbytes = -ENOMEM;
goto errout_with_sem;
}
@@ -2966,7 +2970,7 @@ static ssize_t lpc17_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep,
ret = lpc17_dma_alloc(priv, ed, buffer, buflen, &alloc);
if (ret < 0)
{
- udbg("ERROR: lpc17_dma_alloc failed: %d\n", ret);
+ uerr("ERROR: lpc17_dma_alloc failed: %d\n", ret);
nbytes = (ssize_t)ret;
goto errout_with_xfrinfo;
}
@@ -2987,7 +2991,7 @@ static ssize_t lpc17_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep,
ret = lpc17_wdhwait(priv, ed);
if (ret < 0)
{
- udbg("ERROR: Device disconnected\n");
+ uerr("ERROR: Device disconnected\n");
nbytes = (ssize_t)ret;
goto errout_with_buffers;
}
@@ -2997,7 +3001,7 @@ static ssize_t lpc17_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep,
ret = lpc17_transfer_common(priv, ed, buffer, buflen);
if (ret < 0)
{
- udbg("ERROR: lpc17_transfer_common failed: %d\n", ret);
+ uerr("ERROR: lpc17_transfer_common failed: %d\n", ret);
nbytes = (ssize_t)ret;
goto errout_with_wdhwait;
}
@@ -3021,7 +3025,7 @@ static ssize_t lpc17_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep,
* might understand.
*/
- udbg("ERROR: Bad TD completion status: %d\n", xfrinfo->tdstatus);
+ uerr("ERROR: Bad TD completion status: %d\n", xfrinfo->tdstatus);
switch (xfrinfo->tdstatus)
{
@@ -3111,7 +3115,7 @@ static void lpc17_asynch_completion(struct lpc17_usbhost_s *priv,
* might understand.
*/
- udbg("ERROR: Bad TD completion status: %d\n", xfrinfo->tdstatus);
+ uerr("ERROR: Bad TD completion status: %d\n", xfrinfo->tdstatus);
switch (xfrinfo->tdstatus)
{
@@ -3213,7 +3217,7 @@ static int lpc17_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep,
xfrinfo = lpc17_alloc_xfrinfo();
if (xfrinfo == NULL)
{
- udbg("ERROR: lpc17_alloc_xfrinfo failed\n");
+ uerr("ERROR: lpc17_alloc_xfrinfo failed\n");
ret = -ENOMEM;
goto errout_with_sem;
}
@@ -3234,7 +3238,7 @@ static int lpc17_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep,
ret = lpc17_dma_alloc(priv, ed, buffer, buflen, &xfrinfo->alloc);
if (ret < 0)
{
- udbg("ERROR: lpc17_dma_alloc failed: %d\n", ret);
+ uerr("ERROR: lpc17_dma_alloc failed: %d\n", ret);
goto errout_with_sem;
}
@@ -3251,7 +3255,7 @@ static int lpc17_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep,
ret = lpc17_transfer_common(priv, ed, buffer, buflen);
if (ret < 0)
{
- udbg("ERROR: lpc17_transfer_common failed: %d\n", ret);
+ uerr("ERROR: lpc17_transfer_common failed: %d\n", ret);
goto errout_with_asynch;
}
@@ -3454,7 +3458,7 @@ static int lpc17_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
- ullvdbg("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+ uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */
@@ -3695,19 +3699,19 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller)
lpc17_configgpio(GPIO_USB_OVRCR); /* USB port Over-Current status */
usbhost_dumpgpio();
- udbg("Initializing Host Stack\n");
+ uinfo("Initializing Host Stack\n");
/* Show AHB SRAM memory map */
#if 0 /* Useful if you have doubts about the layout */
- uvdbg("AHB SRAM:\n");
- uvdbg(" HCCA: %08x %d\n", LPC17_HCCA_BASE, LPC17_HCCA_SIZE);
- uvdbg(" TDTAIL: %08x %d\n", LPC17_TDTAIL_ADDR, LPC17_TD_SIZE);
- uvdbg(" EDCTRL: %08x %d\n", LPC17_EDCTRL_ADDR, LPC17_ED_SIZE);
- uvdbg(" EDFREE: %08x %d\n", LPC17_EDFREE_BASE, LPC17_ED_SIZE);
- uvdbg(" TDFREE: %08x %d\n", LPC17_TDFREE_BASE, LPC17_EDFREE_SIZE);
- uvdbg(" TBFREE: %08x %d\n", LPC17_TBFREE_BASE, LPC17_TBFREE_SIZE);
- uvdbg(" IOFREE: %08x %d\n", LPC17_IOFREE_BASE, LPC17_IOBUFFERS * CONFIG_USBHOST_IOBUFSIZE);
+ uinfo("AHB SRAM:\n");
+ uinfo(" HCCA: %08x %d\n", LPC17_HCCA_BASE, LPC17_HCCA_SIZE);
+ uinfo(" TDTAIL: %08x %d\n", LPC17_TDTAIL_ADDR, LPC17_TD_SIZE);
+ uinfo(" EDCTRL: %08x %d\n", LPC17_EDCTRL_ADDR, LPC17_ED_SIZE);
+ uinfo(" EDFREE: %08x %d\n", LPC17_EDFREE_BASE, LPC17_ED_SIZE);
+ uinfo(" TDFREE: %08x %d\n", LPC17_TDFREE_BASE, LPC17_EDFREE_SIZE);
+ uinfo(" TBFREE: %08x %d\n", LPC17_TBFREE_BASE, LPC17_TBFREE_SIZE);
+ uinfo(" IOFREE: %08x %d\n", LPC17_IOFREE_BASE, LPC17_IOBUFFERS * CONFIG_USBHOST_IOBUFSIZE);
#endif
/* Initialize all the TDs, EDs and HCCA to 0 */
@@ -3825,7 +3829,7 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller)
if (irq_attach(LPC17_IRQ_USB, lpc17_usbinterrupt) != 0)
{
- udbg("Failed to attach IRQ\n");
+ uerr("ERROR: Failed to attach IRQ\n");
return NULL;
}
@@ -3850,8 +3854,8 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller)
/* Enable interrupts at the interrupt controller */
up_enable_irq(LPC17_IRQ_USB); /* enable USB interrupt */
- udbg("USB host Initialized, Device connected:%s\n",
- priv->connected ? "YES" : "NO");
+ uinfo("USB host Initialized, Device connected:%s\n",
+ priv->connected ? "YES" : "NO");
return &g_usbconn;
}
diff --git a/arch/arm/src/lpc214x/Kconfig b/arch/arm/src/lpc214x/Kconfig
index 68926095cf0deb8d235805575f08c988e03c1c74..a9fc00c245e5beaa0baba9e763fbcf451da98d93 100644
--- a/arch/arm/src/lpc214x/Kconfig
+++ b/arch/arm/src/lpc214x/Kconfig
@@ -140,7 +140,7 @@ config LPC214X_USBDEV_FRAME_INTERRUPT
config LPC214X_USBDEV_REGDEBUG
bool "USB Device Register-Level Debug Output"
default n
- depends on DEBUG
+ depends on DEBUG_FEATURES
endmenu
endif
diff --git a/arch/arm/src/lpc214x/lpc214x_decodeirq.c b/arch/arm/src/lpc214x/lpc214x_decodeirq.c
index 382c0bba022a949b9b37ce894b4073f13d821580..331fea560ebcdf2e9434806fc8a4c86d1f1c3bf6 100644
--- a/arch/arm/src/lpc214x/lpc214x_decodeirq.c
+++ b/arch/arm/src/lpc214x/lpc214x_decodeirq.c
@@ -111,8 +111,8 @@ static void lpc214x_decodeirq(uint32_t *regs)
#endif
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
- lowsyslog(LOG_ERR, "Unexpected IRQ\n");
CURRENT_REGS = regs;
+ err("ERROR: Unexpected IRQ\n");
PANIC();
#else
diff --git a/arch/arm/src/lpc214x/lpc214x_head.S b/arch/arm/src/lpc214x/lpc214x_head.S
index 8db27f29ebde0131b6debe98baf61c91b2c28949..c0d6c7651005064685c3af454ee3866ac941e9d1 100644
--- a/arch/arm/src/lpc214x/lpc214x_head.S
+++ b/arch/arm/src/lpc214x/lpc214x_head.S
@@ -280,7 +280,7 @@
*/
.macro showprogress, code
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
mov r0, #\code
bl up_lowputc
#endif
diff --git a/arch/arm/src/lpc214x/lpc214x_serial.c b/arch/arm/src/lpc214x/lpc214x_serial.c
index 62b18ecfe35d4a89935de94b3c94922b961673a8..e1b3511f9ca45dfa2eef6f85718a832aba4d08ae 100644
--- a/arch/arm/src/lpc214x/lpc214x_serial.c
+++ b/arch/arm/src/lpc214x/lpc214x_serial.c
@@ -530,7 +530,7 @@ static int up_interrupt(int irq, void *context)
/* Read the modem status register (MSR) to clear */
status = up_serialin(priv, LPC214X_UART_MSR_OFFSET);
- vdbg("MSR: %02x\n", status);
+ _info("MSR: %02x\n", status);
break;
}
@@ -541,7 +541,7 @@ static int up_interrupt(int irq, void *context)
/* Read the line status register (LSR) to clear */
status = up_serialin(priv, LPC214X_UART_LSR_OFFSET);
- vdbg("LSR: %02x\n", status);
+ _info("LSR: %02x\n", status);
break;
}
@@ -549,7 +549,7 @@ static int up_interrupt(int irq, void *context)
default:
{
- dbg("Unexpected IIR: %02x\n", status);
+ _err("ERROR: Unexpected IIR: %02x\n", status);
break;
}
}
diff --git a/arch/arm/src/lpc214x/lpc214x_usbdev.c b/arch/arm/src/lpc214x/lpc214x_usbdev.c
index 5c058a6bc3b297353ab3cfd76311a76ca3ca6b98..636c7391251bb145d0e7a9a68e0e6410fafa8279 100644
--- a/arch/arm/src/lpc214x/lpc214x_usbdev.c
+++ b/arch/arm/src/lpc214x/lpc214x_usbdev.c
@@ -104,7 +104,7 @@
# define USB_FRAME_INT 0
#endif
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
# define USB_ERROR_INT USBDEV_DEVINT_EPRINT
#else
# define USB_ERROR_INT 0
@@ -382,7 +382,7 @@ struct lpc214x_usbdev_s
/* Register operations ********************************************************/
-#if defined(CONFIG_LPC214X_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_LPC214X_USBDEV_REGDEBUG
static uint32_t lpc214x_getreg(uint32_t addr);
static void lpc214x_putreg(uint32_t val, uint32_t addr);
#else
@@ -518,7 +518,7 @@ static const struct usbdev_ops_s g_devops =
*
****************************************************************************/
-#if defined(CONFIG_LPC214X_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_LPC214X_USBDEV_REGDEBUG
static uint32_t lpc214x_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@@ -539,7 +539,7 @@ static uint32_t lpc214x_getreg(uint32_t addr)
{
if (count == 4)
{
- lldbg("...\n");
+ uinfo("...\n");
}
return val;
@@ -556,7 +556,7 @@ static uint32_t lpc214x_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -568,7 +568,7 @@ static uint32_t lpc214x_getreg(uint32_t addr)
/* Show the register value read */
- lldbg("%08x->%08x\n", addr, val);
+ uinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@@ -581,12 +581,12 @@ static uint32_t lpc214x_getreg(uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_LPC214X_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_LPC214X_USBDEV_REGDEBUG
static void lpc214x_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- lldbg("%08x<-%08x\n", addr, val);
+ uinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@@ -1021,8 +1021,9 @@ static int lpc214x_wrrequest(struct lpc214x_ep_s *privep)
return OK;
}
- ullvdbg("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
- privep->epphy, privreq, privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
+ uinfo("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
+ privep->epphy, privreq, privreq->req.len, privreq->req.xfrd,
+ privep->txnullpkt);
/* Ignore any attempt to send a zero length packet on anything but EP0IN */
@@ -1130,8 +1131,8 @@ static int lpc214x_rdrequest(struct lpc214x_ep_s *privep)
return OK;
}
- ullvdbg("len=%d xfrd=%d nullpkt=%d\n",
- privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
+ uinfo("len=%d xfrd=%d nullpkt=%d\n",
+ privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
/* Ignore any attempt to receive a zero length packet */
@@ -1552,8 +1553,8 @@ static inline void lpc214x_ep0setup(struct lpc214x_usbdev_s *priv)
index = GETUINT16(ctrl.index);
len = GETUINT16(ctrl.len);
- ullvdbg("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- ctrl.type, ctrl.req, value, index, len);
+ uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ ctrl.type, ctrl.req, value, index, len);
/* Dispatch any non-standard requests */
@@ -1697,7 +1698,7 @@ static inline void lpc214x_ep0setup(struct lpc214x_usbdev_s *priv)
if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
value == USB_FEATURE_TESTMODE)
{
- ullvdbg("test mode: %d\n", index);
+ uinfo("test mode: %d\n", index);
}
else if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@@ -2055,7 +2056,7 @@ static int lpc214x_usbinterrupt(int irq, FAR void *context)
#endif
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
/* USB engine error interrupt */
if ((devintstatus & USBDEV_DEVINT_EPRINT))
@@ -2287,7 +2288,7 @@ static int lpc214x_usbinterrupt(int irq, FAR void *context)
}
else
{
- ullvdbg("Pending data on OUT endpoint\n");
+ uinfo("Pending data on OUT endpoint\n");
priv->rxpending = 1;
}
}
@@ -2378,7 +2379,7 @@ static int lpc214x_dmasetup(struct lpc214x_usbdev_s *priv, uint8_t epphy,
struct lpc214x_dmadesc_s *dmadesc = priv;
uint32_t reg;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!priv || epphy < 2)
{
usbtrace(TRACE_DEVERROR(LPC214X_TRACEERR_INVALIDPARMS), 0);
@@ -2577,7 +2578,7 @@ static int lpc214x_epdisable(FAR struct usbdev_ep_s *ep)
uint32_t mask = (1 << privep->epphy);
uint32_t reg;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep)
{
usbtrace(TRACE_DEVERROR(LPC214X_TRACEERR_INVALIDPARMS), 0);
@@ -2619,7 +2620,7 @@ static FAR struct usbdev_req_s *lpc214x_epallocreq(FAR struct usbdev_ep_s *ep)
{
FAR struct lpc214x_req_s *privreq;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep)
{
usbtrace(TRACE_DEVERROR(LPC214X_TRACEERR_INVALIDPARMS), 0);
@@ -2651,7 +2652,7 @@ static void lpc214x_epfreereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_
{
FAR struct lpc214x_req_s *privreq = (FAR struct lpc214x_req_s *)req;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(LPC214X_TRACEERR_INVALIDPARMS), 0);
@@ -2759,11 +2760,12 @@ static int lpc214x_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s
irqstate_t flags;
int ret = OK;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(LPC214X_TRACEERR_INVALIDPARMS), 0);
- ullvdbg("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+ uinfo("req=%p callback=%p buf=%p ep=%p\n",
+ req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
@@ -2844,7 +2846,7 @@ static int lpc214x_epcancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s
FAR struct lpc214x_ep_s *privep = (FAR struct lpc214x_ep_s *)ep;
irqstate_t flags;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(LPC214X_TRACEERR_INVALIDPARMS), 0);
@@ -3107,7 +3109,7 @@ static int lpc214x_selfpowered(struct usbdev_s *dev, bool selfpowered)
usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!dev)
{
usbtrace(TRACE_DEVERROR(LPC214X_TRACEERR_INVALIDPARMS), 0);
@@ -3322,7 +3324,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
usbtrace(TRACE_DEVREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!driver || !driver->ops->bind || !driver->ops->unbind ||
!driver->ops->disconnect || !driver->ops->setup)
{
@@ -3372,7 +3374,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
{
usbtrace(TRACE_DEVUNREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (driver != g_usbdev.driver)
{
usbtrace(TRACE_DEVERROR(LPC214X_TRACEERR_INVALIDPARMS), 0);
diff --git a/arch/arm/src/lpc2378/Kconfig b/arch/arm/src/lpc2378/Kconfig
index 08197970c66441ba32757d370888ef34abbf7406..eb9cba75701bf43af424c84e4c63e2ca32329783 100644
--- a/arch/arm/src/lpc2378/Kconfig
+++ b/arch/arm/src/lpc2378/Kconfig
@@ -185,7 +185,7 @@ config LPC2378_USBDEV_FRAME_INTERRUPT
config LPC2378_USBDEV_REGDEBUG
bool "USB Device Register-Level Debug Output"
default n
- depends on DEBUG
+ depends on DEBUG_FEATURES
endmenu
endif
diff --git a/arch/arm/src/lpc2378/lpc23xx_decodeirq.c b/arch/arm/src/lpc2378/lpc23xx_decodeirq.c
index aca536e6651cbfdc90d61faea9ef5ff466d99a69..9c0e0b5b76454b495414eede55a329769e396493 100644
--- a/arch/arm/src/lpc2378/lpc23xx_decodeirq.c
+++ b/arch/arm/src/lpc2378/lpc23xx_decodeirq.c
@@ -110,9 +110,9 @@ static void lpc23xx_decodeirq(uint32_t *regs)
#endif
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
- lowsyslog(LOG_ERR, "Unexpected IRQ\n");
- CURRENT_REGS = regs;
PANIC();
+ err("ERROR: Unexpected IRQ\n");
+ CURRENT_REGS = regs;
#else
/* Check which IRQ fires */
diff --git a/arch/arm/src/lpc2378/lpc23xx_head.S b/arch/arm/src/lpc2378/lpc23xx_head.S
index 179b390271c02226308150de9ae423983f223189..551f2d240e7275403bfeeb92b84c81f90bfe93ac 100644
--- a/arch/arm/src/lpc2378/lpc23xx_head.S
+++ b/arch/arm/src/lpc2378/lpc23xx_head.S
@@ -60,7 +60,7 @@
* modify r0, r1, r2 and r14
*/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
.macro showprogress, code
mov r0, #\code
bl up_lowputc
diff --git a/arch/arm/src/lpc2378/lpc23xx_i2c.c b/arch/arm/src/lpc2378/lpc23xx_i2c.c
index 54efbc52c00e04c480665578692c786d0a6521c5..1c281e8857411f5f2e356d5eb7801634c50fd617 100644
--- a/arch/arm/src/lpc2378/lpc23xx_i2c.c
+++ b/arch/arm/src/lpc2378/lpc23xx_i2c.c
@@ -490,7 +490,7 @@ struct i2c_master_s *lpc2378_i2cbus_initialize(int port)
if (port > 1)
{
- dbg("lpc I2C Only support 0,1\n");
+ l2cerr("ERROR: lpc I2C Only support 0,1\n");
return NULL;
}
diff --git a/arch/arm/src/lpc2378/lpc23xx_serial.c b/arch/arm/src/lpc2378/lpc23xx_serial.c
index 9650a0827a3b21f490a9977af901f9166cb090b4..48e322ec15adf7545c81b12abf4ca7c286c80d92 100644
--- a/arch/arm/src/lpc2378/lpc23xx_serial.c
+++ b/arch/arm/src/lpc2378/lpc23xx_serial.c
@@ -320,14 +320,14 @@ static inline void up_configbaud(struct up_dev_s *priv)
/* Test values calculated for every multiplier/divisor combination */
uint32_t tdiv;
- uint32_t terr;
+ uint32_t tmperr;
int tmulval;
int tdivaddval;
/* Optimal multiplier/divider values */
uint32_t div = 0;
- uint32_t err = 100000;
+ uint32_t errval = 100000;
int mulval = 1;
int divaddval = 0;
@@ -350,13 +350,13 @@ static inline void up_configbaud(struct up_dev_s *priv)
/* Try every valid multiplier, tmulval (or until a perfect match is found). */
- for (tmulval = 1; tmulval <= 15 && err > 0; tmulval++)
+ for (tmulval = 1; tmulval <= 15 && errval > 0; tmulval++)
{
/* Try every valid pre-scale div, tdivaddval (or until a perfect match is
* found).
*/
- for (tdivaddval = 0; tdivaddval <= 15 && err > 0; tdivaddval++)
+ for (tdivaddval = 0; tdivaddval <= 15 && errval > 0; tdivaddval++)
{
/* Calculate the divisor with these fractional divider settings */
@@ -373,16 +373,16 @@ static inline void up_configbaud(struct up_dev_s *priv)
if (actualbaud <= priv->baud)
{
- terr = priv->baud - actualbaud;
+ tmperr = priv->baud - actualbaud;
}
else
{
- terr = actualbaud - priv->baud;
+ tmperr = actualbaud - priv->baud;
}
/* Is this the smallest error we have encountered? */
- if (terr < err)
+ if (tmperr < errval)
{
/* Yes, save these settings as the new, candidate optimal
* settings
@@ -391,7 +391,7 @@ static inline void up_configbaud(struct up_dev_s *priv)
mulval = tmulval;
divaddval = tdivaddval;
div = tdiv;
- err = terr;
+ errval = tmperr;
}
}
}
@@ -648,7 +648,7 @@ static int up_interrupt(int irq, void *context)
/* Read the modem status register (MSR) to clear */
status = up_serialin(priv, UART_MSR_OFFSET);
- vdbg("MSR: %02x\n", status);
+ _info("MSR: %02x\n", status);
break;
}
@@ -659,7 +659,7 @@ static int up_interrupt(int irq, void *context)
/* Read the line status register (LSR) to clear */
status = up_serialin(priv, UART_LSR_OFFSET);
- vdbg("LSR: %02x\n", status);
+ _info("LSR: %02x\n", status);
break;
}
@@ -667,7 +667,7 @@ static int up_interrupt(int irq, void *context)
default:
{
- dbg("Unexpected IIR: %02x\n", status);
+ _err("ERROR: Unexpected IIR: %02x\n", status);
break;
}
}
diff --git a/arch/arm/src/lpc2378/lpc23xx_spi.c b/arch/arm/src/lpc2378/lpc23xx_spi.c
index 42c951c9540eafdca16df6aaef7c56be38da5ab6..cf95f63a8bcdbf4797864ce7d66b0c737160d41e 100644
--- a/arch/arm/src/lpc2378/lpc23xx_spi.c
+++ b/arch/arm/src/lpc2378/lpc23xx_spi.c
@@ -75,21 +75,6 @@
# error CONFIG_SPI_EXCHANGE is not supported by this driver
#endif
-/* Debug ********************************************************************/
-/* CONFIG_DEBUG_SPI enables debug output from this file */
-
-#ifdef CONFIG_DEBUG_SPI
-# define spidbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define spivdbg lldbg
-# else
-# define spivdbg(x...)
-# endif
-#else
-# define spidbg(x...)
-# define spivdbg(x...)
-#endif
-
/* SPI Clocking.
*
* The CPU clock is divided by by 1, 2, 4, or 8 to get the SPI peripheral
@@ -289,7 +274,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
priv->frequency = frequency;
priv->actual = actual;
- spidbg("Frequency %d->%d\n", frequency, actual);
+ spiinfo("Frequency %d->%d\n", frequency, actual);
return actual;
}
@@ -453,7 +438,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
FAR uint8_t *ptr = (FAR uint8_t *)buffer;
uint8_t data;
- spidbg("nwords: %d\n", nwords);
+ spiinfo("nwords: %d\n", nwords);
while (nwords)
{
/* Write the data to transmitted to the SPI Data Register */
@@ -498,7 +483,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
{
FAR uint8_t *ptr = (FAR uint8_t *)buffer;
- spidbg("nwords: %d\n", nwords);
+ spiinfo("nwords: %d\n", nwords);
while (nwords)
{
/* Write some dummy data to the SPI Data Register in order to clock the
diff --git a/arch/arm/src/lpc31xx/Kconfig b/arch/arm/src/lpc31xx/Kconfig
index ffdaa81146074f8e13b6a2ae858a5931459c397b..addeaf16e423c3ed1f96a91d02bda779c014078c 100644
--- a/arch/arm/src/lpc31xx/Kconfig
+++ b/arch/arm/src/lpc31xx/Kconfig
@@ -243,10 +243,11 @@ config LPC31_USBDEV_DMA
config LPC31_USBDEV_REGDEBUG
bool "Register level debug"
- depends on DEBUG
+ depends on DEBUG_USB_INFO
default n
---help---
- Output detailed register-level USB device debug information. Requires also DEBUG.
+ Output detailed register-level USB device debug information. Requires
+ also CONFIG_DEBUG_USB_INFO.
endmenu # USB device driver controller (DCD) options
endif # LPC31_USBOTG && USBDEV
@@ -300,7 +301,7 @@ config LPC31_EHCI_PREALLOCATE
config LPC31_EHCI_REGDEBUG
bool "Enable low-level EHCI register debug"
default n
- depends on DEBUG
+ depends on DEBUG_USB_INFO
endmenu # USB host controller driver (HCD) options
endif # LPC31_USBOTG && USBHOST
@@ -309,9 +310,9 @@ menu "SPI device driver options"
config LPC31_SPI_REGDEBUG
bool "SPI Register level debug"
- depends on LPC31_SPI && DEBUG
+ depends on LPC31_SPI && DEBUG_SPI_INFO
default n
---help---
- Output detailed register-level SPI device debug information. Requires also DEBUG.
+ Output detailed register-level SPI device debug information. Requires also CONFIG_DEBUG_SPI_INFO.
endmenu # SPI device driver options
diff --git a/arch/arm/src/lpc31xx/lpc31_decodeirq.c b/arch/arm/src/lpc31xx/lpc31_decodeirq.c
index 9cfcd3f44353ad25f65f716c4265b823d89e7134..a4f7a11628fa92fc452f77eec4e382c3148e2004 100644
--- a/arch/arm/src/lpc31xx/lpc31_decodeirq.c
+++ b/arch/arm/src/lpc31xx/lpc31_decodeirq.c
@@ -76,8 +76,8 @@
void up_decodeirq(uint32_t *regs)
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
- lowsyslog(LOG_ERR, "Unexpected IRQ\n");
CURRENT_REGS = regs;
+ err("ERROR: Unexpected IRQ\n");
PANIC();
#else
int index;
diff --git a/arch/arm/src/lpc31xx/lpc31_ehci.c b/arch/arm/src/lpc31xx/lpc31_ehci.c
index 67ef095f2d39e3ba0267c926646f284587319c97..e37abe4997f5e3302a668493760845cda9ab2dda 100644
--- a/arch/arm/src/lpc31xx/lpc31_ehci.c
+++ b/arch/arm/src/lpc31xx/lpc31_ehci.c
@@ -113,7 +113,7 @@
/* Debug options */
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_USB_INFO
# undef CONFIG_LPC31_EHCI_REGDEBUG
#endif
@@ -122,13 +122,6 @@
#undef CONFIG_USBHOST_ISOC_DISABLE
#define CONFIG_USBHOST_ISOC_DISABLE 1
-/* Simplify DEBUG checks */
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# undef CONFIG_DEBUG_USB
-#endif
-
/* Registers *******************************************************************/
/* Traditionally, NuttX specifies register locations using individual
* register offsets from a base address. That tradition is broken here and,
@@ -833,7 +826,7 @@ static uint32_t lpc31_swap32(uint32_t value)
static void lpc31_printreg(volatile uint32_t *regaddr, uint32_t regval,
bool iswrite)
{
- lldbg("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
+ uinfo("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
}
#endif
@@ -884,7 +877,7 @@ static void lpc31_checkreg(volatile uint32_t *regaddr, uint32_t regval, bool isw
{
/* No.. More than one. */
- lldbg("[repeats %d more times]\n", count);
+ uinfo("[repeats %d more times]\n", count);
}
}
@@ -1463,13 +1456,13 @@ static int lpc31_qh_flush(struct lpc31_qh_s *qh)
#ifdef CONFIG_LPC31_EHCI_REGDEBUG
static void lpc31_qtd_print(struct lpc31_qtd_s *qtd)
{
- udbg(" QTD[%p]:\n", qtd);
- udbg(" hw:\n");
- udbg(" nqp: %08x alt: %08x token: %08x\n",
- qtd->hw.nqp, qtd->hw.alt, qtd->hw.token);
- udbg(" bpl: %08x %08x %08x %08x %08x\n",
- qtd->hw.bpl[0], qtd->hw.bpl[1], qtd->hw.bpl[2],
- qtd->hw.bpl[3], qtd->hw.bpl[4]);
+ uinfo(" QTD[%p]:\n", qtd);
+ uinfo(" hw:\n");
+ uinfo(" nqp: %08x alt: %08x token: %08x\n",
+ qtd->hw.nqp, qtd->hw.alt, qtd->hw.token);
+ uinfo(" bpl: %08x %08x %08x %08x %08x\n",
+ qtd->hw.bpl[0], qtd->hw.bpl[1], qtd->hw.bpl[2],
+ qtd->hw.bpl[3], qtd->hw.bpl[4]);
}
#endif
@@ -1487,30 +1480,30 @@ static void lpc31_qh_print(struct lpc31_qh_s *qh)
struct lpc31_epinfo_s *epinfo;
struct ehci_overlay_s *overlay;
- udbg("QH[%p]:\n", qh);
- udbg(" hw:\n");
- udbg(" hlp: %08x epchar: %08x epcaps: %08x cqp: %08x\n",
- qh->hw.hlp, qh->hw.epchar, qh->hw.epcaps, qh->hw.cqp);
+ uinfo("QH[%p]:\n", qh);
+ uinfo(" hw:\n");
+ uinfo(" hlp: %08x epchar: %08x epcaps: %08x cqp: %08x\n",
+ qh->hw.hlp, qh->hw.epchar, qh->hw.epcaps, qh->hw.cqp);
overlay = &qh->hw.overlay;
- udbg(" overlay:\n");
- udbg(" nqp: %08x alt: %08x token: %08x\n",
- overlay->nqp, overlay->alt, overlay->token);
- udbg(" bpl: %08x %08x %08x %08x %08x\n",
- overlay->bpl[0], overlay->bpl[1], overlay->bpl[2],
- overlay->bpl[3], overlay->bpl[4]);
+ uinfo(" overlay:\n");
+ uinfo(" nqp: %08x alt: %08x token: %08x\n",
+ overlay->nqp, overlay->alt, overlay->token);
+ uinfo(" bpl: %08x %08x %08x %08x %08x\n",
+ overlay->bpl[0], overlay->bpl[1], overlay->bpl[2],
+ overlay->bpl[3], overlay->bpl[4]);
- udbg(" fqp:\n", qh->fqp);
+ uinfo(" fqp:\n", qh->fqp);
epinfo = qh->epinfo;
- udbg(" epinfo[%p]:\n", epinfo);
+ uinfo(" epinfo[%p]:\n", epinfo);
if (epinfo)
{
- udbg(" EP%d DIR=%s FA=%08x TYPE=%d MaxPacket=%d\n",
- epinfo->epno, epinfo->dirin ? "IN" : "OUT", epinfo->devaddr,
- epinfo->xfrtype, epinfo->maxpacket);
- udbg(" Toggle=%d iocwait=%d speed=%d result=%d\n",
- epinfo->toggle, epinfo->iocwait, epinfo->speed, epinfo->result);
+ uinfo(" EP%d DIR=%s FA=%08x TYPE=%d MaxPacket=%d\n",
+ epinfo->epno, epinfo->dirin ? "IN" : "OUT", epinfo->devaddr,
+ epinfo->xfrtype, epinfo->maxpacket);
+ uinfo(" Toggle=%d iocwait=%d speed=%d result=%d\n",
+ epinfo->toggle, epinfo->iocwait, epinfo->speed, epinfo->result);
}
}
#endif
@@ -2113,7 +2106,7 @@ static int lpc31_async_setup(struct lpc31_rhport_s *rhport,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_ASYNCXFR, epinfo->epno, buflen);
#else
- uvdbg("RHport%d EP%d: buffer=%p, buflen=%d, req=%p\n",
+ uinfo("RHport%d EP%d: buffer=%p, buflen=%d, req=%p\n",
RHPORT(rhport), epinfo->epno, buffer, buflen, req);
#endif
@@ -2391,7 +2384,7 @@ static int lpc31_intr_setup(struct lpc31_rhport_s *rhport,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_INTRXFR, epinfo->epno, buflen);
#else
- uvdbg("RHport%d EP%d: buffer=%p, buflen=%d\n",
+ uinfo("RHport%d EP%d: buffer=%p, buflen=%d\n",
RHPORT(rhport), epinfo->epno, buffer, buflen);
#endif
@@ -3377,7 +3370,7 @@ static int lpc31_ehci_interrupt(int irq, FAR void *context)
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace1(EHCI_VTRACE1_TOPHALF, usbsts & regval);
#else
- ullvdbg("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
+ uinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
#endif
/* Handle all unmasked interrupt sources */
@@ -3909,7 +3902,7 @@ static int lpc31_epalloc(FAR struct usbhost_driver_s *drvr,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_EPALLOC, epdesc->addr, epdesc->xfrtype);
#else
- uvdbg("EP%d DIR=%s FA=%08x TYPE=%d Interval=%d MaxPacket=%d\n",
+ uinfo("EP%d DIR=%s FA=%08x TYPE=%d Interval=%d MaxPacket=%d\n",
epdesc->addr, epdesc->in ? "IN" : "OUT", hport->funcaddr,
epdesc->xfrtype, epdesc->interval, epdesc->mxpacketsize);
#endif
@@ -4199,7 +4192,7 @@ static int lpc31_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_CTRLINOUT, RHPORT(rhport), req->req);
#else
- uvdbg("RHPort%d type: %02x req: %02x value: %02x%02x index: %02x%02x len: %04x\n",
+ uinfo("RHPort%d type: %02x req: %02x value: %02x%02x index: %02x%02x len: %04x\n",
RHPORT(rhport), req->type, req->req, req->value[1], req->value[0],
req->index[1], req->index[0], len);
#endif
@@ -4222,7 +4215,7 @@ static int lpc31_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
ret = lpc31_async_setup(rhport, ep0info, req, buffer, len);
if (ret < 0)
{
- udbg("ERROR: lpc31_async_setup failed: %d\n", ret);
+ uerr("ERROR: lpc31_async_setup failed: %d\n", ret);
goto errout_with_iocwait;
}
@@ -4687,7 +4680,7 @@ static int lpc31_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
- ullvdbg("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+ uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */
@@ -4887,7 +4880,7 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller)
{
FAR struct usbhost_hubport_s *hport;
uint32_t regval;
-#if defined(CONFIG_DEBUG_USB) && defined(CONFIG_DEBUG_VERBOSE)
+#if defined(CONFIG_DEBUG_USB) && defined(CONFIG_DEBUG_ASSERTIONS)
uint16_t regval16;
unsigned int nports;
#endif
@@ -5140,7 +5133,7 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller)
lpc31_putreg(EHCI_INT_ALLINTS, &HCOR->usbsts);
-#if defined(CONFIG_DEBUG_USB) && defined(CONFIG_DEBUG_VERBOSE)
+#if defined(CONFIG_DEBUG_USB) && defined(CONFIG_DEBUG_ASSERTIONS)
/* Show the EHCI version */
regval16 = lpc31_swap16(HCCR->hciversion);
diff --git a/arch/arm/src/lpc31xx/lpc31_lowputc.c b/arch/arm/src/lpc31xx/lpc31_lowputc.c
index 3e3213927f14b5c804598dc66bd9584febb54f27..7d1335fd5ad91605e993234f426c05fb00a656e7 100644
--- a/arch/arm/src/lpc31xx/lpc31_lowputc.c
+++ b/arch/arm/src/lpc31xx/lpc31_lowputc.c
@@ -144,14 +144,14 @@ static inline void up_configbaud(void)
/* Test values calculated for every multiplier/divisor combination */
uint32_t tdiv;
- uint32_t terr;
+ uint32_t tmperr;
int tmulval;
int tdivaddval;
/* Optimal multiplier/divider values */
uint32_t div = 0;
- uint32_t err = 100000;
+ uint32_t errval = 100000;
int mulval = 1;
int divaddval = 0;
@@ -176,13 +176,13 @@ static inline void up_configbaud(void)
* match is found).
*/
- for (tmulval = 1 ; tmulval <= 15 && err > 0; tmulval++)
+ for (tmulval = 1 ; tmulval <= 15 && errval > 0; tmulval++)
{
/* Try every valid pre-scale div, tdivaddval (or until a perfect
* match is found).
*/
- for (tdivaddval = 0 ; tdivaddval <= 15 && err > 0; tdivaddval++)
+ for (tdivaddval = 0 ; tdivaddval <= 15 && errval > 0; tdivaddval++)
{
/* Calculate the divisor with these fractional divider settings */
@@ -199,23 +199,23 @@ static inline void up_configbaud(void)
if (actualbaud <= CONFIG_UART_BAUD)
{
- terr = CONFIG_UART_BAUD - actualbaud;
+ tmperr = CONFIG_UART_BAUD - actualbaud;
}
else
{
- terr = actualbaud - CONFIG_UART_BAUD;
+ tmperr = actualbaud - CONFIG_UART_BAUD;
}
/* Is this the smallest error we have encountered? */
- if (terr < err)
+ if (tmperr < errval)
{
/* Yes, save these settings as the new, candidate optimal settings */
- mulval = tmulval ;
+ mulval = tmulval ;
divaddval = tdivaddval;
div = tdiv;
- err = terr;
+ errval = tmperr;
}
}
}
diff --git a/arch/arm/src/lpc31xx/lpc31_serial.c b/arch/arm/src/lpc31xx/lpc31_serial.c
index 6567ce267e15179d51e23a4e16265e876d27c61d..bf5ac8cd5869fc895fc8245e7290b621cec4a8ab 100644
--- a/arch/arm/src/lpc31xx/lpc31_serial.c
+++ b/arch/arm/src/lpc31xx/lpc31_serial.c
@@ -215,14 +215,14 @@ static inline void up_configbaud(void)
/* Test values calculated for every multiplier/divisor combination */
uint32_t tdiv;
- uint32_t terr;
+ uint32_t tmperr;
int tmulval;
int tdivaddval;
/* Optimal multiplier/divider values */
uint32_t div = 0;
- uint32_t err = 100000;
+ uint32_t errval = 100000;
int mulval = 1;
int divaddval = 0;
@@ -247,13 +247,13 @@ static inline void up_configbaud(void)
* match is found).
*/
- for (tmulval = 1 ; tmulval <= 15 && err > 0; tmulval++)
+ for (tmulval = 1 ; tmulval <= 15 && errval > 0; tmulval++)
{
/* Try every valid pre-scale div, tdivaddval (or until a perfect
* match is found).
*/
- for (tdivaddval = 0 ; tdivaddval <= 15 && err > 0; tdivaddval++)
+ for (tdivaddval = 0 ; tdivaddval <= 15 && errval > 0; tdivaddval++)
{
/* Calculate the divisor with these fractional divider settings */
@@ -270,23 +270,23 @@ static inline void up_configbaud(void)
if (actualbaud <= CONFIG_UART_BAUD)
{
- terr = CONFIG_UART_BAUD - actualbaud;
+ tmperr = CONFIG_UART_BAUD - actualbaud;
}
else
{
- terr = actualbaud - CONFIG_UART_BAUD;
+ tmperr = actualbaud - CONFIG_UART_BAUD;
}
/* Is this the smallest error we have encountered? */
- if (terr < err)
+ if (tmperr < errval)
{
/* Yes, save these settings as the new, candidate optimal settings */
- mulval = tmulval ;
+ mulval = tmulval ;
divaddval = tdivaddval;
div = tdiv;
- err = terr;
+ errval = tmperr;
}
}
}
@@ -541,7 +541,7 @@ static int up_interrupt(int irq, void *context)
/* Read the modem status register (MSR) to clear */
status = getreg32(LPC31_UART_MSR);
- fvdbg("MSR: %02x\n", status);
+ finfo("MSR: %02x\n", status);
break;
}
@@ -552,7 +552,7 @@ static int up_interrupt(int irq, void *context)
/* Read the line status register (LSR) to clear */
status = getreg32(LPC31_UART_LSR);
- fvdbg("LSR: %02x\n", status);
+ finfo("LSR: %02x\n", status);
break;
}
@@ -560,7 +560,7 @@ static int up_interrupt(int irq, void *context)
default:
{
- dbg("Unexpected IIR: %02x\n", status);
+ _err("ERROR: Unexpected IIR: %02x\n", status);
break;
}
}
diff --git a/arch/arm/src/lpc31xx/lpc31_spi.c b/arch/arm/src/lpc31xx/lpc31_spi.c
index f750ca0792db960e6025838e5975bacabfb70076..ca2544bc2654d65966bf372cdb66992fdd0bd178 100644
--- a/arch/arm/src/lpc31xx/lpc31_spi.c
+++ b/arch/arm/src/lpc31xx/lpc31_spi.c
@@ -63,10 +63,10 @@
/* Debug ****************************************************************************/
/* CONFIG_LPC31_SPI_REGDEBUG enabled very low, register-level debug output.
- * CONFIG_DEBUG must also be defined
+ * CONFIG_DEBUG_FEATURES must also be defined
*/
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_SPI_INFO
# undef CONFIG_LPC31_SPI_REGDEBUG
#endif
@@ -207,7 +207,7 @@ static bool spi_checkreg(bool wr, uint32_t value, uint32_t address)
{
if (g_ntimes > 0)
{
- lldbg("...[Repeats %d times]...\n", g_ntimes);
+ spiinfo("...[Repeats %d times]...\n", g_ntimes);
}
g_wrlast = wr;
@@ -239,7 +239,7 @@ static void spi_putreg(uint32_t value, uint32_t address)
{
if (spi_checkreg(true, value, address))
{
- lldbg("%08x<-%08x\n", address, value);
+ spiinfo("%08x<-%08x\n", address, value);
}
putreg32(value, address);
}
@@ -265,7 +265,7 @@ static uint32_t spi_getreg(uint32_t address)
uint32_t value = getreg32(address);
if (spi_checkreg(false, value, address))
{
- lldbg("%08x->%08x\n", address, value);
+ spiinfo("%08x->%08x\n", address, value);
}
return value;
}
@@ -921,10 +921,10 @@ FAR struct spi_dev_s *lpc31_spibus_initialize(int port)
*/
#ifdef CONFIG_LPC31_SPI_REGDEBUG
- lldbg("PINS: %08x MODE0: %08x MODE1: %08x\n",
- spi_getreg(LPC31_IOCONFIG_SPI_PINS),
- spi_getreg(LPC31_IOCONFIG_SPI_MODE0),
- spi_getreg(LPC31_IOCONFIG_SPI_MODE1));
+ spiinfo("PINS: %08x MODE0: %08x MODE1: %08x\n",
+ spi_getreg(LPC31_IOCONFIG_SPI_PINS),
+ spi_getreg(LPC31_IOCONFIG_SPI_MODE0),
+ spi_getreg(LPC31_IOCONFIG_SPI_MODE1));
#endif
/* Enable SPI clocks */
diff --git a/arch/arm/src/lpc31xx/lpc31_usbdev.c b/arch/arm/src/lpc31xx/lpc31_usbdev.c
index c1ece00bf6f37f36e4293690ca5bfcb640f5d61e..1cc9ec0d38b146be0ac6d260a63aa0b8257bdc8e 100644
--- a/arch/arm/src/lpc31xx/lpc31_usbdev.c
+++ b/arch/arm/src/lpc31xx/lpc31_usbdev.c
@@ -100,7 +100,7 @@
# define USB_FRAME_INT 0
#endif
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
# define USB_ERROR_INT USBDEV_USBINTR_UEE
#else
# define USB_ERROR_INT 0
@@ -343,7 +343,7 @@ struct lpc31_usbdev_s
/* Register operations ********************************************************/
-#if defined(CONFIG_LPC31_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_LPC31_USBDEV_REGDEBUG
static uint32_t lpc31_getreg(uint32_t addr);
static void lpc31_putreg(uint32_t val, uint32_t addr);
#else
@@ -480,7 +480,7 @@ static const struct usbdev_ops_s g_devops =
*
****************************************************************************/
-#if defined(CONFIG_LPC31_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_LPC31_USBDEV_REGDEBUG
static uint32_t lpc31_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@@ -501,7 +501,7 @@ static uint32_t lpc31_getreg(uint32_t addr)
{
if (count == 4)
{
- lldbg("...\n");
+ uinfo("...\n");
}
return val;
@@ -518,7 +518,7 @@ static uint32_t lpc31_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -530,7 +530,7 @@ static uint32_t lpc31_getreg(uint32_t addr)
/* Show the register value read */
- lldbg("%08x->%08x\n", addr, val);
+ uinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@@ -543,12 +543,12 @@ static uint32_t lpc31_getreg(uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_LPC31_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_LPC31_USBDEV_REGDEBUG
static void lpc31_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- lldbg("%08x<-%08x\n", addr, val);
+ uinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@@ -1183,8 +1183,8 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv)
index = GETUINT16(ctrl.index);
len = GETUINT16(ctrl.len);
- ullvdbg("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- ctrl.type, ctrl.req, value, index, len);
+ uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ ctrl.type, ctrl.req, value, index, len);
/* Dispatch any non-standard requests */
if ((ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD)
@@ -1323,7 +1323,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv)
if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
value == USB_FEATURE_TESTMODE)
{
- ullvdbg("test mode: %d\n", index);
+ uinfo("test mode: %d\n", index);
}
else if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@@ -1536,7 +1536,7 @@ static void lpc31_ep0complete(struct lpc31_usbdev_s *priv, uint8_t epphy)
break;
default:
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
DEBUGASSERT(priv->ep0state != EP0STATE_DATA_IN &&
priv->ep0state != EP0STATE_DATA_OUT &&
priv->ep0state != EP0STATE_SHORTWRITE &&
@@ -1578,7 +1578,7 @@ static void lpc31_ep0nak(struct lpc31_usbdev_s *priv, uint8_t epphy)
lpc31_ep0state (priv, EP0STATE_WAIT_STATUS_OUT);
break;
default:
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
DEBUGASSERT(priv->ep0state != EP0STATE_WAIT_NAK_IN &&
priv->ep0state != EP0STATE_WAIT_NAK_OUT);
#endif
@@ -1939,7 +1939,7 @@ static int lpc31_epdisable(FAR struct usbdev_ep_s *ep)
FAR struct lpc31_ep_s *privep = (FAR struct lpc31_ep_s *)ep;
irqstate_t flags;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep)
{
usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_INVALIDPARMS), 0);
@@ -1977,7 +1977,7 @@ static FAR struct usbdev_req_s *lpc31_epallocreq(FAR struct usbdev_ep_s *ep)
{
FAR struct lpc31_req_s *privreq;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep)
{
usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_INVALIDPARMS), 0);
@@ -2009,7 +2009,7 @@ static void lpc31_epfreereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s
{
FAR struct lpc31_req_s *privreq = (FAR struct lpc31_req_s *)req;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_INVALIDPARMS), 0);
@@ -2079,11 +2079,11 @@ static int lpc31_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
irqstate_t flags;
int ret = OK;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_INVALIDPARMS), 0);
- ullvdbg("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+ uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
@@ -2144,7 +2144,7 @@ static int lpc31_epcancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
FAR struct lpc31_ep_s *privep = (FAR struct lpc31_ep_s *)ep;
irqstate_t flags;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_INVALIDPARMS), 0);
@@ -2423,7 +2423,7 @@ static int lpc31_selfpowered(struct usbdev_s *dev, bool selfpowered)
usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!dev)
{
usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_INVALIDPARMS), 0);
@@ -2655,7 +2655,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
usbtrace(TRACE_DEVREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!driver || !driver->ops->bind || !driver->ops->unbind ||
!driver->ops->disconnect || !driver->ops->setup)
{
@@ -2716,7 +2716,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
{
usbtrace(TRACE_DEVUNREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (driver != g_usbdev.driver)
{
usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_INVALIDPARMS), 0);
diff --git a/arch/arm/src/lpc43xx/Kconfig b/arch/arm/src/lpc43xx/Kconfig
index 5b7d730151e58a4a9065a7a03a0edd4664c4e5ac..e7f830ed2ba5157cebaab467868cfd77e34d7874 100644
--- a/arch/arm/src/lpc43xx/Kconfig
+++ b/arch/arm/src/lpc43xx/Kconfig
@@ -314,6 +314,12 @@ config LPC43_WWDT
endmenu # LPC43xx Peripheral Support
+config LPC43_GPIO_IRQ
+ bool "GPIO interrupt support"
+ default n
+ ---help---
+ Enable support for GPIO interrupts
+
if LPC43_ETHERNET
menu "Ethernet MAC configuration"
@@ -451,9 +457,9 @@ config LPC43_RMII
config LPC43_ETHERNET_REGDEBUG
bool "Register-Level Debug"
default n
- depends on DEBUG
+ depends on DEBUG_NET_INFO
---help---
- Enable very low-level register access debug. Depends on DEBUG.
+ Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_INFO.
endmenu # Ethernet MAC configuration
endif # LPC43_ETHERNET
diff --git a/arch/arm/src/lpc43xx/Make.defs b/arch/arm/src/lpc43xx/Make.defs
index 018b929d4d42044b823d084fc37cc14c2a8a5609..6e5d7ef3a789e822e5243a1608208cb3bb9e5d74 100644
--- a/arch/arm/src/lpc43xx/Make.defs
+++ b/arch/arm/src/lpc43xx/Make.defs
@@ -110,7 +110,7 @@ ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += lpc43_idle.c
endif
-ifeq ($(CONFIG_DEBUG),y)
+ifeq ($(CONFIG_DEBUG_FEATURES),y)
CHIP_CSRCS += lpc43_debug.c
endif
@@ -118,7 +118,7 @@ ifeq ($(CONFIG_LPC43_GPDMA),y)
CHIP_CSRCS += lpc43_gpdma.c
endif
-ifeq ($(CONFIG_GPIO_IRQ),y)
+ifeq ($(CONFIG_LPC43_GPIO_IRQ),y)
CHIP_CSRCS += lpc43_gpioint.c
endif
diff --git a/arch/arm/src/lpc43xx/lpc43_dac.c b/arch/arm/src/lpc43xx/lpc43_dac.c
index 16fa92a36547167452602bb8142ac73d9a7cb2c5..51b7000def9c1df808a41d6bca37f802cf7c0634 100644
--- a/arch/arm/src/lpc43xx/lpc43_dac.c
+++ b/arch/arm/src/lpc43xx/lpc43_dac.c
@@ -173,7 +173,7 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg)
{
- dbg("Fix me:Not Implemented\n");
+ aerr("ERROR: Fix me:Not Implemented\n");
return 0;
}
diff --git a/arch/arm/src/lpc43xx/lpc43_debug.c b/arch/arm/src/lpc43xx/lpc43_debug.c
index 51cf9470672601f15904c445e435afdcbd7c058a..3b20bc63e74116d6d44f7fbb99003b4093b4d132 100644
--- a/arch/arm/src/lpc43xx/lpc43_debug.c
+++ b/arch/arm/src/lpc43xx/lpc43_debug.c
@@ -47,23 +47,12 @@
#include "lpc43_pinconfig.h"
#include "lpc43_gpio.h"
-#ifdef CONFIG_DEBUG
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
+#ifdef CONFIG_DEBUG_FEATURES
/****************************************************************************
* Public Functions
****************************************************************************/
+
/****************************************************************************
* Function: lpc43_pin_dump
*
@@ -93,4 +82,4 @@ int lpc43_gpio_dump(uint16_t gpiocfg, const char *msg)
return -ENOSYS;
}
-#endif /* CONFIG_DEBUG */
+#endif /* CONFIG_DEBUG_FEATURES */
diff --git a/arch/arm/src/lpc43xx/lpc43_ehci.c b/arch/arm/src/lpc43xx/lpc43_ehci.c
index 08b2ae8e0f99344819224fcb2735b9bb03d59f40..ae462f80b46ac883fd62c21f1978a3eb2dba1d09 100644
--- a/arch/arm/src/lpc43xx/lpc43_ehci.c
+++ b/arch/arm/src/lpc43xx/lpc43_ehci.c
@@ -105,7 +105,7 @@
/* Debug options */
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_USB_INFO
# undef CONFIG_LPC43_EHCI_REGDEBUG
#endif
@@ -116,8 +116,8 @@
/* Simplify DEBUG checks */
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
+#ifndef CONFIG_DEBUG_FEATURES
+# undef CONFIG_DEBUG_INFO
# undef CONFIG_DEBUG_USB
#endif
@@ -817,7 +817,7 @@ static uint32_t lpc43_swap32(uint32_t value)
static void lpc43_printreg(volatile uint32_t *regaddr, uint32_t regval,
bool iswrite)
{
- lldbg("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
+ uinfo("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
}
#endif
@@ -868,7 +868,7 @@ static void lpc43_checkreg(volatile uint32_t *regaddr, uint32_t regval, bool isw
{
/* No.. More than one. */
- lldbg("[repeats %d more times]\n", count);
+ uinfo("[repeats %d more times]\n", count);
}
}
@@ -1350,13 +1350,13 @@ static int lpc43_qh_discard(struct lpc43_qh_s *qh)
#ifdef CONFIG_LPC43_EHCI_REGDEBUG
static void lpc43_qtd_print(struct lpc43_qtd_s *qtd)
{
- udbg(" QTD[%p]:\n", qtd);
- udbg(" hw:\n");
- udbg(" nqp: %08x alt: %08x token: %08x\n",
- qtd->hw.nqp, qtd->hw.alt, qtd->hw.token);
- udbg(" bpl: %08x %08x %08x %08x %08x\n",
- qtd->hw.bpl[0], qtd->hw.bpl[1], qtd->hw.bpl[2],
- qtd->hw.bpl[3], qtd->hw.bpl[4]);
+ uinfo(" QTD[%p]:\n", qtd);
+ uinfo(" hw:\n");
+ uinfo(" nqp: %08x alt: %08x token: %08x\n",
+ qtd->hw.nqp, qtd->hw.alt, qtd->hw.token);
+ uinfo(" bpl: %08x %08x %08x %08x %08x\n",
+ qtd->hw.bpl[0], qtd->hw.bpl[1], qtd->hw.bpl[2],
+ qtd->hw.bpl[3], qtd->hw.bpl[4]);
}
#endif
@@ -1374,30 +1374,30 @@ static void lpc43_qh_print(struct lpc43_qh_s *qh)
struct lpc43_epinfo_s *epinfo;
struct ehci_overlay_s *overlay;
- udbg("QH[%p]:\n", qh);
- udbg(" hw:\n");
- udbg(" hlp: %08x epchar: %08x epcaps: %08x cqp: %08x\n",
- qh->hw.hlp, qh->hw.epchar, qh->hw.epcaps, qh->hw.cqp);
+ uinfo("QH[%p]:\n", qh);
+ uinfo(" hw:\n");
+ uinfo(" hlp: %08x epchar: %08x epcaps: %08x cqp: %08x\n",
+ qh->hw.hlp, qh->hw.epchar, qh->hw.epcaps, qh->hw.cqp);
overlay = &qh->hw.overlay;
- udbg(" overlay:\n");
- udbg(" nqp: %08x alt: %08x token: %08x\n",
- overlay->nqp, overlay->alt, overlay->token);
- udbg(" bpl: %08x %08x %08x %08x %08x\n",
- overlay->bpl[0], overlay->bpl[1], overlay->bpl[2],
- overlay->bpl[3], overlay->bpl[4]);
+ uinfo(" overlay:\n");
+ uinfo(" nqp: %08x alt: %08x token: %08x\n",
+ overlay->nqp, overlay->alt, overlay->token);
+ uinfo(" bpl: %08x %08x %08x %08x %08x\n",
+ overlay->bpl[0], overlay->bpl[1], overlay->bpl[2],
+ overlay->bpl[3], overlay->bpl[4]);
- udbg(" fqp:\n", qh->fqp);
+ uinfo(" fqp:\n", qh->fqp);
epinfo = qh->epinfo;
- udbg(" epinfo[%p]:\n", epinfo);
+ uinfo(" epinfo[%p]:\n", epinfo);
if (epinfo)
{
- udbg(" EP%d DIR=%s FA=%08x TYPE=%d MaxPacket=%d\n",
- epinfo->epno, epinfo->dirin ? "IN" : "OUT", epinfo->devaddr,
- epinfo->xfrtype, epinfo->maxpacket);
- udbg(" Toggle=%d iocwait=%d speed=%d result=%d\n",
- epinfo->toggle, epinfo->iocwait, epinfo->speed, epinfo->result);
+ uinfo(" EP%d DIR=%s FA=%08x TYPE=%d MaxPacket=%d\n",
+ epinfo->epno, epinfo->dirin ? "IN" : "OUT", epinfo->devaddr,
+ epinfo->xfrtype, epinfo->maxpacket);
+ uinfo(" Toggle=%d iocwait=%d speed=%d result=%d\n",
+ epinfo->toggle, epinfo->iocwait, epinfo->speed, epinfo->result);
}
}
#endif
@@ -1989,7 +1989,7 @@ static int lpc43_async_setup(struct lpc43_rhport_s *rhport,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_ASYNCXFR, epinfo->epno, buflen);
#else
- uvdbg("RHport%d EP%d: buffer=%p, buflen=%d, req=%p\n",
+ uinfo("RHport%d EP%d: buffer=%p, buflen=%d, req=%p\n",
RHPORT(rhport), epinfo->epno, buffer, buflen, req);
#endif
@@ -2267,7 +2267,7 @@ static int lpc43_intr_setup(struct lpc43_rhport_s *rhport,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_INTRXFR, epinfo->epno, buflen);
#else
- uvdbg("RHport%d EP%d: buffer=%p, buflen=%d\n",
+ uinfo("RHport%d EP%d: buffer=%p, buflen=%d\n",
RHPORT(rhport), epinfo->epno, buffer, buflen);
#endif
@@ -3207,7 +3207,7 @@ static int lpc43_ehci_interrupt(int irq, FAR void *context)
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace1(EHCI_VTRACE1_TOPHALF, usbsts & regval);
#else
- ullvdbg("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
+ uinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
#endif
/* Handle all unmasked interrupt sources */
@@ -3739,7 +3739,7 @@ static int lpc43_epalloc(FAR struct usbhost_driver_s *drvr,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_EPALLOC, epdesc->addr, epdesc->xfrtype);
#else
- uvdbg("EP%d DIR=%s FA=%08x TYPE=%d Interval=%d MaxPacket=%d\n",
+ uinfo("EP%d DIR=%s FA=%08x TYPE=%d Interval=%d MaxPacket=%d\n",
epdesc->addr, epdesc->in ? "IN" : "OUT", hport->funcaddr,
epdesc->xfrtype, epdesc->interval, epdesc->mxpacketsize);
#endif
@@ -4023,7 +4023,7 @@ static int lpc43_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_CTRLINOUT, RHPORT(rhport), req->req);
#else
- uvdbg("RHPort%d type: %02x req: %02x value: %02x%02x index: %02x%02x len: %04x\n",
+ uinfo("RHPort%d type: %02x req: %02x value: %02x%02x index: %02x%02x len: %04x\n",
RHPORT(rhport), req->type, req->req, req->value[1], req->value[0],
req->index[1], req->index[0], len);
#endif
@@ -4046,7 +4046,7 @@ static int lpc43_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
ret = lpc43_async_setup(rhport, ep0info, req, buffer, len);
if (ret < 0)
{
- udbg("ERROR: lpc43_async_setup failed: %d\n", ret);
+ uerr("ERROR: lpc43_async_setup failed: %d\n", ret);
goto errout_with_iocwait;
}
@@ -4511,7 +4511,7 @@ static int lpc43_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
- ullvdbg("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+ uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */
@@ -4711,7 +4711,7 @@ FAR struct usbhost_connection_s *lpc43_ehci_initialize(int controller)
{
FAR struct usbhost_hubport_s *hport;
uint32_t regval;
-#if defined(CONFIG_DEBUG_USB) && defined(CONFIG_DEBUG_VERBOSE)
+#if defined(CONFIG_DEBUG_USB) && defined(CONFIG_DEBUG_INFO)
uint16_t regval16;
unsigned int nports;
#endif
@@ -4948,7 +4948,7 @@ FAR struct usbhost_connection_s *lpc43_ehci_initialize(int controller)
lpc43_putreg(EHCI_INT_ALLINTS, &HCOR->usbsts);
-#if defined(CONFIG_DEBUG_USB) && defined(CONFIG_DEBUG_VERBOSE)
+#if defined(CONFIG_DEBUG_USB) && defined(CONFIG_DEBUG_INFO)
/* Show the EHCI version */
regval16 = lpc43_swap16(HCCR->hciversion);
diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c
index 733a161c2be0c620fb2c8a6a978313a78deae50c..086dd0b8f3eb54f44359d0323b82e6506e2756a9 100644
--- a/arch/arm/src/lpc43xx/lpc43_ethernet.c
+++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c
@@ -197,7 +197,7 @@
* enabled.
*/
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_NET_INFO
# undef CONFIG_LPC43_ETHMAC_REGDEBUG
#endif
@@ -522,9 +522,9 @@ struct lpc43_ethmac_s
struct work_s work; /* For deferring work to the work queue */
#endif
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
/* Used to track transmit and receive descriptors */
@@ -559,7 +559,7 @@ static struct lpc43_ethmac_s g_lpc43ethmac;
****************************************************************************/
/* Register operations ******************************************************/
-#if defined(CONFIG_LPC43_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_LPC43_ETHMAC_REGDEBUG
static uint32_t lpc43_getreg(uint32_t addr);
static void lpc43_putreg(uint32_t val, uint32_t addr);
static void lpc43_checksetup(void);
@@ -683,7 +683,7 @@ static int lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv);
*
****************************************************************************/
-#if defined(CONFIG_LPC43_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_LPC43_ETHMAC_REGDEBUG
static uint32_t lpc43_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@@ -704,7 +704,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
{
if (count == 4)
{
- lldbg("...\n");
+ ninfo("...\n");
}
return val;
@@ -721,7 +721,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ ninfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -733,7 +733,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
/* Show the register value read */
- lldbg("%08x->%08x\n", addr, val);
+ ninfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@@ -755,12 +755,12 @@ static uint32_t lpc43_getreg(uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_LPC43_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_LPC43_ETHMAC_REGDEBUG
static void lpc43_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- lldbg("%08x<-%08x\n", addr, val);
+ ninfo("%08x<-%08x\n", addr, val);
/* Write the value */
@@ -782,7 +782,7 @@ static void lpc43_putreg(uint32_t val, uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_LPC43_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_LPC43_ETHMAC_REGDEBUG
static void lpc43_checksetup(void)
{
}
@@ -928,7 +928,7 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
struct eth_txdesc_s *txdesc;
struct eth_txdesc_s *txfirst;
- /* The internal (optimal) uIP buffer size may be configured to be larger
+ /* The internal (optimal) network buffer size may be configured to be larger
* than the Ethernet buffer size.
*/
@@ -947,8 +947,8 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
txdesc = priv->txhead;
txfirst = txdesc;
- nllvdbg("d_len: %d d_buf: %p txhead: %p tdes0: %08x\n",
- priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0);
+ ninfo("d_len: %d d_buf: %p txhead: %p tdes0: %08x\n",
+ priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0);
DEBUGASSERT(txdesc && (txdesc->tdes0 & ETH_TDES0_OWN) == 0);
@@ -964,7 +964,7 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
bufcount = (priv->dev.d_len + (CONFIG_LPC43_ETH_BUFSIZE-1)) / CONFIG_LPC43_ETH_BUFSIZE;
lastsize = priv->dev.d_len - (bufcount - 1) * CONFIG_LPC43_ETH_BUFSIZE;
- nllvdbg("bufcount: %d lastsize: %d\n", bufcount, lastsize);
+ ninfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
/* Set the first segment bit in the first TX descriptor */
@@ -1074,8 +1074,8 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
priv->inflight++;
- nllvdbg("txhead: %p txtail: %p inflight: %d\n",
- priv->txhead, priv->txtail, priv->inflight);
+ ninfo("txhead: %p txtail: %p inflight: %d\n",
+ priv->txhead, priv->txtail, priv->inflight);
/* If all TX descriptors are in-flight, then we have to disable receive interrupts
* too. This is because receive events can trigger more un-stoppable transmit
@@ -1114,7 +1114,7 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
* Function: lpc43_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -1373,7 +1373,7 @@ static void lpc43_freesegment(FAR struct lpc43_ethmac_s *priv,
struct eth_rxdesc_s *rxdesc;
int i;
- nllvdbg("rxfirst: %p segments: %d\n", rxfirst, segments);
+ ninfo("rxfirst: %p segments: %d\n", rxfirst, segments);
/* Set OWN bit in RX descriptors. This gives the buffers back to DMA */
@@ -1431,8 +1431,8 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
uint8_t *buffer;
int i;
- nllvdbg("rxhead: %p rxcurr: %p segments: %d\n",
- priv->rxhead, priv->rxcurr, priv->segments);
+ ninfo("rxhead: %p rxcurr: %p segments: %d\n",
+ priv->rxhead, priv->rxcurr, priv->segments);
/* Check if there are free buffers. We cannot receive new frames in this
* design unless there is at least one free buffer.
@@ -1440,7 +1440,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
if (!lpc43_isfreebuffer(priv))
{
- nlldbg("No free buffers\n");
+ nerr("ERROR: No free buffers\n");
return -ENOMEM;
}
@@ -1497,7 +1497,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
rxcurr = priv->rxcurr;
}
- nllvdbg("rxhead: %p rxcurr: %p segments: %d\n",
+ ninfo("rxhead: %p rxcurr: %p segments: %d\n",
priv->rxhead, priv->rxcurr, priv->segments);
/* Check if any errors are reported in the frame */
@@ -1520,7 +1520,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
buffer = lpc43_allocbuffer(priv);
/* Take the buffer from the RX descriptor of the first free
- * segment, put it into the uIP device structure, then replace
+ * segment, put it into the network device structure, then replace
* the buffer in the RX descriptor with the newly allocated
* buffer.
*/
@@ -1536,8 +1536,8 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
priv->rxhead = (struct eth_rxdesc_s *)rxdesc->rdes3;
lpc43_freesegment(priv, rxcurr, priv->segments);
- nllvdbg("rxhead: %p d_buf: %p d_len: %d\n",
- priv->rxhead, dev->d_buf, dev->d_len);
+ ninfo("rxhead: %p d_buf: %p d_len: %d\n",
+ priv->rxhead, dev->d_buf, dev->d_len);
return OK;
}
@@ -1547,7 +1547,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
* scanning logic, and continue scanning with the next frame.
*/
- nlldbg("DROPPED: RX descriptor errors: %08x\n", rxdesc->rdes0);
+ nwarn("WARNING: Dropped, RX descriptor errors: %08x\n", rxdesc->rdes0);
lpc43_freesegment(priv, rxcurr, priv->segments);
}
}
@@ -1563,8 +1563,8 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
priv->rxhead = rxdesc;
- nllvdbg("rxhead: %p rxcurr: %p segments: %d\n",
- priv->rxhead, priv->rxcurr, priv->segments);
+ ninfo("rxhead: %p rxcurr: %p segments: %d\n",
+ priv->rxhead, priv->rxcurr, priv->segments);
return -EAGAIN;
}
@@ -1602,13 +1602,13 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
pkt_input(&priv->dev);
#endif
- /* Check if the packet is a valid size for the uIP buffer configuration
+ /* Check if the packet is a valid size for the network buffer configuration
* (this should not happen)
*/
if (dev->d_len > CONFIG_NET_ETH_MTU)
{
- nlldbg("DROPPED: Too big: %d\n", dev->d_len);
+ nwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
/* Free dropped packet buffer */
if (dev->d_buf)
@@ -1632,7 +1632,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
- nllvdbg("IPv4 frame\n");
+ ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@@ -1672,7 +1672,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
- nllvdbg("Iv6 frame\n");
+ ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@@ -1709,7 +1709,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
- nllvdbg("ARP frame\n");
+ ninfo("ARP frame\n");
/* Handle ARP packet */
@@ -1727,7 +1727,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
else
#endif
{
- nlldbg("DROPPED: Unknown type: %04x\n", BUF->type);
+ nwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
}
/* We are finished with the RX buffer. NOTE: If the buffer is
@@ -1768,8 +1768,8 @@ static void lpc43_freeframe(FAR struct lpc43_ethmac_s *priv)
struct eth_txdesc_s *txdesc;
int i;
- nllvdbg("txhead: %p txtail: %p inflight: %d\n",
- priv->txhead, priv->txtail, priv->inflight);
+ ninfo("txhead: %p txtail: %p inflight: %d\n",
+ priv->txhead, priv->txtail, priv->inflight);
/* Scan for "in-flight" descriptors owned by the CPU */
@@ -1784,8 +1784,8 @@ static void lpc43_freeframe(FAR struct lpc43_ethmac_s *priv)
* TX descriptors.
*/
- nllvdbg("txtail: %p tdes0: %08x tdes2: %08x tdes3: %08x\n",
- txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3);
+ ninfo("txtail: %p tdes0: %08x tdes2: %08x tdes3: %08x\n",
+ txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3);
DEBUGASSERT(txdesc->tdes2 != 0);
@@ -1837,8 +1837,8 @@ static void lpc43_freeframe(FAR struct lpc43_ethmac_s *priv)
priv->txtail = txdesc;
- nllvdbg("txhead: %p txtail: %p inflight: %d\n",
- priv->txhead, priv->txtail, priv->inflight);
+ ninfo("txhead: %p txtail: %p inflight: %d\n",
+ priv->txhead, priv->txtail, priv->inflight);
}
}
@@ -1888,7 +1888,7 @@ static void lpc43_txdone(FAR struct lpc43_ethmac_s *priv)
lpc43_disableint(priv, ETH_DMAINT_TI);
}
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
lpc43_dopoll(priv);
}
@@ -1975,7 +1975,7 @@ static inline void lpc43_interrupt_process(FAR struct lpc43_ethmac_s *priv)
{
/* Just let the user know what happened */
- nlldbg("Abnormal event(s): %08x\n", dmasr);
+ nerr("ERROR: Abnormal event(s): %08x\n", dmasr);
/* Clear all pending abnormal events */
@@ -2120,7 +2120,7 @@ static inline void lpc43_txtimeout_process(FAR struct lpc43_ethmac_s *priv)
lpc43_ifdown(&priv->dev);
lpc43_ifup(&priv->dev);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
lpc43_dopoll(priv);
}
@@ -2179,7 +2179,7 @@ static void lpc43_txtimeout_expiry(int argc, uint32_t arg, ...)
{
FAR struct lpc43_ethmac_s *priv = (FAR struct lpc43_ethmac_s *)arg;
- nlldbg("Timeout!\n");
+ ninfo("Timeout!\n");
#ifdef CONFIG_NET_NOINTS
/* Disable further Ethernet interrupts. This will prevent some race
@@ -2381,15 +2381,15 @@ static int lpc43_ifup(struct net_driver_s *dev)
int ret;
#ifdef CONFIG_NET_IPv4
- ndbg("Bringing up: %d.%d.%d.%d\n",
- dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
- (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+ ninfo("Bringing up: %d.%d.%d.%d\n",
+ dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+ (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
#endif
#ifdef CONFIG_NET_IPv6
- ndbg("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n",
- dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2],
- dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5],
- dev->d_ipv6addr[6], dev->d_ipv6addr[7]);
+ ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n",
+ dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2],
+ dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5],
+ dev->d_ipv6addr[6], dev->d_ipv6addr[7]);
#endif
/* Configure the Ethernet interface for DMA operation. */
@@ -2435,7 +2435,7 @@ static int lpc43_ifdown(struct net_driver_s *dev)
FAR struct lpc43_ethmac_s *priv = (FAR struct lpc43_ethmac_s *)dev->d_private;
irqstate_t flags;
- ndbg("Taking the network down\n");
+ ninfo("Taking the network down\n");
/* Disable the Ethernet interrupt */
@@ -2480,7 +2480,7 @@ static int lpc43_ifdown(struct net_driver_s *dev)
static inline void lpc43_txavail_process(FAR struct lpc43_ethmac_s *priv)
{
- nvdbg("ifup: %d\n", priv->ifup);
+ ninfo("ifup: %d\n", priv->ifup);
/* Ignore the notification if the interface is not yet up */
@@ -2647,8 +2647,8 @@ static int lpc43_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
uint32_t temp;
uint32_t registeraddress;
- nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Add the MAC address to the hardware multicast hash table */
@@ -2704,8 +2704,8 @@ static int lpc43_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
uint32_t temp;
uint32_t registeraddress;
- nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Remove the MAC address to the hardware multicast hash table */
@@ -3065,7 +3065,7 @@ static int lpc43_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *val
}
}
- ndbg("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x\n",
+ nerr("ERROR: MII transfer timed out: phydevaddr: %04x phyregaddr: %04x\n",
phydevaddr, phyregaddr);
return -ETIMEDOUT;
@@ -3124,7 +3124,7 @@ static int lpc43_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t val
}
}
- ndbg("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x value: %04x\n",
+ nerr("ERROR: MII transfer timed out: phydevaddr: %04x phyregaddr: %04x value: %04x\n",
phydevaddr, phyregaddr, value);
return -ETIMEDOUT;
@@ -3161,7 +3161,7 @@ static inline int lpc43_dm9161(FAR struct lpc43_ethmac_s *priv)
ret = lpc43_phyread(CONFIG_LPC43_PHYADDR, MII_PHYID1, &phyval);
if (ret < 0)
{
- ndbg("Failed to read the PHY ID1: %d\n", ret);
+ nerr("ERROR: Failed to read the PHY ID1: %d\n", ret);
return ret;
}
@@ -3172,14 +3172,14 @@ static inline int lpc43_dm9161(FAR struct lpc43_ethmac_s *priv)
up_systemreset();
}
- nvdbg("PHY ID1: 0x%04X\n", phyval);
+ ninfo("PHY ID1: 0x%04X\n", phyval);
/* Now check the "DAVICOM Specified Configuration Register (DSCR)", Register 16 */
ret = lpc43_phyread(CONFIG_LPC43_PHYADDR, 16, &phyval);
if (ret < 0)
{
- ndbg("Failed to read the PHY Register 0x10: %d\n", ret);
+ nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret);
return ret;
}
@@ -3236,7 +3236,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
ret = lpc43_phywrite(CONFIG_LPC43_PHYADDR, MII_MCR, MII_MCR_RESET);
if (ret < 0)
{
- ndbg("Failed to reset the PHY: %d\n", ret);
+ nerr("ERROR: Failed to reset the PHY: %d\n", ret);
return ret;
}
@@ -3248,7 +3248,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
ret = lpc43_phy_boardinitialize(0);
if (ret < 0)
{
- ndbg("Failed to initialize the PHY: %d\n", ret);
+ nerr("ERROR: Failed to initialize the PHY: %d\n", ret);
return ret;
}
#endif
@@ -3273,7 +3273,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
ret = lpc43_phyread(CONFIG_LPC43_PHYADDR, MII_MSR, &phyval);
if (ret < 0)
{
- ndbg("Failed to read the PHY MSR: %d\n", ret);
+ nerr("ERROR: Failed to read the PHY MSR: %d\n", ret);
return ret;
}
else if ((phyval & MII_MSR_LINKSTATUS) != 0)
@@ -3284,7 +3284,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
if (timeout >= PHY_RETRY_TIMEOUT)
{
- ndbg("Timed out waiting for link status: %04x\n", phyval);
+ nerr("ERROR: Timed out waiting for link status: %04x\n", phyval);
return -ETIMEDOUT;
}
@@ -3293,7 +3293,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
ret = lpc43_phywrite(CONFIG_LPC43_PHYADDR, MII_MCR, MII_MCR_ANENABLE);
if (ret < 0)
{
- ndbg("Failed to enable auto-negotiation: %d\n", ret);
+ nerr("ERROR: Failed to enable auto-negotiation: %d\n", ret);
return ret;
}
@@ -3304,7 +3304,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
ret = lpc43_phyread(CONFIG_LPC43_PHYADDR, MII_MSR, &phyval);
if (ret < 0)
{
- ndbg("Failed to read the PHY MSR: %d\n", ret);
+ nerr("ERROR: Failed to read the PHY MSR: %d\n", ret);
return ret;
}
else if ((phyval & MII_MSR_ANEGCOMPLETE) != 0)
@@ -3315,7 +3315,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
if (timeout >= PHY_RETRY_TIMEOUT)
{
- ndbg("Timed out waiting for auto-negotiation\n");
+ nerr("ERROR: Timed out waiting for auto-negotiation\n");
return -ETIMEDOUT;
}
@@ -3324,13 +3324,13 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
ret = lpc43_phyread(CONFIG_LPC43_PHYADDR, CONFIG_LPC43_PHYSR, &phyval);
if (ret < 0)
{
- ndbg("Failed to read PHY status register\n");
+ nerr("ERROR: Failed to read PHY status register\n");
return ret;
}
/* Remember the selected speed and duplex modes */
- nvdbg("PHYSR[%d]: %04x\n", CONFIG_LPC43_PHYSR, phyval);
+ ninfo("PHYSR[%d]: %04x\n", CONFIG_LPC43_PHYSR, phyval);
#ifdef CONFIG_ETH0_PHY_LAN8720
if ((phyval & (MII_MSR_100BASETXHALF | MII_MSR_100BASETXFULL)) != 0)
@@ -3392,6 +3392,9 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
priv->mbps100 = 1;
}
#endif
+#endif
+
+#else /* Auto-negotion not selected */
#ifdef CONFIG_LPC43_ETHFD
priv->mbps100 = 1;
@@ -3400,11 +3403,9 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
#ifdef CONFIG_LPC43_ETH100MBPS
priv->fduplex = 1;
#endif
-#endif
-
- /* However we got here, commit to the hardware */
phyval = 0;
+
if (priv->mbps100)
{
phyval |= MII_MCR_FULLDPLX;
@@ -3418,7 +3419,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
ret = lpc43_phywrite(CONFIG_LPC43_PHYADDR, MII_MCR, phyval);
if (ret < 0)
{
- ndbg("Failed to write the PHY MCR: %d\n", ret);
+ nerr("ERROR: Failed to write the PHY MCR: %d\n", ret);
return ret;
}
@@ -3434,9 +3435,9 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
#endif
#endif
- ndbg("Duplex: %s Speed: %d MBps\n",
- priv->fduplex ? "FULL" : "HALF",
- priv->mbps100 ? 100 : 10);
+ ninfo("Duplex: %s Speed: %d MBps\n",
+ priv->fduplex ? "FULL" : "HALF",
+ priv->mbps100 ? 100 : 10);
return OK;
}
@@ -3718,11 +3719,11 @@ static void lpc43_macaddress(FAR struct lpc43_ethmac_s *priv)
FAR struct net_driver_s *dev = &priv->dev;
uint32_t regval;
- nllvdbg("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- dev->d_ifname,
- dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
- dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
- dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
+ ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ dev->d_ifname,
+ dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+ dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+ dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
/* Set the MAC address high register */
@@ -3786,7 +3787,7 @@ static void lpc43_ipv6multicast(FAR struct lpc43_ethmac_s *priv)
mac[4] = tmp16 & 0xff;
mac[5] = tmp16 >> 8;
- nvdbg("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
(void)lpc43_addmac(dev, mac);
@@ -3925,12 +3926,12 @@ static int lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv)
/* Reset the Ethernet block */
- nllvdbg("Reset the Ethernet block\n");
+ ninfo("Reset the Ethernet block\n");
lpc43_ethreset(priv);
/* Initialize the PHY */
- nllvdbg("Initialize the PHY\n");
+ ninfo("Initialize the PHY\n");
ret = lpc43_phyinit(priv);
if (ret < 0)
{
@@ -3945,7 +3946,7 @@ static int lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv)
/* Initialize the MAC and DMA */
- nllvdbg("Initialize the MAC and DMA\n");
+ ninfo("Initialize the MAC and DMA\n");
ret = lpc43_macconfig(priv);
if (ret < 0)
{
@@ -3966,7 +3967,7 @@ static int lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv)
/* Enable normal MAC operation */
- nllvdbg("Enable normal operation\n");
+ ninfo("Enable normal operation\n");
return lpc43_macenable(priv);
}
diff --git a/arch/arm/src/lpc43xx/lpc43_gpdma.c b/arch/arm/src/lpc43xx/lpc43_gpdma.c
index 991f80a1cfd74590c4d603727c6ef909b4b581ab..d104080a94d2985648cade171046f0217468dcd4 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpdma.c
+++ b/arch/arm/src/lpc43xx/lpc43_gpdma.c
@@ -57,48 +57,6 @@
#ifdef CONFIG_LPC43_GPDMA
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Enables debug output from this file (needs CONFIG_DEBUG too) */
-
-#undef DMA_DEBUG /* Define to enable debug */
-#undef DMA_VERBOSE /* Define to enable verbose debug */
-
-#ifdef DMA_DEBUG
-# define dmadbg lldbg
-# ifdef DMA_VERBOSE
-# define spivdbg lldbg
-# else
-# define spivdbg(x...)
-# endif
-#else
-# undef DMA_VERBOSE
-# define dmadbg(x...)
-# define spivdbg(x...)
-#endif
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
diff --git a/arch/arm/src/lpc43xx/lpc43_gpio.c b/arch/arm/src/lpc43xx/lpc43_gpio.c
index 3d5db11b7e49646dad43ba004812e808f0812298..783c66c0605a2de6a99780852e2002574129abdb 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpio.c
+++ b/arch/arm/src/lpc43xx/lpc43_gpio.c
@@ -49,6 +49,10 @@
#include "up_arch.h"
#include "lpc43_gpio.h"
+#ifdef CONFIG_LPC43_GPIO_IRQ
+#include "lpc43_gpioint.h"
+#endif
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -181,20 +185,20 @@ int lpc43_gpio_config(uint16_t gpiocfg)
case GPIO_MODE_PININTR: /* GPIO pin interrupt */
lpc43_configinput(gpiocfg, port, pin);
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC43_GPIO_IRQ
ret = lpc43_gpioint_pinconfig(gpiocfg);
#endif
break;
case GPIO_MODE_GRPINTR: /* GPIO group interrupt */
lpc43_configinput(gpiocfg, port, pin);
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC43_GPIO_IRQ
ret = lpc43_gpioint_grpconfig(gpiocfg);
#endif
break;
default :
- sdbg("ERROR: Unrecognized pin mode: %04x\n", gpiocfg);
+ serr("ERROR: Unrecognized pin mode: %04x\n", gpiocfg);
ret = -EINVAL;
break;
}
diff --git a/arch/arm/src/lpc43xx/lpc43_gpio.h b/arch/arm/src/lpc43xx/lpc43_gpio.h
index 1ee14fac6395d20f41291c07e3bf0c0fa0af1523..24a492beaed8d0f3851258de97427215111ca541 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpio.h
+++ b/arch/arm/src/lpc43xx/lpc43_gpio.h
@@ -143,7 +143,7 @@
* ..CC C... .... ....
*/
-#define GPIO_PININT_SHIFT (10) /* Bits 11-13: Pin interrupt number */
+#define GPIO_PININT_SHIFT (11) /* Bits 11-13: Pin interrupt number */
#define GPIO_PININT_MASK (7 << GPIO_PININT_SHIFT)
# define GPIO_PININT0 (0 << GPIO_PININT_SHIFT)
# define GPIO_PININT1 (1 << GPIO_PININT_SHIFT)
@@ -162,9 +162,9 @@
* .... .III .... ....
*/
-#define _GPIO_INT_LEVEL (1 << 10) /* Bit 10: 1=Level (vs edge) */
-#define _GPIO_INT_HIGH (1 << 9) /* Bit 9: 1=High level or rising edge */
-#define _GPIO_INT_LOW (1 << 8) /* Bit 8: 1=Low level or falling edge */
+#define _GPIO_INT_EDGE (1 << 10) /* Bit 10: 1=Edge (vs level) */
+#define _GPIO_INT_LOW (1 << 9) /* Bit 9: 1=Low level or falling edge */
+#define _GPIO_INT_HIGH (1 << 8) /* Bit 8: 1=High level or rising edge */
#define GPIO_INT_SHIFT (8) /* Bits 8-10: Interrupt mode */
#define GPIO_INT_MASK (7 << GPIO_INT_SHIFT)
@@ -176,8 +176,8 @@
#define GPIO_IS_ACTIVE_HI(p) (((p) & _GPIO_INT_HIGH) != 0)
#define GPIO_IS_ACTIVE_LOW(p) (((p) & _GPIO_INT_LOW) != 0)
-#define GPIO_IS_EDGE(p) (((p) & _GPIO_INT_LEVEL) == 0)
-#define GPIO_IS_LEVEL(p) (((p) & _GPIO_INT_LEVEL) != 0)
+#define GPIO_IS_LEVEL(p) (((p) & _GPIO_INT_EDGE) == 0)
+#define GPIO_IS_EDGE(p) (((p) & _GPIO_INT_EDGE) != 0)
/* GPIO Port Number:
*
@@ -310,7 +310,7 @@ bool lpc43_gpio_read(uint16_t gpiocfg);
*
********************************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
int lpc43_gpio_dump(uint16_t gpiocfg, const char *msg);
#else
# define lpc43_gpio_dump(p,m)
diff --git a/arch/arm/src/lpc43xx/lpc43_gpioint.c b/arch/arm/src/lpc43xx/lpc43_gpioint.c
index 51e010ba33042ae3349628df7f6000fe27cf55fe..e8726420c15118fa2309e9d6dbc82e866e3ded57 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpioint.c
+++ b/arch/arm/src/lpc43xx/lpc43_gpioint.c
@@ -57,6 +57,7 @@
#include
#include
+#include
#include
@@ -70,7 +71,7 @@
#include "lpc43_gpio.h"
#include "lpc43_gpioint.h"
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC43_GPIO_IRQ
/****************************************************************************
* Pre-processor Definitions
@@ -176,10 +177,13 @@ int lpc43_gpioint_grpinitialize(int group, bool anded, bool level)
int lpc43_gpioint_pinconfig(uint16_t gpiocfg)
{
unsigned int port = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
- unsigned int pin = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
+ unsigned int pin = ((gpiocfg & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
unsigned int pinint = ((gpiocfg & GPIO_PININT_MASK) >> GPIO_PININT_SHIFT);
uint32_t bitmask = (1 << pinint);
- uint32_t regval;
+ uint32_t pinsel;
+ uint32_t isel;
+ uint32_t einr;
+ uint32_t einf;
DEBUGASSERT(port < NUM_GPIO_PORTS && pin < NUM_GPIO_PINS && GPIO_IS_PININT(gpiocfg));
@@ -196,62 +200,69 @@ int lpc43_gpioint_pinconfig(uint16_t gpiocfg)
if (pinint < 4)
{
- regval = getreg32(LPC43_SCU_PINTSEL0);
- regval &= ~SCU_PINTSEL0_MASK(pinint);
- regval |= ((pin << SCU_PINTSEL0_INTPIN_SHIFT(pinint)) |
+ pinsel = getreg32(LPC43_SCU_PINTSEL0);
+ pinsel &= ~SCU_PINTSEL0_MASK(pinint);
+ pinsel |= ((pin << SCU_PINTSEL0_INTPIN_SHIFT(pinint)) |
(port << SCU_PINTSEL0_PORTSEL_SHIFT(pinint)));
- putreg32(regval, LPC43_SCU_PINTSEL0);
+ putreg32(pinsel, LPC43_SCU_PINTSEL0);
}
else
{
- regval = getreg32(LPC43_SCU_PINTSEL1);
- regval &= ~SCU_PINTSEL1_MASK(pinint);
- regval |= ((pin << SCU_PINTSEL1_INTPIN_SHIFT(pinint)) |
+ pinsel = getreg32(LPC43_SCU_PINTSEL1);
+ pinsel &= ~SCU_PINTSEL1_MASK(pinint);
+ pinsel |= ((pin << SCU_PINTSEL1_INTPIN_SHIFT(pinint)) |
(port << SCU_PINTSEL1_PORTSEL_SHIFT(pinint)));
- putreg32(regval, LPC43_SCU_PINTSEL1);
- }
-
- /* Set level or edge sensitive */
-
- regval = getreg32(LPC43_GPIOINT_ISEL);
- if (GPIO_IS_LEVEL(gpiocfg))
- {
- regval |= bitmask;
- }
- else
- {
- regval &= ~bitmask;
+ putreg32(pinsel, LPC43_SCU_PINTSEL1);
}
- putreg32(regval, LPC43_GPIOINT_ISEL);
+ /* Configure the active level or rising/falling edge
+ *
+ * ISEL
+ * 0 = Edge sensitive
+ * 1 = Level sensitive
+ * EINR 0-7:
+ * 0 = Disable rising edge or level interrupt.
+ * 1 = Enable rising edge or level interrupt.
+ * EINF 0-7:
+ * 0 = Disable falling edge interrupt or set active interrupt level
+ * LOW.
+ * 1 = Enable falling edge interrupt enabled or set active interrupt
+ * level HIGH
+ */
- /* Configure the active high level or rising edge */
+ isel = getreg32(LPC43_GPIOINT_ISEL) & ~bitmask;
+ einr = getreg32(LPC43_GPIOINT_IENR) & ~bitmask;
+ einf = getreg32(LPC43_GPIOINT_IENF) & ~bitmask;
- regval = getreg32(LPC43_GPIOINT_IENR);
- if (GPIO_IS_ACTIVE_HI(gpiocfg))
- {
- regval |= bitmask;
- }
- else
+ switch (gpiocfg & GPIO_INT_MASK)
{
- regval &= ~bitmask;
+ case GPIO_INT_LEVEL_HI:
+ einf |= bitmask; /* Enable active level HI */
+ case GPIO_INT_LEVEL_LOW:
+ isel |= bitmask; /* Level sensitive */
+ einr |= bitmask; /* Enable level interrupt */
+ break;
+
+ case GPIO_INT_EDGE_RISING:
+ einr |= bitmask; /* Enable rising edge interrupt */
+ break;
+
+ case GPIO_INT_EDGE_BOTH:
+ einr |= bitmask; /* Enable rising edge interrupt */
+ case GPIO_INT_EDGE_FALLING:
+ einf |= bitmask; /* Enable falling edge interrupt */
+ break;
+
+ /* Default is edge sensitive but with both edges disabled. */
+
+ default:
+ break;
}
- putreg32(regval, LPC43_GPIOINT_IENR);
-
- /* Configure the active high low or falling edge */
-
- regval = getreg32(LPC43_GPIOINT_IENF);
- if (GPIO_IS_ACTIVE_LOW(gpiocfg))
- {
- regval |= bitmask;
- }
- else
- {
- regval &= ~bitmask;
- }
+ putreg32(isel, LPC43_GPIOINT_ISEL);
+ putreg32(einr, LPC43_GPIOINT_IENR);
+ putreg32(einf, LPC43_GPIOINT_IENF);
- putreg32(regval, LPC43_GPIOINT_IENF);
return OK;
}
@@ -321,4 +332,29 @@ int lpc43_gpioint_grpconfig(uint16_t gpiocfg)
return OK;
}
-#endif /* CONFIG_GPIO_IRQ */
+/****************************************************************************
+ * Name: lpc43_gpioint_ack
+ *
+ * Description:
+ * Acknowledge the interrupt for a given pint interrupt number. Call this
+ * inside the interrupt handler. For edge sensitive interrupts, the interrupt
+ * status is cleared. For level sensitive interrupts, the active-high/-low
+ * sensitivity is inverted.
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int lpc43_gpioint_ack(uint8_t intnumber)
+{
+ uint32_t regval;
+
+ regval = getreg32(LPC43_GPIOINT_IST);
+ regval |= (1 << intnumber);
+ putreg32(regval, LPC43_GPIOINT_IST);
+
+ return OK;
+}
+
+#endif /* CONFIG_LPC43_GPIO_IRQ */
diff --git a/arch/arm/src/lpc43xx/lpc43_gpioint.h b/arch/arm/src/lpc43xx/lpc43_gpioint.h
index 35b22f7c7f27abd6e150a1e552bf1787308c184d..ae479f83c67a2e74e75dc7d4fe1f14b9975b20a7 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpioint.h
+++ b/arch/arm/src/lpc43xx/lpc43_gpioint.h
@@ -1,7 +1,7 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/lpc43xx/lpc43_gpioint.h
*
- * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -31,7 +31,8 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
+
/* GPIO pin interrupts
*
* From all available GPIO pins, up to eight pins can be selected in the system
@@ -52,31 +53,19 @@
#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_GPIOINT_H
#define __ARCH_ARM_SRC_LPC43XX_LPC43_GPIOINT_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include
#include "chip.h"
#include "chip/lpc43_gpio.h"
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC43_GPIO_IRQ
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
/****************************************************************************
* Name: lpc43_gpioint_grpinitialize
@@ -136,5 +125,21 @@ int lpc43_gpioint_pinconfig(uint16_t gpiocfg);
int lpc43_gpioint_grpconfig(uint16_t gpiocfg);
-#endif /* CONFIG_GPIO_IRQ */
+/****************************************************************************
+ * Name: lpc43_gpioint_ack
+ *
+ * Description:
+ * Acknowledge the interrupt for a given pint interrupt number. Call this
+ * inside the interrupt handler. For edge sensitive interrupts, the interrupt
+ * status is cleared. For level sensitive interrupts, the active-high/-low
+ * sensitivity is inverted.
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int lpc43_gpioint_ack(uint8_t intnumber);
+
+#endif /* CONFIG_LPC43_GPIO_IRQ */
#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_GPIOINT_H */
diff --git a/arch/arm/src/lpc43xx/lpc43_i2c.c b/arch/arm/src/lpc43xx/lpc43_i2c.c
index a7ddfa4726cbf0f43a9aa4137269b2d353c8c87d..fed79db207346085b6bed336ce76d95d03587325 100644
--- a/arch/arm/src/lpc43xx/lpc43_i2c.c
+++ b/arch/arm/src/lpc43xx/lpc43_i2c.c
@@ -464,7 +464,7 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port)
if (port > 1)
{
- dbg("lpc I2C Only support 0,1\n");
+ i2cerr("ERROR: lpc I2C Only suppors ports 0 and 1\n");
return NULL;
}
diff --git a/arch/arm/src/lpc43xx/lpc43_idle.c b/arch/arm/src/lpc43xx/lpc43_idle.c
index 62f665495e01bd3c1fddad91f2278912e347b362..5cc38b16f5facbdea98eef7a1e239bb284f4de52 100644
--- a/arch/arm/src/lpc43xx/lpc43_idle.c
+++ b/arch/arm/src/lpc43xx/lpc43_idle.c
@@ -98,7 +98,7 @@ static void up_idlepm(void)
/* Perform board-specific, state-dependent logic here */
- llvdbg("newstate= %d oldstate=%d\n", newstate, oldstate);
+ _info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
diff --git a/arch/arm/src/lpc43xx/lpc43_irq.c b/arch/arm/src/lpc43xx/lpc43_irq.c
index 73ca6d3bc7cb53063899cb35d89b94a058036658..345f63b5c24eb8f639da0c47e9dfe3ed04f1a5d4 100644
--- a/arch/arm/src/lpc43xx/lpc43_irq.c
+++ b/arch/arm/src/lpc43xx/lpc43_irq.c
@@ -107,37 +107,39 @@ extern uint32_t _vectors[];
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_IRQ)
+#if defined(CONFIG_DEBUG_IRQ_INFO)
static void lpc43_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
- lldbg("NVIC (%s, irq=%d):\n", msg, irq);
- lldbg(" INTCTRL: %08x VECTAB: %08x\n",
- getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
+
+ irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
+ irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
+ getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
- lldbg(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
- getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
- getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
+ irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
+ getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
+ getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
- lldbg(" IRQ ENABLE: %08x %08x\n",
- getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE));
- lldbg(" SYSH_PRIO: %08x %08x %08x\n",
- getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
- getreg32(NVIC_SYSH12_15_PRIORITY));
- lldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
- getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
- getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
- getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
- lldbg(" %08x %08x %08x\n",
- getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
- getreg32(NVIC_IRQ56_59_PRIORITY));
+ irqinfo(" IRQ ENABLE: %08x %08x\n",
+ getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE));
+ irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
+ getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
+ getreg32(NVIC_SYSH12_15_PRIORITY));
+ irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
+ getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
+ getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
+ getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
+ irqinfo(" %08x %08x %08x\n",
+ getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
+ getreg32(NVIC_IRQ56_59_PRIORITY));
+
leave_critical_section(flags);
}
#else
@@ -155,11 +157,11 @@ static void lpc43_dumpnvic(const char *msg, int irq)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
static int lpc43_nmi(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! NMI received\n");
+ _err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
@@ -167,7 +169,7 @@ static int lpc43_nmi(int irq, FAR void *context)
static int lpc43_busfault(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Bus fault recived\n");
+ _err("PANIC!!! Bus fault recived\n");
PANIC();
return 0;
}
@@ -175,7 +177,7 @@ static int lpc43_busfault(int irq, FAR void *context)
static int lpc43_usagefault(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Usage fault received\n");
+ _err("PANIC!!! Usage fault received\n");
PANIC();
return 0;
}
@@ -183,7 +185,7 @@ static int lpc43_usagefault(int irq, FAR void *context)
static int lpc43_pendsv(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! PendSV received\n");
+ _err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
@@ -191,7 +193,7 @@ static int lpc43_pendsv(int irq, FAR void *context)
static int lpc43_dbgmonitor(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Debug Monitor received\n");
+ _err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
}
@@ -199,7 +201,7 @@ static int lpc43_dbgmonitor(int irq, FAR void *context)
static int lpc43_reserved(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Reserved interrupt\n");
+ _err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
@@ -246,18 +248,45 @@ static int lpc43_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
if (irq >= LPC43_IRQ_EXTINT)
{
+ /* NOTE: We assume that there are at least 32 interrupts */
+
if (irq < (LPC43_IRQ_EXTINT + 32))
{
+ /* Interrupt in range {0-31} */
+
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << (irq - LPC43_IRQ_EXTINT);
}
+#if LPC43M4_IRQ_NEXTINT > 95
+# error Extension to interrupt logic needed
+#elif LPC43M4_IRQ_NEXTINT > 63
+ else if (irq < (LPC43_IRQ_EXTINT + 64))
+ {
+ /* Interrupt in range {32-63} */
+
+ *regaddr = (NVIC_IRQ32_63_ENABLE + offset);
+ *bit = 1 << (irq - LPC43_IRQ_EXTINT - 32);
+ }
else if (irq < LPC43M4_IRQ_NIRQS)
{
+ /* Interrupt in range {64-LPC43M4_IRQ_NIRQS}, LPC43M4_IRQ_NIRQS <= 95 */
+
+ *regaddr = (NVIC_IRQ64_95_ENABLE + offset);
+ *bit = 1 << (irq - LPC43_IRQ_EXTINT - 64);
+ }
+#else /* if LPC43M4_IRQ_NEXTINT > 31 */
+ else if (irq < LPC43M4_IRQ_NIRQS)
+ {
+ /* Interrupt in range {32-LPC43M4_IRQ_NIRQS}, LPC43M4_IRQ_NIRQS <= 63 */
+
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (irq - LPC43_IRQ_EXTINT - 32);
}
+#endif
else
{
+ /* Interrupt >= LPC43M4_IRQ_NIRQS */
+
return ERROR; /* Invalid interrupt */
}
}
@@ -309,7 +338,7 @@ static int lpc43_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
void up_irqinitialize(void)
{
uint32_t regaddr;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
uint32_t regval;
#endif
int num_priority_registers;
@@ -317,7 +346,12 @@ void up_irqinitialize(void)
/* Disable all interrupts */
putreg32(0, NVIC_IRQ0_31_ENABLE);
+#if LPC43M4_IRQ_NEXTINT > 31
putreg32(0, NVIC_IRQ32_63_ENABLE);
+#if LPC43M4_IRQ_NEXTINT > 63
+ putreg32(0, NVIC_IRQ64_95_ENABLE);
+#endif
+#endif
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
@@ -395,7 +429,7 @@ void up_irqinitialize(void)
/* Attach all other processor exceptions (except reset and sys tick) */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
irq_attach(LPC43_IRQ_NMI, lpc43_nmi);
#ifndef CONFIG_ARM_MPU
irq_attach(LPC43_IRQ_MEMFAULT, up_memfault);
@@ -414,7 +448,7 @@ void up_irqinitialize(void)
* operation.
*/
-#if defined(CONFIG_DEBUG) && !defined(CONFIG_ARMV7M_USEBASEPRI)
+#if defined(CONFIG_DEBUG_FEATURES) && !defined(CONFIG_ARMV7M_USEBASEPRI)
regval = getreg32(NVIC_DEMCR);
regval &= ~NVIC_DEMCR_VCHARDERR;
putreg32(regval, NVIC_DEMCR);
diff --git a/arch/arm/src/lpc43xx/lpc43_pinconfig.h b/arch/arm/src/lpc43xx/lpc43_pinconfig.h
index dad885d86bd52050605ed24abd7df00322dde0e7..63e7d768bdc6c712a921970f00819f4512893689 100644
--- a/arch/arm/src/lpc43xx/lpc43_pinconfig.h
+++ b/arch/arm/src/lpc43xx/lpc43_pinconfig.h
@@ -264,7 +264,7 @@ int lpc43_pin_config(uint32_t pinconf);
*
********************************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
int lpc43_pin_dump(uint32_t pinconf, const char *msg);
#else
# define lpc43_pin_dump(p,m)
diff --git a/arch/arm/src/lpc43xx/lpc43_rgu.c b/arch/arm/src/lpc43xx/lpc43_rgu.c
index 9671a4f8a59709f3b672240eeeaa33acb1f5c4f6..799e3c21e65dc5cc79a0d2b548cd9b27d2765cf0 100644
--- a/arch/arm/src/lpc43xx/lpc43_rgu.c
+++ b/arch/arm/src/lpc43xx/lpc43_rgu.c
@@ -75,7 +75,7 @@
* Description:
* Reset as many of the LPC43 peripherals as possible. This is necessary
* because the LPC43 does not provide any way of performing a full system
- * reset under debugger control. So, if CONFIG_DEBUG is set (indicating
+ * reset under debugger control. So, if CONFIG_DEBUG_FEATURES is set (indicating
* that a debugger is being used?), the boot logic will call this
* function on all restarts.
*
diff --git a/arch/arm/src/lpc43xx/lpc43_rgu.h b/arch/arm/src/lpc43xx/lpc43_rgu.h
index 2d1604d23a4c3a9b44ce09773c587b1a6c47e75f..f283a9aaf3611d083652eefa8c6c70309cced9fb 100644
--- a/arch/arm/src/lpc43xx/lpc43_rgu.h
+++ b/arch/arm/src/lpc43xx/lpc43_rgu.h
@@ -76,7 +76,7 @@ extern "C"
* Description:
* Reset as many of the LPC43 peripherals as possible. This is necessary
* because the LPC43 does not provide any way of performing a full system
- * reset under debugger control. So, if CONFIG_DEBUG is set (indicating
+ * reset under debugger control. So, if CONFIG_DEBUG_FEATURES is set (indicating
* that a debugger is being used?), the boot logic will call this
* function on all restarts.
*
diff --git a/arch/arm/src/lpc43xx/lpc43_rit.c b/arch/arm/src/lpc43xx/lpc43_rit.c
index f80cd550ac052725e44155c8ba45c918c1e5003a..e42fc7db438a7c12f66cb1002028c8f043e7a9a8 100644
--- a/arch/arm/src/lpc43xx/lpc43_rit.c
+++ b/arch/arm/src/lpc43xx/lpc43_rit.c
@@ -201,8 +201,8 @@ void up_timer_initialize(void)
mask_bits++;
}
- lldbg("mask_bits = %d, mask = %X, ticks_per_int = %d\r\n",
- mask_bits, (0xffffffff << (32 - mask_bits)), ticks_per_int);
+ tmrinfo("mask_bits = %d, mask = %X, ticks_per_int = %d\r\n",
+ mask_bits, (0xffffffff << (32 - mask_bits)), ticks_per_int);
/* Set the mask and compare value so we get interrupts every
* RIT_TIMER_RESOLUTION cycles.
diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c
index c12d65597b1b2e7df3709df5f75fe79df6bc052d..56e03bbea03cf0a25adac1d62677f2b0fab6c715 100644
--- a/arch/arm/src/lpc43xx/lpc43_serial.c
+++ b/arch/arm/src/lpc43xx/lpc43_serial.c
@@ -854,7 +854,7 @@ static int up_interrupt(int irq, void *context)
/* Read the modem status register (MSR) to clear */
status = up_serialin(priv, LPC43_UART_MSR_OFFSET);
- vdbg("MSR: %02x\n", status);
+ _info("MSR: %02x\n", status);
break;
}
@@ -865,7 +865,7 @@ static int up_interrupt(int irq, void *context)
/* Read the line status register (LSR) to clear */
status = up_serialin(priv, LPC43_UART_LSR_OFFSET);
- vdbg("LSR: %02x\n", status);
+ _info("LSR: %02x\n", status);
break;
}
@@ -873,7 +873,7 @@ static int up_interrupt(int irq, void *context)
default:
{
- dbg("Unexpected IIR: %02x\n", status);
+ _err("ERROR: Unexpected IIR: %02x\n", status);
break;
}
}
diff --git a/arch/arm/src/lpc43xx/lpc43_spi.c b/arch/arm/src/lpc43xx/lpc43_spi.c
index 32b5a45913188bb7bc0d1f39dbfafdf51f41bc01..e30b39bf25980e8df1c4dc679bf709a1c1afcc33 100644
--- a/arch/arm/src/lpc43xx/lpc43_spi.c
+++ b/arch/arm/src/lpc43xx/lpc43_spi.c
@@ -64,21 +64,6 @@
* Pre-processor Definitions
****************************************************************************/
-/* Enables debug output from this file (needs CONFIG_DEBUG too) */
-
-#ifdef CONFIG_DEBUG_SPI
-# define spidbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define spivdbg lldbg
-# else
-# define spivdbg(x...)
-# endif
-#else
-# undef CONFIG_DEBUG_VERBOSE
-# define spidbg(x...)
-# define spivdbg(x...)
-#endif
-
/* SPI Clocking.
*
* The CPU clock by 1, 2, 4, or 8 to get the SPI peripheral clock (SPI_CLOCK).
@@ -274,7 +259,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
priv->frequency = frequency;
priv->actual = actual;
- spidbg("Frequency %d->%d\n", frequency, actual);
+ spiinfo("Frequency %d->%d\n", frequency, actual);
return actual;
}
@@ -436,7 +421,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
FAR uint8_t *ptr = (FAR uint8_t *)buffer;
uint8_t data;
- spidbg("nwords: %d\n", nwords);
+ spiinfo("nwords: %d\n", nwords);
while (nwords)
{
/* Write the data to transmitted to the SPI Data Register */
@@ -481,7 +466,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
{
FAR uint8_t *ptr = (FAR uint8_t *)buffer;
- spidbg("nwords: %d\n", nwords);
+ spiinfo("nwords: %d\n", nwords);
while (nwords)
{
/* Write some dummy data to the SPI Data Register in order to clock the
diff --git a/arch/arm/src/lpc43xx/lpc43_spifi.c b/arch/arm/src/lpc43xx/lpc43_spifi.c
index 0d90ea9fceb15b162652c9a627e1888c160ef990..71920dc47750290990302ffd9dd6d9670f737df5 100644
--- a/arch/arm/src/lpc43xx/lpc43_spifi.c
+++ b/arch/arm/src/lpc43xx/lpc43_spifi.c
@@ -92,7 +92,7 @@
* from the SPI address space after each write.
* CONFIG_DEBUG_SPIFI_DUMP - Debug option to dump read/write buffers. You
* probably do not want to enable this unless you want to dig through a
- * *lot* of debug output! Also required CONFIG_DEBUG, CONFIG_DEBUG_VERBOSE,
+ * *lot* of debug output! Also required CONFIG_DEBUG_FEATURES, CONFIG_DEBUG_INFO,
* and CONFIG_DEBUG_FS,
*/
@@ -263,7 +263,7 @@
* enable this unless you want to dig through a *lot* of debug output!
*/
-#if !defined(CONFIG_DEBUG) || !defined(CONFIG_DEBUG_VERBOSE) || !defined(CONFIG_DEBUG_FS)
+#if !defined(CONFIG_DEBUG_FEATURES) || !defined(CONFIG_DEBUG_INFO) || !defined(CONFIG_DEBUG_FS)
# undef CONFIG_DEBUG_SPIFI_DUMP
#endif
@@ -382,13 +382,13 @@ static void lpc43_blockerase(struct lpc43_dev_s *priv, off_t sector)
priv->operands.dest = SPIFI_BASE + (sector << SPIFI_BLKSHIFT);
priv->operands.length = SPIFI_BLKSIZE;
- fvdbg("SPIFI_ERASE: dest=%p length=%d\n",
+ finfo("SPIFI_ERASE: dest=%p length=%d\n",
priv->operands.dest, priv->operands.length);
result = SPIFI_ERASE(priv, &priv->rom, &priv->operands);
if (result != 0)
{
- fdbg("ERROR: SPIFI_ERASE failed: %05x\n", result);
+ ferr("ERROR: SPIFI_ERASE failed: %05x\n", result);
}
}
@@ -411,13 +411,13 @@ static inline int lpc43_chiperase(struct lpc43_dev_s *priv)
priv->operands.dest = SPIFI_BASE;
priv->operands.length = SPIFI_BLKSIZE * priv->nblocks;
- fvdbg("SPIFI_ERASE: dest=%p length=%d\n",
+ finfo("SPIFI_ERASE: dest=%p length=%d\n",
priv->operands.dest, priv->operands.length);
result = SPIFI_ERASE(priv, &priv->rom, &priv->operands);
if (result != 0)
{
- fdbg("ERROR: SPIFI_ERASE failed: %05x\n", result);
+ ferr("ERROR: SPIFI_ERASE failed: %05x\n", result);
return -EIO;
}
@@ -457,13 +457,13 @@ static int lpc43_pagewrite(FAR struct lpc43_dev_s *priv, FAR uint8_t *dest,
priv->operands.dest = dest;
priv->operands.length = nbytes;
- fvdbg("SPIFI_PROGRAM: src=%p dest=%p length=%d\n",
+ finfo("SPIFI_PROGRAM: src=%p dest=%p length=%d\n",
src, priv->operands.dest, priv->operands.length);
result = SPIFI_PROGRAM(priv, &priv->rom, src, &priv->operands);
if (result != 0)
{
- fdbg("ERROR: SPIFI_PROGRAM failed: %05x\n", result);
+ ferr("ERROR: SPIFI_PROGRAM failed: %05x\n", result);
return -EIO;
}
@@ -475,7 +475,7 @@ static int lpc43_pagewrite(FAR struct lpc43_dev_s *priv, FAR uint8_t *dest,
result = lpc43_verify(priv, dest, src, nbytes);
if (result != 0)
{
- fdbg("ERROR: lpc43_verify failed: %05x\n", result);
+ ferr("ERROR: lpc43_verify failed: %05x\n", result);
return -EIO;
}
#endif
@@ -492,7 +492,7 @@ static inline void lpc43_pageread(FAR struct lpc43_dev_s *priv,
FAR uint8_t *dest, FAR const uint8_t *src,
size_t nbytes)
{
- fvdbg("src=%p dest=%p length=%d\n", src, dest, nbytes);
+ finfo("src=%p dest=%p length=%d\n", src, dest, nbytes);
memcpy(dest, src, nbytes);
}
@@ -511,7 +511,7 @@ static void lpc43_cacheflush(struct lpc43_dev_s *priv)
* the cached erase block to FLASH.
*/
- fvdbg("flags: %02x blkno: %d\n", priv->flags, priv->blkno);
+ finfo("flags: %02x blkno: %d\n", priv->flags, priv->blkno);
if (IS_DIRTY(priv) || IS_ERASED(priv))
{
/* Get the SPIFI address corresponding to the cached erase block */
@@ -523,7 +523,7 @@ static void lpc43_cacheflush(struct lpc43_dev_s *priv)
ret = lpc43_pagewrite(priv, dest, priv->cache, SPIFI_BLKSIZE);
if (ret < 0)
{
- fdbg("ERROR: lpc43_pagewrite failed: %d\n", ret);
+ ferr("ERROR: lpc43_pagewrite failed: %d\n", ret);
}
/* The case is no long dirty and the FLASH is no longer erased */
@@ -551,7 +551,7 @@ static FAR uint8_t *lpc43_cacheread(struct lpc43_dev_s *priv, off_t sector)
*/
blkno = sector >> (SPIFI_BLKSHIFT - SPIFI_512SHIFT);
- fvdbg("sector: %ld blkno: %d\n", sector, blkno);
+ finfo("sector: %ld blkno: %d\n", sector, blkno);
/* Check if the requested erase block is already in the cache */
@@ -612,7 +612,7 @@ static void lpc43_cacheerase(struct lpc43_dev_s *priv, off_t sector)
if (!IS_ERASED(priv))
{
off_t blkno = sector >> (SPIFI_BLKSHIFT - SPIFI_512SHIFT);
- fvdbg("sector: %ld blkno: %d\n", sector, blkno);
+ finfo("sector: %ld blkno: %d\n", sector, blkno);
lpc43_blockerase(priv, blkno);
SET_ERASED(priv);
@@ -646,7 +646,7 @@ static void lpc43_cachewrite(FAR struct lpc43_dev_s *priv, FAR const uint8_t *bu
dest = lpc43_cacheread(priv, sector);
- fvdbg("dest=%p src=%p sector: %ld flags: %02x\n",
+ finfo("dest=%p src=%p sector: %ld flags: %02x\n",
dest, buffer, sector, priv->flags);
/* Erase the block containing this sector if it is not already erased.
@@ -657,7 +657,7 @@ static void lpc43_cachewrite(FAR struct lpc43_dev_s *priv, FAR const uint8_t *bu
if (!IS_ERASED(priv))
{
off_t blkno = sector >> (SPIFI_BLKSHIFT - SPIFI_512SHIFT);
- fvdbg("sector: %ld blkno: %d\n", sector, blkno);
+ finfo("sector: %ld blkno: %d\n", sector, blkno);
lpc43_blockerase(priv, blkno);
SET_ERASED(priv);
@@ -692,7 +692,7 @@ static int lpc43_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nbloc
FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
size_t blocksleft = nblocks;
- fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
+ finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
while (blocksleft-- > 0)
{
@@ -726,7 +726,7 @@ static ssize_t lpc43_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t n
#ifdef CONFIG_SPIFI_SECTOR512
ssize_t nbytes;
- fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
+ finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
/* On this device, we can handle the block read just like the byte-oriented read */
@@ -743,7 +743,7 @@ static ssize_t lpc43_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t n
FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
ssize_t nbytes;
- fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
+ finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
/* On this device, we can handle the block read just like the byte-oriented read */
@@ -774,7 +774,7 @@ static ssize_t lpc43_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t
FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
- fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
+ finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
lpc43_cachewrite(priv, buffer, startblock, nblocks);
@@ -786,7 +786,7 @@ static ssize_t lpc43_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t
FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
FAR uint8_t *dest;
- fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
+ finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
/* Get the SPIFI address corresponding to the erase block */
@@ -798,7 +798,7 @@ static ssize_t lpc43_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t
ret = lpc43_pagewrite(priv, dest, buffer, nblocks << SPIFI_512SHIFT);
if (ret < 0)
{
- fdbg("ERROR: lpc43_pagewrite failed: %d\n", ret);
+ ferr("ERROR: lpc43_pagewrite failed: %d\n", ret);
return ret;
}
#endif
@@ -819,7 +819,7 @@ static ssize_t lpc43_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes
FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
FAR const uint8_t *src;
- fvdbg("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);
+ finfo("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);
/* Get the SPIFI address corresponding sector */
@@ -829,7 +829,7 @@ static ssize_t lpc43_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes
lpc43_pageread(priv, buffer, src, nbytes);
- fvdbg("return nbytes: %d\n", (int)nbytes);
+ finfo("return nbytes: %d\n", (int)nbytes);
return nbytes;
}
@@ -842,7 +842,7 @@ static int lpc43_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
int ret = -EINVAL; /* Assume good command with bad parameters */
- fvdbg("cmd: %d \n", cmd);
+ finfo("cmd: %d \n", cmd);
switch (cmd)
{
@@ -871,7 +871,7 @@ static int lpc43_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
#endif
ret = OK;
- fvdbg("blocksize: %d erasesize: %d neraseblocks: %d\n",
+ finfo("blocksize: %d erasesize: %d neraseblocks: %d\n",
geo->blocksize, geo->erasesize, geo->neraseblocks);
}
}
@@ -891,7 +891,7 @@ static int lpc43_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
break;
}
- fvdbg("return %d\n", ret);
+ finfo("return %d\n", ret);
return ret;
}
@@ -1025,7 +1025,7 @@ static inline int lpc43_rominit(FAR struct lpc43_dev_s *priv)
S_RCVCLK | S_FULLCLK, SCLK_MHZ);
if (result != 0)
{
- fdbg("ERROR: SPIFI_INIT failed: %05x\n", result);
+ ferr("ERROR: SPIFI_INIT failed: %05x\n", result);
/* Try again */
@@ -1033,29 +1033,29 @@ static inline int lpc43_rominit(FAR struct lpc43_dev_s *priv)
S_RCVCLK | S_FULLCLK, SCLK_MHZ);
if (result != 0)
{
- fdbg("ERROR: SPIFI_INIT failed: %05x\n", result);
+ ferr("ERROR: SPIFI_INIT failed: %05x\n", result);
return -ENODEV;
}
}
- fvdbg("SPFI:\n");
- fvdbg(" base: %08x\n", priv->rom.base);
- fvdbg(" regbase: %08x\n", priv->rom.regbase);
- fvdbg(" devsize: %08x\n", priv->rom.devsize);
- fvdbg(" memsize: %08x\n", priv->rom.memsize);
- fvdbg(" mfger: %02x\n", priv->rom.mfger);
- fvdbg(" devtype: %02x\n", priv->rom.devtype);
- fvdbg(" devid: %02x\n", priv->rom.devid);
- fvdbg(" busy: %02x\n", priv->rom.busy);
- fvdbg(" stat: %04x\n", priv->rom.stat.h);
- fvdbg(" setprot: %04x\n", priv->rom.setprot);
- fvdbg(" writeprot: %04x\n", priv->rom.writeprot);
- fvdbg(" memcmd: %08x\n", priv->rom.memcmd);
- fvdbg(" progcmd: %08x\n", priv->rom.progcmd);
- fvdbg(" sectors: %04x\n", priv->rom.sectors);
- fvdbg(" protbytes: %04x\n", priv->rom.protbytes);
- fvdbg(" opts: %08x\n", priv->rom.opts);
- fvdbg(" errcheck: %08x\n", priv->rom.errcheck);
+ finfo("SPFI:\n");
+ finfo(" base: %08x\n", priv->rom.base);
+ finfo(" regbase: %08x\n", priv->rom.regbase);
+ finfo(" devsize: %08x\n", priv->rom.devsize);
+ finfo(" memsize: %08x\n", priv->rom.memsize);
+ finfo(" mfger: %02x\n", priv->rom.mfger);
+ finfo(" devtype: %02x\n", priv->rom.devtype);
+ finfo(" devid: %02x\n", priv->rom.devid);
+ finfo(" busy: %02x\n", priv->rom.busy);
+ finfo(" stat: %04x\n", priv->rom.stat.h);
+ finfo(" setprot: %04x\n", priv->rom.setprot);
+ finfo(" writeprot: %04x\n", priv->rom.writeprot);
+ finfo(" memcmd: %08x\n", priv->rom.memcmd);
+ finfo(" progcmd: %08x\n", priv->rom.progcmd);
+ finfo(" sectors: %04x\n", priv->rom.sectors);
+ finfo(" protbytes: %04x\n", priv->rom.protbytes);
+ finfo(" opts: %08x\n", priv->rom.opts);
+ finfo(" errcheck: %08x\n", priv->rom.errcheck);
/* Get the largest erase block size */
@@ -1065,11 +1065,11 @@ static inline int lpc43_rominit(FAR struct lpc43_dev_s *priv)
sectors = priv->rom.sectors;
log2 = 0;
- fvdbg("FLASH Geometry:\n");
+ finfo("FLASH Geometry:\n");
while (sectors > 0)
{
- fvdbg(" log2: %d rept: %d\n", desc->log2, desc->rept);
+ finfo(" log2: %d rept: %d\n", desc->log2, desc->rept);
/* Check if this is the largest erase block size seen */
@@ -1091,10 +1091,10 @@ static inline int lpc43_rominit(FAR struct lpc43_dev_s *priv)
priv->blksize = (1 << log2);
priv->nblocks = (priv->rom.memsize - CONFIG_SPIFI_OFFSET) / priv->blksize;
- fvdbg("Driver FLASH Geometry:\n");
- fvdbg(" blkshift: %d\n", priv->blkshift);
- fvdbg(" blksize: %08x\n", priv->blksize);
- fvdbg(" nblocks: %d\n", priv->nblocks);
+ finfo("Driver FLASH Geometry:\n");
+ finfo(" blkshift: %d\n", priv->blkshift);
+ finfo(" blksize: %08x\n", priv->blksize);
+ finfo(" nblocks: %d\n", priv->nblocks);
#ifdef CONFIG_SPIFI_SECTOR512
DEBUGASSERT(log2 > 9);
@@ -1106,10 +1106,10 @@ static inline int lpc43_rominit(FAR struct lpc43_dev_s *priv)
priv->nblocks = ((priv->rom.memsize - CONFIG_SPIFI_OFFSET) >> SPIFI_BLKSHIFT);
- fvdbg("Driver FLASH Geometry:\n");
- fvdbg(" blkshift: %d\n", SPIFI_BLKSHIFT);
- fvdbg(" blksize: %08x\n", SPIFI_BLKSIZE);
- fvdbg(" nblocks: %d\n", priv->nblocks);
+ finfo("Driver FLASH Geometry:\n");
+ finfo(" blkshift: %d\n", SPIFI_BLKSHIFT);
+ finfo(" blksize: %08x\n", SPIFI_BLKSIZE);
+ finfo(" nblocks: %d\n", priv->nblocks);
#endif
return OK;
@@ -1201,14 +1201,14 @@ FAR struct mtd_dev_s *lpc43_spifi_initialize(void)
{
/* Allocation failed! Discard all of that work we just did and return NULL */
- fdbg("ERROR: Allocation failed\n");
+ ferr("ERROR: Allocation failed\n");
return NULL;
}
#endif
/* Return the implementation-specific state structure as the MTD device */
- fvdbg("Return %p\n", priv);
+ finfo("Return %p\n", priv);
return (FAR struct mtd_dev_s *)priv;
}
diff --git a/arch/arm/src/lpc43xx/lpc43_ssp.c b/arch/arm/src/lpc43xx/lpc43_ssp.c
index 0d227fa8fa57e3ff7f808a366d78870eb564d22f..49f7c5781f990712dfc04833e5a5d33a496590b7 100644
--- a/arch/arm/src/lpc43xx/lpc43_ssp.c
+++ b/arch/arm/src/lpc43xx/lpc43_ssp.c
@@ -62,34 +62,8 @@
#include "lpc43_ccu.h"
#include "lpc43_pinconfig.h"
-
#if defined(CONFIG_LPC43_SSP0) || defined(CONFIG_LPC43_SSP1)
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* The following enable debug output from this file (needs CONFIG_DEBUG too).
- *
- * CONFIG_SSP_DEBUG - Define to enable basic SSP debug
- * CONFIG_SSP_VERBOSE - Define to enable verbose SSP debug
- */
-
-#ifdef CONFIG_SSP_DEBUG
-# define sspdbg lldbg
-# ifdef CONFIG_SSP_VERBOSE
-# define spivdbg lldbg
-# else
-# define spivdbg(x...)
-# endif
-#else
-# undef CONFIG_SSP_VERBOSE
-# define sspdbg(x...)
-# define spivdbg(x...)
-#endif
-
-
-
/****************************************************************************
* Private Types
****************************************************************************/
@@ -378,7 +352,7 @@ static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
priv->frequency = frequency;
priv->actual = actual;
- sspdbg("Frequency %d->%d\n", frequency, actual);
+ spiinfo("Frequency %d->%d\n", frequency, actual);
return actual;
}
@@ -429,7 +403,7 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
break;
default:
- sspdbg("Bad mode: %d\n", mode);
+ spierr("ERROR: Bad mode: %d\n", mode);
DEBUGASSERT(FALSE);
return;
}
@@ -517,7 +491,7 @@ static uint16_t ssp_send(FAR struct spi_dev_s *dev, uint16_t wd)
/* Get the value from the RX FIFO and return it */
regval = ssp_getreg(priv, LPC43_SSP_DR_OFFSET);
- sspdbg("%04x->%04x\n", wd, regval);
+ spiinfo("%04x->%04x\n", wd, regval);
return (uint16_t)regval;
}
@@ -564,7 +538,7 @@ static void ssp_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
/* While there is remaining to be sent (and no synchronization error has occurred) */
- sspdbg("nwords: %d\n", nwords);
+ spiinfo("nwords: %d\n", nwords);
tx.pv = txbuffer;
rx.pv = rxbuffer;
@@ -576,7 +550,7 @@ static void ssp_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
* and (3) there are more bytes to be sent.
*/
- spivdbg("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
+ spiinfo("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
while ((ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_TNF) &&
(rxpending < LPC43_SSP_FIFOSZ) && nwords)
{
@@ -599,7 +573,7 @@ static void ssp_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
/* Now, read the RX data from the RX FIFO while the RX FIFO is not empty */
- spivdbg("RX: rxpending: %d\n", rxpending);
+ spiinfo("RX: rxpending: %d\n", rxpending);
while (ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_RNE)
{
data = ssp_getreg(priv, LPC43_SSP_DR_OFFSET);
diff --git a/arch/arm/src/lpc43xx/lpc43_start.c b/arch/arm/src/lpc43xx/lpc43_start.c
index 80ffb581ee8fb978e3f69d84435504b2a4493890..e3fe5c552e8b37ff2f652875cd35027fdac61b51 100644
--- a/arch/arm/src/lpc43xx/lpc43_start.c
+++ b/arch/arm/src/lpc43xx/lpc43_start.c
@@ -87,7 +87,7 @@
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) up_lowputc(c)
#else
# define showprogress(c)
@@ -271,12 +271,12 @@ void __start(void)
/* Reset as many of the LPC43 peripherals as possible. This is necessary
* because the LPC43 does not provide any way of performing a full system
- * reset under debugger control. So, if CONFIG_DEBUG is set (indicating
+ * reset under debugger control. So, if CONFIG_DEBUG_FEATURES is set (indicating
* that a debugger is being used?), the boot logic will call this
* function on all restarts.
*/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
lpc43_softreset();
#endif
diff --git a/arch/arm/src/lpc43xx/lpc43_usb0dev.c b/arch/arm/src/lpc43xx/lpc43_usb0dev.c
index 57e3ef2c8ce7a934c7e606182a53b1ab49403721..c583dd30a1854a803bcbd1506dab1fa5121d5bb3 100644
--- a/arch/arm/src/lpc43xx/lpc43_usb0dev.c
+++ b/arch/arm/src/lpc43xx/lpc43_usb0dev.c
@@ -107,7 +107,7 @@
# define USB_FRAME_INT 0
#endif
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
# define USB_ERROR_INT USBDEV_USBINTR_UEE
#else
# define USB_ERROR_INT 0
@@ -361,7 +361,7 @@ struct lpc43_usbdev_s
/* Register operations ********************************************************/
-#if defined(CONFIG_LPC43_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_LPC43_USBDEV_REGDEBUG
static uint32_t lpc43_getreg(uint32_t addr);
static void lpc43_putreg(uint32_t val, uint32_t addr);
#else
@@ -501,7 +501,7 @@ static const struct usbdev_ops_s g_devops =
*
****************************************************************************/
-#if defined(CONFIG_LPC43_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_LPC43_USBDEV_REGDEBUG
static uint32_t lpc43_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@@ -522,7 +522,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
{
if (count == 4)
{
- lldbg("...\n");
+ usbinfo("...\n");
}
return val;
@@ -539,7 +539,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ usbinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -551,7 +551,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
/* Show the register value read */
- lldbg("%08x->%08x\n", addr, val);
+ usbinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@@ -564,12 +564,12 @@ static uint32_t lpc43_getreg(uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_LPC43_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_LPC43_USBDEV_REGDEBUG
static void lpc43_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- lldbg("%08x<-%08x\n", addr, val);
+ usbinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@@ -1228,8 +1228,8 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
priv->ep0buf_len = len;
- ullvdbg("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- ctrl->type, ctrl->req, value, index, len);
+ uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ ctrl->type, ctrl->req, value, index, len);
/* Starting a control request - update state */
@@ -1393,7 +1393,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
if (((ctrl->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
value == USB_FEATURE_TESTMODE)
{
- ullvdbg("test mode: %d\n", index);
+ uinfo("test mode: %d\n", index);
}
else if ((ctrl->type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@@ -1623,7 +1623,7 @@ static void lpc43_ep0complete(struct lpc43_usbdev_s *priv, uint8_t epphy)
break;
default:
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
DEBUGASSERT(priv->ep0state != EP0STATE_DATA_IN &&
priv->ep0state != EP0STATE_DATA_OUT &&
priv->ep0state != EP0STATE_SHORTWRITE &&
@@ -1667,7 +1667,7 @@ static void lpc43_ep0nak(struct lpc43_usbdev_s *priv, uint8_t epphy)
break;
default:
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
DEBUGASSERT(priv->ep0state != EP0STATE_WAIT_NAK_IN &&
priv->ep0state != EP0STATE_WAIT_NAK_OUT);
#endif
@@ -2056,7 +2056,7 @@ static int lpc43_epdisable(FAR struct usbdev_ep_s *ep)
FAR struct lpc43_ep_s *privep = (FAR struct lpc43_ep_s *)ep;
irqstate_t flags;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep)
{
usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDPARMS), 0);
@@ -2100,7 +2100,7 @@ static FAR struct usbdev_req_s *lpc43_epallocreq(FAR struct usbdev_ep_s *ep)
{
FAR struct lpc43_req_s *privreq;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep)
{
usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDPARMS), 0);
@@ -2132,7 +2132,7 @@ static void lpc43_epfreereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s
{
FAR struct lpc43_req_s *privreq = (FAR struct lpc43_req_s *)req;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDPARMS), 0);
@@ -2202,11 +2202,11 @@ static int lpc43_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
irqstate_t flags;
int ret = OK;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDPARMS), 0);
- ullvdbg("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+ uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
@@ -2271,7 +2271,7 @@ static int lpc43_epcancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
FAR struct lpc43_ep_s *privep = (FAR struct lpc43_ep_s *)ep;
irqstate_t flags;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDPARMS), 0);
@@ -2554,7 +2554,7 @@ static int lpc43_selfpowered(struct usbdev_s *dev, bool selfpowered)
usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!dev)
{
usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDPARMS), 0);
@@ -2790,7 +2790,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
usbtrace(TRACE_DEVREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!driver || !driver->ops->bind || !driver->ops->unbind ||
!driver->ops->disconnect || !driver->ops->setup)
{
@@ -2851,7 +2851,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
{
usbtrace(TRACE_DEVUNREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (driver != g_usbdev.driver)
{
usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDPARMS), 0);
diff --git a/arch/arm/src/lpc43xx/spifi/src/spifilib_dev_common.c b/arch/arm/src/lpc43xx/spifi/src/spifilib_dev_common.c
index 8adc8f762b30af84b5ef7cfa5691bf07b03dbe88..c3e0a7b53bb6962b59e405be075183af275a8834 100644
--- a/arch/arm/src/lpc43xx/spifi/src/spifilib_dev_common.c
+++ b/arch/arm/src/lpc43xx/spifi/src/spifilib_dev_common.c
@@ -785,50 +785,50 @@ uint32_t spifiGetSubBlockFromBlock(const SPIFI_HANDLE_T *pHandle, uint32_t block
SPIFI_ERR_T spifiProgram(const SPIFI_HANDLE_T *pHandle, uint32_t addr, const uint32_t *writeBuff, uint32_t bytes)
{
uint32_t sendBytes;
- SPIFI_ERR_T err = SPIFI_ERR_NONE;
+ SPIFI_ERR_T errcode = SPIFI_ERR_NONE;
/* Program using up to page size */
- while ((bytes > 0) && (err == SPIFI_ERR_NONE)) {
+ while ((bytes > 0) && (errcode == SPIFI_ERR_NONE)) {
sendBytes = bytes;
if (sendBytes > pHandle->pInfoData->pageSize) {
sendBytes = pHandle->pInfoData->pageSize;
}
- err = pHandle->pFamFx->pageProgram(pHandle, addr, writeBuff, sendBytes);
+ errcode = pHandle->pFamFx->pageProgram(pHandle, addr, writeBuff, sendBytes);
addr += sendBytes;
writeBuff += (sendBytes >> 2);
bytes -= sendBytes;
}
- return err;
+ return errcode;
}
/* Read the device into the passed buffer */
SPIFI_ERR_T spifiRead(const SPIFI_HANDLE_T *pHandle, uint32_t addr, uint32_t *readBuff, uint32_t bytes)
{
uint32_t readBytes;
- SPIFI_ERR_T err = SPIFI_ERR_NONE;
+ SPIFI_ERR_T errcode = SPIFI_ERR_NONE;
/* Read using up to the maximum read size */
- while ((bytes > 0) && (err == SPIFI_ERR_NONE)) {
+ while ((bytes > 0) && (errcode == SPIFI_ERR_NONE)) {
readBytes = bytes;
if (readBytes > pHandle->pInfoData->maxReadSize) {
readBytes = pHandle->pInfoData->maxReadSize;
}
- err = pHandle->pFamFx->read(pHandle, addr, readBuff, readBytes);
+ errcode = pHandle->pFamFx->read(pHandle, addr, readBuff, readBytes);
addr += readBytes;
readBuff += (readBytes / sizeof(uint32_t));
bytes -= readBytes;
}
- return err;
+ return errcode;
}
/* Erase multiple blocks */
SPIFI_ERR_T spifiErase(const SPIFI_HANDLE_T *pHandle, uint32_t firstBlock, uint32_t numBlocks)
{
- SPIFI_ERR_T err = SPIFI_ERR_NONE;
+ SPIFI_ERR_T errcode = SPIFI_ERR_NONE;
if ((firstBlock + numBlocks) > pHandle->pInfoData->numBlocks) {
return SPIFI_ERR_RANGE;
@@ -836,20 +836,20 @@ SPIFI_ERR_T spifiErase(const SPIFI_HANDLE_T *pHandle, uint32_t firstBlock, uint3
/* Only perform erase if numBlocks is != 0 */
for (; (numBlocks); ++firstBlock, --numBlocks) {
- err = pHandle->pFamFx->eraseBlock(pHandle, firstBlock);
- if (err != SPIFI_ERR_NONE) {
+ errcode = pHandle->pFamFx->eraseBlock(pHandle, firstBlock);
+ if (errcode != SPIFI_ERR_NONE) {
break;
}
}
- return err;
+ return errcode;
}
/* Erase multiple blocks by address range */
SPIFI_ERR_T spifiEraseByAddr(const SPIFI_HANDLE_T *pHandle, uint32_t firstAddr, uint32_t lastAddr)
{
uint32_t firstBlock, lastBlock;
- SPIFI_ERR_T err = SPIFI_ERR_RANGE;
+ SPIFI_ERR_T errcode = SPIFI_ERR_RANGE;
/* Get block numbers for addresses */
firstBlock = spifiGetBlockFromAddr(pHandle, firstAddr);
@@ -857,8 +857,8 @@ SPIFI_ERR_T spifiEraseByAddr(const SPIFI_HANDLE_T *pHandle, uint32_t firstAddr,
/* Limit to legal address range */
if ((firstBlock != ~0UL) && (lastBlock != ~0UL)) {
- err = spifiErase(pHandle, firstBlock, ((lastBlock - firstBlock) + 1));
+ errcode = spifiErase(pHandle, firstBlock, ((lastBlock - firstBlock) + 1));
}
- return err;
+ return errcode;
}
diff --git a/arch/arm/src/moxart/moxart_irq.c b/arch/arm/src/moxart/moxart_irq.c
index 8d2b07cc22011c5136622e354ed77009d09ff99a..31ed83c80fbd7e4f30676dde8401e6c18fee3097 100644
--- a/arch/arm/src/moxart/moxart_irq.c
+++ b/arch/arm/src/moxart/moxart_irq.c
@@ -143,18 +143,15 @@ void up_irqinitialize(void)
/* And finally, enable interrupts */
-#if 1
-#define REG(x) (*(volatile uint32_t *)(x))
- lldbg("\n=============================================================\n");
- lldbg("TM CNTL=%08x INTRS=%08x MASK=%08x LOAD=%08x COUNT=%08x M1=%08x\n",
- REG(0x98400030), REG(0x98400034), REG(0x98400038), REG(0x98400004),
- REG(0x98400000), REG(0x98400008));
- lldbg("IRQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n",
- REG(0x98800014), REG(0x98800004), REG(0x9880000C), REG(0x98800010));
- lldbg("FIQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n",
- REG(0x98800034), REG(0x98800024), REG(0x9880002C), REG(0x98800020));
- lldbg("=============================================================\n");
-#endif
+ irqinfo("TM CNTL=%08x INTRS=%08x MASK=%08x LOAD=%08x COUNT=%08x M1=%08x\n",
+ getreg32(0x98400030), getreg32(0x98400034), getreg32(0x98400038),
+ getreg32(0x98400004), getreg32(0x98400000), getreg32(0x98400008));
+ irqinfo("IRQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n",
+ getreg32(0x98800014), getreg32(0x98800004), getreg32(0x9880000C),
+ getreg32(0x98800010));
+ irqinfo("FIQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n",
+ getreg32(0x98800034), getreg32(0x98800024), getreg32(0x9880002C),
+ getreg32(0x98800020));
#ifndef CONFIG_SUPPRESS_INTERRUPTS
up_irq_restore(SVC_MODE | PSR_F_BIT);
diff --git a/arch/arm/src/nuc1xx/Make.defs b/arch/arm/src/nuc1xx/Make.defs
index 3a9f06519125e649d5395e84056e24f1ec2bd0e6..7a5a00e85a2fe4961dacfb800b81548789e42610 100644
--- a/arch/arm/src/nuc1xx/Make.defs
+++ b/arch/arm/src/nuc1xx/Make.defs
@@ -65,7 +65,7 @@ else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
-ifeq ($(CONFIG_DEBUG),y)
+ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += up_dumpnvic.c
endif
@@ -81,6 +81,6 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += nuc_userspace.c
endif
-ifeq ($(CONFIG_DEBUG),y)
+ifeq ($(CONFIG_DEBUG_FEATURES),y)
CHIP_CSRCS += nuc_dumpgpio.c
endif
diff --git a/arch/arm/src/nuc1xx/nuc_dumpgpio.c b/arch/arm/src/nuc1xx/nuc_dumpgpio.c
index 480bb4f588d3d96e51bbf284e81488dda38ff8ad..82db651a69b96c1f4a8a3f09d6bcbd4fbe02c8e3 100644
--- a/arch/arm/src/nuc1xx/nuc_dumpgpio.c
+++ b/arch/arm/src/nuc1xx/nuc_dumpgpio.c
@@ -49,14 +49,13 @@
#include "chip.h"
#include "nuc_gpio.h"
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_GPIO_INFO
/****************************************************************************
* Private Data
****************************************************************************/
/* Port letters for prettier debug output */
-#ifdef CONFIG_DEBUG
static const char g_portchar[NUC_GPIO_NPORTS] =
{
#if NUC_GPIO_NPORTS > 9
@@ -83,15 +82,6 @@ static const char g_portchar[NUC_GPIO_NPORTS] =
# error "Bad number of GPIOs"
#endif
};
-#endif
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
/****************************************************************************
* Public Functions
@@ -124,22 +114,22 @@ void nuc_dumpgpio(gpio_cfgset_t pinset, const char *msg)
flags = enter_critical_section();
- lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
- g_portchar[port], pinset, base, msg);
- lldbg(" PMD: %08x OFFD: %08x DOUT: %08x DMASK: %08x\n",
- getreg32(base + NUC_GPIO_PMD_OFFSET),
- getreg32(base + NUC_GPIO_OFFD_OFFSET),
- getreg32(base + NUC_GPIO_DOUT_OFFSET),
- getreg32(base + NUC_GPIO_DMASK_OFFSET));
- lldbg(" PIN: %08x DBEN: %08x IMD: %08x IEN: %08x\n",
- getreg32(base + NUC_GPIO_PIN_OFFSET),
- getreg32(base + NUC_GPIO_DBEN_OFFSET),
- getreg32(base + NUC_GPIO_IMD_OFFSET),
- getreg32(base + NUC_GPIO_IEN_OFFSET));
- lldbg(" ISRC: %08x\n",
- getreg32(base + NUC_GPIO_ISRC_OFFSET));
+ gpioinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
+ g_portchar[port], pinset, base, msg);
+ gpioinfo(" PMD: %08x OFFD: %08x DOUT: %08x DMASK: %08x\n",
+ getreg32(base + NUC_GPIO_PMD_OFFSET),
+ getreg32(base + NUC_GPIO_OFFD_OFFSET),
+ getreg32(base + NUC_GPIO_DOUT_OFFSET),
+ getreg32(base + NUC_GPIO_DMASK_OFFSET));
+ gpioinfo(" PIN: %08x DBEN: %08x IMD: %08x IEN: %08x\n",
+ getreg32(base + NUC_GPIO_PIN_OFFSET),
+ getreg32(base + NUC_GPIO_DBEN_OFFSET),
+ getreg32(base + NUC_GPIO_IMD_OFFSET),
+ getreg32(base + NUC_GPIO_IEN_OFFSET));
+ gpioinfo(" ISRC: %08x\n",
+ getreg32(base + NUC_GPIO_ISRC_OFFSET));
leave_critical_section(flags);
}
-#endif /* CONFIG_DEBUG */
+#endif /* CONFIG_DEBUG_GPIO_INFO */
diff --git a/arch/arm/src/nuc1xx/nuc_gpio.h b/arch/arm/src/nuc1xx/nuc_gpio.h
index 52e9dd209506eb1c68801ffdd5a13b21ef635864..1fca1dc0e50933c0ae6f6a1142c67d8f7f6cac5a 100644
--- a/arch/arm/src/nuc1xx/nuc_gpio.h
+++ b/arch/arm/src/nuc1xx/nuc_gpio.h
@@ -245,7 +245,7 @@ bool nuc_gpioread(gpio_cfgset_t pinset);
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
void nuc_dumpgpio(gpio_cfgset_t pinset, const char *msg);
#else
# define nuc_dumpgpio(p,m)
diff --git a/arch/arm/src/nuc1xx/nuc_idle.c b/arch/arm/src/nuc1xx/nuc_idle.c
index 9dd225313f948d8c90e4e62fb2466fb4f373d43c..791ce2f09188b40822f8a32d8da2b619d9476242 100644
--- a/arch/arm/src/nuc1xx/nuc_idle.c
+++ b/arch/arm/src/nuc1xx/nuc_idle.c
@@ -99,7 +99,7 @@ static void up_idlepm(void)
/* Perform board-specific, state-dependent logic here */
- llvdbg("newstate= %d oldstate=%d\n", newstate, oldstate);
+ _info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
diff --git a/arch/arm/src/nuc1xx/nuc_irq.c b/arch/arm/src/nuc1xx/nuc_irq.c
index 0bdb86a8ee91758b9abe40595dc4197cf239cce5..66f6d78044d7993b62f0dc63cfd566a17ca2d015 100644
--- a/arch/arm/src/nuc1xx/nuc_irq.c
+++ b/arch/arm/src/nuc1xx/nuc_irq.c
@@ -90,34 +90,34 @@ volatile uint32_t *g_current_regs[1];
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_IRQ)
+#if defined(CONFIG_DEBUG_IRQ_INFO)
static void nuc_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
- lldbg("NVIC (%s, irq=%d):\n", msg, irq);
- lldbg(" ISER: %08x ICER: %08x\n",
- getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
- lldbg(" ISPR: %08x ICPR: %08x\n",
- getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
- lldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
- getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
- getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
- getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
-
- lldbg("SYSCON:\n");
- lldbg(" CPUID: %08x\n",
- getreg32(ARMV6M_SYSCON_CPUID));
- lldbg(" ICSR: %08x AIRCR: %08x\n",
- getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
- lldbg(" SCR: %08x CCR: %08x\n",
- getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
- lldbg(" SHPR2: %08x SHPR3: %08x\n",
- getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
+ irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
+ irqinfo(" ISER: %08x ICER: %08x\n",
+ getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
+ irqinfo(" ISPR: %08x ICPR: %08x\n",
+ getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
+ irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
+ getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
+ getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
+ getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
+
+ irqinfo("SYSCON:\n");
+ irqinfo(" CPUID: %08x\n",
+ getreg32(ARMV6M_SYSCON_CPUID));
+ irqinfo(" ICSR: %08x AIRCR: %08x\n",
+ getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
+ irqinfo(" SCR: %08x CCR: %08x\n",
+ getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
+ irqinfo(" SHPR2: %08x SHPR3: %08x\n",
+ getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
}
@@ -137,11 +137,11 @@ static void nuc_dumpnvic(const char *msg, int irq)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
static int nuc_nmi(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! NMI received\n");
+ _err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
@@ -149,7 +149,7 @@ static int nuc_nmi(int irq, FAR void *context)
static int nuc_pendsv(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! PendSV received\n");
+ _err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
@@ -157,7 +157,7 @@ static int nuc_pendsv(int irq, FAR void *context)
static int nuc_reserved(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Reserved interrupt\n");
+ _err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
@@ -236,7 +236,7 @@ void up_irqinitialize(void)
/* Attach all other processor exceptions (except reset and sys tick) */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
irq_attach(NUC_IRQ_NMI, nuc_nmi);
irq_attach(NUC_IRQ_PENDSV, nuc_pendsv);
irq_attach(NUC_IRQ_RESERVED, nuc_reserved);
diff --git a/arch/arm/src/nuc1xx/nuc_start.c b/arch/arm/src/nuc1xx/nuc_start.c
index 3cbb5becdeefd337815e90a32aef0a00dea9d778..80c01077ae817643421d210c4bab4ba6e52c60ca 100644
--- a/arch/arm/src/nuc1xx/nuc_start.c
+++ b/arch/arm/src/nuc1xx/nuc_start.c
@@ -92,7 +92,7 @@ const uint32_t g_idle_topstack = IDLE_STACK;
*
****************************************************************************/
-#if defined(CONFIG_DEBUG) && defined(HAVE_SERIAL_CONSOLE)
+#if defined(CONFIG_DEBUG_FEATURES) && defined(HAVE_SERIAL_CONSOLE)
# define showprogress(c) nuc_lowputc((uint32_t)c)
#else
# define showprogress(c)
diff --git a/arch/arm/src/sam34/Kconfig b/arch/arm/src/sam34/Kconfig
index b704da5674f8f1729b3fb05d6d2ef86d627661c3..8e764dff40ee0fef7a3d407386e21cb0c4f6febd 100644
--- a/arch/arm/src/sam34/Kconfig
+++ b/arch/arm/src/sam34/Kconfig
@@ -1118,7 +1118,7 @@ config SAM34_SPI_DMATHRESHOLD
config SAM34_SPI_DMADEBUG
bool "SPI DMA transfer debug"
- depends on SAM34_SPI_DMA && DEBUG && DEBUG_DMA
+ depends on SAM34_SPI_DMA && DEBUG_FEATURES && DEBUG_DMA
default n
---help---
Enable special debug instrumentation analyze SPI DMA data transfers.
@@ -1128,11 +1128,11 @@ config SAM34_SPI_DMADEBUG
config SAM34_SPI_REGDEBUG
bool "SPI Register level debug"
- depends on DEBUG
+ depends on DEBUG_SPI_INFO
default n
---help---
Output detailed register-level SPI device debug information.
- Requires also DEBUG.
+ Requires also CONFIG_SPI_INFO.
endmenu # AT91SAM3/4 SPI device driver options
endif # SAM34_SPI0 || SAM34_SPI1
@@ -1336,9 +1336,9 @@ config SAM34_EMAC_PHYSR_100FD
config SAM34_EMAC_REGDEBUG
bool "Register-Level Debug"
default n
- depends on DEBUG
+ depends on DEBUG_NET_INFO
---help---
- Enable very low-level register access debug. Depends on DEBUG.
+ Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_INFO.
config SAM34_EMAC_ISETH0
bool
@@ -1369,7 +1369,7 @@ config SAM34_HSMCI_WRPROOF
config SAM34_HSMCI_XFRDEBUG
bool "HSMCI transfer debug"
- depends on DEBUG_FS && DEBUG_VERBOSE
+ depends on DEBUG_FS_INFO
default n
---help---
Enable special debug instrumentation analyze HSMCI data transfers.
@@ -1377,11 +1377,11 @@ config SAM34_HSMCI_XFRDEBUG
registers at key points in the data transfer and then dumps all of
the registers at the end of the transfer. If DEBUG_DMA is also
enabled, then DMA register will be collected as well. Requires also
- DEBUG_FS and DEBUG_VERBOSE.
+ DEBUG_FS and CONFIG_DEBUG_INFO.
config SAM34_HSMCI_CMDDEBUG
bool "HSMCI command debug"
- depends on DEBUG_FS && DEBUG_VERBOSE
+ depends on DEBUG_FS_INFO
default n
---help---
Enable special debug instrumentation analyze HSMCI commands. This
@@ -1389,7 +1389,7 @@ config SAM34_HSMCI_CMDDEBUG
key points in the data transfer and then dumps all of the registers
at the end of the transfer. If DEBUG_DMA is also enabled, then DMA
register will be collected as well. Requires also DEBUG_FS and
- DEBUG_VERBOSE.
+ CONFIG_DEBUG_INFO.
endmenu # HSMCI device driver options
endif # SAM34_HSMCI
@@ -1400,7 +1400,7 @@ menu "AT91SAM3/4 USB Full Speed Device Controller driver (DCD) options"
config SAM34_UDP_REGDEBUG
bool "Enable low-level UDP register debug"
default n
- depends on DEBUG
+ depends on DEBUG_USB_INFO
endmenu # USB Full Speed Device Controller driver (DCD) options
@@ -1415,7 +1415,7 @@ menu "AT91SAM3/4 Timer/Counter options"
config SAM34_TC_REGDEBUG
bool "Enable low-level timer/counter register debug"
default n
- depends on DEBUG
+ depends on DEBUG_TIMER_INFO
endmenu # USB Full Speed Device Controller driver (DCD) options
diff --git a/arch/arm/src/sam34/chip/sam_afec.h b/arch/arm/src/sam34/chip/sam_afec.h
index 9e779a1e4c16f5ce9dc1f4d12e39cc0eeb51cd81..d5a8be44ab94786cc901f8e7b7fa664d9bf6e830 100644
--- a/arch/arm/src/sam34/chip/sam_afec.h
+++ b/arch/arm/src/sam34/chip/sam_afec.h
@@ -205,57 +205,57 @@
/* Extended Mode Register */
-#define AFEC_EMR_CMPMODE_SHIFT (0) /* Bit 0-1: Comparison Mode */
-#define AFEC_EMR_CMPMODE_MASK (3 << AFEC_EMR_CMPMODE_SHIFT)
-# define AFEC_EMR_CMPMODE_LOW (0 << AFEC_EMR_CMPMODE_SHIFT) /* Event when lower than low window threshold */
-# define AFEC_EMR_CMPMODE_HIGH (1 << AFEC_EMR_CMPMODE_SHIFT) /* Event when higher than high window threshold */
-# define AFEC_EMR_CMPMODE_IN (2 << AFEC_EMR_CMPMODE_SHIFT) /* Event when in comparison window */
-# define AFEC_EMR_CMPMODE_OUT (3 << AFEC_EMR_CMPMODE_SHIFT) /* Event when out of comparison window */
-#define AFEC_EMR_CMPSEL_SHIFT (4) /* Bit 4-7: Comparison Selected Channel */
-#define AFEC_EMR_CMPSEL_MASK (15 << AFEC_EMR_CMPSEL_SHIFT)
-# define AFEC_EMR_CMPSEL(n) ((uint32_t)(n) << AFEC_EMR_CMPSEL_SHIFT)
-#define AFEC_EMR_CMPALL (1 << 9) /* Bit 9: Compare All Channels */
-#define AFEC_EMR_CMPFILTER_SHIFT (12) /* Bits 12-13: Compare Event Filtering */
-#define AFEC_EMR_CMPFILTER_MASK (3 << AFEC_EMR_CMPFILTER_SHIFT)
-# define AFEC_EMR_CMPFILTER(n) ((uint32_t)(n) << AFEC_EMR_CMPFILTER_SHIFT)
-#define AFEC_EMR_RES_SHIFT (16) /* Bits 16-18: Resolution */
-#define AFEC_EMR_RES_MASK (7 << AFEC_EMR_RES_SHIFT)
-# define AFEC_EMR_RES_NOAVG (0 << AFEC_EMR_RES_SHIFT) /* 12-bit resolution, AFEC sample rate is maximum (no averaging) */
-# define AFEC_EMR_RES_LOWRES (1 << AFEC_EMR_RES_SHIFT) /* 10-bit resolution, AFEC sample rate is maximum (no averaging) */
-# define AFEC_EMR_RES_OSR4 (2 << AFEC_EMR_RES_SHIFT) /* 13-bit resolution, AFEC sample rate divided by 4 (averaging) */
-# define AFEC_EMR_RES_OSR16 (3 << AFEC_EMR_RES_SHIFT) /* 14-bit resolution, AFEC sample rate divided by 16 (averaging) */
-# define AFEC_EMR_RES_OSR64 (4 << AFEC_EMR_RES_SHIFT) /* 15-bit resolution, AFEC sample rate divided by 64 (averaging) */
-# define AFEC_EMR_RES_OSR256 (5 << AFEC_EMR_RES_SHIFT) /* 16-bit resolution, AFEC sample rate divided by 256 (averaging) */
-#define AFEC_EMR_TAG (1 << 24) /* Bit 24: TAG of the AFEC_LDCR register */
-#define AFEC_EMR_STM (1 << 25) /* Bit 25: Single Trigger Mode */
+#define AFEC_EMR_CMPMODE_SHIFT (0) /* Bit 0-1: Comparison Mode */
+#define AFEC_EMR_CMPMODE_MASK (3 << AFEC_EMR_CMPMODE_SHIFT)
+# define AFEC_EMR_CMPMODE_LOW (0 << AFEC_EMR_CMPMODE_SHIFT) /* Event when lower than low window threshold */
+# define AFEC_EMR_CMPMODE_HIGH (1 << AFEC_EMR_CMPMODE_SHIFT) /* Event when higher than high window threshold */
+# define AFEC_EMR_CMPMODE_IN (2 << AFEC_EMR_CMPMODE_SHIFT) /* Event when in comparison window */
+# define AFEC_EMR_CMPMODE_OUT (3 << AFEC_EMR_CMPMODE_SHIFT) /* Event when out of comparison window */
+#define AFEC_EMR_CMPSEL_SHIFT (3) /* Bit 3-7: Comparison Selected Channel */
+#define AFEC_EMR_CMPSEL_MASK (31 << AFEC_EMR_CMPSEL_SHIFT)
+# define AFEC_EMR_CMPSEL(n) ((uint32_t)(n) << AFEC_EMR_CMPSEL_SHIFT)
+#define AFEC_EMR_CMPALL (1 << 9) /* Bit 9: Compare All Channels */
+#define AFEC_EMR_CMPFILTER_SHIFT (12) /* Bits 12-13: Compare Event Filtering */
+#define AFEC_EMR_CMPFILTER_MASK (3 << AFEC_EMR_CMPFILTER_SHIFT)
+# define AFEC_EMR_CMPFILTER(n) ((uint32_t)(n) << AFEC_EMR_CMPFILTER_SHIFT)
+#define AFEC_EMR_RES_SHIFT (16) /* Bits 16-18: Resolution */
+#define AFEC_EMR_RES_MASK (7 << AFEC_EMR_RES_SHIFT)
+# define AFEC_EMR_RES_NOAVG (0 << AFEC_EMR_RES_SHIFT) /* 12-bit resolution, AFEC sample rate is maximum (no averaging) */
+# define AFEC_EMR_RES_LOWRES (1 << AFEC_EMR_RES_SHIFT) /* 10-bit resolution, AFEC sample rate is maximum (no averaging) */
+# define AFEC_EMR_RES_OSR4 (2 << AFEC_EMR_RES_SHIFT) /* 13-bit resolution, AFEC sample rate divided by 4 (averaging) */
+# define AFEC_EMR_RES_OSR16 (3 << AFEC_EMR_RES_SHIFT) /* 14-bit resolution, AFEC sample rate divided by 16 (averaging) */
+# define AFEC_EMR_RES_OSR64 (4 << AFEC_EMR_RES_SHIFT) /* 15-bit resolution, AFEC sample rate divided by 64 (averaging) */
+# define AFEC_EMR_RES_OSR256 (5 << AFEC_EMR_RES_SHIFT) /* 16-bit resolution, AFEC sample rate divided by 256 (averaging) */
+#define AFEC_EMR_TAG (1 << 24) /* Bit 24: TAG of the AFEC_LDCR register */
+#define AFEC_EMR_STM (1 << 25) /* Bit 25: Single Trigger Mode */
/* Channel Sequence 1 Register */
#define AFEC_SEQ1R_USCH_SHIFT(n) ((n) << 2) /* n=0..7 */
#define AFEC_SEQ1R_USCH_MASK(n) (15 << AFEC_SEQ1R_USCH_SHIFT(n))
# define AFEC_SEQ1R_USCH(n,v) ((uint32_t)(v) << AFEC_SEQ1R_USCH_SHIFT(n))
-#define AFEC_SEQ1R_USCH0_SHIFT (0) /* Bits 0-3: User sequence number 0 */
+#define AFEC_SEQ1R_USCH0_SHIFT (0) /* Bits 0-3: User sequence number 0 */
#define AFEC_SEQ1R_USCH0_MASK (15 << AFEC_SEQ1R_USCH0_SHIFT)
# define AFEC_SEQ1R_USCH0(v) ((uint32_t)(v) << AFEC_SEQ1R_USCH0_SHIFT)
-#define AFEC_SEQ1R_USCH1_SHIFT (4) /* Bits 4-7: User sequence number 1 */
+#define AFEC_SEQ1R_USCH1_SHIFT (4) /* Bits 4-7: User sequence number 1 */
#define AFEC_SEQ1R_USCH1_MASK (15 << AFEC_SEQ1R_USCH1_SHIFT)
# define AFEC_SEQ1R_USCH1(v) ((uint32_t)(v) << AFEC_SEQ1R_USCH1_SHIFT)
-#define AFEC_SEQ1R_USCH2_SHIFT (8) /* Bits 8-11: User sequence number 2 */
+#define AFEC_SEQ1R_USCH2_SHIFT (8) /* Bits 8-11: User sequence number 2 */
#define AFEC_SEQ1R_USCH2_MASK (15 << AFEC_SEQ1R_USCH2_SHIFT)
# define AFEC_SEQ1R_USCH2(v) ((uint32_t)(v) << AFEC_SEQ1R_USCH2_SHIFT)
-#define AFEC_SEQ1R_USCH3_SHIFT (12) /* Bits 12-15: User sequence number 3 */
+#define AFEC_SEQ1R_USCH3_SHIFT (12) /* Bits 12-15: User sequence number 3 */
#define AFEC_SEQ1R_USCH3_MASK (15 << AFEC_SEQ1R_USCH3_SHIFT)
# define AFEC_SEQ1R_USCH3(v) ((uint32_t)(v) << AFEC_SEQ1R_USCH3_SHIFT)
-#define AFEC_SEQ1R_USCH4_SHIFT (16) /* Bits 16-19: User sequence number 4 */
+#define AFEC_SEQ1R_USCH4_SHIFT (16) /* Bits 16-19: User sequence number 4 */
#define AFEC_SEQ1R_USCH4_MASK (15 << AFEC_SEQ1R_USCH4_SHIFT)
# define AFEC_SEQ1R_USCH4(v) ((uint32_t)(v) << AFEC_SEQ1R_USCH4_SHIFT)
-#define AFEC_SEQ1R_USCH5_SHIFT (20) /* Bits 20-23: User sequence number 5 */
+#define AFEC_SEQ1R_USCH5_SHIFT (20) /* Bits 20-23: User sequence number 5 */
#define AFEC_SEQ1R_USCH5_MASK (15 << AFEC_SEQ1R_USCH5_SHIFT)
# define AFEC_SEQ1R_USCH5(v) ((uint32_t)(v) << AFEC_SEQ1R_USCH5_SHIFT)
-#define AFEC_SEQ1R_USCH6_SHIFT (24) /* Bits 24-27: User sequence number 6 */
+#define AFEC_SEQ1R_USCH6_SHIFT (24) /* Bits 24-27: User sequence number 6 */
#define AFEC_SEQ1R_USCH6_MASK (15 << AFEC_SEQ1R_USCH6_SHIFT)
# define AFEC_SEQ1R_USCH6(v) ((uint32_t)(v) << AFEC_SEQ1R_USCH6_SHIFT)
-#define AFEC_SEQ1R_USCH7_SHIFT (28) /* Bits 28-31: User sequence number 7 */
+#define AFEC_SEQ1R_USCH7_SHIFT (28) /* Bits 28-31: User sequence number 7 */
#define AFEC_SEQ1R_USCH7_MASK (15 << AFEC_SEQ1R_USCH7_SHIFT)
# define AFEC_SEQ1R_USCH7(v) ((uint32_t)(v) << AFEC_SEQ1R_USCH7_SHIFT)
@@ -264,28 +264,28 @@
#define AFEC_SEQ2R_USCH_SHIFT(n) (((n)-8) << 2) /* n=8..15 */
#define AFEC_SEQ2R_USCH_MASK(n) (15 << AFEC_SEQ2R_USCH_SHIFT(n))
# define AFEC_SEQ2R_USCH(n,v) ((uint32_t)(v) << AFEC_SEQ2R_USCH_SHIFT(n))
-#define AFEC_SEQ2R_USCH8_SHIFT (0) /* Bits 0-3: User sequence number 8 */
+#define AFEC_SEQ2R_USCH8_SHIFT (0) /* Bits 0-3: User sequence number 8 */
#define AFEC_SEQ2R_USCH8_MASK (15 << AFEC_SEQ2R_USCH8_SHIFT)
# define AFEC_SEQ2R_USCH8(v) ((uint32_t)(v) << AFEC_SEQ2R_USCH8_SHIFT)
-#define AFEC_SEQ2R_USCH9_SHIFT (4) /* Bits 4-7: User sequence number 9 */
+#define AFEC_SEQ2R_USCH9_SHIFT (4) /* Bits 4-7: User sequence number 9 */
#define AFEC_SEQ2R_USCH9_MASK (15 << AFEC_SEQ2R_USCH9_SHIFT)
# define AFEC_SEQ2R_USCH9(v) ((uint32_t)(v) << AFEC_SEQ2R_USCH9_SHIFT)
-#define AFEC_SEQ2R_USCH10_SHIFT (8) /* Bits 8-11: User sequence number 10 */
+#define AFEC_SEQ2R_USCH10_SHIFT (8) /* Bits 8-11: User sequence number 10 */
#define AFEC_SEQ2R_USCH10_MASK (15 << AFEC_SEQ2R_USCH10_SHIFT)
# define AFEC_SEQ2R_USCH10(v) ((uint32_t)(v) << AFEC_SEQ2R_USCH10_SHIFT)
-#define AFEC_SEQ2R_USCH11_SHIFT (12) /* Bits 12-15: User sequence number 11 */
+#define AFEC_SEQ2R_USCH11_SHIFT (12) /* Bits 12-15: User sequence number 11 */
#define AFEC_SEQ2R_USCH11_MASK (15 << AFEC_SEQ2R_USCH11_SHIFT)
# define AFEC_SEQ2R_USCH11(v) ((uint32_t)(v) << AFEC_SEQ2R_USCH11_SHIFT)
-#define AFEC_SEQ2R_USCH12_SHIFT (16) /* Bits 16-19: User sequence number 12 */
+#define AFEC_SEQ2R_USCH12_SHIFT (16) /* Bits 16-19: User sequence number 12 */
#define AFEC_SEQ2R_USCH12_MASK (15 << AFEC_SEQ2R_USCH12_SHIFT)
# define AFEC_SEQ2R_USCH12(v) ((uint32_t)(v) << AFEC_SEQ2R_USCH12_SHIFT)
-#define AFEC_SEQ2R_USCH13_SHIFT (20) /* Bits 20-23: User sequence number 13 */
+#define AFEC_SEQ2R_USCH13_SHIFT (20) /* Bits 20-23: User sequence number 13 */
#define AFEC_SEQ2R_USCH13_MASK (15 << AFEC_SEQ2R_USCH13_SHIFT)
# define AFEC_SEQ2R_USCH13(v) ((uint32_t)(v) << AFEC_SEQ2R_USCH13_SHIFT)
-#define AFEC_SEQ2R_USCH14_SHIFT (24) /* Bits 24-27: User sequence number 14 */
+#define AFEC_SEQ2R_USCH14_SHIFT (24) /* Bits 24-27: User sequence number 14 */
#define AFEC_SEQ2R_USCH14_MASK (15 << AFEC_SEQ2R_USCH14_SHIFT)
# define AFEC_SEQ2R_USCH14(v) ((uint32_t)(v) << AFEC_SEQ2R_USCH14_SHIFT)
-#define AFEC_SEQ2R_USCH15_SHIFT (28) /* Bits 28-31: User sequence number 15 */
+#define AFEC_SEQ2R_USCH15_SHIFT (28) /* Bits 28-31: User sequence number 15 */
#define AFEC_SEQ2R_USCH15_MASK (15 << AFEC_SEQ2R_USCH15_SHIFT)
# define AFEC_SEQ2R_USCH15(v) ((uint32_t)(v) << AFEC_SEQ2R_USCH15_SHIFT)
@@ -375,59 +375,59 @@
# define AFEC_CWR_LOWTHRES(n) ((uint32_t)(n) << AFEC_CWR_LOWTHRES_SHIFT)
#define AFEC_CWR_HIGHTHRES_SHIFT (16) /* Bits 16-27: High Threshold */
#define AFEC_CWR_HIGHTHRES_MASK (0xfff << AFEC_CWR_LOWTHRES_SHIFT)
-# define AFEC_CWR_HIGHTHRES(n)K ((uint32_t)(n) << AFEC_CWR_LOWTHRES_SHIFT)
+# define AFEC_CWR_HIGHTHRES(n) ((uint32_t)(n) << AFEC_CWR_LOWTHRES_SHIFT)
/* Channel Gain Register */
#define AFEC_CGR_GAIN_SHIFT(n) ((n) << 1) /* n=0..15 */
#define AFEC_CGR_GAIN_MASK(n) (3 << AFEC_CGR_GAIN_SHIFT(n))
# define AFEC_CGR_GAIN(n,v) ((uint32_t)(v) << AFEC_CGR_GAIN_SHIFT(n))
-#define AFEC_CGR_GAIN0_SHIFT (0) /* Bits 0-1: Gain for channel 0 */
+#define AFEC_CGR_GAIN0_SHIFT (0) /* Bits 0-1: Gain for channel 0 */
#define AFEC_CGR_GAIN0_MASK (3 << AFEC_CGR_GAIN0_SHIFT)
# define AFEC_CGR_GAIN0(v) ((uint32_t)(v) << AFEC_CGR_GAIN0_SHIFT)
-#define AFEC_CGR_GAIN1_SHIFT (2) /* Bits 2-3: Gain for channel 1 */
+#define AFEC_CGR_GAIN1_SHIFT (2) /* Bits 2-3: Gain for channel 1 */
#define AFEC_CGR_GAIN1_MASK (3 << AFEC_CGR_GAIN1_SHIFT)
# define AFEC_CGR_GAIN1(v) ((uint32_t)(v) << AFEC_CGR_GAIN1_SHIFT)
-#define AFEC_CGR_GAIN2_SHIFT (4) /* Bits 4-5: Gain for channel 2 */
+#define AFEC_CGR_GAIN2_SHIFT (4) /* Bits 4-5: Gain for channel 2 */
#define AFEC_CGR_GAIN2_MASK (3 << AFEC_CGR_GAIN2_SHIFT)
# define AFEC_CGR_GAIN2(v) ((uint32_t)(v) << AFEC_CGR_GAIN2_SHIFT)
-#define AFEC_CGR_GAIN3_SHIFT (6) /* Bits 6-7: Gain for channel 3 */
+#define AFEC_CGR_GAIN3_SHIFT (6) /* Bits 6-7: Gain for channel 3 */
#define AFEC_CGR_GAIN3_MASK (3 << AFEC_CGR_GAIN3_SHIFT)
# define AFEC_CGR_GAIN3(v) ((uint32_t)(v) << AFEC_CGR_GAIN3_SHIFT)
-#define AFEC_CGR_GAIN4_SHIFT (8) /* Bits 8-9: Gain for channel 4 */
+#define AFEC_CGR_GAIN4_SHIFT (8) /* Bits 8-9: Gain for channel 4 */
#define AFEC_CGR_GAIN4_MASK (3 << AFEC_CGR_GAIN4_SHIFT)
# define AFEC_CGR_GAIN4(v) ((uint32_t)(v) << AFEC_CGR_GAIN4_SHIFT)
-#define AFEC_CGR_GAIN5_SHIFT (10) /* Bits 10-11: Gain for channel 5 */
+#define AFEC_CGR_GAIN5_SHIFT (10) /* Bits 10-11: Gain for channel 5 */
#define AFEC_CGR_GAIN5_MASK (3 << AFEC_CGR_GAIN5_SHIFT)
# define AFEC_CGR_GAIN5(v) ((uint32_t)(v) << AFEC_CGR_GAIN5_SHIFT)
-#define AFEC_CGR_GAIN6_SHIFT (12) /* Bits 12-13: Gain for channel 6 */
+#define AFEC_CGR_GAIN6_SHIFT (12) /* Bits 12-13: Gain for channel 6 */
#define AFEC_CGR_GAIN6_MASK (3 << AFEC_CGR_GAIN6_SHIFT)
# define AFEC_CGR_GAIN6(v) ((uint32_t)(v) << AFEC_CGR_GAIN6_SHIFT)
-#define AFEC_CGR_GAIN7_SHIFT (14) /* Bits 14-15: Gain for channel 7 */
+#define AFEC_CGR_GAIN7_SHIFT (14) /* Bits 14-15: Gain for channel 7 */
#define AFEC_CGR_GAIN7_MASK (3 << AFEC_CGR_GAIN7_SHIFT)
# define AFEC_CGR_GAIN7(v) ((uint32_t)(v) << AFEC_CGR_GAIN7_SHIFT)
-#define AFEC_CGR_GAIN8_SHIFT (16) /* Bits 16-17: Gain for channel 8 */
+#define AFEC_CGR_GAIN8_SHIFT (16) /* Bits 16-17: Gain for channel 8 */
#define AFEC_CGR_GAIN8_MASK (3 << AFEC_CGR_GAIN8_SHIFT)
# define AFEC_CGR_GAIN8(v) ((uint32_t)(v) << AFEC_CGR_GAIN8_SHIFT)
-#define AFEC_CGR_GAIN9_SHIFT (18) /* Bits 18-19: Gain for channel 9 */
+#define AFEC_CGR_GAIN9_SHIFT (18) /* Bits 18-19: Gain for channel 9 */
#define AFEC_CGR_GAIN9_MASK (3 << AFEC_CGR_GAIN9_SHIFT)
# define AFEC_CGR_GAIN9(v) ((uint32_t)(v) << AFEC_CGR_GAIN9_SHIFT)
-#define AFEC_CGR_GAIN10_SHIFT (20) /* Bits 20-21: Gain for channel 10 */
+#define AFEC_CGR_GAIN10_SHIFT (20) /* Bits 20-21: Gain for channel 10 */
#define AFEC_CGR_GAIN10_MASK (3 << AFEC_CGR_GAIN10_SHIFT)
# define AFEC_CGR_GAIN10(v) ((uint32_t)(v) << AFEC_CGR_GAIN10_SHIFT)
-#define AFEC_CGR_GAIN11_SHIFT (22) /* Bits 22-23: Gain for channel 11 */
+#define AFEC_CGR_GAIN11_SHIFT (22) /* Bits 22-23: Gain for channel 11 */
#define AFEC_CGR_GAIN11_MASK (3 << AFEC_CGR_GAIN11_SHIFT)
# define AFEC_CGR_GAIN11(v) ((uint32_t)(v) << AFEC_CGR_GAIN11_SHIFT)
-#define AFEC_CGR_GAIN12_SHIFT (24) /* Bits 24-25: Gain for channel 12 */
+#define AFEC_CGR_GAIN12_SHIFT (24) /* Bits 24-25: Gain for channel 12 */
#define AFEC_CGR_GAIN12_MASK (3 << AFEC_CGR_GAIN12_SHIFT)
# define AFEC_CGR_GAIN12(v) ((uint32_t)(v) << AFEC_CGR_GAIN12_SHIFT)
-#define AFEC_CGR_GAIN13_SHIFT (26) /* Bits 26-27: Gain for channel 13 */
+#define AFEC_CGR_GAIN13_SHIFT (26) /* Bits 26-27: Gain for channel 13 */
#define AFEC_CGR_GAIN13_MASK (3 << AFEC_CGR_GAIN13_SHIFT)
# define AFEC_CGR_GAIN13(v) ((uint32_t)(v) << AFEC_CGR_GAIN13_SHIFT)
-#define AFEC_CGR_GAIN14_SHIFT (28) /* Bits 28-29: Gain for channel 14 */
+#define AFEC_CGR_GAIN14_SHIFT (28) /* Bits 28-29: Gain for channel 14 */
#define AFEC_CGR_GAIN14_MASK (3 << AFEC_CGR_GAIN14_SHIFT)
# define AFEC_CGR_GAIN14(v) ((uint32_t)(v) << AFEC_CGR_GAIN14_SHIFT)
-#define AFEC_CGR_GAIN15_SHIFT (30) /* Bits 30-31: Gain for channel 15 */
+#define AFEC_CGR_GAIN15_SHIFT (30) /* Bits 30-31: Gain for channel 15 */
#define AFEC_CGR_GAIN15_MASK (3 << AFEC_CGR_GAIN15_SHIFT)
# define AFEC_CGR_GAIN15(v) ((uint32_t)(v) << AFEC_CGR_GAIN15_SHIFT)
@@ -487,8 +487,8 @@
/* Temperature Sensor Mode Register */
-#define AFEC_TEMPMR_RTCT (1 << 0) /* Bit 0: Temperature Sensor RTC Trigger mode */
-#define AFEC_TEMPMR_TEMPCMPMOD_SHIFT (4) /* Bits 4-5: Temperature Comparison Mode */
+#define AFEC_TEMPMR_RTCT (1 << 0) /* Bit 0: Temperature Sensor RTC Trigger mode */
+#define AFEC_TEMPMR_TEMPCMPMOD_SHIFT (4) /* Bits 4-5: Temperature Comparison Mode */
#define AFEC_TEMPMR_TEMPCMPMOD_MASK (3 << AFEC_TEMPMR_TEMPCMPMOD_SHIFT)
# define AFEC_TEMPMR_TEMPCMPMOD_LOW (0 << AFEC_TEMPMR_TEMPCMPMOD_SHIFT) /* Event when data is lower than low threshold */
# define AFEC_TEMPMR_TEMPCMPMOD_HIGH (1 << AFEC_TEMPMR_TEMPCMPMOD_SHIFT) /* Event when data is higher than high threshold */
diff --git a/arch/arm/src/sam34/chip/sam_dacc.h b/arch/arm/src/sam34/chip/sam_dacc.h
index 4581289edae6b27b4a6f78da6a3868b6718fbf4f..80a61d874a7a20d37ca6ec65aef0813165f8b0eb 100644
--- a/arch/arm/src/sam34/chip/sam_dacc.h
+++ b/arch/arm/src/sam34/chip/sam_dacc.h
@@ -209,7 +209,7 @@
#define DACC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
#define DACC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
#define DACC_WPMR_WPKEY_MASK (0x00ffffff << DACC_WPMR_WPKEY_SHIFT)
-# define DACC_WPMR_WPKEY_MASK (0x00444143 << DACC_WPMR_WPKEY_SHIFT)
+# define DACC_WPMR_WPKEY (0x00444143 << DACC_WPMR_WPKEY_SHIFT)
/* Write Protect Status register */
diff --git a/arch/arm/src/sam34/sam4cm_freerun.c b/arch/arm/src/sam34/sam4cm_freerun.c
index 63bcea20315f4e43701f461926d6a376ee1f2bc0..a26578e99aca42d11badcada97df4531f05cf244 100644
--- a/arch/arm/src/sam34/sam4cm_freerun.c
+++ b/arch/arm/src/sam34/sam4cm_freerun.c
@@ -121,7 +121,7 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan,
uint32_t cmr;
int ret;
- tcvdbg("chan=%d resolution=%d usec\n", chan, resolution);
+ tmrinfo("chan=%d resolution=%d usec\n", chan, resolution);
DEBUGASSERT(freerun && resolution > 0);
/* Get the TC frequency the corresponds to the requested resolution */
@@ -133,13 +133,13 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan,
ret = sam_tc_divisor(frequency, &divisor, &cmr);
if (ret < 0)
{
- tcdbg("ERROR: sam_tc_divisor failed: %d\n", ret);
+ tmrerr("ERROR: sam_tc_divisor failed: %d\n", ret);
return ret;
}
- tcvdbg("frequency=%lu, divisor=%u, cmr=%08lx\n",
- (unsigned long)frequency, (unsigned long)divisor,
- (unsigned long)cmr);
+ tmrinfo("frequency=%lu, divisor=%u, cmr=%08lx\n",
+ (unsigned long)frequency, (unsigned long)divisor,
+ (unsigned long)cmr);
/* Allocate the timer/counter and select its mode of operation
*
@@ -172,7 +172,7 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan,
freerun->tch = sam_tc_allocate(chan, cmr);
if (!freerun->tch)
{
- tcdbg("ERROR: Failed to allocate timer channel %d\n", chan);
+ tmrerr("ERROR: Failed to allocate timer channel %d\n", chan);
return -EBUSY;
}
@@ -257,9 +257,9 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts)
leave_critical_section(flags);
- tcvdbg("counter=%lu (%lu) overflow=%lu, sr=%08lx\n",
- (unsigned long)counter, (unsigned long)verify,
- (unsigned long)overflow, (unsigned long)sr);
+ tmrinfo("counter=%lu (%lu) overflow=%lu, sr=%08lx\n",
+ (unsigned long)counter, (unsigned long)verify,
+ (unsigned long)overflow, (unsigned long)sr);
/* Convert the whole thing to units of microseconds.
*
@@ -277,7 +277,7 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts)
ts->tv_sec = sec;
ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC;
- tcvdbg("usec=%llu ts=(%lu, %lu)\n",
+ tmrinfo("usec=%llu ts=(%lu, %lu)\n",
usec, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
return OK;
diff --git a/arch/arm/src/sam34/sam4cm_oneshot.c b/arch/arm/src/sam34/sam4cm_oneshot.c
index eeda41bc8ee98ad77dc48ae420fd3e45a0bba428..a7505b5a72e2871da1e3b126e52334a361327c9e 100644
--- a/arch/arm/src/sam34/sam4cm_oneshot.c
+++ b/arch/arm/src/sam34/sam4cm_oneshot.c
@@ -91,7 +91,7 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
oneshot_handler_t oneshot_handler;
void *oneshot_arg;
- tcllvdbg("Expired...\n");
+ tmrinfo("Expired...\n");
DEBUGASSERT(oneshot && oneshot->handler);
/* The clock was stopped, but not disabled when the RC match occurred.
@@ -148,7 +148,7 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
uint32_t cmr;
int ret;
- tcvdbg("chan=%d resolution=%d usec\n", chan, resolution);
+ tmrinfo("chan=%d resolution=%d usec\n", chan, resolution);
DEBUGASSERT(oneshot && resolution > 0);
/* Get the TC frequency the corresponds to the requested resolution */
@@ -160,13 +160,13 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
ret = sam_tc_divisor(frequency, &divisor, &cmr);
if (ret < 0)
{
- tcdbg("ERROR: sam_tc_divisor failed: %d\n", ret);
+ tmrerr("ERROR: sam_tc_divisor failed: %d\n", ret);
return ret;
}
- tcvdbg("frequency=%lu, divisor=%lu, cmr=%08lx\n",
- (unsigned long)frequency, (unsigned long)divisor,
- (unsigned long)cmr);
+ tmrinfo("frequency=%lu, divisor=%lu, cmr=%08lx\n",
+ (unsigned long)frequency, (unsigned long)divisor,
+ (unsigned long)cmr);
/* Allocate the timer/counter and select its mode of operation
*
@@ -200,7 +200,7 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
oneshot->tch = sam_tc_allocate(chan, cmr);
if (!oneshot->tch)
{
- tcdbg("ERROR: Failed to allocate timer channel %d\n", chan);
+ tmrerr("ERROR: Failed to allocate timer channel %d\n", chan);
return -EBUSY;
}
@@ -258,8 +258,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
uint64_t regval;
irqstate_t flags;
- tcvdbg("handler=%p arg=%p, ts=(%lu, %lu)\n",
- handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
+ tmrinfo("handler=%p arg=%p, ts=(%lu, %lu)\n",
+ handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
DEBUGASSERT(oneshot && handler && ts);
/* Was the oneshot already running? */
@@ -269,7 +269,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
{
/* Yes.. then cancel it */
- tcvdbg("Already running... cancelling\n");
+ tmrinfo("Already running... cancelling\n");
(void)sam_oneshot_cancel(oneshot, freerun, NULL);
}
@@ -291,7 +291,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
regval = (usec * (uint64_t)sam_tc_divfreq(oneshot->tch)) / USEC_PER_SEC;
- tcvdbg("usec=%llu regval=%08llx\n", usec, regval);
+ tmrinfo("usec=%llu regval=%08llx\n", usec, regval);
DEBUGASSERT(regval <= UINT16_MAX);
/* Set up to receive the callback when the interrupt occurs */
@@ -400,7 +400,7 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
* REVISIT: This does not appear to be the case.
*/
- tcvdbg("Cancelling...\n");
+ tmrinfo("Cancelling...\n");
count = sam_tc_getcounter(oneshot->tch);
rc = sam_tc_getregister(oneshot->tch, TC_REGC);
@@ -436,8 +436,8 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
* oneshot timer.
*/
- tcvdbg("rc=%lu count=%lu usec=%lu\n",
- (unsigned long)rc, (unsigned long)count, (unsigned long)usec);
+ tmrinfo("rc=%lu count=%lu usec=%lu\n",
+ (unsigned long)rc, (unsigned long)count, (unsigned long)usec);
/* REVISIT: I am not certain why the timer counter value sometimes
* exceeds RC. Might be a bug, or perhaps the counter does not stop
@@ -481,8 +481,8 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
ts->tv_nsec = (unsigned long)nsec;
}
- tcvdbg("remaining (%lu, %lu)\n",
- (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
+ tmrinfo("remaining (%lu, %lu)\n",
+ (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
}
return OK;
diff --git a/arch/arm/src/sam34/sam4cm_tc.c b/arch/arm/src/sam34/sam4cm_tc.c
index 91ab9c3ca2e86957eb10d6108be31127a1e12b57..d10ac3310128523837b66015e77000a9ad0b6f4d 100644
--- a/arch/arm/src/sam34/sam4cm_tc.c
+++ b/arch/arm/src/sam34/sam4cm_tc.c
@@ -77,6 +77,10 @@
* Pre-processor Definitions
****************************************************************************/
+#ifndef CONFIG_DEBUG_TIMER_INFO
+# undef CONFIG_SAM34_TC_REGDEBUG
+#endif
+
/****************************************************************************
* Private Types
****************************************************************************/
@@ -390,21 +394,21 @@ static void sam_regdump(struct sam_chan_s *chan, const char *msg)
uintptr_t base;
base = chan->base;
- lldbg("TC%d [%08x]: %s\n", chan->chan, (int)base, msg);
- lldbg(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n",
- getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET),
- getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET));
+ tmrinfo("TC%d [%08x]: %s\n", chan->chan, (int)base, msg);
+ tmrinfo(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n",
+ getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET),
+ getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET));
base = chan->base;
- lldbg("TC%d Channel %d [%08x]: %s\n", chan->chan, chan->chan, (int)base, msg);
- lldbg(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n",
- getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET),
- getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET));
- lldbg(" RA: %08x RB: %08x RC: %08x SR: %08x\n",
- getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET),
- getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_SR_OFFSET));
- lldbg(" IMR: %08x\n",
- getreg32(base+SAM_TC_IMR_OFFSET));
+ tmrinfo("TC%d Channel %d [%08x]: %s\n", chan->chan, chan->chan, (int)base, msg);
+ tmrinfo(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n",
+ getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET),
+ getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET));
+ tmrinfo(" RA: %08x RB: %08x RC: %08x SR: %08x\n",
+ getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET),
+ getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_SR_OFFSET));
+ tmrinfo(" IMR: %08x\n",
+ getreg32(base+SAM_TC_IMR_OFFSET));
}
#endif
@@ -447,7 +451,7 @@ static bool sam_checkreg(struct sam_chan_s *chan, bool wr, uint32_t regaddr,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", chan->ntimes);
+ tmrinfo("...[Repeats %d times]...\n", chan->ntimes);
}
/* Save information about the new access */
@@ -481,7 +485,7 @@ static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan,
#ifdef CONFIG_SAM34_TC_REGDEBUG
if (sam_checkreg(chan, false, regaddr, regval))
{
- lldbg("%08x->%08x\n", regaddr, regval);
+ tmrinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@@ -504,7 +508,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset,
#ifdef CONFIG_SAM34_TC_REGDEBUG
if (sam_checkreg(chan, true, regaddr, regval))
{
- lldbg("%08x<-%08x\n", regaddr, regval);
+ tmrinfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@@ -757,7 +761,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel)
{
/* Timer/counter is not invalid or not enabled */
- tcdbg("ERROR: Bad channel number: %d\n", channel);
+ tmrerr("ERROR: Bad channel number: %d\n", channel);
return NULL;
}
@@ -770,7 +774,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel)
{
/* Initialize the channel. */
- tcdbg("Initializing TC%d\n", chconfig->chan);
+ tmrerr("ERROR: Initializing TC%d\n", chconfig->chan);
memset(chan, 0, sizeof(struct sam_chan_s));
sem_init(&chan->exclsem, 0, 1);
@@ -831,7 +835,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel)
{
/* No.. return a failure */
- tcdbg("Channel %d is in-used\n", channel);
+ tmrerr("ERROR: Channel %d is in-use\n", channel);
sam_givesem(chan);
return NULL;
}
@@ -876,7 +880,7 @@ TC_HANDLE sam_tc_allocate(int channel, int mode)
* access to the requested channel.
*/
- tcvdbg("channel=%d mode=%08x\n", channel, mode);
+ tmrinfo("channel=%d mode=%08x\n", channel, mode);
chan = sam_tc_initialize(channel);
if (chan)
@@ -902,7 +906,7 @@ TC_HANDLE sam_tc_allocate(int channel, int mode)
/* Return an opaque reference to the channel */
- tcvdbg("Returning %p\n", chan);
+ tmrinfo("Returning %p\n", chan);
return (TC_HANDLE)chan;
}
@@ -924,7 +928,7 @@ void sam_tc_free(TC_HANDLE handle)
{
struct sam_chan_s *chan = (struct sam_chan_s *)handle;
- tcvdbg("Freeing %p channel=%d inuse=%d\n", chan, chan->chan, chan->inuse);
+ tmrinfo("Freeing %p channel=%d inuse=%d\n", chan, chan->chan, chan->inuse);
DEBUGASSERT(chan && chan->inuse);
/* Make sure that interrupts are detached and disabled and that the channel
@@ -957,7 +961,7 @@ void sam_tc_start(TC_HANDLE handle)
{
struct sam_chan_s *chan = (struct sam_chan_s *)handle;
- tcvdbg("Starting channel %d inuse=%d\n", chan->chan, chan->inuse);
+ tmrinfo("Starting channel %d inuse=%d\n", chan->chan, chan->inuse);
DEBUGASSERT(chan && chan->inuse);
/* Read the SR to clear any pending interrupts on this channel */
@@ -989,7 +993,7 @@ void sam_tc_stop(TC_HANDLE handle)
{
struct sam_chan_s *chan = (struct sam_chan_s *)handle;
- tcvdbg("Stopping channel %d inuse=%d\n", chan->chan, chan->inuse);
+ tmrinfo("Stopping channel %d inuse=%d\n", chan->chan, chan->inuse);
DEBUGASSERT(chan && chan->inuse);
sam_chan_putreg(chan, SAM_TC_CCR_OFFSET, TC_CCR_CLKDIS);
@@ -1096,8 +1100,8 @@ void sam_tc_setregister(TC_HANDLE handle, int regid, uint32_t regval)
DEBUGASSERT(chan && regid < TC_NREGISTERS);
- tcvdbg("Channel %d: Set register RC%d to %08lx\n",
- chan->chan, regid, (unsigned long)regval);
+ tmrinfo("Channel %d: Set register RC%d to %08lx\n",
+ chan->chan, regid, (unsigned long)regval);
sam_chan_putreg(chan, g_regoffset[regid], regval);
sam_regdump(chan, "Set register");
@@ -1233,7 +1237,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks)
uint32_t ftcin = sam_tc_infreq();
int ndx = 0;
- tcvdbg("frequency=%d\n", frequency);
+ tmrinfo("frequency=%d\n", frequency);
/* Satisfy lower bound. That is, the value of the divider such that:
*
@@ -1246,7 +1250,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks)
{
/* If no divisor can be found, return -ERANGE */
- tcdbg("Lower bound search failed\n");
+ tmrerr("ERROR: Lower bound search failed\n");
return -ERANGE;
}
}
@@ -1270,7 +1274,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks)
if (div)
{
uint32_t value = sam_tc_freqdiv_lookup(ftcin, ndx);
- tcvdbg("return div=%lu\n", (unsigned long)value);
+ tmrinfo("return div=%lu\n", (unsigned long)value);
*div = value;
}
@@ -1278,7 +1282,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks)
if (tcclks)
{
- tcvdbg("return tcclks=%08lx\n", (unsigned long)TC_CMR_TCCLKS(ndx));
+ tmrinfo("return tcclks=%08lx\n", (unsigned long)TC_CMR_TCCLKS(ndx));
*tcclks = TC_CMR_TCCLKS(ndx);
}
diff --git a/arch/arm/src/sam34/sam4cm_tc.h b/arch/arm/src/sam34/sam4cm_tc.h
index 85520d84d935c7b89e3ccc52166ea976351c4397..e474f2bc6666b6cea451cc2626b4ab5aa4764803 100644
--- a/arch/arm/src/sam34/sam4cm_tc.h
+++ b/arch/arm/src/sam34/sam4cm_tc.h
@@ -71,8 +71,7 @@
/* Timer debug is enabled if any timer client is enabled */
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_ANALOG
+#ifndef CONFIG_DEBUG_TIMER_INFO
# undef CONFIG_SAMA5_TC_REGDEBUG
#endif
@@ -80,20 +79,6 @@
# define CONFIG_SAM34_TC_DEBUG 1
#endif
-/* Timer/counter debug output */
-
-#ifdef CONFIG_SAM34_TC_DEBUG
-# define tcdbg dbg
-# define tcvdbg vdbg
-# define tclldbg lldbg
-# define tcllvdbg llvdbg
-#else
-# define tcdbg(x...)
-# define tcvdbg(x...)
-# define tclldbg(x...)
-# define tcllvdbg(x...)
-#endif
-
/****************************************************************************
* Public Types
****************************************************************************/
diff --git a/arch/arm/src/sam34/sam4cm_tickless.c b/arch/arm/src/sam34/sam4cm_tickless.c
index 7d13e8756ef10502e1c9043d983c4510918597c6..54b6c943af947bec5c4fc5e4005ded68b6755df0 100644
--- a/arch/arm/src/sam34/sam4cm_tickless.c
+++ b/arch/arm/src/sam34/sam4cm_tickless.c
@@ -197,7 +197,7 @@ static struct sam_tickless_s g_tickless;
static void sam_oneshot_handler(void *arg)
{
- tcllvdbg("Expired...\n");
+ tmrinfo("Expired...\n");
sched_timer_expiration();
}
@@ -244,7 +244,7 @@ void up_timer_initialize(void)
CONFIG_USEC_PER_TICK);
if (ret < 0)
{
- tclldbg("ERROR: sam_oneshot_initialize failed\n");
+ tmrerr("ERROR: sam_oneshot_initialize failed\n");
PANIC();
}
@@ -256,7 +256,7 @@ void up_timer_initialize(void)
ret = sam_oneshot_max_delay(&g_tickless.oneshot, &max_delay);
if (ret < 0)
{
- tclldbg("ERROR: sam_oneshot_max_delay failed\n");
+ tmrerr("ERROR: sam_oneshot_max_delay failed\n");
PANIC();
}
@@ -280,7 +280,7 @@ void up_timer_initialize(void)
CONFIG_USEC_PER_TICK);
if (ret < 0)
{
- tclldbg("ERROR: sam_freerun_initialize failed\n");
+ tmrerr("ERROR: sam_freerun_initialize failed\n");
PANIC();
}
diff --git a/arch/arm/src/sam34/sam4l_gpio.c b/arch/arm/src/sam34/sam4l_gpio.c
index 4dcefcef55e1a5e3ee8e3fe614a674829377d7b9..02394a543faeb63f0b01050a689030aca0f76301 100644
--- a/arch/arm/src/sam34/sam4l_gpio.c
+++ b/arch/arm/src/sam34/sam4l_gpio.c
@@ -59,7 +59,7 @@
* Private Data
****************************************************************************/
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
static const char g_portchar[4] = { 'A', 'B', 'C', 'D' };
#endif
@@ -522,7 +522,7 @@ bool sam_gpioread(gpio_pinset_t pinset)
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
int sam_dumpgpio(uint32_t pinset, const char *msg)
{
irqstate_t flags;
@@ -539,23 +539,25 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
/* The following requires exclusive access to the GPIO registers */
flags = enter_critical_section();
- lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
- g_portchar[port], pinset, base, msg);
- lldbg(" GPER: %08x PMR0: %08x PMR1: %08x PMR2: %08x\n",
- getreg32(base + SAM_GPIO_GPER_OFFSET), getreg32(base + SAM_GPIO_PMR0_OFFSET),
- getreg32(base + SAM_GPIO_PMR1_OFFSET), getreg32(base + SAM_GPIO_PMR2_OFFSET));
- lldbg(" ODER: %08x OVR: %08x PVR: %08x PUER: %08x\n",
- getreg32(base + SAM_GPIO_ODER_OFFSET), getreg32(base + SAM_GPIO_OVR_OFFSET),
- getreg32(base + SAM_GPIO_PVR_OFFSET), getreg32(base + SAM_GPIO_PUER_OFFSET));
- lldbg(" PDER: %08x IER: %08x IMR0: %08x IMR1: %08x\n",
- getreg32(base + SAM_GPIO_PDER_OFFSET), getreg32(base + SAM_GPIO_IER_OFFSET),
- getreg32(base + SAM_GPIO_IMR0_OFFSET), getreg32(base + SAM_GPIO_IMR1_OFFSET));
- lldbg(" GFER: %08x IFR: %08x ODCR0: %08x ODCR1: %08x\n",
- getreg32(base + SAM_GPIO_GFER_OFFSET), getreg32(base + SAM_GPIO_IFR_OFFSET),
- getreg32(base + SAM_GPIO_ODCR0_OFFSET), getreg32(base + SAM_GPIO_ODCR1_OFFSET));
- lldbg(" OSRR0: %08x EVER: %08x PARAM: %08x VERS: %08x\n",
- getreg32(base + SAM_GPIO_OSRR0_OFFSET), getreg32(base + SAM_GPIO_EVER_OFFSET),
- getreg32(base + SAM_GPIO_PARAMETER_OFFSET), getreg32(base + SAM_GPIO_VERSION_OFFSET));
+
+ gpioinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
+ g_portchar[port], pinset, base, msg);
+ gpioinfo(" GPER: %08x PMR0: %08x PMR1: %08x PMR2: %08x\n",
+ getreg32(base + SAM_GPIO_GPER_OFFSET), getreg32(base + SAM_GPIO_PMR0_OFFSET),
+ getreg32(base + SAM_GPIO_PMR1_OFFSET), getreg32(base + SAM_GPIO_PMR2_OFFSET));
+ gpioinfo(" ODER: %08x OVR: %08x PVR: %08x PUER: %08x\n",
+ getreg32(base + SAM_GPIO_ODER_OFFSET), getreg32(base + SAM_GPIO_OVR_OFFSET),
+ getreg32(base + SAM_GPIO_PVR_OFFSET), getreg32(base + SAM_GPIO_PUER_OFFSET));
+ gpioinfo(" PDER: %08x IER: %08x IMR0: %08x IMR1: %08x\n",
+ getreg32(base + SAM_GPIO_PDER_OFFSET), getreg32(base + SAM_GPIO_IER_OFFSET),
+ getreg32(base + SAM_GPIO_IMR0_OFFSET), getreg32(base + SAM_GPIO_IMR1_OFFSET));
+ gpioinfo(" GFER: %08x IFR: %08x ODCR0: %08x ODCR1: %08x\n",
+ getreg32(base + SAM_GPIO_GFER_OFFSET), getreg32(base + SAM_GPIO_IFR_OFFSET),
+ getreg32(base + SAM_GPIO_ODCR0_OFFSET), getreg32(base + SAM_GPIO_ODCR1_OFFSET));
+ gpioinfo(" OSRR0: %08x EVER: %08x PARAM: %08x VERS: %08x\n",
+ getreg32(base + SAM_GPIO_OSRR0_OFFSET), getreg32(base + SAM_GPIO_EVER_OFFSET),
+ getreg32(base + SAM_GPIO_PARAMETER_OFFSET), getreg32(base + SAM_GPIO_VERSION_OFFSET));
+
leave_critical_section(flags);
return OK;
}
diff --git a/arch/arm/src/sam34/sam_dmac.c b/arch/arm/src/sam34/sam_dmac.c
index bcc8fb03f0726e14c8c3b0176437beba35c26adf..7cf1cff349991acae896bab29e2cf5f9a94ae548 100644
--- a/arch/arm/src/sam34/sam_dmac.c
+++ b/arch/arm/src/sam34/sam_dmac.c
@@ -889,7 +889,7 @@ sam_allocdesc(struct sam_dma_s *dmach, struct dma_linklist_s *prev,
* Obviously setting it to zero would break that usage.
*/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (src != 0)
#endif
{
@@ -1354,7 +1354,7 @@ static int sam_dmainterrupt(int irq, void *context)
void weak_function up_dmainitialize(void)
{
- dmallvdbg("Initialize DMAC0\n");
+ dmainfo("Initialize DMAC0\n");
/* Enable peripheral clock */
@@ -1460,7 +1460,7 @@ DMA_HANDLE sam_dmachannel(uint32_t chflags)
sam_givechsem();
- dmavdbg("chflags: %08x returning dmach: %p\n", (int)chflags, dmach);
+ dmainfo("chflags: %08x returning dmach: %p\n", (int)chflags, dmach);
return (DMA_HANDLE)dmach;
}
@@ -1486,7 +1486,7 @@ void sam_dmaconfig(DMA_HANDLE handle, uint32_t chflags)
/* Set the new DMA channel flags. */
- dmavdbg("chflags: %08x\n", (int)chflags);
+ dmainfo("chflags: %08x\n", (int)chflags);
dmach->flags = chflags;
}
@@ -1507,7 +1507,7 @@ void sam_dmafree(DMA_HANDLE handle)
{
struct sam_dma_s *dmach = (struct sam_dma_s *)handle;
- dmavdbg("dmach: %p\n", dmach);
+ dmainfo("dmach: %p\n", dmach);
DEBUGASSERT((dmach != NULL) && (dmach->inuse));
/* Mark the channel no longer in use. Clearing the inuse flag is an atomic
@@ -1536,10 +1536,10 @@ int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t nby
size_t maxtransfer;
int ret = OK;
- dmavdbg("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
+ dmainfo("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
dmach, (int)paddr, (int)maddr, (int)nbytes);
DEBUGASSERT(dmach);
- dmavdbg("llhead: %p lltail: %p\n", dmach->llhead, dmach->lltail);
+ dmainfo("llhead: %p lltail: %p\n", dmach->llhead, dmach->lltail);
/* The maximum transfer size in bytes depends upon the maximum number of
* transfers and the number of bytes per transfer.
@@ -1604,10 +1604,10 @@ int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t nby
size_t maxtransfer;
int ret = OK;
- dmavdbg("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
+ dmainfo("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
dmach, (int)paddr, (int)maddr, (int)nbytes);
DEBUGASSERT(dmach);
- dmavdbg("llhead: %p lltail: %p\n", dmach->llhead, dmach->lltail);
+ dmainfo("llhead: %p lltail: %p\n", dmach->llhead, dmach->lltail);
/* The maximum transfer size in bytes depends upon the maximum number of
* transfers and the number of bytes per transfer.
@@ -1667,7 +1667,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
struct sam_dma_s *dmach = (struct sam_dma_s *)handle;
int ret = -EINVAL;
- dmavdbg("dmach: %p callback: %p arg: %p\n", dmach, callback, arg);
+ dmainfo("dmach: %p callback: %p arg: %p\n", dmach, callback, arg);
DEBUGASSERT(dmach != NULL);
/* Verify that the DMA has been setup (i.e., at least one entry in the
@@ -1711,7 +1711,7 @@ void sam_dmastop(DMA_HANDLE handle)
struct sam_dma_s *dmach = (struct sam_dma_s *)handle;
irqstate_t flags;
- dmavdbg("dmach: %p\n", dmach);
+ dmainfo("dmach: %p\n", dmach);
DEBUGASSERT(dmach != NULL);
flags = enter_critical_section();
@@ -1730,7 +1730,7 @@ void sam_dmastop(DMA_HANDLE handle)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
{
struct sam_dma_s *dmach = (struct sam_dma_s *)handle;
@@ -1761,7 +1761,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
regs->cfg = getreg32(dmach->base + SAM_DMACHAN_CFG_OFFSET);
leave_critical_section(flags);
}
-#endif /* CONFIG_DEBUG_DMA */
+#endif /* CONFIG_DEBUG_DMA_INFO */
/****************************************************************************
* Name: sam_dmadump
@@ -1774,28 +1774,28 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
const char *msg)
{
struct sam_dma_s *dmach = (struct sam_dma_s *)handle;
- dmadbg("%s\n", msg);
- dmadbg(" DMA Global Registers:\n");
- dmadbg(" GCFG[%08x]: %08x\n", SAM_DMAC_GCFG, regs->gcfg);
- dmadbg(" EN[%08x]: %08x\n", SAM_DMAC_EN, regs->en);
- dmadbg(" SREQ[%08x]: %08x\n", SAM_DMAC_SREQ, regs->sreq);
- dmadbg(" CREQ[%08x]: %08x\n", SAM_DMAC_CREQ, regs->creq);
- dmadbg(" LAST[%08x]: %08x\n", SAM_DMAC_LAST, regs->last);
- dmadbg(" EBCIMR[%08x]: %08x\n", SAM_DMAC_EBCIMR, regs->ebcimr);
- dmadbg(" CHSR[%08x]: %08x\n", SAM_DMAC_CHSR, regs->chsr);
- dmadbg(" DMA Channel Registers:\n");
- dmadbg(" SADDR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_SADDR_OFFSET, regs->saddr);
- dmadbg(" DADDR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_DADDR_OFFSET, regs->daddr);
- dmadbg(" DSCR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_DSCR_OFFSET, regs->dscr);
- dmadbg(" CTRLA[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CTRLA_OFFSET, regs->ctrla);
- dmadbg(" CTRLB[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CTRLB_OFFSET, regs->ctrlb);
- dmadbg(" CFG[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CFG_OFFSET, regs->cfg);
+ dmainfo("%s\n", msg);
+ dmainfo(" DMA Global Registers:\n");
+ dmainfo(" GCFG[%08x]: %08x\n", SAM_DMAC_GCFG, regs->gcfg);
+ dmainfo(" EN[%08x]: %08x\n", SAM_DMAC_EN, regs->en);
+ dmainfo(" SREQ[%08x]: %08x\n", SAM_DMAC_SREQ, regs->sreq);
+ dmainfo(" CREQ[%08x]: %08x\n", SAM_DMAC_CREQ, regs->creq);
+ dmainfo(" LAST[%08x]: %08x\n", SAM_DMAC_LAST, regs->last);
+ dmainfo(" EBCIMR[%08x]: %08x\n", SAM_DMAC_EBCIMR, regs->ebcimr);
+ dmainfo(" CHSR[%08x]: %08x\n", SAM_DMAC_CHSR, regs->chsr);
+ dmainfo(" DMA Channel Registers:\n");
+ dmainfo(" SADDR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_SADDR_OFFSET, regs->saddr);
+ dmainfo(" DADDR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_DADDR_OFFSET, regs->daddr);
+ dmainfo(" DSCR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_DSCR_OFFSET, regs->dscr);
+ dmainfo(" CTRLA[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CTRLA_OFFSET, regs->ctrla);
+ dmainfo(" CTRLB[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CTRLB_OFFSET, regs->ctrlb);
+ dmainfo(" CFG[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CFG_OFFSET, regs->cfg);
}
-#endif /* CONFIG_DEBUG_DMA */
+#endif /* CONFIG_DEBUG_DMA_INFO */
#endif /* CONFIG_SAM34_DMAC0 */
diff --git a/arch/arm/src/sam34/sam_dmac.h b/arch/arm/src/sam34/sam_dmac.h
index 0ff4f2e14485f92635e190cf0fab525f7ad3f973..58e7e68eb80d1e8732f6964a11a27ce5e859f5d2 100644
--- a/arch/arm/src/sam34/sam_dmac.h
+++ b/arch/arm/src/sam34/sam_dmac.h
@@ -50,12 +50,6 @@
* Pre-processor Definitions
************************************************************************************/
-/* Configuration ********************************************************************/
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_DMA
-#endif
-
/* DMA ******************************************************************************/
/* Flags used to characterize the desired DMA channel. The naming convention is that
@@ -125,7 +119,7 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
struct sam_dmaregs_s
{
/* Global Registers */
@@ -285,7 +279,7 @@ void sam_dmastop(DMA_HANDLE handle);
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs);
#else
# define sam_dmasample(handle,regs)
@@ -299,7 +293,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs);
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
const char *msg);
#else
diff --git a/arch/arm/src/sam34/sam_emac.c b/arch/arm/src/sam34/sam_emac.c
index d33f1d8aabb83151e6e9ee31b1cef566679c2a52..5e4e348f6c05647be73160f66367a2aba99ab88b 100644
--- a/arch/arm/src/sam34/sam_emac.c
+++ b/arch/arm/src/sam34/sam_emac.c
@@ -231,7 +231,7 @@
* enabled.
*/
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_NET_INFO
# undef CONFIG_SAM34_EMAC_REGDEBUG
#endif
@@ -278,9 +278,9 @@ struct sam_emac_s
struct work_s work; /* For deferring work to the work queue */
#endif
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
/* Used to track transmit and receive descriptors */
@@ -346,7 +346,7 @@ static uint8_t g_rxbuffer[CONFIG_SAM34_EMAC_NRXBUFFERS * EMAC_RX_UNITSIZE]
****************************************************************************/
/* Register operations ******************************************************/
-#if defined(CONFIG_SAM34_EMAC_REGDEBUG) && defined(CONFIG_DEBUG)
+#if defined(CONFIG_SAM34_EMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
static bool sam_checkreg(struct sam_emac_s *priv, bool wr,
uint32_t regval, uintptr_t address);
static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t addr);
@@ -419,7 +419,7 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, long arg);
/* PHY Initialization */
-#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_VERBOSE)
+#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_INFO)
static void sam_phydump(struct sam_emac_s *priv);
#else
# define sam_phydump(priv)
@@ -490,7 +490,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", priv->ntimes);
+ ninfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@@ -522,7 +522,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t address)
if (sam_checkreg(priv, false, regval, address))
{
- lldbg("%08x->%08x\n", address, regval);
+ ninfo("%08x->%08x\n", address, regval);
}
return regval;
@@ -543,7 +543,7 @@ static void sam_putreg(struct sam_emac_s *priv, uintptr_t address,
{
if (sam_checkreg(priv, true, regval, address))
{
- lldbg("%08x<-%08x\n", address, regval);
+ ninfo("%08x<-%08x\n", address, regval);
}
putreg32(regval, address);
@@ -636,7 +636,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->txdesc = (struct emac_txdesc_s *)kmm_memalign(8, allocsize);
if (!priv->txdesc)
{
- nlldbg("ERROR: Failed to allocate TX descriptors\n");
+ nerr("ERROR: Failed to allocate TX descriptors\n");
return -ENOMEM;
}
@@ -646,7 +646,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->rxdesc = (struct emac_rxdesc_s *)kmm_memalign(8, allocsize);
if (!priv->rxdesc)
{
- nlldbg("ERROR: Failed to allocate RX descriptors\n");
+ nerr("ERROR: Failed to allocate RX descriptors\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -657,7 +657,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->txbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->txbuffer)
{
- nlldbg("ERROR: Failed to allocate TX buffer\n");
+ nerr("ERROR: Failed to allocate TX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -666,7 +666,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->rxbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->rxbuffer)
{
- nlldbg("ERROR: Failed to allocate RX buffer\n");
+ nerr("ERROR: Failed to allocate RX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -753,14 +753,14 @@ static int sam_transmit(struct sam_emac_s *priv)
uint32_t regval;
uint32_t status;
- nllvdbg("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
+ ninfo("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
/* Check parameter */
if (dev->d_len > EMAC_TX_UNITSIZE)
{
- nlldbg("ERROR: Packet too big: %d\n", dev->d_len);
+ nerr("ERROR: Packet too big: %d\n", dev->d_len);
return -EINVAL;
}
@@ -772,7 +772,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
- nlldbg("ERROR: No free TX descriptors\n");
+ nerr("ERROR: No free TX descriptors\n");
return -EBUSY;
}
@@ -830,7 +830,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
- nllvdbg("Disabling RX interrupts\n");
+ ninfo("Disabling RX interrupts\n");
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_RCOMP);
}
@@ -841,7 +841,7 @@ static int sam_transmit(struct sam_emac_s *priv)
* Function: sam_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -951,7 +951,7 @@ static void sam_dopoll(struct sam_emac_s *priv)
if (sam_txfree(priv) > 0)
{
- /* If we have the descriptor, then poll uIP for new XMIT data. */
+ /* If we have the descriptor, then poll the network for new XMIT data. */
(void)devif_poll(dev, sam_txpoll);
}
@@ -1010,7 +1010,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
sam_cmcc_invalidate((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
- nllvdbg("rxndx: %d\n", rxndx);
+ ninfo("rxndx: %d\n", rxndx);
while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
{
@@ -1060,7 +1060,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
{
if (rxndx == priv->rxndx)
{
- nllvdbg("ERROR: No EOF (Invalid of buffers too small)\n");
+ nerr("ERROR: No EOF (Invalid of buffers too small)\n");
do
{
/* Give ownership back to the EMAC */
@@ -1107,7 +1107,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Frame size from the EMAC */
dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
- nllvdbg("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
+ ninfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
/* All data have been copied in the application frame buffer,
* release the RX descriptor
@@ -1132,11 +1132,11 @@ static int sam_recvframe(struct sam_emac_s *priv)
* all of the data.
*/
- nllvdbg("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
+ ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
if (pktlen < dev->d_len)
{
- nlldbg("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
+ nerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
return -E2BIG;
}
@@ -1167,7 +1167,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* No packet was found */
priv->rxndx = rxndx;
- nllvdbg("rxndx: %d\n", priv->rxndx);
+ ninfo("rxndx: %d\n", priv->rxndx);
return -EAGAIN;
}
@@ -1201,13 +1201,13 @@ static void sam_receive(struct sam_emac_s *priv)
{
sam_dumppacket("Received packet", dev->d_buf, dev->d_len);
- /* Check if the packet is a valid size for the uIP buffer configuration
+ /* Check if the packet is a valid size for the network buffer configuration
* (this should not happen)
*/
if (dev->d_len > CONFIG_NET_ETH_MTU)
{
- nlldbg("DROPPED: Too big: %d\n", dev->d_len);
+ nwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
continue;
}
@@ -1222,7 +1222,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
- nllvdbg("IPv4 frame\n");
+ ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@@ -1262,7 +1262,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
- nllvdbg("Iv6 frame\n");
+ ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@@ -1299,7 +1299,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
- nllvdbg("ARP frame\n");
+ ninfo("ARP frame\n");
/* Handle ARP packet */
@@ -1317,7 +1317,7 @@ static void sam_receive(struct sam_emac_s *priv)
else
#endif
{
- nlldbg("DROPPED: Unknown type: %04x\n", BUF->type);
+ nwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
}
}
}
@@ -1403,7 +1403,7 @@ static void sam_txdone(struct sam_emac_s *priv)
sam_putreg(priv, SAM_EMAC_IER, EMAC_INT_RCOMP);
}
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -1442,7 +1442,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
imr = sam_getreg(priv, SAM_EMAC_IMR);
pending = isr & ~(imr | EMAC_INT_UNUSED);
- nllvdbg("isr: %08x pending: %08x\n", isr, pending);
+ ninfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
@@ -1468,7 +1468,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
clrbits = EMAC_TSR_RLE | sam_txinuse(priv);
sam_txreset(priv);
- nlldbg("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
+ nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval |= EMAC_NCR_TXEN;
@@ -1479,7 +1479,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((tsr & EMAC_TSR_COL) != 0)
{
- nlldbg("ERROR: Collision occurred TSR: %08x\n", tsr);
+ nerr("ERROR: Collision occurred TSR: %08x\n", tsr);
clrbits |= EMAC_TSR_COL;
}
@@ -1487,7 +1487,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((tsr & EMAC_TSR_TFC) != 0)
{
- nlldbg("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
+ nerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
clrbits |= EMAC_TSR_TFC;
}
@@ -1502,7 +1502,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((tsr & EMAC_TSR_UND) != 0)
{
- nlldbg("ERROR: Transmit Underrun TSR: %08x\n", tsr);
+ nerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
clrbits |= EMAC_TSR_UND;
}
@@ -1539,7 +1539,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((rsr & EMAC_RSR_RXOVR) != 0)
{
- nlldbg("ERROR: Receiver overrun RSR: %08x\n", rsr);
+ nerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_RXOVR;
}
@@ -1556,7 +1556,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((rsr & EMAC_RSR_BNA) != 0)
{
- nlldbg("ERROR: Buffer not available RSR: %08x\n", rsr);
+ nerr("ERROR: Buffer not available RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_BNA;
}
@@ -1578,7 +1578,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((pending & EMAC_INT_PFNZ) != 0)
{
- nlldbg("Pause frame received\n");
+ nwarn("WARNING: Pause frame received\n");
}
/* Check for Pause Time Zero (PTZ)
@@ -1588,7 +1588,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((pending & EMAC_INT_PTZ) != 0)
{
- nlldbg("Pause TO!\n");
+ nwarn("WARNING: Pause TO!\n");
}
#endif
}
@@ -1725,7 +1725,7 @@ static int sam_emac_interrupt(int irq, void *context)
static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv)
{
- nlldbg("Timeout!\n");
+ nerr("ERROR: Timeout!\n");
/* Then reset the hardware. Just take the interface down, then back
* up again.
@@ -1734,7 +1734,7 @@ static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv)
sam_ifdown(&priv->dev);
sam_ifup(&priv->dev);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -1844,7 +1844,7 @@ static inline void sam_poll_process(FAR struct sam_emac_s *priv)
if (sam_txfree(priv) > 0)
{
- /* Update TCP timing states and poll uIP for new XMIT data. */
+ /* Update TCP timing states and poll the network for new XMIT data. */
(void)devif_timer(dev, sam_txpoll);
}
@@ -1956,13 +1956,13 @@ static int sam_ifup(struct net_driver_s *dev)
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
int ret;
- nlldbg("Bringing up: %d.%d.%d.%d\n",
- dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
- (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+ ninfo("Bringing up: %d.%d.%d.%d\n",
+ dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+ (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
/* Configure the EMAC interface for normal operation. */
- nllvdbg("Initialize the EMAC\n");
+ ninfo("Initialize the EMAC\n");
sam_emac_configure(priv);
/* Set the MAC address (should have been configured while we were down) */
@@ -1980,7 +1980,7 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_phyinit(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phyinit failed: %d\n", ret);
+ nerr("ERROR: sam_phyinit failed: %d\n", ret);
return ret;
}
@@ -1989,16 +1989,16 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_autonegotiate(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_autonegotiate failed: %d\n", ret);
+ nerr("ERROR: sam_autonegotiate failed: %d\n", ret);
return ret;
}
while (sam_linkup(priv) == 0);
- nllvdbg("Link detected \n");
+ ninfo("Link detected \n");
/* Enable normal MAC operation */
- nllvdbg("Enable normal operation\n");
+ ninfo("Enable normal operation\n");
/* Set and activate a timer process */
@@ -2032,7 +2032,7 @@ static int sam_ifdown(struct net_driver_s *dev)
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
irqstate_t flags;
- nlldbg("Taking the network down\n");
+ ninfo("Taking the network down\n");
/* Disable the EMAC interrupt */
@@ -2077,13 +2077,13 @@ static int sam_ifdown(struct net_driver_s *dev)
static inline void sam_txavail_process(FAR struct sam_emac_s *priv)
{
- nllvdbg("ifup: %d\n", priv->ifup);
+ ninfo("ifup: %d\n", priv->ifup);
/* Ignore the notification if the interface is not yet up */
if (priv->ifup)
{
- /* Poll uIP for new XMIT data */
+ /* Poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -2331,8 +2331,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
- nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@@ -2405,8 +2405,8 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
- nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@@ -2588,7 +2588,7 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, long arg)
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_VERBOSE)
+#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_INFO)
static void sam_phydump(struct sam_emac_s *priv)
{
uint32_t regval;
@@ -2601,21 +2601,21 @@ static void sam_phydump(struct sam_emac_s *priv)
sam_putreg(priv, SAM_EMAC_NCR, regval);
#ifdef CONFIG_SAM34_EMAC_RMII
- nllvdbg("RMII Registers (Address %02x)\n", priv->phyaddr);
+ ninfo("RMII Registers (Address %02x)\n", priv->phyaddr);
#else /* defined(CONFIG_SAM34_EMAC_MII) */
- nllvdbg("MII Registers (Address %02x)\n", priv->phyaddr);
+ ninfo("MII Registers (Address %02x)\n", priv->phyaddr);
#endif
sam_phyread(priv, priv->phyaddr, MII_MCR, &phyval);
- nllvdbg(" MCR: %04x\n", phyval);
+ ninfo(" MCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_MSR, &phyval);
- nllvdbg(" MSR: %04x\n", phyval);
+ ninfo(" MSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_ADVERTISE, &phyval);
- nllvdbg(" ADVERTISE: %04x\n", phyval);
+ ninfo(" ADVERTISE: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_LPA, &phyval);
- nllvdbg(" LPR: %04x\n", phyval);
+ ninfo(" LPR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, CONFIG_SAM34_EMAC_PHYSR, &phyval);
- nllvdbg(" PHYSR: %04x\n", phyval);
+ ninfo(" PHYSR: %04x\n", phyval);
/* Disable management port */
@@ -2738,7 +2738,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int timeout;
int ret;
- nllvdbg(" sam_phyreset\n");
+ ninfo(" sam_phyreset\n");
/* Enable management port */
@@ -2751,7 +2751,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, MII_MCR_RESET);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywrite failed: %d\n", ret);
+ nerr("ERROR: sam_phywrite failed: %d\n", ret);
}
/* Wait for the PHY reset to complete */
@@ -2763,7 +2763,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int result = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (result < 0)
{
- nlldbg("ERROR: Failed to read the MCR register: %d\n", ret);
+ nerr("ERROR: Failed to read the MCR register: %d\n", ret);
ret = result;
}
else if ((mcr & MII_MCR_RESET) == 0)
@@ -2805,7 +2805,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
unsigned int offset;
int ret = -ESRCH;
- nllvdbg("Find a valid PHY address\n");
+ ninfo("Find a valid PHY address\n");
/* Enable management port */
@@ -2828,8 +2828,8 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
else
{
- nlldbg("ERROR: sam_phyread failed for PHY address %02x: %d\n",
- candidate, ret);
+ nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
+ candidate, ret);
for (offset = 0; offset < 32; offset++)
{
@@ -2850,10 +2850,10 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
if (ret == OK)
{
- nllvdbg(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
+ ninfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
*phyaddr = candidate;
sam_phyread(priv, candidate, CONFIG_SAM34_EMAC_PHYSR, &phyval);
- nllvdbg(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
+ ninfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
}
/* Disable management port */
@@ -2894,7 +2894,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -2918,7 +2918,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -2958,7 +2958,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -2982,7 +2982,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -3026,32 +3026,32 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID1, &phyid1);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read PHYID1\n");
+ nerr("ERROR: Failed to read PHYID1\n");
goto errout;
}
- nllvdbg("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
+ ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID2, &phyid2);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read PHYID2\n");
+ nerr("ERROR: Failed to read PHYID2\n");
goto errout;
}
- nllvdbg("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
+ ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
if (phyid1 == MII_OUI_MSB &&
((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) == MII_OUI_LSB)
{
- nllvdbg(" Vendor Model Number: %04x\n",
- (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
- nllvdbg(" Model Revision Number: %04x\n",
- (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
+ ninfo(" Vendor Model Number: %04x\n",
+ (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
+ ninfo(" Model Revision Number: %04x\n",
+ (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
}
else
{
- nlldbg("ERROR: PHY not recognized\n");
+ nerr("ERROR: PHY not recognized\n");
}
/* Setup control register */
@@ -3059,7 +3059,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read MCR\n");
+ nerr("ERROR: Failed to read MCR\n");
goto errout;
}
@@ -3070,7 +3070,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to write MCR\n");
+ nerr("ERROR: Failed to write MCR\n");
goto errout;
}
@@ -3085,7 +3085,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_ADVERTISE, advertise);
if (ret < 0)
{
- nlldbg("ERROR: Failed to write ANAR\n");
+ nerr("ERROR: Failed to write ANAR\n");
goto errout;
}
@@ -3094,7 +3094,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read MCR\n");
+ nerr("ERROR: Failed to read MCR\n");
goto errout;
}
@@ -3102,7 +3102,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to write MCR\n");
+ nerr("ERROR: Failed to write MCR\n");
goto errout;
}
@@ -3114,11 +3114,11 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to write MCR\n");
+ nerr("ERROR: Failed to write MCR\n");
goto errout;
}
- nllvdbg(" MCR: %04x\n", mcr);
+ ninfo(" MCR: %04x\n", mcr);
/* Check AutoNegotiate complete */
@@ -3128,7 +3128,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read MSR\n");
+ nerr("ERROR: Failed to read MSR\n");
goto errout;
}
@@ -3138,7 +3138,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
{
/* Yes.. break out of the loop */
- nllvdbg("AutoNegotiate complete\n");
+ ninfo("AutoNegotiate complete\n");
break;
}
@@ -3146,7 +3146,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
if (++timeout >= PHY_RETRY_MAX)
{
- nlldbg("ERROR: TimeOut\n");
+ nerr("ERROR: TimeOut\n");
sam_phydump(priv);
ret = -ETIMEDOUT;
goto errout;
@@ -3158,7 +3158,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_LPA, &lpa);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read ANLPAR\n");
+ nerr("ERROR: Failed to read ANLPAR\n");
goto errout;
}
@@ -3244,13 +3244,13 @@ static bool sam_linkup(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read MSR: %d\n", ret);
+ nerr("ERROR: Failed to read MSR: %d\n", ret);
goto errout;
}
if ((msr & MII_MSR_LINKSTATUS) == 0)
{
- nlldbg("ERROR: MSR LinkStatus: %04x\n", msr);
+ nerr("ERROR: MSR LinkStatus: %04x\n", msr);
goto errout;
}
@@ -3259,7 +3259,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, CONFIG_SAM34_EMAC_PHYSR, &physr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read PHYSR: %d\n", ret);
+ nerr("ERROR: Failed to read PHYSR: %d\n", ret);
goto errout;
}
@@ -3297,7 +3297,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
/* Start the EMAC transfers */
- nllvdbg("Link is up\n");
+ ninfo("Link is up\n");
linkup = true;
errout:
@@ -3354,7 +3354,7 @@ static int sam_phyinit(struct sam_emac_s *priv)
ret = sam_phyfind(priv, &priv->phyaddr);
if (ret < 0)
{
- nlldbg("ERROR: sam_phyfind failed: %d\n", ret);
+ nerr("ERROR: sam_phyfind failed: %d\n", ret);
return ret;
}
@@ -3598,11 +3598,11 @@ static void sam_macaddress(struct sam_emac_s *priv)
struct net_driver_s *dev = &priv->dev;
uint32_t regval;
- nllvdbg("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- dev->d_ifname,
- dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
- dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
- dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
+ ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ dev->d_ifname,
+ dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+ dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+ dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
/* Set the MAC address */
@@ -3664,7 +3664,7 @@ static void sam_ipv6multicast(struct sam_emac_s *priv)
mac[4] = tmp16 & 0xff;
mac[5] = tmp16 >> 8;
- nvdbg("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
(void)sam_addmac(dev, mac);
@@ -3710,7 +3710,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
{
uint32_t regval;
- nllvdbg("Entry\n");
+ ninfo("Entry\n");
/* Enable clocking to the EMAC peripheral */
@@ -3823,14 +3823,14 @@ void up_netinitialize(void)
priv->txpoll = wd_create();
if (!priv->txpoll)
{
- nlldbg("ERROR: Failed to create periodic poll timer\n");
+ nerr("ERROR: Failed to create periodic poll timer\n");
return;
}
priv->txtimeout = wd_create(); /* Create TX timeout timer */
if (!priv->txtimeout)
{
- nlldbg("ERROR: Failed to create periodic poll timer\n");
+ nerr("ERROR: Failed to create periodic poll timer\n");
goto errout_with_txpoll;
}
@@ -3843,7 +3843,7 @@ void up_netinitialize(void)
ret = sam_buffer_initialize(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_buffer_initialize failed: %d\n", ret);
+ nerr("ERROR: sam_buffer_initialize failed: %d\n", ret);
goto errout_with_txtimeout;
}
@@ -3854,7 +3854,7 @@ void up_netinitialize(void)
ret = irq_attach(SAM_IRQ_EMAC, sam_emac_interrupt);
if (ret < 0)
{
- nlldbg("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_EMAC);
+ nerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_EMAC);
goto errout_with_buffers;
}
@@ -3867,7 +3867,7 @@ void up_netinitialize(void)
ret = sam_ifdown(&priv->dev);
if (ret < 0)
{
- nlldbg("ERROR: Failed to put the interface in the down state: %d\n", ret);
+ nerr("ERROR: Failed to put the interface in the down state: %d\n", ret);
goto errout_with_buffers;
}
@@ -3879,7 +3879,7 @@ void up_netinitialize(void)
return;
}
- nlldbg("ERROR: netdev_register() failed: %d\n", ret);
+ nerr("ERROR: netdev_register() failed: %d\n", ret);
errout_with_buffers:
sam_buffer_free(priv);
diff --git a/arch/arm/src/sam34/sam_gpio.c b/arch/arm/src/sam34/sam_gpio.c
index b0f45e89e7ba95b4baa96feceb1b4dd55e19e124..89461c58369c2fc6fe2ef3e8a311a873c99b6c2f 100644
--- a/arch/arm/src/sam34/sam_gpio.c
+++ b/arch/arm/src/sam34/sam_gpio.c
@@ -70,7 +70,7 @@
* Private Data
****************************************************************************/
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
static const char g_portchar[4] = { 'A', 'B', 'C', 'D' };
#endif
@@ -473,7 +473,7 @@ bool sam_gpioread(gpio_pinset_t pinset)
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
int sam_dumpgpio(uint32_t pinset, const char *msg)
{
irqstate_t flags;
@@ -488,44 +488,46 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
/* The following requires exclusive access to the GPIO registers */
flags = enter_critical_section();
- lldbg("PIO%c pinset: %08x base: %08x -- %s\n",
+
+ gpioinfo("PIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
- lldbg(" PSR: %08x OSR: %08x IFSR: %08x ODSR: %08x\n",
- getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET),
- getreg32(base + SAM_PIO_IFSR_OFFSET), getreg32(base + SAM_PIO_ODSR_OFFSET));
- lldbg(" PDSR: %08x IMR: %08x ISR: %08x MDSR: %08x\n",
- getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
- getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET));
+ gpioinfo(" PSR: %08x OSR: %08x IFSR: %08x ODSR: %08x\n",
+ getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET),
+ getreg32(base + SAM_PIO_IFSR_OFFSET), getreg32(base + SAM_PIO_ODSR_OFFSET));
+ gpioinfo(" PDSR: %08x IMR: %08x ISR: %08x MDSR: %08x\n",
+ getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
+ getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET));
#if defined(CONFIG_ARCH_CHIP_SAM3U)
- lldbg(" ABSR: %08x SCIFSR: %08x DIFSR: %08x IFDGSR: %08x\n",
- getreg32(base + SAM_PIO_ABSR_OFFSET), getreg32(base + SAM_PIO_SCIFSR_OFFSET),
- getreg32(base + SAM_PIO_DIFSR_OFFSET), getreg32(base + SAM_PIO_IFDGSR_OFFSET));
+ gpioinfo(" ABSR: %08x SCIFSR: %08x DIFSR: %08x IFDGSR: %08x\n",
+ getreg32(base + SAM_PIO_ABSR_OFFSET), getreg32(base + SAM_PIO_SCIFSR_OFFSET),
+ getreg32(base + SAM_PIO_DIFSR_OFFSET), getreg32(base + SAM_PIO_IFDGSR_OFFSET));
#elif defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
- lldbg(" ABCDSR: %08x %08x IFSCSR: %08x PPDSR: %08x\n",
- getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET),
- getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_PPDSR_OFFSET));
+ gpioinfo(" ABCDSR: %08x %08x IFSCSR: %08x PPDSR: %08x\n",
+ getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET),
+ getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_PPDSR_OFFSET));
#endif
- lldbg(" PUSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n",
- getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
- getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET));
- lldbg(" ESR: %08x LSR: %08x ELSR: %08x FELLSR: %08x\n",
- getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET),
- getreg32(base + SAM_PIO_ELSR_OFFSET), getreg32(base + SAM_PIO_FELLSR_OFFSET));
- lldbg(" FRLHSR: %08x LOCKSR: %08x WPMR: %08x WPSR: %08x\n",
- getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET),
- getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
+ gpioinfo(" PUSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n",
+ getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
+ getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET));
+ gpioinfo(" ESR: %08x LSR: %08x ELSR: %08x FELLSR: %08x\n",
+ getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET),
+ getreg32(base + SAM_PIO_ELSR_OFFSET), getreg32(base + SAM_PIO_FELLSR_OFFSET));
+ gpioinfo(" FRLHSR: %08x LOCKSR: %08x WPMR: %08x WPSR: %08x\n",
+ getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET),
+ getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
- lldbg(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n",
- getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
- getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
+ gpioinfo(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n",
+ getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
+ getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
#ifdef CONFIG_ARCH_CHIP_SAM4E
- lldbg("SCHMITT: %08x DELAYR:%08x\n",
- getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DELAYR_OFFSET));
+ gpioinfo("SCHMITT: %08x DELAYR:%08x\n",
+ getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DELAYR_OFFSET));
#else
- lldbg("SCHMITT: %08x\n",
- getreg32(base + SAM_PIO_SCHMITT_OFFSET));
+ gpioinfo("SCHMITT: %08x\n",
+ getreg32(base + SAM_PIO_SCHMITT_OFFSET));
#endif
#endif
+
leave_critical_section(flags);
return OK;
}
diff --git a/arch/arm/src/sam34/sam_gpio.h b/arch/arm/src/sam34/sam_gpio.h
index f8f267ef5e39a95025affce1248a5e82c06d9707..a5cbe6e3e3fdc606624aa519d29674a608fa7a49 100644
--- a/arch/arm/src/sam34/sam_gpio.h
+++ b/arch/arm/src/sam34/sam_gpio.h
@@ -77,24 +77,12 @@
# undef CONFIG_SAM34_GPIO_IRQ
#endif
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_GPIO
-#endif
-
/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Inline Functions
+ * Public Function Prototypes
************************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
@@ -104,10 +92,6 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
/************************************************************************************
* Name: sam_gpioirqinitialize
*
@@ -202,7 +186,7 @@ void sam_gpioirqdisable(int irq);
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
int sam_dumpgpio(uint32_t pinset, const char *msg);
#else
# define sam_dumpgpio(p,m)
diff --git a/arch/arm/src/sam34/sam_hsmci.c b/arch/arm/src/sam34/sam_hsmci.c
index 21e9098cd5aecc3804eab568f5d86e75a9424c4a..fa4073d6a2799c877ef66df8b2fb4d6a6a0365e4 100644
--- a/arch/arm/src/sam34/sam_hsmci.c
+++ b/arch/arm/src/sam34/sam_hsmci.c
@@ -104,7 +104,7 @@
#define SAM34_HSMCI_PRIO NVIC_SYSH_PRIORITY_DEFAULT
-#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_VERBOSE)
+#ifndef CONFIG_DEBUG_MEMCARD_INFO
# undef CONFIG_SAM34_HSMCI_CMDDEBUG
# undef CONFIG_SAM34_HSMCI_XFRDEBUG
#endif
@@ -831,38 +831,38 @@ static void sam_hsmcisample(struct sam_hsmciregs_s *regs)
#if defined(CONFIG_SAM34_HSMCI_XFRDEBUG) || defined(CONFIG_SAM34_HSMCI_CMDDEBUG)
static void sam_hsmcidump(struct sam_hsmciregs_s *regs, const char *msg)
{
- fdbg("HSMCI Registers: %s\n", msg);
- fdbg(" MR[%08x]: %08x\n", SAM_HSMCI_MR, regs->mr);
- fdbg(" DTOR[%08x]: %08x\n", SAM_HSMCI_DTOR, regs->dtor);
- fdbg(" SDCR[%08x]: %08x\n", SAM_HSMCI_SDCR, regs->sdcr);
- fdbg(" ARGR[%08x]: %08x\n", SAM_HSMCI_ARGR, regs->argr);
- fdbg(" BLKR[%08x]: %08x\n", SAM_HSMCI_BLKR, regs->blkr);
- fdbg(" CSTOR[%08x]: %08x\n", SAM_HSMCI_CSTOR, regs->cstor);
- fdbg(" RSPR0[%08x]: %08x\n", SAM_HSMCI_RSPR0, regs->rsp0);
- fdbg(" RSPR1[%08x]: %08x\n", SAM_HSMCI_RSPR1, regs->rsp1);
- fdbg(" RSPR2[%08x]: %08x\n", SAM_HSMCI_RSPR2, regs->rsp2);
- fdbg(" RSPR3[%08x]: %08x\n", SAM_HSMCI_RSPR3, regs->rsp3);
- fdbg(" SR[%08x]: %08x\n", SAM_HSMCI_SR, regs->sr);
- fdbg(" IMR[%08x]: %08x\n", SAM_HSMCI_IMR, regs->imr);
+ mcinfo("HSMCI Registers: %s\n", msg);
+ mcinfo(" MR[%08x]: %08x\n", SAM_HSMCI_MR, regs->mr);
+ mcinfo(" DTOR[%08x]: %08x\n", SAM_HSMCI_DTOR, regs->dtor);
+ mcinfo(" SDCR[%08x]: %08x\n", SAM_HSMCI_SDCR, regs->sdcr);
+ mcinfo(" ARGR[%08x]: %08x\n", SAM_HSMCI_ARGR, regs->argr);
+ mcinfo(" BLKR[%08x]: %08x\n", SAM_HSMCI_BLKR, regs->blkr);
+ mcinfo(" CSTOR[%08x]: %08x\n", SAM_HSMCI_CSTOR, regs->cstor);
+ mcinfo(" RSPR0[%08x]: %08x\n", SAM_HSMCI_RSPR0, regs->rsp0);
+ mcinfo(" RSPR1[%08x]: %08x\n", SAM_HSMCI_RSPR1, regs->rsp1);
+ mcinfo(" RSPR2[%08x]: %08x\n", SAM_HSMCI_RSPR2, regs->rsp2);
+ mcinfo(" RSPR3[%08x]: %08x\n", SAM_HSMCI_RSPR3, regs->rsp3);
+ mcinfo(" SR[%08x]: %08x\n", SAM_HSMCI_SR, regs->sr);
+ mcinfo(" IMR[%08x]: %08x\n", SAM_HSMCI_IMR, regs->imr);
#if defined(CONFIG_ARCH_CHIP_SAM3U)
- fdbg(" DMA[%08x]: %08x\n", SAM_HSMCI_DMA, regs->dma);
+ mcinfo(" DMA[%08x]: %08x\n", SAM_HSMCI_DMA, regs->dma);
#endif
- fdbg(" CFG[%08x]: %08x\n", SAM_HSMCI_CFG, regs->cfg);
- fdbg(" WPMR[%08x]: %08x\n", SAM_HSMCI_WPMR, regs->wpmr);
- fdbg(" WPSR[%08x]: %08x\n", SAM_HSMCI_WPSR, regs->wpsr);
+ mcinfo(" CFG[%08x]: %08x\n", SAM_HSMCI_CFG, regs->cfg);
+ mcinfo(" WPMR[%08x]: %08x\n", SAM_HSMCI_WPMR, regs->wpmr);
+ mcinfo(" WPSR[%08x]: %08x\n", SAM_HSMCI_WPSR, regs->wpsr);
#ifdef CONFIG_SAM34_PDCA
- fdbg("HSMCI PDC Registers:\n");
- fdbg(" RPR[%08x]: %08x\n", SAM_HSMCI_PDC_RPR, regs->pdc_rpr);
- fdbg(" RCR[%08x]: %08x\n", SAM_HSMCI_PDC_RCR, regs->pdc_rcr);
- fdbg(" TPR[%08x]: %08x\n", SAM_HSMCI_PDC_TPR, regs->pdc_tpr);
- fdbg(" TCR[%08x]: %08x\n", SAM_HSMCI_PDC_TCR, regs->pdc_tcr);
- fdbg(" RNPR[%08x]: %08x\n", SAM_HSMCI_PDC_RNPR, regs->pdc_rnpr);
- fdbg(" RNCR[%08x]: %08x\n", SAM_HSMCI_PDC_RNCR, regs->pdc_rncr);
- fdbg(" TNPR[%08x]: %08x\n", SAM_HSMCI_PDC_TNPR, regs->pdc_tnpr);
- fdbg(" TNCR[%08x]: %08x\n", SAM_HSMCI_PDC_TNCR, regs->pdc_tncr);
-//fdbg(" TCR[%08x]: %08x\n", SAM_HSMCI_PDC_PTCR, regs->pdc_ptcr);
- fdbg(" PTSR[%08x]: %08x\n", SAM_HSMCI_PDC_PTSR, regs->pdc_ptsr);
+ mcinfo("HSMCI PDC Registers:\n");
+ mcinfo(" RPR[%08x]: %08x\n", SAM_HSMCI_PDC_RPR, regs->pdc_rpr);
+ mcinfo(" RCR[%08x]: %08x\n", SAM_HSMCI_PDC_RCR, regs->pdc_rcr);
+ mcinfo(" TPR[%08x]: %08x\n", SAM_HSMCI_PDC_TPR, regs->pdc_tpr);
+ mcinfo(" TCR[%08x]: %08x\n", SAM_HSMCI_PDC_TCR, regs->pdc_tcr);
+ mcinfo(" RNPR[%08x]: %08x\n", SAM_HSMCI_PDC_RNPR, regs->pdc_rnpr);
+ mcinfo(" RNCR[%08x]: %08x\n", SAM_HSMCI_PDC_RNCR, regs->pdc_rncr);
+ mcinfo(" TNPR[%08x]: %08x\n", SAM_HSMCI_PDC_TNPR, regs->pdc_tnpr);
+ mcinfo(" TNCR[%08x]: %08x\n", SAM_HSMCI_PDC_TNCR, regs->pdc_tncr);
+//mcinfo(" TCR[%08x]: %08x\n", SAM_HSMCI_PDC_PTCR, regs->pdc_ptcr);
+ mcinfo(" PTSR[%08x]: %08x\n", SAM_HSMCI_PDC_PTSR, regs->pdc_ptsr);
#endif
}
#endif
@@ -1083,7 +1083,7 @@ static void sam_eventtimeout(int argc, uint32_t arg)
/* Yes.. wake up any waiting threads */
sam_endwait(priv, SDIOWAIT_TIMEOUT);
- flldbg("Timeout\n");
+ mcerr("ERROR: Timeout\n");
}
}
@@ -1278,7 +1278,7 @@ static int sam_interrupt(int irq, void *context)
{
/* Yes.. Was it some kind of timeout error? */
- flldbg("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
+ mcerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
if ((pending & HSMCI_DATA_TIMEOUT_ERRORS) != 0)
{
/* Yes.. Terminate with a timeout. */
@@ -1320,8 +1320,8 @@ static int sam_interrupt(int irq, void *context)
{
/* Yes.. Was the error some kind of timeout? */
- fllvdbg("ERROR: events: %08x SR: %08x\n",
- priv->cmdrmask, enabled);
+ mcerr("ERROR: events: %08x SR: %08x\n",
+ priv->cmdrmask, enabled);
if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
{
@@ -1754,7 +1754,7 @@ static int sam_sendcmd(FAR struct sdio_dev_s *dev,
/* Write the fully decorated command to CMDR */
- fvdbg("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
+ mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
putreg32(regval, SAM_HSMCI_CMDR);
sam_cmdsample1(SAMPLENDX_AFTER_CMDR);
return OK;
@@ -1933,7 +1933,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
{
/* Yes.. Was the error some kind of timeout? */
- fdbg("ERROR: cmd: %08x events: %08x SR: %08x\n",
+ mcerr("ERROR: cmd: %08x events: %08x SR: %08x\n",
cmd, priv->cmdrmask, sr);
if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
@@ -1963,7 +1963,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
}
else if (--timeout <= 0)
{
- fdbg("ERROR: Timeout cmd: %08x events: %08x SR: %08x\n",
+ mcerr("ERROR: Timeout cmd: %08x events: %08x SR: %08x\n",
cmd, priv->cmdrmask, sr);
priv->wkupevent = SDIOWAIT_TIMEOUT;
@@ -2035,10 +2035,10 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev,
* 0 1 End bit
*/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!rshort)
{
- fdbg("ERROR: rshort=NULL\n");
+ mcerr("ERROR: rshort=NULL\n");
ret = -EINVAL;
}
@@ -2050,7 +2050,7 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev,
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE &&
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE)
{
- fdbg("ERROR: Wrong response CMD=%08x\n", cmd);
+ mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
ret = -EINVAL;
}
else
@@ -2095,12 +2095,12 @@ static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong
* 0 1 End bit
*/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
/* Check that R1 is the correct response to this command */
if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE)
{
- fdbg("ERROR: Wrong response CMD=%08x\n", cmd);
+ mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
ret = -EINVAL;
}
else
@@ -2282,7 +2282,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev,
1, (uint32_t)priv);
if (ret != OK)
{
- fdbg("ERROR: wd_start failed: %d\n", ret);
+ mcerr("ERROR: wd_start failed: %d\n", ret);
}
}
@@ -2348,7 +2348,7 @@ static void sam_callbackenable(FAR struct sdio_dev_s *dev,
{
struct sam_dev_s *priv = (struct sam_dev_s *)dev;
- fvdbg("eventset: %02x\n", eventset);
+ mcinfo("eventset: %02x\n", eventset);
DEBUGASSERT(priv != NULL);
priv->cbevents = eventset;
@@ -2384,7 +2384,7 @@ static int sam_registercallback(FAR struct sdio_dev_s *dev,
/* Disable callbacks and register this callback and is argument */
- fvdbg("Register %p(%p)\n", callback, arg);
+ mcinfo("Register %p(%p)\n", callback, arg);
DEBUGASSERT(priv != NULL);
priv->cbevents = 0;
@@ -2472,7 +2472,8 @@ static int sam_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
#ifdef CONFIG_SAM34_PDCA
modifyreg32(SAM_HSMCI_MR, 0, HSMCI_MR_PDCMODE);
- fdbg("SAM_HSMCI_MR = 0x%08X\n", getreg32(SAM_HSMCI_MR));
+ mcinfo("SAM_HSMCI_MR = 0x%08X\n", getreg32(SAM_HSMCI_MR));
+
putreg32((uint32_t)buffer, SAM_HSMCI_PDC_RPR);
putreg32(buflen/4, SAM_HSMCI_PDC_RCR);
putreg32(PDC_PTCR_RXTEN, SAM_HSMCI_PDC_PTCR);
@@ -2541,7 +2542,8 @@ static int sam_dmasendsetup(FAR struct sdio_dev_s *dev,
#ifdef CONFIG_SAM34_PDCA
modifyreg32(SAM_HSMCI_MR, 0, HSMCI_MR_PDCMODE);
- fdbg("SAM_HSMCI_MR = 0x%08X\n", getreg32(SAM_HSMCI_MR));
+ mcinfo("SAM_HSMCI_MR = 0x%08X\n", getreg32(SAM_HSMCI_MR));
+
putreg32((uint32_t)buffer, SAM_HSMCI_PDC_TPR);
putreg32(buflen/4, SAM_HSMCI_PDC_TCR);
putreg32(PDC_PTCR_TXTEN, SAM_HSMCI_PDC_PTCR);
@@ -2581,7 +2583,7 @@ static void sam_callback(void *arg)
/* Is a callback registered? */
DEBUGASSERT(priv != NULL);
- fvdbg("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
+ mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
if (priv->callback)
@@ -2626,14 +2628,14 @@ static void sam_callback(void *arg)
{
/* Yes.. queue it */
- fllvdbg("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
+ mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
(void)work_queue(LPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
}
else
{
/* No.. then just call the callback here */
- fvdbg("Callback to %p(%p)\n", priv->callback, priv->cbarg);
+ mcinfo("Callback to %p(%p)\n", priv->callback, priv->cbarg);
priv->callback(priv->cbarg);
}
}
@@ -2663,7 +2665,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
struct sam_dev_s *priv = &g_sdiodev;
- fdbg("slotno: %d\n", slotno);
+ mcinfo("slotno: %d\n", slotno);
/* Initialize the HSMCI slot structure */
@@ -2741,7 +2743,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
priv->cdstatus &= ~SDIO_STATUS_PRESENT;
}
- fllvdbg("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
+ mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
/* Perform any requested callback if the status has changed */
@@ -2786,7 +2788,7 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED;
}
- fvdbg("cdstatus: %02x\n", priv->cdstatus);
+ mcinfo("cdstatus: %02x\n", priv->cdstatus);
leave_critical_section(flags);
}
#endif /* CONFIG_SAM34_HSMCI */
diff --git a/arch/arm/src/sam34/sam_irq.c b/arch/arm/src/sam34/sam_irq.c
index 2a8b2f990ed4c6b582a9dca47e5d907927e4e606..68f1777434725792819d5731686ce8acddcffbc8 100644
--- a/arch/arm/src/sam34/sam_irq.c
+++ b/arch/arm/src/sam34/sam_irq.c
@@ -108,52 +108,54 @@ extern uint32_t _vectors[];
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_IRQ)
+#if defined(CONFIG_DEBUG_IRQ_INFO)
static void sam_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
- lldbg("NVIC (%s, irq=%d):\n", msg, irq);
- lldbg(" INTCTRL: %08x VECTAB: %08x\n",
- getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
+
+ irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
+ irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
+ getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
- lldbg(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
- getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
- getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
+ irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
+ getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
+ getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
- lldbg(" IRQ ENABLE: %08x %08x %08x\n",
- getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
- getreg32(NVIC_IRQ64_95_ENABLE));
- lldbg(" SYSH_PRIO: %08x %08x %08x\n",
- getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
- getreg32(NVIC_SYSH12_15_PRIORITY));
- lldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
- getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
+ irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
+ getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
+ getreg32(NVIC_IRQ64_95_ENABLE));
+ irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
+ getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
+ getreg32(NVIC_SYSH12_15_PRIORITY));
+ irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
+ getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
#if SAM_IRQ_NEXTINT > 15
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
- getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
+ getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
#endif
#if SAM_IRQ_NEXTINT > 31
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
- getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
+ getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
#endif
#if SAM_IRQ_NEXTINT > 47
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
- getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
+ getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
#endif
#if SAM_IRQ_NEXTINT > 63
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
- getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
+ getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
#endif
#if SAM_IRQ_NEXTINT > 79
# warning Missing logic
#endif
+
leave_critical_section(flags);
}
#else
@@ -171,11 +173,11 @@ static void sam_dumpnvic(const char *msg, int irq)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
static int sam_nmi(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! NMI received\n");
+ _err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
@@ -183,7 +185,7 @@ static int sam_nmi(int irq, FAR void *context)
static int sam_busfault(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
+ _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
}
@@ -191,7 +193,7 @@ static int sam_busfault(int irq, FAR void *context)
static int sam_usagefault(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
+ _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
}
@@ -199,7 +201,7 @@ static int sam_usagefault(int irq, FAR void *context)
static int sam_pendsv(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! PendSV received\n");
+ _err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
@@ -207,7 +209,7 @@ static int sam_pendsv(int irq, FAR void *context)
static int sam_dbgmonitor(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Debug Monitor received\n");
+ _err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
}
@@ -215,7 +217,7 @@ static int sam_dbgmonitor(int irq, FAR void *context)
static int sam_reserved(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Reserved interrupt\n");
+ _err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
@@ -456,7 +458,7 @@ void up_irqinitialize(void)
/* Attach all other processor exceptions (except reset and sys tick) */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
irq_attach(SAM_IRQ_NMI, sam_nmi);
#ifndef CONFIG_ARM_MPU
irq_attach(SAM_IRQ_MEMFAULT, up_memfault);
diff --git a/arch/arm/src/sam34/sam_rtc.c b/arch/arm/src/sam34/sam_rtc.c
index 8dbe4e9e1af6602dddee528887cabf0772b44745..c4c548cc9f987152aa3c23e0b31309b89e2d89a7 100644
--- a/arch/arm/src/sam34/sam_rtc.c
+++ b/arch/arm/src/sam34/sam_rtc.c
@@ -80,30 +80,6 @@
#define RTC_MAGIC 0xdeadbeef
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_RTC
-#endif
-
-/* Constants ************************************************************************/
-
-/* Debug ****************************************************************************/
-
-#ifdef CONFIG_DEBUG_RTC
-# define rtcdbg dbg
-# define rtcvdbg vdbg
-# define rtclldbg lldbg
-# define rtcllvdbg llvdbg
-#else
-# define rtcdbg(x...)
-# define rtcvdbg(x...)
-# define rtclldbg(x...)
-# define rtcllvdbg(x...)
-#endif
-
-/************************************************************************************
- * Private Types
- ************************************************************************************/
-
/************************************************************************************
* Private Data
************************************************************************************/
@@ -146,19 +122,19 @@ uint32_t g_rtt_offset = 0;
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_RTC
+#ifdef CONFIG_DEBUG_RTC_INFO
static void rtc_dumpregs(FAR const char *msg)
{
- rtclldbg("%s:\n", msg);
- rtclldbg(" CR: %08x\n", getreg32(SAM_RTC_CR));
- rtclldbg(" MR: %08x\n", getreg32(SAM_RTC_MR));
- rtclldbg(" TIMR: %08x\n", getreg32(SAM_RTC_TIMR));
- rtclldbg(" CALR: %08x\n", getreg32(SAM_RTC_CALR));
- rtclldbg(" TIMALR: %08x\n", getreg32(SAM_RTC_TIMALR));
- rtclldbg(" CALALR: %08x\n", getreg32(SAM_RTC_CALALR));
- rtclldbg(" SR: %08x\n", getreg32(SAM_RTC_SR));
- rtclldbg(" IMR: %08x\n", getreg32(SAM_RTC_IMR));
- rtclldbg(" VER: %08x\n", getreg32(SAM_RTC_VER));
+ rtcinfo("%s:\n", msg);
+ rtcinfo(" CR: %08x\n", getreg32(SAM_RTC_CR));
+ rtcinfo(" MR: %08x\n", getreg32(SAM_RTC_MR));
+ rtcinfo(" TIMR: %08x\n", getreg32(SAM_RTC_TIMR));
+ rtcinfo(" CALR: %08x\n", getreg32(SAM_RTC_CALR));
+ rtcinfo(" TIMALR: %08x\n", getreg32(SAM_RTC_TIMALR));
+ rtcinfo(" CALALR: %08x\n", getreg32(SAM_RTC_CALALR));
+ rtcinfo(" SR: %08x\n", getreg32(SAM_RTC_SR));
+ rtcinfo(" IMR: %08x\n", getreg32(SAM_RTC_IMR));
+ rtcinfo(" VER: %08x\n", getreg32(SAM_RTC_VER));
}
#else
# define rtc_dumpregs(msg)
@@ -178,16 +154,16 @@ static void rtc_dumpregs(FAR const char *msg)
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_RTC
+#ifdef CONFIG_DEBUG_RTC_INFO
static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg)
{
- rtclldbg("%s:\n", msg);
- rtclldbg(" tm_sec: %08x\n", tp->tm_sec);
- rtclldbg(" tm_min: %08x\n", tp->tm_min);
- rtclldbg(" tm_hour: %08x\n", tp->tm_hour);
- rtclldbg(" tm_mday: %08x\n", tp->tm_mday);
- rtclldbg(" tm_mon: %08x\n", tp->tm_mon);
- rtclldbg(" tm_year: %08x\n", tp->tm_year);
+ rtcinfo("%s:\n", msg);
+ rtcinfo(" tm_sec: %08x\n", tp->tm_sec);
+ rtcinfo(" tm_min: %08x\n", tp->tm_min);
+ rtcinfo(" tm_hour: %08x\n", tp->tm_hour);
+ rtcinfo(" tm_mday: %08x\n", tp->tm_mday);
+ rtcinfo(" tm_mon: %08x\n", tp->tm_mon);
+ rtcinfo(" tm_year: %08x\n", tp->tm_year);
}
#else
# define rtc_dumptime(tp, msg)
@@ -298,7 +274,7 @@ static int rtc_interrupt(int irq, void *context)
ret = work_queue(LPWORK, &g_alarmwork, rtc_worker, NULL, 0);
if (ret < 0)
{
- rtclldbg("ERRPR: work_queue failed: %d\n", ret);
+ rtcerr("ERROR: work_queue failed: %d\n", ret);
}
/* Disable any further alarm interrupts */
diff --git a/arch/arm/src/sam34/sam_rtt.c b/arch/arm/src/sam34/sam_rtt.c
index a0c94f7ef77e0323eafb6009fec459100fa06603..9df244cccea9fa67875b4fd01569a62e36b050ce 100644
--- a/arch/arm/src/sam34/sam_rtt.c
+++ b/arch/arm/src/sam34/sam_rtt.c
@@ -74,18 +74,8 @@
/* Configuration ************************************************************/
-/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing the timer
- * driver. NOTE: that only lldbg types are used so that the output is
- * immediately available.
- */
-
-#ifdef CONFIG_DEBUG_RTT
-# define rttdbg lldbg
-# define rttvdbg llvdbg
-#else
-# define rttdbg(x...)
-# define rttvdbg(x...)
+#ifndef CONFIG_DEBUG_TIMER_INFO
+# undef CONFIG_SAM34_RTT_REGDEBUG
#endif
/****************************************************************************
@@ -115,7 +105,7 @@ struct sam34_lowerhalf_s
****************************************************************************/
/* Register operations ******************************************************/
-#if defined(CONFIG_SAM34_RTT_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAM34_RTT_REGDEBUG
static uint32_t sam34_getreg(uint32_t addr);
static void sam34_putreg(uint32_t val, uint32_t addr);
#else
@@ -193,7 +183,7 @@ static inline uint32_t sam34_readvr(void)
*
****************************************************************************/
-#if defined(CONFIG_SAM34_RTT_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAM34_RTT_REGDEBUG
static uint32_t sam34_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@@ -214,7 +204,7 @@ static uint32_t sam34_getreg(uint32_t addr)
{
if (count == 4)
{
- lldbg("...\n");
+ tmrinfo("...\n");
}
return val;
@@ -231,7 +221,7 @@ static uint32_t sam34_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ tmrinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -243,7 +233,7 @@ static uint32_t sam34_getreg(uint32_t addr)
/* Show the register value read */
- lldbg("%08lx->%08lx\n", addr, val);
+ tmrinfo("%08lx->%08lx\n", addr, val);
return val;
}
#endif
@@ -256,12 +246,12 @@ static uint32_t sam34_getreg(uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_SAM34_RTT_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAM34_RTT_REGDEBUG
static void sam34_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- lldbg("%08lx<-%08lx\n", addr, val);
+ tmrinfo("%08lx<-%08lx\n", addr, val);
/* Write the value */
@@ -287,7 +277,7 @@ static int sam34_interrupt(int irq, FAR void *context)
{
FAR struct sam34_lowerhalf_s *priv = &g_tcdev;
- rttvdbg("Entry\n");
+ tmrinfo("Entry\n");
DEBUGASSERT(irq == SAM_IRQ_RTT);
/* Check if the interrupt is really pending */
@@ -373,7 +363,7 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower)
uint32_t mr;
uint32_t vr;
- rttvdbg("Entry\n");
+ tmrinfo("Entry\n");
DEBUGASSERT(priv);
if (priv->started)
@@ -433,7 +423,7 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower)
static int sam34_stop(FAR struct timer_lowerhalf_s *lower)
{
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
- rttvdbg("Entry\n");
+ tmrinfo("Entry\n");
DEBUGASSERT(priv);
if (!priv->started)
@@ -474,7 +464,7 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower,
{
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
- rttvdbg("Entry\n");
+ tmrinfo("Entry\n");
DEBUGASSERT(priv);
/* Return the status bit */
@@ -498,9 +488,9 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower,
status->timeleft = 1000000ULL*(sam34_getreg(SAM_RTT_AR) - sam34_readvr())/RTT_FCLK;
- rttvdbg(" flags : %08x\n", status->flags);
- rttvdbg(" timeout : %d\n", status->timeout);
- rttvdbg(" timeleft : %d\n", status->timeleft);
+ tmrinfo(" flags : %08x\n", status->flags);
+ tmrinfo(" timeout : %d\n", status->timeout);
+ tmrinfo(" timeleft : %d\n", status->timeleft);
return OK;
}
@@ -526,7 +516,7 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower,
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
DEBUGASSERT(priv);
- rttvdbg("Entry: timeout=%d\n", timeout);
+ tmrinfo("Entry: timeout=%d\n", timeout);
if (priv->started)
{
@@ -537,7 +527,7 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower,
if (timeout < 1 || timeout > RTT_MAXTIMEOUT)
{
- rttdbg("Cannot represent timeout=%lu > %lu\n",
+ tmrerr("ERROR: Cannot represent timeout=%lu > %lu\n",
timeout, RTT_MAXTIMEOUT);
return -ERANGE;
}
@@ -547,7 +537,7 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower,
timeout = (1000000ULL * priv->clkticks) / RTT_FCLK; /* Truncated timeout */
priv->adjustment = priv->timeout - timeout; /* Truncated time to be added to next interval (dither) */
- rttvdbg("fclk=%d clkticks=%d timout=%d, adjustment=%d\n",
+ tmrinfo("fclk=%d clkticks=%d timout=%d, adjustment=%d\n",
RTT_FCLK, priv->clkticks, priv->timeout, priv->adjustment);
return OK;
@@ -582,7 +572,7 @@ static tccb_t sam34_sethandler(FAR struct timer_lowerhalf_s *lower,
flags = enter_critical_section();
DEBUGASSERT(priv);
- rttvdbg("Entry: handler=%p\n", handler);
+ tmrinfo("Entry: handler=%p\n", handler);
/* Get the old handler return value */
@@ -623,7 +613,7 @@ static int sam34_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd,
int ret = -ENOTTY;
DEBUGASSERT(priv);
- rttvdbg("Entry: cmd=%d arg=%ld\n", cmd, arg);
+ tmrinfo("Entry: cmd=%d arg=%ld\n", cmd, arg);
UNUSED(priv);
return ret;
@@ -653,7 +643,7 @@ void sam_rttinitialize(FAR const char *devpath)
{
FAR struct sam34_lowerhalf_s *priv = &g_tcdev;
- rttvdbg("Entry: devpath=%s\n", devpath);
+ tmrinfo("Entry: devpath=%s\n", devpath);
/* Initialize the driver state structure. Here we assume: (1) the state
* structure lies in .bss and was zeroed at reset time. (2) This function
diff --git a/arch/arm/src/sam34/sam_spi.c b/arch/arm/src/sam34/sam_spi.c
index 424d9218449e6f8185d098442a54e03398f7c69c..4b7f1dba7e8b4a3e23be10979bacfb241a0ee33d 100644
--- a/arch/arm/src/sam34/sam_spi.c
+++ b/arch/arm/src/sam34/sam_spi.c
@@ -102,7 +102,11 @@
# endif
#endif
-#ifndef CONFIG_SAM34_SPI_DMA
+#ifndef CONFIG_DEBUG_SPI_INFO
+# undef CONFIG_SAM34_SPI_REGDEBUG
+#endif
+
+#ifndef CONFIG_DEBUG_DMA_INFO
# undef CONFIG_SAM34_SPI_DMADEBUG
#endif
@@ -132,31 +136,10 @@
#define DMA_TIMEOUT_TICKS MSEC2TICK(DMA_TIMEOUT_MS)
/* Debug *******************************************************************/
-/* Check if SPI debut is enabled (non-standard.. no support in
- * include/debug.h
- */
+/* Check if SPI debut is enabled */
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# undef CONFIG_DEBUG_SPI
+#ifndef CONFIG_DEBUG_DMA_INFO
# undef CONFIG_SAM34_SPI_DMADEBUG
-# undef CONFIG_SAM34_SPI_REGDEBUG
-#endif
-
-#ifndef CONFIG_DEBUG_DMA
-# undef CONFIG_SAM34_SPI_DMADEBUG
-#endif
-
-#ifdef CONFIG_DEBUG_SPI
-# define spidbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define spivdbg lldbg
-# else
-# define spivdbg(x...)
-# endif
-#else
-# define spidbg(x...)
-# define spivdbg(x...)
#endif
#define DMA_INITIAL 0
@@ -252,7 +235,7 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value,
unsigned int offset);
static inline struct sam_spidev_s *spi_device(struct sam_spics_s *spics);
-#if defined(CONFIG_DEBUG_SPI) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_SPI_INFO
static void spi_dumpregs(struct sam_spidev_s *spi, const char *msg);
#else
# define spi_dumpregs(spi,msg)
@@ -441,7 +424,7 @@ static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, uint32_t value,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", spi->ntimes);
+ spiinfo("...[Repeats %d times]...\n", spi->ntimes);
}
/* Save information about the new access */
@@ -475,7 +458,7 @@ static inline uint32_t spi_getreg(struct sam_spidev_s *spi,
#ifdef CONFIG_SAM34_SPI_REGDEBUG
if (spi_checkreg(spi, false, value, address))
{
- lldbg("%08x->%08x\n", address, value);
+ spiinfo("%08x->%08x\n", address, value);
}
#endif
@@ -498,7 +481,7 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value,
#ifdef CONFIG_SAM34_SPI_REGDEBUG
if (spi_checkreg(spi, true, value, address))
{
- lldbg("%08x<-%08x\n", address, value);
+ spiinfo("%08x<-%08x\n", address, value);
}
#endif
@@ -520,20 +503,20 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value,
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_SPI) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_SPI_INFO
static void spi_dumpregs(struct sam_spidev_s *spi, const char *msg)
{
- spivdbg("%s:\n", msg);
- spivdbg(" MR:%08x SR:%08x IMR:%08x\n",
+ spiinfo("%s:\n", msg);
+ spiinfo(" MR:%08x SR:%08x IMR:%08x\n",
getreg32(spi->base + SAM_SPI_MR_OFFSET),
getreg32(spi->base + SAM_SPI_SR_OFFSET),
getreg32(spi->base + SAM_SPI_IMR_OFFSET));
- spivdbg(" CSR0:%08x CSR1:%08x CSR2:%08x CSR3:%08x\n",
+ spiinfo(" CSR0:%08x CSR1:%08x CSR2:%08x CSR3:%08x\n",
getreg32(spi->base + SAM_SPI_CSR0_OFFSET),
getreg32(spi->base + SAM_SPI_CSR1_OFFSET),
getreg32(spi->base + SAM_SPI_CSR2_OFFSET),
getreg32(spi->base + SAM_SPI_CSR3_OFFSET));
- spivdbg(" WPCR:%08x WPSR:%08x\n",
+ spiinfo(" WPCR:%08x WPSR:%08x\n",
getreg32(spi->base + SAM_SPI_WPCR_OFFSET),
getreg32(spi->base + SAM_SPI_WPSR_OFFSET));
}
@@ -893,7 +876,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock)
struct sam_spics_s *spics = (struct sam_spics_s *)dev;
struct sam_spidev_s *spi = spi_device(spics);
- spivdbg("lock=%d\n", lock);
+ spiinfo("lock=%d\n", lock);
if (lock)
{
/* Take the semaphore (perhaps waiting) */
@@ -941,10 +924,10 @@ static void spi_select(struct spi_dev_s *dev, enum spi_dev_e devid,
/* Are we selecting or de-selecting the device? */
- spivdbg("selected=%d\n", selected);
+ spiinfo("selected=%d\n", selected);
if (selected)
{
- spivdbg("cs=%d\n", spics->cs);
+ spiinfo("cs=%d\n", spics->cs);
/* Before writing the TDR, the PCS field in the SPI_MR register must be set
* in order to select a slave.
@@ -999,7 +982,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
uint32_t regval;
unsigned int offset;
- spivdbg("cs=%d frequency=%d\n", spics->cs, frequency);
+ spiinfo("cs=%d frequency=%d\n", spics->cs, frequency);
/* Check if the requested frequency is the same as the frequency selection */
@@ -1069,14 +1052,14 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
/* Calculate the new actual frequency */
actual = SAM_SPI_CLOCK / scbr;
- spivdbg("csr[offset=%02x]=%08x actual=%d\n", offset, regval, actual);
+ spiinfo("csr[offset=%02x]=%08x actual=%d\n", offset, regval, actual);
/* Save the frequency setting */
spics->frequency = frequency;
spics->actual = actual;
- spidbg("Frequency %d->%d\n", frequency, actual);
+ spiinfo("Frequency %d->%d\n", frequency, actual);
return actual;
}
@@ -1102,7 +1085,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
uint32_t regval;
unsigned int offset;
- spivdbg("cs=%d mode=%d\n", spics->cs, mode);
+ spiinfo("cs=%d mode=%d\n", spics->cs, mode);
/* Has the mode changed? */
@@ -1145,7 +1128,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
}
spi_putreg(spi, regval, offset);
- spivdbg("csr[offset=%02x]=%08x\n", offset, regval);
+ spiinfo("csr[offset=%02x]=%08x\n", offset, regval);
/* Save the mode so that subsequent re-configurations will be faster */
@@ -1175,7 +1158,7 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
uint32_t regval;
unsigned int offset;
- spivdbg("cs=%d nbits=%d\n", spics->cs, nbits);
+ spiinfo("cs=%d nbits=%d\n", spics->cs, nbits);
DEBUGASSERT(spics && nbits > 7 && nbits < 17);
/* Has the number of bits changed? */
@@ -1190,7 +1173,7 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
regval |= SPI_CSR_BITS(nbits);
spi_putreg(spi, regval, offset);
- spivdbg("csr[offset=%02x]=%08x\n", offset, regval);
+ spiinfo("csr[offset=%02x]=%08x\n", offset, regval);
/* Save the selection so the subsequence re-configurations will be faster */
@@ -1228,7 +1211,7 @@ static uint16_t spi_send(struct spi_dev_s *dev, uint16_t wd)
rxbyte = (uint8_t)0;
spi_exchange(dev, &txbyte, &rxbyte, 1);
- spivdbg("Sent %02x received %02x\n", txbyte, rxbyte);
+ spiinfo("Sent %02x received %02x\n", txbyte, rxbyte);
return (uint16_t)rxbyte;
}
@@ -1276,7 +1259,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
uint8_t *rxptr8;
uint8_t *txptr8;
- spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
+ spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
/* Set up PCS bits */
@@ -1422,7 +1405,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
return;
}
- spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
+ spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
spics = (struct sam_spics_s *)dev;
spi = spi_device(spics);
@@ -1543,7 +1526,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
ret = sam_dmarxsetup(spics->rxdma, regaddr, memaddr, nwords);
if (ret < 0)
{
- dmadbg("ERROR: sam_dmarxsetup failed: %d\n", ret);
+ dmaerr("ERROR: sam_dmarxsetup failed: %d\n", ret);
return;
}
@@ -1557,7 +1540,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
ret = sam_dmatxsetup(spics->txdma, regaddr, memaddr, nwords);
if (ret < 0)
{
- dmadbg("ERROR: sam_dmatxsetup failed: %d\n", ret);
+ dmaerr("ERROR: sam_dmatxsetup failed: %d\n", ret);
return;
}
@@ -1569,7 +1552,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
ret = sam_dmastart(spics->rxdma, spi_rxcallback, (void *)spics);
if (ret < 0)
{
- dmadbg("ERROR: RX sam_dmastart failed: %d\n", ret);
+ dmaerr("ERROR: RX sam_dmastart failed: %d\n", ret);
return;
}
@@ -1578,7 +1561,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
ret = sam_dmastart(spics->txdma, spi_txcallback, (void *)spics);
if (ret < 0)
{
- dmadbg("ERROR: RX sam_dmastart failed: %d\n", ret);
+ dmaerr("ERROR: RX sam_dmastart failed: %d\n", ret);
sam_dmastop(spics->rxdma);
return;
}
@@ -1600,7 +1583,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
(wdentry_t)spi_dmatimeout, 1, (uint32_t)spics);
if (ret != OK)
{
- spidbg("ERROR: wd_start failed: %d\n", ret);
+ spierr("ERROR: wd_start failed: %d\n", ret);
}
/* Wait for the DMA complete */
@@ -1651,7 +1634,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
if (spics->result)
{
- spidbg("ERROR: DMA failed with result: %d\n", spics->result);
+ spierr("ERROR: DMA failed with result: %d\n", spics->result);
}
}
#endif /* CONFIG_SAM34_SPI_DMA */
@@ -1745,7 +1728,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
/* The support SAM parts have only a single SPI port */
- spivdbg("port: %d csno: %d spino: %d\n", port, csno, spino);
+ spiinfo("port: %d csno: %d spino: %d\n", port, csno, spino);
DEBUGASSERT(csno >= 0 && csno <= SAM_SPI_NCS);
#if defined(CONFIG_SAM34_SPI0) && defined(CONFIG_SAM34_SPI1)
@@ -1764,7 +1747,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
spics = (struct sam_spics_s *)zalloc(sizeof(struct sam_spics_s));
if (!spics)
{
- spidbg("ERROR: Failed to allocate a chip select structure\n");
+ spierr("ERROR: Failed to allocate a chip select structure\n");
return NULL;
}
@@ -1787,7 +1770,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
spics->rxdma = sam_dmachannel(0);
if (!spics->rxdma)
{
- spidbg("ERROR: Failed to allocate the RX DMA channel\n");
+ spierr("ERROR: Failed to allocate the RX DMA channel\n");
spics->candma = false;
}
}
@@ -1797,7 +1780,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
spics->txdma = sam_dmachannel(0);
if (!spics->txdma)
{
- spidbg("ERROR: Failed to allocate the TX DMA channel\n");
+ spierr("ERROR: Failed to allocate the TX DMA channel\n");
sam_dmafree(spics->rxdma);
spics->rxdma = NULL;
spics->candma = false;
@@ -1924,7 +1907,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
spi_putreg(spi, regval, offset);
spics->nbits = 8;
- spivdbg("csr[offset=%02x]=%08x\n", offset, regval);
+ spiinfo("csr[offset=%02x]=%08x\n", offset, regval);
return &spics->spidev;
}
diff --git a/arch/arm/src/sam34/sam_start.c b/arch/arm/src/sam34/sam_start.c
index dc1d449808ab653ad2d43a1d5730a745c740451b..abae1da7615ee1040fe70e7d33fd8d480ce86b1f 100644
--- a/arch/arm/src/sam34/sam_start.c
+++ b/arch/arm/src/sam34/sam_start.c
@@ -88,7 +88,7 @@ void __start(void) __attribute__ ((no_instrument_function));
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) up_lowputc(c)
#else
# define showprogress(c)
diff --git a/arch/arm/src/sam34/sam_tc.c b/arch/arm/src/sam34/sam_tc.c
index a95fa495273d1f392a2491705ea48ec45f254790..369aa7323a5e079a99db7e228fdd083be0a951f8 100644
--- a/arch/arm/src/sam34/sam_tc.c
+++ b/arch/arm/src/sam34/sam_tc.c
@@ -63,6 +63,12 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+/* Configuration ************************************************************/
+
+#ifndef CONFIG_DEBUG_TIMER_INFO
+# undef CONFIG_SAM34_TC_REGDEBUG
+#endif
+
/* Clocking *****************************************************************/
/* TODO: Allow selection of any of the input clocks */
@@ -70,22 +76,6 @@
#define TC_FCLK (BOARD_SCLK_FREQUENCY)
#define TC_MAXTIMEOUT ((1000000ULL * (1ULL + TC_RVALUE_MASK)) / TC_FCLK)
-/* Configuration ************************************************************/
-
-/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing the timer
- * driver. NOTE: that only lldbg types are used so that the output is
- * immediately available.
- */
-
-#ifdef CONFIG_DEBUG_TIMER
-# define tcdbg lldbg
-# define tcvdbg llvdbg
-#else
-# define tcdbg(x...)
-# define tcvdbg(x...)
-#endif
-
/****************************************************************************
* Private Types
****************************************************************************/
@@ -114,7 +104,7 @@ struct sam34_lowerhalf_s
****************************************************************************/
/* Register operations ******************************************************/
-#if defined(CONFIG_SAM34_TC_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAM34_TC_REGDEBUG
static uint32_t sam34_getreg(uint32_t addr);
static void sam34_putreg(uint32_t val, uint32_t addr);
#else
@@ -174,7 +164,7 @@ static struct sam34_lowerhalf_s g_tcdevs[6];
*
****************************************************************************/
-#if defined(CONFIG_SAM34_TC_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAM34_TC_REGDEBUG
static uint32_t sam34_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@@ -195,7 +185,7 @@ static uint32_t sam34_getreg(uint32_t addr)
{
if (count == 4)
{
- lldbg("...\n");
+ tmrinfo("...\n");
}
return val;
@@ -212,7 +202,7 @@ static uint32_t sam34_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ tmrinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -224,7 +214,7 @@ static uint32_t sam34_getreg(uint32_t addr)
/* Show the register value read */
- lldbg("%08lx->%08lx\n", addr, val);
+ tmrinfo("%08lx->%08lx\n", addr, val);
return val;
}
#endif
@@ -237,12 +227,12 @@ static uint32_t sam34_getreg(uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_SAM34_TC_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAM34_TC_REGDEBUG
static void sam34_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- lldbg("%08lx<-%08lx\n", addr, val);
+ tmrinfo("%08lx<-%08lx\n", addr, val);
/* Write the value */
@@ -268,7 +258,7 @@ static int sam34_interrupt(int irq, FAR void *context)
{
FAR struct sam34_lowerhalf_s *priv = &g_tcdevs[irq-SAM_IRQ_TC0];
- tcvdbg("Entry\n");
+ tmrinfo("Entry\n");
DEBUGASSERT((irq >= SAM_IRQ_TC0) && (irq <= SAM_IRQ_TC5));
/* Check if the interrupt is really pending */
@@ -299,7 +289,7 @@ static int sam34_interrupt(int irq, FAR void *context)
/* No handler or the handler returned false.. stop the timer */
sam34_stop((FAR struct timer_lowerhalf_s *)priv);
- tcvdbg("Stopped\n");
+ tmrinfo("Stopped\n");
}
/* TC_INT_CPCS is cleared by reading SAM_TCx_SR */
@@ -328,7 +318,7 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower)
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
uint32_t mr_val;
- tcvdbg("Entry\n");
+ tmrinfo("Entry\n");
DEBUGASSERT(priv);
if (priv->started)
@@ -382,7 +372,7 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower)
static int sam34_stop(FAR struct timer_lowerhalf_s *lower)
{
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
- tcvdbg("Entry\n");
+ tmrinfo("Entry\n");
DEBUGASSERT(priv);
if (!priv->started)
@@ -421,7 +411,7 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower,
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
uint32_t elapsed;
- tcvdbg("Entry\n");
+ tmrinfo("Entry\n");
DEBUGASSERT(priv);
/* Return the status bit */
@@ -446,9 +436,9 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower,
elapsed = sam34_getreg(priv->base + SAM_TC_CV_OFFSET);
status->timeleft = ((uint64_t)priv->timeout * elapsed) / (priv->clkticks + 1); /* TODO - check on this +1 */
- tcvdbg(" flags : %08x\n", status->flags);
- tcvdbg(" timeout : %d\n", status->timeout);
- tcvdbg(" timeleft : %d\n", status->timeleft);
+ tmrinfo(" flags : %08x\n", status->flags);
+ tmrinfo(" timeout : %d\n", status->timeout);
+ tmrinfo(" timeleft : %d\n", status->timeleft);
return OK;
}
@@ -480,14 +470,14 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower,
return -EPERM;
}
- tcvdbg("Entry: timeout=%d\n", timeout);
+ tmrinfo("Entry: timeout=%d\n", timeout);
/* Can this timeout be represented? */
if (timeout < 1 || timeout > TC_MAXTIMEOUT)
{
- tcdbg("Cannot represent timeout=%lu > %lu\n",
- timeout, TC_MAXTIMEOUT);
+ tmrerr("ERROR: Cannot represent timeout=%lu > %lu\n",
+ timeout, TC_MAXTIMEOUT);
return -ERANGE;
}
@@ -496,8 +486,8 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower,
timeout = (1000000ULL * priv->clkticks) / TC_FCLK; /* Truncated timeout */
priv->adjustment = priv->timeout - timeout; /* Truncated time to be added to next interval (dither) */
- tcvdbg("fclk=%d clkticks=%d timout=%d, adjustment=%d\n",
- TC_FCLK, priv->clkticks, priv->timeout, priv->adjustment);
+ tmrinfo("fclk=%d clkticks=%d timout=%d, adjustment=%d\n",
+ TC_FCLK, priv->clkticks, priv->timeout, priv->adjustment);
return OK;
}
@@ -531,7 +521,7 @@ static tccb_t sam34_sethandler(FAR struct timer_lowerhalf_s *lower,
flags = enter_critical_section();
DEBUGASSERT(priv);
- tcvdbg("Entry: handler=%p\n", handler);
+ tmrinfo("Entry: handler=%p\n", handler);
/* Get the old handler return value */
@@ -572,7 +562,7 @@ static int sam34_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd,
int ret = -ENOTTY;
DEBUGASSERT(priv);
- tcvdbg("Entry: cmd=%d arg=%ld\n", cmd, arg);
+ tmrinfo("Entry: cmd=%d arg=%ld\n", cmd, arg);
UNUSED(priv);
return ret;
@@ -602,7 +592,7 @@ void sam_tcinitialize(FAR const char *devpath, int irq)
{
FAR struct sam34_lowerhalf_s *priv = &g_tcdevs[irq-SAM_IRQ_TC0];
- tcvdbg("Entry: devpath=%s\n", devpath);
+ tmrinfo("Entry: devpath=%s\n", devpath);
DEBUGASSERT((irq >= SAM_IRQ_TC0) && (irq <= SAM_IRQ_TC5));
/* Initialize the driver state structure. Here we assume: (1) the state
diff --git a/arch/arm/src/sam34/sam_twi.c b/arch/arm/src/sam34/sam_twi.c
index f8c2f7f7caf6af014b1f80c981bcf5eea08b9752..6e4aae14271885d3f60bc02d3dfbfb9ba829e79d 100644
--- a/arch/arm/src/sam34/sam_twi.c
+++ b/arch/arm/src/sam34/sam_twi.c
@@ -85,6 +85,10 @@
# define CONFIG_SAM34_TWI1_FREQUENCY 100000
#endif
+#ifndef CONFIG_DEBUG_I2C_INFO
+# undef CONFIG_SAM34_TWI_REGDEBUG
+#endif
+
/* Driver internal definitions *************************************************/
#define TWI_TIMEOUT ((100 * CLK_TCK) / 1000) /* 100 mS */
@@ -95,21 +99,6 @@
#define TWI_MAX_FREQUENCY 66000000 /* Maximum TWI frequency */
-/* Debug ***********************************************************************/
-/* CONFIG_DEBUG_I2C + CONFIG_DEBUG enables general I2C debug output. */
-
-#ifdef CONFIG_DEBUG_I2C
-# define i2cdbg dbg
-# define i2cvdbg vdbg
-# define i2clldbg lldbg
-# define i2cllvdbg llvdbg
-#else
-# define i2cdbg(x...)
-# define i2cvdbg(x...)
-# define i2clldbg(x...)
-# define i2cllvdbg(x...)
-#endif
-
/****************************************************************************
* Private Types
****************************************************************************/
@@ -288,7 +277,7 @@ static bool twi_checkreg(struct twi_dev_s *priv, bool wr, uint32_t value,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", priv->ntimes);
+ i2cinfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@@ -320,7 +309,7 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address)
if (twi_checkreg(priv, false, value, address))
{
- lldbg("%08x->%08x\n", address, value);
+ i2cinfo("%08x->%08x\n", address, value);
}
return value;
@@ -341,7 +330,7 @@ static void twi_putabs(struct twi_dev_s *priv, uintptr_t address,
{
if (twi_checkreg(priv, true, value, address))
{
- lldbg("%08x<-%08x\n", address, value);
+ i2cinfo("%08x<-%08x\n", address, value);
}
putreg32(value, address);
@@ -401,9 +390,9 @@ static int twi_wait(struct twi_dev_s *priv)
do
{
- i2clldbg("TWI%d Waiting...\n", priv->twi);
+ i2cinfo("TWI%d Waiting...\n", priv->twi);
twi_takesem(&priv->waitsem);
- i2clldbg("TWI%d Awakened with result: %d\n", priv->twi, priv->result);
+ i2cinfo("TWI%d Awakened with result: %d\n", priv->twi, priv->result);
}
while (priv->result == -EBUSY);
@@ -460,7 +449,7 @@ static int twi_interrupt(struct twi_dev_s *priv)
imr = twi_getrel(priv, SAM_TWI_IMR_OFFSET);
pending = sr & imr;
- i2cllvdbg("TWI%d pending: %08x\n", priv->twi, pending);
+ i2cinfo("TWI%d pending: %08x\n", priv->twi, pending);
msg = priv->msg;
@@ -470,7 +459,7 @@ static int twi_interrupt(struct twi_dev_s *priv)
{
/* Wake up the thread with an I/O error indication */
- i2clldbg("ERROR: TWI%d pending: %08x\n", priv->twi, pending);
+ i2cerr("ERROR: TWI%d pending: %08x\n", priv->twi, pending);
twi_wakeup(priv, -EIO);
}
@@ -593,7 +582,7 @@ static void twi_timeout(int argc, uint32_t arg, ...)
{
struct twi_dev_s *priv = (struct twi_dev_s *)arg;
- i2clldbg("TWI%d Timeout!\n", priv->twi);
+ i2cerr("ERROR: TWI%d Timeout!\n", priv->twi);
twi_wakeup(priv, -ETIMEDOUT);
}
@@ -708,7 +697,7 @@ static int twi_transfer(FAR struct i2c_master_s *dev,
int ret;
DEBUGASSERT(dev != NULL);
- i2cvdbg("TWI%d count: %d\n", priv->twi, count);
+ i2cinfo("TWI%d count: %d\n", priv->twi, count);
/* Get exclusive access to the device */
@@ -742,7 +731,7 @@ static int twi_transfer(FAR struct i2c_master_s *dev,
ret = twi_wait(priv);
if (ret < 0)
{
- i2cdbg("ERROR: Transfer failed: %d\n", ret);
+ i2cerr("ERROR: Transfer failed: %d\n", ret);
}
leave_critical_section(flags);
@@ -842,7 +831,7 @@ static void twi_hw_initialize(struct twi_dev_s *priv, unsigned int pid,
uint32_t mck;
#endif
- i2cvdbg("TWI%d Initializing\n", priv->twi);
+ i2cinfo("TWI%d Initializing\n", priv->twi);
/* SVEN: TWI Slave Mode Enabled */
@@ -925,7 +914,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
uint32_t frequency;
unsigned int pid;
- i2cvdbg("Initializing TWI%d\n", bus);
+ i2cinfo("Initializing TWI%d\n", bus);
flags = enter_critical_section();
@@ -985,7 +974,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
#endif
{
leave_critical_section(flags);
- i2cdbg("ERROR: Unsupported bus: TWI%d\n", bus);
+ i2cerr("ERROR: Unsupported bus: TWI%d\n", bus);
return NULL;
}
@@ -1029,7 +1018,7 @@ int sam_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
{
struct twi_dev_s *priv = (struct twi_dev_s *) dev;
- i2cvdbg("TWI%d Un-initializing\n", priv->twi);
+ i2cinfo("TWI%d Un-initializing\n", priv->twi);
/* Disable interrupts */
diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c
index 0a74f5ba243bdaaddb41da57dc7ac2d50296e472..6fe76f4f57b3b5e851ff96ce00a90d8af798bbfe 100644
--- a/arch/arm/src/sam34/sam_udp.c
+++ b/arch/arm/src/sam34/sam_udp.c
@@ -90,7 +90,7 @@
* enabled.
*/
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_USB
# undef CONFIG_SAM34_UDP_REGDEBUG
#endif
@@ -606,7 +606,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] =
#ifdef CONFIG_SAM34_UDP_REGDEBUG
static void sam_printreg(uintptr_t regaddr, uint32_t regval, bool iswrite)
{
- lldbg("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval);
+ _info("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval);
}
#endif
@@ -657,7 +657,7 @@ static void sam_checkreg(uintptr_t regaddr, uint32_t regval, bool iswrite)
{
/* No.. More than one. */
- lldbg("[repeats %d more times]\n", count);
+ _info("[repeats %d more times]\n", count);
}
}
@@ -732,20 +732,20 @@ static inline void sam_putreg(uint32_t regval, uint32_t regaddr)
* Name: sam_dumpep
****************************************************************************/
-#if defined(CONFIG_SAM34_UDP_REGDEBUG) && defined(CONFIG_DEBUG)
+#if defined(CONFIG_SAM34_UDP_REGDEBUG) && defined(CONFIG_DEBUG_USB)
static void sam_dumpep(struct sam_usbdev_s *priv, uint8_t epno)
{
/* Global Registers */
- lldbg("Global Registers:\n");
- lldbg(" FRMNUM: %08x\n", sam_getreg(SAM_UDP_FRMNUM));
- lldbg("GLBSTAT: %08x\n", sam_getreg(SAM_UDP_GLBSTAT));
- lldbg(" FADDR: %08x\n", sam_getreg(SAM_UDP_FADDR));
- lldbg(" IMR: %08x\n", sam_getreg(SAM_UDP_IMR));
- lldbg(" ISR: %08x\n", sam_getreg(SAM_UDP_ISR));
- lldbg(" RSTEP: %08x\n", sam_getreg(SAM_UDP_RSTEP));
- lldbg(" TXVC: %08x\n", sam_getreg(SAM_UDP_TXVC));
- lldbg(" CSR[%d]: %08x\n", epno, sam_getreg(SAM_UDPEP_CSR(epno)));
+ _info("Global Registers:\n");
+ _info(" FRMNUM: %08x\n", sam_getreg(SAM_UDP_FRMNUM));
+ _info("GLBSTAT: %08x\n", sam_getreg(SAM_UDP_GLBSTAT));
+ _info(" FADDR: %08x\n", sam_getreg(SAM_UDP_FADDR));
+ _info(" IMR: %08x\n", sam_getreg(SAM_UDP_IMR));
+ _info(" ISR: %08x\n", sam_getreg(SAM_UDP_ISR));
+ _info(" RSTEP: %08x\n", sam_getreg(SAM_UDP_RSTEP));
+ _info(" TXVC: %08x\n", sam_getreg(SAM_UDP_TXVC));
+ _info(" CSR[%d]: %08x\n", epno, sam_getreg(SAM_UDPEP_CSR(epno)));
}
#endif
@@ -968,9 +968,9 @@ static int sam_req_write(struct sam_usbdev_s *priv, struct sam_ep_s *privep)
return -ENOENT;
}
- ullvdbg("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
- epno, privreq, privreq->req.len, privreq->req.xfrd,
- privreq->inflight, privep->zlpneeded);
+ uinfo("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
+ epno, privreq, privreq->req.len, privreq->req.xfrd,
+ privreq->inflight, privep->zlpneeded);
/* Handle any bytes in flight. */
@@ -1139,8 +1139,8 @@ static int sam_req_read(struct sam_usbdev_s *priv, struct sam_ep_s *privep,
return -ENOENT;
}
- ullvdbg("EP%d: len=%d xfrd=%d\n",
- epno, privreq->req.len, privreq->req.xfrd);
+ uinfo("EP%d: len=%d xfrd=%d\n",
+ epno, privreq->req.len, privreq->req.xfrd);
/* Ignore any attempt to receive a zero length packet */
@@ -1408,8 +1408,8 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
index.w = GETUINT16(priv->ctrl.index);
len.w = GETUINT16(priv->ctrl.len);
- ullvdbg("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
+ uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
/* Dispatch any non-standard requests */
@@ -1572,7 +1572,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
{
/* Special case recipient=device test mode */
- ullvdbg("test mode: %d\n", index.w);
+ uinfo("test mode: %d\n", index.w);
}
else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@@ -2749,7 +2749,7 @@ static int sam_ep_configure_internal(struct sam_ep_s *privep,
DEBUGASSERT(privep && privep->dev && desc);
- uvdbg("len: %02x type: %02x addr: %02x attr: %02x "
+ uinfo("len: %02x type: %02x addr: %02x attr: %02x "
"maxpacketsize: %02x %02x interval: %02x\n",
desc->len, desc->type, desc->addr, desc->attr,
desc->mxpacketsize[0], desc->mxpacketsize[1],
@@ -2891,7 +2891,7 @@ static int sam_ep_configure(struct usbdev_ep_s *ep,
/* Verify parameters. Endpoint 0 is not available at this interface */
-#if defined(CONFIG_DEBUG) || defined(CONFIG_USBDEV_TRACE)
+#if defined(CONFIG_DEBUG_USB) || defined(CONFIG_USBDEV_TRACE)
uint8_t epno = USB_EPNO(desc->addr);
usbtrace(TRACE_EPCONFIGURE, (uint16_t)epno);
@@ -2942,11 +2942,11 @@ static int sam_ep_disable(struct usbdev_ep_s *ep)
irqstate_t flags;
uint8_t epno;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!ep)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
- ulldbg("ERROR: ep=%p\n", ep);
+ uerr("ERROR: ep=%p\n", ep);
return -EINVAL;
}
#endif
@@ -2979,13 +2979,14 @@ static struct usbdev_req_s *sam_ep_allocreq(struct usbdev_ep_s *ep)
{
struct sam_req_s *privreq;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!ep)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
return NULL;
}
#endif
+
usbtrace(TRACE_EPALLOCREQ, USB_EPNO(ep->eplog));
privreq = (struct sam_req_s *)kmm_malloc(sizeof(struct sam_req_s));
@@ -3011,7 +3012,7 @@ static void sam_ep_freereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
{
struct sam_req_s *privreq = (struct sam_req_s *)req;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
@@ -3074,11 +3075,12 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
uint8_t epno;
int ret = OK;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
- ulldbg("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+ uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n",
+ req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
@@ -3086,11 +3088,11 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
usbtrace(TRACE_EPSUBMIT, USB_EPNO(ep->eplog));
priv = privep->dev;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!priv->driver)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
- ulldbg("ERROR: driver=%p\n", priv->driver);
+ uerr("ERROR: driver=%p\n", priv->driver);
return -ESHUTDOWN;
}
#endif
@@ -3114,11 +3116,11 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
if (privep->stalled || privep->pending)
{
- /* Yes.. in this case, save the new they will get in a special
- * "pending" they will get queue until the stall is cleared.
+ /* Yes.. in this case, save the request in a special "pending"
+ * queue. They will stay queuee until the stall is cleared.
*/
- ulldbg("Pending stall clear\n");
+ uinfo("Pending stall clear\n");
sam_req_enqueue(&privep->pendq, privreq);
usbtrace(TRACE_INREQQUEUED(epno), req->len);
ret = OK;
@@ -3182,13 +3184,14 @@ static int sam_ep_cancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
struct sam_ep_s *privep = (struct sam_ep_s *)ep;
irqstate_t flags;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
return -EINVAL;
}
#endif
+
usbtrace(TRACE_EPCANCEL, USB_EPNO(ep->eplog));
flags = enter_critical_section();
@@ -3208,7 +3211,7 @@ static int sam_ep_stallresume(struct usbdev_ep_s *ep, bool resume)
irqstate_t flags;
int ret;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!ep)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
@@ -3283,7 +3286,8 @@ static struct usbdev_ep_s *sam_allocep(struct usbdev_s *dev, uint8_t epno,
uint16_t epset = SAM_EPSET_NOTEP0;
usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno);
-#ifdef CONFIG_DEBUG
+
+#ifdef CONFIG_DEBUG_USB
if (!dev)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
@@ -3345,13 +3349,14 @@ static void sam_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep)
struct sam_usbdev_s *priv;
struct sam_ep_s *privep;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!dev || !ep)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
return;
}
#endif
+
priv = (struct sam_usbdev_s *)dev;
privep = (struct sam_ep_s *)ep;
usbtrace(TRACE_DEVFREEEP, (uint16_t)USB_EPNO(ep->eplog));
@@ -3377,7 +3382,7 @@ static int sam_getframe(struct usbdev_s *dev)
uint32_t regval;
uint16_t frameno;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!dev)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
@@ -3409,7 +3414,8 @@ static int sam_wakeup(struct usbdev_s *dev)
uint32_t regval;
usbtrace(TRACE_DEVWAKEUP, 0);
-#ifdef CONFIG_DEBUG
+
+#ifdef CONFIG_DEBUG_USB
if (!dev)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
@@ -3480,7 +3486,7 @@ static int sam_selfpowered(struct usbdev_s *dev, bool selfpowered)
usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!dev)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
@@ -3926,7 +3932,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
usbtrace(TRACE_DEVREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!driver || !driver->ops->bind || !driver->ops->unbind ||
!driver->ops->disconnect || !driver->ops->setup)
{
@@ -4000,7 +4006,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
usbtrace(TRACE_DEVUNREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (driver != priv->driver)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
diff --git a/arch/arm/src/sam34/sam_wdt.c b/arch/arm/src/sam34/sam_wdt.c
index dbb3f6f895ec5136cc1aa17dea21a364840dc9da..cf3d70b1613e66d04fd435a1fbc20d9f8b157904 100644
--- a/arch/arm/src/sam34/sam_wdt.c
+++ b/arch/arm/src/sam34/sam_wdt.c
@@ -81,18 +81,8 @@
# define CONFIG_SAM34_WDT_DEFTIMOUT WDT_MAXTIMEOUT
#endif
-/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing the watchdog
- * driver. NOTE: that only lldbg types are used so that the output is
- * immediately available.
- */
-
-#ifdef CONFIG_DEBUG_WATCHDOG
-# define wddbg lldbg
-# define wdvdbg llvdbg
-#else
-# define wddbg(x...)
-# define wdvdbg(x...)
+#ifndef CONFIG_DEBUG_WATCHDOG_INFO
+# undef CONFIG_SAM34_WDT_REGDEBUG
#endif
/****************************************************************************
@@ -118,7 +108,7 @@ struct sam34_lowerhalf_s
****************************************************************************/
/* Register operations ******************************************************/
-#if defined(CONFIG_SAM34_WDT_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAM34_WDT_REGDEBUG
static uint32_t sam34_getreg(uint32_t addr);
static void sam34_putreg(uint32_t val, uint32_t addr);
#else
@@ -176,7 +166,7 @@ static struct sam34_lowerhalf_s g_wdgdev;
*
****************************************************************************/
-#if defined(CONFIG_SAM34_WDT_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAM34_WDT_REGDEBUG
static uint32_t sam34_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@@ -197,7 +187,7 @@ static uint32_t sam34_getreg(uint32_t addr)
{
if (count == 4)
{
- lldbg("...\n");
+ wdinfo("...\n");
}
return val;
@@ -214,7 +204,7 @@ static uint32_t sam34_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ wdinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -226,7 +216,7 @@ static uint32_t sam34_getreg(uint32_t addr)
/* Show the register value read */
- lldbg("%08x->%08x\n", addr, val);
+ wdinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@@ -239,12 +229,12 @@ static uint32_t sam34_getreg(uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_SAM34_WDT_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAM34_WDT_REGDEBUG
static void sam34_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- lldbg("%08x<-%08x\n", addr, val);
+ wdinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@@ -314,7 +304,7 @@ static int sam34_start(FAR struct watchdog_lowerhalf_s *lower)
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
uint32_t mr_val = 0;
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
DEBUGASSERT(priv);
/* The watchdog is always disabled after a reset. It is enabled by setting
@@ -360,7 +350,7 @@ static int sam34_stop(FAR struct watchdog_lowerhalf_s *lower)
* except by a reset.
*/
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
return -ENOSYS;
}
@@ -386,7 +376,7 @@ static int sam34_stop(FAR struct watchdog_lowerhalf_s *lower)
static int sam34_keepalive(FAR struct watchdog_lowerhalf_s *lower)
{
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
sam34_putreg((WDT_CR_KEY | WDT_CR_WDRSTT), SAM_WDT_CR);
return OK;
@@ -414,7 +404,7 @@ static int sam34_getstatus(FAR struct watchdog_lowerhalf_s *lower,
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
uint32_t elapsed;
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
DEBUGASSERT(priv);
/* Return the status bit */
@@ -441,10 +431,10 @@ static int sam34_getstatus(FAR struct watchdog_lowerhalf_s *lower,
status->timeleft = (priv->timeout * elapsed) / (priv->reload + 1);
- wdvdbg("Status : %08x\n", sam34_getreg(SAM_WDT_SR));
- wdvdbg(" flags : %08x\n", status->flags);
- wdvdbg(" timeout : %d\n", status->timeout);
- wdvdbg(" timeleft : %d\n", status->timeleft);
+ wdinfo("Status : %08x\n", sam34_getreg(SAM_WDT_SR));
+ wdinfo(" flags : %08x\n", status->flags);
+ wdinfo(" timeout : %d\n", status->timeout);
+ wdinfo(" timeleft : %d\n", status->timeleft);
return OK;
}
@@ -471,13 +461,13 @@ static int sam34_settimeout(FAR struct watchdog_lowerhalf_s *lower,
uint32_t reload;
DEBUGASSERT(priv);
- wdvdbg("Entry: timeout=%d\n", timeout);
+ wdinfo("Entry: timeout=%d\n", timeout);
/* Can this timeout be represented? */
if (timeout < 1 || timeout > WDT_MAXTIMEOUT)
{
- wddbg("Cannot represent timeout=%d > %d\n",
+ wderr("ERROR: Cannot represent timeout=%d > %d\n",
timeout, WDT_MAXTIMEOUT);
return -ERANGE;
}
@@ -503,7 +493,7 @@ static int sam34_settimeout(FAR struct watchdog_lowerhalf_s *lower,
priv->reload = reload;
- wdvdbg("fwdt=%d reload=%d timout=%d\n",
+ wdinfo("fwdt=%d reload=%d timout=%d\n",
WDT_FCLK, reload, priv->timeout);
/* Don't commit to MR register until started! */
@@ -543,7 +533,7 @@ static xcpt_t sam34_capture(FAR struct watchdog_lowerhalf_s *lower,
uint16_t regval;
DEBUGASSERT(priv);
- wdvdbg("Entry: handler=%p\n", handler);
+ wdinfo("Entry: handler=%p\n", handler);
/* Get the old handler return value */
@@ -611,7 +601,7 @@ static int sam34_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
int ret = -ENOTTY;
DEBUGASSERT(priv);
- wdvdbg("Entry: cmd=%d arg=%ld\n", cmd, arg);
+ wdinfo("Entry: cmd=%d arg=%ld\n", cmd, arg);
/* WDIOC_MINTIME: Set the minimum ping time. If two keepalive ioctls
* are received within this time, a reset event will be generated.
@@ -676,7 +666,7 @@ void sam_wdtinitialize(FAR const char *devpath)
WDT_MR_WDRSTEN);
sam34_putreg(mr_val, SAM_WDT_MR);
- wdvdbg("Entry: devpath=%s\n", devpath);
+ wdinfo("Entry: devpath=%s\n", devpath);
/* NOTE we assume that clocking to the IWDG has already been provided by
* the RCC initialization logic.
diff --git a/arch/arm/src/sama5/Kconfig b/arch/arm/src/sama5/Kconfig
index b2701131bc292e0907c39aac351af9aa5d87d5c3..11aa7179f1f9aff562b9f5c55ca542f093c31f75 100644
--- a/arch/arm/src/sama5/Kconfig
+++ b/arch/arm/src/sama5/Kconfig
@@ -1393,9 +1393,9 @@ endif # SAMA5_LCDC_HCR
config SAMA5_LCDC_REGDEBUG
bool "Register-Level Debug"
default n
- depends on DEBUG
+ depends on DEBUG_LCD_INFO
---help---
- Enable very low-level register access debug. Depends on DEBUG.
+ Enable very low-level register access debug. Depends on CONFIG_DEBUG_LCD_INFO.
endmenu # LCDC configuration
endif # SAMA5_LCDC
@@ -1499,9 +1499,9 @@ endif # !SAMA5_GMAC_AUTONEG
config SAMA5_GMAC_REGDEBUG
bool "Register-Level Debug"
default n
- depends on DEBUG
+ depends on DEBUG_NET_INFO
---help---
- Enable very low-level register access debug. Depends on DEBUG.
+ Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_INFO.
endmenu # GMAC device driver options
endif # SAMA5_GMAC
@@ -1678,9 +1678,9 @@ config SAMA5_EMACA_NBC
config SAMA5_EMACA_REGDEBUG
bool "Register-Level Debug"
default n
- depends on DEBUG
+ depends on DEBUG_NET_FEATURES
---help---
- Enable very low-level register access debug. Depends on DEBUG.
+ Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_FEATURES.
endmenu # EMAC device driver options
endif # SAMA5_EMACA
@@ -2076,7 +2076,7 @@ config SAMA5_EMACB_NBC
config SAMA5_EMACB_DEBUG
bool "Force EMAC0/1 DEBUG"
default n
- depends on DEBUG && !DEBUG_NET
+ depends on DEBUG_FEATURES && !DEBUG_NET
---help---
This option will force debug output from EMAC driver even without
network debug output enabled. This is not normally something
@@ -2087,9 +2087,9 @@ config SAMA5_EMACB_DEBUG
config SAMA5_EMACB_REGDEBUG
bool "Register-Level Debug"
default n
- depends on DEBUG
+ depends on DEBUG_NET_INFO
---help---
- Enable very low-level register access debug. Depends on DEBUG.
+ Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_INFO.
endmenu # EMAC device driver options
endif # SAMA5_EMACB
@@ -2323,11 +2323,11 @@ config SAMA5_CAN_AUTOBAUD
config SAMA5_CAN_REGDEBUG
bool "CAN Register level debug"
- depends on DEBUG
+ depends on DEBUG_CAN_INFO
default n
---help---
Output detailed register-level CAN device debug information.
- Requires also DEBUG.
+ Requires also CONFIG_DEBUG_CAN_INFO.
endmenu # CAN device driver options
endif # SAMA5_CAN0 || SAMA5_CAN1
@@ -2354,7 +2354,7 @@ config SAMA5_SPI_DMATHRESHOLD
config SAMA5_SPI_DMADEBUG
bool "SPI DMA transfer debug"
- depends on SAMA5_SPI_DMA && DEBUG && DEBUG_DMA
+ depends on SAMA5_SPI_DMA && DEBUG_FEATURES && DEBUG_DMA
default n
---help---
Enable special debug instrumentation analyze SPI DMA data transfers.
@@ -2364,11 +2364,11 @@ config SAMA5_SPI_DMADEBUG
config SAMA5_SPI_REGDEBUG
bool "SPI Register level debug"
- depends on DEBUG
+ depends on DEBUG_SPI_INFO
default n
---help---
Output detailed register-level SPI device debug information.
- Requires also DEBUG.
+ Requires also CONFIG_DEBUG_SPI_INFO.
endmenu # SPI device driver options
endif # SAMA5_SPI0 || SAMA5_SPI1
@@ -2399,11 +2399,11 @@ config SAMA5_TWI3_FREQUENCY
config SAMA5_TWI_REGDEBUG
bool "TWI register level debug"
- depends on DEBUG
+ depends on DEBUG_I2C_INFO
default n
---help---
Output detailed register-level TWI device debug information.
- Very invasive! Requires also DEBUG.
+ Very invasive! Requires also CONFIG_DEBUG_I2C_INFO.
endmenu # TWI device driver options
endif # SAMA5_TWI0 || SAMA5_TWI1 || SAMA5_TWI2 || SAMA5_TWI3
@@ -2766,7 +2766,7 @@ endif # SAMA5_SSC1
config SAMA5_SSC_DMADEBUG
bool "SSC DMA transfer debug"
- depends on DEBUG && DEBUG_DMA
+ depends on DEBUG_FEATURES && DEBUG_DMA
default n
---help---
Enable special debug instrumentation analyze SSC DMA data transfers.
@@ -2776,11 +2776,11 @@ config SAMA5_SSC_DMADEBUG
config SAMA5_SSC_REGDEBUG
bool "SSC Register level debug"
- depends on DEBUG
+ depends on DEBUG_I2S_INFO
default n
---help---
Output detailed register-level SSC device debug information.
- Very invasive! Requires also DEBUG.
+ Very invasive! Requires also CONFIG_DEBUG_I2S_INFO.
config SAMA5_SSC_QDEBUG
bool "SSC Queue debug"
@@ -2857,7 +2857,7 @@ config SAMA5_HSMCI_WRPROOF
config SAMA5_HSMCI_XFRDEBUG
bool "HSMCI transfer debug"
- depends on DEBUG_FS && DEBUG_VERBOSE
+ depends on DEBUG_FS_INFO
default n
---help---
Enable special debug instrumentation analyze HSMCI data transfers.
@@ -2865,11 +2865,11 @@ config SAMA5_HSMCI_XFRDEBUG
registers at key points in the data transfer and then dumps all of
the registers at the end of the transfer. If DEBUG_DMA is also
enabled, then DMA register will be collected as well. Requires also
- DEBUG_FS and DEBUG_VERBOSE.
+ DEBUG_FS and CONFIG_DEBUG_INFO.
config SAMA5_HSMCI_CMDDEBUG
bool "HSMCI command debug"
- depends on DEBUG_FS && DEBUG_VERBOSE
+ depends on DEBUG_FS_INFO
default n
---help---
Enable special debug instrumentation analyze HSMCI commands. This
@@ -2877,15 +2877,15 @@ config SAMA5_HSMCI_CMDDEBUG
key points in the data transfer and then dumps all of the registers
at the end of the transfer. If DEBUG_DMA is also enabled, then DMA
register will be collected as well. Requires also DEBUG_FS and
- DEBUG_VERBOSE.
+ CONFIG_DEBUG_INFO.
config SAMA5_HSMCI_REGDEBUG
bool "HSMCI Register level debug"
- depends on DEBUG
+ depends on DEBUG_MEMCARD_INFO
default n
---help---
Output detailed register-level HSCMI device debug information.
- Very invasive! Requires also DEBUG.
+ Very invasive! Requires also CONFIG_DEBUG_MEMCARD_INFO.
endmenu # HSMCI device driver options
endif # SAMA5_HSMCI0 || SAMA5_HSMCI1 || SAMA5_HSMCI2
@@ -2920,7 +2920,7 @@ config SAMA5_UDPHS_PREALLOCATE
config SAMA5_UDPHS_REGDEBUG
bool "Enable low-level UDPHS register debug"
default n
- depends on DEBUG
+ depends on DEBUG_USB_INFO
endmenu # USB High Speed Device Controller driver (DCD) options
endif # SAMA5_UDPHS
@@ -2960,7 +2960,7 @@ config SAMA5_OHCI_TDBUFSIZE
config SAMA5_OHCI_REGDEBUG
bool "Enable low-level OHCI register debug"
default n
- depends on DEBUG
+ depends on DEBUG_USB_INFO
endif # SAMA5_OHCI
@@ -3009,7 +3009,7 @@ config SAMA5_EHCI_PREALLOCATE
config SAMA5_EHCI_REGDEBUG
bool "Enable low-level EHCI register debug"
default n
- depends on DEBUG
+ depends on DEBUG_USB_INFO
endif # SAMA5_EHCI
@@ -3661,7 +3661,7 @@ endif # SAMA5_ADC_HAVE_CHAN
config SAMA5_ADC_REGDEBUG
bool "Enable register-level ADC/touchscreen debug"
default n
- depends on DEBUG
+ depends on DEBUG_ANALOG_INFO
---help---
Enable very low register-level debug output.
@@ -3903,23 +3903,23 @@ endif
config SAMA5_TC_DEBUG
bool "TC debug"
- depends on DEBUG
+ depends on DEBUG_FEATURES
default n
---help---
Output high level Timer/Counter device debug information.
- Requires also DEBUG. If this option AND DEBUG_VERBOSE are
+ Requires also CONFIG_DEBUG_FEATURES. If this option AND CONFIG_DEBUG_INFO are
enabled, then the system will be overwhelmed the timer debug
- output. If DEBUG_VERBOSE is disabled, then debug output will
+ output. If CONFIG_DEBUG_INFO is disabled, then debug output will
only indicate if/when timer-related errors occur. This
latter mode is completely usable.
config SAMA5_TC_REGDEBUG
bool "TC register level debug"
- depends on DEBUG
+ depends on DEBUG_TIMER_INFO
default n
---help---
Output detailed register-level Timer/Counter device debug
- information. Very invasive! Requires also DEBUG.
+ information. Very invasive! Requires also CONFIG_DEBUG_TIMER_INFO.
endmenu # Timer/counter Configuration
endif # SAMA5_HAVE_TC
@@ -4150,7 +4150,7 @@ endif # SAMA5_PWM_CHAN3
config SAMA5_PWM_REGDEBUG
bool "Enable register-level PWM debug"
default n
- depends on DEBUG
+ depends on DEBUG_PWM_INFO
---help---
Enable very low register-level debug output.
@@ -4171,8 +4171,8 @@ config SAMA5_WDT_INTERRUPT
config SAMA5_WDT_DEBUGHALT
bool "Halt on DEBUG"
- default y if DEBUG
- default n if !DEBUG
+ default y if DEBUG_FEATURES
+ default n if !DEBUG_FEATURES
---help---
Halt the watchdog timer in the debug state
@@ -4185,7 +4185,7 @@ config SAMA5_WDT_IDLEHALT
config SAMA5_WDT_REGDEBUG
bool "Register level debug"
default n
- depends on DEBUG
+ depends on DEBUG_WATCHDOG_INFO
---help---
Enable low-level register debug output
@@ -4688,7 +4688,7 @@ endif # SAMA5_HAVE_PMECC
config SAMA5_NAND_DMADEBUG
bool "NAND DMA transfer debug"
- depends on SAMA5_NAND_DMA && DEBUG && DEBUG_DMA
+ depends on SAMA5_NAND_DMA && DEBUG_FEATURES && DEBUG_DMA
default n
---help---
Enable special debug instrumentation analyze NAND DMA data transfers.
@@ -4699,18 +4699,17 @@ config SAMA5_NAND_DMADEBUG
config SAMA5_NAND_REGDEBUG
bool "Register-Level NAND Debug"
default n
- depends on DEBUG && DEBUG_FS
+ depends on DEBUG_FS_INFO
---help---
- Enable very low-level register access debug. Depends on DEBUG and
- DEBUG_FS.
+ Enable very low-level register access debug. Depends on CONFIG_DEBUG_FS_INFO.
config SAMA5_NAND_DUMP
bool "NAND data dump"
default n
- depends on DEBUG && DEBUG_FS
+ depends on DEBUG_FEATURES && DEBUG_FS
---help---
Dump the contents of all data read and written to FLAH. Depends on
- DEBUG and DEBUG_FS.
+ CONFIG_DEBUG_FEATURES and DEBUG_FS.
endif # SAMA5_HAVE_NAND
endmenu # External Memory Configuration
diff --git a/arch/arm/src/sama5/sam_adc.c b/arch/arm/src/sama5/sam_adc.c
index 68565bc502fa80f0f5a5fc69253aac04151b7789..dcf82b1f6d9c5f72bf7f7edd4dac7ead2e629e09 100644
--- a/arch/arm/src/sama5/sam_adc.c
+++ b/arch/arm/src/sama5/sam_adc.c
@@ -371,6 +371,10 @@
#define SAMA5_ADC_SAMPLES (CONFIG_SAMA5_ADC_DMASAMPLES * SAMA5_NCHANNELS)
+#ifndef CONFIG_DEBUG_ANALOG_INFO
+# undef CONFIG_SAMA5_ADC_REGDEBUG
+#endif
+
/****************************************************************************
* Private Types
****************************************************************************/
@@ -423,7 +427,7 @@ struct sam_adc_s
****************************************************************************/
/* Register operations ******************************************************/
-#if defined(CONFIG_SAMA5_ADC_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAMA5_ADC_REGDEBUG
static bool sam_adc_checkreg(struct sam_adc_s *priv, bool wr,
uint32_t regval, uintptr_t address);
#endif
@@ -544,7 +548,7 @@ static bool sam_adc_checkreg(struct sam_adc_s *priv, bool wr,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", priv->ntimes);
+ ainfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@@ -604,7 +608,7 @@ static void sam_adc_dmadone(void *arg)
int chan;
int i;
- avdbg("ready=%d enabled=%d\n", priv->enabled, priv->ready);
+ ainfo("ready=%d enabled=%d\n", priv->enabled, priv->ready);
ASSERT(priv != NULL && !priv->ready);
/* If the DMA transfer is not enabled, just ignore the data (and do not start
@@ -725,7 +729,7 @@ static void sam_adc_dmacallback(DMA_HANDLE handle, void *arg, int result)
struct sam_adc_s *priv = (struct sam_adc_s *)arg;
int ret;
- allvdbg("ready=%d enabled=%d\n", priv->enabled, priv->ready);
+ ainfo("ready=%d enabled=%d\n", priv->enabled, priv->ready);
DEBUGASSERT(priv->ready);
/* Check of the bottom half is keeping up with us.
@@ -751,7 +755,7 @@ static void sam_adc_dmacallback(DMA_HANDLE handle, void *arg, int result)
ret = work_queue(HPWORK, &priv->work, sam_adc_dmadone, priv, 0);
if (ret != 0)
{
- alldbg("ERROR: Failed to queue work: %d\n", ret);
+ aerr("ERROR: Failed to queue work: %d\n", ret);
}
}
@@ -798,7 +802,7 @@ static int sam_adc_dmasetup(FAR struct sam_adc_s *priv, FAR uint8_t *buffer,
uint32_t paddr;
uint32_t maddr;
- avdbg("buffer=%p buflen=%d\n", buffer, (int)buflen);
+ ainfo("buffer=%p buflen=%d\n", buffer, (int)buflen);
DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
DEBUGASSERT(((uint32_t)buffer & 3) == 0);
@@ -849,7 +853,7 @@ static void sam_adc_endconversion(void *arg)
int chan;
ASSERT(priv != NULL);
- avdbg("pending=%08x\n", priv->pending);
+ ainfo("pending=%08x\n", priv->pending);
/* Get the set of unmasked, pending ADC interrupts */
@@ -957,7 +961,7 @@ static int sam_adc_interrupt(int irq, void *context)
ret = work_queue(HPWORK, &priv->work, sam_adc_endconversion, priv, 0);
if (ret != 0)
{
- alldbg("ERROR: Failed to queue work: %d\n", ret);
+ aerr("ERROR: Failed to queue work: %d\n", ret);
}
pending &= ~ADC_INT_EOCALL;
@@ -1011,7 +1015,7 @@ static void sam_adc_reset(struct adc_dev_s *dev)
#endif
uint32_t regval;
- avdbg("Resetting..\n");
+ ainfo("Resetting..\n");
/* NOTE: We can't really reset the ADC hardware without losing the
* touchscreen configuration.
@@ -1081,7 +1085,7 @@ static int sam_adc_setup(struct adc_dev_s *dev)
struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
uint32_t regval;
- avdbg("Setup\n");
+ ainfo("Setup\n");
/* Enable channel number tag. This bit will force the channel number (CHNB)
* to be included in the LDCR register content.
@@ -1152,7 +1156,7 @@ static void sam_adc_shutdown(struct adc_dev_s *dev)
struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
#endif
- avdbg("Shutdown\n");
+ ainfo("Shutdown\n");
/* Reset the ADC peripheral */
@@ -1181,7 +1185,7 @@ static void sam_adc_rxint(struct adc_dev_s *dev, bool enable)
struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
#endif
- avdbg("enable=%d\n", enable);
+ ainfo("enable=%d\n", enable);
#ifdef CONFIG_SAMA5_ADC_DMA
/* Ignore redundant requests */
@@ -1232,7 +1236,7 @@ static int sam_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
#endif
int ret = OK;
- avdbg("cmd=%d arg=%ld\n", cmd, arg);
+ ainfo("cmd=%d arg=%ld\n", cmd, arg);
switch (cmd)
{
@@ -1277,7 +1281,7 @@ static int sam_adc_settimer(struct sam_adc_s *priv, uint32_t frequency,
uint32_t regval;
int ret;
- avdbg("frequency=%ld channel=%d\n", (long)frequency, channel);
+ ainfo("frequency=%ld channel=%d\n", (long)frequency, channel);
DEBUGASSERT(priv && frequency > 0);
/* Configure TC for a 1Hz frequency and trigger on RC compare. */
@@ -1285,7 +1289,7 @@ static int sam_adc_settimer(struct sam_adc_s *priv, uint32_t frequency,
ret = sam_tc_divisor(frequency, &div, &tcclks);
if (ret < 0)
{
- adbg("ERROR: sam_tc_divisor failed: %d\n", ret);
+ aerr("ERROR: sam_tc_divisor failed: %d\n", ret);
return ret;
}
@@ -1304,7 +1308,7 @@ static int sam_adc_settimer(struct sam_adc_s *priv, uint32_t frequency,
priv->tc = sam_tc_allocate(channel, mode);
if (!priv->tc)
{
- adbg("ERROR: Failed to allocate channel %d mode %08x\n", channel, mode);
+ aerr("ERROR: Failed to allocate channel %d mode %08x\n", channel, mode);
return -EINVAL;
}
@@ -1350,7 +1354,7 @@ static void sam_adc_freetimer(struct sam_adc_s *priv)
{
/* Is a timer allocated? */
- avdbg("tc=%p\n", priv->tc);
+ ainfo("tc=%p\n", priv->tc);
if (priv->tc)
{
@@ -1377,7 +1381,7 @@ static int sam_adc_trigger(struct sam_adc_s *priv)
int ret = OK;
#if defined(CONFIG_SAMA5_ADC_SWTRIG)
- avdbg("Setup software trigger\n");
+ ainfo("Setup software trigger\n");
/* Configure the software trigger */
@@ -1393,7 +1397,7 @@ static int sam_adc_trigger(struct sam_adc_s *priv)
sam_adc_putreg(priv, SAM_ADC_TRGR, regval);
#elif defined(CONFIG_SAMA5_ADC_ADTRG)
- avdbg("Setup ADTRG trigger\n");
+ ainfo("Setup ADTRG trigger\n");
/* Configure the trigger via the external ADTRG signal */
@@ -1420,7 +1424,7 @@ static int sam_adc_trigger(struct sam_adc_s *priv)
sam_adc_putreg(priv, SAM_ADC_TRGR, regval);
#elif defined(CONFIG_SAMA5_ADC_TIOATRIG)
- avdbg("Setup timer/counter trigger\n");
+ ainfo("Setup timer/counter trigger\n");
/* Start the timer */
@@ -1436,7 +1440,7 @@ static int sam_adc_trigger(struct sam_adc_s *priv)
#endif
if (ret < 0)
{
- adbg("ERROR: sam_adc_settimer failed: %d\n", ret);
+ aerr("ERROR: sam_adc_settimer failed: %d\n", ret);
return ret;
}
@@ -1500,7 +1504,7 @@ static void sam_adc_autocalibrate(struct sam_adc_s *priv)
#ifdef CONFIG_SAMA5_ADC_AUTOCALIB
uint32_t regval;
- avdbg("Entry\n");
+ ainfo("Entry\n");
/* Launch an automatic calibration of the ADC cell on next sequence */
@@ -1527,7 +1531,7 @@ static void sam_adc_offset(struct sam_adc_s *priv)
{
uint32_t regval = 0;
- avdbg("Entry\n");
+ ainfo("Entry\n");
#ifdef CONFIG_SAMA5_ADC_ANARCH
/* Set the offset for each enabled channel. This centers the analog signal
@@ -1644,7 +1648,7 @@ static void sam_adc_gain(struct sam_adc_s *priv)
#ifdef CONFIG_SAMA5_ADC_ANARCH
uint32_t regval;
- avdbg("Entry\n");
+ ainfo("Entry\n");
/* Set the gain for each enabled channel */
@@ -1690,7 +1694,7 @@ static void sam_adc_gain(struct sam_adc_s *priv)
sam_adc_putreg(priv, SAM_ADC_CGR, regval);
#else
- avdbg("Gain=%d\n", CONFIG_SAMA5_ADC_GAIN);
+ ainfo("Gain=%d\n", CONFIG_SAMA5_ADC_GAIN);
/* Set GAIN0 only. GAIN0 will be used for all channels. */
@@ -1711,7 +1715,7 @@ static void sam_adc_analogchange(struct sam_adc_s *priv)
{
uint32_t regval;
- avdbg("Entry\n");
+ ainfo("Entry\n");
/* Enable/disable the analog change feature */
@@ -1754,7 +1758,7 @@ static void sam_adc_setseqr(int chan, uint32_t *seqr1, uint32_t *seqr2, int seq)
*seqr1 |= ADC_SEQR1_USCH(seq, chan);
}
- avdbg("chan=%d seqr1=%08x seqr2=%08x seq=%d\n", chan, *seqr1, *seqr2, seq);
+ ainfo("chan=%d seqr1=%08x seqr2=%08x seq=%d\n", chan, *seqr1, *seqr2, seq);
}
#endif
@@ -1766,7 +1770,7 @@ static void sam_adc_sequencer(struct sam_adc_s *priv)
uint32_t seqr2;
int seq;
- avdbg("Setup sequencer\n");
+ ainfo("Setup sequencer\n");
/* Set user configured channel sequence */
@@ -1855,7 +1859,7 @@ static void sam_adc_sequencer(struct sam_adc_s *priv)
#else
uint32_t regval;
- avdbg("Disable sequencer\n");
+ ainfo("Disable sequencer\n");
/* Disable the sequencer */
@@ -1878,7 +1882,7 @@ static void sam_adc_channels(struct sam_adc_s *priv)
{
uint32_t regval;
- avdbg("Entry\n");
+ ainfo("Entry\n");
/* Enable channels. */
@@ -1964,7 +1968,7 @@ struct adc_dev_s *sam_adc_initialize(void)
if (!priv->initialized)
{
- avdbg("Initializing...\n");
+ ainfo("Initializing...\n");
/* Disable ADC peripheral clock */
@@ -2056,7 +2060,7 @@ struct adc_dev_s *sam_adc_initialize(void)
}
else
{
- adbg("ERROR: Cannot realize ADC input frequency\n");
+ aerr("ERROR: Cannot realize ADC input frequency\n");
return NULL;
}
@@ -2108,7 +2112,7 @@ struct adc_dev_s *sam_adc_initialize(void)
ret = irq_attach(SAM_IRQ_ADC, sam_adc_interrupt);
if (ret < 0)
{
- adbg("ERROR: Failed to attach IRQ %d: %d\n", SAM_IRQ_ADC, ret);
+ aerr("ERROR: Failed to attach IRQ %d: %d\n", SAM_IRQ_ADC, ret);
return NULL;
}
@@ -2127,7 +2131,7 @@ struct adc_dev_s *sam_adc_initialize(void)
/* Return a pointer to the device structure */
- avdbg("Returning %p\n", &g_adcdev);
+ ainfo("Returning %p\n", &g_adcdev);
return &g_adcdev;
}
@@ -2143,7 +2147,7 @@ void sam_adc_lock(FAR struct sam_adc_s *priv)
{
int ret;
- avdbg("Locking\n");
+ ainfo("Locking\n");
do
{
@@ -2168,7 +2172,7 @@ void sam_adc_lock(FAR struct sam_adc_s *priv)
void sam_adc_unlock(FAR struct sam_adc_s *priv)
{
- avdbg("Unlocking\n");
+ ainfo("Unlocking\n");
sem_post(&priv->exclsem);
}
@@ -2187,7 +2191,7 @@ uint32_t sam_adc_getreg(struct sam_adc_s *priv, uintptr_t address)
if (sam_adc_checkreg(priv, false, regval, address))
{
- lldbg("%08x->%08x\n", address, regval);
+ ainfo("%08x->%08x\n", address, regval);
}
return regval;
@@ -2207,7 +2211,7 @@ void sam_adc_putreg(struct sam_adc_s *priv, uintptr_t address, uint32_t regval)
{
if (sam_adc_checkreg(priv, true, regval, address))
{
- lldbg("%08x<-%08x\n", address, regval);
+ ainfo("%08x<-%08x\n", address, regval);
}
putreg32(regval, address);
diff --git a/arch/arm/src/sama5/sam_adc.h b/arch/arm/src/sama5/sam_adc.h
index f8ba29f157636ed0913b530aca1cf3c069bd6d32..f84a45a65d027e675a4b59417c1d83d04c090b51 100644
--- a/arch/arm/src/sama5/sam_adc.h
+++ b/arch/arm/src/sama5/sam_adc.h
@@ -57,7 +57,7 @@
# error Work queue support is required (CONFIG_SCHED_WORKQUEUE)
#endif
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_FEATURES
# undef CONFIG_SAMA5_ADC_REGDEBUG
#endif
diff --git a/arch/arm/src/sama5/sam_allocateheap.c b/arch/arm/src/sama5/sam_allocateheap.c
index 14388795f984bcd3b72bd4b7835ea6da662b7411..29dcf728f6f6ee0084b9911c3afe81211720e33e 100644
--- a/arch/arm/src/sama5/sam_allocateheap.c
+++ b/arch/arm/src/sama5/sam_allocateheap.c
@@ -312,9 +312,9 @@ void up_addregion(void)
}
else
{
- lldbg("ERROR: SDRAM memory not added to heap. CONFIG_MM_NREGIONS=%d\n",
- CONFIG_MM_REGIONS);
- lldbg(" Increase the size of CONFIG_MM_NREGIONS\n");
+ serr("ERROR: SDRAM memory not added to heap. CONFIG_MM_NREGIONS=%d\n",
+ CONFIG_MM_REGIONS);
+ serr(" Increase the size of CONFIG_MM_NREGIONS\n");
}
#endif
@@ -331,9 +331,9 @@ void up_addregion(void)
}
else
{
- lldbg("ERROR: CS0 memory not added to heap. CONFIG_MM_NREGIONS=%d\n",
- CONFIG_MM_REGIONS);
- lldbg(" Increase the size of CONFIG_MM_NREGIONS\n");
+ serr("ERROR: CS0 memory not added to heap. CONFIG_MM_NREGIONS=%d\n",
+ CONFIG_MM_REGIONS);
+ serr(" Increase the size of CONFIG_MM_NREGIONS\n");
}
#endif
@@ -350,9 +350,9 @@ void up_addregion(void)
}
else
{
- lldbg("ERROR: CS1 memory not added to heap. CONFIG_MM_NREGIONS=%d\n",
- CONFIG_MM_REGIONS);
- lldbg(" Increase the size of CONFIG_MM_NREGIONS\n");
+ serr("ERROR: CS1 memory not added to heap. CONFIG_MM_NREGIONS=%d\n",
+ CONFIG_MM_REGIONS);
+ serr(" Increase the size of CONFIG_MM_NREGIONS\n");
}
#endif
@@ -369,9 +369,9 @@ void up_addregion(void)
}
else
{
- lldbg("ERROR: CS2 memory not added to heap. CONFIG_MM_NREGIONS=%d\n",
- CONFIG_MM_REGIONS);
- lldbg(" Increase the size of CONFIG_MM_NREGIONS\n");
+ serr("ERROR: CS2 memory not added to heap. CONFIG_MM_NREGIONS=%d\n",
+ CONFIG_MM_REGIONS);
+ serr(" Increase the size of CONFIG_MM_NREGIONS\n");
}
#endif
@@ -388,9 +388,9 @@ void up_addregion(void)
}
else
{
- lldbg("ERROR: CS3 memory not added to heap. CONFIG_MM_NREGIONS=%d\n",
- CONFIG_MM_REGIONS);
- lldbg(" Increase the size of CONFIG_MM_NREGIONS\n");
+ serr("ERROR: CS3 memory not added to heap. CONFIG_MM_NREGIONS=%d\n",
+ CONFIG_MM_REGIONS);
+ serr(" Increase the size of CONFIG_MM_NREGIONS\n");
}
#endif
@@ -398,9 +398,9 @@ void up_addregion(void)
if (nregions > 0)
{
- lldbg("ERROR: Not all regions added to heap: %d added, but CONFIG_MM_NREGIONS=%d\n",
- CONFIG_MM_REGIONS - nregions, CONFIG_MM_REGIONS);
- lldbg(" Decrease the size of CONFIG_MM_NREGIONS\n");
+ serr("ERROR: Not all regions added to heap: %d added, but CONFIG_MM_NREGIONS=%d\n",
+ CONFIG_MM_REGIONS - nregions, CONFIG_MM_REGIONS);
+ serr(" Decrease the size of CONFIG_MM_NREGIONS\n");
}
}
#endif
diff --git a/arch/arm/src/sama5/sam_can.c b/arch/arm/src/sama5/sam_can.c
index ac9e93cc08a6e2474498c12ed062702e89892e1c..3e1b3d116a1993da67b2c4614d607ce5cbef4a48 100644
--- a/arch/arm/src/sama5/sam_can.c
+++ b/arch/arm/src/sama5/sam_can.c
@@ -123,22 +123,7 @@
#define CAN_DEBUG_INTS (CAN_INT_ERRA | CAN_INT_WARN | CAN_INT_CERR | \
CAN_INT_SERR | CAN_INT_FERR | CAN_INT_BERR)
-/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing CAN */
-
-#ifdef CONFIG_DEBUG_CAN
-# define candbg dbg
-# define canvdbg vdbg
-# define canlldbg lldbg
-# define canllvdbg llvdbg
-#else
-# define candbg(x...)
-# define canvdbg(x...)
-# define canlldbg(x...)
-# define canllvdbg(x...)
-#endif
-
-#if !defined(CONFIG_DEBUG) || !defined(CONFIG_DEBUG_CAN)
+#ifndef CONFIG_DEBUG_CAN_INFO
# undef CONFIG_SAMA5_CAN_REGDEBUG
#endif
@@ -386,7 +371,7 @@ static uint32_t can_getreg(FAR struct sam_can_s *priv, int offset)
{
if (priv->count == 4)
{
- lldbg("...\n");
+ caninfo("...\n");
}
return regval;
@@ -403,7 +388,7 @@ static uint32_t can_getreg(FAR struct sam_can_s *priv, int offset)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", priv->count - 3);
+ caninfo("[repeats %d more times]\n", priv->count - 3);
}
/* Save the new address, value, and count */
@@ -415,7 +400,7 @@ static uint32_t can_getreg(FAR struct sam_can_s *priv, int offset)
/* Show the register value read */
- lldbg("%08x->%08x\n", regaddr, regval);
+ caninfo("%08x->%08x\n", regaddr, regval);
return regval;
}
@@ -452,7 +437,7 @@ static void can_putreg(FAR struct sam_can_s *priv, int offset, uint32_t regval)
/* Show the register value being written */
- lldbg("%08x<-%08x\n", regaddr, regval);
+ caninfo("%08x<-%08x\n", regaddr, regval);
/* Write the value */
@@ -489,29 +474,29 @@ static void can_dumpctrlregs(FAR struct sam_can_s *priv, FAR const char *msg)
if (msg)
{
- canlldbg("Control Registers: %s\n", msg);
+ caninfo("Control Registers: %s\n", msg);
}
else
{
- canlldbg("Control Registers:\n");
+ caninfo("Control Registers:\n");
}
/* CAN control and status registers */
- lldbg(" MR: %08x IMR: %08x SR: %08x\n",
- getreg32(config->base + SAM_CAN_MR_OFFSET),
- getreg32(config->base + SAM_CAN_IMR_OFFSET),
- getreg32(config->base + SAM_CAN_SR_OFFSET));
+ caninfo(" MR: %08x IMR: %08x SR: %08x\n",
+ getreg32(config->base + SAM_CAN_MR_OFFSET),
+ getreg32(config->base + SAM_CAN_IMR_OFFSET),
+ getreg32(config->base + SAM_CAN_SR_OFFSET));
- lldbg(" BR: %08x TIM: %08x TIMESTP: %08x\n",
- getreg32(config->base + SAM_CAN_BR_OFFSET),
- getreg32(config->base + SAM_CAN_TIM_OFFSET),
- getreg32(config->base + SAM_CAN_TIMESTP_OFFSET));
+ caninfo(" BR: %08x TIM: %08x TIMESTP: %08x\n",
+ getreg32(config->base + SAM_CAN_BR_OFFSET),
+ getreg32(config->base + SAM_CAN_TIM_OFFSET),
+ getreg32(config->base + SAM_CAN_TIMESTP_OFFSET));
- lldbg(" ECR: %08x WPMR: %08x WPSR: %08x\n",
- getreg32(config->base + SAM_CAN_ECR_OFFSET),
- getreg32(config->base + SAM_CAN_TCR_OFFSET),
- getreg32(config->base + SAM_CAN_ACR_OFFSET));
+ caninfo(" ECR: %08x WPMR: %08x WPSR: %08x\n",
+ getreg32(config->base + SAM_CAN_ECR_OFFSET),
+ getreg32(config->base + SAM_CAN_TCR_OFFSET),
+ getreg32(config->base + SAM_CAN_ACR_OFFSET));
}
#endif
@@ -538,30 +523,30 @@ static void can_dumpmbregs(FAR struct sam_can_s *priv, FAR const char *msg)
if (msg)
{
- canlldbg("Mailbox Registers: %s\n", msg);
+ caninfo("Mailbox Registers: %s\n", msg);
}
else
{
- canlldbg("Mailbox Registers:\n");
+ caninfo("Mailbox Registers:\n");
}
for (i = 0; i < SAM_CAN_NMAILBOXES; i++)
{
mbbase = config->base + SAM_CAN_MBn_OFFSET(i);
- lldbg(" MB%d:\n", i);
+ caninfo(" MB%d:\n", i);
/* CAN mailbox registers */
- lldbg(" MMR: %08x MAM: %08x MID: %08x MFID: %08x\n",
- getreg32(mbbase + SAM_CAN_MMR_OFFSET),
- getreg32(mbbase + SAM_CAN_MAM_OFFSET),
- getreg32(mbbase + SAM_CAN_MID_OFFSET),
- getreg32(mbbase + SAM_CAN_MFID_OFFSET));
+ caninfo(" MMR: %08x MAM: %08x MID: %08x MFID: %08x\n",
+ getreg32(mbbase + SAM_CAN_MMR_OFFSET),
+ getreg32(mbbase + SAM_CAN_MAM_OFFSET),
+ getreg32(mbbase + SAM_CAN_MID_OFFSET),
+ getreg32(mbbase + SAM_CAN_MFID_OFFSET));
- lldbg(" MSR: %08x MDL: %08x MDH: %08x\n",
- getreg32(mbbase + SAM_CAN_MSR_OFFSET),
- getreg32(mbbase + SAM_CAN_MDL_OFFSET),
- getreg32(mbbase + SAM_CAN_MDH_OFFSET));
+ caninfo(" MSR: %08x MDL: %08x MDH: %08x\n",
+ getreg32(mbbase + SAM_CAN_MSR_OFFSET),
+ getreg32(mbbase + SAM_CAN_MDL_OFFSET),
+ getreg32(mbbase + SAM_CAN_MDH_OFFSET));
}
}
#endif
@@ -722,7 +707,7 @@ static int can_recvsetup(FAR struct sam_can_s *priv)
mbndx = can_mballoc(priv);
if (mbndx < 0)
{
- candbg("ERROR: Failed to allocate mailbox %d: %d\n", mbno, mbndx);
+ canerr("ERROR: Failed to allocate mailbox %d: %d\n", mbno, mbndx);
return mbndx;
}
@@ -730,7 +715,7 @@ static int can_recvsetup(FAR struct sam_can_s *priv)
priv->rxmbset |= (1 << mbndx);
- canvdbg("CAN%d Mailbox %d: Index=%d rxmbset=%02x\n",
+ caninfo("CAN%d Mailbox %d: Index=%d rxmbset=%02x\n",
config->port, mbno, mbndx, priv->rxmbset);
/* Set up the message ID and filter mask
@@ -798,7 +783,7 @@ static void can_reset(FAR struct can_dev_s *dev)
config = priv->config;
DEBUGASSERT(config);
- canllvdbg("CAN%d\n", config->port);
+ caninfo("CAN%d\n", config->port);
UNUSED(config);
/* Get exclusive access to the CAN peripheral */
@@ -855,7 +840,7 @@ static int can_setup(FAR struct can_dev_s *dev)
config = priv->config;
DEBUGASSERT(config);
- canllvdbg("CAN%d pid: %d\n", config->port, config->pid);
+ caninfo("CAN%d pid: %d\n", config->port, config->pid);
/* Get exclusive access to the CAN peripheral */
@@ -866,7 +851,7 @@ static int can_setup(FAR struct can_dev_s *dev)
ret = can_hwinitialize(priv);
if (ret < 0)
{
- canlldbg("CAN%d H/W initialization failed: %d\n", config->port, ret);
+ canerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret);
return ret;
}
@@ -878,7 +863,7 @@ static int can_setup(FAR struct can_dev_s *dev)
ret = irq_attach(config->pid, config->handler);
if (ret < 0)
{
- canlldbg("Failed to attach CAN%d IRQ (%d)", config->port, config->pid);
+ canerr("ERROR: Failed to attach CAN%d IRQ (%d)", config->port, config->pid);
return ret;
}
@@ -887,13 +872,13 @@ static int can_setup(FAR struct can_dev_s *dev)
ret = can_recvsetup(priv);
if (ret < 0)
{
- canlldbg("CAN%d H/W initialization failed: %d\n", config->port, ret);
+ canerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret);
return ret;
}
/* Enable all error interrupts */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
can_putreg(priv, SAM_CAN_IER_OFFSET, CAN_DEBUG_INTS);
#endif
@@ -933,7 +918,7 @@ static void can_shutdown(FAR struct can_dev_s *dev)
config = priv->config;
DEBUGASSERT(config);
- canllvdbg("CAN%d\n", config->port);
+ caninfo("CAN%d\n", config->port);
/* Get exclusive access to the CAN peripheral */
@@ -972,7 +957,7 @@ static void can_rxint(FAR struct can_dev_s *dev, bool enable)
FAR struct sam_can_s *priv = dev->cd_priv;
DEBUGASSERT(priv && priv->config);
- canllvdbg("CAN%d enable: %d\n", priv->config->port, enable);
+ caninfo("CAN%d enable: %d\n", priv->config->port, enable);
/* Enable/disable the mailbox interrupts from all receive mailboxes */
@@ -1005,7 +990,7 @@ static void can_txint(FAR struct can_dev_s *dev, bool enable)
FAR struct sam_can_s *priv = dev->cd_priv;
DEBUGASSERT(priv && priv->config);
- canllvdbg("CAN%d enable: %d\n", priv->config->port, enable);
+ caninfo("CAN%d enable: %d\n", priv->config->port, enable);
/* Get exclusive access to the CAN peripheral */
@@ -1106,9 +1091,9 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
priv = dev->cd_priv;
DEBUGASSERT(priv && priv->config);
- canllvdbg("CAN%d\n", priv->config->port);
- canllvdbg("CAN%d ID: %d DLC: %d\n",
- priv->config->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
+ caninfo("CAN%d\n", priv->config->port);
+ caninfo("CAN%d ID: %d DLC: %d\n",
+ priv->config->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
/* Get exclusive access to the CAN peripheral */
@@ -1119,14 +1104,14 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
mbndx = can_mballoc(priv);
if (mbndx < 0)
{
- candbg("ERROR: CAN%d failed to allocate a mailbox: %d\n",
+ canerr("ERROR: CAN%d failed to allocate a mailbox: %d\n",
priv->config->port, mbndx);
return mbndx;
}
priv->txmbset |= (1 << mbndx);
- canvdbg("Mailbox Index=%d txmbset=%02x\n", mbndx, priv->txmbset);
+ caninfo("Mailbox Index=%d txmbset=%02x\n", mbndx, priv->txmbset);
/* Set up the ID and mask, standard 11-bit or extended 29-bit.
* REVISIT: This logic should be capable of sending standard messages
@@ -1342,7 +1327,7 @@ static inline void can_rxinterrupt(FAR struct can_dev_s *dev, int mbndx,
ret = can_receive(dev, &hdr, (FAR uint8_t *)md);
if (ret < 0)
{
- canlldbg("ERROR: can_receive failed: %d\n", ret);
+ canerr("ERROR: can_receive failed: %d\n", ret);
}
/* Set the MTCR flag in the CAN_MCRx register. This clears the
@@ -1437,9 +1422,9 @@ static inline void can_mbinterrupt(FAR struct can_dev_s *dev, int mbndx)
case CAN_MMR_MOT_CONSUMER: /* Consumer Mailbox */
case CAN_MMR_MOT_PRODUCER: /* Producer Mailbox */
case CAN_MMR_MOT_DISABLED: /* Mailbox is disabled */
- canlldbg("ERROR: CAN%d MB%d: Unsupported or invalid mailbox type\n",
- priv->config->port, mbndx);
- canlldbg(" MSR: %08x MMR: %08x\n", msr, mmr);
+ canerr("ERROR: CAN%d MB%d: Unsupported or invalid mailbox type\n",
+ priv->config->port, mbndx);
+ canerr(" MSR: %08x MMR: %08x\n", msr, mmr);
break;
}
}
@@ -1530,8 +1515,8 @@ static void can_interrupt(FAR struct can_dev_s *dev)
if ((pending & ~CAN_INT_MBALL) != 0)
{
- canlldbg("ERROR: CAN%d system interrupt, SR=%08x IMR=%08x\n",
- priv->config->port, sr, imr);
+ canerr("ERROR: CAN%d system interrupt, SR=%08x IMR=%08x\n",
+ priv->config->port, sr, imr);
}
}
@@ -1708,7 +1693,7 @@ static int can_bittiming(struct sam_can_s *priv)
{
/* The BRP field must be within the range 1 - 0x7f */
- candbg("CAN%d: baud %d too high\n", config->port, config->baud);
+ canerr("CAN%d ERROR: baud %d too high\n", config->port, config->baud);
return -EINVAL;
}
@@ -1756,7 +1741,7 @@ static int can_bittiming(struct sam_can_s *priv)
if ((propag + phase1 + phase2) != (uint32_t)(tq - 4))
{
- candbg("CAN%d: Could not realize baud %d\n", config->port, config->baud);
+ canerr("CAN%d ERROR: Could not realize baud %d\n", config->port, config->baud);
return -EINVAL;
}
@@ -1788,7 +1773,7 @@ static int can_autobaud(struct sam_can_s *priv)
uint32_t regval;
int ret;
- canllvdbg("CAN%d\n", config->port);
+ caninfo("CAN%d\n", config->port);
/* The CAN controller can start listening to the network in Autobaud Mode.
* In this case, the error counters are locked and a mailbox may be
@@ -1858,7 +1843,7 @@ static int can_hwinitialize(struct sam_can_s *priv)
uint32_t mck;
int ret;
- canllvdbg("CAN%d\n", config->port);
+ caninfo("CAN%d\n", config->port);
/* Configure CAN pins */
@@ -1890,7 +1875,7 @@ static int can_hwinitialize(struct sam_can_s *priv)
}
else
{
- candbg("ERROR: Cannot realize CAN input frequency\n");
+ canerr("ERROR: Cannot realize CAN input frequency\n");
return -EINVAL;
}
@@ -1912,7 +1897,7 @@ static int can_hwinitialize(struct sam_can_s *priv)
ret = can_bittiming(priv);
if (ret < 0)
{
- candbg("ERROR: Failed to set bit timing: %d\n", ret);
+ canerr("ERROR: Failed to set bit timing: %d\n", ret);
return ret;
}
@@ -1922,7 +1907,7 @@ static int can_hwinitialize(struct sam_can_s *priv)
ret = can_autobaud(priv);
if (ret < 0)
{
- candbg("ERROR: can_autobaud failed: %d\n", ret);
+ canerr("ERROR: can_autobaud failed: %d\n", ret);
return ret;
}
#endif
@@ -1970,7 +1955,7 @@ FAR struct can_dev_s *sam_caninitialize(int port)
FAR struct sam_can_s *priv;
FAR const struct sam_config_s *config;
- canvdbg("CAN%d\n", port);
+ caninfo("CAN%d\n", port);
/* NOTE: Peripherical clocking for CAN0 and/or CAN1 was already provided
* by sam_clockconfig() early in the reset sequence.
@@ -1999,7 +1984,7 @@ FAR struct can_dev_s *sam_caninitialize(int port)
else
#endif
{
- candbg("ERROR: Unsupported port %d\n", port);
+ canerr("ERROR: Unsupported port %d\n", port);
return NULL;
}
diff --git a/arch/arm/src/sama5/sam_dmac.c b/arch/arm/src/sama5/sam_dmac.c
index bf3f1481684dc365848620542012ee4aac424e42..e3a813c1b211889c8887ad86766e94e7fadc319b 100644
--- a/arch/arm/src/sama5/sam_dmac.c
+++ b/arch/arm/src/sama5/sam_dmac.c
@@ -657,7 +657,7 @@ static uint8_t sam_channel(uint8_t pid, const struct sam_pidmap_s *table,
}
}
- dmadbg("No channel found for pid %d\n", pid);
+ dmaerr("ERROR: No channel found for pid %d\n", pid);
DEBUGPANIC();
return 0x3f;
}
@@ -1364,7 +1364,7 @@ sam_allocdesc(struct sam_dmach_s *dmach, struct dma_linklist_s *prev,
* Obviously setting it to zero would break that usage.
*/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (saddr != 0)
#endif
{
@@ -1818,7 +1818,7 @@ static int sam_dmac_interrupt(struct sam_dmac_s *dmac)
{
/* Yes... Terminate the transfer with an error? */
- dmalldbg("ERROR: DMA failed: %08x\n", regval);
+ dmaerr("ERROR: DMA failed: %08x\n", regval);
sam_dmaterminate(dmach, -EIO);
}
@@ -1920,7 +1920,7 @@ void sam_dmainitialize(struct sam_dmac_s *dmac)
void weak_function up_dmainitialize(void)
{
#ifdef CONFIG_SAMA5_DMAC0
- dmallvdbg("Initialize DMAC0\n");
+ dmainfo("Initialize DMAC0\n");
/* Enable peripheral clock */
@@ -1940,7 +1940,7 @@ void weak_function up_dmainitialize(void)
#endif
#ifdef CONFIG_SAMA5_DMAC1
- dmallvdbg("Initialize DMAC1\n");
+ dmainfo("Initialize DMAC1\n");
/* Enable peripheral clock */
@@ -2002,7 +2002,7 @@ DMA_HANDLE sam_dmachannel(uint8_t dmacno, uint32_t chflags)
#endif
{
- dmadbg("ERROR: Bad DMAC number: %d\n", dmacno);
+ dmaerr("ERROR: Bad DMAC number: %d\n", dmacno);
DEBUGPANIC();
return (DMA_HANDLE)NULL;
}
@@ -2046,12 +2046,12 @@ DMA_HANDLE sam_dmachannel(uint8_t dmacno, uint32_t chflags)
if (dmach)
{
- dmavdbg("DMAC%d CH%d: chflags: %08x returning dmach: %p\n",
+ dmainfo("DMAC%d CH%d: chflags: %08x returning dmach: %p\n",
(int)dmacno, dmach->chan, (int)chflags, dmach);
}
else
{
- dmadbg("ERROR: Failed allocate DMAC%d channel\n", (int)dmacno);
+ dmaerr("ERROR: Failed allocate DMAC%d channel\n", (int)dmacno);
}
return (DMA_HANDLE)dmach;
@@ -2082,13 +2082,13 @@ void sam_dmaconfig(DMA_HANDLE handle, uint32_t chflags)
dmach->flags = chflags;
#if defined(CONFIG_SAMA5_DMAC0) && defined(CONFIG_SAMA5_DMAC1)
- dmavdbg("DMAC%d CH%d: chflags: %08x\n",
+ dmainfo("DMAC%d CH%d: chflags: %08x\n",
dmach->dmac, dmach->chan, (int)chflags);
#elif defined(CONFIG_SAMA5_DMAC0)
- dmavdbg("DMAC0 CH%d: chflags: %08x\n",
+ dmainfo("DMAC0 CH%d: chflags: %08x\n",
dmach->chan, (int)chflags);
#else
- dmavdbg("DMAC1 CH%d: chflags: %08x\n",
+ dmainfo("DMAC1 CH%d: chflags: %08x\n",
dmach->chan, (int)chflags);
#endif
}
@@ -2110,7 +2110,7 @@ void sam_dmafree(DMA_HANDLE handle)
{
struct sam_dmach_s *dmach = (struct sam_dmach_s *)handle;
- dmavdbg("dmach: %p\n", dmach);
+ dmainfo("dmach: %p\n", dmach);
DEBUGASSERT((dmach != NULL) && (dmach->inuse));
/* Mark the channel no longer in use. Clearing the inuse flag is an atomic
@@ -2140,10 +2140,10 @@ int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
size_t remaining;
int ret = OK;
- dmavdbg("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
+ dmainfo("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
dmach, (int)paddr, (int)maddr, (int)nbytes);
DEBUGASSERT(dmach);
- dmavdbg("llhead: %p lltail: %p\n", dmach->llhead, dmach->lltail);
+ dmainfo("llhead: %p lltail: %p\n", dmach->llhead, dmach->lltail);
/* The maximum transfer size in bytes depends upon the maximum number of
* transfers and the number of bytes per transfer.
@@ -2219,10 +2219,10 @@ int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
size_t remaining;
int ret = OK;
- dmavdbg("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
+ dmainfo("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
dmach, (int)paddr, (int)maddr, (int)nbytes);
DEBUGASSERT(dmach);
- dmavdbg("llhead: %p lltail: %p\n", dmach->llhead, dmach->lltail);
+ dmainfo("llhead: %p lltail: %p\n", dmach->llhead, dmach->lltail);
/* The maximum transfer size in bytes depends upon the maximum number of
* transfers and the number of bytes per transfer.
@@ -2294,7 +2294,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
struct sam_dmach_s *dmach = (struct sam_dmach_s *)handle;
int ret = -EINVAL;
- dmavdbg("dmach: %p callback: %p arg: %p\n", dmach, callback, arg);
+ dmainfo("dmach: %p callback: %p arg: %p\n", dmach, callback, arg);
DEBUGASSERT(dmach != NULL);
/* Verify that the DMA has been setup (i.e., at least one entry in the
@@ -2338,7 +2338,7 @@ void sam_dmastop(DMA_HANDLE handle)
struct sam_dmach_s *dmach = (struct sam_dmach_s *)handle;
irqstate_t flags;
- dmavdbg("dmach: %p\n", dmach);
+ dmainfo("dmach: %p\n", dmach);
DEBUGASSERT(dmach != NULL);
flags = enter_critical_section();
@@ -2414,27 +2414,27 @@ void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
struct sam_dmach_s *dmach = (struct sam_dmach_s *)handle;
struct sam_dmac_s *dmac = sam_controller(dmach);
- dmadbg("%s\n", msg);
- dmadbg(" DMA Global Registers:\n");
- dmadbg(" GCFG[%08x]: %08x\n", dmac->base + SAM_DMAC_GCFG_OFFSET, regs->gcfg);
- dmadbg(" EN[%08x]: %08x\n", dmac->base + SAM_DMAC_EN_OFFSET, regs->en);
- dmadbg(" SREQ[%08x]: %08x\n", dmac->base + SAM_DMAC_SREQ_OFFSET, regs->sreq);
- dmadbg(" CREQ[%08x]: %08x\n", dmac->base + SAM_DMAC_CREQ_OFFSET, regs->creq);
- dmadbg(" LAST[%08x]: %08x\n", dmac->base + SAM_DMAC_LAST_OFFSET, regs->last);
- dmadbg(" EBCIMR[%08x]: %08x\n", dmac->base + SAM_DMAC_EBCIMR_OFFSET, regs->ebcimr);
- dmadbg(" EBCISR[%08x]: %08x\n", dmac->base + SAM_DMAC_EBCISR_OFFSET, regs->ebcisr);
- dmadbg(" CHSR[%08x]: %08x\n", dmac->base + SAM_DMAC_CHSR_OFFSET, regs->chsr);
- dmadbg(" WPMR[%08x]: %08x\n", dmac->base + SAM_DMAC_WPMR_OFFSET, regs->wpmr);
- dmadbg(" WPSR[%08x]: %08x\n", dmac->base + SAM_DMAC_WPSR_OFFSET, regs->wpsr);
- dmadbg(" DMA Channel Registers:\n");
- dmadbg(" SADDR[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_SADDR_OFFSET, regs->saddr);
- dmadbg(" DADDR[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_DADDR_OFFSET, regs->daddr);
- dmadbg(" DSCR[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_DSCR_OFFSET, regs->dscr);
- dmadbg(" CTRLA[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_CTRLA_OFFSET, regs->ctrla);
- dmadbg(" CTRLB[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_CTRLB_OFFSET, regs->ctrlb);
- dmadbg(" CFG[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_CFG_OFFSET, regs->cfg);
- dmadbg(" SPIP[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_SPIP_OFFSET, regs->spip);
- dmadbg(" DPIP[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_DPIP_OFFSET, regs->dpip);
+ dmainfo("%s\n", msg);
+ dmainfo(" DMA Global Registers:\n");
+ dmainfo(" GCFG[%08x]: %08x\n", dmac->base + SAM_DMAC_GCFG_OFFSET, regs->gcfg);
+ dmainfo(" EN[%08x]: %08x\n", dmac->base + SAM_DMAC_EN_OFFSET, regs->en);
+ dmainfo(" SREQ[%08x]: %08x\n", dmac->base + SAM_DMAC_SREQ_OFFSET, regs->sreq);
+ dmainfo(" CREQ[%08x]: %08x\n", dmac->base + SAM_DMAC_CREQ_OFFSET, regs->creq);
+ dmainfo(" LAST[%08x]: %08x\n", dmac->base + SAM_DMAC_LAST_OFFSET, regs->last);
+ dmainfo(" EBCIMR[%08x]: %08x\n", dmac->base + SAM_DMAC_EBCIMR_OFFSET, regs->ebcimr);
+ dmainfo(" EBCISR[%08x]: %08x\n", dmac->base + SAM_DMAC_EBCISR_OFFSET, regs->ebcisr);
+ dmainfo(" CHSR[%08x]: %08x\n", dmac->base + SAM_DMAC_CHSR_OFFSET, regs->chsr);
+ dmainfo(" WPMR[%08x]: %08x\n", dmac->base + SAM_DMAC_WPMR_OFFSET, regs->wpmr);
+ dmainfo(" WPSR[%08x]: %08x\n", dmac->base + SAM_DMAC_WPSR_OFFSET, regs->wpsr);
+ dmainfo(" DMA Channel Registers:\n");
+ dmainfo(" SADDR[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_SADDR_OFFSET, regs->saddr);
+ dmainfo(" DADDR[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_DADDR_OFFSET, regs->daddr);
+ dmainfo(" DSCR[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_DSCR_OFFSET, regs->dscr);
+ dmainfo(" CTRLA[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_CTRLA_OFFSET, regs->ctrla);
+ dmainfo(" CTRLB[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_CTRLB_OFFSET, regs->ctrlb);
+ dmainfo(" CFG[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_CFG_OFFSET, regs->cfg);
+ dmainfo(" SPIP[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_SPIP_OFFSET, regs->spip);
+ dmainfo(" DPIP[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_DPIP_OFFSET, regs->dpip);
}
#endif /* CONFIG_DEBUG_DMA */
#endif /* CONFIG_SAMA5_DMAC0 || CONFIG_SAMA5_DMAC1 */
diff --git a/arch/arm/src/sama5/sam_dmac.h b/arch/arm/src/sama5/sam_dmac.h
index c9fc885369db4f1e689ebc442b2b638cf47c2a0c..b6ba92c23f1f60f55796ff8def881c5e9e5e9dd2 100644
--- a/arch/arm/src/sama5/sam_dmac.h
+++ b/arch/arm/src/sama5/sam_dmac.h
@@ -52,7 +52,7 @@
/* Configuration ********************************************************************/
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_FEATURES
# undef CONFIG_DEBUG_DMA
#endif
diff --git a/arch/arm/src/sama5/sam_ehci.c b/arch/arm/src/sama5/sam_ehci.c
index a6cb3d0d7aacbf46ccdd5113dbde8a7e349a461c..78135e3e8da744b05fddac210d79d1b7aa781732 100644
--- a/arch/arm/src/sama5/sam_ehci.c
+++ b/arch/arm/src/sama5/sam_ehci.c
@@ -112,7 +112,7 @@
/* Debug options */
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_USB_INFO
# undef CONFIG_SAMA5_EHCI_REGDEBUG
#endif
@@ -127,13 +127,6 @@
# undef CONFIG_SAMA5_UHPHS_RHPORT1
#endif
-/* Simplify DEBUG checks */
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# undef CONFIG_DEBUG_USB
-#endif
-
/* For now, suppress use of PORTA in any event. I use that for SAM-BA and
* would prefer that the board not try to drive VBUS on that port!
*/
@@ -635,7 +628,7 @@ static uint32_t sam_swap32(uint32_t value)
static void sam_printreg(volatile uint32_t *regaddr, uint32_t regval,
bool iswrite)
{
- lldbg("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
+ uinfo("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
}
#endif
@@ -686,7 +679,7 @@ static void sam_checkreg(volatile uint32_t *regaddr, uint32_t regval, bool iswri
{
/* No.. More than one. */
- lldbg("[repeats %d more times]\n", count);
+ uinfo("[repeats %d more times]\n", count);
}
}
@@ -1275,13 +1268,13 @@ static int sam_qh_flush(struct sam_qh_s *qh)
#ifdef CONFIG_SAMA5_EHCI_REGDEBUG
static void sam_qtd_print(struct sam_qtd_s *qtd)
{
- udbg(" QTD[%p]:\n", qtd);
- udbg(" hw:\n");
- udbg(" nqp: %08x alt: %08x token: %08x\n",
- qtd->hw.nqp, qtd->hw.alt, qtd->hw.token);
- udbg(" bpl: %08x %08x %08x %08x %08x\n",
- qtd->hw.bpl[0], qtd->hw.bpl[1], qtd->hw.bpl[2],
- qtd->hw.bpl[3], qtd->hw.bpl[4]);
+ uinfo(" QTD[%p]:\n", qtd);
+ uinfo(" hw:\n");
+ uinfo(" nqp: %08x alt: %08x token: %08x\n",
+ qtd->hw.nqp, qtd->hw.alt, qtd->hw.token);
+ uinfo(" bpl: %08x %08x %08x %08x %08x\n",
+ qtd->hw.bpl[0], qtd->hw.bpl[1], qtd->hw.bpl[2],
+ qtd->hw.bpl[3], qtd->hw.bpl[4]);
}
#endif
@@ -1299,30 +1292,30 @@ static void sam_qh_print(struct sam_qh_s *qh)
struct sam_epinfo_s *epinfo;
struct ehci_overlay_s *overlay;
- udbg("QH[%p]:\n", qh);
- udbg(" hw:\n");
- udbg(" hlp: %08x epchar: %08x epcaps: %08x cqp: %08x\n",
- qh->hw.hlp, qh->hw.epchar, qh->hw.epcaps, qh->hw.cqp);
+ uinfo("QH[%p]:\n", qh);
+ uinfo(" hw:\n");
+ uinfo(" hlp: %08x epchar: %08x epcaps: %08x cqp: %08x\n",
+ qh->hw.hlp, qh->hw.epchar, qh->hw.epcaps, qh->hw.cqp);
overlay = &qh->hw.overlay;
- udbg(" overlay:\n");
- udbg(" nqp: %08x alt: %08x token: %08x\n",
- overlay->nqp, overlay->alt, overlay->token);
- udbg(" bpl: %08x %08x %08x %08x %08x\n",
- overlay->bpl[0], overlay->bpl[1], overlay->bpl[2],
- overlay->bpl[3], overlay->bpl[4]);
+ uinfo(" overlay:\n");
+ uinfo(" nqp: %08x alt: %08x token: %08x\n",
+ overlay->nqp, overlay->alt, overlay->token);
+ uinfo(" bpl: %08x %08x %08x %08x %08x\n",
+ overlay->bpl[0], overlay->bpl[1], overlay->bpl[2],
+ overlay->bpl[3], overlay->bpl[4]);
- udbg(" fqp:\n", qh->fqp);
+ uinfo(" fqp:\n", qh->fqp);
epinfo = qh->epinfo;
- udbg(" epinfo[%p]:\n", epinfo);
+ uinfo(" epinfo[%p]:\n", epinfo);
if (epinfo)
{
- udbg(" EP%d DIR=%s FA=%08x TYPE=%d MaxPacket=%d\n",
- epinfo->epno, epinfo->dirin ? "IN" : "OUT", epinfo->devaddr,
- epinfo->xfrtype, epinfo->maxpacket);
- udbg(" Toggle=%d iocwait=%d speed=%d result=%d\n",
- epinfo->toggle, epinfo->iocwait, epinfo->speed, epinfo->result);
+ uinfo(" EP%d DIR=%s FA=%08x TYPE=%d MaxPacket=%d\n",
+ epinfo->epno, epinfo->dirin ? "IN" : "OUT", epinfo->devaddr,
+ epinfo->xfrtype, epinfo->maxpacket);
+ uinfo(" Toggle=%d iocwait=%d speed=%d result=%d\n",
+ epinfo->toggle, epinfo->iocwait, epinfo->speed, epinfo->result);
}
}
#endif
@@ -1928,7 +1921,7 @@ static int sam_async_setup(struct sam_rhport_s *rhport,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_ASYNCXFR, epinfo->epno, buflen);
#else
- uvdbg("RHport%d EP%d: buffer=%p, buflen=%d, req=%p\n",
+ uinfo("RHport%d EP%d: buffer=%p, buflen=%d, req=%p\n",
RHPORT(rhport), epinfo->epno, buffer, buflen, req);
#endif
@@ -2206,7 +2199,7 @@ static int sam_intr_setup(struct sam_rhport_s *rhport,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_INTRXFR, epinfo->epno, buflen);
#else
- uvdbg("RHport%d EP%d: buffer=%p, buflen=%d\n",
+ uinfo("RHport%d EP%d: buffer=%p, buflen=%d\n",
RHPORT(rhport), epinfo->epno, buffer, buflen);
#endif
@@ -3187,7 +3180,7 @@ static int sam_ehci_tophalf(int irq, FAR void *context)
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace1(EHCI_VTRACE1_TOPHALF, usbsts & regval);
#else
- ullvdbg("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
+ uinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
#endif
/* Handle all unmasked interrupt sources */
@@ -3730,7 +3723,7 @@ static int sam_epalloc(FAR struct usbhost_driver_s *drvr,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_EPALLOC, epdesc->addr, epdesc->xfrtype);
#else
- uvdbg("EP%d DIR=%s FA=%08x TYPE=%d Interval=%d MaxPacket=%d\n",
+ uinfo("EP%d DIR=%s FA=%08x TYPE=%d Interval=%d MaxPacket=%d\n",
epdesc->addr, epdesc->in ? "IN" : "OUT", hport->funcaddr,
epdesc->xfrtype, epdesc->interval, epdesc->mxpacketsize);
#endif
@@ -4019,7 +4012,7 @@ static int sam_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(EHCI_VTRACE2_CTRLINOUT, RHPORT(rhport), req->req);
#else
- uvdbg("RHPort%d type: %02x req: %02x value: %02x%02x index: %02x%02x len: %04x\n",
+ uinfo("RHPort%d type: %02x req: %02x value: %02x%02x index: %02x%02x len: %04x\n",
RHPORT(rhport), req->type, req->req, req->value[1], req->value[0],
req->index[1], req->index[0], len);
#endif
@@ -4042,7 +4035,7 @@ static int sam_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
ret = sam_async_setup(rhport, ep0info, req, buffer, len);
if (ret < 0)
{
- udbg("ERROR: sam_async_setup failed: %d\n", ret);
+ uerr("ERROR: sam_async_setup failed: %d\n", ret);
goto errout_with_iocwait;
}
@@ -4160,7 +4153,7 @@ static ssize_t sam_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
if (ret < 0)
{
- udbg("ERROR: Transfer setup failed: %d\n", ret);
+ uerr("ERROR: Transfer setup failed: %d\n", ret);
goto errout_with_iocwait;
}
@@ -4500,7 +4493,7 @@ static int sam_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
- ullvdbg("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+ uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */
@@ -4701,7 +4694,7 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
FAR struct usbhost_hubport_s *hport;
irqstate_t flags;
uint32_t regval;
-#if defined(CONFIG_DEBUG_USB) && defined(CONFIG_DEBUG_VERBOSE)
+#if defined(CONFIG_DEBUG_USB) && defined(CONFIG_DEBUG_ASSERTIONS)
uint16_t regval16;
unsigned int nports;
#endif
@@ -4952,7 +4945,7 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
sam_putreg(EHCI_INT_ALLINTS, &HCOR->usbsts);
-#if defined(CONFIG_DEBUG_USB) && defined(CONFIG_DEBUG_VERBOSE)
+#if defined(CONFIG_DEBUG_USB) && defined(CONFIG_DEBUG_ASSERTIONS)
/* Show the EHCI version */
regval16 = sam_swap16(HCCR->hciversion);
diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c
index 5d3ad03e60beb7ae8b113390ae3ba87dbae656ad..3972f2324ac5b37fc2f0869a646b21d6d4b5f591 100644
--- a/arch/arm/src/sama5/sam_emaca.c
+++ b/arch/arm/src/sama5/sam_emaca.c
@@ -223,7 +223,7 @@
* enabled.
*/
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_NET_INFO
# undef CONFIG_SAMA5_EMACA_REGDEBUG
#endif
@@ -267,9 +267,9 @@ struct sam_emac_s
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
/* Used to track transmit and receive descriptors */
@@ -335,7 +335,7 @@ static uint8_t g_rxbuffer[CONFIG_SAMA5_EMAC_NRXBUFFERS * EMAC_RX_UNITSIZE]
****************************************************************************/
/* Register operations ******************************************************/
-#if defined(CONFIG_SAMA5_EMACA_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAMA5_EMACA_REGDEBUG
static bool sam_checkreg(struct sam_emac_s *priv, bool wr,
uint32_t regval, uintptr_t address);
static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t addr);
@@ -390,7 +390,7 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, long arg);
/* PHY Initialization */
-#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_VERBOSE)
+#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_INFO)
static void sam_phydump(struct sam_emac_s *priv);
#else
# define sam_phydump(priv)
@@ -461,7 +461,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", priv->ntimes);
+ ninfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@@ -493,7 +493,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t address)
if (sam_checkreg(priv, false, regval, address))
{
- lldbg("%08x->%08x\n", address, regval);
+ ninfo("%08x->%08x\n", address, regval);
}
return regval;
@@ -514,7 +514,7 @@ static void sam_putreg(struct sam_emac_s *priv, uintptr_t address,
{
if (sam_checkreg(priv, true, regval, address))
{
- lldbg("%08x<-%08x\n", address, regval);
+ ninfo("%08x<-%08x\n", address, regval);
}
putreg32(regval, address);
@@ -607,7 +607,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->txdesc = (struct emac_txdesc_s *)kmm_memalign(8, allocsize);
if (!priv->txdesc)
{
- nlldbg("ERROR: Failed to allocate TX descriptors\n");
+ nerr("ERROR: Failed to allocate TX descriptors\n");
return -ENOMEM;
}
@@ -617,7 +617,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->rxdesc = (struct emac_rxdesc_s *)kmm_memalign(8, allocsize);
if (!priv->rxdesc)
{
- nlldbg("ERROR: Failed to allocate RX descriptors\n");
+ nerr("ERROR: Failed to allocate RX descriptors\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -628,7 +628,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->txbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->txbuffer)
{
- nlldbg("ERROR: Failed to allocate TX buffer\n");
+ nerr("ERROR: Failed to allocate TX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -637,7 +637,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->rxbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->rxbuffer)
{
- nlldbg("ERROR: Failed to allocate RX buffer\n");
+ nerr("ERROR: Failed to allocate RX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -725,14 +725,14 @@ static int sam_transmit(struct sam_emac_s *priv)
uint32_t regval;
uint32_t status;
- nllvdbg("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
+ ninfo("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
/* Check parameter */
if (dev->d_len > EMAC_TX_UNITSIZE)
{
- nlldbg("ERROR: Packet too big: %d\n", dev->d_len);
+ nerr("ERROR: Packet too big: %d\n", dev->d_len);
return -EINVAL;
}
@@ -744,7 +744,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
- nlldbg("ERROR: No free TX descriptors\n");
+ nerr("ERROR: No free TX descriptors\n");
return -EBUSY;
}
@@ -806,7 +806,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
- nllvdbg("Disabling RX interrupts\n");
+ ninfo("Disabling RX interrupts\n");
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_RCOMP);
}
@@ -817,7 +817,7 @@ static int sam_transmit(struct sam_emac_s *priv)
* Function: sam_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -926,7 +926,7 @@ static void sam_dopoll(struct sam_emac_s *priv)
if (sam_txfree(priv) > 0)
{
- /* If we have the descriptor, then poll uIP for new XMIT data. */
+ /* If we have the descriptor, then poll the network for new XMIT data. */
(void)devif_poll(dev, sam_txpoll);
}
@@ -986,7 +986,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
arch_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
- nllvdbg("rxndx: %d\n", rxndx);
+ ninfo("rxndx: %d\n", rxndx);
while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
{
@@ -1042,7 +1042,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
{
if (rxndx == priv->rxndx)
{
- nllvdbg("ERROR: No EOF (Invalid of buffers too small)\n");
+ nerr("ERROR: No EOF (Invalid of buffers too small)\n");
do
{
/* Give ownership back to the EMAC */
@@ -1097,7 +1097,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Frame size from the EMAC */
dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
- nllvdbg("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
+ ninfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
/* All data have been copied in the application frame buffer,
* release the RX descriptor
@@ -1128,11 +1128,11 @@ static int sam_recvframe(struct sam_emac_s *priv)
* all of the data.
*/
- nllvdbg("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
+ ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
if (pktlen < dev->d_len)
{
- nlldbg("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
+ nerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
return -E2BIG;
}
@@ -1172,7 +1172,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* No packet was found */
priv->rxndx = rxndx;
- nllvdbg("rxndx: %d\n", priv->rxndx);
+ ninfo("rxndx: %d\n", priv->rxndx);
return -EAGAIN;
}
@@ -1206,13 +1206,13 @@ static void sam_receive(struct sam_emac_s *priv)
{
sam_dumppacket("Received packet", dev->d_buf, dev->d_len);
- /* Check if the packet is a valid size for the uIP buffer configuration
+ /* Check if the packet is a valid size for the network buffer configuration
* (this should not happen)
*/
if (dev->d_len > CONFIG_NET_ETH_MTU)
{
- nlldbg("DROPPED: Too big: %d\n", dev->d_len);
+ nwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
continue;
}
@@ -1227,7 +1227,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
- nllvdbg("IPv4 frame\n");
+ ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@@ -1267,7 +1267,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
- nllvdbg("Iv6 frame\n");
+ ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@@ -1304,7 +1304,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
- nllvdbg("ARP frame\n");
+ ninfo("ARP frame\n");
/* Handle ARP packet */
@@ -1322,7 +1322,7 @@ static void sam_receive(struct sam_emac_s *priv)
else
#endif
{
- nlldbg("DROPPED: Unknown type: %04x\n", BUF->type);
+ nwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
}
}
}
@@ -1410,7 +1410,7 @@ static void sam_txdone(struct sam_emac_s *priv)
sam_putreg(priv, SAM_EMAC_IER, EMAC_INT_RCOMP);
}
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -1449,7 +1449,7 @@ static int sam_emac_interrupt(int irq, void *context)
imr = sam_getreg(priv, SAM_EMAC_IMR);
pending = isr & ~(imr | EMAC_INT_UNUSED);
- nllvdbg("isr: %08x pending: %08x\n", isr, pending);
+ ninfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
@@ -1475,7 +1475,7 @@ static int sam_emac_interrupt(int irq, void *context)
clrbits = EMAC_TSR_RLES | sam_txinuse(priv);
sam_txreset(priv);
- nlldbg("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
+ nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval |= EMAC_NCR_TE;
@@ -1486,7 +1486,7 @@ static int sam_emac_interrupt(int irq, void *context)
if ((tsr & EMAC_TSR_COL) != 0)
{
- nlldbg("ERROR: Collision occurred TSR: %08x\n", tsr);
+ nerr("ERROR: Collision occurred TSR: %08x\n", tsr);
clrbits |= EMAC_TSR_COL;
}
@@ -1494,7 +1494,7 @@ static int sam_emac_interrupt(int irq, void *context)
if ((tsr & EMAC_TSR_BEX) != 0)
{
- nlldbg("ERROR: Buffers exhausted mid-frame TSR: %08x\n", tsr);
+ nerr("ERROR: Buffers exhausted mid-frame TSR: %08x\n", tsr);
clrbits |= EMAC_TSR_BEX;
}
@@ -1509,7 +1509,7 @@ static int sam_emac_interrupt(int irq, void *context)
if ((tsr & EMAC_TSR_UND) != 0)
{
- nlldbg("ERROR: Transmit Underrun TSR: %08x\n", tsr);
+ nerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
clrbits |= EMAC_TSR_UND;
}
@@ -1546,7 +1546,7 @@ static int sam_emac_interrupt(int irq, void *context)
if ((rsr & EMAC_RSR_OVR) != 0)
{
- nlldbg("ERROR: Receiver overrun RSR: %08x\n", rsr);
+ nerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_OVR;
}
@@ -1563,7 +1563,7 @@ static int sam_emac_interrupt(int irq, void *context)
if ((rsr & EMAC_RSR_BNA) != 0)
{
- nlldbg("ERROR: Buffer not available RSR: %08x\n", rsr);
+ nerr("ERROR: Buffer not available RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_BNA;
}
@@ -1584,7 +1584,7 @@ static int sam_emac_interrupt(int irq, void *context)
if ((pending & EMAC_INT_PFR) != 0)
{
- nlldbg("Pause frame received\n");
+ nwarn("WARNING: Pause frame received\n");
}
/* Check for Pause Time Zero (PTZ)
@@ -1594,7 +1594,7 @@ static int sam_emac_interrupt(int irq, void *context)
if ((pending & EMAC_INT_PTZ) != 0)
{
- nlldbg("Pause TO!\n");
+ nwarn("WARNING: Pause TO!\n");
}
#endif
@@ -1624,7 +1624,7 @@ static void sam_txtimeout(int argc, uint32_t arg, ...)
{
struct sam_emac_s *priv = (struct sam_emac_s *)arg;
- nlldbg("Timeout!\n");
+ nerr("ERROR: Timeout!\n");
/* Then reset the hardware. Just take the interface down, then back
* up again.
@@ -1633,7 +1633,7 @@ static void sam_txtimeout(int argc, uint32_t arg, ...)
sam_ifdown(&priv->dev);
sam_ifup(&priv->dev);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -1667,7 +1667,7 @@ static void sam_polltimer(int argc, uint32_t arg, ...)
if (sam_txfree(priv) > 0)
{
- /* Update TCP timing states and poll uIP for new XMIT data. */
+ /* Update TCP timing states and poll the network for new XMIT data. */
(void)devif_timer(dev, sam_txpoll);
}
@@ -1699,13 +1699,13 @@ static int sam_ifup(struct net_driver_s *dev)
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
int ret;
- nlldbg("Bringing up: %d.%d.%d.%d\n",
- dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
- (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+ ninfo("Bringing up: %d.%d.%d.%d\n",
+ dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+ (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
/* Configure the EMAC interface for normal operation. */
- nllvdbg("Initialize the EMAC\n");
+ ninfo("Initialize the EMAC\n");
sam_emac_configure(priv);
/* Set the MAC address (should have been configured while we were down) */
@@ -1723,7 +1723,7 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_phyinit(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phyinit failed: %d\n", ret);
+ nerr("ERROR: sam_phyinit failed: %d\n", ret);
return ret;
}
@@ -1732,16 +1732,16 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_autonegotiate(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_autonegotiate failed: %d\n", ret);
+ nerr("ERROR: sam_autonegotiate failed: %d\n", ret);
return ret;
}
while (sam_linkup(priv) == 0);
- nllvdbg("Link detected \n");
+ ninfo("Link detected \n");
/* Enable normal MAC operation */
- nllvdbg("Enable normal operation\n");
+ ninfo("Enable normal operation\n");
/* Set and activate a timer process */
@@ -1775,7 +1775,7 @@ static int sam_ifdown(struct net_driver_s *dev)
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
irqstate_t flags;
- nlldbg("Taking the network down\n");
+ ninfo("Taking the network down\n");
/* Disable the EMAC interrupt */
@@ -1825,7 +1825,7 @@ static int sam_txavail(struct net_driver_s *dev)
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
irqstate_t flags;
- nllvdbg("ifup: %d\n", priv->ifup);
+ ninfo("ifup: %d\n", priv->ifup);
/* Disable interrupts because this function may be called from interrupt
* level processing.
@@ -1837,7 +1837,7 @@ static int sam_txavail(struct net_driver_s *dev)
if (priv->ifup)
{
- /* Poll uIP for new XMIT data */
+ /* Poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -2003,8 +2003,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
- nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@@ -2077,8 +2077,8 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
- nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@@ -2260,7 +2260,7 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, long arg)
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_VERBOSE)
+#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_INFO)
static void sam_phydump(struct sam_emac_s *priv)
{
uint32_t regval;
@@ -2273,21 +2273,21 @@ static void sam_phydump(struct sam_emac_s *priv)
sam_putreg(priv, SAM_EMAC_NCR, regval);
#ifdef CONFIG_SAMA5_EMAC_RMII
- nllvdbg("RMII Registers (Address %02x)\n", priv->phyaddr);
+ ninfo("RMII Registers (Address %02x)\n", priv->phyaddr);
#else /* defined(CONFIG_SAMA5_EMAC_MII) */
- nllvdbg("MII Registers (Address %02x)\n", priv->phyaddr);
+ ninfo("MII Registers (Address %02x)\n", priv->phyaddr);
#endif
sam_phyread(priv, priv->phyaddr, MII_MCR, &phyval);
- nllvdbg(" MCR: %04x\n", phyval);
+ ninfo(" MCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_MSR, &phyval);
- nllvdbg(" MSR: %04x\n", phyval);
+ ninfo(" MSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_ADVERTISE, &phyval);
- nllvdbg(" ADVERTISE: %04x\n", phyval);
+ ninfo(" ADVERTISE: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_LPA, &phyval);
- nllvdbg(" LPR: %04x\n", phyval);
+ ninfo(" LPR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, CONFIG_SAMA5_EMAC_PHYSR, &phyval);
- nllvdbg(" PHYSR: %04x\n", phyval);
+ ninfo(" PHYSR: %04x\n", phyval);
/* Disable management port */
@@ -2410,7 +2410,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int timeout;
int ret;
- nllvdbg(" sam_phyreset\n");
+ ninfo(" sam_phyreset\n");
/* Enable management port */
@@ -2423,7 +2423,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, MII_MCR_RESET);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywrite failed: %d\n", ret);
+ nerr("ERROR: sam_phywrite failed: %d\n", ret);
}
/* Wait for the PHY reset to complete */
@@ -2435,7 +2435,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int result = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (result < 0)
{
- nlldbg("ERROR: Failed to read the MCR register: %d\n", ret);
+ nerr("ERROR: Failed to read the MCR register: %d\n", ret);
ret = result;
}
else if ((mcr & MII_MCR_RESET) == 0)
@@ -2477,7 +2477,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
unsigned int offset;
int ret = -ESRCH;
- nllvdbg("Find a valid PHY address\n");
+ ninfo("Find a valid PHY address\n");
/* Enable management port */
@@ -2500,8 +2500,8 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
else
{
- nlldbg("ERROR: sam_phyread failed for PHY address %02x: %d\n",
- candidate, ret);
+ nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
+ candidate, ret);
for (offset = 0; offset < 32; offset++)
{
@@ -2522,10 +2522,10 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
if (ret == OK)
{
- nllvdbg(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
+ ninfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
*phyaddr = candidate;
sam_phyread(priv, candidate, CONFIG_SAMA5_EMAC_PHYSR, &phyval);
- nllvdbg(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
+ ninfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
}
/* Disable management port */
@@ -2566,7 +2566,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -2581,7 +2581,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -2621,7 +2621,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -2636,7 +2636,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -2680,32 +2680,32 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID1, &phyid1);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read PHYID1\n");
+ nerr("ERROR: Failed to read PHYID1\n");
goto errout;
}
- nllvdbg("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
+ ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID2, &phyid2);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read PHYID2\n");
+ nerr("ERROR: Failed to read PHYID2\n");
goto errout;
}
- nllvdbg("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
+ ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
if (phyid1 == MII_OUI_MSB &&
((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) == MII_OUI_LSB)
{
- nllvdbg(" Vendor Model Number: %04x\n",
- (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
- nllvdbg(" Model Revision Number: %04x\n",
- (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
+ ninfo(" Vendor Model Number: %04x\n",
+ (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
+ ninfo(" Model Revision Number: %04x\n",
+ (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
}
else
{
- nlldbg("ERROR: PHY not recognized\n");
+ nerr("ERROR: PHY not recognized\n");
}
/* Setup control register */
@@ -2713,7 +2713,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read MCR\n");
+ nerr("ERROR: Failed to read MCR\n");
goto errout;
}
@@ -2724,7 +2724,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to write MCR\n");
+ nerr("ERROR: Failed to write MCR\n");
goto errout;
}
@@ -2739,7 +2739,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_ADVERTISE, advertise);
if (ret < 0)
{
- nlldbg("ERROR: Failed to write ANAR\n");
+ nerr("ERROR: Failed to write ANAR\n");
goto errout;
}
@@ -2748,7 +2748,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read MCR\n");
+ nerr("ERROR: Failed to read MCR\n");
goto errout;
}
@@ -2756,7 +2756,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to write MCR\n");
+ nerr("ERROR: Failed to write MCR\n");
goto errout;
}
@@ -2768,11 +2768,11 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to write MCR\n");
+ nerr("ERROR: Failed to write MCR\n");
goto errout;
}
- nllvdbg(" MCR: %04x\n", mcr);
+ ninfo(" MCR: %04x\n", mcr);
/* Check AutoNegotiate complete */
@@ -2782,7 +2782,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read MSR\n");
+ nerr("ERROR: Failed to read MSR\n");
goto errout;
}
@@ -2792,7 +2792,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
{
/* Yes.. break out of the loop */
- nllvdbg("AutoNegotiate complete\n");
+ ninfo("AutoNegotiate complete\n");
break;
}
@@ -2800,7 +2800,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
if (++timeout >= PHY_RETRY_MAX)
{
- nlldbg("ERROR: TimeOut\n");
+ nerr("ERROR: TimeOut\n");
sam_phydump(priv);
ret = -ETIMEDOUT;
goto errout;
@@ -2812,7 +2812,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_LPA, &lpa);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read ANLPAR\n");
+ nerr("ERROR: Failed to read ANLPAR\n");
goto errout;
}
@@ -2902,13 +2902,13 @@ static bool sam_linkup(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read MSR: %d\n", ret);
+ nerr("ERROR: Failed to read MSR: %d\n", ret);
goto errout;
}
if ((msr & MII_MSR_LINKSTATUS) == 0)
{
- nlldbg("ERROR: MSR LinkStatus: %04x\n", msr);
+ nerr("ERROR: MSR LinkStatus: %04x\n", msr);
goto errout;
}
@@ -2917,7 +2917,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, CONFIG_SAMA5_EMAC_PHYSR, &physr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read PHYSR: %d\n", ret);
+ nerr("ERROR: Failed to read PHYSR: %d\n", ret);
goto errout;
}
@@ -2955,7 +2955,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
/* Start the EMAC transfers */
- nllvdbg("Link is up\n");
+ ninfo("Link is up\n");
linkup = true;
errout:
@@ -2996,7 +2996,7 @@ static int sam_phyinit(struct sam_emac_s *priv)
mck = BOARD_MCK_FREQUENCY;
if (mck > (160*1000*1000))
{
- ndbg("ERROR: Cannot realize PHY clock\n");
+ nerr("ERROR: Cannot realize PHY clock\n");
return -EINVAL;
}
else if (mck > (80*1000*1000))
@@ -3024,7 +3024,7 @@ static int sam_phyinit(struct sam_emac_s *priv)
ret = sam_phyfind(priv, &priv->phyaddr);
if (ret < 0)
{
- nlldbg("ERROR: sam_phyfind failed: %d\n", ret);
+ nerr("ERROR: sam_phyfind failed: %d\n", ret);
return ret;
}
@@ -3276,11 +3276,11 @@ static void sam_macaddress(struct sam_emac_s *priv)
struct net_driver_s *dev = &priv->dev;
uint32_t regval;
- nllvdbg("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- dev->d_ifname,
- dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
- dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
- dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
+ ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ dev->d_ifname,
+ dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+ dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+ dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
/* Set the MAC address */
@@ -3342,7 +3342,7 @@ static void sam_ipv6multicast(struct sam_emac_s *priv)
mac[4] = tmp16 & 0xff;
mac[5] = tmp16 >> 8;
- nvdbg("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
(void)sam_addmac(dev, mac);
@@ -3388,7 +3388,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
{
uint32_t regval;
- nllvdbg("Entry\n");
+ ninfo("Entry\n");
/* Enable clocking to the EMAC peripheral */
@@ -3501,7 +3501,7 @@ int sam_emac_initialize(void)
priv->txpoll = wd_create();
if (!priv->txpoll)
{
- ndbg("ERROR: Failed to create periodic poll timer\n");
+ nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout;
}
@@ -3509,7 +3509,7 @@ int sam_emac_initialize(void)
priv->txtimeout = wd_create(); /* Create TX timeout timer */
if (!priv->txtimeout)
{
- ndbg("ERROR: Failed to create periodic poll timer\n");
+ nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout_with_txpoll;
}
@@ -3523,7 +3523,7 @@ int sam_emac_initialize(void)
ret = sam_buffer_initialize(priv);
if (ret < 0)
{
- ndbg("ERROR: sam_buffer_initialize failed: %d\n", ret);
+ nerr("ERROR: sam_buffer_initialize failed: %d\n", ret);
goto errout_with_txtimeout;
}
@@ -3534,7 +3534,7 @@ int sam_emac_initialize(void)
ret = irq_attach(SAM_IRQ_EMAC, sam_emac_interrupt);
if (ret < 0)
{
- ndbg("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_EMAC);
+ nerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_EMAC);
goto errout_with_buffers;
}
@@ -3547,7 +3547,7 @@ int sam_emac_initialize(void)
ret = sam_ifdown(&priv->dev);
if (ret < 0)
{
- ndbg("ERROR: Failed to put the interface in the down state: %d\n", ret);
+ nerr("ERROR: Failed to put the interface in the down state: %d\n", ret);
goto errout_with_buffers;
}
@@ -3559,7 +3559,7 @@ int sam_emac_initialize(void)
return ret;
}
- ndbg("ERROR: netdev_register() failed: %d\n", ret);
+ nerr("ERROR: netdev_register() failed: %d\n", ret);
errout_with_buffers:
sam_buffer_free(priv);
diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c
index fccc2d51f035b440985fd94dd491cf5aa38095b2..9b64fbc5ab9e5557136b9877990667a91d63522f 100644
--- a/arch/arm/src/sama5/sam_emacb.c
+++ b/arch/arm/src/sama5/sam_emacb.c
@@ -58,7 +58,7 @@
#include
-#if defined(CONFIG_DEBUG) && defined(CONFIG_SAMA5_EMACB_DEBUG)
+#if defined(CONFIG_DEBUG_FEATURES) && defined(CONFIG_SAMA5_EMACB_DEBUG)
/* Force debug output (from this file only) */
# undef CONFIG_DEBUG_NET
@@ -295,7 +295,7 @@
* enabled.
*/
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_NET_INFO
# undef CONFIG_SAMA5_EMACB_REGDEBUG
#endif
@@ -421,9 +421,9 @@ struct sam_emac_s
struct work_s work; /* For deferring work to the work queue */
#endif
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
/* Constant and configured attributes of the EMAC */
@@ -459,7 +459,7 @@ struct sam_emac_s
****************************************************************************/
/* Register operations ******************************************************/
-#if defined(CONFIG_SAMA5_EMACB_REGDEBUG) && defined(CONFIG_DEBUG)
+#if defined(CONFIG_SAMA5_EMACB_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
static bool sam_checkreg(struct sam_emac_s *priv, bool wr,
uint32_t regval, uintptr_t address);
#endif
@@ -536,7 +536,7 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, long arg);
/* PHY Initialization */
-#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_VERBOSE)
+#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_INFO)
static void sam_phydump(struct sam_emac_s *priv);
#else
# define sam_phydump(priv)
@@ -820,7 +820,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", priv->ntimes);
+ ninfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@@ -853,7 +853,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uint16_t offset)
#ifdef CONFIG_SAMA5_EMACB_REGDEBUG
if (sam_checkreg(priv, false, regval, regaddr))
{
- lldbg("%08x->%08x\n", regaddr, regval);
+ ninfo("%08x->%08x\n", regaddr, regval);
}
#endif
@@ -877,7 +877,7 @@ static void sam_putreg(struct sam_emac_s *priv, uint16_t offset,
#ifdef CONFIG_SAMA5_EMACB_REGDEBUG
if (sam_checkreg(priv, true, regval, regaddr))
{
- lldbg("%08x<-%08x\n", regaddr, regval);
+ ninfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@@ -970,7 +970,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->txdesc = (struct emac_txdesc_s *)kmm_memalign(8, allocsize);
if (!priv->txdesc)
{
- nlldbg("ERROR: Failed to allocate TX descriptors\n");
+ nerr("ERROR: Failed to allocate TX descriptors\n");
return -ENOMEM;
}
@@ -980,7 +980,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->rxdesc = (struct emac_rxdesc_s *)kmm_memalign(8, allocsize);
if (!priv->rxdesc)
{
- nlldbg("ERROR: Failed to allocate RX descriptors\n");
+ nerr("ERROR: Failed to allocate RX descriptors\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -991,7 +991,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->txbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->txbuffer)
{
- nlldbg("ERROR: Failed to allocate TX buffer\n");
+ nerr("ERROR: Failed to allocate TX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -1000,7 +1000,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->rxbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->rxbuffer)
{
- nlldbg("ERROR: Failed to allocate RX buffer\n");
+ nerr("ERROR: Failed to allocate RX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -1088,14 +1088,14 @@ static int sam_transmit(struct sam_emac_s *priv)
uint32_t regval;
uint32_t status;
- nllvdbg("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
+ ninfo("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
/* Check parameter */
if (dev->d_len > EMAC_TX_UNITSIZE)
{
- nlldbg("ERROR: Packet too big: %d\n", dev->d_len);
+ nerr("ERROR: Packet too big: %d\n", dev->d_len);
return -EINVAL;
}
@@ -1107,7 +1107,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
- nlldbg("ERROR: No free TX descriptors\n");
+ nerr("ERROR: No free TX descriptors\n");
return -EBUSY;
}
@@ -1169,7 +1169,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
- nllvdbg("Disabling RX interrupts\n");
+ ninfo("Disabling RX interrupts\n");
sam_putreg(priv, SAM_EMAC_IDR_OFFSET, EMAC_INT_RCOMP);
}
@@ -1180,7 +1180,7 @@ static int sam_transmit(struct sam_emac_s *priv)
* Function: sam_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -1290,7 +1290,7 @@ static void sam_dopoll(struct sam_emac_s *priv)
if (sam_txfree(priv) > 0)
{
- /* If we have the descriptor, then poll uIP for new XMIT data. */
+ /* If we have the descriptor, then poll the network for new XMIT data. */
(void)devif_poll(dev, sam_txpoll);
}
@@ -1349,7 +1349,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
arch_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
- nllvdbg("rxndx: %d\n", rxndx);
+ ninfo("rxndx: %d\n", rxndx);
while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
{
@@ -1405,7 +1405,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
{
if (rxndx == priv->rxndx)
{
- nllvdbg("ERROR: No EOF (Invalid of buffers too small)\n");
+ nerr("ERROR: No EOF (Invalid of buffers too small)\n");
do
{
/* Give ownership back to the EMAC */
@@ -1460,7 +1460,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Frame size from the EMAC */
dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
- nllvdbg("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
+ ninfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
/* All data have been copied in the application frame buffer,
* release the RX descriptor
@@ -1491,11 +1491,11 @@ static int sam_recvframe(struct sam_emac_s *priv)
* all of the data.
*/
- nllvdbg("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
+ ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
if (pktlen < dev->d_len)
{
- nlldbg("ERROR: Buffer size %d; frame size %d\n",
- dev->d_len, pktlen);
+ nerr("ERROR: Buffer size %d; frame size %d\n",
+ dev->d_len, pktlen);
return -E2BIG;
}
@@ -1535,7 +1535,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* No packet was found */
priv->rxndx = rxndx;
- nllvdbg("rxndx: %d\n", priv->rxndx);
+ ninfo("rxndx: %d\n", priv->rxndx);
return -EAGAIN;
}
@@ -1569,13 +1569,13 @@ static void sam_receive(struct sam_emac_s *priv)
{
sam_dumppacket("Received packet", dev->d_buf, dev->d_len);
- /* Check if the packet is a valid size for the uIP buffer configuration
+ /* Check if the packet is a valid size for the network buffer configuration
* (this should not happen)
*/
if (dev->d_len > CONFIG_NET_ETH_MTU)
{
- nlldbg("DROPPED: Too big: %d\n", dev->d_len);
+ nwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
continue;
}
@@ -1590,7 +1590,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
- nllvdbg("IPv4 frame\n");
+ ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@@ -1630,7 +1630,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
- nllvdbg("Iv6 frame\n");
+ ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@@ -1667,7 +1667,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
- nllvdbg("ARP frame\n");
+ ninfo("ARP frame\n");
/* Handle ARP packet */
@@ -1685,7 +1685,7 @@ static void sam_receive(struct sam_emac_s *priv)
else
#endif
{
- nlldbg("DROPPED: Unknown type: %04x\n", BUF->type);
+ nwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
}
}
}
@@ -1797,7 +1797,7 @@ static void sam_txdone(struct sam_emac_s *priv)
sam_putreg(priv, SAM_EMAC_IER_OFFSET, EMAC_INT_RCOMP);
}
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -1836,7 +1836,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
imr = sam_getreg(priv, SAM_EMAC_IMR_OFFSET);
pending = isr & ~(imr | EMAC_INT_UNUSED);
- nllvdbg("isr: %08x pending: %08x\n", isr, pending);
+ ninfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
@@ -1862,7 +1862,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
clrbits = EMAC_TSR_RLE | sam_txinuse(priv);
sam_txreset(priv);
- nlldbg("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
+ nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
regval |= EMAC_NCR_TXEN;
@@ -1873,7 +1873,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((tsr & EMAC_TSR_COL) != 0)
{
- nlldbg("ERROR: Collision occurred TSR: %08x\n", tsr);
+ nerr("ERROR: Collision occurred TSR: %08x\n", tsr);
clrbits |= EMAC_TSR_COL;
}
@@ -1881,7 +1881,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((tsr & EMAC_TSR_TFC) != 0)
{
- nlldbg("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
+ nerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
clrbits |= EMAC_TSR_TFC;
}
@@ -1896,7 +1896,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((tsr & EMAC_TSR_UND) != 0)
{
- nlldbg("ERROR: Transmit Underrun TSR: %08x\n", tsr);
+ nerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
clrbits |= EMAC_TSR_UND;
}
@@ -1933,7 +1933,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((rsr & EMAC_RSR_RXOVR) != 0)
{
- nlldbg("ERROR: Receiver overrun RSR: %08x\n", rsr);
+ nerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_RXOVR;
}
@@ -1950,7 +1950,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((rsr & EMAC_RSR_BNA) != 0)
{
- nlldbg("ERROR: Buffer not available RSR: %08x\n", rsr);
+ nerr("ERROR: Buffer not available RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_BNA;
}
@@ -1972,7 +1972,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((pending & EMAC_INT_PFNZ) != 0)
{
- nlldbg("Pause frame received\n");
+ nwarn("WARNING: Pause frame received\n");
}
/* Check for Pause Time Zero (PTZ)
@@ -1982,7 +1982,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((pending & EMAC_INT_PTZ) != 0)
{
- nlldbg("Pause TO!\n");
+ nwarn("WARNING: Pause TO!\n");
}
#endif
}
@@ -2147,14 +2147,14 @@ static int sam_emac1_interrupt(int irq, void *context)
static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv)
{
- nlldbg("Timeout!\n");
+ nerr("ERROR: Timeout!\n");
/* Reset the hardware. Just take the interface down, then back up again. */
sam_ifdown(&priv->dev);
sam_ifup(&priv->dev);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -2264,7 +2264,7 @@ static inline void sam_poll_process(FAR struct sam_emac_s *priv)
if (sam_txfree(priv) > 0)
{
- /* Update TCP timing states and poll uIP for new XMIT data. */
+ /* Update TCP timing states and poll the network for new XMIT data. */
(void)devif_timer(dev, sam_txpoll);
}
@@ -2377,20 +2377,20 @@ static int sam_ifup(struct net_driver_s *dev)
int ret;
#ifdef CONFIG_NET_IPv4
- ndbg("Bringing up: %d.%d.%d.%d\n",
- dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
- (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+ ninfo("Bringing up: %d.%d.%d.%d\n",
+ dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+ (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
#endif
#ifdef CONFIG_NET_IPv6
- ndbg("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n",
- dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2],
- dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5],
- dev->d_ipv6addr[6], dev->d_ipv6addr[7]);
+ ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n",
+ dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2],
+ dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5],
+ dev->d_ipv6addr[6], dev->d_ipv6addr[7]);
#endif
/* Configure the EMAC interface for normal operation. */
- nllvdbg("Initialize the EMAC\n");
+ ninfo("Initialize the EMAC\n");
sam_emac_configure(priv);
/* Set the MAC address (should have been configured while we were down) */
@@ -2408,7 +2408,7 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_phyinit(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phyinit failed: %d\n", ret);
+ nerr("ERROR: sam_phyinit failed: %d\n", ret);
return ret;
}
@@ -2417,16 +2417,16 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_autonegotiate(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_autonegotiate failed: %d\n", ret);
+ nerr("ERROR: sam_autonegotiate failed: %d\n", ret);
return ret;
}
while (sam_linkup(priv) == 0);
- nllvdbg("Link detected \n");
+ ninfo("Link detected \n");
/* Enable normal MAC operation */
- nllvdbg("Enable normal operation\n");
+ ninfo("Enable normal operation\n");
/* Set and activate a timer process */
@@ -2460,7 +2460,7 @@ static int sam_ifdown(struct net_driver_s *dev)
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
irqstate_t flags;
- nlldbg("Taking the network down\n");
+ ninfo("Taking the network down\n");
/* Disable the EMAC interrupt */
@@ -2505,13 +2505,13 @@ static int sam_ifdown(struct net_driver_s *dev)
static inline void sam_txavail_process(FAR struct sam_emac_s *priv)
{
- nllvdbg("ifup: %d\n", priv->ifup);
+ ninfo("ifup: %d\n", priv->ifup);
/* Ignore the notification if the interface is not yet up */
if (priv->ifup)
{
- /* Poll uIP for new XMIT data */
+ /* Poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -2758,8 +2758,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int ndx;
unsigned int bit;
- nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@@ -2831,8 +2831,8 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int ndx;
unsigned int bit;
- nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@@ -3014,7 +3014,7 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, long arg)
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_VERBOSE)
+#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_INFO)
static void sam_phydump(struct sam_emac_s *priv)
{
uint32_t regval;
@@ -3026,19 +3026,19 @@ static void sam_phydump(struct sam_emac_s *priv)
regval |= EMAC_NCR_MPE;
sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
- nllvdbg("%s Registers (Address %02x)\n",
- priv->attr->rmii ? "RMII" : "MII", priv->phyaddr);
+ ninfo("%s Registers (Address %02x)\n",
+ priv->attr->rmii ? "RMII" : "MII", priv->phyaddr);
sam_phyread(priv, priv->phyaddr, MII_MCR, &phyval);
- nllvdbg(" MCR: %04x\n", phyval);
+ ninfo(" MCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_MSR, &phyval);
- nllvdbg(" MSR: %04x\n", phyval);
+ ninfo(" MSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_ADVERTISE, &phyval);
- nllvdbg(" ADVERTISE: %04x\n", phyval);
+ ninfo(" ADVERTISE: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_LPA, &phyval);
- nllvdbg(" LPR: %04x\n", phyval);
+ ninfo(" LPR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, priv->attr->physr, &phyval);
- nllvdbg(" PHYSR: %04x\n", phyval);
+ ninfo(" PHYSR: %04x\n", phyval);
/* Disable management port */
@@ -3198,7 +3198,7 @@ static int sam_phyintenable(struct sam_emac_s *priv)
else
#endif
{
- ndbg("ERROR: Unsupported PHY type: %d\n", priv->phytype);
+ nerr("ERROR: Unsupported PHY type: %d\n", priv->phytype);
ret = -ENOSYS;
}
@@ -3262,7 +3262,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int timeout;
int ret;
- nllvdbg(" sam_phyreset\n");
+ ninfo(" sam_phyreset\n");
/* Enable management port */
@@ -3275,7 +3275,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, MII_MCR_RESET);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywrite failed: %d\n", ret);
+ nerr("ERROR: sam_phywrite failed: %d\n", ret);
}
/* Wait for the PHY reset to complete */
@@ -3287,7 +3287,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int result = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (result < 0)
{
- nlldbg("ERROR: Failed to read the MCR register: %d\n", ret);
+ nerr("ERROR: Failed to read the MCR register: %d\n", ret);
ret = result;
}
else if ((mcr & MII_MCR_RESET) == 0)
@@ -3329,7 +3329,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
unsigned int offset;
int ret = -ESRCH;
- nllvdbg("Find a valid PHY address\n");
+ ninfo("Find a valid PHY address\n");
/* Enable management port */
@@ -3352,8 +3352,8 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
else
{
- nlldbg("ERROR: sam_phyread failed for PHY address %02x: %d\n",
- candidate, ret);
+ nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
+ candidate, ret);
for (offset = 0; offset < 32; offset++)
{
@@ -3374,10 +3374,10 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
if (ret == OK)
{
- nllvdbg(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
+ ninfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
*phyaddr = candidate;
sam_phyread(priv, candidate, priv->attr->physr, &phyval);
- nllvdbg(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
+ ninfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
}
/* Disable management port */
@@ -3418,7 +3418,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -3443,7 +3443,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -3483,7 +3483,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -3508,7 +3508,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -3552,33 +3552,33 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID1, &phyid1);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read PHYID1\n");
+ nerr("ERROR: Failed to read PHYID1\n");
goto errout;
}
- nllvdbg("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
+ ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID2, &phyid2);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read PHYID2\n");
+ nerr("ERROR: Failed to read PHYID2\n");
goto errout;
}
- nllvdbg("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
+ ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
if (phyid1 == priv->attr->msoui &&
((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) ==
(uint16_t)priv->attr->lsoui)
{
- nllvdbg(" Vendor Model Number: %04x\n",
- (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
- nllvdbg(" Model Revision Number: %04x\n",
- (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
+ ninfo(" Vendor Model Number: %04x\n",
+ (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
+ ninfo(" Model Revision Number: %04x\n",
+ (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
}
else
{
- nlldbg("ERROR: PHY not recognized\n");
+ nerr("ERROR: PHY not recognized\n");
}
/* Setup control register */
@@ -3586,7 +3586,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read MCR\n");
+ nerr("ERROR: Failed to read MCR\n");
goto errout;
}
@@ -3597,7 +3597,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to write MCR\n");
+ nerr("ERROR: Failed to write MCR\n");
goto errout;
}
@@ -3612,7 +3612,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_ADVERTISE, advertise);
if (ret < 0)
{
- nlldbg("ERROR: Failed to write ANAR\n");
+ nerr("ERROR: Failed to write ANAR\n");
goto errout;
}
@@ -3621,7 +3621,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read MCR\n");
+ nerr("ERROR: Failed to read MCR\n");
goto errout;
}
@@ -3629,7 +3629,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to write MCR\n");
+ nerr("ERROR: Failed to write MCR\n");
goto errout;
}
@@ -3641,11 +3641,11 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to write MCR\n");
+ nerr("ERROR: Failed to write MCR\n");
goto errout;
}
- nllvdbg(" MCR: %04x\n", mcr);
+ ninfo(" MCR: %04x\n", mcr);
/* Check AutoNegotiate complete */
@@ -3655,7 +3655,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read MSR\n");
+ nerr("ERROR: Failed to read MSR\n");
goto errout;
}
@@ -3665,7 +3665,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
{
/* Yes.. break out of the loop */
- nllvdbg("AutoNegotiate complete\n");
+ ninfo("AutoNegotiate complete\n");
break;
}
@@ -3673,7 +3673,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
if (++timeout >= PHY_RETRY_MAX)
{
- nlldbg("ERROR: TimeOut\n");
+ nerr("ERROR: TimeOut\n");
sam_phydump(priv);
ret = -ETIMEDOUT;
goto errout;
@@ -3685,7 +3685,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_LPA, &lpa);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read ANLPAR\n");
+ nerr("ERROR: Failed to read ANLPAR\n");
goto errout;
}
@@ -3775,13 +3775,13 @@ static bool sam_linkup(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read MSR: %d\n", ret);
+ nerr("ERROR: Failed to read MSR: %d\n", ret);
goto errout;
}
if ((msr & MII_MSR_LINKSTATUS) == 0)
{
- nlldbg("ERROR: MSR LinkStatus: %04x\n", msr);
+ nerr("ERROR: MSR LinkStatus: %04x\n", msr);
goto errout;
}
@@ -3790,7 +3790,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, priv->attr->physr, &physr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read PHYSR: %d\n", ret);
+ nerr("ERROR: Failed to read PHYSR: %d\n", ret);
goto errout;
}
@@ -3828,7 +3828,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
/* Start the EMAC transfers */
- nllvdbg("Link is up\n");
+ ninfo("Link is up\n");
linkup = true;
errout:
@@ -3869,7 +3869,7 @@ static int sam_phyinit(struct sam_emac_s *priv)
mck = BOARD_MCK_FREQUENCY;
if (mck > (160*1000*1000))
{
- ndbg("ERROR: Cannot realize PHY clock\n");
+ nerr("ERROR: Cannot realize PHY clock\n");
return -EINVAL;
}
else if (mck > (80*1000*1000))
@@ -3897,7 +3897,7 @@ static int sam_phyinit(struct sam_emac_s *priv)
ret = sam_phyfind(priv, &priv->phyaddr);
if (ret < 0)
{
- nlldbg("ERROR: sam_phyfind failed: %d\n", ret);
+ nerr("ERROR: sam_phyfind failed: %d\n", ret);
return ret;
}
@@ -4012,7 +4012,7 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv)
else
#endif
{
- nvdbg("ERROR: emac=%d\n", priv->attr->emac);
+ nerr("ERROR: emac=%d\n", priv->attr->emac);
}
}
@@ -4311,11 +4311,11 @@ static void sam_macaddress(struct sam_emac_s *priv)
struct net_driver_s *dev = &priv->dev;
uint32_t regval;
- nllvdbg("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- dev->d_ifname,
- dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
- dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
- dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
+ ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ dev->d_ifname,
+ dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+ dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+ dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
/* Set the MAC address */
@@ -4377,7 +4377,7 @@ static void sam_ipv6multicast(struct sam_emac_s *priv)
mac[4] = tmp16 & 0xff;
mac[5] = tmp16 >> 8;
- nvdbg("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
(void)sam_addmac(dev, mac);
@@ -4423,7 +4423,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
{
uint32_t regval;
- nllvdbg("Entry\n");
+ ninfo("Entry\n");
/* Enable clocking to the EMAC peripheral */
@@ -4545,7 +4545,7 @@ int sam_emac_initialize(int intf)
else
#endif
{
- ndbg("ERROR: Interface %d not supported\n", intf);
+ nerr("ERROR: Interface %d not supported\n", intf);
return -EINVAL;
}
@@ -4574,7 +4574,7 @@ int sam_emac_initialize(int intf)
priv->txpoll = wd_create();
if (!priv->txpoll)
{
- ndbg("ERROR: Failed to create periodic poll timer\n");
+ nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout;
}
@@ -4582,7 +4582,7 @@ int sam_emac_initialize(int intf)
priv->txtimeout = wd_create(); /* Create TX timeout timer */
if (!priv->txtimeout)
{
- ndbg("ERROR: Failed to create periodic poll timer\n");
+ nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout_with_txpoll;
}
@@ -4596,7 +4596,7 @@ int sam_emac_initialize(int intf)
ret = sam_buffer_initialize(priv);
if (ret < 0)
{
- ndbg("ERROR: sam_buffer_initialize failed: %d\n", ret);
+ nerr("ERROR: sam_buffer_initialize failed: %d\n", ret);
goto errout_with_txtimeout;
}
@@ -4607,7 +4607,7 @@ int sam_emac_initialize(int intf)
ret = irq_attach(priv->attr->irq, priv->attr->handler);
if (ret < 0)
{
- ndbg("ERROR: Failed to attach the handler to the IRQ%d\n", priv->attr->irq);
+ nerr("ERROR: Failed to attach the handler to the IRQ%d\n", priv->attr->irq);
goto errout_with_buffers;
}
@@ -4620,7 +4620,7 @@ int sam_emac_initialize(int intf)
ret = sam_ifdown(&priv->dev);
if (ret < 0)
{
- ndbg("ERROR: Failed to put the interface in the down state: %d\n", ret);
+ nerr("ERROR: Failed to put the interface in the down state: %d\n", ret);
goto errout_with_buffers;
}
@@ -4632,7 +4632,7 @@ int sam_emac_initialize(int intf)
return ret;
}
- ndbg("ERROR: netdev_register() failed: %d\n", ret);
+ nerr("ERROR: netdev_register() failed: %d\n", ret);
errout_with_buffers:
sam_buffer_free(priv);
diff --git a/arch/arm/src/sama5/sam_ethernet.c b/arch/arm/src/sama5/sam_ethernet.c
index 409db45535d2c4867b6fbea900d5e82f64ea1d1c..206af9fc6724e29217516bb54d12c4d3ce0a0f73 100644
--- a/arch/arm/src/sama5/sam_ethernet.c
+++ b/arch/arm/src/sama5/sam_ethernet.c
@@ -88,7 +88,7 @@ static inline void up_gmac_initialize(void)
ret = sam_gmac_initialize();
if (ret < 0)
{
- nlldbg("ERROR: sam_gmac_initialize failed: %d\n", ret);
+ nerr("ERROR: sam_gmac_initialize failed: %d\n", ret);
}
}
#else
@@ -119,7 +119,7 @@ static inline void up_emac_initialize(void)
ret = sam_emac_initialize();
if (ret < 0)
{
- nlldbg("ERROR: up_emac_initialize failed: %d\n", ret);
+ nerr("ERROR: up_emac_initialize failed: %d\n", ret);
}
}
#elif defined(CONFIG_SAMA5_EMACB)
@@ -133,7 +133,7 @@ static inline void up_emac_initialize(void)
ret = sam_emac_initialize(EMAC0_INTF);
if (ret < 0)
{
- nlldbg("ERROR: up_emac_initialize(EMAC0) failed: %d\n", ret);
+ nerr("ERROR: up_emac_initialize(EMAC0) failed: %d\n", ret);
}
#endif
@@ -143,7 +143,7 @@ static inline void up_emac_initialize(void)
ret = sam_emac_initialize(EMAC1_INTF);
if (ret < 0)
{
- nlldbg("ERROR: up_emac_initialize(EMAC1) failed: %d\n", ret);
+ nerr("ERROR: up_emac_initialize(EMAC1) failed: %d\n", ret);
}
#endif
}
diff --git a/arch/arm/src/sama5/sam_freerun.c b/arch/arm/src/sama5/sam_freerun.c
index 18d2556bbf5d07e8c27833ac9f6af1c4fa1064da..8870988ce608e5d6997378a99ba7e71e06253761 100644
--- a/arch/arm/src/sama5/sam_freerun.c
+++ b/arch/arm/src/sama5/sam_freerun.c
@@ -138,7 +138,7 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan,
uint32_t cmr;
int ret;
- tcvdbg("chan=%d resolution=%d usec\n", chan, resolution);
+ tmrinfo("chan=%d resolution=%d usec\n", chan, resolution);
DEBUGASSERT(freerun && resolution > 0);
/* Get the TC frequency the corresponds to the requested resolution */
@@ -150,13 +150,13 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan,
ret = sam_tc_divisor(frequency, &divisor, &cmr);
if (ret < 0)
{
- tcdbg("ERROR: sam_tc_divisor failed: %d\n", ret);
+ tmrerr("ERROR: sam_tc_divisor failed: %d\n", ret);
return ret;
}
- tcvdbg("frequency=%lu, divisor=%u, cmr=%08lx\n",
- (unsigned long)frequency, (unsigned long)divisor,
- (unsigned long)cmr);
+ tmrinfo("frequency=%lu, divisor=%u, cmr=%08lx\n",
+ (unsigned long)frequency, (unsigned long)divisor,
+ (unsigned long)cmr);
/* Allocate the timer/counter and select its mode of operation
*
@@ -189,7 +189,7 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan,
freerun->tch = sam_tc_allocate(chan, cmr);
if (!freerun->tch)
{
- tcdbg("ERROR: Failed to allocate timer channel %d\n", chan);
+ tmrerr("ERROR: Failed to allocate timer channel %d\n", chan);
return -EBUSY;
}
@@ -274,9 +274,9 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts)
leave_critical_section(flags);
- tcvdbg("counter=%lu (%lu) overflow=%lu, sr=%08lx\n",
- (unsigned long)counter, (unsigned long)verify,
- (unsigned long)overflow, (unsigned long)sr);
+ tmrinfo("counter=%lu (%lu) overflow=%lu, sr=%08lx\n",
+ (unsigned long)counter, (unsigned long)verify,
+ (unsigned long)overflow, (unsigned long)sr);
/* Convert the whole thing to units of microseconds.
*
@@ -294,7 +294,7 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts)
ts->tv_sec = sec;
ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC;
- tcvdbg("usec=%llu ts=(%lu, %lu)\n",
+ tmrinfo("usec=%llu ts=(%lu, %lu)\n",
usec, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
return OK;
diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c
index 8426e7dcb3b36929fd8d5e45f285c6e556f8add7..75a383655400cc01354c81948b7d2a0b45434969 100644
--- a/arch/arm/src/sama5/sam_gmac.c
+++ b/arch/arm/src/sama5/sam_gmac.c
@@ -149,7 +149,7 @@
* enabled.
*/
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_NET_INFO
# undef CONFIG_SAMA5_GMAC_REGDEBUG
#endif
@@ -193,9 +193,9 @@ struct sam_gmac_s
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
/* Used to track transmit and receive descriptors */
@@ -260,7 +260,7 @@ static uint8_t g_rxbuffer[CONFIG_SAMA5_GMAC_NRXBUFFERS * GMAC_RX_UNITSIZE]
****************************************************************************/
/* Register operations ******************************************************/
-#if defined(CONFIG_SAMA5_GMAC_REGDEBUG) && defined(CONFIG_DEBUG)
+#if defined(CONFIG_SAMA5_GMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
static bool sam_checkreg(struct sam_gmac_s *priv, bool wr,
uint32_t regval, uintptr_t address);
static uint32_t sam_getreg(struct sam_gmac_s *priv, uintptr_t addr);
@@ -315,7 +315,7 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, long arg);
/* PHY Initialization */
-#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_VERBOSE)
+#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_INFO)
static void sam_phydump(struct sam_gmac_s *priv);
#else
# define sam_phydump(priv)
@@ -392,7 +392,7 @@ static bool sam_checkreg(struct sam_gmac_s *priv, bool wr, uint32_t regval,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", priv->ntimes);
+ ninfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@@ -424,7 +424,7 @@ static uint32_t sam_getreg(struct sam_gmac_s *priv, uintptr_t address)
if (sam_checkreg(priv, false, regval, address))
{
- lldbg("%08x->%08x\n", address, regval);
+ ninfo("%08x->%08x\n", address, regval);
}
return regval;
@@ -445,7 +445,7 @@ static void sam_putreg(struct sam_gmac_s *priv, uintptr_t address,
{
if (sam_checkreg(priv, true, regval, address))
{
- lldbg("%08x<-%08x\n", address, regval);
+ ninfo("%08x<-%08x\n", address, regval);
}
putreg32(regval, address);
@@ -538,7 +538,7 @@ static int sam_buffer_initialize(struct sam_gmac_s *priv)
priv->txdesc = (struct gmac_txdesc_s *)kmm_memalign(8, allocsize);
if (!priv->txdesc)
{
- nlldbg("ERROR: Failed to allocate TX descriptors\n");
+ nerr("ERROR: Failed to allocate TX descriptors\n");
return -ENOMEM;
}
@@ -548,7 +548,7 @@ static int sam_buffer_initialize(struct sam_gmac_s *priv)
priv->rxdesc = (struct gmac_rxdesc_s *)kmm_memalign(8, allocsize);
if (!priv->rxdesc)
{
- nlldbg("ERROR: Failed to allocate RX descriptors\n");
+ nerr("ERROR: Failed to allocate RX descriptors\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -559,7 +559,7 @@ static int sam_buffer_initialize(struct sam_gmac_s *priv)
priv->txbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->txbuffer)
{
- nlldbg("ERROR: Failed to allocate TX buffer\n");
+ nerr("ERROR: Failed to allocate TX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -568,7 +568,7 @@ static int sam_buffer_initialize(struct sam_gmac_s *priv)
priv->rxbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->rxbuffer)
{
- nlldbg("ERROR: Failed to allocate RX buffer\n");
+ nerr("ERROR: Failed to allocate RX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -656,15 +656,15 @@ static int sam_transmit(struct sam_gmac_s *priv)
uint32_t regval;
uint32_t status;
- nllvdbg("d_len: %d txhead: %d txtail: %d\n",
- dev->d_len, priv->txhead, priv->txtail);
+ ninfo("d_len: %d txhead: %d txtail: %d\n",
+ dev->d_len, priv->txhead, priv->txtail);
sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
/* Check parameter */
if (dev->d_len > GMAC_TX_UNITSIZE)
{
- nlldbg("ERROR: Packet too big: %d\n", dev->d_len);
+ nerr("ERROR: Packet too big: %d\n", dev->d_len);
return -EINVAL;
}
@@ -676,7 +676,7 @@ static int sam_transmit(struct sam_gmac_s *priv)
if (sam_txfree(priv) < 1)
{
- nlldbg("ERROR: No free TX descriptors\n");
+ nerr("ERROR: No free TX descriptors\n");
return -EBUSY;
}
@@ -738,7 +738,7 @@ static int sam_transmit(struct sam_gmac_s *priv)
if (sam_txfree(priv) < 1)
{
- nllvdbg("Disabling RX interrupts\n");
+ ninfo("Disabling RX interrupts\n");
sam_putreg(priv, SAM_GMAC_IDR, GMAC_INT_RCOMP);
}
@@ -749,7 +749,7 @@ static int sam_transmit(struct sam_gmac_s *priv)
* Function: sam_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -858,7 +858,7 @@ static void sam_dopoll(struct sam_gmac_s *priv)
if (sam_txfree(priv) > 0)
{
- /* If we have the descriptor, then poll uIP for new XMIT data. */
+ /* If we have the descriptor, then poll the network for new XMIT data. */
(void)devif_poll(dev, sam_txpoll);
}
@@ -918,7 +918,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
arch_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct gmac_rxdesc_s));
- nllvdbg("rxndx: %d\n", rxndx);
+ ninfo("rxndx: %d\n", rxndx);
while ((rxdesc->addr & GMACRXD_ADDR_OWNER) != 0)
{
@@ -974,7 +974,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
{
if (rxndx == priv->rxndx)
{
- nllvdbg("ERROR: No EOF (Invalid of buffers too small)\n");
+ nerr("ERROR: No EOF (Invalid of buffers too small)\n");
do
{
/* Give ownership back to the GMAC */
@@ -1029,7 +1029,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
/* Frame size from the GMAC */
dev->d_len = (rxdesc->status & GMACRXD_STA_FRLEN_MASK);
- nllvdbg("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
+ ninfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
/* All data have been copied in the application frame buffer,
* release the RX descriptor
@@ -1060,11 +1060,11 @@ static int sam_recvframe(struct sam_gmac_s *priv)
* all of the data.
*/
- nllvdbg("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
+ ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
if (pktlen < dev->d_len)
{
- nlldbg("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
+ nerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
return -E2BIG;
}
@@ -1102,7 +1102,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
/* No packet was found */
priv->rxndx = rxndx;
- nllvdbg("rxndx: %d\n", priv->rxndx);
+ ninfo("rxndx: %d\n", priv->rxndx);
return -EAGAIN;
}
@@ -1136,13 +1136,13 @@ static void sam_receive(struct sam_gmac_s *priv)
{
sam_dumppacket("Received packet", dev->d_buf, dev->d_len);
- /* Check if the packet is a valid size for the uIP buffer configuration
+ /* Check if the packet is a valid size for the network buffer configuration
* (this should not happen)
*/
if (dev->d_len > CONFIG_NET_ETH_MTU)
{
- nlldbg("DROPPED: Too big: %d\n", dev->d_len);
+ nwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
continue;
}
@@ -1157,7 +1157,7 @@ static void sam_receive(struct sam_gmac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
- nllvdbg("IPv4 frame\n");
+ ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@@ -1197,7 +1197,7 @@ static void sam_receive(struct sam_gmac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
- nllvdbg("Iv6 frame\n");
+ ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@@ -1234,7 +1234,7 @@ static void sam_receive(struct sam_gmac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
- nllvdbg("ARP frame\n");
+ ninfo("ARP frame\n");
/* Handle ARP packet */
@@ -1252,7 +1252,7 @@ static void sam_receive(struct sam_gmac_s *priv)
else
#endif
{
- nlldbg("DROPPED: Unknown type: %04x\n", BUF->type);
+ nwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
}
}
}
@@ -1338,7 +1338,7 @@ static void sam_txdone(struct sam_gmac_s *priv)
sam_putreg(priv, SAM_GMAC_IER, GMAC_INT_RCOMP);
}
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -1377,7 +1377,7 @@ static int sam_gmac_interrupt(int irq, void *context)
imr = sam_getreg(priv, SAM_GMAC_IMR);
pending = isr & ~(imr | GMAC_INT_UNUSED);
- nllvdbg("isr: %08x pending: %08x\n", isr, pending);
+ ninfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
@@ -1403,7 +1403,7 @@ static int sam_gmac_interrupt(int irq, void *context)
clrbits = GMAC_TSR_RLE | sam_txinuse(priv);
sam_txreset(priv);
- nlldbg("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
+ nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
regval = sam_getreg(priv, SAM_GMAC_NCR);
regval |= GMAC_NCR_TXEN;
@@ -1414,7 +1414,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((tsr & GMAC_TSR_COL) != 0)
{
- nlldbg("ERROR: Collision occurred TSR: %08x\n", tsr);
+ nerr("ERROR: Collision occurred TSR: %08x\n", tsr);
clrbits |= GMAC_TSR_COL;
}
@@ -1422,7 +1422,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((tsr & GMAC_TSR_TFC) != 0)
{
- nlldbg("ERROR: Buffers exhausted mid-frame TSR: %08x\n", tsr);
+ nerr("ERROR: Buffers exhausted mid-frame TSR: %08x\n", tsr);
clrbits |= GMAC_TSR_TFC;
}
@@ -1437,7 +1437,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((tsr & GMAC_TSR_UND) != 0)
{
- nlldbg("ERROR: Transmit Underrun TSR: %08x\n", tsr);
+ nerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
clrbits |= GMAC_TSR_UND;
}
@@ -1445,7 +1445,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((tsr & GMAC_TSR_HRESP) != 0)
{
- nlldbg("ERROR: HRESP not OK: %08x\n", tsr);
+ nerr("ERROR: HRESP not OK: %08x\n", tsr);
clrbits |= GMAC_TSR_HRESP;
}
@@ -1453,7 +1453,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((tsr & GMAC_TSR_LCO) != 0)
{
- nlldbg("ERROR: Late collision: %08x\n", tsr);
+ nerr("ERROR: Late collision: %08x\n", tsr);
clrbits |= GMAC_TSR_LCO;
}
@@ -1490,7 +1490,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((rsr & GMAC_RSR_RXOVR) != 0)
{
- nlldbg("ERROR: Receiver overrun RSR: %08x\n", rsr);
+ nerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
clrbits |= GMAC_RSR_RXOVR;
}
@@ -1507,7 +1507,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((rsr & GMAC_RSR_BNA) != 0)
{
- nlldbg("ERROR: Buffer not available RSR: %08x\n", rsr);
+ nerr("ERROR: Buffer not available RSR: %08x\n", rsr);
clrbits |= GMAC_RSR_BNA;
}
@@ -1515,7 +1515,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((rsr & GMAC_RSR_HNO) != 0)
{
- nlldbg("ERROR: HRESP not OK: %08x\n", rsr);
+ nerr("ERROR: HRESP not OK: %08x\n", rsr);
clrbits |= GMAC_RSR_HNO;
}
@@ -1536,7 +1536,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((pending & GMAC_INT_PFNZ) != 0)
{
- nlldbg("Pause frame received\n");
+ nwarn("WARNING: Pause frame received\n");
}
/* Check for Pause Time Zero (PTZ)
@@ -1546,7 +1546,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((pending & GMAC_INT_PTZ) != 0)
{
- nlldbg("Pause TO!\n");
+ nwarn("WARNING: Pause TO!\n");
}
#endif
@@ -1576,7 +1576,7 @@ static void sam_txtimeout(int argc, uint32_t arg, ...)
{
struct sam_gmac_s *priv = (struct sam_gmac_s *)arg;
- nlldbg("Timeout!\n");
+ nerr("ERROR: Timeout!\n");
/* Then reset the hardware. Just take the interface down, then back
* up again.
@@ -1585,7 +1585,7 @@ static void sam_txtimeout(int argc, uint32_t arg, ...)
sam_ifdown(&priv->dev);
sam_ifup(&priv->dev);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -1619,7 +1619,7 @@ static void sam_polltimer(int argc, uint32_t arg, ...)
if (sam_txfree(priv) > 0)
{
- /* Update TCP timing states and poll uIP for new XMIT data. */
+ /* Update TCP timing states and poll the network for new XMIT data. */
(void)devif_timer(dev, sam_txpoll);
}
@@ -1651,13 +1651,13 @@ static int sam_ifup(struct net_driver_s *dev)
struct sam_gmac_s *priv = (struct sam_gmac_s *)dev->d_private;
int ret;
- nlldbg("Bringing up: %d.%d.%d.%d\n",
- dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
- (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+ ninfo("Bringing up: %d.%d.%d.%d\n",
+ dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+ (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
/* Configure the GMAC interface for normal operation. */
- nllvdbg("Initialize the GMAC\n");
+ ninfo("Initialize the GMAC\n");
sam_gmac_configure(priv);
/* Set the MAC address (should have been configured while we were down) */
@@ -1675,7 +1675,7 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_phyinit(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phyinit failed: %d\n", ret);
+ nerr("ERROR: sam_phyinit failed: %d\n", ret);
return ret;
}
@@ -1685,7 +1685,7 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_autonegotiate(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_autonegotiate failed: %d\n", ret);
+ nerr("ERROR: sam_autonegotiate failed: %d\n", ret);
return ret;
}
#else
@@ -1696,7 +1696,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Enable normal MAC operation */
- nllvdbg("Enable normal operation\n");
+ ninfo("Enable normal operation\n");
/* Set and activate a timer process */
@@ -1730,7 +1730,7 @@ static int sam_ifdown(struct net_driver_s *dev)
struct sam_gmac_s *priv = (struct sam_gmac_s *)dev->d_private;
irqstate_t flags;
- nlldbg("Taking the network down\n");
+ ninfo("Taking the network down\n");
/* Disable the GMAC interrupt */
@@ -1780,7 +1780,7 @@ static int sam_txavail(struct net_driver_s *dev)
struct sam_gmac_s *priv = (struct sam_gmac_s *)dev->d_private;
irqstate_t flags;
- nllvdbg("ifup: %d\n", priv->ifup);
+ ninfo("ifup: %d\n", priv->ifup);
/* Disable interrupts because this function may be called from interrupt
* level processing.
@@ -1792,7 +1792,7 @@ static int sam_txavail(struct net_driver_s *dev)
if (priv->ifup)
{
- /* Poll uIP for new XMIT data */
+ /* Poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -1958,8 +1958,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
- nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@@ -2032,8 +2032,8 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
- nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@@ -2211,7 +2211,7 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, long arg)
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_VERBOSE)
+#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_INFO)
static void sam_phydump(struct sam_gmac_s *priv)
{
uint16_t phyval;
@@ -2220,21 +2220,21 @@ static void sam_phydump(struct sam_gmac_s *priv)
sam_enablemdio(priv);
- nllvdbg("GMII Registers (Address %02x)\n", priv->phyaddr);
+ ninfo("GMII Registers (Address %02x)\n", priv->phyaddr);
sam_phyread(priv, priv->phyaddr, GMII_MCR, &phyval);
- nllvdbg(" MCR: %04x\n", phyval);
+ ninfo(" MCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_MSR, &phyval);
- nllvdbg(" MSR: %04x\n", phyval);
+ ninfo(" MSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_ADVERTISE, &phyval);
- nllvdbg(" ADVERTISE: %04x\n", phyval);
+ ninfo(" ADVERTISE: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_LPA, &phyval);
- nllvdbg(" LPR: %04x\n", phyval);
+ ninfo(" LPR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_1000BTCR, &phyval);
- nllvdbg(" 1000BTCR: %04x\n", phyval);
+ ninfo(" 1000BTCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_1000BTSR, &phyval);
- nllvdbg(" 1000BTSR: %04x\n", phyval);
+ ninfo(" 1000BTSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_ESTATUS, &phyval);
- nllvdbg(" ESTATUS: %04x\n", phyval);
+ ninfo(" ESTATUS: %04x\n", phyval);
/* Disable management port */
@@ -2418,7 +2418,7 @@ static int sam_phyreset(struct sam_gmac_s *priv)
int timeout;
int ret;
- nllvdbg(" sam_phyreset\n");
+ ninfo(" sam_phyreset\n");
/* Enable management port */
@@ -2429,7 +2429,7 @@ static int sam_phyreset(struct sam_gmac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, GMII_MCR, GMII_MCR_RESET);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywrite failed: %d\n", ret);
+ nerr("ERROR: sam_phywrite failed: %d\n", ret);
}
/* Wait for the PHY reset to complete */
@@ -2441,7 +2441,7 @@ static int sam_phyreset(struct sam_gmac_s *priv)
int result = sam_phyread(priv, priv->phyaddr, GMII_MCR, &mcr);
if (result < 0)
{
- nlldbg("ERROR: Failed to read the MCR register: %d\n", ret);
+ nerr("ERROR: Failed to read the MCR register: %d\n", ret);
ret = result;
}
else if ((mcr & GMII_MCR_RESET) == 0)
@@ -2480,7 +2480,7 @@ static int sam_phyfind(struct sam_gmac_s *priv, uint8_t *phyaddr)
unsigned int offset;
int ret = -ESRCH;
- nllvdbg("Find a valid PHY address\n");
+ ninfo("Find a valid PHY address\n");
/* Enable management port */
@@ -2501,8 +2501,8 @@ static int sam_phyfind(struct sam_gmac_s *priv, uint8_t *phyaddr)
else
{
- nlldbg("ERROR: sam_phyread failed for PHY address %02x: %d\n",
- candidate, ret);
+ nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
+ candidate, ret);
for (offset = 0; offset < 32; offset++)
{
@@ -2523,7 +2523,7 @@ static int sam_phyfind(struct sam_gmac_s *priv, uint8_t *phyaddr)
if (ret == OK)
{
- nllvdbg(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
+ ninfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
*phyaddr = candidate;
}
@@ -2563,7 +2563,7 @@ static int sam_phyread(struct sam_gmac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -2578,7 +2578,7 @@ static int sam_phyread(struct sam_gmac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -2618,7 +2618,7 @@ static int sam_phywrite(struct sam_gmac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -2633,7 +2633,7 @@ static int sam_phywrite(struct sam_gmac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -2679,35 +2679,35 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, GMII_PHYID1, &phyid1);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read PHYID1 register\n");
+ nerr("ERROR: Failed to read PHYID1 register\n");
goto errout;
}
- nllvdbg("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
+ ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
/* Read the LS bits of the OUI from Pthe PHYID2 register */
ret = sam_phyread(priv, priv->phyaddr, GMII_PHYID2, &phyid2);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read PHYID2 register\n");
+ nerr("ERROR: Failed to read PHYID2 register\n");
goto errout;
}
- nllvdbg("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
+ ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
if (phyid1 == GMII_OUI_MSB &&
(phyid2 & GMII_PHYID2_OUI_MASK) == GMII_OUI_LSB)
{
- nllvdbg(" Vendor Model Number: %04x\n",
- (phyid2 & GMII_PHYID2_MODEL_MASK) >> GMII_PHYID2_MODEL_SHIFT);
- nllvdbg(" Model Revision Number: %04x\n",
- (phyid2 & GMII_PHYID2_REV_MASK) >> GMII_PHYID2_REV_SHIFT);
+ ninfo(" Vendor Model Number: %04x\n",
+ (phyid2 & GMII_PHYID2_MODEL_MASK) >> GMII_PHYID2_MODEL_SHIFT);
+ ninfo(" Model Revision Number: %04x\n",
+ (phyid2 & GMII_PHYID2_REV_MASK) >> GMII_PHYID2_REV_SHIFT);
}
else
{
- nlldbg("ERROR: PHY not recognized: PHYID1=%04x PHYID2=%04x\n",
- phyid1, phyid2);
+ nerr("ERROR: PHY not recognized: PHYID1=%04x PHYID2=%04x\n",
+ phyid1, phyid2);
}
#ifdef SAMA5_GMAC_PHY_KSZ90x1
@@ -2735,7 +2735,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, GMII_ADVERTISE, advertise);
if (ret < 0)
{
- nlldbg("ERROR: Failed to write ADVERTISE register\n");
+ nerr("ERROR: Failed to write ADVERTISE register\n");
goto errout;
}
@@ -2746,7 +2746,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, GMII_1000BTCR, &btcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read 1000BTCR register: %d\n", ret);
+ nerr("ERROR: Failed to read 1000BTCR register: %d\n", ret);
goto errout;
}
@@ -2755,7 +2755,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, GMII_1000BTCR, btcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to write 1000BTCR register: %d\n", ret);
+ nerr("ERROR: Failed to write 1000BTCR register: %d\n", ret);
goto errout;
}
@@ -2764,7 +2764,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, GMII_MCR, &phyval);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read MCR register: %d\n", ret);
+ nerr("ERROR: Failed to read MCR register: %d\n", ret);
goto errout;
}
@@ -2773,11 +2773,11 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, GMII_MCR, phyval);
if (ret < 0)
{
- nlldbg("ERROR: Failed to write MCR register: %d\n", ret);
+ nerr("ERROR: Failed to write MCR register: %d\n", ret);
goto errout;
}
- nllvdbg(" MCR: 0x%X\n", phyval);
+ ninfo(" MCR: 0x%X\n", phyval);
/* Wait for autonegotion to complete */
@@ -2787,7 +2787,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, GMII_MSR, &phyval);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read MSR register: %d\n", ret);
+ nerr("ERROR: Failed to read MSR register: %d\n", ret);
goto errout;
}
@@ -2797,7 +2797,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
{
/* Yes.. break out of the loop */
- nllvdbg("AutoNegotiate complete\n");
+ ninfo("AutoNegotiate complete\n");
break;
}
@@ -2805,7 +2805,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
if (++timeout >= PHY_RETRY_MAX)
{
- nlldbg("ERROR: TimeOut\n");
+ nerr("ERROR: TimeOut\n");
sam_phydump(priv);
ret = -ETIMEDOUT;
goto errout;
@@ -2822,7 +2822,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, GMII_1000BTSR, &btsr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read 1000BTSR register: %d\n", ret);
+ nerr("ERROR: Failed to read 1000BTSR register: %d\n", ret);
goto errout;
}
@@ -2850,7 +2850,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, GMII_LPA, &lpa);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read LPA register: %d\n", ret);
+ nerr("ERROR: Failed to read LPA register: %d\n", ret);
goto errout;
}
@@ -2892,7 +2892,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
if (++timeout >= PHY_RETRY_MAX)
{
- nlldbg("ERROR: TimeOut\n");
+ nerr("ERROR: TimeOut\n");
sam_phydump(priv);
ret = -ETIMEDOUT;
goto errout;
@@ -3065,7 +3065,7 @@ static int sam_phyinit(struct sam_gmac_s *priv)
ret = sam_phyfind(priv, &priv->phyaddr);
if (ret < 0)
{
- nlldbg("ERROR: sam_phyfind failed: %d\n", ret);
+ nerr("ERROR: sam_phyfind failed: %d\n", ret);
return ret;
}
@@ -3324,11 +3324,11 @@ static void sam_macaddress(struct sam_gmac_s *priv)
struct net_driver_s *dev = &priv->dev;
uint32_t regval;
- nllvdbg("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- dev->d_ifname,
- dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
- dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
- dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
+ ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ dev->d_ifname,
+ dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+ dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+ dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
/* Set the MAC address */
@@ -3390,7 +3390,7 @@ static void sam_ipv6multicast(struct sam_gmac_s *priv)
mac[4] = tmp16 & 0xff;
mac[5] = tmp16 >> 8;
- nvdbg("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
(void)sam_addmac(dev, mac);
@@ -3436,7 +3436,7 @@ static int sam_gmac_configure(struct sam_gmac_s *priv)
{
uint32_t regval;
- nllvdbg("Entry\n");
+ ninfo("Entry\n");
/* Enable clocking to the GMAC peripheral */
@@ -3573,7 +3573,7 @@ int sam_gmac_initialize(void)
priv->txpoll = wd_create();
if (!priv->txpoll)
{
- nlldbg("ERROR: Failed to create periodic poll timer\n");
+ nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout;
}
@@ -3581,7 +3581,7 @@ int sam_gmac_initialize(void)
priv->txtimeout = wd_create(); /* Create TX timeout timer */
if (!priv->txtimeout)
{
- nlldbg("ERROR: Failed to create periodic poll timer\n");
+ nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout_with_txpoll;
}
@@ -3595,7 +3595,7 @@ int sam_gmac_initialize(void)
ret = sam_buffer_initialize(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_buffer_initialize failed: %d\n", ret);
+ nerr("ERROR: sam_buffer_initialize failed: %d\n", ret);
goto errout_with_txtimeout;
}
@@ -3606,7 +3606,7 @@ int sam_gmac_initialize(void)
ret = irq_attach(SAM_IRQ_GMAC, sam_gmac_interrupt);
if (ret < 0)
{
- nlldbg("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_GMAC);
+ nerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_GMAC);
goto errout_with_buffers;
}
@@ -3619,7 +3619,7 @@ int sam_gmac_initialize(void)
ret = sam_ifdown(&priv->dev);
if (ret < 0)
{
- nlldbg("ERROR: Failed to put the interface in the down state: %d\n", ret);
+ nerr("ERROR: Failed to put the interface in the down state: %d\n", ret);
goto errout_with_buffers;
}
@@ -3631,7 +3631,7 @@ int sam_gmac_initialize(void)
return ret;
}
- nlldbg("ERROR: netdev_register() failed: %d\n", ret);
+ nerr("ERROR: netdev_register() failed: %d\n", ret);
errout_with_buffers:
sam_buffer_free(priv);
diff --git a/arch/arm/src/sama5/sam_hsmci.c b/arch/arm/src/sama5/sam_hsmci.c
index 54a7e34d9a5cc1ea69bf190ad6d3f65f6dae6431..2b4eb8361a31665ca2aff3c186d90ae3275139f3 100644
--- a/arch/arm/src/sama5/sam_hsmci.c
+++ b/arch/arm/src/sama5/sam_hsmci.c
@@ -79,6 +79,10 @@
/* Configuration ************************************************************/
+#ifndef CONFIG_DEBUG_MEMCARD_INFO
+# undef CONFIG_SAMA5_HSMCI_REGDEBUG
+#endif
+
#if defined(ATSAMA5D3)
/* The SAMA5D3 has three HSMCI blocks: HSMCI0-2. HSMCI0 requires DMAC0
* support, HSMCI1-2 require DMAC1 support.
@@ -162,7 +166,7 @@
# error "This driver requires CONFIG_SDIO_BLOCKSETUP"
#endif
-#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_VERBOSE)
+#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_INFO)
# undef CONFIG_SAMA5_HSMCI_CMDDEBUG
# undef CONFIG_SAMA5_HSMCI_XFRDEBUG
#endif
@@ -725,7 +729,7 @@ static bool sam_checkreg(struct sam_dev_s *priv, bool wr, uint32_t value,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", priv->ntimes);
+ mcinfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@@ -758,7 +762,7 @@ static inline uint32_t sam_getreg(struct sam_dev_s *priv, unsigned int offset)
#ifdef CONFIG_SAMA5_HSMCI_REGDEBUG
if (sam_checkreg(priv, false, value, address))
{
- lldbg("%08x->%08x\n", address, value);
+ mcinfo("%08x->%08x\n", address, value);
}
#endif
@@ -781,7 +785,7 @@ static inline void sam_putreg(struct sam_dev_s *priv, uint32_t value,
#ifdef CONFIG_SAMA5_HSMCI_REGDEBUG
if (sam_checkreg(priv, true, value, address))
{
- lldbg("%08x<-%08x\n", address, value);
+ mcinfo("%08x<-%08x\n", address, value);
}
#endif
@@ -1003,23 +1007,23 @@ static void sam_hsmcisample(struct sam_dev_s *priv,
static void sam_hsmcidump(struct sam_dev_s *priv,
struct sam_hsmciregs_s *regs, const char *msg)
{
- fdbg("HSMCI Registers: %s\n", msg);
- fdbg(" MR[%08x]: %08x\n", priv->base + SAM_HSMCI_MR_OFFSET, regs->mr);
- fdbg(" DTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_DTOR_OFFSET, regs->dtor);
- fdbg(" SDCR[%08x]: %08x\n", priv->base + SAM_HSMCI_SDCR_OFFSET, regs->sdcr);
- fdbg(" ARGR[%08x]: %08x\n", priv->base + SAM_HSMCI_ARGR_OFFSET, regs->argr);
- fdbg(" BLKR[%08x]: %08x\n", priv->base + SAM_HSMCI_BLKR_OFFSET, regs->blkr);
- fdbg(" CSTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_CSTOR_OFFSET, regs->cstor);
- fdbg(" RSPR0[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR0_OFFSET, regs->rsp0);
- fdbg(" RSPR1[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR1_OFFSET, regs->rsp1);
- fdbg(" RSPR2[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR2_OFFSET, regs->rsp2);
- fdbg(" RSPR3[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR3_OFFSET, regs->rsp3);
- fdbg(" SR[%08x]: %08x\n", priv->base + SAM_HSMCI_SR_OFFSET, regs->sr);
- fdbg(" IMR[%08x]: %08x\n", priv->base + SAM_HSMCI_IMR_OFFSET, regs->imr);
- fdbg(" DMA[%08x]: %08x\n", priv->base + SAM_HSMCI_DMA_OFFSET, regs->dma);
- fdbg(" CFG[%08x]: %08x\n", priv->base + SAM_HSMCI_CFG_OFFSET, regs->cfg);
- fdbg(" WPMR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPMR_OFFSET, regs->wpmr);
- fdbg(" WPSR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPSR_OFFSET, regs->wpsr);
+ lcdinfo("HSMCI Registers: %s\n", msg);
+ lcdinfo(" MR[%08x]: %08x\n", priv->base + SAM_HSMCI_MR_OFFSET, regs->mr);
+ lcdinfo(" DTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_DTOR_OFFSET, regs->dtor);
+ lcdinfo(" SDCR[%08x]: %08x\n", priv->base + SAM_HSMCI_SDCR_OFFSET, regs->sdcr);
+ lcdinfo(" ARGR[%08x]: %08x\n", priv->base + SAM_HSMCI_ARGR_OFFSET, regs->argr);
+ lcdinfo(" BLKR[%08x]: %08x\n", priv->base + SAM_HSMCI_BLKR_OFFSET, regs->blkr);
+ lcdinfo(" CSTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_CSTOR_OFFSET, regs->cstor);
+ lcdinfo(" RSPR0[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR0_OFFSET, regs->rsp0);
+ lcdinfo(" RSPR1[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR1_OFFSET, regs->rsp1);
+ lcdinfo(" RSPR2[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR2_OFFSET, regs->rsp2);
+ lcdinfo(" RSPR3[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR3_OFFSET, regs->rsp3);
+ lcdinfo(" SR[%08x]: %08x\n", priv->base + SAM_HSMCI_SR_OFFSET, regs->sr);
+ lcdinfo(" IMR[%08x]: %08x\n", priv->base + SAM_HSMCI_IMR_OFFSET, regs->imr);
+ lcdinfo(" DMA[%08x]: %08x\n", priv->base + SAM_HSMCI_DMA_OFFSET, regs->dma);
+ lcdinfo(" CFG[%08x]: %08x\n", priv->base + SAM_HSMCI_CFG_OFFSET, regs->cfg);
+ lcdinfo(" WPMR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPMR_OFFSET, regs->wpmr);
+ lcdinfo(" WPSR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPSR_OFFSET, regs->wpsr);
}
#endif
@@ -1093,7 +1097,7 @@ static void sam_xfrdumpone(struct sam_dev_s *priv, int index,
}
else
{
- fdbg("%s: Not collected\n", msg);
+ lcdinfo("%s: Not collected\n", msg);
}
}
#endif
@@ -1237,7 +1241,7 @@ static void sam_dmacallback(DMA_HANDLE handle, void *arg, int result)
if (result < 0)
{
wkupevent = (result == -ETIMEDOUT ? SDIOWAIT_TIMEOUT : SDIOWAIT_ERROR);
- flldbg("ERROR: DMA failed: result=%d wkupevent=%04x\n", result, wkupevent);
+ mcerr("ERROR: DMA failed: result=%d wkupevent=%04x\n", result, wkupevent);
/* sam_endtransfer will terminate the transfer and wait up the waiting
* client in this case.
@@ -1337,7 +1341,7 @@ static void sam_eventtimeout(int argc, uint32_t arg)
/* Yes.. wake up any waiting threads */
sam_endwait(priv, SDIOWAIT_TIMEOUT);
- flldbg("ERROR: Timeout\n");
+ mcerr("ERROR: Timeout\n");
}
}
@@ -1537,7 +1541,7 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv)
{
/* Yes.. Was it some kind of timeout error? */
- flldbg("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
+ mcerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
if ((pending & HSMCI_DATA_TIMEOUT_ERRORS) != 0)
{
/* Yes.. Terminate with a timeout. */
@@ -1609,8 +1613,8 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv)
{
/* Yes.. Was the error some kind of timeout? */
- fllvdbg("ERROR: events: %08x SR: %08x\n",
- priv->cmdrmask, enabled);
+ mcerr("ERROR: events: %08x SR: %08x\n",
+ priv->cmdrmask, enabled);
if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
{
@@ -2090,7 +2094,7 @@ static int sam_sendcmd(FAR struct sdio_dev_s *dev,
/* Write the fully decorated command to CMDR */
- fvdbg("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
+ mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
sam_putreg(priv, regval, SAM_HSMCI_CMDR_OFFSET);
sam_cmdsample1(priv, SAMPLENDX_AFTER_CMDR);
return OK;
@@ -2253,7 +2257,7 @@ static int sam_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer,
{
/* Some fatal error has occurred */
- fdbg("ERROR: sr %08x\n", sr);
+ lcderr("ERROR: sr %08x\n", sr);
return -EIO;
}
else if ((sr & HSMCI_INT_TXRDY) != 0)
@@ -2388,7 +2392,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
{
/* Yes.. Was the error some kind of timeout? */
- fdbg("ERROR: cmd: %08x events: %08x SR: %08x\n",
+ lcderr("ERROR: cmd: %08x events: %08x SR: %08x\n",
cmd, priv->cmdrmask, sr);
if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
@@ -2418,8 +2422,8 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
}
else if (--timeout <= 0)
{
- fdbg("ERROR: Timeout cmd: %08x events: %08x SR: %08x\n",
- cmd, priv->cmdrmask, sr);
+ lcderr("ERROR: Timeout cmd: %08x events: %08x SR: %08x\n",
+ cmd, priv->cmdrmask, sr);
priv->wkupevent = SDIOWAIT_TIMEOUT;
return -ETIMEDOUT;
@@ -2490,10 +2494,10 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev,
* 0 1 End bit
*/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!rshort)
{
- fdbg("ERROR: rshort=NULL\n");
+ lcderr("ERROR: rshort=NULL\n");
ret = -EINVAL;
}
@@ -2505,7 +2509,7 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev,
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE &&
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE)
{
- fdbg("ERROR: Wrong response CMD=%08x\n", cmd);
+ lcderr("ERROR: Wrong response CMD=%08x\n", cmd);
ret = -EINVAL;
}
else
@@ -2550,12 +2554,12 @@ static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong
* 0 1 End bit
*/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
/* Check that R1 is the correct response to this command */
if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE)
{
- fdbg("ERROR: Wrong response CMD=%08x\n", cmd);
+ lcderr("ERROR: Wrong response CMD=%08x\n", cmd);
ret = -EINVAL;
}
else
@@ -2746,7 +2750,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev,
1, (uint32_t)priv);
if (ret != OK)
{
- fdbg("ERROR: wd_start failed: %d\n", ret);
+ lcderr("ERROR: wd_start failed: %d\n", ret);
}
}
@@ -2812,7 +2816,7 @@ static void sam_callbackenable(FAR struct sdio_dev_s *dev,
{
struct sam_dev_s *priv = (struct sam_dev_s *)dev;
- fvdbg("eventset: %02x\n", eventset);
+ mcinfo("eventset: %02x\n", eventset);
DEBUGASSERT(priv != NULL);
priv->cbevents = eventset;
@@ -2848,7 +2852,7 @@ static int sam_registercallback(FAR struct sdio_dev_s *dev,
/* Disable callbacks and register this callback and is argument */
- fvdbg("Register %p(%p)\n", callback, arg);
+ mcinfo("Register %p(%p)\n", callback, arg);
DEBUGASSERT(priv != NULL);
priv->cbevents = 0;
@@ -3095,8 +3099,8 @@ static void sam_callback(void *arg)
/* Is a callback registered? */
DEBUGASSERT(priv != NULL);
- fvdbg("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
- priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
+ mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
+ priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
flags = enter_critical_section();
if (priv->callback)
@@ -3150,17 +3154,17 @@ static void sam_callback(void *arg)
{
/* NOTE: Currently, work_cancel only returns success */
- fdbg("ERROR: Failed to cancel work: %d\n", ret);
+ lcderr("ERROR: Failed to cancel work: %d\n", ret);
}
- fllvdbg("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
+ mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
ret = work_queue(LPWORK, &priv->cbwork, (worker_t)priv->callback,
priv->cbarg, 0);
if (ret < 0)
{
/* NOTE: Currently, work_queue only returns success */
- fdbg("ERROR: Failed to schedule work: %d\n", ret);
+ lcderr("ERROR: Failed to schedule work: %d\n", ret);
}
}
@@ -3199,7 +3203,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
* for now, an* HSMCI peripheral does correspond to a slot.
*/
- fdbg("slotno: %d\n", slotno);
+ lcdinfo("slotno: %d\n", slotno);
#ifdef CONFIG_SAMA5_HSMCI0
if (slotno == 0)
@@ -3323,8 +3327,8 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
return NULL;
}
- fvdbg("priv: %p base: %08x hsmci: %d dmac: %d pid: %d\n",
- priv, priv->base, priv->hsmci, dmac, pid);
+ mcinfo("priv: %p base: %08x hsmci: %d dmac: %d pid: %d\n",
+ priv, priv->base, priv->hsmci, dmac, pid);
/* Initialize the HSMCI slot structure */
@@ -3393,7 +3397,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
priv->cdstatus &= ~SDIO_STATUS_PRESENT;
}
- fllvdbg("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
+ mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
/* Perform any requested callback if the status has changed */
@@ -3438,7 +3442,7 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED;
}
- fvdbg("cdstatus: %02x\n", priv->cdstatus);
+ mcinfo("cdstatus: %02x\n", priv->cdstatus);
leave_critical_section(flags);
}
diff --git a/arch/arm/src/sama5/sam_irq.c b/arch/arm/src/sama5/sam_irq.c
index 21ce68ff236dbe29458a80cc8d4ba9fde796d940..c8cf1f5cd5495f50c47b3c76605a7414c68b6f25 100644
--- a/arch/arm/src/sama5/sam_irq.c
+++ b/arch/arm/src/sama5/sam_irq.c
@@ -125,13 +125,13 @@ static const uint32_t g_h64mxpids[3] =
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_IRQ)
+#if defined(CONFIG_DEBUG_IRQ_INFO)
static void sam_dumpaic(const char *msg, uintptr_t base, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
- lldbg("AIC (%s, base=%08x irq=%d):\n", msg, base, irq);
+ irqinfo("AIC (%s, base=%08x irq=%d):\n", msg, base, irq);
/* Select the register set associated with this irq */
@@ -139,39 +139,39 @@ static void sam_dumpaic(const char *msg, uintptr_t base, int irq)
/* Then dump all of the (readable) register contents */
- lldbg(" SSR: %08x SMR: %08x SVR: %08x IVR: %08x\n",
- getreg32(base + SAM_AIC_SSR_OFFSET),
- getreg32(base + SAM_AIC_SMR_OFFSET),
- getreg32(base + SAM_AIC_SVR_OFFSET),
- getreg32(base + SAM_AIC_IVR_OFFSET));
- lldbg(" FVR: %08x ISR: %08x\n",
- getreg32(base + SAM_AIC_FVR_OFFSET),
- getreg32(base + SAM_AIC_ISR_OFFSET));
- lldbg(" IPR: %08x %08x %08x %08x\n",
- getreg32(base + SAM_AIC_IPR0_OFFSET),
- getreg32(base + SAM_AIC_IPR1_OFFSET),
- getreg32(base + SAM_AIC_IPR2_OFFSET),
- getreg32(base + SAM_AIC_IPR3_OFFSET));
+ irqinfo(" SSR: %08x SMR: %08x SVR: %08x IVR: %08x\n",
+ getreg32(base + SAM_AIC_SSR_OFFSET),
+ getreg32(base + SAM_AIC_SMR_OFFSET),
+ getreg32(base + SAM_AIC_SVR_OFFSET),
+ getreg32(base + SAM_AIC_IVR_OFFSET));
+ irqinfo(" FVR: %08x ISR: %08x\n",
+ getreg32(base + SAM_AIC_FVR_OFFSET),
+ getreg32(base + SAM_AIC_ISR_OFFSET));
+ irqinfo(" IPR: %08x %08x %08x %08x\n",
+ getreg32(base + SAM_AIC_IPR0_OFFSET),
+ getreg32(base + SAM_AIC_IPR1_OFFSET),
+ getreg32(base + SAM_AIC_IPR2_OFFSET),
+ getreg32(base + SAM_AIC_IPR3_OFFSET));
/* SAMA5D4 does not have the FFSR register */
#if defined(SAM_AIC_FFSR)
- lldbg(" IMR: %08x CISR: %08x SPU: %08x FFSR: %08x\n",
- getreg32(base + SAM_AIC_IMR_OFFSET),
- getreg32(base + SAM_AIC_CISR_OFFSET),
- getreg32(base + SAM_AIC_SPU_OFFSET),
- getreg32(base + SAM_AIC_FFSR_OFFSET));
+ irqinfo(" IMR: %08x CISR: %08x SPU: %08x FFSR: %08x\n",
+ getreg32(base + SAM_AIC_IMR_OFFSET),
+ getreg32(base + SAM_AIC_CISR_OFFSET),
+ getreg32(base + SAM_AIC_SPU_OFFSET),
+ getreg32(base + SAM_AIC_FFSR_OFFSET));
#else
- lldbg(" IMR: %08x CISR: %08x SPU: %08x\n",
- getreg32(base + SAM_AIC_IMR_OFFSET),
- getreg32(base + SAM_AIC_CISR_OFFSET),
- getreg32(base + SAM_AIC_SPU_OFFSET));
+ irqinfo(" IMR: %08x CISR: %08x SPU: %08x\n",
+ getreg32(base + SAM_AIC_IMR_OFFSET),
+ getreg32(base + SAM_AIC_CISR_OFFSET),
+ getreg32(base + SAM_AIC_SPU_OFFSET));
#endif
- lldbg(" DCR: %08x WPMR: %08x WPSR: %08x\n",
- getreg32(base + SAM_AIC_DCR_OFFSET),
- getreg32(base + SAM_AIC_WPMR_OFFSET),
- getreg32(base + SAM_AIC_WPSR_OFFSET));
+ irqinfo(" DCR: %08x WPMR: %08x WPSR: %08x\n",
+ getreg32(base + SAM_AIC_DCR_OFFSET),
+ getreg32(base + SAM_AIC_WPMR_OFFSET),
+ getreg32(base + SAM_AIC_WPSR_OFFSET));
leave_critical_section(flags);
}
@@ -234,8 +234,8 @@ static uint32_t *sam_spurious(int irq, uint32_t *regs)
* in this implementation. The value of AIC_IVR is ignored.
*/
-#if defined(CONFIG_DEBUG_IRQ)
- lldbg("Spurious interrupt: IRQ %d\n", irq);
+#if defined(CONFIG_DEBUG_IRQ_INFO)
+ irqinfo("Spurious interrupt: IRQ %d\n", irq);
#endif
return regs;
}
@@ -327,12 +327,12 @@ static void sam_aic_redirection(void)
regval |= SFR_AICREDIR_ENABLE;
putreg32(regval, SAM_SFR_AICREDIR);
-#if defined(CONFIG_DEBUG_IRQ)
+#if defined(CONFIG_DEBUG_IRQ_INFO)
/* Check if redirection was successfully enabled */
regval = getreg32(SAM_SFR_AICREDIR);
- lldbg("Interrupts %s redirected to the AIC\n",
- (regval & SFR_AICREDIR_ENABLE) != 0 ? "ARE" : "NOT");
+ irqinfo("Interrupts %s redirected to the AIC\n",
+ (regval & SFR_AICREDIR_ENABLE) != 0 ? "ARE" : "NOT");
#endif
}
}
diff --git a/arch/arm/src/sama5/sam_isi.c b/arch/arm/src/sama5/sam_isi.c
index 124734a416cc389bcd6b6871659a14512b41d5b2..86fa8e0dad8d7393a0f32735577d25117b27657f 100644
--- a/arch/arm/src/sama5/sam_isi.c
+++ b/arch/arm/src/sama5/sam_isi.c
@@ -160,7 +160,7 @@ int sam_isi_initialize(void)
*/
g_isi.actual = sam_pck_configure(ISI_PCKID, PCKSRC_MCK, CONFIG_ISI_MCKFREQ);
- gvdbg("PCK%d frequency=%d actual=%d\n",
+ ginfo("PCK%d frequency=%d actual=%d\n",
ISI_PCKID, CONFIG_ISI_MCKFREQ, g_isi.actual);
/* Enable the MCK (output) */
diff --git a/arch/arm/src/sama5/sam_lcd.c b/arch/arm/src/sama5/sam_lcd.c
index 8032bb04f46620ecca0d016172e76035870e1046..3befc8fec63fa02f620af99e424a71674826a461 100644
--- a/arch/arm/src/sama5/sam_lcd.c
+++ b/arch/arm/src/sama5/sam_lcd.c
@@ -492,7 +492,7 @@
/* Debug */
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_LCD_INFO
# undef CONFIG_SAMA5_LCDC_REGDEBUG
#endif
@@ -666,7 +666,7 @@ struct sam_lcdc_s
****************************************************************************/
/* Register operations ******************************************************/
-#if defined(CONFIG_SAMA5_LCDC_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAMA5_LCDC_REGDEBUG
static bool sam_checkreg(bool wr, uint32_t regval, uintptr_t address);
static uint32_t sam_getreg(uintptr_t addr);
static void sam_putreg(uintptr_t addr, uint32_t val);
@@ -977,10 +977,6 @@ static const uintptr_t g_layerclut[LCDC_NLAYERS] =
};
#endif
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -1021,7 +1017,7 @@ static bool sam_checkreg(bool wr, uint32_t regval, uintptr_t address)
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", g_lcdc.ntimes);
+ lcdinfo("...[Repeats %d times]...\n", g_lcdc.ntimes);
}
/* Save information about the new access */
@@ -1053,7 +1049,7 @@ static uint32_t sam_getreg(uintptr_t address)
if (sam_checkreg(false, regval, address))
{
- lldbg("%08x->%08x\n", address, regval);
+ lcdinfo("%08x->%08x\n", address, regval);
}
return regval;
@@ -1073,7 +1069,7 @@ static void sam_putreg(uintptr_t address, uint32_t regval)
{
if (sam_checkreg(true, regval, address))
{
- lldbg("%08x<-%08x\n", address, regval);
+ lcdinfo("%08x<-%08x\n", address, regval);
}
putreg32(regval, address);
@@ -1101,14 +1097,14 @@ static void sam_wait_lcdstatus(uint32_t mask, uint32_t value)
static int sam_base_getvideoinfo(struct fb_vtable_s *vtable,
struct fb_videoinfo_s *vinfo)
{
- gvdbg("vtable=%p vinfo=%p\n", vtable, vinfo);
+ lcdinfo("vtable=%p vinfo=%p\n", vtable, vinfo);
if (vtable && vinfo)
{
memcpy(vinfo, &g_base_videoinfo, sizeof(struct fb_videoinfo_s));
return OK;
}
- gdbg("ERROR: Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -1119,7 +1115,7 @@ static int sam_base_getvideoinfo(struct fb_vtable_s *vtable,
static int sam_base_getplaneinfo(struct fb_vtable_s *vtable, int planeno,
struct fb_planeinfo_s *pinfo)
{
- gvdbg("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo);
+ lcdinfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo);
if (vtable && planeno == 0 && pinfo)
{
pinfo->fbmem = (void *)LAYER_BASE.framebuffer;
@@ -1130,7 +1126,7 @@ static int sam_base_getplaneinfo(struct fb_vtable_s *vtable, int planeno,
return OK;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -1166,27 +1162,27 @@ static int sam_base_putcmap(struct fb_vtable_s *vtable,
static int sam_hcr_getcursor(struct fb_vtable_s *vtable,
struct fb_cursorattrib_s *attrib)
{
- gvdbg("vtable=%p attrib=%p\n", vtable, attrib);
+ lcdinfo("vtable=%p attrib=%p\n", vtable, attrib);
if (vtable && attrib)
{
#ifdef CONFIG_FB_HWCURSORIMAGE
attrib->fmt = SAMA5_HCR_COLOR_FMT;
#endif
- gvdbg("pos: (x=%d, y=%d)\n", g_lcdc.cpos.x, g_lcdc.cpos.y);
+ lcdinfo("pos: (x=%d, y=%d)\n", g_lcdc.cpos.x, g_lcdc.cpos.y);
attrib->pos = g_lcdc.cpos;
#ifdef CONFIG_FB_HWCURSORSIZE
attrib->mxsize.h = CONFIG_SAMA5_LCDC_HCR_HEIGHT;
attrib->mxsize.w = CONFIG_SAMA5_LCDC_HCR_WIDTH;
- gvdbg("size: (h=%d, w=%d)\n", g_lcdc.csize.h, g_lcdc.csize.w);
+ lcdinfo("size: (h=%d, w=%d)\n", g_lcdc.csize.h, g_lcdc.csize.w);
attrib->size = g_lcdc.csize;
#endif
return OK;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
#endif
@@ -1199,26 +1195,26 @@ static int sam_hcr_getcursor(struct fb_vtable_s *vtable,
static int sam_hcr_setcursor(struct fb_vtable_s *vtable,
struct fb_setcursor_s *setttings)
{
- gvdbg("vtable=%p setttings=%p\n", vtable, setttings);
+ lcdinfo("vtable=%p setttings=%p\n", vtable, setttings);
if (vtable && setttings)
{
- gvdbg("flags: %02x\n", settings->flags);
+ lcdinfo("flags: %02x\n", settings->flags);
if ((flags & FB_CUR_SETPOSITION) != 0)
{
g_lcdc.cpos = settings->pos;
- gvdbg("pos: (h:%d, w:%d)\n", g_lcdc.cpos.x, g_lcdc.cpos.y);
+ lcdinfo("pos: (h:%d, w:%d)\n", g_lcdc.cpos.x, g_lcdc.cpos.y);
}
#ifdef CONFIG_FB_HWCURSORSIZE
if ((flags & FB_CUR_SETSIZE) != 0)
{
g_lcdc.csize = settings->size;
- gvdbg("size: (h:%d, w:%d)\n", g_lcdc.csize.h, g_lcdc.csize.w);
+ lcdinfo("size: (h:%d, w:%d)\n", g_lcdc.csize.h, g_lcdc.csize.w);
}
#endif
#ifdef CONFIG_FB_HWCURSORIMAGE
if ((flags & FB_CUR_SETIMAGE) != 0)
{
- gvdbg("image: (h:%d, w:%d) @ %p\n",
+ lcdinfo("image: (h:%d, w:%d) @ %p\n",
settings->img.height, settings->img.width,
settings->img.image);
}
@@ -1226,7 +1222,7 @@ static int sam_hcr_setcursor(struct fb_vtable_s *vtable,
return OK;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
#endif
@@ -1291,14 +1287,14 @@ static void sam_dmasetup(int lid, struct sam_dscr_s *dscr, uint8_t *buffer)
sam_putreg(g_layernext[lid], physdscr);
}
-#if defined(CONFIG_DEBUG_GRAPHICS) && defined(CONFIG_DEBUG_VERBOSE)
+#if defined(CONFIG_DEBUG_GRAPHICS) && defined(CONFIG_DEBUG_INFO)
/* Dump the DMA setup */
- gvdbg("DMA descriptor: addr=%08x ctrl=%08x next=%08x\n",
- dscr->addr, dscr->ctrl, dscr->next);
- gvdbg("DMA registers[%d]: head=%08x addr=%08x ctrl=%08x next=%08x\n",
- lid, sam_getreg(g_layerhead[lid]), sam_getreg(g_layeraddr[lid]),
- sam_getreg(g_layerctrl[lid]), sam_getreg(g_layernext[lid]));
+ lcdinfo("DMA descriptor: addr=%08x ctrl=%08x next=%08x\n",
+ dscr->addr, dscr->ctrl, dscr->next);
+ lcdinfo("DMA registers[%d]: head=%08x addr=%08x ctrl=%08x next=%08x\n",
+ lid, sam_getreg(g_layerhead[lid]), sam_getreg(g_layeraddr[lid]),
+ sam_getreg(g_layerctrl[lid]), sam_getreg(g_layernext[lid]));
#endif
}
@@ -1379,8 +1375,8 @@ static int sam_setclut(struct sam_layer_s *layer,
unsigned int end;
int i;
- gvdbg("layer=%d cmap=%p first=%d len=%d\n",
- layer->lid, cmap, cmap->first, cmap->len);
+ lcdinfo("layer=%d cmap=%p first=%d len=%d\n",
+ layer->lid, cmap, cmap->first, cmap->len);
DEBUGASSERT(layer && cmap);
@@ -1391,7 +1387,7 @@ static int sam_setclut(struct sam_layer_s *layer,
if (offset >= SAM_LCDC_NCLUT)
{
- gdbg("ERROR: CLUT offset is out of range: %d\n", offset);
+ lcderr("ERROR: CLUT offset is out of range: %d\n", offset);
return -EINVAL;
}
@@ -1460,7 +1456,7 @@ static int sam_getclut(struct sam_layer_s *layer,
uintptr_t regval;
int i;
- gvdbg("layer=%d cmap=%p first=%d len=%d\n",
+ lcdinfo("layer=%d cmap=%p first=%d len=%d\n",
layer->lid, cmap, layer->offset, layer->nclut);
DEBUGASSERT(layer && cmap);
@@ -1514,7 +1510,7 @@ static void sam_pio_config(void)
{
int i;
- gvdbg("Configuring pins\n");
+ lcdinfo("Configuring pins\n");
/* Configure each pin */
@@ -2915,7 +2911,7 @@ int up_fbinitialize(int display)
uint32_t regval;
#endif
- gvdbg("Entry\n");
+ lcdinfo("Entry\n");
/* Configure layer layer structures, DMA descriptor memory, and
* framebuffers
@@ -2931,7 +2927,7 @@ int up_fbinitialize(int display)
sam_pio_config();
- gvdbg("Configuring the LCD controller\n");
+ lcdinfo("Configuring the LCD controller\n");
/* Enable the LCD peripheral clock */
@@ -2959,7 +2955,7 @@ int up_fbinitialize(int display)
/* And turn the LCD on */
- gvdbg("Enabling the display\n");
+ lcdinfo("Enabling the display\n");
sam_lcd_enable();
/* Display base layer */
@@ -3012,7 +3008,7 @@ int up_fbinitialize(int display)
FAR struct fb_vtable_s *up_fbgetvplane(int display, int vplane)
{
- gvdbg("vplane: %d\n", vplane);
+ lcdinfo("vplane: %d\n", vplane);
if (vplane == 0)
{
return (struct fb_vtable_s *)&g_base_vtable;
@@ -3062,8 +3058,8 @@ void sam_lcdclear(nxgl_mxpixel_t color)
uint16_t *dest = (uint16_t *)LAYER_BASE.framebuffer;
int i;
- gvdbg("Clearing display: BPP=16 color=%04x framebuffer=%08x size=%d\n",
- color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE);
+ lcdinfo("Clearing display: BPP=16 color=%04x framebuffer=%08x size=%d\n",
+ color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE);
for (i = 0; i < SAMA5_BASE_FBSIZE; i += sizeof(uint16_t))
{
@@ -3076,8 +3072,8 @@ void sam_lcdclear(nxgl_mxpixel_t color)
uint8_t b;
int i;
- gvdbg("Clearing display: BPP=24 color=%06x framebuffer=%08x size=%d\n",
- color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE);
+ lcdinfo("Clearing display: BPP=24 color=%06x framebuffer=%08x size=%d\n",
+ color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE);
b = color & 0xff;
g = (color >> 8) & 0xff;
@@ -3093,8 +3089,8 @@ void sam_lcdclear(nxgl_mxpixel_t color)
uint32_t *dest = (uint32_t *)LAYER_BASE.framebuffer;
int i;
- gvdbg("Clearing display: BPP=32 color=%08x framebuffer=%08x size=%d\n",
- color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE);
+ lcdinfo("Clearing display: BPP=32 color=%08x framebuffer=%08x size=%d\n",
+ color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE);
for (i = 0; i < SAMA5_BASE_FBSIZE; i += sizeof(uint32_t))
{
diff --git a/arch/arm/src/sama5/sam_memories.c b/arch/arm/src/sama5/sam_memories.c
index 231545ed55928a05a83286315d8c69ebcb21805f..54c8e65b5616e9d2c8d904caafd46685cc541af3 100644
--- a/arch/arm/src/sama5/sam_memories.c
+++ b/arch/arm/src/sama5/sam_memories.c
@@ -766,7 +766,7 @@ uintptr_t sam_physregaddr(uintptr_t virtregaddr)
* address
*/
- dbg("Bad virtual address: %08lx\n", virtregaddr);
+ serr("ERROR: Bad virtual address: %08lx\n", virtregaddr);
DEBUGPANIC();
return virtregaddr;
}
@@ -925,7 +925,7 @@ uintptr_t sam_physramaddr(uintptr_t virtramaddr)
if (virtramaddr != 0)
{
- dbg("Bad virtual address: %08lx\n", virtramaddr);
+ serr("ERROR: Bad virtual address: %08lx\n", virtramaddr);
DEBUGPANIC();
}
@@ -1058,7 +1058,7 @@ uintptr_t sam_virtramaddr(uintptr_t physramaddr)
if (physramaddr != 0)
{
- dbg("Bad physical address: %08lx\n|", physramaddr);
+ serr("ERROR: Bad physical address: %08lx\n|", physramaddr);
DEBUGPANIC();
}
diff --git a/arch/arm/src/sama5/sam_nand.c b/arch/arm/src/sama5/sam_nand.c
index d5d235d21685c828b942afc4098d483a6a9dec6a..0e6757c073e4eb8a3c37610da101e13fcad48f24 100644
--- a/arch/arm/src/sama5/sam_nand.c
+++ b/arch/arm/src/sama5/sam_nand.c
@@ -999,7 +999,7 @@ static uint32_t nand_nfc_poll(void)
sr = nand_getreg(SAM_HSMC_SR);
#ifndef CONFIG_SAMA5_NAND_REGDEBUG
- // fllvdbg("sr=%08x\n", sr);
+ // finfo("sr=%08x\n", sr);
#endif
/* When set to one, this XFRDONE indicates that the NFC has terminated
@@ -1065,7 +1065,7 @@ static int hsmc_interrupt(int irq, void *context)
uint32_t pending = sr & imr;
#ifndef CONFIG_SAMA5_NAND_REGDEBUG
- fllvdbg("sr=%08x imr=%08x\n", sr, imr);
+ finfo("sr=%08x imr=%08x\n", sr, imr);
#endif
/* When set to one, this XFRDONE indicates that the NFC has terminated
@@ -1163,7 +1163,7 @@ static void nand_dma_sampleinit(struct sam_nandcs_s *priv)
#ifdef CONFIG_SAMA5_NAND_DMADEBUG
static void nand_dma_sampledone(struct sam_nandcs_s *priv, int result)
{
- lldbg("result: %d\n", result);
+ finfo("result: %d\n", result);
/* Sample the final registers */
@@ -1233,7 +1233,7 @@ static int nand_wait_dma(struct sam_nandcs_s *priv)
}
}
- fvdbg("Awakened: result=%d\n", priv->result);
+ finfo("Awakened: result=%d\n", priv->result);
priv->dmadone = false;
return priv->result;
}
@@ -1293,7 +1293,7 @@ static int nand_dma_read(struct sam_nandcs_s *priv,
DEBUGASSERT(priv->dma);
- fvdbg("vsrc=%08x vdest=%08x nbytes=%d\n",
+ finfo("vsrc=%08x vdest=%08x nbytes=%d\n",
(int)vsrc, (int)vdest, (int)nbytes);
/* Initialize sampling */
@@ -1325,7 +1325,7 @@ static int nand_dma_read(struct sam_nandcs_s *priv,
ret = sam_dmarxsetup(priv->dma, psrc, pdest, nbytes);
if (ret < 0)
{
- fdbg("ERROR: sam_dmarxsetup failed: %d\n", ret);
+ ferr("ERROR: sam_dmarxsetup failed: %d\n", ret);
return ret;
}
@@ -1344,7 +1344,7 @@ static int nand_dma_read(struct sam_nandcs_s *priv,
ret = nand_wait_dma(priv);
if (ret < 0)
{
- fdbg("ERROR: DMA failed: %d\n", ret);
+ ferr("ERROR: DMA failed: %d\n", ret);
}
nand_dma_sample(priv, DMA_END_TRANSFER);
@@ -1410,7 +1410,7 @@ static int nand_dma_write(struct sam_nandcs_s *priv,
ret = sam_dmatxsetup(priv->dma, pdest, psrc, nbytes);
if (ret < 0)
{
- fdbg("ERROR: sam_dmatxsetup failed: %d\n", ret);
+ ferr("ERROR: sam_dmatxsetup failed: %d\n", ret);
return ret;
}
@@ -1429,7 +1429,7 @@ static int nand_dma_write(struct sam_nandcs_s *priv,
ret = nand_wait_dma(priv);
if (ret < 0)
{
- fdbg("ERROR: DMA failed: %d\n", ret);
+ ferr("ERROR: DMA failed: %d\n", ret);
}
nand_dma_sample(priv, DMA_END_TRANSFER);
@@ -1463,7 +1463,7 @@ static int nand_nfcsram_read(struct sam_nandcs_s *priv, uint8_t *buffer,
int remaining;
int ret;
- fvdbg("buffer=%p buflen=%d\n", buffer, buflen);
+ finfo("buffer=%p buflen=%d\n", buffer, buflen);
/* Get the offset data source address */
@@ -1530,7 +1530,7 @@ static int nand_read(struct sam_nandcs_s *priv, uint8_t *buffer,
int buswidth;
int ret;
- fvdbg("buffer=%p buflen=%d\n", buffer, (int)buflen);
+ finfo("buffer=%p buflen=%d\n", buffer, (int)buflen);
/* Get the buswidth */
@@ -1622,7 +1622,7 @@ static int nand_read_pmecc(struct sam_nandcs_s *priv, off_t block,
uint16_t sparesize;
int ret;
- fvdbg("block=%d page=%d data=%p\n", (int)block, page, data);
+ finfo("block=%d page=%d data=%p\n", (int)block, page, data);
DEBUGASSERT(priv && data);
/* Get page and spare sizes */
@@ -1655,7 +1655,7 @@ static int nand_read_pmecc(struct sam_nandcs_s *priv, off_t block,
break;
default:
- fdbg("ERROR: Unsupported page size: %d\n", pagesize);
+ ferr("ERROR: Unsupported page size: %d\n", pagesize);
return -EINVAL;
}
@@ -1719,7 +1719,7 @@ static int nand_read_pmecc(struct sam_nandcs_s *priv, off_t block,
#endif
if (ret < 0)
{
- fdbg("ERROR: nand_read for data region failed: %d\n", ret);
+ ferr("ERROR: nand_read for data region failed: %d\n", ret);
return ret;
}
@@ -1732,7 +1732,7 @@ static int nand_read_pmecc(struct sam_nandcs_s *priv, off_t block,
#endif
if (ret < 0)
{
- fdbg("ERROR: nand_read for spare region failed: %d\n", ret);
+ ferr("ERROR: nand_read for spare region failed: %d\n", ret);
return ret;
}
@@ -1765,7 +1765,7 @@ static int nand_nfcsram_write(struct sam_nandcs_s *priv, uint8_t *buffer,
uintptr_t dest;
int ret;
- fvdbg("buffer=%p buflen=%d offset=%d\n", buffer, buflen, offset);
+ finfo("buffer=%p buflen=%d offset=%d\n", buffer, buflen, offset);
nand_dump("NFC SRAM Write", buffer, buflen);
/* Apply the offset to the destination address */
@@ -1829,7 +1829,7 @@ static int nand_write(struct sam_nandcs_s *priv, uint8_t *buffer,
int buswidth;
int ret;
- fvdbg("buffer=%p buflen=%d offset=%d\n", buffer, buflen, offset);
+ finfo("buffer=%p buflen=%d offset=%d\n", buffer, buflen, offset);
nand_dump("NAND Write", buffer, buflen);
/* Apply the offset to the destination address */
@@ -1924,7 +1924,7 @@ static int nand_readpage_noecc(struct sam_nandcs_s *priv, off_t block,
off_t coladdr;
int ret;
- fvdbg("block=%d page=%d data=%p spare=%p\n", (int)block, page, data, spare);
+ finfo("block=%d page=%d data=%p spare=%p\n", (int)block, page, data, spare);
DEBUGASSERT(priv && (data || spare));
/* Get page and spare sizes */
@@ -1957,7 +1957,7 @@ static int nand_readpage_noecc(struct sam_nandcs_s *priv, off_t block,
break;
default:
- fdbg("ERROR: Unsupported page size: %d\n", pagesize);
+ ferr("ERROR: Unsupported page size: %d\n", pagesize);
return -EINVAL;
}
@@ -1987,7 +1987,7 @@ static int nand_readpage_noecc(struct sam_nandcs_s *priv, off_t block,
ret = nand_nfcsram_read(priv, (uint8_t *)data, pagesize, 0);
if (ret < 0)
{
- fdbg("ERROR: nand_nfcsram_read for data region failed: %d\n", ret);
+ ferr("ERROR: nand_nfcsram_read for data region failed: %d\n", ret);
return ret;
}
}
@@ -2003,7 +2003,7 @@ static int nand_readpage_noecc(struct sam_nandcs_s *priv, off_t block,
ret = nand_nfcsram_read(priv, (uint8_t *)spare, sparesize, offset);
if (ret < 0)
{
- fdbg("ERROR: nand_nfcsram_read for spare region failed: %d\n", ret);
+ ferr("ERROR: nand_nfcsram_read for spare region failed: %d\n", ret);
return ret;
}
}
@@ -2038,7 +2038,7 @@ static int nand_readpage_pmecc(struct sam_nandcs_s *priv, off_t block,
int ret;
int i;
- fvdbg("block=%d page=%d data=%p\n", (int)block, page, data);
+ finfo("block=%d page=%d data=%p\n", (int)block, page, data);
DEBUGASSERT(priv && data);
/* Make sure that we have exclusive access to the PMECC and that the PMECC
@@ -2049,7 +2049,7 @@ static int nand_readpage_pmecc(struct sam_nandcs_s *priv, off_t block,
ret = pmecc_configure(priv, false);
if (ret < 0)
{
- fdbg("ERROR: pmecc_configure failed: %d\n", ret);
+ ferr("ERROR: pmecc_configure failed: %d\n", ret);
goto errout;
}
@@ -2060,7 +2060,7 @@ static int nand_readpage_pmecc(struct sam_nandcs_s *priv, off_t block,
ret = nand_read_pmecc(priv, block, page, data);
if (ret < 0)
{
- fdbg("ERROR: Block %d page %d Failed to read page\n",
+ ferr("ERROR: Block %d page %d Failed to read page\n",
block, page, ret);
goto errout;
}
@@ -2076,7 +2076,7 @@ static int nand_readpage_pmecc(struct sam_nandcs_s *priv, off_t block,
ret = nand_readpage_noecc(priv, block, page, NULL, priv->raw.spare);
if (ret < 0)
{
- fdbg("ERROR: Block %d page %d Failed to re-read spare area: %d\n",
+ ferr("ERROR: Block %d page %d Failed to re-read spare area: %d\n",
block, page, ret);
goto errout;
}
@@ -2098,13 +2098,13 @@ static int nand_readpage_pmecc(struct sam_nandcs_s *priv, off_t block,
{
/* Yes.. clear sector errors */
- fdbg("Block=%d page=%d has been erased: %08x\n",
+ finfo("Block=%d page=%d has been erased: %08x\n",
block, page, regval);
regval = 0;
}
else
{
- fdbg("ERROR: block=%d page=%d Corrupted sectors: %08x\n",
+ ferr("ERROR: block=%d page=%d Corrupted sectors: %08x\n",
block, page, regval);
}
}
@@ -2114,7 +2114,7 @@ static int nand_readpage_pmecc(struct sam_nandcs_s *priv, off_t block,
ret = pmecc_correction(regval, (uintptr_t)data);
if (ret < 0)
{
- fdbg("ERROR: block=%d page=%d Unrecoverable data error: %d\n",
+ ferr("ERROR: block=%d page=%d Unrecoverable data error: %d\n",
block, page, ret);
}
@@ -2159,7 +2159,7 @@ static int nand_writepage_noecc(struct sam_nandcs_s *priv, off_t block,
off_t rowaddr;
int ret = OK;
- fvdbg("block=%d page=%d data=%p spare=%p\n", (int)block, page, data, spare);
+ finfo("block=%d page=%d data=%p spare=%p\n", (int)block, page, data, spare);
/* Get page and spare sizes */
@@ -2191,7 +2191,7 @@ static int nand_writepage_noecc(struct sam_nandcs_s *priv, off_t block,
break;
default:
- fdbg("ERROR: Unsupported page size: %d\n", pagesize);
+ ferr("ERROR: Unsupported page size: %d\n", pagesize);
return -EINVAL;
}
@@ -2220,7 +2220,7 @@ static int nand_writepage_noecc(struct sam_nandcs_s *priv, off_t block,
ret = nand_nfcsram_write(priv, (uint8_t *)data, pagesize, 0);
if (ret < 0)
{
- fdbg("ERROR: nand_nfcsram_write for data region failed: %d\n", ret);
+ ferr("ERROR: nand_nfcsram_write for data region failed: %d\n", ret);
return ret;
}
@@ -2229,7 +2229,7 @@ static int nand_writepage_noecc(struct sam_nandcs_s *priv, off_t block,
ret = nand_nfcsram_write(priv, (uint8_t *)spare, sparesize, pagesize);
if (ret < 0)
{
- fdbg("ERROR: nand_nfcsram_write for data region failed: %d\n", ret);
+ ferr("ERROR: nand_nfcsram_write for data region failed: %d\n", ret);
return ret;
}
}
@@ -2257,7 +2257,7 @@ static int nand_writepage_noecc(struct sam_nandcs_s *priv, off_t block,
ret = nand_operation_complete(priv);
if (ret < 0)
{
- fdbg("ERROR: Failed writing data area: %d\n", ret);
+ ferr("ERROR: Failed writing data area: %d\n", ret);
}
}
@@ -2272,7 +2272,7 @@ static int nand_writepage_noecc(struct sam_nandcs_s *priv, off_t block,
ret = nand_write(priv, (uint8_t *)spare, sparesize, 0);
if (ret < 0)
{
- fdbg("ERROR: nand_write for spare region failed: %d\n", ret);
+ ferr("ERROR: nand_write for spare region failed: %d\n", ret);
ret = -EPERM;
}
@@ -2320,7 +2320,7 @@ static int nand_writepage_pmecc(struct sam_nandcs_s *priv, off_t block,
unsigned int i;
int ret = 0;
- fvdbg("block=%d page=%d data=%p\n", (int)block, page, data);
+ finfo("block=%d page=%d data=%p\n", (int)block, page, data);
DEBUGASSERT(priv && data);
/* Make sure that we have exclusive access to the PMECC and that the PMECC
@@ -2331,7 +2331,7 @@ static int nand_writepage_pmecc(struct sam_nandcs_s *priv, off_t block,
ret = pmecc_configure(priv, false);
if (ret < 0)
{
- fdbg("ERROR: pmecc_configure failed: %d\n", ret);
+ ferr("ERROR: pmecc_configure failed: %d\n", ret);
goto errout;
}
@@ -2344,7 +2344,7 @@ static int nand_writepage_pmecc(struct sam_nandcs_s *priv, off_t block,
/* Calculate physical address of the page */
rowaddr = block * nandmodel_pagesperblock(&priv->raw.model) + page;
- fvdbg("pagesize=%d eccsaddr=%d rowaddr=%d\n", pagesize, eccsaddr, rowaddr);
+ finfo("pagesize=%d eccsaddr=%d rowaddr=%d\n", pagesize, eccsaddr, rowaddr);
#if 1 /* Use NFC SRAM */
/* Write the data area to NFC SRAM */
@@ -2352,7 +2352,7 @@ static int nand_writepage_pmecc(struct sam_nandcs_s *priv, off_t block,
ret = nand_nfcsram_write(priv, (uint8_t *)data, pagesize, 0);
if (ret < 0)
{
- fdbg("ERROR: Block %d page %d nand_nfcsram_write for data region failed: %d\n",
+ ferr("ERROR: Block %d page %d nand_nfcsram_write for data region failed: %d\n",
block, page, ret);
goto errout;
}
@@ -2417,7 +2417,7 @@ static int nand_writepage_pmecc(struct sam_nandcs_s *priv, off_t block,
ret = nand_write(priv, (uint8_t *)data, pagesize, 0);
if (ret < 0)
{
- fdbg("ERROR: Block %d page %d nand_write for data region failed: %d\n",
+ ferr("ERROR: Block %d page %d nand_write for data region failed: %d\n",
block, page, ret);
goto errout;
}
@@ -2437,7 +2437,7 @@ static int nand_writepage_pmecc(struct sam_nandcs_s *priv, off_t block,
eccpersector = (pmecc_get_eccsize()) / sectersperpage;
eccsize = sectersperpage * eccpersector;
- fvdbg("sectersperpage=%d eccpersector=%d eccsize=%d\n",
+ finfo("sectersperpage=%d eccpersector=%d eccsize=%d\n",
sectersperpage, eccpersector, eccsize);
#ifdef CONFIG_SAMA5_PMECC_TRIMPAGE
@@ -2474,7 +2474,7 @@ static int nand_writepage_pmecc(struct sam_nandcs_s *priv, off_t block,
ret = nand_write(priv, (uint8_t *)g_nand.ecctab, eccsize, 0);
if (ret < 0)
{
- fdbg("ERROR: Block %d page %d nand_write for spare region failed: %d\n",
+ ferr("ERROR: Block %d page %d nand_write for spare region failed: %d\n",
block, page, ret);
goto errout;
}
@@ -2487,7 +2487,7 @@ static int nand_writepage_pmecc(struct sam_nandcs_s *priv, off_t block,
ret = nand_operation_complete(priv);
if (ret < 0)
{
- fdbg("ERROR: Block %d page %d Failed writing data area: %d\n",
+ ferr("ERROR: Block %d page %d Failed writing data area: %d\n",
block, page, ret);
}
@@ -2536,7 +2536,7 @@ static inline int nand_tryeraseblock(struct sam_nandcs_s *priv, off_t block)
ret = nand_operation_complete(priv);
if (ret < 0)
{
- fdbg("ERROR: Block %d Could not erase: %d\n", block, ret);
+ ferr("ERROR: Block %d Could not erase: %d\n", block, ret);
}
return ret;
@@ -2550,7 +2550,7 @@ static int nand_eraseblock(struct nand_raw_s *raw, off_t block)
DEBUGASSERT(priv);
- fvdbg("block=%d\n", (int)block);
+ finfo("block=%d\n", (int)block);
/* Get exclusvie access to the HSMC hardware.
* REVISIT: The scope of this exclusivity is just NAND.
@@ -2572,7 +2572,7 @@ static int nand_eraseblock(struct nand_raw_s *raw, off_t block)
retries--;
}
- fdbg("ERROR: Block %d Failed to erase after %d tries\n",
+ ferr("ERROR: Block %d Failed to erase after %d tries\n",
(int)block, NAND_ERASE_NRETRIES);
nand_unlock();
@@ -2796,7 +2796,7 @@ static int nand_writepage(struct nand_raw_s *raw, off_t block,
static void nand_reset(struct sam_nandcs_s *priv)
{
- fvdbg("Resetting\n");
+ finfo("Resetting\n");
nand_nfc_cleale(priv, 0, COMMAND_RESET, 0, 0, 0);
nand_wait_ready(priv);
}
@@ -2834,7 +2834,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
uint8_t ecctype;
int ret;
- fvdbg("CS%d\n", cs);
+ finfo("CS%d\n", cs);
/* Select the device structure (In SAMA5D3, NAND is only supported on CS3). */
@@ -2923,7 +2923,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
else
#endif
{
- fdbg("ERROR: CS%d unsupported or invalid\n", cs);
+ ferr("ERROR: CS%d unsupported or invalid\n", cs);
return NULL;
}
@@ -2983,7 +2983,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
ret = irq_attach(SAM_IRQ_HSMC, hsmc_interrupt);
if (ret < 0)
{
- fdbg("Failed to attach HSMC IRQ (%d)", SAM_IRQ_HSMC);
+ ferr("ERROR: Failed to attach HSMC IRQ (%d)", SAM_IRQ_HSMC);
return NULL;
}
#endif
@@ -3013,7 +3013,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
ret = board_nandflash_config(cs);
if (ret < 0)
{
- fdbg("ERROR: board_nandflash_config failed for CS%d: %d\n",
+ ferr("ERROR: board_nandflash_config failed for CS%d: %d\n",
cs, ret);
return NULL;
}
@@ -3029,7 +3029,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
mtd = nand_initialize(&priv->raw);
if (!mtd)
{
- fdbg("ERROR: CS%d nand_initialize failed %d\n", cs);
+ ferr("ERROR: CS%d nand_initialize failed %d\n", cs);
return NULL;
}
@@ -3043,7 +3043,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
priv->dma = sam_dmachannel(NAND_DMAC, 0);
if (!priv->dma)
{
- fdbg("ERROR: Failed to allocate the DMA channel for CS%d\n", cs);
+ ferr("ERROR: Failed to allocate the DMA channel for CS%d\n", cs);
}
#endif
@@ -3088,7 +3088,7 @@ bool nand_checkreg(bool wr, uintptr_t regaddr, uint32_t regval)
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", g_nand.ntimes);
+ finfo("...[Repeats %d times]...\n", g_nand.ntimes);
}
/* Save information about the new access */
diff --git a/arch/arm/src/sama5/sam_nand.h b/arch/arm/src/sama5/sam_nand.h
index f4229b8d6c0f4075e183cd8b038b632452bd4b9f..808b719aa52d3a94462fb81a64b8a56afec7e64f 100644
--- a/arch/arm/src/sama5/sam_nand.h
+++ b/arch/arm/src/sama5/sam_nand.h
@@ -259,14 +259,13 @@
/* Debug */
-#if !defined(CONFIG_DEBUG) || !defined(CONFIG_DEBUG_FS)
-# undef CONFIG_DEBUG_FS
+#ifndef defined(CONFIG_DEBUG_FS_INFO
# undef CONFIG_SAMA5_NAND_DMADEBUG
# undef CONFIG_SAMA5_NAND_REGDEBUG
# undef CONFIG_SAMA5_NAND_DUMP
#endif
-#if !defined(CONFIG_SAMA5_NAND_DMA) || !defined(CONFIG_DEBUG_DMA)
+#if !defined(CONFIG_SAMA5_NAND_DMA) || !defined(CONFIG_DEBUG_DMA_INFO)
# undef CONFIG_SAMA5_NAND_DMADEBUG
#endif
@@ -518,7 +517,7 @@ static inline uint32_t nand_getreg(uintptr_t regaddr)
#ifdef CONFIG_SAMA5_NAND_REGDEBUG
if (nand_checkreg(false, regaddr, regval))
{
- lldbg("%08x->%08x\n", regaddr, regval);
+ sinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@@ -538,7 +537,7 @@ static inline void nand_putreg(uintptr_t regaddr, uint32_t regval)
#ifdef CONFIG_SAMA5_NAND_REGDEBUG
if (nand_checkreg(true, regaddr, regval))
{
- lldbg("%08x<-%08x\n", regaddr, regval);
+ sinfo("%08x<-%08x\n", regaddr, regval);
}
#endif
diff --git a/arch/arm/src/sama5/sam_ohci.c b/arch/arm/src/sama5/sam_ohci.c
index 5dbad089e961cb9040a5e5cf9ec72db4a0a66404..7d4533dca68907b26077edb006d0954b5f6526ac 100644
--- a/arch/arm/src/sama5/sam_ohci.c
+++ b/arch/arm/src/sama5/sam_ohci.c
@@ -151,7 +151,7 @@
/* Debug */
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_USB_INFO
# undef CONFIG_SAMA5_OHCI_REGDEBUG
#endif
@@ -505,10 +505,6 @@ static struct sam_gtd_s g_tdalloc[SAMA5_OHCI_NTDS]
static uint8_t g_bufalloc[SAM_BUFALLOC]
__attribute__ ((aligned (SAMA5_DMA_ALIGN)));
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -524,7 +520,7 @@ static uint8_t g_bufalloc[SAM_BUFALLOC]
#ifdef CONFIG_SAMA5_OHCI_REGDEBUG
static void sam_printreg(uint32_t addr, uint32_t val, bool iswrite)
{
- lldbg("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
+ uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
}
#endif
@@ -574,7 +570,7 @@ static void sam_checkreg(uint32_t addr, uint32_t val, bool iswrite)
{
/* No.. More than one. */
- lldbg("[repeats %d more times]\n", count);
+ uinfo("[repeats %d more times]\n", count);
}
}
@@ -1318,7 +1314,7 @@ static inline int sam_reminted(struct sam_ed_s *ed)
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace1(OHCI_VTRACE1_VIRTED, (uintptr_t)ed);
#else
- uvdbg("ed: %08x head: %08x next: %08x offset: %d\n",
+ uinfo("ed: %08x head: %08x next: %08x offset: %d\n",
ed, physhead, head ? head->hw.nexted : 0, offset);
#endif
@@ -1358,7 +1354,7 @@ static inline int sam_reminted(struct sam_ed_s *ed)
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace1(OHCI_VTRACE1_VIRTED, (uintptr_t)ed);
#else
- uvdbg("ed: %08x head: %08x next: %08x\n",
+ uinfo("ed: %08x head: %08x next: %08x\n",
ed, physhead, head ? head->hw.nexted : 0);
#endif
@@ -2835,7 +2831,7 @@ errout:
static int sam_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep)
{
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_ASSERTIONS
struct sam_rhport_s *rhport = (struct sam_rhport_s *)drvr;
#endif
struct sam_eplist_s *eplist = (struct sam_eplist_s *)ep;
@@ -3103,7 +3099,7 @@ static int sam_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(OHCI_VTRACE2_CTRLIN, RHPORT(rhport), req->req);
#else
- uvdbg("RHPort%d type: %02x req: %02x value: %02x%02x index: %02x%02x len: %02x%02x\n",
+ uinfo("RHPort%d type: %02x req: %02x value: %02x%02x index: %02x%02x len: %02x%02x\n",
RHPORT(rhport), req->type, req->req, req->value[1],
req->value[0], req->index[1], req->index[0], req->len[1],
req->len[0]);
@@ -3152,7 +3148,7 @@ static int sam_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace2(OHCI_VTRACE2_CTRLOUT, RHPORT(rhport), req->req);
#else
- uvdbg("RHPort%d type: %02x req: %02x value: %02x%02x index: %02x%02x len: %02x%02x\n",
+ uinfo("RHPort%d type: %02x req: %02x value: %02x%02x index: %02x%02x len: %02x%02x\n",
RHPORT(rhport), req->type, req->req, req->value[1],
req->value[0], req->index[1], req->index[0], req->len[1],
req->len[0]);
@@ -3227,7 +3223,7 @@ static int sam_transfer_common(struct sam_rhport_s *rhport,
(ed->hw.ctrl & ED_CONTROL_EN_MASK) >> ED_CONTROL_EN_SHIFT,
(uint16_t)buflen);
#else
- uvdbg("EP%d %s toggle: %d maxpacket: %d buflen: %d\n",
+ uinfo("EP%d %s toggle: %d maxpacket: %d buflen: %d\n",
(ed->hw.ctrl & ED_CONTROL_EN_MASK) >> ED_CONTROL_EN_SHIFT,
in ? "IN" : "OUT",
(ed->hw.headp & ED_HEADP_C) != 0 ? 1 : 0,
@@ -3342,7 +3338,7 @@ static ssize_t sam_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep,
ret = sam_transfer_common(rhport, eplist, buffer, buflen);
if (ret < 0)
{
- udbg("ERROR: sam_transfer_common failed: %d\n", ret);
+ uerr("ERROR: sam_transfer_common failed: %d\n", ret);
goto errout;
}
@@ -3593,7 +3589,7 @@ static int sam_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep,
ret = sam_transfer_common(rhport, eplist, buffer, buflen);
if (ret < 0)
{
- udbg("ERROR: sam_transfer_common failed: %d\n", ret);
+ uerr("ERROR: sam_transfer_common failed: %d\n", ret);
goto errout;
}
@@ -3788,7 +3784,7 @@ static int sam_connect(struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
- ullvdbg("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+ uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */
diff --git a/arch/arm/src/sama5/sam_oneshot.c b/arch/arm/src/sama5/sam_oneshot.c
index c6d0a79ef58ea3575941fbfc5084a9685c1d4959..5f011ea28745d652f96aa0d458540fd66d9ed722 100644
--- a/arch/arm/src/sama5/sam_oneshot.c
+++ b/arch/arm/src/sama5/sam_oneshot.c
@@ -108,7 +108,7 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
oneshot_handler_t oneshot_handler;
void *oneshot_arg;
- tcllvdbg("Expired...\n");
+ tmrinfo("Expired...\n");
DEBUGASSERT(oneshot && oneshot->handler);
/* The clock was stopped, but not disabled when the RC match occurred.
@@ -165,7 +165,7 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
uint32_t cmr;
int ret;
- tcvdbg("chan=%d resolution=%d usec\n", chan, resolution);
+ tmrinfo("chan=%d resolution=%d usec\n", chan, resolution);
DEBUGASSERT(oneshot && resolution > 0);
/* Get the TC frequency the corresponds to the requested resolution */
@@ -177,13 +177,13 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
ret = sam_tc_divisor(frequency, &divisor, &cmr);
if (ret < 0)
{
- tcdbg("ERROR: sam_tc_divisor failed: %d\n", ret);
+ tmrerr("ERROR: sam_tc_divisor failed: %d\n", ret);
return ret;
}
- tcvdbg("frequency=%lu, divisor=%lu, cmr=%08lx\n",
- (unsigned long)frequency, (unsigned long)divisor,
- (unsigned long)cmr);
+ tmrinfo("frequency=%lu, divisor=%lu, cmr=%08lx\n",
+ (unsigned long)frequency, (unsigned long)divisor,
+ (unsigned long)cmr);
/* Allocate the timer/counter and select its mode of operation
*
@@ -217,7 +217,7 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
oneshot->tch = sam_tc_allocate(chan, cmr);
if (!oneshot->tch)
{
- tcdbg("ERROR: Failed to allocate timer channel %d\n", chan);
+ tmrerr("ERROR: Failed to allocate timer channel %d\n", chan);
return -EBUSY;
}
@@ -260,8 +260,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
uint64_t regval;
irqstate_t flags;
- tcvdbg("handler=%p arg=%p, ts=(%lu, %lu)\n",
- handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
+ tmrinfo("handler=%p arg=%p, ts=(%lu, %lu)\n",
+ handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
DEBUGASSERT(oneshot && handler && ts);
/* Was the oneshot already running? */
@@ -271,7 +271,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
{
/* Yes.. then cancel it */
- tcvdbg("Already running... cancelling\n");
+ tmrinfo("Already running... cancelling\n");
(void)sam_oneshot_cancel(oneshot, freerun, NULL);
}
@@ -293,7 +293,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
regval = (usec * (uint64_t)sam_tc_divfreq(oneshot->tch)) / USEC_PER_SEC;
- tcvdbg("usec=%llu regval=%08llx\n", usec, regval);
+ tmrinfo("usec=%llu regval=%08llx\n", usec, regval);
DEBUGASSERT(regval <= UINT32_MAX);
/* Set up to receive the callback when the interrupt occurs */
@@ -402,7 +402,7 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
* REVISIT: This does not appear to be the case.
*/
- tcvdbg("Cancelling...\n");
+ tmrinfo("Cancelling...\n");
count = sam_tc_getcounter(oneshot->tch);
rc = sam_tc_getregister(oneshot->tch, TC_REGC);
@@ -438,8 +438,8 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
* oneshot timer.
*/
- tcvdbg("rc=%lu count=%lu usec=%lu\n",
- (unsigned long)rc, (unsigned long)count, (unsigned long)usec);
+ tmrinfo("rc=%lu count=%lu usec=%lu\n",
+ (unsigned long)rc, (unsigned long)count, (unsigned long)usec);
/* REVISIT: I am not certain why the timer counter value sometimes
* exceeds RC. Might be a bug, or perhaps the counter does not stop
@@ -483,8 +483,8 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
ts->tv_nsec = (unsigned long)nsec;
}
- tcvdbg("remaining (%lu, %lu)\n",
- (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
+ tmrinfo("remaining (%lu, %lu)\n",
+ (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
}
return OK;
diff --git a/arch/arm/src/sama5/sam_pck.c b/arch/arm/src/sama5/sam_pck.c
index 11202c5d5653709afcfd613443c222ea493b554a..dc96ab678c7df7e2970d369f2abce55bbbefc610 100644
--- a/arch/arm/src/sama5/sam_pck.c
+++ b/arch/arm/src/sama5/sam_pck.c
@@ -151,7 +151,7 @@ uint32_t sam_pck_configure(enum pckid_e pckid, enum pckid_clksrc_e clksrc,
break;
default:
- dbg("ERROR: Unknown clock source\n");
+ _err("ERROR: Unknown clock source\n");
return 0;
}
@@ -213,8 +213,8 @@ uint32_t sam_pck_configure(enum pckid_e pckid, enum pckid_clksrc_e clksrc,
}
else
{
- sdbg("ERROR: frequency cannot be realized.\n");
- sdbg(" frequency=%lu clkin=%lu\n",
+ serr("ERROR: frequency cannot be realized.\n");
+ serr(" frequency=%lu clkin=%lu\n",
(unsigned long)frequency, (unsigned long)clkin);
return 0;
}
diff --git a/arch/arm/src/sama5/sam_pio.h b/arch/arm/src/sama5/sam_pio.h
index 2b867ea05a9748339b5b43e0e07a7947cc6b7b24..fbcf94d034085072b163c6fb241248befbc16972 100644
--- a/arch/arm/src/sama5/sam_pio.h
+++ b/arch/arm/src/sama5/sam_pio.h
@@ -214,7 +214,7 @@ void sam_pio_forceclk(pio_pinset_t pinset, bool enable);
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
int sam_dumppio(uint32_t pinset, const char *msg);
#else
# define sam_dumppio(p,m)
diff --git a/arch/arm/src/sama5/sam_pmecc.c b/arch/arm/src/sama5/sam_pmecc.c
index 8dfee40e3a6286472294bc37162ac0b5ba84093d..0339068c4fc0729b3ccab1dd6a4da7b52c1f8ec6 100644
--- a/arch/arm/src/sama5/sam_pmecc.c
+++ b/arch/arm/src/sama5/sam_pmecc.c
@@ -632,7 +632,7 @@ static uint32_t pmecc_errorcorrection(uintptr_t sectorbase,
if (bytepos < sectorsz + nand_getreg(SAM_HSMC_PMECCSADDR))
{
- fdbg("Correct error bit @[Byte %d, Bit %d]\n",
+ fwarn("WARNING: Correct error bit @[Byte %d, Bit %d]\n",
(int)bytepos, (int)bitpos);
if (*(uint8_t *)(sectorbase + bytepos) & (1 << bitpos))
@@ -858,7 +858,7 @@ static int pmecc_pagelayout(uint16_t datasize, uint16_t eccsize)
int bcherr1k;
int selector;
- fvdbg("datasize=%d eccsize=%d\n", datasize, eccsize);
+ finfo("datasize=%d eccsize=%d\n", datasize, eccsize);
DEBUGASSERT(datasize > 0 && eccsize > 0);
/* Try for 512 byte sectors */
@@ -870,14 +870,14 @@ static int pmecc_pagelayout(uint16_t datasize, uint16_t eccsize)
bcherr512 = pmecc_bcherr512(nsectors512, eccsize);
if (bcherr512 < 0)
{
- fdbg("WARNING: Cannot realize 512B sectors\n");
+ fwarn("WARNING: Cannot realize 512B sectors\n");
}
else
{
selector = 1;
}
- fvdbg("nsectors512=%d bcherr512=%d selector=%d\n",
+ finfo("nsectors512=%d bcherr512=%d selector=%d\n",
nsectors512, bcherr512, selector);
/* Try for 1024 byte sectors */
@@ -895,14 +895,14 @@ static int pmecc_pagelayout(uint16_t datasize, uint16_t eccsize)
if (bcherr1k < 0)
{
- fdbg("WARNING: Cannot realize 1KB sectors\n");
+ fwarn("WARNING: Cannot realize 1KB sectors\n");
}
else
{
selector |= 2;
}
- fvdbg("nsectors1k=%d bcherr1k=%d selector=%d\n",
+ finfo("nsectors1k=%d bcherr1k=%d selector=%d\n",
nsectors1k, bcherr1k, selector);
/* Now pick the best (most likely 1024) */
@@ -960,7 +960,7 @@ static int pmecc_pagelayout(uint16_t datasize, uint16_t eccsize)
g_pmecc.desc.bcherr = ((uint32_t)bcherr << HSMC_PMECCFG_BCHERR_SHIFT);
- fvdbg("sector1k=%d nsectors=%d bcherr=%d correctability=%d\n",
+ finfo("sector1k=%d nsectors=%d bcherr=%d correctability=%d\n",
g_pmecc.sector1k, g_pmecc.nsectors, bcherr, g_pmecc.correctability);
return OK;
@@ -1018,7 +1018,7 @@ int pmecc_configure(struct sam_nandcs_s *priv, bool protected)
uint32_t regval;
int ret;
- fvdbg("protected=%d configured=%d\n", protected, g_pmecc.configured);
+ finfo("protected=%d configured=%d\n", protected, g_pmecc.configured);
/* Check if we need to re-configure */
@@ -1030,7 +1030,7 @@ int pmecc_configure(struct sam_nandcs_s *priv, bool protected)
{
/* No, we are already configured */
- fvdbg("Already configured\n");
+ finfo("Already configured\n");
return OK;
}
@@ -1059,7 +1059,7 @@ int pmecc_configure(struct sam_nandcs_s *priv, bool protected)
ret = pmecc_pagelayout(priv->raw.model.pagesize, eccsize);
if (ret < 0)
{
- fdbg("ERROR: pmecc_pagelayout failed: %d\n", ret);
+ ferr("ERROR: pmecc_pagelayout failed: %d\n", ret);
return ret;
}
@@ -1096,7 +1096,7 @@ int pmecc_configure(struct sam_nandcs_s *priv, bool protected)
#endif
}
- fvdbg("sectorsz=%08x sectorsperpage=%d mm=%d\n",
+ finfo("sectorsz=%08x sectorsperpage=%d mm=%d\n",
g_pmecc.desc.sectorsz, sectorsperpage, g_pmecc.desc.mm);
switch (sectorsperpage)
@@ -1114,13 +1114,13 @@ int pmecc_configure(struct sam_nandcs_s *priv, bool protected)
g_pmecc.desc.pagesize = HSMC_PMECCFG_PAGESIZE_8SEC;
break;
default:
- fdbg("ERROR: Unsupported sectors per page: %d\n", sectorsperpage);
+ ferr("ERROR: Unsupported sectors per page: %d\n", sectorsperpage);
return -EINVAL;
}
g_pmecc.desc.nn = (1 << g_pmecc.desc.mm) - 1;
- fvdbg("pagesize=%08x nn=%d\n", g_pmecc.desc.pagesize, g_pmecc.desc.nn);
+ finfo("pagesize=%08x nn=%d\n", g_pmecc.desc.pagesize, g_pmecc.desc.nn);
/* Real value of ECC bit number correction (2, 4, 8, 12, 24) */
@@ -1136,19 +1136,19 @@ int pmecc_configure(struct sam_nandcs_s *priv, bool protected)
(((g_pmecc.desc.mm * g_pmecc.correctability) >> 3) + 1) * sectorsperpage;
}
- fvdbg("mm=%d correctability=%d eccsize=%d\n",
+ finfo("mm=%d correctability=%d eccsize=%d\n",
g_pmecc.desc.mm, g_pmecc.correctability, g_pmecc.desc.eccsize);
g_pmecc.desc.eccstart = eccoffset;
g_pmecc.desc.eccend = eccoffset + g_pmecc.desc.eccsize;
- fvdbg("eccstart=%d eccend=%d sparesize=%d\n",
+ finfo("eccstart=%d eccend=%d sparesize=%d\n",
g_pmecc.desc.eccstart, g_pmecc.desc.eccend,
priv->raw.model.sparesize);
if (g_pmecc.desc.eccend > priv->raw.model.sparesize)
{
- fdbg("ERROR: No room for ECC in spare bytes %d > %d\n",
+ ferr("ERROR: No room for ECC in spare bytes %d > %d\n",
g_pmecc.desc.eccend, priv->raw.model.sparesize);
return -ENOSPC;
diff --git a/arch/arm/src/sama5/sam_pwm.c b/arch/arm/src/sama5/sam_pwm.c
index c83764d50c5df86d708db534fa566bf2f9f853d1..0de1d91dea0b7ac80bd3b585bcc2d7b7e8c206f4 100644
--- a/arch/arm/src/sama5/sam_pwm.c
+++ b/arch/arm/src/sama5/sam_pwm.c
@@ -65,6 +65,11 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
+
+#ifndef CONFIG_DEBUG_PWM_INFO
+# undef CONFIG_SAMA5_PWM_REGDEBUG
+#endif
+
/* Currently, we support only a single PWM peripheral. However, the hooks
* are in place to support multiple PWM peripherals.
*/
@@ -393,30 +398,6 @@
#define PWM_PINMASK (PIO_PORT_MASK | PIO_PIN_MASK)
#define PWM_MKINPUT(cfg) (((cfg) & PWM_PINMASK) | PWM_INPUTCFG)
-/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing PWM */
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_PWM
-#endif
-
-#ifdef CONFIG_DEBUG_PWM
-# define pwmdbg dbg
-# define pwmlldbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define pwmvdbg vdbg
-# define pwmllvdbg llvdbg
-# else
-# define pwmlldbg(x...)
-# define pwmllvdbg(x...)
-# endif
-#else
-# define pwmdbg(x...)
-# define pwmlldbg(x...)
-# define pwmvdbg(x...)
-# define pwmllvdbg(x...)
-#endif
-
/****************************************************************************
* Private Types
****************************************************************************/
@@ -480,7 +461,7 @@ static bool pwm_checkreg(FAR struct sam_pwm_s *chan, bool wr, uint32_t regval,
static uint32_t pwm_getreg(FAR struct sam_pwm_chan_s *chan, int offset);
static void pwm_putreg(FAR struct sam_pwm_chan_s *chan, int offset, uint32_t regval);
-#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_PWM_INFO
static void pwm_dumpregs(FAR struct sam_pwm_chan_s *chan, FAR const char *msg);
#else
# define pwm_dumpregs(chan,msg)
@@ -713,7 +694,7 @@ static bool pwm_checkreg(FAR struct sam_pwm_s *pwm, bool wr, uint32_t regval,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", pwm->count);
+ pwminfo("...[Repeats %d times]...\n", pwm->count);
}
/* Save information about the new access */
@@ -757,7 +738,7 @@ static uint32_t pwm_getreg(struct sam_pwm_chan_s *chan, int offset)
#ifdef CONFIG_SAMA5_PWM_REGDEBUG
if (pwm_checkreg(&g_pwm, false, regval, regaddr))
{
- lldbg("%08x->%08x\n", regaddr, regval);
+ pwminfo("%08x->%08x\n", regaddr, regval);
}
#endif
@@ -774,7 +755,7 @@ static uint32_t pwm_getreg(struct sam_pwm_chan_s *chan, int offset)
#ifdef CONFIG_SAMA5_PWM_REGDEBUG
if (pwm_checkreg(pwm, false, regval, regaddr))
{
- lldbg("%08x->%08x\n", regaddr, regval);
+ pwminfo("%08x->%08x\n", regaddr, regval);
}
#endif
@@ -813,7 +794,7 @@ static uint32_t pwm_chan_getreg(struct sam_pwm_chan_s *chan, int offset)
if (pwm_checkreg(chan->pwm, false, regval, regaddr))
#endif
{
- lldbg("%08x->%08x\n", regaddr, regval);
+ pwminfo("%08x->%08x\n", regaddr, regval);
}
#endif
@@ -844,7 +825,7 @@ static void pwm_putreg(struct sam_pwm_chan_s *chan, int offset,
#ifdef CONFIG_SAMA5_PWM_REGDEBUG
if (pwm_checkreg(&g_pwm, true, regval, regaddr))
{
- lldbg("%08x<-%08x\n", regaddr, regval);
+ pwminfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@@ -857,7 +838,7 @@ static void pwm_putreg(struct sam_pwm_chan_s *chan, int offset,
#ifdef CONFIG_SAMA5_PWM_REGDEBUG
if (pwm_checkreg(pwm, true, regval, regaddr))
{
- lldbg("%08x<-%08x\n", regaddr, regval);
+ pwminfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@@ -893,7 +874,7 @@ static void pwm_chan_putreg(struct sam_pwm_chan_s *chan, int offset,
if (pwm_checkreg(chan->pwm, true, regval, regaddr))
#endif
{
- lldbg("%08x<-%08x\n", regaddr, regval);
+ pwminfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@@ -914,61 +895,61 @@ static void pwm_chan_putreg(struct sam_pwm_chan_s *chan, int offset,
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_PWM_INFO
static void pwm_dumpregs(struct sam_pwm_chan_s *chan, FAR const char *msg)
{
- pwmvdbg("PWM: %s\n", msg);
- pwmvdbg(" CLK: %08x SR: %08x IMR1: %08x ISR1: %08x\n",
+ pwminfo("PWM: %s\n", msg);
+ pwminfo(" CLK: %08x SR: %08x IMR1: %08x ISR1: %08x\n",
pwm_getreg(chan, SAM_PWM_CLK_OFFSET),
pwm_getreg(chan, SAM_PWM_SR_OFFSET),
pwm_getreg(chan, SAM_PWM_IMR1_OFFSET),
pwm_getreg(chan, SAM_PWM_ISR1_OFFSET));
- pwmvdbg(" SCM: %08x SCUC: %08x SCUP: %08x IMR2: %08x\n",
+ pwminfo(" SCM: %08x SCUC: %08x SCUP: %08x IMR2: %08x\n",
pwm_getreg(chan, SAM_PWM_SCM_OFFSET),
pwm_getreg(chan, SAM_PWM_SCUC_OFFSET),
pwm_getreg(chan, SAM_PWM_SCUP_OFFSET),
pwm_getreg(chan, SAM_PWM_IMR2_OFFSET));
- pwmvdbg(" ISR2: %08x OOV: %08x OS: %08x FMR: %08x\n",
+ pwminfo(" ISR2: %08x OOV: %08x OS: %08x FMR: %08x\n",
pwm_getreg(chan, SAM_PWM_ISR2_OFFSET),
pwm_getreg(chan, SAM_PWM_OOV_OFFSET),
pwm_getreg(chan, SAM_PWM_OS_OFFSET),
pwm_getreg(chan, SAM_PWM_FMR_OFFSET));
- pwmvdbg(" FSR: %08x FPV: %08x FPE: %08x ELMR0: %08x\n",
+ pwminfo(" FSR: %08x FPV: %08x FPE: %08x ELMR0: %08x\n",
pwm_getreg(chan, SAM_PWM_FSR_OFFSET),
pwm_getreg(chan, SAM_PWM_FPV_OFFSET),
pwm_getreg(chan, SAM_PWM_FPE_OFFSET),
pwm_getreg(chan, SAM_PWM_ELMR0_OFFSET));
- pwmvdbg(" ELMR1: %08x SMMR: %08x WPSR: %08x\n",
+ pwminfo(" ELMR1: %08x SMMR: %08x WPSR: %08x\n",
pwm_getreg(chan, SAM_PWM_ELMR1_OFFSET),
pwm_getreg(chan, SAM_PWM_SMMR_OFFSET),
pwm_getreg(chan, SAM_PWM_WPSR_OFFSET));
- pwmvdbg(" CMPV0: %08x CMPM0: %08x CMPV1: %08x CMPM1: %08x\n",
+ pwminfo(" CMPV0: %08x CMPM0: %08x CMPV1: %08x CMPM1: %08x\n",
pwm_getreg(chan, SAM_PWM_CMPV0_OFFSET),
pwm_getreg(chan, SAM_PWM_CMPM0_OFFSET),
pwm_getreg(chan, SAM_PWM_CMPV1_OFFSET),
pwm_getreg(chan, SAM_PWM_CMPM1_OFFSET));
- pwmvdbg(" CMPV2: %08x CMPM2: %08x CMPV3: %08x CMPM3: %08x\n",
+ pwminfo(" CMPV2: %08x CMPM2: %08x CMPV3: %08x CMPM3: %08x\n",
pwm_getreg(chan, SAM_PWM_CMPV2_OFFSET),
pwm_getreg(chan, SAM_PWM_CMPM2_OFFSET),
pwm_getreg(chan, SAM_PWM_CMPV3_OFFSET),
pwm_getreg(chan, SAM_PWM_CMPM3_OFFSET));
- pwmvdbg(" CMPV4: %08x CMPM4: %08x CMPV5: %08x CMPM5: %08x\n",
+ pwminfo(" CMPV4: %08x CMPM4: %08x CMPV5: %08x CMPM5: %08x\n",
pwm_getreg(chan, SAM_PWM_CMPV4_OFFSET),
pwm_getreg(chan, SAM_PWM_CMPM4_OFFSET),
pwm_getreg(chan, SAM_PWM_CMPV5_OFFSET),
pwm_getreg(chan, SAM_PWM_CMPM5_OFFSET));
- pwmvdbg(" CMPV6: %08x CMPM6: %08x CMPV7: %08x CMPM7: %08x\n",
+ pwminfo(" CMPV6: %08x CMPM6: %08x CMPV7: %08x CMPM7: %08x\n",
pwm_getreg(chan, SAM_PWM_CMPV6_OFFSET),
pwm_getreg(chan, SAM_PWM_CMPM6_OFFSET),
pwm_getreg(chan, SAM_PWM_CMPV7_OFFSET),
pwm_getreg(chan, SAM_PWM_CMPM7_OFFSET));
- pwmvdbg("Channel %d: %s\n", chan->channel, msg);
- pwmvdbg(" CMR: %08x CDTY: %08x CPRD: %08x CCNT: %08x\n",
+ pwminfo("Channel %d: %s\n", chan->channel, msg);
+ pwminfo(" CMR: %08x CDTY: %08x CPRD: %08x CCNT: %08x\n",
pwm_chan_getreg(chan, SAM_PWM_CMR_OFFSET),
pwm_chan_getreg(chan, SAM_PWM_CDTY_OFFSET),
pwm_chan_getreg(chan, SAM_PWM_CPRD_OFFSET),
pwm_chan_getreg(chan, SAM_PWM_CCNT_OFFSET));
- pwmvdbg(" CT: %08x\n",
+ pwminfo(" CT: %08x\n",
pwm_chan_getreg(chan, SAM_PWM_DT_OFFSET));
}
#endif
@@ -1018,7 +999,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
{
FAR struct sam_pwm_chan_s *chan = (FAR struct sam_pwm_chan_s *)dev;
- pwmvdbg("Channel %d: H=%08x L=%08x FI=%08x\n",
+ pwminfo("Channel %d: H=%08x L=%08x FI=%08x\n",
chan->channel, chan->ohpincfg, chan->olpincfg, chan->fipincfg);
/* Configure selected PWM pins */
@@ -1061,7 +1042,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
{
FAR struct sam_pwm_chan_s *chan = (FAR struct sam_pwm_chan_s *)dev;
- pwmvdbg("Channel %d\n", chan->channel);
+ pwminfo("Channel %d\n", chan->channel);
/* Make sure that the output has been stopped */
@@ -1124,7 +1105,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
#endif
default:
- pwmdbg("ERROR: Invalid or unsupported clock source value: %d\n", chan->clksrc);
+ pwmerr("ERROR: Invalid or unsupported clock source value: %d\n", chan->clksrc);
return -EINVAL;
}
@@ -1167,7 +1148,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
}
pwm_chan_putreg(chan, SAM_PWM_CDTY_OFFSET, regval);
- pwmvdbg("Fsrc=%d cprd=%d cdty=%d\n", fsrc, cprd, regval);
+ pwminfo("Fsrc=%d cprd=%d cdty=%d\n", fsrc, cprd, regval);
/* Enable the channel */
@@ -1199,7 +1180,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
{
FAR struct sam_pwm_chan_s *chan = (FAR struct sam_pwm_chan_s *)dev;
- pwmvdbg("Channel %d\n", chan->channel);
+ pwminfo("Channel %d\n", chan->channel);
/* Disable further PWM interrupts from this channel */
@@ -1231,12 +1212,12 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg)
{
-#ifdef CONFIG_DEBUG_PWM
+#ifdef CONFIG_DEBUG_PWM_INFO
FAR struct sam_pwm_chan_s *chan = (FAR struct sam_pwm_chan_s *)dev;
/* There are no platform-specific ioctl commands */
- pwmvdbg("Channel %d\n", chan->channel);
+ pwminfo("Channel %d\n", chan->channel);
#endif
return -ENOTTY;
}
@@ -1299,7 +1280,7 @@ FAR struct pwm_lowerhalf_s *sam_pwminitialize(int channel)
FAR struct sam_pwm_chan_s *chan;
uint32_t regval;
- pwmvdbg("Channel %d\n", channel);
+ pwminfo("Channel %d\n", channel);
switch (channel)
{
@@ -1336,7 +1317,7 @@ FAR struct pwm_lowerhalf_s *sam_pwminitialize(int channel)
#endif
default:
- pwmdbg("ERROR: Channel invalid or not configured: %d\n", channel);
+ pwmerr("ERROR: Channel invalid or not configured: %d\n", channel);
return NULL;
}
@@ -1366,7 +1347,7 @@ FAR struct pwm_lowerhalf_s *sam_pwminitialize(int channel)
ret = irq_attach(SAM_IRQ_PWM, pwm_interrupt);
if (ret < 0)
{
- pwmdbg("ERROR: Failed to attach IRQ%d\n", channel);
+ pwmerr("ERROR: Failed to attach IRQ%d\n", channel);
return NULL;
}
diff --git a/arch/arm/src/sama5/sam_rtc.c b/arch/arm/src/sama5/sam_rtc.c
index 94bca9114246b1a0f894c4de41712667bb7aab86..e73e473b706a7f8e25676f08da7e994d883c4b37 100644
--- a/arch/arm/src/sama5/sam_rtc.c
+++ b/arch/arm/src/sama5/sam_rtc.c
@@ -77,30 +77,6 @@
#define RTC_MAGIC 0xdeadbeef
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_RTC
-#endif
-
-/* Constants ************************************************************************/
-
-/* Debug ****************************************************************************/
-
-#ifdef CONFIG_DEBUG_RTC
-# define rtcdbg dbg
-# define rtcvdbg vdbg
-# define rtclldbg lldbg
-# define rtcllvdbg llvdbg
-#else
-# define rtcdbg(x...)
-# define rtcvdbg(x...)
-# define rtclldbg(x...)
-# define rtcllvdbg(x...)
-#endif
-
-/************************************************************************************
- * Private Types
- ************************************************************************************/
-
/************************************************************************************
* Private Data
************************************************************************************/
@@ -137,19 +113,19 @@ volatile bool g_rtc_enabled = false;
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_RTC
+#ifdef CONFIG_DEBUG_RTC_INFO
static void rtc_dumpregs(FAR const char *msg)
{
- rtclldbg("%s:\n", msg);
- rtclldbg(" CR: %08x\n", getreg32(SAM_RTC_CR));
- rtclldbg(" MR: %08x\n", getreg32(SAM_RTC_MR));
- rtclldbg(" TIMR: %08x\n", getreg32(SAM_RTC_TIMR));
- rtclldbg(" CALR: %08x\n", getreg32(SAM_RTC_CALR));
- rtclldbg(" TIMALR: %08x\n", getreg32(SAM_RTC_TIMALR));
- rtclldbg(" CALALR: %08x\n", getreg32(SAM_RTC_CALALR));
- rtclldbg(" SR: %08x\n", getreg32(SAM_RTC_SR));
- rtclldbg(" IMR: %08x\n", getreg32(SAM_RTC_IMR));
- rtclldbg(" VER: %08x\n", getreg32(SAM_RTC_VER));
+ rtcinfo("%s:\n", msg);
+ rtcinfo(" CR: %08x\n", getreg32(SAM_RTC_CR));
+ rtcinfo(" MR: %08x\n", getreg32(SAM_RTC_MR));
+ rtcinfo(" TIMR: %08x\n", getreg32(SAM_RTC_TIMR));
+ rtcinfo(" CALR: %08x\n", getreg32(SAM_RTC_CALR));
+ rtcinfo(" TIMALR: %08x\n", getreg32(SAM_RTC_TIMALR));
+ rtcinfo(" CALALR: %08x\n", getreg32(SAM_RTC_CALALR));
+ rtcinfo(" SR: %08x\n", getreg32(SAM_RTC_SR));
+ rtcinfo(" IMR: %08x\n", getreg32(SAM_RTC_IMR));
+ rtcinfo(" VER: %08x\n", getreg32(SAM_RTC_VER));
}
#else
# define rtc_dumpregs(msg)
@@ -169,16 +145,16 @@ static void rtc_dumpregs(FAR const char *msg)
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_RTC
+#ifdef CONFIG_DEBUG_RTC_INFO
static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg)
{
- rtclldbg("%s:\n", msg);
- rtclldbg(" tm_sec: %08x\n", tp->tm_sec);
- rtclldbg(" tm_min: %08x\n", tp->tm_min);
- rtclldbg(" tm_hour: %08x\n", tp->tm_hour);
- rtclldbg(" tm_mday: %08x\n", tp->tm_mday);
- rtclldbg(" tm_mon: %08x\n", tp->tm_mon);
- rtclldbg(" tm_year: %08x\n", tp->tm_year);
+ rtcinfo("%s:\n", msg);
+ rtcinfo(" tm_sec: %08x\n", tp->tm_sec);
+ rtcinfo(" tm_min: %08x\n", tp->tm_min);
+ rtcinfo(" tm_hour: %08x\n", tp->tm_hour);
+ rtcinfo(" tm_mday: %08x\n", tp->tm_mday);
+ rtcinfo(" tm_mon: %08x\n", tp->tm_mon);
+ rtcinfo(" tm_year: %08x\n", tp->tm_year);
}
#else
# define rtc_dumptime(tp, msg)
@@ -289,7 +265,7 @@ static int rtc_interrupt(int irq, void *context)
ret = work_queue(LPWORK, &g_alarmwork, rtc_worker, NULL, 0);
if (ret < 0)
{
- rtclldbg("ERRPR: work_queue failed: %d\n", ret);
+ rtcerr("ERROR: work_queue failed: %d\n", ret);
}
/* Disable any further alarm interrupts */
diff --git a/arch/arm/src/sama5/sam_spi.c b/arch/arm/src/sama5/sam_spi.c
index 2d370fe7a94175451a6f61cf4d598c9e92d360ab..0386fcc6818c28c65642be08bd5f8e69e07cadad 100644
--- a/arch/arm/src/sama5/sam_spi.c
+++ b/arch/arm/src/sama5/sam_spi.c
@@ -90,6 +90,10 @@
# define CONFIG_SAMA5_SPI_DMATHRESHOLD 4
#endif
+#ifndef CONFIG_DEBUG_SPI_INFO
+# undef CONFIG_SAMA5_SPI_REGDEBUG
+#endif
+
#ifdef CONFIG_SAMA5_SPI_DMA
# if defined(CONFIG_SAMA5_SPI0) && defined(CONFIG_SAMA5_DMAC0)
@@ -125,33 +129,12 @@
#define DMA_TIMEOUT_TICKS MSEC2TICK(DMA_TIMEOUT_MS)
/* Debug *******************************************************************/
-/* Check if SPI debut is enabled (non-standard.. no support in
- * include/debug.h
- */
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# undef CONFIG_DEBUG_SPI
-# undef CONFIG_SAMA5_SPI_DMADEBUG
-# undef CONFIG_SAMA5_SPI_REGDEBUG
-#endif
+/* Check if SPI debug is enabled */
#ifndef CONFIG_DEBUG_DMA
# undef CONFIG_SAMA5_SPI_DMADEBUG
#endif
-#ifdef CONFIG_DEBUG_SPI
-# define spidbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define spivdbg lldbg
-# else
-# define spivdbg(x...)
-# endif
-#else
-# define spidbg(x...)
-# define spivdbg(x...)
-#endif
-
#define DMA_INITIAL 0
#define DMA_AFTER_SETUP 1
#define DMA_AFTER_START 2
@@ -243,7 +226,7 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value,
unsigned int offset);
static inline struct sam_spidev_s *spi_device(struct sam_spics_s *spics);
-#if defined(CONFIG_DEBUG_SPI) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_SPI_INFO
static void spi_dumpregs(struct sam_spidev_s *spi, const char *msg);
#else
# define spi_dumpregs(spi,msg)
@@ -430,7 +413,7 @@ static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, uint32_t value,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", spi->ntimes);
+ spiinfo("...[Repeats %d times]...\n", spi->ntimes);
}
/* Save information about the new access */
@@ -464,7 +447,7 @@ static inline uint32_t spi_getreg(struct sam_spidev_s *spi,
#ifdef CONFIG_SAMA5_SPI_REGDEBUG
if (spi_checkreg(spi, false, value, address))
{
- lldbg("%08x->%08x\n", address, value);
+ spiinfo("%08x->%08x\n", address, value);
}
#endif
@@ -487,7 +470,7 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value,
#ifdef CONFIG_SAMA5_SPI_REGDEBUG
if (spi_checkreg(spi, true, value, address))
{
- lldbg("%08x<-%08x\n", address, value);
+ spiinfo("%08x<-%08x\n", address, value);
}
#endif
@@ -509,20 +492,20 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value,
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_SPI) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_SPI_INFO
static void spi_dumpregs(struct sam_spidev_s *spi, const char *msg)
{
- spivdbg("%s:\n", msg);
- spivdbg(" MR:%08x SR:%08x IMR:%08x\n",
+ spiinfo("%s:\n", msg);
+ spiinfo(" MR:%08x SR:%08x IMR:%08x\n",
getreg32(spi->base + SAM_SPI_MR_OFFSET),
getreg32(spi->base + SAM_SPI_SR_OFFSET),
getreg32(spi->base + SAM_SPI_IMR_OFFSET));
- spivdbg(" CSR0:%08x CSR1:%08x CSR2:%08x CSR3:%08x\n",
+ spiinfo(" CSR0:%08x CSR1:%08x CSR2:%08x CSR3:%08x\n",
getreg32(spi->base + SAM_SPI_CSR0_OFFSET),
getreg32(spi->base + SAM_SPI_CSR1_OFFSET),
getreg32(spi->base + SAM_SPI_CSR2_OFFSET),
getreg32(spi->base + SAM_SPI_CSR3_OFFSET));
- spivdbg(" WPCR:%08x WPSR:%08x\n",
+ spiinfo(" WPCR:%08x WPSR:%08x\n",
getreg32(spi->base + SAM_SPI_WPCR_OFFSET),
getreg32(spi->base + SAM_SPI_WPSR_OFFSET));
}
@@ -882,7 +865,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock)
struct sam_spics_s *spics = (struct sam_spics_s *)dev;
struct sam_spidev_s *spi = spi_device(spics);
- spivdbg("lock=%d\n", lock);
+ spiinfo("lock=%d\n", lock);
if (lock)
{
/* Take the semaphore (perhaps waiting) */
@@ -930,10 +913,10 @@ static void spi_select(struct spi_dev_s *dev, enum spi_dev_e devid,
/* Are we selecting or de-selecting the device? */
- spivdbg("selected=%d\n", selected);
+ spiinfo("selected=%d\n", selected);
if (selected)
{
- spivdbg("cs=%d\n", spics->cs);
+ spiinfo("cs=%d\n", spics->cs);
/* Before writing the TDR, the PCS field in the SPI_MR register must be set
* in order to select a slave.
@@ -988,7 +971,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
uint32_t regval;
unsigned int offset;
- spivdbg("cs=%d frequency=%d\n", spics->cs, frequency);
+ spiinfo("cs=%d frequency=%d\n", spics->cs, frequency);
/* Check if the requested frequency is the same as the frequency selection */
@@ -1058,14 +1041,14 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
/* Calculate the new actual frequency */
actual = SAM_SPI_CLOCK / scbr;
- spivdbg("csr[offset=%02x]=%08x actual=%d\n", offset, regval, actual);
+ spiinfo("csr[offset=%02x]=%08x actual=%d\n", offset, regval, actual);
/* Save the frequency setting */
spics->frequency = frequency;
spics->actual = actual;
- spidbg("Frequency %d->%d\n", frequency, actual);
+ spiinfo("Frequency %d->%d\n", frequency, actual);
return actual;
}
@@ -1091,7 +1074,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
uint32_t regval;
unsigned int offset;
- spivdbg("cs=%d mode=%d\n", spics->cs, mode);
+ spiinfo("cs=%d mode=%d\n", spics->cs, mode);
/* Has the mode changed? */
@@ -1134,7 +1117,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
}
spi_putreg(spi, regval, offset);
- spivdbg("csr[offset=%02x]=%08x\n", offset, regval);
+ spiinfo("csr[offset=%02x]=%08x\n", offset, regval);
/* Save the mode so that subsequent re-configurations will be faster */
@@ -1164,7 +1147,7 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
uint32_t regval;
unsigned int offset;
- spivdbg("cs=%d nbits=%d\n", spics->cs, nbits);
+ spiinfo("cs=%d nbits=%d\n", spics->cs, nbits);
DEBUGASSERT(spics && nbits > 7 && nbits < 17);
/* NOTE: The logic in spi_send and in spi_exchange only handles 8-bit
@@ -1186,7 +1169,7 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
regval |= SPI_CSR_BITS(nbits);
spi_putreg(spi, regval, offset);
- spivdbg("csr[offset=%02x]=%08x\n", offset, regval);
+ spiinfo("csr[offset=%02x]=%08x\n", offset, regval);
/* Save the selection so the subsequence re-configurations will be faster */
@@ -1224,7 +1207,7 @@ static uint16_t spi_send(struct spi_dev_s *dev, uint16_t wd)
rxbyte = (uint8_t)0;
spi_exchange(dev, &txbyte, &rxbyte, 1);
- spivdbg("Sent %02x received %02x\n", txbyte, rxbyte);
+ spiinfo("Sent %02x received %02x\n", txbyte, rxbyte);
return (uint16_t)rxbyte;
}
@@ -1270,7 +1253,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
uint32_t pcs;
uint32_t data;
- spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
+ spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
/* Set up PCS bits */
@@ -1390,7 +1373,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
return;
}
- spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
+ spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
spics = (struct sam_spics_s *)dev;
spi = spi_device(spics);
@@ -1476,7 +1459,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
ret = sam_dmarxsetup(spics->rxdma, paddr, maddr, nwords);
if (ret < 0)
{
- dmadbg("ERROR: sam_dmarxsetup failed: %d\n", ret);
+ dmaerr("ERROR: sam_dmarxsetup failed: %d\n", ret);
return;
}
@@ -1488,7 +1471,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
ret = sam_dmatxsetup(spics->txdma, paddr, maddr, nwords);
if (ret < 0)
{
- dmadbg("ERROR: sam_dmatxsetup failed: %d\n", ret);
+ dmaerr("ERROR: sam_dmatxsetup failed: %d\n", ret);
return;
}
@@ -1500,7 +1483,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
ret = sam_dmastart(spics->rxdma, spi_rxcallback, (void *)spics);
if (ret < 0)
{
- dmadbg("ERROR: RX sam_dmastart failed: %d\n", ret);
+ dmaerr("ERROR: RX sam_dmastart failed: %d\n", ret);
return;
}
@@ -1509,7 +1492,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
ret = sam_dmastart(spics->txdma, spi_txcallback, (void *)spics);
if (ret < 0)
{
- dmadbg("ERROR: RX sam_dmastart failed: %d\n", ret);
+ dmaerr("ERROR: RX sam_dmastart failed: %d\n", ret);
sam_dmastop(spics->rxdma);
return;
}
@@ -1531,7 +1514,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
(wdentry_t)spi_dmatimeout, 1, (uint32_t)spics);
if (ret != OK)
{
- spidbg("ERROR: wd_start failed: %d\n", ret);
+ spierr("ERROR: wd_start failed: %d\n", ret);
}
/* Wait for the DMA complete */
@@ -1582,7 +1565,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
if (spics->result)
{
- spidbg("ERROR: DMA failed with result: %d\n", spics->result);
+ spierr("ERROR: DMA failed with result: %d\n", spics->result);
}
}
#endif /* CONFIG_SAMA5_SPI_DMA */
@@ -1673,7 +1656,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
/* The support SAM parts have only a single SPI port */
- spivdbg("port: %d csno: %d spino: %d\n", port, csno, spino);
+ spiinfo("port: %d csno: %d spino: %d\n", port, csno, spino);
DEBUGASSERT(csno >= 0 && csno <= SAM_SPI_NCS);
#if defined(CONFIG_SAMA5_SPI0) && defined(CONFIG_SAMA5_SPI1)
@@ -1692,7 +1675,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
spics = (struct sam_spics_s *)zalloc(sizeof(struct sam_spics_s));
if (!spics)
{
- spidbg("ERROR: Failed to allocate a chip select structure\n");
+ spierr("ERROR: Failed to allocate a chip select structure\n");
return NULL;
}
@@ -1715,7 +1698,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
spics->rxdma = sam_dmachannel(spino, 0);
if (!spics->rxdma)
{
- spidbg("ERROR: Failed to allocate the RX DMA channel\n");
+ spierr("ERROR: Failed to allocate the RX DMA channel\n");
spics->candma = false;
}
}
@@ -1725,7 +1708,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
spics->txdma = sam_dmachannel(spino, 0);
if (!spics->txdma)
{
- spidbg("ERROR: Failed to allocate the TX DMA channel\n");
+ spierr("ERROR: Failed to allocate the TX DMA channel\n");
sam_dmafree(spics->rxdma);
spics->rxdma = NULL;
spics->candma = false;
@@ -1852,7 +1835,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
spi_putreg(spi, regval, offset);
spics->nbits = 8;
- spivdbg("csr[offset=%02x]=%08x\n", offset, regval);
+ spiinfo("csr[offset=%02x]=%08x\n", offset, regval);
return &spics->spidev;
}
diff --git a/arch/arm/src/sama5/sam_ssc.c b/arch/arm/src/sama5/sam_ssc.c
index 52aac74b17d7d96efb53a35814c04000b94527d8..8e4e66a03272ccbd8b076de16787f4f286b75cba 100644
--- a/arch/arm/src/sama5/sam_ssc.c
+++ b/arch/arm/src/sama5/sam_ssc.c
@@ -397,12 +397,7 @@
* include/debug.h
*/
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# undef CONFIG_DEBUG_I2S
-#endif
-
-#ifndef CONFIG_DEBUG_I2S
+#ifndef CONFIG_DEBUG_I2S_INFO
# undef CONFIG_SAMA5_SSC_DMADEBUG
# undef CONFIG_SAMA5_SSC_REGDEBUG
# undef CONFIG_SAMA5_SSC_QDEBUG
@@ -413,22 +408,6 @@
# undef CONFIG_SAMA5_SSC_DMADEBUG
#endif
-#ifdef CONFIG_DEBUG_I2S
-# define i2sdbg dbg
-# define i2slldbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define i2svdbg dbg
-# define i2sllvdbg lldbg
-# else
-# define i2svdbg(x...)
-# endif
-#else
-# define i2sdbg(x...)
-# define i2slldbg(x...)
-# define i2svdbg(x...)
-# define i2sllvdbg(x...)
-#endif
-
#define DMA_INITIAL 0
#define DMA_AFTER_SETUP 1
#define DMA_AFTER_START 2
@@ -476,7 +455,7 @@ struct sam_ssc_s
uintptr_t base; /* SSC controller register base address */
sem_t exclsem; /* Assures mutually exclusive acess to SSC */
uint8_t datalen; /* Data width (8, 16, or 32) */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
uint8_t align; /* Log2 of data width (0, 1, or 3) */
#endif
uint8_t pid; /* Peripheral ID */
@@ -539,7 +518,7 @@ static inline void ssc_putreg(struct sam_ssc_s *priv, unsigned int offset,
static inline uintptr_t ssc_physregaddr(struct sam_ssc_s *priv,
unsigned int offset);
-#if defined(CONFIG_DEBUG_I2S) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_I2S_INFO
static void scc_dump_regs(struct sam_ssc_s *priv, const char *msg);
#else
# define scc_dump_regs(s,m)
@@ -724,7 +703,7 @@ static bool ssc_checkreg(struct sam_ssc_s *priv, bool wr, uint32_t regval,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", priv->count);
+ i2sinfo("...[Repeats %d times]...\n", priv->count);
}
/* Save information about the new access */
@@ -758,7 +737,7 @@ static inline uint32_t ssc_getreg(struct sam_ssc_s *priv,
#ifdef CONFIG_SAMA5_SSC_REGDEBUG
if (ssc_checkreg(priv, false, regval, regaddr))
{
- lldbg("%08x->%08x\n", regaddr, regval);
+ i2sinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@@ -781,7 +760,7 @@ static inline void ssc_putreg(struct sam_ssc_s *priv, unsigned int offset,
#ifdef CONFIG_SAMA5_SSC_REGDEBUG
if (ssc_checkreg(priv, true, regval, regaddr))
{
- lldbg("%08x<-%08x\n", regaddr, regval);
+ i2sinfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@@ -817,21 +796,21 @@ static inline uintptr_t ssc_physregaddr(struct sam_ssc_s *priv,
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_I2S) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_I2S_INFO
static void scc_dump_regs(struct sam_ssc_s *priv, const char *msg)
{
- i2svdbg("SSC%d: %s\n", priv->sscno, msg);
- i2svdbg(" CMR:%08x RCMR:%08x RFMR:%08x TCMR:%08x\n",
+ i2sinfo("SSC%d: %s\n", priv->sscno, msg);
+ i2sinfo(" CMR:%08x RCMR:%08x RFMR:%08x TCMR:%08x\n",
getreg32(priv->base + SAM_SSC_CMR_OFFSET),
getreg32(priv->base + SAM_SSC_RCMR_OFFSET),
getreg32(priv->base + SAM_SSC_RFMR_OFFSET),
getreg32(priv->base + SAM_SSC_TCMR_OFFSET));
- i2svdbg(" TFMR:%08x RC0R:%08x RC1R:%08x SR:%08x\n",
+ i2sinfo(" TFMR:%08x RC0R:%08x RC1R:%08x SR:%08x\n",
getreg32(priv->base + SAM_SSC_TFMR_OFFSET),
getreg32(priv->base + SAM_SSC_RC0R_OFFSET),
getreg32(priv->base + SAM_SSC_RC1R_OFFSET),
getreg32(priv->base + SAM_SSC_SR_OFFSET));
- i2svdbg(" IMR:%08x WPMR:%08x WPSR:%08x\n",
+ i2sinfo(" IMR:%08x WPMR:%08x WPSR:%08x\n",
getreg32(priv->base + SAM_SSC_IMR_OFFSET),
getreg32(priv->base + SAM_SSC_WPMR_OFFSET),
getreg32(priv->base + SAM_SSC_WPSR_OFFSET));
@@ -868,12 +847,12 @@ static void ssc_dump_queue(sq_queue_t *queue)
if (!apb)
{
- i2sllvdbg(" %p: No buffer\n", bfcontainer);
+ i2sinfo(" %p: No buffer\n", bfcontainer);
}
else
{
- i2sllvdbg(" %p: buffer=%p nmaxbytes=%d nbytes=%d\n",
- bfcontainer, apb, apb->nmaxbytes, apb->nbytes);
+ i2sinfo(" %p: buffer=%p nmaxbytes=%d nbytes=%d\n",
+ bfcontainer, apb, apb->nmaxbytes, apb->nbytes);
}
}
}
@@ -883,12 +862,12 @@ static void ssc_dump_queues(struct sam_transport_s *xpt, const char *msg)
irqstate_t flags;
flags = enter_critical_section();
- i2sllvdbg("%s\n", msg);
- i2sllvdbg(" Pending:\n");
+ i2sinfo("%s\n", msg);
+ i2sinfo(" Pending:\n");
ssc_dump_queue(&xpt->pend);
- i2sllvdbg(" Active:\n");
+ i2sinfo(" Active:\n");
ssc_dump_queue(&xpt->act);
- i2sllvdbg(" Done:\n");
+ i2sinfo(" Done:\n");
ssc_dump_queue(&xpt->done);
leave_critical_section(flags);
}
@@ -1111,7 +1090,7 @@ static void ssc_dma_sampleinit(struct sam_ssc_s *priv,
#if defined(CONFIG_SAMA5_SSC_DMADEBUG) && defined(SSC_HAVE_RX)
static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result)
{
- lldbg("result: %d\n", result);
+ i2sinfo("result: %d\n", result);
/* Sample the final registers */
@@ -1176,7 +1155,7 @@ static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result)
#if defined(CONFIG_SAMA5_SSC_DMADEBUG) && defined(SSC_HAVE_TX)
static void ssc_txdma_sampledone(struct sam_ssc_s *priv, int result)
{
- lldbg("result: %d\n", result);
+ i2sinfo("result: %d\n", result);
/* Sample the final registers */
@@ -1398,7 +1377,7 @@ static int ssc_rxdma_setup(struct sam_ssc_s *priv)
if (ret < 0)
{
- i2slldbg("ERROR: wd_start failed: %d\n", errno);
+ i2serr("ERROR: wd_start failed: %d\n", errno);
}
}
@@ -1447,7 +1426,7 @@ static void ssc_rx_worker(void *arg)
* So we have to start the next DMA here.
*/
- i2svdbg("rx.act.head=%p rx.done.head=%p\n",
+ i2sinfo("rx.act.head=%p rx.done.head=%p\n",
priv->rx.act.head, priv->rx.done.head);
ssc_dump_rxqueues(priv, "RX worker start");
@@ -1586,7 +1565,7 @@ static void ssc_rx_schedule(struct sam_ssc_s *priv, int result)
ret = work_queue(HPWORK, &priv->rx.work, ssc_rx_worker, priv, 0);
if (ret != 0)
{
- i2slldbg("ERROR: Failed to queue RX work: %d\n", ret);
+ i2serr("ERROR: Failed to queue RX work: %d\n", ret);
}
}
}
@@ -1811,7 +1790,7 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv)
if (ret < 0)
{
- i2slldbg("ERROR: wd_start failed: %d\n", errno);
+ i2serr("ERROR: wd_start failed: %d\n", errno);
}
}
@@ -1859,7 +1838,7 @@ static void ssc_tx_worker(void *arg)
* So we have to start the next DMA here.
*/
- i2svdbg("tx.act.head=%p tx.done.head=%p\n",
+ i2sinfo("tx.act.head=%p tx.done.head=%p\n",
priv->tx.act.head, priv->tx.done.head);
ssc_dump_txqueues(priv, "TX worker start");
@@ -1986,7 +1965,7 @@ static void ssc_tx_schedule(struct sam_ssc_s *priv, int result)
ret = work_queue(HPWORK, &priv->tx.work, ssc_tx_worker, priv, 0);
if (ret != 0)
{
- i2slldbg("ERROR: Failed to queue TX work: %d\n", ret);
+ i2serr("ERROR: Failed to queue TX work: %d\n", ret);
}
}
}
@@ -2059,25 +2038,25 @@ static int ssc_checkwidth(struct sam_ssc_s *priv, int bits)
switch (bits)
{
case 8:
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
priv->align = 0;
#endif
break;
case 16:
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
priv->align = 1;
#endif
break;
case 32:
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
priv->align = 3;
#endif
break;
default:
- i2sdbg("ERROR: Unsupported or invalid data width: %d\n", bits);
+ i2serr("ERROR: Unsupported or invalid data width: %d\n", bits);
return (bits < 2 || bits > 32) ? -EINVAL : -ENOSYS;
}
@@ -2155,7 +2134,7 @@ static uint32_t ssc_rxdatawidth(struct i2s_dev_s *dev, int bits)
ret = ssc_checkwidth(priv, bits);
if (ret < 0)
{
- i2sdbg("ERROR: ssc_checkwidth failed: %d\n", ret);
+ i2serr("ERROR: ssc_checkwidth failed: %d\n", ret);
return 0;
}
@@ -2164,7 +2143,7 @@ static uint32_t ssc_rxdatawidth(struct i2s_dev_s *dev, int bits)
ret = ssc_dma_flags(priv, &dmaflags);
if (ret < 0)
{
- i2sdbg("ERROR: ssc_dma_flags failed: %d\n", ret);
+ i2serr("ERROR: ssc_dma_flags failed: %d\n", ret);
return 0;
}
@@ -2234,7 +2213,7 @@ static int ssc_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb,
#endif
DEBUGASSERT(priv && apb && ((uintptr_t)apb->samp & priv->align) == 0);
- i2svdbg("apb=%p nmaxbytes=%d arg=%p timeout=%d\n",
+ i2sinfo("apb=%p nmaxbytes=%d arg=%p timeout=%d\n",
apb, apb->nmaxbytes, arg, timeout);
ssc_init_buffer(apb->samp, apb->nmaxbytes);
@@ -2253,7 +2232,7 @@ static int ssc_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb,
if (!priv->rxenab)
{
- i2sdbg("ERROR: SSC%d has no receiver\n", priv->sscno);
+ i2serr("ERROR: SSC%d has no receiver\n", priv->sscno);
ret = -EAGAIN;
goto errout_with_exclsem;
}
@@ -2292,7 +2271,7 @@ errout_with_exclsem:
return ret;
#else
- i2sdbg("ERROR: SSC%d has no receiver\n", priv->sscno);
+ i2serr("ERROR: SSC%d has no receiver\n", priv->sscno);
UNUSED(priv);
return -ENOSYS;
#endif
@@ -2366,7 +2345,7 @@ static uint32_t ssc_txdatawidth(struct i2s_dev_s *dev, int bits)
ret = ssc_checkwidth(priv, bits);
if (ret < 0)
{
- i2sdbg("ERROR: ssc_checkwidth failed: %d\n", ret);
+ i2serr("ERROR: ssc_checkwidth failed: %d\n", ret);
return 0;
}
@@ -2375,7 +2354,7 @@ static uint32_t ssc_txdatawidth(struct i2s_dev_s *dev, int bits)
ret = ssc_dma_flags(priv, &dmaflags);
if (ret < 0)
{
- i2sdbg("ERROR: ssc_dma_flags failed: %d\n", ret);
+ i2serr("ERROR: ssc_dma_flags failed: %d\n", ret);
return 0;
}
@@ -2449,7 +2428,7 @@ static int ssc_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb,
*/
DEBUGASSERT(priv && apb);
- i2svdbg("apb=%p nbytes=%d arg=%p timeout=%d\n",
+ i2sinfo("apb=%p nbytes=%d arg=%p timeout=%d\n",
apb, apb->nbytes - apb->curbyte, arg, timeout);
ssc_dump_buffer("Sending", &apb->samp[apb->curbyte],
@@ -2470,7 +2449,7 @@ static int ssc_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb,
if (!priv->txenab)
{
- i2sdbg("ERROR: SSC%d has no transmitter\n", priv->sscno);
+ i2serr("ERROR: SSC%d has no transmitter\n", priv->sscno);
ret = -EAGAIN;
goto errout_with_exclsem;
}
@@ -2509,7 +2488,7 @@ errout_with_exclsem:
return ret;
#else
- i2sdbg("ERROR: SSC%d has no transmitter\n", priv->sscno);
+ i2serr("ERROR: SSC%d has no transmitter\n", priv->sscno);
UNUSED(priv);
return -ENOSYS;
#endif
@@ -2563,7 +2542,7 @@ static int ssc_rx_configure(struct sam_ssc_s *priv)
case SSC_CLKSRC_NONE: /* No clock */
default:
- i2sdbg("ERROR: No receiver clock\n");
+ i2serr("ERROR: No receiver clock\n");
return -EINVAL;
}
@@ -2584,7 +2563,7 @@ static int ssc_rx_configure(struct sam_ssc_s *priv)
break;
default:
- i2sdbg("ERROR: Invalid clock output selection\n");
+ i2serr("ERROR: Invalid clock output selection\n");
return -EINVAL;
}
@@ -2688,7 +2667,7 @@ static int ssc_tx_configure(struct sam_ssc_s *priv)
case SSC_CLKSRC_NONE: /* No clock */
default:
- i2sdbg("ERROR: No transmitter clock\n");
+ i2serr("ERROR: No transmitter clock\n");
return -EINVAL;
}
@@ -2709,7 +2688,7 @@ static int ssc_tx_configure(struct sam_ssc_s *priv)
break;
default:
- i2sdbg("ERROR: Invalid clock output selection\n");
+ i2serr("ERROR: Invalid clock output selection\n");
return -EINVAL;
}
@@ -2929,7 +2908,7 @@ static void ssc_clocking(struct sam_ssc_s *priv)
sam_enableperiph1(priv->pid);
- i2svdbg("PCSR1=%08x PCR=%08x CMR=%08x\n",
+ i2sinfo("PCSR1=%08x PCR=%08x CMR=%08x\n",
getreg32(SAM_PMC_PCSR1), regval,
ssc_getreg(priv, SAM_SSC_CMR_OFFSET));
}
@@ -2968,7 +2947,7 @@ static int ssc_dma_flags(struct sam_ssc_s *priv, uint32_t *dmaflags)
break;
default:
- i2sdbg("ERROR: Unsupported data width: %d\n", priv->datalen);
+ i2serr("ERROR: Unsupported data width: %d\n", priv->datalen);
return -ENOSYS;
}
@@ -3001,7 +2980,7 @@ static int ssc_dma_allocate(struct sam_ssc_s *priv)
ret = ssc_dma_flags(priv, &dmaflags);
if (ret < 0)
{
- i2sdbg("ERROR: ssc_dma_flags failed: %d\n", ret);
+ i2serr("ERROR: ssc_dma_flags failed: %d\n", ret);
return ret;
}
@@ -3018,7 +2997,7 @@ static int ssc_dma_allocate(struct sam_ssc_s *priv)
priv->rx.dma = sam_dmachannel(priv->sscno, dmaflags);
if (!priv->rx.dma)
{
- i2sdbg("ERROR: Failed to allocate the RX DMA channel\n");
+ i2serr("ERROR: Failed to allocate the RX DMA channel\n");
goto errout;
}
@@ -3027,7 +3006,7 @@ static int ssc_dma_allocate(struct sam_ssc_s *priv)
priv->rx.dog = wd_create();
if (!priv->rx.dog)
{
- i2sdbg("ERROR: Failed to create the RX DMA watchdog\n");
+ i2serr("ERROR: Failed to create the RX DMA watchdog\n");
goto errout;
}
}
@@ -3041,7 +3020,7 @@ static int ssc_dma_allocate(struct sam_ssc_s *priv)
priv->tx.dma = sam_dmachannel(priv->sscno, dmaflags);
if (!priv->tx.dma)
{
- i2sdbg("ERROR: Failed to allocate the TX DMA channel\n");
+ i2serr("ERROR: Failed to allocate the TX DMA channel\n");
goto errout;
}
@@ -3050,7 +3029,7 @@ static int ssc_dma_allocate(struct sam_ssc_s *priv)
priv->tx.dog = wd_create();
if (!priv->tx.dog)
{
- i2sdbg("ERROR: Failed to create the TX DMA watchdog\n");
+ i2serr("ERROR: Failed to create the TX DMA watchdog\n");
goto errout;
}
}
@@ -3257,7 +3236,7 @@ static void ssc0_configure(struct sam_ssc_s *priv)
priv->base = SAM_SSC0_VBASE;
priv->datalen = CONFIG_SAMA5_SSC0_DATALEN;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
priv->align = SAMA5_SSC0_DATAMASK;
#endif
priv->pid = SAM_PID_SSC0;
@@ -3398,7 +3377,7 @@ static void ssc1_configure(struct sam_ssc_s *priv)
priv->base = SAM_SSC1_VBASE;
priv->datalen = CONFIG_SAMA5_SSC1_DATALEN;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
priv->align = SAMA5_SSC1_DATAMASK;
#endif
priv->pid = SAM_PID_SSC1;
@@ -3431,7 +3410,7 @@ struct i2s_dev_s *sam_ssc_initialize(int port)
/* The support SAM parts have only a single SSC port */
- i2svdbg("port: %d\n", port);
+ i2sinfo("port: %d\n", port);
/* Allocate a new state structure for this chip select. NOTE that there
* is no protection if the same chip select is used in two different
@@ -3441,7 +3420,7 @@ struct i2s_dev_s *sam_ssc_initialize(int port)
priv = (struct sam_ssc_s *)zalloc(sizeof(struct sam_ssc_s));
if (!priv)
{
- i2sdbg("ERROR: Failed to allocate a chip select structure\n");
+ i2serr("ERROR: Failed to allocate a chip select structure\n");
return NULL;
}
@@ -3475,7 +3454,7 @@ struct i2s_dev_s *sam_ssc_initialize(int port)
else
#endif /* CONFIG_SAMA5_SSC1 */
{
- i2sdbg("ERROR: Unsupported I2S port: %d\n", port);
+ i2serr("ERROR: Unsupported I2S port: %d\n", port);
goto errout_with_alloc;
}
@@ -3496,7 +3475,7 @@ struct i2s_dev_s *sam_ssc_initialize(int port)
ret = ssc_rx_configure(priv);
if (ret < 0)
{
- i2sdbg("ERROR: Failed to configure the receiver: %d\n", ret);
+ i2serr("ERROR: Failed to configure the receiver: %d\n", ret);
goto errout_with_clocking;
}
@@ -3505,7 +3484,7 @@ struct i2s_dev_s *sam_ssc_initialize(int port)
ret = ssc_tx_configure(priv);
if (ret < 0)
{
- i2sdbg("ERROR: Failed to configure the transmitter: %d\n", ret);
+ i2serr("ERROR: Failed to configure the transmitter: %d\n", ret);
goto errout_with_clocking;
}
diff --git a/arch/arm/src/sama5/sam_tc.c b/arch/arm/src/sama5/sam_tc.c
index 54cf71242c3205afb57c264d3779d9cf94fb3cfe..7d8e19370cc64d87d4d653ade7d888d60055ffcd 100644
--- a/arch/arm/src/sama5/sam_tc.c
+++ b/arch/arm/src/sama5/sam_tc.c
@@ -75,6 +75,10 @@
* Pre-processor Definitions
****************************************************************************/
+#ifndef CONFIG_DEBUG_TIMER_INFO
+# undef CONFIG_SAMA5_TC_REGDEBUG
+#endif
+
/****************************************************************************
* Private Types
****************************************************************************/
@@ -501,20 +505,20 @@ static void sam_regdump(struct sam_chan_s *chan, const char *msg)
uintptr_t base;
base = tc->base;
- lldbg("TC%d [%08x]: %s\n", tc->tc, (int)base, msg);
- lldbg(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n",
+ tminfo("TC%d [%08x]: %s\n", tc->tc, (int)base, msg);
+ tminfo(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n",
getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET),
getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET));
base = chan->base;
- lldbg("TC%d Channel %d [%08x]: %s\n", tc->tc, chan->chan, (int)base, msg);
- lldbg(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n",
+ tminfo("TC%d Channel %d [%08x]: %s\n", tc->tc, chan->chan, (int)base, msg);
+ tminfo(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n",
getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET),
getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET));
- lldbg(" RA: %08x RB: %08x RC: %08x SR: %08x\n",
+ tminfo(" RA: %08x RB: %08x RC: %08x SR: %08x\n",
getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET),
getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_SR_OFFSET));
- lldbg(" IMR: %08x\n",
+ tminfo(" IMR: %08x\n",
getreg32(base+SAM_TC_IMR_OFFSET));
}
#endif
@@ -558,7 +562,7 @@ static bool sam_checkreg(struct sam_tc_s *tc, bool wr, uint32_t regaddr,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", tc->ntimes);
+ tmrinfo("...[Repeats %d times]...\n", tc->ntimes);
}
/* Save information about the new access */
@@ -593,7 +597,7 @@ static inline uint32_t sam_tc_getreg(struct sam_chan_s *chan,
#ifdef CONFIG_SAMA5_TC_REGDEBUG
if (sam_checkreg(tc, false, regaddr, regval))
{
- lldbg("%08x->%08x\n", regaddr, regval);
+ tmrinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@@ -617,7 +621,7 @@ static inline void sam_tc_putreg(struct sam_chan_s *chan, uint32_t regval,
#ifdef CONFIG_SAMA5_TC_REGDEBUG
if (sam_checkreg(tc, true, regaddr, regval))
{
- lldbg("%08x<-%08x\n", regaddr, regval);
+ tmrinfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@@ -641,7 +645,7 @@ static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan,
#ifdef CONFIG_SAMA5_TC_REGDEBUG
if (sam_checkreg(chan->tc, false, regaddr, regval))
{
- lldbg("%08x->%08x\n", regaddr, regval);
+ tmrinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@@ -664,7 +668,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset,
#ifdef CONFIG_SAMA5_TC_REGDEBUG
if (sam_checkreg(chan->tc, true, regaddr, regval))
{
- lldbg("%08x<-%08x\n", regaddr, regval);
+ tmrinfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@@ -953,7 +957,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel)
{
/* Timer/counter is not invalid or not enabled */
- tcdbg("ERROR: Bad channel number: %d\n", channel);
+ tmrerr("ERROR: Bad channel number: %d\n", channel);
return NULL;
}
@@ -976,7 +980,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel)
for (i = 0, ch = tcconfig->chfirst; i < SAM_TC_NCHANNELS; i++)
{
- tcdbg("Initializing TC%d channel %d\n", tcconfig->tc, ch);
+ tmrerr("ERROR: Initializing TC%d channel %d\n", tcconfig->tc, ch);
/* Initialize the channel data structure */
@@ -1057,7 +1061,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel)
{
/* No.. return a failure */
- tcdbg("Channel %d is in-used\n", channel);
+ tmrerr("ERROR: Channel %d is in-use\n", channel);
sam_givesem(tc);
return NULL;
}
@@ -1102,7 +1106,7 @@ TC_HANDLE sam_tc_allocate(int channel, int mode)
* access to the requested channel.
*/
- tcvdbg("channel=%d mode=%08x\n", channel, mode);
+ tmrinfo("channel=%d mode=%08x\n", channel, mode);
chan = sam_tc_initialize(channel);
if (chan)
@@ -1128,7 +1132,7 @@ TC_HANDLE sam_tc_allocate(int channel, int mode)
/* Return an opaque reference to the channel */
- tcvdbg("Returning %p\n", chan);
+ tmrinfo("Returning %p\n", chan);
return (TC_HANDLE)chan;
}
@@ -1150,7 +1154,7 @@ void sam_tc_free(TC_HANDLE handle)
{
struct sam_chan_s *chan = (struct sam_chan_s *)handle;
- tcvdbg("Freeing %p channel=%d inuse=%d\n", chan, chan->chan, chan->inuse);
+ tmrinfo("Freeing %p channel=%d inuse=%d\n", chan, chan->chan, chan->inuse);
DEBUGASSERT(chan && chan->inuse);
/* Make sure that interrupts are detached and disabled and that the channel
@@ -1183,7 +1187,7 @@ void sam_tc_start(TC_HANDLE handle)
{
struct sam_chan_s *chan = (struct sam_chan_s *)handle;
- tcvdbg("Starting channel %d inuse=%d\n", chan->chan, chan->inuse);
+ tmrinfo("Starting channel %d inuse=%d\n", chan->chan, chan->inuse);
DEBUGASSERT(chan && chan->inuse);
/* Read the SR to clear any pending interrupts on this channel */
@@ -1215,7 +1219,7 @@ void sam_tc_stop(TC_HANDLE handle)
{
struct sam_chan_s *chan = (struct sam_chan_s *)handle;
- tcvdbg("Stopping channel %d inuse=%d\n", chan->chan, chan->inuse);
+ tmrinfo("Stopping channel %d inuse=%d\n", chan->chan, chan->inuse);
DEBUGASSERT(chan && chan->inuse);
sam_chan_putreg(chan, SAM_TC_CCR_OFFSET, TC_CCR_CLKDIS);
@@ -1322,8 +1326,8 @@ void sam_tc_setregister(TC_HANDLE handle, int regid, uint32_t regval)
DEBUGASSERT(chan && regid < TC_NREGISTERS);
- tcvdbg("Channel %d: Set register RC%d to %08lx\n",
- chan->chan, regid, (unsigned long)regval);
+ tmrinfo("Channel %d: Set register RC%d to %08lx\n",
+ chan->chan, regid, (unsigned long)regval);
sam_chan_putreg(chan, g_regoffset[regid], regval);
sam_regdump(chan, "Set register");
@@ -1465,7 +1469,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks)
uint32_t ftcin = sam_tc_infreq();
int ndx = 0;
- tcvdbg("frequency=%d\n", frequency);
+ tmrinfo("frequency=%d\n", frequency);
/* Satisfy lower bound. That is, the value of the divider such that:
*
@@ -1478,7 +1482,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks)
{
/* If no divisor can be found, return -ERANGE */
- tcdbg("Lower bound search failed\n");
+ tmrerr("ERROR: Lower bound search failed\n");
return -ERANGE;
}
}
@@ -1502,7 +1506,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks)
if (div)
{
uint32_t value = sam_tc_freqdiv_lookup(ftcin, ndx);
- tcvdbg("return div=%lu\n", (unsigned long)value);
+ tmrinfo("return div=%lu\n", (unsigned long)value);
*div = value;
}
@@ -1510,7 +1514,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks)
if (tcclks)
{
- tcvdbg("return tcclks=%08lx\n", (unsigned long)TC_CMR_TCCLKS(ndx));
+ tmrinfo("return tcclks=%08lx\n", (unsigned long)TC_CMR_TCCLKS(ndx));
*tcclks = TC_CMR_TCCLKS(ndx);
}
diff --git a/arch/arm/src/sama5/sam_tc.h b/arch/arm/src/sama5/sam_tc.h
index 311f6d329f2d459a15c7e69c4764bc758bbc3fbf..4cf53f9cc801fb86d767bf1c127948a538cd8c79 100644
--- a/arch/arm/src/sama5/sam_tc.h
+++ b/arch/arm/src/sama5/sam_tc.h
@@ -74,8 +74,7 @@
/* Timer debug is enabled if any timer client is enabled */
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_ANALOG
+#ifndef CONFIG_DEBUG_TIMER_INFO
# undef CONFIG_SAMA5_TC_REGDEBUG
#endif
@@ -83,20 +82,6 @@
# define CONFIG_SAMA5_TC_DEBUG 1
#endif
-/* Timer/counter debug output */
-
-#ifdef CONFIG_SAMA5_TC_DEBUG
-# define tcdbg dbg
-# define tcvdbg vdbg
-# define tclldbg lldbg
-# define tcllvdbg llvdbg
-#else
-# define tcdbg(x...)
-# define tcvdbg(x...)
-# define tclldbg(x...)
-# define tcllvdbg(x...)
-#endif
-
/****************************************************************************
* Public Types
****************************************************************************/
diff --git a/arch/arm/src/sama5/sam_tickless.c b/arch/arm/src/sama5/sam_tickless.c
index 70cecb1217a24f80f2c51579f16b1d9c6518663c..4ae30bf7185d09d66a9fac4afa4fd437b1f4637c 100644
--- a/arch/arm/src/sama5/sam_tickless.c
+++ b/arch/arm/src/sama5/sam_tickless.c
@@ -209,7 +209,7 @@ static struct sam_tickless_s g_tickless;
static void sam_oneshot_handler(void *arg)
{
- tcllvdbg("Expired...\n");
+ tmrinfo("Expired...\n");
sched_timer_expiration();
}
@@ -256,7 +256,7 @@ void up_timer_initialize(void)
CONFIG_USEC_PER_TICK);
if (ret < 0)
{
- tclldbg("ERROR: sam_oneshot_initialize failed\n");
+ tmrerr("ERROR: sam_oneshot_initialize failed\n");
PANIC();
}
@@ -268,7 +268,7 @@ void up_timer_initialize(void)
ret = sam_oneshot_max_delay(&g_tickless.oneshot, &max_delay);
if (ret < 0)
{
- tclldbg("ERROR: sam_oneshot_max_delay failed\n");
+ tmrerr("ERROR: sam_oneshot_max_delay failed\n");
PANIC();
}
@@ -292,7 +292,7 @@ void up_timer_initialize(void)
CONFIG_USEC_PER_TICK);
if (ret < 0)
{
- tclldbg("ERROR: sam_freerun_initialize failed\n");
+ tmrerr("ERROR: sam_freerun_initialize failed\n");
PANIC();
}
diff --git a/arch/arm/src/sama5/sam_trng.c b/arch/arm/src/sama5/sam_trng.c
index 1be5585bc4ba8f2eb22a1c90a58c59edb5e61f0e..a3eb102640e8fa881e727640623deaa61bc5884a 100644
--- a/arch/arm/src/sama5/sam_trng.c
+++ b/arch/arm/src/sama5/sam_trng.c
@@ -243,7 +243,7 @@ static ssize_t sam_read(struct file *filep, char *buffer, size_t buflen)
ssize_t retval;
int ret;
- fvdbg("buffer=%p buflen=%d\n", buffer, (int)buflen);
+ finfo("buffer=%p buflen=%d\n", buffer, (int)buflen);
/* Get exclusive access to the TRNG harware */
@@ -283,7 +283,7 @@ static ssize_t sam_read(struct file *filep, char *buffer, size_t buflen)
{
ret = sem_wait(&g_trngdev.waitsem);
- fvdbg("Awakened: nsamples=%d maxsamples=%d ret=%d\n",
+ finfo("Awakened: nsamples=%d maxsamples=%d ret=%d\n",
g_trngdev.nsamples, g_trngdev.maxsamples, ret);
if (ret < 0)
@@ -320,7 +320,7 @@ errout:
sem_post(&g_trngdev.exclsem);
- fvdbg("Return %d\n", (int)retval);
+ finfo("Return %d\n", (int)retval);
return retval;
}
@@ -346,7 +346,7 @@ void up_rnginitialize(void)
{
int ret;
- fvdbg("Initializing TRNG hardware\n");
+ finfo("Initializing TRNG hardware\n");
/* Initialize the device structure */
@@ -362,7 +362,7 @@ void up_rnginitialize(void)
if (irq_attach(SAM_IRQ_TRNG, sam_interrupt))
{
- fdbg("ERROR: Failed to attach to IRQ%d\n", SAM_IRQ_TRNG);
+ ferr("ERROR: Failed to attach to IRQ%d\n", SAM_IRQ_TRNG);
return;
}
@@ -379,7 +379,7 @@ void up_rnginitialize(void)
ret = register_driver("/dev/random", &g_trngops, 0644, NULL);
if (ret < 0)
{
- fdbg("ERROR: Failed to register /dev/random\n");
+ ferr("ERROR: Failed to register /dev/random\n");
return;
}
diff --git a/arch/arm/src/sama5/sam_tsd.c b/arch/arm/src/sama5/sam_tsd.c
index 3bed567508bc02d54d2d4394da586eb8c1988697..edb2199f36ce063615c19bad421beb9d89a390ce 100644
--- a/arch/arm/src/sama5/sam_tsd.c
+++ b/arch/arm/src/sama5/sam_tsd.c
@@ -285,7 +285,7 @@ static void sam_tsd_notify(struct sam_tsd_s *priv)
if (fds)
{
fds->revents |= POLLIN;
- ivdbg("Report events: %02x\n", fds->revents);
+ iinfo("Report events: %02x\n", fds->revents);
sem_post(fds->sem);
}
}
@@ -380,7 +380,7 @@ static int sam_tsd_waitsample(struct sam_tsd_s *priv, struct sam_sample_s *sampl
{
/* Wait for a sample data */
- ivdbg("Waiting..\n");
+ iinfo("Waiting..\n");
priv->nwaiters++;
ret = sem_wait(&priv->waitsem);
priv->nwaiters--;
@@ -391,14 +391,14 @@ static int sam_tsd_waitsample(struct sam_tsd_s *priv, struct sam_sample_s *sampl
* the failure now.
*/
- idbg("ERROR: sem_wait: %d\n", errno);
+ ierr("ERROR: sem_wait: %d\n", errno);
DEBUGASSERT(errno == EINTR);
ret = -EINTR;
goto errout;
}
}
- ivdbg("Sampled\n");
+ iinfo("Sampled\n");
/* Re-acquire the semaphore that manages mutually exclusive access to
* the device structure. We may have to wait here. But we have our sample.
@@ -538,7 +538,7 @@ static void sam_tsd_bottomhalf(void *arg)
/* Handle the change from pen down to pen up */
- ivdbg("pending: %08x pendown: %d contact: %d\n",
+ iinfo("pending: %08x pendown: %d contact: %d\n",
pending, pendown, priv->sample.contact);
if (!pendown)
@@ -644,7 +644,7 @@ static void sam_tsd_bottomhalf(void *arg)
if (xraw == 0 || xraw >= xscale || yraw == 0 || yraw > yscale)
{
- idbg("Discarding: x %d:%d y %d:%d\n", xraw, xscale);
+ iwarn("WARNING: Discarding: x %d:%d y %d:%d\n", xraw, xscale);
goto ignored;
}
@@ -799,7 +799,7 @@ static int sam_tsd_schedule(struct sam_tsd_s *priv)
ret = work_queue(HPWORK, &priv->work, sam_tsd_bottomhalf, priv, 0);
if (ret != 0)
{
- illdbg("Failed to queue work: %d\n", ret);
+ ierr("ERROR: Failed to queue work: %d\n", ret);
}
return OK;
@@ -834,7 +834,7 @@ static int sam_tsd_open(struct file *filep)
uint8_t tmp;
int ret;
- ivdbg("crefs: %d\n", priv->crefs);
+ iinfo("crefs: %d\n", priv->crefs);
/* Get exclusive access to the device structures */
@@ -883,7 +883,7 @@ static int sam_tsd_close(struct file *filep)
FAR struct inode *inode = filep->f_inode;
FAR struct sam_tsd_s *priv = inode->i_private;
- ivdbg("crefs: %d\n", priv->crefs);
+ iinfo("crefs: %d\n", priv->crefs);
/* Get exclusive access to the ADC device */
@@ -919,7 +919,7 @@ static ssize_t sam_tsd_read(struct file *filep, char *buffer, size_t len)
struct sam_sample_s sample;
int ret;
- ivdbg("buffer:%p len:%d\n", buffer, len);
+ iinfo("buffer:%p len:%d\n", buffer, len);
DEBUGASSERT(filep);
inode = filep->f_inode;
@@ -936,7 +936,7 @@ static ssize_t sam_tsd_read(struct file *filep, char *buffer, size_t len)
* handle smaller reads... but why?
*/
- idbg("ERROR: Unsupported read size: %d\n", len);
+ ierr("ERROR: Unsupported read size: %d\n", len);
return -ENOSYS;
}
@@ -954,7 +954,7 @@ static ssize_t sam_tsd_read(struct file *filep, char *buffer, size_t len)
* option, then just return an error.
*/
- ivdbg("Sample data is not available\n");
+ iinfo("Sample data is not available\n");
if (filep->f_oflags & O_NONBLOCK)
{
ret = -EAGAIN;
@@ -968,7 +968,7 @@ static ssize_t sam_tsd_read(struct file *filep, char *buffer, size_t len)
{
/* We might have been awakened by a signal */
- idbg("ERROR: sam_tsd_waitsample: %d\n", ret);
+ ierr("ERROR: sam_tsd_waitsample: %d\n", ret);
goto errout;
}
}
@@ -1018,16 +1018,16 @@ static ssize_t sam_tsd_read(struct file *filep, char *buffer, size_t len)
report->point[0].flags = TSD_PENMOVE;
}
- ivdbg(" id: %d\n", report->point[0].id);
- ivdbg(" flags: %02x\n", report->point[0].flags);
- ivdbg(" x: %d\n", report->point[0].x);
- ivdbg(" y: %d\n", report->point[0].y);
+ iinfo(" id: %d\n", report->point[0].id);
+ iinfo(" flags: %02x\n", report->point[0].flags);
+ iinfo(" x: %d\n", report->point[0].x);
+ iinfo(" y: %d\n", report->point[0].y);
ret = SIZEOF_TOUCH_SAMPLE_S(1);
errout:
sam_adc_unlock(priv->adc);
- ivdbg("Returning: %d\n", ret);
+ iinfo("Returning: %d\n", ret);
return (ssize_t)ret;
}
@@ -1041,7 +1041,7 @@ static int sam_tsd_ioctl(struct file *filep, int cmd, unsigned long arg)
struct sam_tsd_s *priv;
int ret;
- ivdbg("cmd: %d arg: %ld\n", cmd, arg);
+ iinfo("cmd: %d arg: %ld\n", cmd, arg);
DEBUGASSERT(filep);
inode = filep->f_inode;
@@ -1077,7 +1077,7 @@ static int sam_tsd_poll(struct file *filep, struct pollfd *fds, bool setup)
int ret = OK;
int i;
- ivdbg("setup: %d\n", (int)setup);
+ iinfo("setup: %d\n", (int)setup);
DEBUGASSERT(filep && fds);
inode = filep->f_inode;
@@ -1655,7 +1655,7 @@ int sam_tsd_register(struct sam_adc_s *adc, int minor)
char devname[DEV_NAMELEN];
int ret;
- ivdbg("minor: %d\n", minor);
+ iinfo("minor: %d\n", minor);
/* Debug-only sanity checks */
@@ -1674,12 +1674,12 @@ int sam_tsd_register(struct sam_adc_s *adc, int minor)
/* Register the device as an input device */
(void)snprintf(devname, DEV_NAMELEN, DEV_FORMAT, minor);
- ivdbg("Registering %s\n", devname);
+ iinfo("Registering %s\n", devname);
ret = register_driver(devname, &g_tsdops, 0666, priv);
if (ret < 0)
{
- idbg("ERROR: register_driver() failed: %d\n", ret);
+ ierr("ERROR: register_driver() failed: %d\n", ret);
goto errout_with_priv;
}
@@ -1724,7 +1724,7 @@ void sam_tsd_interrupt(uint32_t pending)
ret = sam_tsd_schedule(priv);
if (ret < 0)
{
- idbg("ERROR: sam_tsd_schedule failed: %d\n", ret);
+ ierr("ERROR: sam_tsd_schedule failed: %d\n", ret);
}
}
}
diff --git a/arch/arm/src/sama5/sam_twi.c b/arch/arm/src/sama5/sam_twi.c
index 14df0f62a4219d3256436e87d7e80bd7eef11761..4af5f702b0b9dd0e6cd73ccd40d530387e582c8f 100644
--- a/arch/arm/src/sama5/sam_twi.c
+++ b/arch/arm/src/sama5/sam_twi.c
@@ -95,15 +95,19 @@
# define CONFIG_SAMA5_TWI3_FREQUENCY 100000
#endif
+#ifndef CONFIG_DEBUG_I2C_INFO
+# undef CONFIG_SAMA5_TWI_REGDEBUG
+#endif
+
/* Driver internal definitions *************************************************/
-/* If verbose I2C debug output is enable, then allow more time before we declare
+/* If verbose I2C debug output is enabled, then allow more time before we declare
* a timeout. The debug output from twi_interrupt will really slow things down!
*
* With a very slow clock (say 100,000 Hz), less than 100 usec would be required
* to transfer on byte. So these define a "long" timeout.
*/
-#if defined(CONFIG_DEBUG_I2C) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_I2C_INFO
# define TWI_TIMEOUT_MSPB (50) /* 50 msec/byte */
#else
# define TWI_TIMEOUT_MSPB (5) /* 5 msec/byte */
@@ -123,21 +127,6 @@
#define MKI2C_INPUT(p) (((p) & (PIO_PORT_MASK | PIO_PIN_MASK)) | I2C_INPUT)
#define MKI2C_OUTPUT(p) (((p) & (PIO_PORT_MASK | PIO_PIN_MASK)) | I2C_OUTPUT)
-/* Debug ***********************************************************************/
-/* CONFIG_DEBUG_I2C + CONFIG_DEBUG enables general I2C debug output. */
-
-#ifdef CONFIG_DEBUG_I2C
-# define i2cdbg dbg
-# define i2cvdbg vdbg
-# define i2clldbg lldbg
-# define i2cllvdbg llvdbg
-#else
-# define i2cdbg(x...)
-# define i2cvdbg(x...)
-# define i2clldbg(x...)
-# define i2cllvdbg(x...)
-#endif
-
/****************************************************************************
* Private Types
****************************************************************************/
@@ -384,7 +373,7 @@ static bool twi_checkreg(struct twi_dev_s *priv, bool wr, uint32_t value,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", priv->ntimes);
+ i2cinfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@@ -416,7 +405,7 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address)
if (twi_checkreg(priv, false, value, address))
{
- lldbg("%08x->%08x\n", address, value);
+ i2cinfo("%08x->%08x\n", address, value);
}
return value;
@@ -437,7 +426,7 @@ static void twi_putabs(struct twi_dev_s *priv, uintptr_t address,
{
if (twi_checkreg(priv, true, value, address))
{
- lldbg("%08x<-%08x\n", address, value);
+ i2cinfo("%08x<-%08x\n", address, value);
}
putreg32(value, address);
@@ -514,9 +503,9 @@ static int twi_wait(struct twi_dev_s *priv, unsigned int size)
do
{
- i2cvdbg("TWI%d Waiting...\n", priv->attr->twi);
+ i2cinfo("TWI%d Waiting...\n", priv->attr->twi);
twi_takesem(&priv->waitsem);
- i2cvdbg("TWI%d Awakened with result: %d\n",
+ i2cinfo("TWI%d Awakened with result: %d\n",
priv->attr->twi, priv->result);
}
while (priv->result == -EBUSY);
@@ -574,7 +563,7 @@ static int twi_interrupt(struct twi_dev_s *priv)
imr = twi_getrel(priv, SAM_TWI_IMR_OFFSET);
pending = sr & imr;
- i2cllvdbg("TWI%d pending: %08x\n", priv->attr->twi, pending);
+ i2cinfo("TWI%d pending: %08x\n", priv->attr->twi, pending);
/* Byte received */
@@ -670,7 +659,7 @@ static int twi_interrupt(struct twi_dev_s *priv)
{
/* Wake up the thread with an I/O error indication */
- i2clldbg("ERROR: TWI%d pending: %08x\n", priv->attr->twi, pending);
+ i2cerr("ERROR: TWI%d pending: %08x\n", priv->attr->twi, pending);
twi_wakeup(priv, -EIO);
}
@@ -720,7 +709,7 @@ static void twi_timeout(int argc, uint32_t arg, ...)
{
struct twi_dev_s *priv = (struct twi_dev_s *)arg;
- i2clldbg("ERROR: TWI%d Timeout!\n", priv->attr->twi);
+ i2cerr("ERROR: TWI%d Timeout!\n", priv->attr->twi);
twi_wakeup(priv, -ETIMEDOUT);
}
@@ -841,7 +830,7 @@ static int twi_transfer(FAR struct i2c_master_s *dev,
int ret;
DEBUGASSERT(dev != NULL && msgs != NULL && count > 0);
- i2cvdbg("TWI%d count: %d\n", priv->attr->twi, count);
+ i2cinfo("TWI%d count: %d\n", priv->attr->twi, count);
/* Calculate the total transfer size so that we can calculate a reasonable
* timeout value.
@@ -887,7 +876,7 @@ static int twi_transfer(FAR struct i2c_master_s *dev,
ret = twi_wait(priv, size);
if (ret < 0)
{
- i2cdbg("ERROR: Transfer failed: %d\n", ret);
+ i2cerr("ERROR: Transfer failed: %d\n", ret);
}
leave_critical_section(flags);
@@ -1127,7 +1116,7 @@ static void twi_hw_initialize(struct twi_dev_s *priv, uint32_t frequency)
uint32_t regval;
uint32_t mck;
- i2cvdbg("TWI%d Initializing\n", priv->attr->twi);
+ i2cinfo("TWI%d Initializing\n", priv->attr->twi);
/* Configure PIO pins */
@@ -1228,7 +1217,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
irqstate_t flags;
int ret;
- i2cvdbg("Initializing TWI%d\n", bus);
+ i2cinfo("Initializing TWI%d\n", bus);
#ifdef CONFIG_SAMA5_TWI0
if (bus == 0)
@@ -1287,7 +1276,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
else
#endif
{
- i2cdbg("ERROR: Unsupported bus: TWI%d\n", bus);
+ i2cerr("ERROR: Unsupported bus: TWI%d\n", bus);
return NULL;
}
@@ -1300,7 +1289,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
priv->timeout = wd_create();
if (priv->timeout == NULL)
{
- idbg("ERROR: Failed to allocate a timer\n");
+ ierr("ERROR: Failed to allocate a timer\n");
goto errout_with_irq;
}
@@ -1309,7 +1298,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
ret = irq_attach(priv->attr->irq, priv->attr->handler);
if (ret < 0)
{
- idbg("ERROR: Failed to attach irq %d\n", priv->attr->irq);
+ ierr("ERROR: Failed to attach irq %d\n", priv->attr->irq);
goto errout_with_wdog;
}
@@ -1347,7 +1336,7 @@ int sam_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
{
struct twi_dev_s *priv = (struct twi_dev_s *) dev;
- i2cvdbg("TWI%d Un-initializing\n", priv->attr->twi);
+ i2cinfo("TWI%d Un-initializing\n", priv->attr->twi);
/* Disable TWI interrupts */
diff --git a/arch/arm/src/sama5/sam_udphs.c b/arch/arm/src/sama5/sam_udphs.c
index 06c2cf2fed41d8f79cf8df99275d26d87b62238e..76f704d1f690b19d19a416430f02a59ddf9ac6c1 100644
--- a/arch/arm/src/sama5/sam_udphs.c
+++ b/arch/arm/src/sama5/sam_udphs.c
@@ -91,11 +91,7 @@
# define CONFIG_SAMA5_UDPHS_NDTDS 8
#endif
-/* Extremely detailed register debug that you would normally never want
- * enabled.
- */
-
-#ifndef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB_INFO
# undef CONFIG_SAMA5_UDPHS_REGDEBUG
#endif
@@ -671,7 +667,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] =
#ifdef CONFIG_SAMA5_UDPHS_REGDEBUG
static void sam_printreg(uintptr_t regaddr, uint32_t regval, bool iswrite)
{
- lldbg("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval);
+ uinfo("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval);
}
#endif
@@ -722,7 +718,7 @@ static void sam_checkreg(uintptr_t regaddr, uint32_t regval, bool iswrite)
{
/* No.. More than one. */
- lldbg("[repeats %d more times]\n", count);
+ uinfo("[repeats %d more times]\n", count);
}
}
@@ -797,36 +793,36 @@ static inline void sam_putreg(uint32_t regval, uint32_t regaddr)
* Name: sam_dumpep
****************************************************************************/
-#if defined(CONFIG_SAMA5_UDPHS_REGDEBUG) && defined(CONFIG_DEBUG)
+#if defined(CONFIG_SAMA5_UDPHS_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
static void sam_dumpep(struct sam_usbdev_s *priv, int epno)
{
/* Global Registers */
- lldbg("Global Register:\n");
- lldbg(" CTRL: %04x\n", sam_getreg(SAM_UDPHS_CTRL));
- lldbg(" FNUM: %04x\n", sam_getreg(SAM_UDPHS_FNUM));
- lldbg(" IEN: %04x\n", sam_getreg(SAM_UDPHS_IEN));
- lldbg(" INSTA: %04x\n", sam_getreg(SAM_UDPHS_INTSTA));
- lldbg(" TST: %04x\n", sam_getreg(SAM_UDPHS_TST));
+ uinfo("Global Register:\n");
+ uinfo(" CTRL: %04x\n", sam_getreg(SAM_UDPHS_CTRL));
+ uinfo(" FNUM: %04x\n", sam_getreg(SAM_UDPHS_FNUM));
+ uinfo(" IEN: %04x\n", sam_getreg(SAM_UDPHS_IEN));
+ uinfo(" INSTA: %04x\n", sam_getreg(SAM_UDPHS_INTSTA));
+ uinfo(" TST: %04x\n", sam_getreg(SAM_UDPHS_TST));
/* Endpoint registers */
- lldbg("Endpoint %d Register:\n", epno);
- lldbg(" CFG: %04x\n", sam_getreg(SAM_UDPHS_EPTCFG(epno)));
- lldbg(" CTL: %04x\n", sam_getreg(SAM_UDPHS_EPTCTL(epno)));
- lldbg(" STA: %04x\n", sam_getreg(SAM_UDPHS_EPTSTA(epno)));
+ uinfo("Endpoint %d Register:\n", epno);
+ uinfo(" CFG: %04x\n", sam_getreg(SAM_UDPHS_EPTCFG(epno)));
+ uinfo(" CTL: %04x\n", sam_getreg(SAM_UDPHS_EPTCTL(epno)));
+ uinfo(" STA: %04x\n", sam_getreg(SAM_UDPHS_EPTSTA(epno)));
- lldbg("DMA %d Register:\n", epno);
+ uinfo("DMA %d Register:\n", epno);
if ((SAM_EPSET_DMA & SAM_EP_BIT(epno)) != 0)
{
- lldbg(" NXTDSC: %04x\n", sam_getreg(SAM_UDPHS_DMANXTDSC(epno)));
- lldbg(" ADDRESS: %04x\n", sam_getreg(SAM_UDPHS_DMAADDRESS(epno)));
- lldbg(" CONTROL: %04x\n", sam_getreg(SAM_UDPHS_DMACONTROL(epno)));
- lldbg(" STATUS: %04x\n", sam_getreg(SAM_UDPHS_DMASTATUS(epno)));
+ uinfo(" NXTDSC: %04x\n", sam_getreg(SAM_UDPHS_DMANXTDSC(epno)));
+ uinfo(" ADDRESS: %04x\n", sam_getreg(SAM_UDPHS_DMAADDRESS(epno)));
+ uinfo(" CONTROL: %04x\n", sam_getreg(SAM_UDPHS_DMACONTROL(epno)));
+ uinfo(" STATUS: %04x\n", sam_getreg(SAM_UDPHS_DMASTATUS(epno)));
}
else
{
- lldbg(" None\n");
+ uinfo(" None\n");
}
}
#endif
@@ -1357,9 +1353,9 @@ static int sam_req_write(struct sam_usbdev_s *priv, struct sam_ep_s *privep)
return -ENOENT;
}
- ullvdbg("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
- epno, privreq, privreq->req.len, privreq->req.xfrd,
- privreq->inflight, privep->zlpneeded);
+ uinfo("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
+ epno, privreq, privreq->req.len, privreq->req.xfrd,
+ privreq->inflight, privep->zlpneeded);
/* Handle any bytes in flight. */
@@ -1600,8 +1596,8 @@ static int sam_req_read(struct sam_usbdev_s *priv, struct sam_ep_s *privep,
return -ENOENT;
}
- ullvdbg("EP%d: len=%d xfrd=%d\n",
- epno, privreq->req.len, privreq->req.xfrd);
+ uinfo("EP%d: len=%d xfrd=%d\n",
+ epno, privreq->req.len, privreq->req.xfrd);
/* Ignore any attempt to receive a zero length packet */
@@ -1885,8 +1881,8 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
index.w = GETUINT16(priv->ctrl.index);
len.w = GETUINT16(priv->ctrl.len);
- ullvdbg("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
+ uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
/* Dispatch any non-standard requests */
@@ -2049,7 +2045,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
{
/* Special case recipient=device test mode */
- ullvdbg("test mode: %d\n", index.w);
+ uinfo("test mode: %d\n", index.w);
}
else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@@ -2349,7 +2345,7 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno)
/* Get the result of the DMA operation */
dmastatus = sam_getreg(SAM_UDPHS_DMASTATUS(epno));
- uvdbg("DMA%d DMASTATUS: %08x\n", epno, dmastatus);
+ uinfo("DMA%d DMASTATUS: %08x\n", epno, dmastatus);
/* Disable DMA interrupt to avoid receiving 2 (B_EN and TR_EN) */
@@ -3220,7 +3216,7 @@ static int sam_ep_configure_internal(struct sam_ep_s *privep,
uint8_t nbtrans;
bool dirin;
- uvdbg("len: %02x type: %02x addr: %02x attr: %02x "
+ uinfo("len: %02x type: %02x addr: %02x attr: %02x "
"maxpacketsize: %02x %02x interval: %02x\n",
desc->len, desc->type, desc->addr, desc->attr,
desc->mxpacketsize[0], desc->mxpacketsize[1],
@@ -3397,7 +3393,7 @@ static int sam_ep_configure(struct usbdev_ep_s *ep,
/* Verify parameters. Endpoint 0 is not available at this interface */
-#if defined(CONFIG_DEBUG) || defined(CONFIG_USBDEV_TRACE)
+#if defined(CONFIG_DEBUG_FEATURES) || defined(CONFIG_USBDEV_TRACE)
uint8_t epno = USB_EPNO(desc->addr);
usbtrace(TRACE_EPCONFIGURE, (uint16_t)epno);
@@ -3436,11 +3432,11 @@ static int sam_ep_disable(struct usbdev_ep_s *ep)
irqstate_t flags;
uint8_t epno;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
- ulldbg("ERROR: ep=%p\n", ep);
+ uerr("ERROR: ep=%p\n", ep);
return -EINVAL;
}
#endif
@@ -3473,7 +3469,7 @@ static struct usbdev_req_s *sam_ep_allocreq(struct usbdev_ep_s *ep)
{
struct sam_req_s *privreq;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
@@ -3505,7 +3501,7 @@ static void sam_ep_freereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
{
struct sam_req_s *privreq = (struct sam_req_s *)req;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
@@ -3568,11 +3564,12 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
uint8_t epno;
int ret = OK;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
- ulldbg("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+ uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n",
+ req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
@@ -3580,11 +3577,11 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
usbtrace(TRACE_EPSUBMIT, USB_EPNO(ep->eplog));
priv = privep->dev;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!priv->driver)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
- ulldbg("ERROR: driver=%p\n", priv->driver);
+ uerr("ERROR: driver=%p\n", priv->driver);
return -ESHUTDOWN;
}
#endif
@@ -3611,7 +3608,7 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
if (privep->stalled)
{
sam_req_abort(privep, privreq, -EBUSY);
- ulldbg("ERROR: stalled\n");
+ uerr("ERROR: stalled\n");
ret = -EPERM;
}
else
@@ -3660,7 +3657,7 @@ static int sam_ep_cancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
struct sam_ep_s *privep = (struct sam_ep_s *)ep;
irqstate_t flags;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
@@ -3687,7 +3684,7 @@ static int sam_ep_stall(struct usbdev_ep_s *ep, bool resume)
uint32_t regval;
irqstate_t flags;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
@@ -3826,7 +3823,7 @@ static struct usbdev_ep_s *sam_allocep(struct usbdev_s *dev, uint8_t epno,
uint16_t epset = SAM_EPSET_NOTEP0;
usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!dev)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
@@ -3888,7 +3885,7 @@ static void sam_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep)
struct sam_usbdev_s *priv;
struct sam_ep_s *privep;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!dev || !ep)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
@@ -3920,7 +3917,7 @@ static int sam_getframe(struct usbdev_s *dev)
uint32_t regval;
uint16_t frameno;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!dev)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
@@ -3952,7 +3949,7 @@ static int sam_wakeup(struct usbdev_s *dev)
uint32_t regval;
usbtrace(TRACE_DEVWAKEUP, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!dev)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
@@ -3998,7 +3995,7 @@ static int sam_selfpowered(struct usbdev_s *dev, bool selfpowered)
usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!dev)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
@@ -4300,7 +4297,7 @@ static void sam_sw_setup(struct sam_usbdev_s *priv)
kmm_memalign(16, CONFIG_SAMA5_UDPHS_NDTDS * sizeof(struct sam_dtd_s));
if (!priv->dtdpool)
{
- udbg("ERROR: Failed to allocate the DMA transfer descriptor pool\n");
+ uerr("ERROR: Failed to allocate the DMA transfer descriptor pool\n");
return NULL;
}
@@ -4517,7 +4514,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
usbtrace(TRACE_DEVREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!driver || !driver->ops->bind || !driver->ops->unbind ||
!driver->ops->disconnect || !driver->ops->setup)
{
@@ -4591,7 +4588,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
usbtrace(TRACE_DEVUNREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (driver != priv->driver)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
diff --git a/arch/arm/src/sama5/sam_wdt.c b/arch/arm/src/sama5/sam_wdt.c
index d14f45c1983e1786b94ca680d4948577bb65c1a6..26f40860b7c503c0b98108209471f96500a69325 100644
--- a/arch/arm/src/sama5/sam_wdt.c
+++ b/arch/arm/src/sama5/sam_wdt.c
@@ -57,6 +57,11 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
+
+#ifndef CONFIG_DEBUG_WATCHDOG_INFO
+# undef CONFIG_SAMA5_WDT_REGDEBUG
+#endif
+
/* The Watchdog Timer uses the Slow Clock divided by 128 to establish the
* maximum Watchdog period to be 16 seconds (with a typical Slow Clock of
* 32768 kHz).
@@ -80,20 +85,6 @@
#define WDT_MINTIMEOUT ((1000 + WDT_FREQUENCY - 1) / WDT_FREQUENCY)
#define WDT_MAXTIMEOUT ((4096 * 1000) / WDT_FREQUENCY)
-/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing the watchdog
- * driver. NOTE: that only lldbg types are used so that the output is
- * immediately available.
- */
-
-#ifdef CONFIG_DEBUG_WATCHDOG
-# define wddbg lldbg
-# define wdvdbg llvdbg
-#else
-# define wddbg(x...)
-# define wdvdbg(x...)
-#endif
-
/****************************************************************************
* Private Types
****************************************************************************/
@@ -118,7 +109,7 @@ struct sam_lowerhalf_s
****************************************************************************/
/* Register operations ******************************************************/
-#if defined(CONFIG_SAMA5_WDT_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAMA5_WDT_REGDEBUG
static uint32_t sam_getreg(uintptr_t regaddr);
static void sam_putreg(uint32_t regval, uintptr_t regaddr);
#else
@@ -178,7 +169,7 @@ static struct sam_lowerhalf_s g_wdtdev;
*
****************************************************************************/
-#if defined(CONFIG_SAMA5_WDT_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAMA5_WDT_REGDEBUG
static uint32_t sam_getreg(uintptr_t regaddr)
{
static uint32_t prevaddr = 0;
@@ -199,7 +190,7 @@ static uint32_t sam_getreg(uintptr_t regaddr)
{
if (count == 4)
{
- lldbg("...\n");
+ wdinfo("...\n");
}
return regval;
@@ -216,7 +207,7 @@ static uint32_t sam_getreg(uintptr_t regaddr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ wdinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -228,7 +219,7 @@ static uint32_t sam_getreg(uintptr_t regaddr)
/* Show the register value read */
- lldbg("%08x->%048\n", regaddr, regval);
+ wdinfo("%08x->%048\n", regaddr, regval);
return regval;
}
#endif
@@ -241,12 +232,12 @@ static uint32_t sam_getreg(uintptr_t regaddr)
*
****************************************************************************/
-#if defined(CONFIG_SAMA5_WDT_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAMA5_WDT_REGDEBUG
static void sam_putreg(uint32_t regval, uintptr_t regaddr)
{
/* Show the register value being written */
- lldbg("%08x<-%08x\n", regaddr, regval);
+ wdinfo("%08x<-%08x\n", regaddr, regval);
/* Write the value */
@@ -315,7 +306,7 @@ static int sam_start(FAR struct watchdog_lowerhalf_s *lower)
* timer with the newly programmed mode parameters.
*/
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
return priv->started ? OK : -ENOSYS;
}
@@ -343,7 +334,7 @@ static int sam_stop(FAR struct watchdog_lowerhalf_s *lower)
* timer with the newly programmed mode parameters.
*/
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
return -ENOSYS;
}
@@ -366,7 +357,7 @@ static int sam_stop(FAR struct watchdog_lowerhalf_s *lower)
static int sam_keepalive(FAR struct watchdog_lowerhalf_s *lower)
{
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
/* Write WDT_CR_WDRSTT to the WDT CR regiser (along with the KEY value)
* will restart the watchdog timer.
@@ -397,7 +388,7 @@ static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower,
{
FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower;
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
DEBUGASSERT(priv);
/* Return the status bit */
@@ -426,10 +417,10 @@ static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower,
status->timeleft = 0;
- wdvdbg("Status :\n");
- wdvdbg(" flags : %08x\n", status->flags);
- wdvdbg(" timeout : %d\n", status->timeout);
- wdvdbg(" timeleft : %d\n", status->timeleft);
+ wdinfo("Status :\n");
+ wdinfo(" flags : %08x\n", status->flags);
+ wdinfo(" timeout : %d\n", status->timeout);
+ wdinfo(" timeleft : %d\n", status->timeleft);
return OK;
}
@@ -457,13 +448,13 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower,
uint32_t regval;
DEBUGASSERT(priv);
- wdvdbg("Entry: timeout=%d\n", timeout);
+ wdinfo("Entry: timeout=%d\n", timeout);
/* Can this timeout be represented? */
if (timeout < WDT_MINTIMEOUT || timeout >= WDT_MAXTIMEOUT)
{
- wddbg("Cannot represent timeout: %d < %d > %d\n",
+ wderr("ERROR: Cannot represent timeout: %d < %d > %d\n",
WDT_MINTIMEOUT, timeout, WDT_MAXTIMEOUT);
return -ERANGE;
}
@@ -496,7 +487,7 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower,
priv->reload = reload;
- wdvdbg("reload=%d timout: %d->%d\n",
+ wdinfo("reload=%d timout: %d->%d\n",
reload, timeout, priv->timeout);
/* Set the WDT_MR according to calculated value
@@ -541,7 +532,7 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower,
priv->started = true;
- wdvdbg("Setup: CR: %08x MR: %08x SR: %08x\n",
+ wdinfo("Setup: CR: %08x MR: %08x SR: %08x\n",
sam_getreg(SAM_WDT_CR), sam_getreg(SAM_WDT_MR),
sam_getreg(SAM_WDT_SR));
@@ -574,7 +565,7 @@ static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower,
xcpt_t handler)
{
#ifndef CONFIG_SAMA5_WDT_INTERRUPT
- wddbg("ERROR: Not configured for this mode\n");
+ wderr("ERROR: Not configured for this mode\n");
return NULL;
#else
FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower;
@@ -582,7 +573,7 @@ static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower,
xcpt_t oldhandler;
DEBUGASSERT(priv);
- wdvdbg("Entry: handler=%p\n", handler);
+ wdinfo("Entry: handler=%p\n", handler);
/* Get the old handler return value */
@@ -636,7 +627,7 @@ static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower,
static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
unsigned long arg)
{
- wdvdbg("cmd=%d arg=%ld\n", cmd, arg);
+ wdinfo("cmd=%d arg=%ld\n", cmd, arg);
/* No ioctls are supported */
@@ -667,7 +658,7 @@ int sam_wdt_initialize(void)
{
FAR struct sam_lowerhalf_s *priv = &g_wdtdev;
- wdvdbg("Entry: CR: %08x MR: %08x SR: %08x\n",
+ wdinfo("Entry: CR: %08x MR: %08x SR: %08x\n",
sam_getreg(SAM_WDT_CR), sam_getreg(SAM_WDT_MR),
sam_getreg(SAM_WDT_SR));
diff --git a/arch/arm/src/sama5/sam_xdmac.c b/arch/arm/src/sama5/sam_xdmac.c
index bb4ce4e1ddcb54165a3fede40c35bdc35981a657..9b819555569e3079c1fcc3fed55cd10542da9d36 100644
--- a/arch/arm/src/sama5/sam_xdmac.c
+++ b/arch/arm/src/sama5/sam_xdmac.c
@@ -807,7 +807,7 @@ static uint8_t sam_channel(uint8_t pid, const struct sam_pidmap_s *table,
}
}
- dmadbg("No channel found for pid %d\n", pid);
+ dmaerr("ERROR: No channel found for pid %d\n", pid);
DEBUGPANIC();
return 0x3f;
}
@@ -1330,7 +1330,7 @@ sam_allocdesc(struct sam_xdmach_s *xdmach, struct chnext_view1_s *prev,
* Obviously setting it to zero would break that usage.
*/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (csa != 0)
#endif
{
@@ -1650,7 +1650,7 @@ static inline int sam_single(struct sam_xdmach_s *xdmach)
static inline int sam_multiple(struct sam_xdmach_s *xdmach)
{
struct sam_xdmac_s *xdmac = sam_controller(xdmach);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_ASSERTIONS
struct chnext_view1_s *llhead = xdmach->llhead;
#endif
uintptr_t paddr;
@@ -1860,7 +1860,7 @@ static int sam_xdmac_interrupt(struct sam_xdmac_s *xdmac)
{
/* Yes... Terminate the transfer with an error? */
- dmalldbg("ERROR: DMA failed: %08x\n", chpending);
+ dmaerr("ERROR: DMA failed: %08x\n", chpending);
sam_dmaterminate(xdmach, -EIO);
}
@@ -1877,7 +1877,7 @@ static int sam_xdmac_interrupt(struct sam_xdmac_s *xdmac)
else
{
- dmalldbg("ERROR: Unexpected interrupt: %08x\n", chpending);
+ dmaerr("ERROR: Unexpected interrupt: %08x\n", chpending);
DEBUGPANIC();
}
@@ -1957,7 +1957,7 @@ void sam_dmainitialize(struct sam_xdmac_s *xdmac)
void weak_function up_dmainitialize(void)
{
#ifdef CONFIG_SAMA5_XDMAC0
- dmallvdbg("Initialize XDMAC0\n");
+ dmainfo("Initialize XDMAC0\n");
/* Enable peripheral clock */
@@ -1977,7 +1977,7 @@ void weak_function up_dmainitialize(void)
#endif
#ifdef CONFIG_SAMA5_XDMAC1
- dmallvdbg("Initialize XDMAC1\n");
+ dmainfo("Initialize XDMAC1\n");
/* Enable peripheral clock */
@@ -2039,7 +2039,7 @@ DMA_HANDLE sam_dmachannel(uint8_t dmacno, uint32_t chflags)
#endif
{
- dmadbg("ERROR: Bad XDMAC number: %d\n", dmacno);
+ dmaerr("ERROR: Bad XDMAC number: %d\n", dmacno);
DEBUGPANIC();
return (DMA_HANDLE)NULL;
}
@@ -2083,12 +2083,12 @@ DMA_HANDLE sam_dmachannel(uint8_t dmacno, uint32_t chflags)
if (xdmach)
{
- dmavdbg("XDMAC%d CH%d: chflags: %08x returning xdmach: %p\n",
+ dmainfo("XDMAC%d CH%d: chflags: %08x returning xdmach: %p\n",
(int)dmacno, xdmach->chan, (int)chflags, xdmach);
}
else
{
- dmadbg("ERROR: Failed allocate XDMAC%d channel\n", (int)dmacno);
+ dmaerr("ERROR: Failed allocate XDMAC%d channel\n", (int)dmacno);
}
return (DMA_HANDLE)xdmach;
@@ -2119,13 +2119,13 @@ void sam_dmaconfig(DMA_HANDLE handle, uint32_t chflags)
xdmach->flags = chflags;
#if defined(CONFIG_SAMA5_XDMAC0) && defined(CONFIG_SAMA5_XDMAC1)
- dmavdbg("XDMAC%d CH%d: chflags: %08x\n",
+ dmainfo("XDMAC%d CH%d: chflags: %08x\n",
xdmach->xdmac, xdmach->chan, (int)chflags);
#elif defined(CONFIG_SAMA5_XDMAC0)
- dmavdbg("XDMAC0 CH%d: chflags: %08x\n",
+ dmainfo("XDMAC0 CH%d: chflags: %08x\n",
xdmach->chan, (int)chflags);
#else
- dmavdbg("XDMAC1 CH%d: chflags: %08x\n",
+ dmainfo("XDMAC1 CH%d: chflags: %08x\n",
xdmach->chan, (int)chflags);
#endif
}
@@ -2148,7 +2148,7 @@ void sam_dmafree(DMA_HANDLE handle)
struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle;
struct sam_xdmac_s *xdmac;
- dmavdbg("xdmach: %p\n", xdmach);
+ dmainfo("xdmach: %p\n", xdmach);
DEBUGASSERT((xdmach != NULL) && (xdmach->inuse));
xdmac = sam_controller(xdmach);
@@ -2186,10 +2186,10 @@ int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
size_t remaining;
int ret = OK;
- dmavdbg("xdmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
+ dmainfo("xdmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
xdmach, (int)paddr, (int)maddr, (int)nbytes);
DEBUGASSERT(xdmach);
- dmavdbg("llhead: %p lltail: %p\n", xdmach->llhead, xdmach->lltail);
+ dmainfo("llhead: %p lltail: %p\n", xdmach->llhead, xdmach->lltail);
/* The maximum transfer size in bytes depends upon the maximum number of
* transfers and the number of bytes per transfer.
@@ -2265,10 +2265,10 @@ int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
size_t remaining;
int ret = OK;
- dmavdbg("xdmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
+ dmainfo("xdmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
xdmach, (int)paddr, (int)maddr, (int)nbytes);
DEBUGASSERT(xdmach);
- dmavdbg("llhead: %p lltail: %p\n", xdmach->llhead, xdmach->lltail);
+ dmainfo("llhead: %p lltail: %p\n", xdmach->llhead, xdmach->lltail);
/* The maximum transfer size in bytes depends upon the maximum number of
* transfers and the number of bytes per transfer.
@@ -2340,7 +2340,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle;
int ret = -EINVAL;
- dmavdbg("xdmach: %p callback: %p arg: %p\n", xdmach, callback, arg);
+ dmainfo("xdmach: %p callback: %p arg: %p\n", xdmach, callback, arg);
DEBUGASSERT(xdmach != NULL);
/* Verify that the DMA has been setup (i.e., at least one entry in the
@@ -2384,7 +2384,7 @@ void sam_dmastop(DMA_HANDLE handle)
struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle;
irqstate_t flags;
- dmavdbg("xdmach: %p\n", xdmach);
+ dmainfo("xdmach: %p\n", xdmach);
DEBUGASSERT(xdmach != NULL);
flags = enter_critical_section();
@@ -2403,7 +2403,7 @@ void sam_dmastop(DMA_HANDLE handle)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
{
struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle;
@@ -2445,7 +2445,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
leave_critical_section(flags);
}
-#endif /* CONFIG_DEBUG_DMA */
+#endif /* CONFIG_DEBUG_DMA_INFO */
/****************************************************************************
* Name: sam_dmadump
@@ -2458,37 +2458,37 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
const char *msg)
{
struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle;
struct sam_xdmac_s *xdmac = sam_controller(xdmach);
- dmadbg("%s\n", msg);
- dmadbg(" DMA Global Registers:\n");
- dmadbg(" GTYPE[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GTYPE_OFFSET, regs->gtype);
- dmadbg(" GCFG[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GCFG_OFFSET, regs->gcfg);
- dmadbg(" GWAC[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GWAC_OFFSET, regs->gwac);
- dmadbg(" GIM[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GIM_OFFSET, regs->gim);
- dmadbg(" GIS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GIS_OFFSET, regs->gis);
- dmadbg(" GS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GS_OFFSET, regs->gs);
- dmadbg(" GRS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GRS_OFFSET, regs->grs);
- dmadbg(" GWS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GWS_OFFSET, regs->gws);
- dmadbg(" GSWS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GSWS_OFFSET, regs->gsws);
- dmadbg(" DMA Channel Registers:\n");
- dmadbg(" CIM[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIM_OFFSET, regs->cim);
- dmadbg(" CIS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIS_OFFSET, regs->cis);
- dmadbg(" CSA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSA_OFFSET, regs->csa);
- dmadbg(" CDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDA_OFFSET, regs->cda);
- dmadbg(" CNDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDA_OFFSET, regs->cnda);
- dmadbg(" CNDC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDC_OFFSET, regs->cndc);
- dmadbg(" CUBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CUBC_OFFSET, regs->cubc);
- dmadbg(" CBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CBC_OFFSET, regs->cbc);
- dmadbg(" CC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CC_OFFSET, regs->cc);
- dmadbg(" CDSMSP[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDSMSP_OFFSET, regs->cdsmsp);
- dmadbg(" CSUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSUS_OFFSET, regs->csus);
- dmadbg(" CDUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDUS_OFFSET, regs->cdus);
+ dmainfo("%s\n", msg);
+ dmainfo(" DMA Global Registers:\n");
+ dmainfo(" GTYPE[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GTYPE_OFFSET, regs->gtype);
+ dmainfo(" GCFG[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GCFG_OFFSET, regs->gcfg);
+ dmainfo(" GWAC[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GWAC_OFFSET, regs->gwac);
+ dmainfo(" GIM[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GIM_OFFSET, regs->gim);
+ dmainfo(" GIS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GIS_OFFSET, regs->gis);
+ dmainfo(" GS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GS_OFFSET, regs->gs);
+ dmainfo(" GRS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GRS_OFFSET, regs->grs);
+ dmainfo(" GWS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GWS_OFFSET, regs->gws);
+ dmainfo(" GSWS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GSWS_OFFSET, regs->gsws);
+ dmainfo(" DMA Channel Registers:\n");
+ dmainfo(" CIM[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIM_OFFSET, regs->cim);
+ dmainfo(" CIS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIS_OFFSET, regs->cis);
+ dmainfo(" CSA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSA_OFFSET, regs->csa);
+ dmainfo(" CDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDA_OFFSET, regs->cda);
+ dmainfo(" CNDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDA_OFFSET, regs->cnda);
+ dmainfo(" CNDC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDC_OFFSET, regs->cndc);
+ dmainfo(" CUBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CUBC_OFFSET, regs->cubc);
+ dmainfo(" CBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CBC_OFFSET, regs->cbc);
+ dmainfo(" CC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CC_OFFSET, regs->cc);
+ dmainfo(" CDSMSP[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDSMSP_OFFSET, regs->cdsmsp);
+ dmainfo(" CSUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSUS_OFFSET, regs->csus);
+ dmainfo(" CDUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDUS_OFFSET, regs->cdus);
}
-#endif /* CONFIG_DEBUG_DMA */
+#endif /* CONFIG_DEBUG_DMA_INFO */
#endif /* CONFIG_SAMA5_XDMAC0 || CONFIG_SAMA5_XDMAC1 */
diff --git a/arch/arm/src/sama5/sama5d2x_pio.c b/arch/arm/src/sama5/sama5d2x_pio.c
index d6daf15a82003fb57987c21d863e362e8988481d..3a87d3da666e42ca6ee64ef1f0ce96cf0420254b 100644
--- a/arch/arm/src/sama5/sama5d2x_pio.c
+++ b/arch/arm/src/sama5/sama5d2x_pio.c
@@ -118,7 +118,7 @@ const uintptr_t g_spiobase[SAM_NPIO] =
****************************************************************************/
/* Maps a port number to the standard port character */
-#if defined(CONFIG_DEBUG_GPIO) && SAM_NPIO > 0
+#if defined(CONFIG_DEBUG_GPIO_INFO) && SAM_NPIO > 0
static const char g_portchar[SAM_NPIO] =
{
'A'
@@ -610,7 +610,7 @@ void sam_pio_forceclk(pio_pinset_t pinset, bool enable)
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
int sam_dumppio(uint32_t pinset, const char *msg)
{
irqstate_t flags;
@@ -630,32 +630,32 @@ int sam_dumppio(uint32_t pinset, const char *msg)
if (secure)
{
- lldbg("SPIO%c pinset: %08x base: %08x -- %s\n",
+ gpioinfo("SPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
}
else
{
- lldbg("PIO%c pinset: %08x base: %08x -- %s\n",
+ gpioinfo("PIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
}
- lldbg(" MSKR: %08x CFGR: %08x PDSR: %08x LOCKSR: %08x\n",
- getreg32(base + SAM_PIO_MSKR_OFFSET), getreg32(base + SAM_PIO_CFGR_OFFSET),
- getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET));
- lldbg(" ODSR: %08x IMR: %08x ISR: %08x\n",
- getreg32(base + SAM_PIO_ODSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
- getreg32(base + SAM_PIO_ISR_OFFSET));
+ gpioinfo(" MSKR: %08x CFGR: %08x PDSR: %08x LOCKSR: %08x\n",
+ getreg32(base + SAM_PIO_MSKR_OFFSET), getreg32(base + SAM_PIO_CFGR_OFFSET),
+ getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET));
+ gpioinfo(" ODSR: %08x IMR: %08x ISR: %08x\n",
+ getreg32(base + SAM_PIO_ODSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
+ getreg32(base + SAM_PIO_ISR_OFFSET));
if (secure)
{
- lldbg(" SCDR: %08x WPMR: %08x WPSR: %08x IOSSR: %08x\n",
- getreg32(SAM_SPIO_SCDR), getreg32(SAM_SPIO_WPMR),
- getreg32(SAM_SPIO_WPSR), getreg32(base + SAM_SPIO_IOSSR_OFFSET));
+ gpioinfo(" SCDR: %08x WPMR: %08x WPSR: %08x IOSSR: %08x\n",
+ getreg32(SAM_SPIO_SCDR), getreg32(SAM_SPIO_WPMR),
+ getreg32(SAM_SPIO_WPSR), getreg32(base + SAM_SPIO_IOSSR_OFFSET));
}
else
{
- lldbg(" WPMR: %08x WPSR: %08x\n",
- getreg32(SAM_PIO_WPMR), getreg32(SAM_PIO_WPSR));
+ gpioinfo(" WPMR: %08x WPSR: %08x\n",
+ getreg32(SAM_PIO_WPMR), getreg32(SAM_PIO_WPSR));
}
leave_critical_section(flags);
diff --git a/arch/arm/src/sama5/sama5d2x_pio.h b/arch/arm/src/sama5/sama5d2x_pio.h
index 4b37166d4b3f0a65870dfe31a7eaea17835f8cd7..4b0324dc96317b3c7c7ffa9a52b7c5645ba2660b 100644
--- a/arch/arm/src/sama5/sama5d2x_pio.h
+++ b/arch/arm/src/sama5/sama5d2x_pio.h
@@ -58,10 +58,6 @@
# undef CONFIG_SAMA5_PIO_IRQ
#endif
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_GPIO
-#endif
-
#define PIO_HAVE_PULLDOWN 1
#define PIO_HAVE_PERIPHCD 1
#define PIO_HAVE_SCHMITT 1
diff --git a/arch/arm/src/sama5/sama5d3x4x_pio.c b/arch/arm/src/sama5/sama5d3x4x_pio.c
index b9379ad868c734f96e427f7711c0ae5c11d69e7b..0165a382acfef968893243d0c090309c43bc58e9 100644
--- a/arch/arm/src/sama5/sama5d3x4x_pio.c
+++ b/arch/arm/src/sama5/sama5d3x4x_pio.c
@@ -67,10 +67,6 @@
#define PIO_INPUT_BITS (PIO_INPUT | PIO_CFG_DEFAULT)
#define MK_INPUT(p) (((p) & (PIO_PORT_MASK | PIO_PIN_MASK)) | PIO_INPUT_BITS)
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
/****************************************************************************
* Public Data
****************************************************************************/
@@ -99,7 +95,7 @@ const uintptr_t g_piobase[SAM_NPIO] =
****************************************************************************/
/* Maps a port number to the standard port character */
-#if defined(CONFIG_DEBUG_GPIO) && SAM_NPIO > 0
+#if defined(CONFIG_DEBUG_GPIO_INFO) && SAM_NPIO > 0
static const char g_portchar[SAM_NPIO] =
{
'A'
@@ -854,7 +850,7 @@ void sam_pio_forceclk(pio_pinset_t pinset, bool enable)
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
int sam_dumppio(uint32_t pinset, const char *msg)
{
irqstate_t flags;
@@ -869,41 +865,42 @@ int sam_dumppio(uint32_t pinset, const char *msg)
/* The following requires exclusive access to the PIO registers */
flags = enter_critical_section();
- lldbg("PIO%c pinset: %08x base: %08x -- %s\n",
- g_portchar[port], pinset, base, msg);
+
+ gpioinfo("PIO%c pinset: %08x base: %08x -- %s\n",
+ g_portchar[port], pinset, base, msg);
#ifdef SAM_PIO_ISLR_OFFSET
- lldbg(" PSR: %08x ISLR: %08x OSR: %08x IFSR: %08x\n",
- getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_ISLR_OFFSET),
- getreg32(base + SAM_PIO_OSR_OFFSET), getreg32(base + SAM_PIO_IFSR_OFFSET));
+ gpioinfo(" PSR: %08x ISLR: %08x OSR: %08x IFSR: %08x\n",
+ getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_ISLR_OFFSET),
+ getreg32(base + SAM_PIO_OSR_OFFSET), getreg32(base + SAM_PIO_IFSR_OFFSET));
#else
- lldbg(" PSR: %08x OSR: %08x IFSR: %08x\n",
- getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET),
- getreg32(base + SAM_PIO_IFSR_OFFSET));
-#endif
- lldbg(" ODSR: %08x PDSR: %08x IMR: %08x ISR: %08x\n",
- getreg32(base + SAM_PIO_ODSR_OFFSET), getreg32(base + SAM_PIO_PDSR_OFFSET),
- getreg32(base + SAM_PIO_IMR_OFFSET), getreg32(base + SAM_PIO_ISR_OFFSET));
- lldbg(" MDSR: %08x PUSR: %08x ABDCSR: %08x %08x\n",
- getreg32(base + SAM_PIO_MDSR_OFFSET), getreg32(base + SAM_PIO_PUSR_OFFSET),
- getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET));
- lldbg(" IFSCSR: %08x SCDR: %08x PPDSR: %08x OWSR: %08x\n",
- getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
- getreg32(base + SAM_PIO_PPDSR_OFFSET), getreg32(base + SAM_PIO_OWSR_OFFSET));
+ gpioinfo(" PSR: %08x OSR: %08x IFSR: %08x\n",
+ getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET),
+ getreg32(base + SAM_PIO_IFSR_OFFSET));
+#endif
+ gpioinfo(" ODSR: %08x PDSR: %08x IMR: %08x ISR: %08x\n",
+ getreg32(base + SAM_PIO_ODSR_OFFSET), getreg32(base + SAM_PIO_PDSR_OFFSET),
+ getreg32(base + SAM_PIO_IMR_OFFSET), getreg32(base + SAM_PIO_ISR_OFFSET));
+ gpioinfo(" MDSR: %08x PUSR: %08x ABDCSR: %08x %08x\n",
+ getreg32(base + SAM_PIO_MDSR_OFFSET), getreg32(base + SAM_PIO_PUSR_OFFSET),
+ getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET));
+ gpioinfo(" IFSCSR: %08x SCDR: %08x PPDSR: %08x OWSR: %08x\n",
+ getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
+ getreg32(base + SAM_PIO_PPDSR_OFFSET), getreg32(base + SAM_PIO_OWSR_OFFSET));
#ifdef SAM_PIO_LOCKSR_OFFSET
- lldbg(" AIMMR: %08x ELSR: %08x FRLHSR: %08x LOCKSR: %08x\n",
- getreg32(base + SAM_PIO_AIMMR_OFFSET), getreg32(base + SAM_PIO_ELSR_OFFSET),
- getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET));
+ gpioinfo(" AIMMR: %08x ELSR: %08x FRLHSR: %08x LOCKSR: %08x\n",
+ getreg32(base + SAM_PIO_AIMMR_OFFSET), getreg32(base + SAM_PIO_ELSR_OFFSET),
+ getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET));
#else
- lldbg(" AIMMR: %08x ELSR: %08x FRLHSR: %08x\n",
- getreg32(base + SAM_PIO_AIMMR_OFFSET), getreg32(base + SAM_PIO_ELSR_OFFSET),
- getreg32(base + SAM_PIO_FRLHSR_OFFSET));
-#endif
- lldbg("SCHMITT: %08x DRIVER: %08x %08x\n",
- getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DRIVER1_OFFSET),
- getreg32(base + SAM_PIO_DRIVER2_OFFSET));
- lldbg(" WPMR: %08x WPSR: %08x\n",
- getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
+ gpioinfo(" AIMMR: %08x ELSR: %08x FRLHSR: %08x\n",
+ getreg32(base + SAM_PIO_AIMMR_OFFSET), getreg32(base + SAM_PIO_ELSR_OFFSET),
+ getreg32(base + SAM_PIO_FRLHSR_OFFSET));
+#endif
+ gpioinfo("SCHMITT: %08x DRIVER: %08x %08x\n",
+ getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DRIVER1_OFFSET),
+ getreg32(base + SAM_PIO_DRIVER2_OFFSET));
+ gpioinfo(" WPMR: %08x WPSR: %08x\n",
+ getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
leave_critical_section(flags);
return OK;
diff --git a/arch/arm/src/sama5/sama5d3x4x_pio.h b/arch/arm/src/sama5/sama5d3x4x_pio.h
index 63b6615b556955465ba7f093342c3fb3e7fa4b13..cd5f1d3a59816ac04ba1be6535c980062485e520 100644
--- a/arch/arm/src/sama5/sama5d3x4x_pio.h
+++ b/arch/arm/src/sama5/sama5d3x4x_pio.h
@@ -52,10 +52,6 @@
# undef CONFIG_SAMA5_PIO_IRQ
#endif
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_GPIO
-#endif
-
#define PIO_HAVE_PULLDOWN 1
#define PIO_HAVE_PERIPHCD 1
#define PIO_HAVE_SCHMITT 1
diff --git a/arch/arm/src/samdl/Kconfig b/arch/arm/src/samdl/Kconfig
index a890db6a0fdd8dcbc14ac478ebe8bf8ad2febefc..28ca29c90c342f2b9ecb851bbfd635554d768c20 100644
--- a/arch/arm/src/samdl/Kconfig
+++ b/arch/arm/src/samdl/Kconfig
@@ -711,7 +711,7 @@ if SAMDL_HAVE_SPI
config SAMDL_SPI_REGDEBUG
bool "SPI register-Level Debug"
default n
- depends on DEBUG_SPI
+ depends on DEBUG_SPI_INFO
---help---
Enable very low-level register access debug. Depends on DEBUG_SPI.
diff --git a/arch/arm/src/samdl/Make.defs b/arch/arm/src/samdl/Make.defs
index d9a82f959e592953e0732a5e8c066feda4e9fc7c..7ef0105780becf9555c51205ae426c66680edf1d 100644
--- a/arch/arm/src/samdl/Make.defs
+++ b/arch/arm/src/samdl/Make.defs
@@ -65,7 +65,7 @@ else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
-ifeq ($(CONFIG_DEBUG),y)
+ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += up_dumpnvic.c
endif
diff --git a/arch/arm/src/samdl/sam_dmac.c b/arch/arm/src/samdl/sam_dmac.c
index de5004f2d74a5c5195076e76ae3616b16c1a3997..d465d4d5f87c89e14e1607d8befee060f5d68572 100644
--- a/arch/arm/src/samdl/sam_dmac.c
+++ b/arch/arm/src/samdl/sam_dmac.c
@@ -769,7 +769,7 @@ static int sam_rxbuffer(struct sam_dmach_s *dmach, uint32_t paddr,
void weak_function up_dmainitialize(void)
{
- dmallvdbg("Initialize DMAC\n");
+ dmainfo("Initialize DMAC\n");
int i;
/* Initialize global semaphores */
@@ -888,7 +888,7 @@ DMA_HANDLE sam_dmachannel(uint32_t chflags)
sam_givechsem();
- dmavdbg("chflags: %08x returning dmach: %p\n", (int)chflags, dmach);
+ dmainfo("chflags: %08x returning dmach: %p\n", (int)chflags, dmach);
return (DMA_HANDLE)dmach;
}
@@ -914,7 +914,7 @@ void sam_dmaconfig(DMA_HANDLE handle, uint32_t chflags)
/* Set the new DMA channel flags. */
- dmavdbg("chflags: %08x\n", (int)chflags);
+ dmainfo("chflags: %08x\n", (int)chflags);
dmach->dc_flags = chflags;
}
@@ -935,7 +935,7 @@ void sam_dmafree(DMA_HANDLE handle)
{
struct sam_dmach_s *dmach = (struct sam_dmach_s *)handle;
- dmavdbg("dmach: %p\n", dmach);
+ dmainfo("dmach: %p\n", dmach);
DEBUGASSERT((dmach != NULL) && (dmach->dc_inuse));
/* Mark the channel no longer in use. Clearing the inuse flag is an atomic
@@ -965,12 +965,12 @@ int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
size_t maxtransfer;
int ret = OK;
- dmavdbg("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
+ dmainfo("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
dmach, (int)paddr, (int)maddr, (int)nbytes);
DEBUGASSERT(dmach);
#if CONFIG_SAMDL_DMAC_NDESC > 0
- dmavdbg("dc_head: %p dc_tail: %p\n", dmach->dc_head, dmach->dc_tail);
+ dmainfo("dc_head: %p dc_tail: %p\n", dmach->dc_head, dmach->dc_tail);
#endif
/* The maximum transfer size in bytes depends upon the maximum number of
@@ -1039,12 +1039,12 @@ int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
size_t maxtransfer;
int ret = OK;
- dmavdbg("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
+ dmainfo("dmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
dmach, (int)paddr, (int)maddr, (int)nbytes);
DEBUGASSERT(dmach);
#if CONFIG_SAMDL_DMAC_NDESC > 0
- dmavdbg("dc_head: %p dc_tail: %p\n", dmach->dc_head, dmach->dc_tail);
+ dmainfo("dc_head: %p dc_tail: %p\n", dmach->dc_head, dmach->dc_tail);
#endif
/* The maximum transfer size in bytes depends upon the maximum number of
@@ -1115,7 +1115,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
uint8_t memqos;
int ret = -EINVAL;
- dmavdbg("dmach: %p callback: %p arg: %p\n", dmach, callback, arg);
+ dmainfo("dmach: %p callback: %p arg: %p\n", dmach, callback, arg);
DEBUGASSERT(dmach != NULL && dmach->dc_chan < SAMDL_NDMACHAN);
head = &g_base_desc[dmach->dc_chan];
@@ -1240,7 +1240,7 @@ void sam_dmastop(DMA_HANDLE handle)
struct sam_dmach_s *dmach = (struct sam_dmach_s *)handle;
irqstate_t flags;
- dmavdbg("dmach: %p\n", dmach);
+ dmainfo("dmach: %p\n", dmach);
DEBUGASSERT(dmach != NULL);
flags = enter_critical_section();
@@ -1259,7 +1259,7 @@ void sam_dmastop(DMA_HANDLE handle)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
{
struct sam_dmach_s *dmach = (struct sam_dmach_s *)handle;
@@ -1274,7 +1274,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
regs->crcdatain = getreg32(SAM_DMAC_CRCDATAIN); /* CRC Data Input Register */
regs->crcchksum = getreg32(SAM_DMAC_CRCCHKSUM); /* CRC Checksum Register */
regs->crcstatus = getreg8(SAM_DMAC_CRCSTATUS); /* CRC Status Register */
- regs->dbgctrl = getreg8(SAM_DMAC_DBGCTRL); /* Debug Control Register */
+ regs->errctrl = getreg8(SAM_DMAC_DBGCTRL); /* Debug Control Register */
regs->qosctrl = getreg8(SAM_DMAC_QOSCTRL); /* Quality of Service Control Register */
regs->swtrigctrl = getreg32(SAM_DMAC_SWTRIGCTRL); /* Software Trigger Control Register */
regs->prictrl0 = getreg32(SAM_DMAC_PRICTRL0); /* Priority Control 0 Register */
@@ -1291,7 +1291,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
regs->chintflag = getreg8(SAM_DMAC_CHINTFLAG); /* Channel Interrupt Flag Status and Clear Register */
regs->chstatus = getreg8(SAM_DMAC_CHSTATUS); /* Channel Status Register */
}
-#endif /* CONFIG_DEBUG_DMA */
+#endif /* CONFIG_DEBUG_DMA_INFO */
/****************************************************************************
* Name: sam_dmadump
@@ -1304,26 +1304,26 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
const char *msg)
{
struct sam_dmach_s *dmach = (struct sam_dmach_s *)handle;
- dmadbg("%s\n", msg);
- dmadbg(" DMAC Registers:\n");
- dmadbg(" CTRL: %04x CRCCTRL: %04x CRCDATAIN: %08x CRCCHKSUM: %08x\n",
- regs->ctrl, regs->crcctrl, regs->crcdatain, regs->crcchksum);
- dmadbg(" CRCSTATUS: %02x DBGCTRL: %02x QOSCTRL: %02x SWTRIGCTRL: %08x\n",
- regs->crcstatus, regs->dbgctrl, regs->qosctrl, regs->swtrigctrl);
- dmadbg(" PRICTRL0: %08x INTPEND: %04x INSTSTATUS: %08x BUSYCH: %08x\n",
- regs->prictrl0, regs->intpend, regs->intstatus, regs->busych);
- dmadbg(" PENDCH: %08x ACTIVE: %08x BASEADDR: %08x WRBADDR: %08x\n",
- regs->pendch, regs->active, regs->baseaddr, regs->wrbaddr);
- dmadbg(" CHID: %02x CHCRTRLA: %02x CHCRTRLB: %08x CHINFLAG: %02x\n",
- regs->chid, regs->chctrla, regs->chctrlb, regs->chintflag,
- dmadbg(" CHSTATUS: %02x\n",
- regs->chstatus);
+ dmainfo("%s\n", msg);
+ dmainfo(" DMAC Registers:\n");
+ dmainfo(" CTRL: %04x CRCCTRL: %04x CRCDATAIN: %08x CRCCHKSUM: %08x\n",
+ regs->ctrl, regs->crcctrl, regs->crcdatain, regs->crcchksum);
+ dmainfo(" CRCSTATUS: %02x DBGCTRL: %02x QOSCTRL: %02x SWTRIGCTRL: %08x\n",
+ regs->crcstatus, regs->errctrl, regs->qosctrl, regs->swtrigctrl);
+ dmainfo(" PRICTRL0: %08x INTPEND: %04x INSTSTATUS: %08x BUSYCH: %08x\n",
+ regs->prictrl0, regs->intpend, regs->intstatus, regs->busych);
+ dmainfo(" PENDCH: %08x ACTIVE: %08x BASEADDR: %08x WRBADDR: %08x\n",
+ regs->pendch, regs->active, regs->baseaddr, regs->wrbaddr);
+ dmainfo(" CHID: %02x CHCRTRLA: %02x CHCRTRLB: %08x CHINFLAG: %02x\n",
+ regs->chid, regs->chctrla, regs->chctrlb, regs->chintflag,
+ dmainfo(" CHSTATUS: %02x\n",
+ regs->chstatus);
}
-#endif /* CONFIG_DEBUG_DMA */
+#endif /* CONFIG_DEBUG_DMA_INFO */
#endif /* CONFIG_SAMDL_DMAC */
diff --git a/arch/arm/src/samdl/sam_dmac.h b/arch/arm/src/samdl/sam_dmac.h
index cc1c60e7a0cd781d2d37aed06b533b53428ccd0b..2a6937dd6820014c626c3a88d8c86b2655b26471 100644
--- a/arch/arm/src/samdl/sam_dmac.h
+++ b/arch/arm/src/samdl/sam_dmac.h
@@ -62,12 +62,6 @@
* Pre-processor Definitions
************************************************************************************/
-/* Configuration ********************************************************************/
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_DMA
-#endif
-
/* DMA ******************************************************************************/
/* Flags used to characterize the desired DMA channel. The naming convention is that
@@ -157,7 +151,7 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
struct sam_dmaregs_s
{
/* DMAC Registers */
@@ -321,7 +315,7 @@ void sam_dmastop(DMA_HANDLE handle);
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs);
#else
# define sam_dmasample(handle,regs)
@@ -335,7 +329,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs);
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
const char *msg);
#else
diff --git a/arch/arm/src/samdl/sam_idle.c b/arch/arm/src/samdl/sam_idle.c
index be58de12be6351cf9b21f970441e583dcb33a8f0..b791f991191802b2f40b21a88efa6d431d23476c 100644
--- a/arch/arm/src/samdl/sam_idle.c
+++ b/arch/arm/src/samdl/sam_idle.c
@@ -99,7 +99,7 @@ static void up_idlepm(void)
/* Perform board-specific, state-dependent logic here */
- llvdbg("newstate= %d oldstate=%d\n", newstate, oldstate);
+ _info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
diff --git a/arch/arm/src/samdl/sam_irq.c b/arch/arm/src/samdl/sam_irq.c
index 3f12b9943ac58f79823e36f3b285fd8f5b8c9834..025c20081825d7b0736386a1c346ac9ed1cbf419 100644
--- a/arch/arm/src/samdl/sam_irq.c
+++ b/arch/arm/src/samdl/sam_irq.c
@@ -93,11 +93,11 @@ volatile uint32_t *g_current_regs[1];
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
static int sam_nmi(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! NMI received\n");
+ _err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
@@ -105,7 +105,7 @@ static int sam_nmi(int irq, FAR void *context)
static int sam_pendsv(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! PendSV received\n");
+ _err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
@@ -113,7 +113,7 @@ static int sam_pendsv(int irq, FAR void *context)
static int sam_reserved(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Reserved interrupt\n");
+ _err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
@@ -192,7 +192,7 @@ void up_irqinitialize(void)
/* Attach all other processor exceptions (except reset and sys tick) */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
irq_attach(SAM_IRQ_NMI, sam_nmi);
irq_attach(SAM_IRQ_PENDSV, sam_pendsv);
irq_attach(SAM_IRQ_RESERVED, sam_reserved);
@@ -299,34 +299,34 @@ void up_ack_irq(int irq)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_IRQ
+#ifdef CONFIG_DEBUG_IRQ_INFO
void sam_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
- lldbg("NVIC (%s, irq=%d):\n", msg, irq);
- lldbg(" ISER: %08x ICER: %08x\n",
- getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
- lldbg(" ISPR: %08x ICPR: %08x\n",
- getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
- lldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
- getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
- getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
- getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
-
- lldbg("SYSCON:\n");
- lldbg(" CPUID: %08x\n",
- getreg32(ARMV6M_SYSCON_CPUID));
- lldbg(" ICSR: %08x AIRCR: %08x\n",
- getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
- lldbg(" SCR: %08x CCR: %08x\n",
- getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
- lldbg(" SHPR2: %08x SHPR3: %08x\n",
- getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
+ irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
+ irqinfo(" ISER: %08x ICER: %08x\n",
+ getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
+ irqinfo(" ISPR: %08x ICPR: %08x\n",
+ getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
+ irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
+ getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
+ getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
+ getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
+
+ irqinfo("SYSCON:\n");
+ irqinfo(" CPUID: %08x\n",
+ getreg32(ARMV6M_SYSCON_CPUID));
+ irqinfo(" ICSR: %08x AIRCR: %08x\n",
+ getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
+ irqinfo(" SCR: %08x CCR: %08x\n",
+ getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
+ irqinfo(" SHPR2: %08x SHPR3: %08x\n",
+ getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
}
diff --git a/arch/arm/src/samdl/sam_irq.h b/arch/arm/src/samdl/sam_irq.h
index ddc5a7ada5204f9a5a3bd116b68f513aaf567f3a..ea26cbd159364058cf0582e2a614b279bb0e7b1f 100644
--- a/arch/arm/src/samdl/sam_irq.h
+++ b/arch/arm/src/samdl/sam_irq.h
@@ -43,23 +43,7 @@
#include
/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
+ * Public Function Prototypes
************************************************************************************/
/****************************************************************************
@@ -70,7 +54,7 @@
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_IRQ
+#ifdef CONFIG_DEBUG_IRQ_INFO
void sam_dumpnvic(const char *msg, int irq);
#else
# define sam_dumpnvic(msg, irq)
diff --git a/arch/arm/src/samdl/sam_port.c b/arch/arm/src/samdl/sam_port.c
index 53c8664efdf97d96710f7312521b6c14b2cfb472..8ba1e1f88cb94bdb5fa1ff81b79dcf034c9abe91 100644
--- a/arch/arm/src/samdl/sam_port.c
+++ b/arch/arm/src/samdl/sam_port.c
@@ -62,7 +62,7 @@
* Private Data
****************************************************************************/
-#ifdef CONFIG_DEBUG_PORT
+#ifdef CONFIG_DEBUG_GPIO_INFO
static const char g_portchar[2] = { 'A', 'B' };
#endif
@@ -521,7 +521,7 @@ bool sam_portread(port_pinset_t pinset)
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_PORT
+#ifdef CONFIG_DEBUG_GPIO_INFO
int sam_dumpport(uint32_t pinset, const char *msg)
{
irqstate_t flags;
@@ -538,20 +538,20 @@ int sam_dumpport(uint32_t pinset, const char *msg)
/* The following requires exclusive access to the PORT registers */
flags = enter_critical_section();
- lldbg("PORT%c pin: %d pinset: %08x base: %08x -- %s\n",
- g_portchar[port], pin, pinset, base, msg);
- lldbg(" DIR: %08x OUT: %08x IN: %08x\n",
- getreg32(base + SAM_PORT_DIR_OFFSET),
- getreg32(base + SAM_PORT_OUT_OFFSET),
- getreg32(base + SAM_PORT_IN_OFFSET));
- lldbg(" CTRL: %08x WRCONFIG: %08x\n",
- getreg32(base + SAM_PORT_CTRL_OFFSET),
- getreg32(base + SAM_PORT_WRCONFIG_OFFSET));
- lldbg(" PMUX[%08x]: %02x PINCFG[%08x]: %02x\n",
- base + SAM_PORT_PMUX_OFFSET(pin),
- getreg8(base + SAM_PORT_PMUX_OFFSET(pin)),
- base + SAM_PORT_PINCFG_OFFSET(pin),
- getreg8(base + SAM_PORT_PINCFG_OFFSET(pin)));
+ gpioinfo("PORT%c pin: %d pinset: %08x base: %08x -- %s\n",
+ g_portchar[port], pin, pinset, base, msg);
+ gpioinfo(" DIR: %08x OUT: %08x IN: %08x\n",
+ getreg32(base + SAM_PORT_DIR_OFFSET),
+ getreg32(base + SAM_PORT_OUT_OFFSET),
+ getreg32(base + SAM_PORT_IN_OFFSET));
+ gpioinfo(" CTRL: %08x WRCONFIG: %08x\n",
+ getreg32(base + SAM_PORT_CTRL_OFFSET),
+ getreg32(base + SAM_PORT_WRCONFIG_OFFSET));
+ gpioinfo(" PMUX[%08x]: %02x PINCFG[%08x]: %02x\n",
+ base + SAM_PORT_PMUX_OFFSET(pin),
+ getreg8(base + SAM_PORT_PMUX_OFFSET(pin)),
+ base + SAM_PORT_PINCFG_OFFSET(pin),
+ getreg8(base + SAM_PORT_PINCFG_OFFSET(pin)));
leave_critical_section(flags);
return OK;
diff --git a/arch/arm/src/samdl/sam_port.h b/arch/arm/src/samdl/sam_port.h
index 26ba8bcb5d3562617a54ab2552d2cc20cba4a2f1..3e9704cd141fe23b4c71e1c76e90b1a336b9c78b 100644
--- a/arch/arm/src/samdl/sam_port.h
+++ b/arch/arm/src/samdl/sam_port.h
@@ -379,7 +379,7 @@ bool sam_portread(port_pinset_t pinset);
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
int sam_dumpport(port_pinset_t pinset, const char *msg);
#else
# define sam_dumpport(p,m)
diff --git a/arch/arm/src/samdl/sam_sercom.c b/arch/arm/src/samdl/sam_sercom.c
index ae50ca39c1e3a779a2d481782f713a60517951ea..779db03738fff4175e4f97ba20d3277d9a41859c 100644
--- a/arch/arm/src/samdl/sam_sercom.c
+++ b/arch/arm/src/samdl/sam_sercom.c
@@ -68,14 +68,6 @@
# define HAVE_SERCOM0_4
#endif
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -162,9 +154,9 @@ void sercom_slowclk_configure(int sercom, int gclkgen)
#ifdef CONFIG_SAMDL_SERCOM5
static bool configured5 = false;
#endif
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_ASSERTIONS
#ifdef HAVE_SERCOM0_4
- static uint8_t slowgen = 0xff;
+ static uint8_t slowgen04 = 0xff;
#endif
#ifdef CONFIG_SAMDL_SERCOM5
static uint8_t slowgen5 = 0xff;
@@ -205,19 +197,19 @@ void sercom_slowclk_configure(int sercom, int gclkgen)
*/
configured = true;
-#ifdef CONFIG_DEBUG
- slowgen = (uint8_t)gclkgen;
+#ifdef CONFIG_DEBUG_ASSERTIONS
+ slowgen04 = (uint8_t)gclkgen;
#endif
}
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_ASSERTIONS
/* Already configured. This is okay provided that the same GCLK
* generator is being used. Otherwise, there is a problem.
*/
else
{
- DEBUGASSERT((int)slowgen == gclkgen);
+ DEBUGASSERT((int)slowgen04 == gclkgen);
}
#endif
break;
@@ -236,12 +228,12 @@ void sercom_slowclk_configure(int sercom, int gclkgen)
*/
configured5 = true;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_ASSERTIONS
slowgen5 = (uint8_t)gclkgen;
#endif
}
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_ASSERTIONS
/* Already configured. This is okay provided that the same GCLK
* generator is being used. Otherwise, there is a problem.
*/
diff --git a/arch/arm/src/samdl/sam_spi.c b/arch/arm/src/samdl/sam_spi.c
index 2a7df796bac1498d4ada4b8e47f25eb67f556605..ac7ea3d2cc2cf1e30d219a5490e4ed2eaea3e774 100644
--- a/arch/arm/src/samdl/sam_spi.c
+++ b/arch/arm/src/samdl/sam_spi.c
@@ -74,34 +74,13 @@
#ifdef SAMDL_HAVE_SPI
/****************************************************************************
- * Pre-processor Definitions
+ * Pre-process Definitions
****************************************************************************/
-/* Clocking *****************************************************************/
-
-/* Debug *******************************************************************/
-/* Check if SPI debug is enabled (non-standard.. no support in
- * include/debug.h
- */
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# undef CONFIG_DEBUG_SPI
+#ifndef CONFIG_DEBUG_SPI_INFO
# undef CONFIG_SAMDL_SPI_REGDEBUG
#endif
-#ifdef CONFIG_DEBUG_SPI
-# define spidbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define spivdbg lldbg
-# else
-# define spivdbg(x...)
-# endif
-#else
-# define spidbg(x...)
-# define spivdbg(x...)
-#endif
-
/****************************************************************************
* Private Types
****************************************************************************/
@@ -175,7 +154,7 @@ static uint32_t spi_getreg32(struct sam_spidev_s *priv,
static void spi_putreg32(struct sam_spidev_s *priv, uint32_t regval,
unsigned int offset);
-#if defined(CONFIG_DEBUG_SPI) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_SPI_INFO
static void spi_dumpregs(struct sam_spidev_s *priv, const char *msg);
#else
# define spi_dumpregs(priv,msg)
@@ -569,7 +548,7 @@ static bool spi_checkreg(struct sam_spidev_s *priv, bool wr, uint32_t regval,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", priv->ntimes);
+ spiinfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@@ -602,7 +581,7 @@ static uint8_t spi_getreg8(struct sam_spidev_s *priv, unsigned int offset)
#ifdef CONFIG_SAMDL_SPI_REGDEBUG
if (spi_checkreg(priv, false, (uint32_t)regval, regaddr))
{
- lldbg("%08x->%02x\n", regaddr, regval);
+ spiinfo("%08x->%02x\n", regaddr, regval);
}
#endif
@@ -625,7 +604,7 @@ static void spi_putreg8(struct sam_spidev_s *priv, uint8_t regval,
#ifdef CONFIG_SAMDL_SPI_REGDEBUG
if (spi_checkreg(priv, true, (uint32_t)regval, regaddr))
{
- lldbg("%08x<-%02x\n", regaddr, regval);
+ spiinfo("%08x<-%02x\n", regaddr, regval);
}
#endif
@@ -648,7 +627,7 @@ static uint16_t spi_getreg16(struct sam_spidev_s *priv, unsigned int offset)
#ifdef CONFIG_SAMDL_SPI_REGDEBUG
if (spi_checkreg(priv, false, (uint32_t)regval, regaddr))
{
- lldbg("%08x->%04x\n", regaddr, regval);
+ spiinfo("%08x->%04x\n", regaddr, regval);
}
#endif
@@ -671,7 +650,7 @@ static void spi_putreg16(struct sam_spidev_s *priv, uint16_t regval,
#ifdef CONFIG_SAMDL_SPI_REGDEBUG
if (spi_checkreg(priv, true, (uint32_t)regval, regaddr))
{
- lldbg("%08x<-%04x\n", regaddr, regval);
+ spiinfo("%08x<-%04x\n", regaddr, regval);
}
#endif
@@ -694,7 +673,7 @@ static uint32_t spi_getreg32(struct sam_spidev_s *priv, unsigned int offset)
#ifdef CONFIG_SAMDL_SPI_REGDEBUG
if (spi_checkreg(priv, false, regval, regaddr))
{
- lldbg("%08x->%08x\n", regaddr, regval);
+ spiinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@@ -717,7 +696,7 @@ static void spi_putreg32(struct sam_spidev_s *priv, uint32_t regval,
#ifdef CONFIG_SAMDL_SPI_REGDEBUG
if (spi_checkreg(priv, true, regval, regaddr))
{
- lldbg("%08x<-%08x\n", regaddr, regval);
+ spiinfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@@ -739,19 +718,19 @@ static void spi_putreg32(struct sam_spidev_s *priv, uint32_t regval,
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_SPI) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_SPI_INFO
static void spi_dumpregs(struct sam_spidev_s *priv, const char *msg)
{
- spivdbg("%s:\n", msg);
- spivdbg(" CTRLA:%08x CTRLB:%08x DBGCTRL:%02x\n",
+ spiinfo("%s:\n", msg);
+ spiinfo(" CTRLA:%08x CTRLB:%08x DBGCTRL:%02x\n",
getreg32(priv->base + SAM_SPI_CTRLA_OFFSET),
getreg32(priv->base + SAM_SPI_CTRLB_OFFSET),
getreg8(priv->base + SAM_SPI_DBGCTRL_OFFSET));
- spivdbg(" BAUD:%02x INTEN:%02x INTFLAG:%02x\n",
+ spiinfo(" BAUD:%02x INTEN:%02x INTFLAG:%02x\n",
getreg8(priv->base + SAM_SPI_BAUD_OFFSET),
getreg8(priv->base + SAM_SPI_INTENCLR_OFFSET),
getreg8(priv->base + SAM_SPI_INTFLAG_OFFSET));
- spivdbg(" STATUS:%04x ADDR:%08x\n",
+ spiinfo(" STATUS:%04x ADDR:%08x\n",
getreg16(priv->base + SAM_SPI_STATUS_OFFSET),
getreg32(priv->base + SAM_SPI_ADDR_OFFSET));
}
@@ -890,7 +869,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock)
{
struct sam_spidev_s *priv = (struct sam_spidev_s *)dev;
- spivdbg("lock=%d\n", lock);
+ spiinfo("lock=%d\n", lock);
if (lock)
{
/* Take the semaphore (perhaps waiting) */
@@ -935,7 +914,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
uint32_t baud;
uint32_t ctrla;
- spivdbg("sercom=%d frequency=%d\n", priv->sercom, frequency);
+ spiinfo("sercom=%d frequency=%d\n", priv->sercom, frequency);
/* Check if the configured BAUD is within the valid range */
@@ -944,7 +923,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
{
/* Set the frequency to the maximum */
- spidbg("ERROR: Cannot realize frequency: %ld\n", (long)frequency);
+ spierr("ERROR: Cannot realize frequency: %ld\n", (long)frequency);
frequency = maxfreq;
}
@@ -975,7 +954,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
if (baud > 255)
{
- spidbg("ERROR: BAUD is out of range: %ld\n", (long)baud);
+ spierr("ERROR: BAUD is out of range: %ld\n", (long)baud);
baud = 255;
}
@@ -1016,7 +995,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
priv->frequency = frequency;
priv->actual = actual;
- spivdbg("Frequency %d->%d\n", frequency, actual);
+ spiinfo("Frequency %d->%d\n", frequency, actual);
return actual;
}
@@ -1040,7 +1019,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
struct sam_spidev_s *priv = (struct sam_spidev_s *)dev;
uint32_t regval;
- spivdbg("sercom=%d mode=%d\n", priv->sercom, mode);
+ spiinfo("sercom=%d mode=%d\n", priv->sercom, mode);
/* Has the mode changed? */
@@ -1101,7 +1080,7 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
struct sam_spidev_s *priv = (struct sam_spidev_s *)dev;
uint32_t regval;
- spivdbg("sercom=%d nbits=%d\n", priv->sercom, nbits);
+ spiinfo("sercom=%d nbits=%d\n", priv->sercom, nbits);
DEBUGASSERT(priv && nbits > 7 && nbits < 10);
/* Has the number of bits changed? */
@@ -1156,7 +1135,7 @@ static uint16_t spi_send(struct spi_dev_s *dev, uint16_t wd)
rxbyte = (uint8_t)0;
spi_exchange(dev, &txbyte, &rxbyte, 1);
- spivdbg("Sent %02x received %02x\n", txbyte, rxbyte);
+ spiinfo("Sent %02x received %02x\n", txbyte, rxbyte);
return (uint16_t)rxbyte;
}
@@ -1194,7 +1173,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
uint8_t *prx8;
uint16_t data;
- spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
+ spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
/* Set up data receive and transmit pointers */
@@ -1281,7 +1260,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
data = spi_getreg16(priv, SAM_SPI_STATUS_OFFSET);
if ((data & SPI_STATUS_BUFOVF) != 0)
{
- spidbg("ERROR: Buffer overflow!\n");
+ spierr("ERROR: Buffer overflow!\n");
/* Clear the buffer overflow flag */
@@ -1438,7 +1417,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
/* Get the port state structure */
- spivdbg("port: %d \n", port);
+ spiinfo("port: %d \n", port);
#ifdef SAMDL_HAVE_SPI0
if (port == 0)
@@ -1488,7 +1467,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
else
#endif
{
- spidbg("ERROR: Unsupported port: %d\n", port);
+ spierr("ERROR: Unsupported port: %d\n", port);
return NULL;
}
@@ -1570,7 +1549,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
ret = irq_attach(priv->irq, priv->handler);
if (ret < 0)
{
- spidbg("ERROR: Failed to attach interrupt: %d\n", irq);
+ spierr("ERROR: Failed to attach interrupt: %d\n", irq);
return NULL;
}
diff --git a/arch/arm/src/samdl/sam_start.c b/arch/arm/src/samdl/sam_start.c
index e31a1b274df320404f28896d39d68c8dc8ddd299..f46e114fd66e41b78858a7151ca856d5ae723a27 100644
--- a/arch/arm/src/samdl/sam_start.c
+++ b/arch/arm/src/samdl/sam_start.c
@@ -91,7 +91,7 @@ const uint32_t g_idle_topstack = IDLE_STACK;
*
****************************************************************************/
-#if defined(CONFIG_DEBUG) && defined(HAVE_SERIAL_CONSOLE)
+#if defined(CONFIG_DEBUG_FEATURES) && defined(HAVE_SERIAL_CONSOLE)
# define showprogress(c) sam_lowputc((uint32_t)c)
#else
# define showprogress(c)
diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig
index 7a7d75c840844a32a17dbd895af281686e6834ab..9507e0c59c842e4897254f332795f2124e8edb14 100644
--- a/arch/arm/src/samv7/Kconfig
+++ b/arch/arm/src/samv7/Kconfig
@@ -687,8 +687,8 @@ config SAMV7_WDT_INTERRUPT
config SAMV7_WDT_DEBUGHALT
bool "Halt on DEBUG"
- default y if DEBUG
- default n if !DEBUG
+ default y if DEBUG_FEATURES
+ default n if !DEBUG_FEATURES
---help---
Halt the watchdog timer in the debug state
@@ -701,7 +701,7 @@ config SAMV7_WDT_IDLEHALT
config SAMV7_WDT_REGDEBUG
bool "Register level debug"
default n
- depends on DEBUG
+ depends on DEBUG_WATCHDOG_INFO
---help---
Enable low-level register debug output
@@ -721,8 +721,8 @@ config SAMV7_RSWDT_INTERRUPT
config SAMV7_RSWDT_DEBUGHALT
bool "Halt on DEBUG"
- default y if DEBUG
- default n if !DEBUG
+ default y if DEBUG_FEATURES
+ default n if !DEBUG_FEATURES
---help---
Halt the watchdog timer in the debug state
@@ -735,7 +735,7 @@ config SAMV7_RSWDT_IDLEHALT
config SAMV7_RSWDT_REGDEBUG
bool "Register level debug"
default n
- depends on DEBUG
+ depends on DEBUG_WATCHDOG_INFO
---help---
Enable low-level register debug output
@@ -835,6 +835,23 @@ config SAMV7_SPI_CS_DECODING
---help---
Use Peripheral Chip Select Decoding on SPI Master
+config SAMV7_SPI_VARSELECT
+ bool "SPI Variable Peripheral Select Mode"
+ default n
+ ---help---
+ When enabled, the spi device is working in the "Variable Peripheral
+ Select Mode" (VARMODE) instead of the "Fixed Peripheral Select Mode"
+ (FIXEDMODE).
+
+ In FIXEDMODE the ChipSelect is set (once) with a call to spi_select and
+ stays the same value all the time. In addition an eventually signaled
+ LASTXFER has to be written to the global control register (SPI_CR).
+ Within the VARMODE, the ChipSelect can be changed with each datablock
+ transferred via spi_exchange because it is encoded by the driver
+ within the data.
+
+ The same behavior applies for the LASTXFER bit.
+
config SAMV7_SPI_DMA
bool "SPI DMA"
default n
@@ -853,7 +870,7 @@ config SAMV7_SPI_DMATHRESHOLD
config SAMV7_SPI_DMADEBUG
bool "SPI DMA transfer debug"
- depends on SAMV7_SPI_DMA && DEBUG && DEBUG_DMA
+ depends on SAMV7_SPI_DMA && DEBUG_FEATURES && DEBUG_DMA
default n
---help---
Enable special debug instrumentation analyze SPI DMA data transfers.
@@ -877,11 +894,11 @@ endif # SAMV7_SPI_SLAVE
config SAMV7_SPI_REGDEBUG
bool "SPI Register level debug"
- depends on DEBUG
+ depends on DEBUG_SPI_INFO
default n
---help---
Output detailed register-level SPI device debug information.
- Requires also DEBUG.
+ Requires also CONFIG_DEBUG_SPI_INFO.
endmenu # SPI device driver options
@@ -914,7 +931,7 @@ config SAMV7_QSPI_DMATHRESHOLD
config SAMV7_QSPI_DMADEBUG
bool "QSPI DMA transfer debug"
- depends on SAMV7_QSPI_DMA && DEBUG && DEBUG_DMA
+ depends on SAMV7_QSPI_DMA && DEBUG_FEATURES && DEBUG_DMA
default n
---help---
Enable special debug instrumentation analyze QSPI DMA data transfers.
@@ -924,11 +941,11 @@ config SAMV7_QSPI_DMADEBUG
config SAMV7_QSPI_REGDEBUG
bool "QSPI Register level debug"
- depends on DEBUG
+ depends on DEBUG_SPI_INFO
default n
---help---
Output detailed register-level QSPI device debug information.
- Requires also DEBUG.
+ Requires also CONFIG_DEBUG_SPI_INFO.
endmenu # QSPI device driver options
@@ -940,23 +957,92 @@ config SAMV7_TWIHS0_FREQUENCY
default 100000
depends on SAMV7_TWIHS0
+config SAMV7_TWIHS0_GLITCH_FILTER
+ int "TWIHS0 Glitch Filter Time"
+ default 1
+ range 0 7
+ depends on SAMV7_TWIHS0
+ ---help---
+ Apply filtering on TWIHS Inputs. Given number is the maximum pulse width
+ (defined in peripheral CLKs) of spikes to be suppressed by the input filter.
+ Setting this value to zero will disable glitch filtering.
+
+config SAMV7_TWIHS0_SINGLE_MASTER
+ bool "TWIHS0 Single Master Mode"
+ default y
+ depends on SAMV7_TWIHS0
+ depends on I2C_RESET
+ ---help---
+ Enables a mode, where errors on the I2C-Bus (e.g. by EMC or
+ stuck slaves) are automatically handled by the driver.
+ In an error-case the I2C-Bus is reset so further communication
+ on the bus can take place.
+ This option is default on because the TWI-Driver can't handle
+ Multi-Master I2C anyways.
+
config SAMV7_TWIHS1_FREQUENCY
int "TWIHS1 Frequency"
default 100000
depends on SAMV7_TWIHS1
+config SAMV7_TWIHS1_GLITCH_FILTER
+ int "TWIHS1 Glitch Filter Time"
+ default 1
+ range 0 7
+ depends on SAMV7_TWIHS1
+ ---help---
+ Apply filtering on TWIHS Inputs. Given number is the maximum pulse width
+ (defined in peripheral CLKs) of spikes to be suppressed by the input filter.
+ Setting this value to zero will disable glitch filtering.
+
+config SAMV7_TWIHS1_SINGLE_MASTER
+ bool "TWIHS1 Single Master Mode"
+ default y
+ depends on SAMV7_TWIHS1
+ depends on I2C_RESET
+ ---help---
+ Enables a mode, where errors on the I2C-Bus (e.g. by EMC or
+ stuck slaves) are automatically handled by the driver.
+ In an error-case the I2C-Bus is reset so further communication
+ on the bus can take place.
+ This option is default on because the TWI-Driver can't handle
+ Multi-Master I2C anyways.
+
config SAMV7_TWIHS2_FREQUENCY
int "TWIHS2 Frequency"
default 100000
depends on SAMV7_TWIHS2
+config SAMV7_TWIHS2_GLITCH_FILTER
+ int "TWIHS2 Glitch Filter Time"
+ default 1
+ range 0 7
+ depends on SAMV7_TWIHS2
+ ---help---
+ Apply filtering on TWIHS Inputs. Given number is the maximum pulse width
+ (defined in peripheral CLKs) of spikes to be suppressed by the input filter.
+ Setting this value to zero will disable glitch filtering.
+
+config SAMV7_TWIHS2_SINGLE_MASTER
+ bool "TWIHS2 Single Master Mode"
+ default y
+ depends on SAMV7_TWIHS2
+ depends on I2C_RESET
+ ---help---
+ Enables a mode, where errors on the I2C-Bus (e.g. by EMC or
+ stuck slaves) are automatically handled by the driver.
+ In an error-case the I2C-Bus is reset so further communication
+ on the bus can take place.
+ This option is default on because the TWI-Driver can't handle
+ Multi-Master I2C anyways.
+
config SAMV7_TWIHS_REGDEBUG
bool "TWIHS register level debug"
- depends on DEBUG
+ depends on DEBUG_I2C_INFO
default n
---help---
Output detailed register-level TWIHS device debug information.
- Very invasive! Requires also DEBUG.
+ Very invasive! Requires also CONFIG_DEBUG_I2C_INFO.
endmenu # TWIHS device driver options
@@ -1318,7 +1404,7 @@ endif # SAMV7_SSC1
config SAMV7_SSC_DMADEBUG
bool "SSC DMA transfer debug"
- depends on DEBUG && DEBUG_DMA
+ depends on DEBUG_FEATURES && DEBUG_DMA
default n
---help---
Enable special debug instrumentation analyze SSC DMA data transfers.
@@ -1328,11 +1414,11 @@ config SAMV7_SSC_DMADEBUG
config SAMV7_SSC_REGDEBUG
bool "SSC Register level debug"
- depends on DEBUG
+ depends on DEBUG_I2S_INFO
default n
---help---
Output detailed register-level SSC device debug information.
- Very invasive! Requires also DEBUG.
+ Very invasive! Requires also CONFIG_DEBUG_I2S_INFO.
config SAMV7_SSC_QDEBUG
bool "SSC Queue debug"
@@ -1551,23 +1637,23 @@ endif
config SAMV7_TC_DEBUG
bool "TC debug"
- depends on DEBUG
+ depends on DEBUG_FEATURES
default n
---help---
Output high level Timer/Counter device debug information.
- Requires also DEBUG. If this option AND DEBUG_VERBOSE are
+ Requires also CONFIG_DEBUG_FEATURES. If this option AND CONFIG_DEBUG_INFO are
enabled, then the system will be overwhelmed the timer debug
- output. If DEBUG_VERBOSE is disabled, then debug output will
+ output. If CONFIG_DEBUG_INFO is disabled, then debug output will
only indicate if/when timer-related errors occur. This
latter mode is completely usable.
config SAMV7_TC_REGDEBUG
bool "TC register level debug"
- depends on DEBUG
+ depends on DEBUG_TIMER_INFO
default n
---help---
Output detailed register-level Timer/Counter device debug
- information. Very invasive! Requires also DEBUG.
+ information. Very invasive! Requires also CONFIG_DEBUG_TIMER_INFO.
endmenu # Timer/counter Configuration
endif # SAMV7_HAVE_TC
@@ -1617,7 +1703,7 @@ config SAMV7_HSMCI_UNALIGNED
config SAMV7_HSMCI_XFRDEBUG
bool "HSMCI transfer debug"
- depends on DEBUG_FS && DEBUG_VERBOSE
+ depends on DEBUG_FS_INFO
default n
---help---
Enable special debug instrumentation analyze HSMCI data transfers.
@@ -1625,11 +1711,11 @@ config SAMV7_HSMCI_XFRDEBUG
registers at key points in the data transfer and then dumps all of
the registers at the end of the transfer. If DEBUG_DMA is also
enabled, then DMA register will be collected as well. Requires also
- DEBUG_FS and DEBUG_VERBOSE.
+ DEBUG_FS and CONFIG_DEBUG_INFO.
config SAMV7_HSMCI_CMDDEBUG
bool "HSMCI command debug"
- depends on DEBUG_FS && DEBUG_VERBOSE
+ depends on DEBUG_FS_INFO
default n
---help---
Enable special debug instrumentation analyze HSMCI commands. This
@@ -1637,15 +1723,15 @@ config SAMV7_HSMCI_CMDDEBUG
key points in the data transfer and then dumps all of the registers
at the end of the transfer. If DEBUG_DMA is also enabled, then DMA
register will be collected as well. Requires also DEBUG_FS and
- DEBUG_VERBOSE.
+ CONFIG_DEBUG_INFO.
config SAMV7_HSMCI_REGDEBUG
bool "HSMCI Register level debug"
- depends on DEBUG
+ depends on DEBUG_MEMCARD_INFO
default n
---help---
Output detailed register-level HSCMI device debug information.
- Very invasive! Requires also DEBUG.
+ Very invasive! Requires also DEBUG_MEMCARD_INFO.
endmenu # HSMCI device driver options
@@ -1854,7 +1940,7 @@ config SAMV7_EMAC_NBC
config SAMV7_EMAC_DEBUG
bool "Force EMAC0/1 DEBUG"
default n
- depends on DEBUG && !DEBUG_NET
+ depends on DEBUG_FEATURES && !DEBUG_NET
---help---
This option will force debug output from EMAC driver even without
network debug output enabled. This is not normally something
@@ -1865,9 +1951,9 @@ config SAMV7_EMAC_DEBUG
config SAMV7_EMAC_REGDEBUG
bool "Register-Level Debug"
default n
- depends on DEBUG
+ depends on DEBUG_NET_INFO
---help---
- Enable very low-level register access debug. Depends on DEBUG.
+ Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_INFO.
endmenu # EMAC0 device driver options
@@ -1923,7 +2009,7 @@ config SAMV7_USBHS_EP7DMA_WAR
config SAMV7_USBHS_REGDEBUG
bool "Enable low-level USBHS register debug"
default n
- depends on DEBUG
+ depends on DEBUG_USB_INFO
endmenu # USB High Speed Device Controller driver (DCD) options
@@ -2598,11 +2684,11 @@ endmenu # MCAN1 device driver options
config SAMV7_MCAN_REGDEBUG
bool "CAN Register level debug"
- depends on DEBUG
+ depends on DEBUG_CAN_INFO
default n
---help---
Output detailed register-level CAN device debug information.
- Requires also DEBUG.
+ Requires also CONFIG_DEBUG_CAN_INFO.
endmenu # CAN device driver options
endif # SAMV7_MCAN
diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c
index 39e14457dd4c56da3f2a6519b33ce04bf83e94dc..7fcedd857167a2495ada2fe44664475403cbb9fb 100644
--- a/arch/arm/src/samv7/sam_emac.c
+++ b/arch/arm/src/samv7/sam_emac.c
@@ -48,7 +48,7 @@
#include
-#if defined(CONFIG_DEBUG) && defined(CONFIG_SAMV7_EMAC_DEBUG)
+#if defined(CONFIG_DEBUG_FEATURES) && defined(CONFIG_SAMV7_EMAC_DEBUG)
/* Force debug output (from this file only) */
# undef CONFIG_DEBUG_NET
@@ -307,16 +307,16 @@
* enabled.
*/
-#ifndef CONFIG_DEBUG
-# undef CONFIG_SAMV7_EMAC_REGDEBUG
-#endif
-
#ifdef CONFIG_NET_DUMPPACKET
# define sam_dumppacket(m,a,n) lib_dumpbuffer(m,a,n)
#else
# define sam_dumppacket(m,a,n)
#endif
+#ifndef CONFIG_NET_INFO
+# undef CONFIG_SAMV7_EMAC_REGDEBUG
+#endif
+
/* EMAC buffer sizes, number of buffers, and number of descriptors ***********
*
* REVISIT: The CONFIG_NET_MULTIBUFFER might be useful. It might be possible
@@ -560,7 +560,7 @@ struct sam_emac_s
****************************************************************************/
/* Register operations ******************************************************/
-#if defined(CONFIG_SAMV7_EMAC_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAMV7_EMAC_REGDEBUG
static bool sam_checkreg(struct sam_emac_s *priv, bool wr,
uint32_t regval, uintptr_t address);
#endif
@@ -639,7 +639,7 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, long arg);
/* PHY Initialization */
-#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_VERBOSE)
+#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_INFO)
static void sam_phydump(struct sam_emac_s *priv);
#else
# define sam_phydump(priv)
@@ -966,7 +966,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", priv->ntimes);
+ ninfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@@ -999,7 +999,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uint16_t offset)
#ifdef CONFIG_SAMV7_EMAC_REGDEBUG
if (sam_checkreg(priv, false, regval, regaddr))
{
- lldbg("%08x->%08x\n", regaddr, regval);
+ ninfo("%08x->%08x\n", regaddr, regval);
}
#endif
@@ -1023,7 +1023,7 @@ static void sam_putreg(struct sam_emac_s *priv, uint16_t offset,
#ifdef CONFIG_SAMV7_EMAC_REGDEBUG
if (sam_checkreg(priv, true, regval, regaddr))
{
- lldbg("%08x<-%08x\n", regaddr, regval);
+ ninfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@@ -1147,7 +1147,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
priv->xfrq[0].txdesc = (struct emac_txdesc_s *)kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[0].txdesc)
{
- nlldbg("ERROR: Failed to allocate TX descriptors\n");
+ nerr("ERROR: Failed to allocate TX descriptors\n");
return -ENOMEM;
}
@@ -1158,7 +1158,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
priv->xfrq[0].rxdesc = (struct emac_rxdesc_s *)kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[0].rxdesc)
{
- nlldbg("ERROR: Failed to allocate RX descriptors\n");
+ nerr("ERROR: Failed to allocate RX descriptors\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -1170,7 +1170,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
priv->xfrq[0].txbuffer = (uint8_t *)kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[0].txbuffer)
{
- nlldbg("ERROR: Failed to allocate TX buffer\n");
+ nerr("ERROR: Failed to allocate TX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -1181,7 +1181,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
priv->xfrq[0].rxbuffer = (uint8_t *)kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[0].rxbuffer)
{
- nlldbg("ERROR: Failed to allocate RX buffer\n");
+ nerr("ERROR: Failed to allocate RX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -1194,7 +1194,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
priv->xfrq[1].txdesc = (struct emac_txdesc_s *)kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[1].txdesc)
{
- nlldbg("ERROR: Failed to allocate TX descriptors\n");
+ nerr("ERROR: Failed to allocate TX descriptors\n");
return -ENOMEM;
}
@@ -1205,7 +1205,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
priv->xfrq[1].rxdesc = (struct emac_rxdesc_s *)kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[1].rxdesc)
{
- nlldbg("ERROR: Failed to allocate RX descriptors\n");
+ nerr("ERROR: Failed to allocate RX descriptors\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -1217,7 +1217,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
priv->xfrq[1].txbuffer = (uint8_t *)kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[1].txbuffer)
{
- nlldbg("ERROR: Failed to allocate TX buffer\n");
+ nerr("ERROR: Failed to allocate TX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -1228,7 +1228,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
priv->xfrq[1].rxbuffer = (uint8_t *)kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[1].rxbuffer)
{
- nlldbg("ERROR: Failed to allocate RX buffer\n");
+ nerr("ERROR: Failed to allocate RX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -1369,7 +1369,7 @@ static int sam_transmit(struct sam_emac_s *priv, int qid)
if (dev->d_len > EMAC_TX_UNITSIZE)
{
- nlldbg("ERROR: Packet too big: %d\n", dev->d_len);
+ nerr("ERROR: Packet too big: %d\n", dev->d_len);
return -EINVAL;
}
@@ -1379,14 +1379,14 @@ static int sam_transmit(struct sam_emac_s *priv, int qid)
txhead = xfrq->txhead;
txdesc = &xfrq->txdesc[txhead];
- nllvdbg("d_len: %d txhead[%d]: %d\n", dev->d_len, qid, xfrq->txhead);
+ ninfo("d_len: %d txhead[%d]: %d\n", dev->d_len, qid, xfrq->txhead);
sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
/* If no free TX descriptor, buffer can't be sent */
if (sam_txfree(priv, qid) < 1)
{
- nlldbg("ERROR: No free TX descriptors\n");
+ nerr("ERROR: No free TX descriptors\n");
return -EBUSY;
}
@@ -1460,7 +1460,7 @@ static int sam_transmit(struct sam_emac_s *priv, int qid)
if (sam_txfree(priv, qid) < 1)
{
- nllvdbg("Disabling RX interrupts\n");
+ ninfo("Disabling RX interrupts\n");
sam_putreg(priv, SAM_EMAC_IDR_OFFSET, EMAC_INT_RCOMP);
}
@@ -1646,7 +1646,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
arch_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
- nllvdbg("Entry rxndx[%d]: %d\n", qid, rxndx);
+ ninfo("Entry rxndx[%d]: %d\n", qid, rxndx);
while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
{
@@ -1709,7 +1709,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
{
if (rxndx == xfrq->rxndx)
{
- nllvdbg("ERROR: No EOF (Invalid or buffers too small)\n");
+ nerr("ERROR: No EOF (Invalid or buffers too small)\n");
do
{
/* Give ownership back to the EMAC */
@@ -1767,7 +1767,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
/* Frame size from the EMAC */
dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
- nllvdbg("packet %d-%d (%d)\n", xfrq->rxndx, rxndx, dev->d_len);
+ ninfo("packet %d-%d (%d)\n", xfrq->rxndx, rxndx, dev->d_len);
/* All data have been copied in the application frame buffer,
* release the RX descriptor(s). Loop until all descriptors
@@ -1801,12 +1801,12 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
* all of the data.
*/
- nllvdbg("rxndx: %d d_len: %d\n",
- xfrq->rxndx, dev->d_len);
+ ninfo("rxndx: %d d_len: %d\n",
+ xfrq->rxndx, dev->d_len);
if (pktlen < dev->d_len)
{
- nlldbg("ERROR: Buffer size %d; frame size %d\n",
- dev->d_len, pktlen);
+ nerr("ERROR: Buffer size %d; frame size %d\n",
+ dev->d_len, pktlen);
NETDEV_RXERRORS(&priv->dev);
return -E2BIG;
}
@@ -1854,7 +1854,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
/* No packet was found */
xfrq->rxndx = rxndx;
- nllvdbg("Exit rxndx[%d]: %d\n", qid, xfrq->rxndx);
+ ninfo("Exit rxndx[%d]: %d\n", qid, xfrq->rxndx);
return -EAGAIN;
}
@@ -1896,7 +1896,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid)
if (dev->d_len > CONFIG_NET_ETH_MTU)
{
- nlldbg("DROPPED: Too big: %d\n", dev->d_len);
+ nwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
NETDEV_RXERRORS(&priv->dev);
continue;
}
@@ -1912,7 +1912,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
- nllvdbg("IPv4 frame\n");
+ ninfo("IPv4 frame\n");
NETDEV_RXIPV4(&priv->dev);
/* Handle ARP on input then give the IPv4 packet to the network
@@ -1953,7 +1953,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
- nllvdbg("Iv6 frame\n");
+ ninfo("Iv6 frame\n");
NETDEV_RXIPV6(&priv->dev);
/* Give the IPv6 packet to the network layer */
@@ -1991,7 +1991,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
- nllvdbg("ARP frame\n");
+ ninfo("ARP frame\n");
NETDEV_RXARP(&priv->dev);
/* Handle ARP packet */
@@ -2010,7 +2010,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid)
else
#endif
{
- nlldbg("DROPPED: Unknown type: %04x\n", BUF->type);
+ nwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
NETDEV_RXDROPPED(&priv->dev);
}
}
@@ -2286,7 +2286,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
imr = sam_getreg(priv, SAM_EMAC_IMR_OFFSET);
pending = isr & ~(imr | EMAC_INT_UNUSED);
- nllvdbg("isr: %08x pending: %08x\n", isr, pending);
+ ninfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the receipt of an RX packet.
*
@@ -2312,7 +2312,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
if ((rsr & EMAC_RSR_RXOVR) != 0)
{
- nlldbg("ERROR: Receiver overrun RSR: %08x\n", rsr);
+ nerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_RXOVR;
}
@@ -2329,7 +2329,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
if ((rsr & EMAC_RSR_BNA) != 0)
{
- nlldbg("ERROR: Buffer not available RSR: %08x\n", rsr);
+ nerr("ERROR: Buffer not available RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_BNA;
}
@@ -2370,7 +2370,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
clrbits = EMAC_TSR_RLE | sam_txinuse(priv, qid);
sam_txreset(priv, qid);
- nlldbg("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
+ nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
regval |= EMAC_NCR_TXEN;
@@ -2381,7 +2381,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
if ((tsr & EMAC_TSR_COL) != 0)
{
- nlldbg("ERROR: Collision occurred TSR: %08x\n", tsr);
+ nerr("ERROR: Collision occurred TSR: %08x\n", tsr);
NETDEV_TXERRORS(&priv->dev);
}
@@ -2389,7 +2389,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
if ((tsr & EMAC_TSR_TFC) != 0)
{
- nlldbg("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
+ nerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
NETDEV_TXERRORS(&priv->dev);
}
@@ -2407,7 +2407,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
if ((pending & EMAC_INT_HRESP) != 0)
{
- nlldbg("ERROR: Hresp not OK\n");
+ nerr("ERROR: Hresp not OK\n");
}
/* Check for PAUSE Frame received (PFRE).
@@ -2418,7 +2418,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
if ((pending & EMAC_INT_PFNZ) != 0)
{
- nlldbg("Pause frame received\n");
+ ninfo("Pause frame received\n");
}
/* Check for Pause Time Zero (PTZ)
@@ -2428,7 +2428,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
if ((pending & EMAC_INT_PTZ) != 0)
{
- nlldbg("Pause TO!\n");
+ ninfo("Pause TO!\n");
}
#endif
}
@@ -2593,7 +2593,7 @@ static int sam_emac1_interrupt(int irq, void *context)
static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv)
{
- nlldbg("Timeout!\n");
+ nerr("ERROR: Timeout!\n");
NETDEV_TXTIMEOUTS(&priv->dev);
/* Reset the hardware. Just take the interface down, then back up again. */
@@ -2824,20 +2824,20 @@ static int sam_ifup(struct net_driver_s *dev)
int ret;
#ifdef CONFIG_NET_IPv4
- ndbg("Bringing up: %d.%d.%d.%d\n",
- dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
- (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+ ninfo("Bringing up: %d.%d.%d.%d\n",
+ dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+ (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
#endif
#ifdef CONFIG_NET_IPv6
- ndbg("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n",
- dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2],
- dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5],
- dev->d_ipv6addr[6], dev->d_ipv6addr[7]);
+ ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n",
+ dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2],
+ dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5],
+ dev->d_ipv6addr[6], dev->d_ipv6addr[7]);
#endif
/* Configure the EMAC interface for normal operation. */
- nllvdbg("Initialize the EMAC\n");
+ ninfo("Initialize the EMAC\n");
sam_emac_configure(priv);
sam_queue_configure(priv, EMAC_QUEUE_1);
sam_queue_configure(priv, EMAC_QUEUE_2);
@@ -2858,7 +2858,7 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_phyinit(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phyinit failed: %d\n", ret);
+ nerr("ERROR: sam_phyinit failed: %d\n", ret);
return ret;
}
@@ -2867,16 +2867,16 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_autonegotiate(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_autonegotiate failed: %d\n", ret);
+ nerr("ERROR: sam_autonegotiate failed: %d\n", ret);
return ret;
}
while (sam_linkup(priv) == 0);
- nllvdbg("Link detected \n");
+ ninfo("Link detected \n");
/* Enable normal MAC operation */
- nllvdbg("Enable normal operation\n");
+ ninfo("Enable normal operation\n");
/* Set and activate a timer process */
@@ -2910,7 +2910,7 @@ static int sam_ifdown(struct net_driver_s *dev)
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
irqstate_t flags;
- nlldbg("Taking the network down\n");
+ ninfo("Taking the network down\n");
/* Disable the EMAC interrupt */
@@ -2955,7 +2955,7 @@ static int sam_ifdown(struct net_driver_s *dev)
static inline void sam_txavail_process(FAR struct sam_emac_s *priv)
{
- nllvdbg("ifup: %d\n", priv->ifup);
+ ninfo("ifup: %d\n", priv->ifup);
/* Ignore the notification if the interface is not yet up */
@@ -3208,8 +3208,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int ndx;
unsigned int bit;
- nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@@ -3281,8 +3281,8 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int ndx;
unsigned int bit;
- nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@@ -3464,7 +3464,7 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, long arg)
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_VERBOSE)
+#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_INFO)
static void sam_phydump(struct sam_emac_s *priv)
{
uint32_t regval;
@@ -3476,19 +3476,19 @@ static void sam_phydump(struct sam_emac_s *priv)
regval |= EMAC_NCR_MPE;
sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
- nllvdbg("%s Registers (Address %02x)\n",
- priv->attr->rmii ? "RMII" : "MII", priv->phyaddr);
+ ninfo("%s Registers (Address %02x)\n",
+ priv->attr->rmii ? "RMII" : "MII", priv->phyaddr);
sam_phyread(priv, priv->phyaddr, MII_MCR, &phyval);
- nllvdbg(" MCR: %04x\n", phyval);
+ ninfo(" MCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_MSR, &phyval);
- nllvdbg(" MSR: %04x\n", phyval);
+ ninfo(" MSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_ADVERTISE, &phyval);
- nllvdbg(" ADVERTISE: %04x\n", phyval);
+ ninfo(" ADVERTISE: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_LPA, &phyval);
- nllvdbg(" LPR: %04x\n", phyval);
+ ninfo(" LPR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, priv->attr->physr, &phyval);
- nllvdbg(" PHYSR: %04x\n", phyval);
+ ninfo(" PHYSR: %04x\n", phyval);
/* Disable management port */
@@ -3652,7 +3652,7 @@ static int sam_phyintenable(struct sam_emac_s *priv)
else
#endif
{
- ndbg("ERROR: Unsupported PHY type: %d\n", priv->phytype);
+ nerr("ERROR: Unsupported PHY type: %d\n", priv->phytype);
ret = -ENOSYS;
}
@@ -3716,7 +3716,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int timeout;
int ret;
- nllvdbg(" sam_phyreset\n");
+ ninfo(" sam_phyreset\n");
/* Enable management port */
@@ -3729,7 +3729,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, MII_MCR_RESET);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywrite failed: %d\n", ret);
+ nerr("ERROR: sam_phywrite failed: %d\n", ret);
}
/* Wait for the PHY reset to complete */
@@ -3741,7 +3741,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int result = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (result < 0)
{
- nlldbg("ERROR: Failed to read the MCR register: %d\n", ret);
+ nerr("ERROR: Failed to read the MCR register: %d\n", ret);
ret = result;
}
else if ((mcr & MII_MCR_RESET) == 0)
@@ -3783,7 +3783,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
unsigned int offset;
int ret = -ESRCH;
- nllvdbg("Find a valid PHY address\n");
+ ninfo("Find a valid PHY address\n");
/* Enable management port */
@@ -3806,8 +3806,8 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
else
{
- nlldbg("ERROR: sam_phyread failed for PHY address %02x: %d\n",
- candidate, ret);
+ nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
+ candidate, ret);
for (offset = 0; offset < 32; offset++)
{
@@ -3828,10 +3828,10 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
if (ret == OK)
{
- nllvdbg(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
+ ninfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
*phyaddr = candidate;
sam_phyread(priv, candidate, priv->attr->physr, &phyval);
- nllvdbg(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
+ ninfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
}
/* Disable management port */
@@ -3872,7 +3872,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -3897,7 +3897,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -3937,7 +3937,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -3962,7 +3962,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nlldbg("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -4007,33 +4007,33 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID1, &phyid1);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read PHYID1\n");
+ nerr("ERROR: Failed to read PHYID1\n");
goto errout;
}
- nllvdbg("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
+ ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID2, &phyid2);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read PHYID2\n");
+ nerr("ERROR: Failed to read PHYID2\n");
goto errout;
}
- nllvdbg("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
+ ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
if (phyid1 == priv->attr->msoui &&
((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) ==
(uint16_t)priv->attr->lsoui)
{
- nllvdbg(" Vendor Model Number: %04x\n",
- (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
- nllvdbg(" Model Revision Number: %04x\n",
- (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
+ ninfo(" Vendor Model Number: %04x\n",
+ (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
+ ninfo(" Model Revision Number: %04x\n",
+ (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
}
else
{
- nlldbg("ERROR: PHY not recognized\n");
+ nerr("ERROR: PHY not recognized\n");
}
/* Setup control register */
@@ -4041,7 +4041,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read MCR\n");
+ nerr("ERROR: Failed to read MCR\n");
goto errout;
}
@@ -4052,7 +4052,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to write MCR\n");
+ nerr("ERROR: Failed to write MCR\n");
goto errout;
}
@@ -4067,7 +4067,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_ADVERTISE, advertise);
if (ret < 0)
{
- nlldbg("ERROR: Failed to write ANAR\n");
+ nerr("ERROR: Failed to write ANAR\n");
goto errout;
}
@@ -4076,7 +4076,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read MCR\n");
+ nerr("ERROR: Failed to read MCR\n");
goto errout;
}
@@ -4084,7 +4084,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to write MCR\n");
+ nerr("ERROR: Failed to write MCR\n");
goto errout;
}
@@ -4096,11 +4096,11 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to write MCR\n");
+ nerr("ERROR: Failed to write MCR\n");
goto errout;
}
- nllvdbg(" MCR: %04x\n", mcr);
+ ninfo(" MCR: %04x\n", mcr);
/* Check AutoNegotiate complete */
@@ -4110,7 +4110,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read MSR\n");
+ nerr("ERROR: Failed to read MSR\n");
goto errout;
}
@@ -4120,7 +4120,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
{
/* Yes.. break out of the loop */
- nllvdbg("AutoNegotiate complete\n");
+ ninfo("AutoNegotiate complete\n");
break;
}
@@ -4128,7 +4128,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
if (++timeout >= PHY_RETRY_MAX)
{
- nlldbg("ERROR: TimeOut\n");
+ nerr("ERROR: TimeOut\n");
sam_phydump(priv);
ret = -ETIMEDOUT;
goto errout;
@@ -4140,7 +4140,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_LPA, &lpa);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read ANLPAR\n");
+ nerr("ERROR: Failed to read ANLPAR\n");
goto errout;
}
@@ -4235,13 +4235,13 @@ static bool sam_linkup(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read MSR: %d\n", ret);
+ nerr("ERROR: Failed to read MSR: %d\n", ret);
goto errout;
}
if ((msr & MII_MSR_LINKSTATUS) == 0)
{
- nlldbg("ERROR: MSR LinkStatus: %04x\n", msr);
+ nerr("ERROR: MSR LinkStatus: %04x\n", msr);
goto errout;
}
@@ -4250,7 +4250,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, priv->attr->physr, &physr);
if (ret < 0)
{
- nlldbg("ERROR: Failed to read PHYSR: %d\n", ret);
+ nerr("ERROR: Failed to read PHYSR: %d\n", ret);
goto errout;
}
@@ -4288,7 +4288,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
/* Start the EMAC transfers */
- nllvdbg("Link is up\n");
+ ninfo("Link is up\n");
linkup = true;
errout:
@@ -4329,7 +4329,7 @@ static int sam_phyinit(struct sam_emac_s *priv)
mck = BOARD_MCK_FREQUENCY;
if (mck > (240*1000*1000))
{
- ndbg("ERROR: Cannot realize PHY clock\n");
+ nerr("ERROR: Cannot realize PHY clock\n");
return -EINVAL;
}
else if (mck > (160*1000*1000))
@@ -4365,7 +4365,7 @@ static int sam_phyinit(struct sam_emac_s *priv)
ret = sam_phyfind(priv, &priv->phyaddr);
if (ret < 0)
{
- nlldbg("ERROR: sam_phyfind failed: %d\n", ret);
+ nerr("ERROR: sam_phyfind failed: %d\n", ret);
return ret;
}
@@ -4480,7 +4480,7 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv)
else
#endif
{
- nvdbg("ERROR: emac=%d\n", priv->attr->emac);
+ nerr("ERROR: emac=%d\n", priv->attr->emac);
}
}
@@ -4803,11 +4803,11 @@ static void sam_macaddress(struct sam_emac_s *priv)
struct net_driver_s *dev = &priv->dev;
uint32_t regval;
- nllvdbg("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- dev->d_ifname,
- dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
- dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
- dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
+ ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ dev->d_ifname,
+ dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+ dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+ dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
/* Set the MAC address */
@@ -4869,7 +4869,7 @@ static void sam_ipv6multicast(struct sam_emac_s *priv)
mac[4] = tmp16 & 0xff;
mac[5] = tmp16 >> 8;
- nvdbg("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
(void)sam_addmac(dev, mac);
@@ -5006,7 +5006,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
{
uint32_t regval;
- nllvdbg("Entry\n");
+ ninfo("Entry\n");
/* Enable clocking to the EMAC peripheral */
@@ -5111,7 +5111,7 @@ int sam_emac_initialize(int intf)
else
#endif
{
- ndbg("ERROR: Interface %d not supported\n", intf);
+ nerr("ERROR: Interface %d not supported\n", intf);
return -EINVAL;
}
@@ -5140,7 +5140,7 @@ int sam_emac_initialize(int intf)
priv->txpoll = wd_create();
if (!priv->txpoll)
{
- ndbg("ERROR: Failed to create periodic poll timer\n");
+ nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout;
}
@@ -5148,7 +5148,7 @@ int sam_emac_initialize(int intf)
priv->txtimeout = wd_create(); /* Create TX timeout timer */
if (!priv->txtimeout)
{
- ndbg("ERROR: Failed to create periodic poll timer\n");
+ nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout_with_txpoll;
}
@@ -5162,7 +5162,7 @@ int sam_emac_initialize(int intf)
ret = sam_buffer_allocate(priv);
if (ret < 0)
{
- ndbg("ERROR: sam_buffer_allocate failed: %d\n", ret);
+ nerr("ERROR: sam_buffer_allocate failed: %d\n", ret);
goto errout_with_txtimeout;
}
@@ -5173,7 +5173,7 @@ int sam_emac_initialize(int intf)
ret = irq_attach(priv->attr->irq, priv->attr->handler);
if (ret < 0)
{
- ndbg("ERROR: Failed to attach the handler to the IRQ%d\n", priv->attr->irq);
+ nerr("ERROR: Failed to attach the handler to the IRQ%d\n", priv->attr->irq);
goto errout_with_buffers;
}
@@ -5186,7 +5186,7 @@ int sam_emac_initialize(int intf)
ret = sam_ifdown(&priv->dev);
if (ret < 0)
{
- ndbg("ERROR: Failed to put the interface in the down state: %d\n", ret);
+ nerr("ERROR: Failed to put the interface in the down state: %d\n", ret);
goto errout_with_buffers;
}
@@ -5198,7 +5198,7 @@ int sam_emac_initialize(int intf)
return ret;
}
- ndbg("ERROR: netdev_register() failed: %d\n", ret);
+ nerr("ERROR: netdev_register() failed: %d\n", ret);
errout_with_buffers:
sam_buffer_free(priv);
@@ -5261,7 +5261,7 @@ int sam_emac_setmacaddr(int intf, uint8_t mac[6])
else
#endif
{
- ndbg("ERROR: Interface %d not supported\n", intf);
+ nerr("ERROR: Interface %d not supported\n", intf);
return -EINVAL;
}
@@ -5270,7 +5270,7 @@ int sam_emac_setmacaddr(int intf, uint8_t mac[6])
dev = &priv->dev;
memcpy(dev->d_mac.ether_addr_octet, mac, 6);
- nvdbg("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
diff --git a/arch/arm/src/samv7/sam_ethernet.c b/arch/arm/src/samv7/sam_ethernet.c
index 3e19d958738ce3d441328cd799771cf6636f34c1..0137b16115304119f7b2b924dde03cd887bfb757 100644
--- a/arch/arm/src/samv7/sam_ethernet.c
+++ b/arch/arm/src/samv7/sam_ethernet.c
@@ -99,7 +99,7 @@ void up_netinitialize(void)
ret = sam_emac_initialize(EMAC0_INTF);
if (ret < 0)
{
- nlldbg("ERROR: up_emac_initialize(EMAC0) failed: %d\n", ret);
+ nerr("ERROR: up_emac_initialize(EMAC0) failed: %d\n", ret);
}
#endif
@@ -109,7 +109,7 @@ void up_netinitialize(void)
ret = sam_emac_initialize(EMAC1_INTF);
if (ret < 0)
{
- nlldbg("ERROR: up_emac_initialize(EMAC1) failed: %d\n", ret);
+ nerr("ERROR: up_emac_initialize(EMAC1) failed: %d\n", ret);
}
#endif
#endif
diff --git a/arch/arm/src/samv7/sam_freerun.c b/arch/arm/src/samv7/sam_freerun.c
index c5eec516ddf7be1a4ede26d1a053f900258dc95b..b3fbfbf6dfc6eb114edfab61a9baed79986d6426 100644
--- a/arch/arm/src/samv7/sam_freerun.c
+++ b/arch/arm/src/samv7/sam_freerun.c
@@ -124,7 +124,7 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan,
uint32_t cmr;
int ret;
- tcvdbg("chan=%d resolution=%d usec\n", chan, resolution);
+ tmrinfo("chan=%d resolution=%d usec\n", chan, resolution);
DEBUGASSERT(freerun && resolution > 0);
/* Get the TC frequency the corresponds to the requested resolution */
@@ -136,13 +136,13 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan,
ret = sam_tc_clockselect(frequency, &cmr, &actual);
if (ret < 0)
{
- tcdbg("ERROR: sam_tc_clockselect failed: %d\n", ret);
+ tmrerr("ERROR: sam_tc_clockselect failed: %d\n", ret);
return ret;
}
- tcvdbg("frequency=%lu, actual=%lu, cmr=%08lx\n",
- (unsigned long)frequency, (unsigned long)actual,
- (unsigned long)cmr);
+ tmrinfo("frequency=%lu, actual=%lu, cmr=%08lx\n",
+ (unsigned long)frequency, (unsigned long)actual,
+ (unsigned long)cmr);
/* Allocate the timer/counter and select its mode of operation
*
@@ -175,7 +175,7 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan,
freerun->tch = sam_tc_allocate(chan, cmr);
if (!freerun->tch)
{
- tcdbg("ERROR: Failed to allocate timer channel %d\n", chan);
+ tmrerr("ERROR: Failed to allocate timer channel %d\n", chan);
return -EBUSY;
}
@@ -260,9 +260,9 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts)
leave_critical_section(flags);
- tcvdbg("counter=%lu (%lu) overflow=%lu, sr=%08lx\n",
- (unsigned long)counter, (unsigned long)verify,
- (unsigned long)overflow, (unsigned long)sr);
+ tmrinfo("counter=%lu (%lu) overflow=%lu, sr=%08lx\n",
+ (unsigned long)counter, (unsigned long)verify,
+ (unsigned long)overflow, (unsigned long)sr);
/* Convert the whole thing to units of microseconds.
*
@@ -280,7 +280,7 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts)
ts->tv_sec = sec;
ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC;
- tcvdbg("usec=%llu ts=(%lu, %lu)\n",
+ tmrinfo("usec=%llu ts=(%lu, %lu)\n",
usec, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
return OK;
diff --git a/arch/arm/src/samv7/sam_gpio.c b/arch/arm/src/samv7/sam_gpio.c
index 32547ff1a3b060a876c3cbf0f7ce8c1c1b61e917..cf681e766207c252f92d0e5969b5d275ebf3d3a3 100644
--- a/arch/arm/src/samv7/sam_gpio.c
+++ b/arch/arm/src/samv7/sam_gpio.c
@@ -86,7 +86,7 @@
* Private Data
****************************************************************************/
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
static const char g_portchar[SAMV7_NPIO] =
{
'A'
@@ -543,15 +543,11 @@ bool sam_gpioread(gpio_pinset_t pinset)
uint32_t pin = sam_gpio_pinmask(pinset);
uint32_t regval;
- if ((pinset & GPIO_MODE_MASK) == GPIO_OUTPUT)
- {
- regval = getreg32(base + SAM_PIO_ODSR_OFFSET);
- }
- else
- {
- regval = getreg32(base + SAM_PIO_PDSR_OFFSET);
- }
+ /* Always read the Pin Data Status Register. Otherwise an Open-Drain
+ * Output pin will not be read back correctly.
+ */
+ regval = getreg32(base + SAM_PIO_PDSR_OFFSET);
return (regval & pin) != 0;
}
@@ -563,7 +559,7 @@ bool sam_gpioread(gpio_pinset_t pinset)
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
int sam_dumpgpio(uint32_t pinset, const char *msg)
{
irqstate_t flags;
@@ -578,40 +574,42 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
/* The following requires exclusive access to the GPIO registers */
flags = enter_critical_section();
- lldbg("PIO%c pinset: %08x base: %08x -- %s\n",
- g_portchar[port], pinset, base, msg);
- lldbg(" PSR: %08x OSR: %08x IFSR: %08x ODSR: %08x\n",
- getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET),
- getreg32(base + SAM_PIO_IFSR_OFFSET), getreg32(base + SAM_PIO_ODSR_OFFSET));
- lldbg(" PDSR: %08x IMR: %08x ISR: %08x MDSR: %08x\n",
- getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
- getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET));
- lldbg(" ABCDSR: %08x %08x IFSCSR: %08x PPDSR: %08x\n",
- getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET),
- getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_PPDSR_OFFSET));
- lldbg(" PUSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n",
- getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
- getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET));
- lldbg(" ESR: %08x LSR: %08x ELSR: %08x FELLSR: %08x\n",
- getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET),
- getreg32(base + SAM_PIO_ELSR_OFFSET), getreg32(base + SAM_PIO_FELLSR_OFFSET));
- lldbg(" FRLHSR: %08x LOCKSR: %08x WPMR: %08x WPSR: %08x\n",
- getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET),
- getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
- lldbg(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n",
- getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
- getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
- lldbg("SCHMITT: %08x DRIVER:%08x\n",
- getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DRIVER_OFFSET));
- lldbg(" KER: %08x KRCR: %08x KDR: %08x KIMR: %08x\n",
- getreg32(base + SAM_PIO_KER_OFFSET), getreg32(base + SAM_PIO_KRCR_OFFSET),
- getreg32(base + SAM_PIO_KDR_OFFSET), getreg32(base + SAM_PIO_KIMR_OFFSET));
- lldbg(" KSR: %08x KKPR: %08x KKRR: %08x\n",
- getreg32(base + SAM_PIO_KSR_OFFSET), getreg32(base + SAM_PIO_KKPR_OFFSET),
- getreg32(base + SAM_PIO_KKRR_OFFSET));
- lldbg(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n",
- getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
- getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
+
+ gpioinfo("PIO%c pinset: %08x base: %08x -- %s\n",
+ g_portchar[port], pinset, base, msg);
+ gpioinfo(" PSR: %08x OSR: %08x IFSR: %08x ODSR: %08x\n",
+ getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET),
+ getreg32(base + SAM_PIO_IFSR_OFFSET), getreg32(base + SAM_PIO_ODSR_OFFSET));
+ gpioinfo(" PDSR: %08x IMR: %08x ISR: %08x MDSR: %08x\n",
+ getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
+ getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET));
+ gpioinfo(" ABCDSR: %08x %08x IFSCSR: %08x PPDSR: %08x\n",
+ getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET),
+ getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_PPDSR_OFFSET));
+ gpioinfo(" PUSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n",
+ getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
+ getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET));
+ gpioinfo(" ESR: %08x LSR: %08x ELSR: %08x FELLSR: %08x\n",
+ getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET),
+ getreg32(base + SAM_PIO_ELSR_OFFSET), getreg32(base + SAM_PIO_FELLSR_OFFSET));
+ gpioinfo(" FRLHSR: %08x LOCKSR: %08x WPMR: %08x WPSR: %08x\n",
+ getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET),
+ getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
+ gpioinfo(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n",
+ getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
+ getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
+ gpioinfo("SCHMITT: %08x DRIVER:%08x\n",
+ getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DRIVER_OFFSET));
+ gpioinfo(" KER: %08x KRCR: %08x KDR: %08x KIMR: %08x\n",
+ getreg32(base + SAM_PIO_KER_OFFSET), getreg32(base + SAM_PIO_KRCR_OFFSET),
+ getreg32(base + SAM_PIO_KDR_OFFSET), getreg32(base + SAM_PIO_KIMR_OFFSET));
+ gpioinfo(" KSR: %08x KKPR: %08x KKRR: %08x\n",
+ getreg32(base + SAM_PIO_KSR_OFFSET), getreg32(base + SAM_PIO_KKPR_OFFSET),
+ getreg32(base + SAM_PIO_KKRR_OFFSET));
+ gpioinfo(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n",
+ getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
+ getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
+
leave_critical_section(flags);
return OK;
}
diff --git a/arch/arm/src/samv7/sam_gpio.h b/arch/arm/src/samv7/sam_gpio.h
index 2e564ec787ddfe80124e6f5484df0f82936e9308..e6746da3978174158ea053b53f0bdf0faf7b4ed3 100644
--- a/arch/arm/src/samv7/sam_gpio.h
+++ b/arch/arm/src/samv7/sam_gpio.h
@@ -377,7 +377,7 @@ void sam_gpioirqdisable(int irq);
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
int sam_dumpgpio(uint32_t pinset, const char *msg);
#else
# define sam_dumpgpio(p,m)
diff --git a/arch/arm/src/samv7/sam_hsmci.c b/arch/arm/src/samv7/sam_hsmci.c
index 89d16b37928882b6ca1639d970f18ba3dbc79a7f..cffada9e47014828b795cd6756f87689a771b166 100644
--- a/arch/arm/src/samv7/sam_hsmci.c
+++ b/arch/arm/src/samv7/sam_hsmci.c
@@ -81,6 +81,10 @@
# error "HSMCI support requires CONFIG_SAMV7_XDMAC"
#endif
+#ifndef CONFIG_DEBUG_MEMCARD_INFO
+# undef CONFIG_SAMV7_HSMCI_REGDEBUG
+#endif
+
/* System Bus Interfaces */
#if defined(CONFIG_ARCH_CHIP_SAMV71) || defined(CONFIG_ARCH_CHIP_SAME70)
@@ -98,7 +102,7 @@
# error "This driver requires CONFIG_SDIO_BLOCKSETUP"
#endif
-#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_VERBOSE)
+#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_INFO)
# undef CONFIG_SAMV7_HSMCI_CMDDEBUG
# undef CONFIG_SAMV7_HSMCI_XFRDEBUG
#endif
@@ -653,7 +657,7 @@ static bool sam_checkreg(struct sam_dev_s *priv, bool wr, uint32_t value,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", priv->ntimes);
+ mcinfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@@ -686,7 +690,7 @@ static inline uint32_t sam_getreg(struct sam_dev_s *priv, unsigned int offset)
#ifdef CONFIG_SAMV7_HSMCI_REGDEBUG
if (sam_checkreg(priv, false, value, address))
{
- lldbg("%08x->%08x\n", address, value);
+ mcinfo("%08x->%08x\n", address, value);
}
#endif
@@ -709,7 +713,7 @@ static inline void sam_putreg(struct sam_dev_s *priv, uint32_t value,
#ifdef CONFIG_SAMV7_HSMCI_REGDEBUG
if (sam_checkreg(priv, true, value, address))
{
- lldbg("%08x<-%08x\n", address, value);
+ mcinfo("%08x<-%08x\n", address, value);
}
#endif
@@ -933,25 +937,25 @@ static void sam_hsmcisample(struct sam_dev_s *priv,
static void sam_hsmcidump(struct sam_dev_s *priv,
struct sam_hsmciregs_s *regs, const char *msg)
{
- fdbg("HSMCI Registers: %s\n", msg);
- fdbg(" MR[%08x]: %08x\n", priv->base + SAM_HSMCI_MR_OFFSET, regs->mr);
- fdbg(" DTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_DTOR_OFFSET, regs->dtor);
- fdbg(" SDCR[%08x]: %08x\n", priv->base + SAM_HSMCI_SDCR_OFFSET, regs->sdcr);
- fdbg(" ARGR[%08x]: %08x\n", priv->base + SAM_HSMCI_ARGR_OFFSET, regs->argr);
- fdbg(" BLKR[%08x]: %08x\n", priv->base + SAM_HSMCI_BLKR_OFFSET, regs->blkr);
- fdbg(" CSTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_CSTOR_OFFSET, regs->cstor);
+ mcinfo("HSMCI Registers: %s\n", msg);
+ mcinfo(" MR[%08x]: %08x\n", priv->base + SAM_HSMCI_MR_OFFSET, regs->mr);
+ mcinfo(" DTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_DTOR_OFFSET, regs->dtor);
+ mcinfo(" SDCR[%08x]: %08x\n", priv->base + SAM_HSMCI_SDCR_OFFSET, regs->sdcr);
+ mcinfo(" ARGR[%08x]: %08x\n", priv->base + SAM_HSMCI_ARGR_OFFSET, regs->argr);
+ mcinfo(" BLKR[%08x]: %08x\n", priv->base + SAM_HSMCI_BLKR_OFFSET, regs->blkr);
+ mcinfo(" CSTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_CSTOR_OFFSET, regs->cstor);
#if 0 /* Reading these can cause loss of response data */
- fdbg(" RSPR0[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR0_OFFSET, regs->rsp0);
- fdbg(" RSPR1[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR1_OFFSET, regs->rsp1);
- fdbg(" RSPR2[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR2_OFFSET, regs->rsp2);
- fdbg(" RSPR3[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR3_OFFSET, regs->rsp3);
-#endif
- fdbg(" SR[%08x]: %08x\n", priv->base + SAM_HSMCI_SR_OFFSET, regs->sr);
- fdbg(" IMR[%08x]: %08x\n", priv->base + SAM_HSMCI_IMR_OFFSET, regs->imr);
- fdbg(" DMA[%08x]: %08x\n", priv->base + SAM_HSMCI_DMA_OFFSET, regs->dma);
- fdbg(" CFG[%08x]: %08x\n", priv->base + SAM_HSMCI_CFG_OFFSET, regs->cfg);
- fdbg(" WPMR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPMR_OFFSET, regs->wpmr);
- fdbg(" WPSR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPSR_OFFSET, regs->wpsr);
+ mcinfo(" RSPR0[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR0_OFFSET, regs->rsp0);
+ mcinfo(" RSPR1[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR1_OFFSET, regs->rsp1);
+ mcinfo(" RSPR2[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR2_OFFSET, regs->rsp2);
+ mcinfo(" RSPR3[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR3_OFFSET, regs->rsp3);
+#endif
+ mcinfo(" SR[%08x]: %08x\n", priv->base + SAM_HSMCI_SR_OFFSET, regs->sr);
+ mcinfo(" IMR[%08x]: %08x\n", priv->base + SAM_HSMCI_IMR_OFFSET, regs->imr);
+ mcinfo(" DMA[%08x]: %08x\n", priv->base + SAM_HSMCI_DMA_OFFSET, regs->dma);
+ mcinfo(" CFG[%08x]: %08x\n", priv->base + SAM_HSMCI_CFG_OFFSET, regs->cfg);
+ mcinfo(" WPMR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPMR_OFFSET, regs->wpmr);
+ mcinfo(" WPSR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPSR_OFFSET, regs->wpsr);
}
#endif
@@ -1025,7 +1029,7 @@ static void sam_xfrdumpone(struct sam_dev_s *priv, int index,
}
else
{
- fdbg("%s: Not collected\n", msg);
+ mcerr("ERROR: %s: Not collected\n", msg);
}
}
#endif
@@ -1169,7 +1173,7 @@ static void sam_dmacallback(DMA_HANDLE handle, void *arg, int result)
if (result < 0)
{
wkupevent = (result == -ETIMEDOUT ? SDIOWAIT_TIMEOUT : SDIOWAIT_ERROR);
- flldbg("ERROR: DMA failed: result=%d wkupevent=%04x\n", result, wkupevent);
+ mcerr("ERROR: DMA failed: result=%d wkupevent=%04x\n", result, wkupevent);
/* sam_endtransfer will terminate the transfer and wait up the waiting
* client in this case.
@@ -1269,7 +1273,7 @@ static void sam_eventtimeout(int argc, uint32_t arg)
/* Yes.. wake up any waiting threads */
sam_endwait(priv, SDIOWAIT_TIMEOUT);
- flldbg("ERROR: Timeout\n");
+ mcerr("ERROR: Timeout\n");
}
}
@@ -1469,7 +1473,7 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv)
{
/* Yes.. Was it some kind of timeout error? */
- flldbg("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
+ mcerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
if ((pending & HSMCI_DATA_TIMEOUT_ERRORS) != 0)
{
/* Yes.. Terminate with a timeout. */
@@ -1590,8 +1594,8 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv)
{
/* Yes.. Was the error some kind of timeout? */
- fllvdbg("ERROR: events: %08x SR: %08x\n",
- priv->cmdrmask, enabled);
+ mcerr("ERROR: events: %08x SR: %08x\n",
+ priv->cmdrmask, enabled);
if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
{
@@ -2056,7 +2060,7 @@ static int sam_sendcmd(FAR struct sdio_dev_s *dev,
/* Write the fully decorated command to CMDR */
- fvdbg("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
+ mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
sam_putreg(priv, regval, SAM_HSMCI_CMDR_OFFSET);
sam_cmdsample1(priv, SAMPLENDX_AFTER_CMDR);
return OK;
@@ -2239,7 +2243,7 @@ static int sam_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer,
{
/* Some fatal error has occurred */
- fdbg("ERROR: sr %08x\n", sr);
+ mcerr("ERROR: sr %08x\n", sr);
return -EIO;
}
else if ((sr & HSMCI_INT_TXRDY) != 0)
@@ -2419,7 +2423,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
{
/* Yes.. Was the error some kind of timeout? */
- fdbg("ERROR: cmd: %08x events: %08x SR: %08x\n",
+ mcerr("ERROR: cmd: %08x events: %08x SR: %08x\n",
cmd, priv->cmdrmask, sr);
if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
@@ -2449,7 +2453,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
}
else if (--timeout <= 0)
{
- fdbg("ERROR: Timeout cmd: %08x events: %08x SR: %08x\n",
+ mcerr("ERROR: Timeout cmd: %08x events: %08x SR: %08x\n",
cmd, priv->cmdrmask, sr);
priv->wkupevent = SDIOWAIT_TIMEOUT;
@@ -2521,10 +2525,10 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev,
* 0 1 End bit
*/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!rshort)
{
- fdbg("ERROR: rshort=NULL\n");
+ mcerr("ERROR: rshort=NULL\n");
ret = -EINVAL;
}
@@ -2536,7 +2540,7 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev,
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE &&
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE)
{
- fdbg("ERROR: Wrong response CMD=%08x\n", cmd);
+ mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
ret = -EINVAL;
}
else
@@ -2582,12 +2586,12 @@ static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd,
* 0 1 End bit
*/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
/* Check that R1 is the correct response to this command */
if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE)
{
- fdbg("ERROR: Wrong response CMD=%08x\n", cmd);
+ mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
ret = -EINVAL;
}
else
@@ -2597,7 +2601,7 @@ static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd,
if ((priv->wkupevent & SDIOWAIT_TIMEOUT) != 0)
{
- fdbg("ERROR: timeout\n");
+ mcerr("ERROR: timeout\n");
ret = -EINVAL;
}
@@ -2605,7 +2609,7 @@ static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd,
else if ((priv->wkupevent & SDIOWAIT_ERROR) != 0)
{
- fdbg("ERROR: Other error\n");
+ mcerr("ERROR: Other error\n");
ret = -EIO;
}
@@ -2781,7 +2785,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev,
1, (uint32_t)priv);
if (ret != OK)
{
- fdbg("ERROR: wd_start failed: %d\n", ret);
+ mcerr("ERROR: wd_start failed: %d\n", ret);
}
}
@@ -2847,7 +2851,7 @@ static void sam_callbackenable(FAR struct sdio_dev_s *dev,
{
struct sam_dev_s *priv = (struct sam_dev_s *)dev;
- fvdbg("eventset: %02x\n", eventset);
+ mcinfo("eventset: %02x\n", eventset);
DEBUGASSERT(priv != NULL);
priv->cbevents = eventset;
@@ -2883,7 +2887,7 @@ static int sam_registercallback(FAR struct sdio_dev_s *dev,
/* Disable callbacks and register this callback and is argument */
- fvdbg("Register %p(%p)\n", callback, arg);
+ mcinfo("Register %p(%p)\n", callback, arg);
DEBUGASSERT(priv != NULL);
priv->cbevents = 0;
@@ -3158,7 +3162,7 @@ static void sam_callback(void *arg)
/* Is a callback registered? */
DEBUGASSERT(priv != NULL);
- fvdbg("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
+ mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
flags = enter_critical_section();
@@ -3213,17 +3217,17 @@ static void sam_callback(void *arg)
{
/* NOTE: Currently, work_cancel only returns success */
- fdbg("ERROR: Failed to cancel work: %d\n", ret);
+ mcerr("ERROR: Failed to cancel work: %d\n", ret);
}
- fllvdbg("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
+ mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
ret = work_queue(LPWORK, &priv->cbwork, (worker_t)priv->callback,
priv->cbarg, 0);
if (ret < 0)
{
/* NOTE: Currently, work_queue only returns success */
- fdbg("ERROR: Failed to schedule work: %d\n", ret);
+ mcerr("ERROR: Failed to schedule work: %d\n", ret);
}
}
@@ -3261,7 +3265,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
* for now, an* HSMCI peripheral does correspond to a slot.
*/
- fvdbg("slotno: %d\n", slotno);
+ mcinfo("slotno: %d\n", slotno);
#ifdef CONFIG_SAMV7_HSMCI0
if (slotno == 0)
@@ -3344,7 +3348,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
return NULL;
}
- fvdbg("priv: %p base: %08x hsmci: %d pid: %d\n",
+ mcinfo("priv: %p base: %08x hsmci: %d pid: %d\n",
priv, priv->base, priv->hsmci, pid);
/* Initialize the HSMCI slot structure */
@@ -3414,7 +3418,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
priv->cdstatus &= ~SDIO_STATUS_PRESENT;
}
- fllvdbg("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
+ mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
/* Perform any requested callback if the status has changed */
@@ -3459,7 +3463,7 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED;
}
- fvdbg("cdstatus: %02x\n", priv->cdstatus);
+ mcinfo("cdstatus: %02x\n", priv->cdstatus);
leave_critical_section(flags);
}
diff --git a/arch/arm/src/samv7/sam_irq.c b/arch/arm/src/samv7/sam_irq.c
index 963b87db1daec5e15a714b763fb355068426c2e1..08537f65970950d13d58aa5c1a0c299a6c22323a 100644
--- a/arch/arm/src/samv7/sam_irq.c
+++ b/arch/arm/src/samv7/sam_irq.c
@@ -108,52 +108,54 @@ extern uint32_t _vectors[];
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_IRQ)
+#if defined(CONFIG_DEBUG_IRQ_INFO)
static void sam_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
- lldbg("NVIC (%s, irq=%d):\n", msg, irq);
- lldbg(" INTCTRL: %08x VECTAB: %08x\n",
+
+ irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
+ irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
- lldbg(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
- getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
- getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
+ irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
+ getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
+ getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
- lldbg(" IRQ ENABLE: %08x %08x %08x\n",
- getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
- getreg32(NVIC_IRQ64_95_ENABLE));
- lldbg(" SYSH_PRIO: %08x %08x %08x\n",
- getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
- getreg32(NVIC_SYSH12_15_PRIORITY));
- lldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
- getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
+ irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
+ getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
+ getreg32(NVIC_IRQ64_95_ENABLE));
+ irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
+ getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
+ getreg32(NVIC_SYSH12_15_PRIORITY));
+ irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
+ getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
#if SAM_IRQ_NEXTINT > 15
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
- getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
+ getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
#endif
#if SAM_IRQ_NEXTINT > 31
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
- getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
+ getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
#endif
#if SAM_IRQ_NEXTINT > 47
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
- getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
+ getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
#endif
#if SAM_IRQ_NEXTINT > 63
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
- getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
+ getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
#endif
#if SAM_IRQ_NEXTINT > 79
# warning Missing logic
#endif
+
leave_critical_section(flags);
}
#else
@@ -171,11 +173,11 @@ static void sam_dumpnvic(const char *msg, int irq)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
static int sam_nmi(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! NMI received\n");
+ _err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
@@ -183,7 +185,7 @@ static int sam_nmi(int irq, FAR void *context)
static int sam_busfault(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
+ _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
}
@@ -191,7 +193,7 @@ static int sam_busfault(int irq, FAR void *context)
static int sam_usagefault(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
+ _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
}
@@ -199,7 +201,7 @@ static int sam_usagefault(int irq, FAR void *context)
static int sam_pendsv(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! PendSV received\n");
+ _err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
@@ -207,7 +209,7 @@ static int sam_pendsv(int irq, FAR void *context)
static int sam_dbgmonitor(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Debug Monitor received\n");
+ _err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
}
@@ -215,7 +217,7 @@ static int sam_dbgmonitor(int irq, FAR void *context)
static int sam_reserved(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Reserved interrupt\n");
+ _err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
@@ -456,7 +458,7 @@ void up_irqinitialize(void)
/* Attach all other processor exceptions (except reset and sys tick) */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
irq_attach(SAM_IRQ_NMI, sam_nmi);
#ifndef CONFIG_ARM_MPU
irq_attach(SAM_IRQ_MEMFAULT, up_memfault);
diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c
index f1f8f788a2f3107cb946d7f666d8a8b1b1d2414c..2091390cab257f0bdd125995525bd9da35316e72 100644
--- a/arch/arm/src/samv7/sam_mcan.c
+++ b/arch/arm/src/samv7/sam_mcan.c
@@ -789,28 +789,14 @@
/* Debug ********************************************************************/
/* Debug configurations that may be enabled just for testing MCAN */
-#if !defined(CONFIG_DEBUG) || !defined(CONFIG_DEBUG_CAN)
+#ifndef CONFIG_DEBUG_CAN_INFO
# undef CONFIG_SAMV7_MCAN_REGDEBUG
#endif
-#ifdef CONFIG_DEBUG_CAN
-# define candbg dbg
-# define canvdbg vdbg
-# define canlldbg lldbg
-# define canllvdbg llvdbg
-
-# ifdef CONFIG_SAMV7_MCAN_REGDEBUG
-# define canregdbg lldbg
-# else
-# define canregdbg(x...)
-# endif
-
+#ifdef CONFIG_SAMV7_MCAN_REGDEBUG
+# define reginfo caninfo
#else
-# define candbg(x...)
-# define canvdbg(x...)
-# define canlldbg(x...)
-# define canllvdbg(x...)
-# define canregdbg(x...)
+# define reginfo(x...)
#endif
/****************************************************************************
@@ -1209,7 +1195,7 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset)
{
if (priv->count == 4)
{
- lldbg("...\n");
+ caninfo("...\n");
}
return regval;
@@ -1226,7 +1212,7 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", priv->count - 3);
+ caninfo("[repeats %d more times]\n", priv->count - 3);
}
/* Save the new address, value, and count */
@@ -1238,7 +1224,7 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset)
/* Show the register value read */
- lldbg("%08x->%08x\n", regaddr, regval);
+ caninfo("%08x->%08x\n", regaddr, regval);
return regval;
}
@@ -1275,7 +1261,7 @@ static void mcan_putreg(FAR struct sam_mcan_s *priv, int offset, uint32_t regval
/* Show the register value being written */
- lldbg("%08x<-%08x\n", regaddr, regval);
+ caninfo("%08x<-%08x\n", regaddr, regval);
/* Write the value */
@@ -1310,74 +1296,74 @@ static void mcan_dumpregs(FAR struct sam_mcan_s *priv, FAR const char *msg)
{
FAR const struct sam_config_s *config = priv->config;
- lldbg("MCAN%d Registers: %s\n", config->port, msg);
- lldbg(" Base: %08x\n", config->base);
-
- lldbg(" CUST: %08x FBTP: %08x TEST: %08x RWD: %08x\n",
- getreg32(config->base + SAM_MCAN_CUST_OFFSET),
- getreg32(config->base + SAM_MCAN_FBTP_OFFSET),
- getreg32(config->base + SAM_MCAN_TEST_OFFSET),
- getreg32(config->base + SAM_MCAN_RWD_OFFSET));
-
- lldbg(" CCCR: %08x BTP: %08x TSCC: %08x TSCV: %08x\n",
- getreg32(config->base + SAM_MCAN_CCCR_OFFSET),
- getreg32(config->base + SAM_MCAN_BTP_OFFSET),
- getreg32(config->base + SAM_MCAN_TSCC_OFFSET),
- getreg32(config->base + SAM_MCAN_TSCV_OFFSET));
-
- lldbg(" TOCC: %08x TOCV: %08x ECR: %08x PSR: %08x\n",
- getreg32(config->base + SAM_MCAN_TOCC_OFFSET),
- getreg32(config->base + SAM_MCAN_TOCV_OFFSET),
- getreg32(config->base + SAM_MCAN_ECR_OFFSET),
- getreg32(config->base + SAM_MCAN_PSR_OFFSET));
-
- lldbg(" IR: %08x IE: %08x ILS: %08x ILE: %08x\n",
- getreg32(config->base + SAM_MCAN_IR_OFFSET),
- getreg32(config->base + SAM_MCAN_IE_OFFSET),
- getreg32(config->base + SAM_MCAN_ILS_OFFSET),
- getreg32(config->base + SAM_MCAN_ILE_OFFSET));
-
- lldbg(" GFC: %08x SIDFC: %08x XIDFC: %08x XIDAM: %08x\n",
- getreg32(config->base + SAM_MCAN_GFC_OFFSET),
- getreg32(config->base + SAM_MCAN_SIDFC_OFFSET),
- getreg32(config->base + SAM_MCAN_XIDFC_OFFSET),
- getreg32(config->base + SAM_MCAN_XIDAM_OFFSET));
-
- lldbg(" HPMS: %08x NDAT1: %08x NDAT2: %08x RXF0C: %08x\n",
- getreg32(config->base + SAM_MCAN_HPMS_OFFSET),
- getreg32(config->base + SAM_MCAN_NDAT1_OFFSET),
- getreg32(config->base + SAM_MCAN_NDAT2_OFFSET),
- getreg32(config->base + SAM_MCAN_RXF0C_OFFSET));
-
- lldbg(" RXF0S: %08x FXF0A: %08x RXBC: %08x RXF1C: %08x\n",
- getreg32(config->base + SAM_MCAN_RXF0S_OFFSET),
- getreg32(config->base + SAM_MCAN_RXF0A_OFFSET),
- getreg32(config->base + SAM_MCAN_RXBC_OFFSET),
- getreg32(config->base + SAM_MCAN_RXF1C_OFFSET));
-
- lldbg(" RXF1S: %08x FXF1A: %08x RXESC: %08x TXBC: %08x\n",
- getreg32(config->base + SAM_MCAN_RXF1S_OFFSET),
- getreg32(config->base + SAM_MCAN_RXF1A_OFFSET),
- getreg32(config->base + SAM_MCAN_RXESC_OFFSET),
- getreg32(config->base + SAM_MCAN_TXBC_OFFSET));
-
- lldbg(" TXFQS: %08x TXESC: %08x TXBRP: %08x TXBAR: %08x\n",
- getreg32(config->base + SAM_MCAN_TXFQS_OFFSET),
- getreg32(config->base + SAM_MCAN_TXESC_OFFSET),
- getreg32(config->base + SAM_MCAN_TXBRP_OFFSET),
- getreg32(config->base + SAM_MCAN_TXBAR_OFFSET));
-
- lldbg(" TXBCR: %08x TXBTO: %08x TXBCF: %08x TXBTIE: %08x\n",
- getreg32(config->base + SAM_MCAN_TXBCR_OFFSET),
- getreg32(config->base + SAM_MCAN_TXBTO_OFFSET),
- getreg32(config->base + SAM_MCAN_TXBCF_OFFSET),
- getreg32(config->base + SAM_MCAN_TXBTIE_OFFSET));
-
- lldbg("TXBCIE: %08x TXEFC: %08x TXEFS: %08x TXEFA: %08x\n",
- getreg32(config->base + SAM_MCAN_TXBCIE_OFFSET),
- getreg32(config->base + SAM_MCAN_TXEFC_OFFSET),
- getreg32(config->base + SAM_MCAN_TXEFS_OFFSET),
- getreg32(config->base + SAM_MCAN_TXEFA_OFFSET));
+ caninfo("MCAN%d Registers: %s\n", config->port, msg);
+ caninfo(" Base: %08x\n", config->base);
+
+ caninfo(" CUST: %08x FBTP: %08x TEST: %08x RWD: %08x\n",
+ getreg32(config->base + SAM_MCAN_CUST_OFFSET),
+ getreg32(config->base + SAM_MCAN_FBTP_OFFSET),
+ getreg32(config->base + SAM_MCAN_TEST_OFFSET),
+ getreg32(config->base + SAM_MCAN_RWD_OFFSET));
+
+ caninfo(" CCCR: %08x BTP: %08x TSCC: %08x TSCV: %08x\n",
+ getreg32(config->base + SAM_MCAN_CCCR_OFFSET),
+ getreg32(config->base + SAM_MCAN_BTP_OFFSET),
+ getreg32(config->base + SAM_MCAN_TSCC_OFFSET),
+ getreg32(config->base + SAM_MCAN_TSCV_OFFSET));
+
+ caninfo(" TOCC: %08x TOCV: %08x ECR: %08x PSR: %08x\n",
+ getreg32(config->base + SAM_MCAN_TOCC_OFFSET),
+ getreg32(config->base + SAM_MCAN_TOCV_OFFSET),
+ getreg32(config->base + SAM_MCAN_ECR_OFFSET),
+ getreg32(config->base + SAM_MCAN_PSR_OFFSET));
+
+ caninfo(" IR: %08x IE: %08x ILS: %08x ILE: %08x\n",
+ getreg32(config->base + SAM_MCAN_IR_OFFSET),
+ getreg32(config->base + SAM_MCAN_IE_OFFSET),
+ getreg32(config->base + SAM_MCAN_ILS_OFFSET),
+ getreg32(config->base + SAM_MCAN_ILE_OFFSET));
+
+ caninfo(" GFC: %08x SIDFC: %08x XIDFC: %08x XIDAM: %08x\n",
+ getreg32(config->base + SAM_MCAN_GFC_OFFSET),
+ getreg32(config->base + SAM_MCAN_SIDFC_OFFSET),
+ getreg32(config->base + SAM_MCAN_XIDFC_OFFSET),
+ getreg32(config->base + SAM_MCAN_XIDAM_OFFSET));
+
+ caninfo(" HPMS: %08x NDAT1: %08x NDAT2: %08x RXF0C: %08x\n",
+ getreg32(config->base + SAM_MCAN_HPMS_OFFSET),
+ getreg32(config->base + SAM_MCAN_NDAT1_OFFSET),
+ getreg32(config->base + SAM_MCAN_NDAT2_OFFSET),
+ getreg32(config->base + SAM_MCAN_RXF0C_OFFSET));
+
+ caninfo(" RXF0S: %08x FXF0A: %08x RXBC: %08x RXF1C: %08x\n",
+ getreg32(config->base + SAM_MCAN_RXF0S_OFFSET),
+ getreg32(config->base + SAM_MCAN_RXF0A_OFFSET),
+ getreg32(config->base + SAM_MCAN_RXBC_OFFSET),
+ getreg32(config->base + SAM_MCAN_RXF1C_OFFSET));
+
+ caninfo(" RXF1S: %08x FXF1A: %08x RXESC: %08x TXBC: %08x\n",
+ getreg32(config->base + SAM_MCAN_RXF1S_OFFSET),
+ getreg32(config->base + SAM_MCAN_RXF1A_OFFSET),
+ getreg32(config->base + SAM_MCAN_RXESC_OFFSET),
+ getreg32(config->base + SAM_MCAN_TXBC_OFFSET));
+
+ caninfo(" TXFQS: %08x TXESC: %08x TXBRP: %08x TXBAR: %08x\n",
+ getreg32(config->base + SAM_MCAN_TXFQS_OFFSET),
+ getreg32(config->base + SAM_MCAN_TXESC_OFFSET),
+ getreg32(config->base + SAM_MCAN_TXBRP_OFFSET),
+ getreg32(config->base + SAM_MCAN_TXBAR_OFFSET));
+
+ caninfo(" TXBCR: %08x TXBTO: %08x TXBCF: %08x TXBTIE: %08x\n",
+ getreg32(config->base + SAM_MCAN_TXBCR_OFFSET),
+ getreg32(config->base + SAM_MCAN_TXBTO_OFFSET),
+ getreg32(config->base + SAM_MCAN_TXBCF_OFFSET),
+ getreg32(config->base + SAM_MCAN_TXBTIE_OFFSET));
+
+ caninfo("TXBCIE: %08x TXEFC: %08x TXEFS: %08x TXEFA: %08x\n",
+ getreg32(config->base + SAM_MCAN_TXBCIE_OFFSET),
+ getreg32(config->base + SAM_MCAN_TXEFC_OFFSET),
+ getreg32(config->base + SAM_MCAN_TXEFS_OFFSET),
+ getreg32(config->base + SAM_MCAN_TXEFA_OFFSET));
}
#endif
@@ -1502,7 +1488,7 @@ static void mcan_buffer_reserve(FAR struct sam_mcan_s *priv)
if (sval > 0)
{
- candbg("ERROR: TX FIFOQ full but txfsem is %d\n", sval);
+ canerr("ERROR: TX FIFOQ full but txfsem is %d\n", sval);
sem_reset(&priv->txfsem, 0);
}
}
@@ -1520,7 +1506,7 @@ static void mcan_buffer_reserve(FAR struct sam_mcan_s *priv)
else if (sval <= 0)
{
- candbg("ERROR: TX FIFOQ not full but txfsem is %d\n", sval);
+ canerr("ERROR: TX FIFOQ not full but txfsem is %d\n", sval);
/* Less than zero means that another thread is waiting */
@@ -1551,7 +1537,7 @@ static void mcan_buffer_reserve(FAR struct sam_mcan_s *priv)
if (tffl > priv->config->ntxfifoq)
{
- candbg("ERROR: TX FIFO reports %d but max is %d\n",
+ canerr("ERROR: TX FIFO reports %d but max is %d\n",
tffl, priv->config->ntxfifoq);
tffl = priv->config->ntxfifoq;
}
@@ -1564,7 +1550,7 @@ static void mcan_buffer_reserve(FAR struct sam_mcan_s *priv)
if (sval != tffl)
{
- candbg("ERROR: TX FIFO reports %d but txfsem is %d\n", tffl, sval);
+ canerr("ERROR: TX FIFO reports %d but txfsem is %d\n", tffl, sval);
/* Reset the semaphore count to the Tx FIFO free level. */
@@ -1620,7 +1606,7 @@ static void mcan_buffer_release(FAR struct sam_mcan_s *priv)
}
else
{
- candbg("ERROR: txfsem would increment beyond %d\n",
+ canerr("ERROR: txfsem would increment beyond %d\n",
priv->config->ntxfifoq);
}
}
@@ -2151,7 +2137,7 @@ static void mcan_reset(FAR struct can_dev_s *dev)
config = priv->config;
DEBUGASSERT(config);
- canllvdbg("MCAN%d\n", config->port);
+ caninfo("MCAN%d\n", config->port);
UNUSED(config);
/* Get exclusive access to the MCAN peripheral */
@@ -2208,7 +2194,7 @@ static int mcan_setup(FAR struct can_dev_s *dev)
config = priv->config;
DEBUGASSERT(config);
- canllvdbg("MCAN%d pid: %d\n", config->port, config->pid);
+ caninfo("MCAN%d pid: %d\n", config->port, config->pid);
/* Get exclusive access to the MCAN peripheral */
@@ -2219,7 +2205,7 @@ static int mcan_setup(FAR struct can_dev_s *dev)
ret = mcan_hw_initialize(priv);
if (ret < 0)
{
- canlldbg("MCAN%d H/W initialization failed: %d\n", config->port, ret);
+ canerr("ERROR: MCAN%d H/W initialization failed: %d\n", config->port, ret);
return ret;
}
@@ -2230,7 +2216,7 @@ static int mcan_setup(FAR struct can_dev_s *dev)
ret = irq_attach(config->irq0, config->handler);
if (ret < 0)
{
- canlldbg("Failed to attach MCAN%d line 0 IRQ (%d)",
+ canerr("ERROR: Failed to attach MCAN%d line 0 IRQ (%d)",
config->port, config->irq0);
return ret;
}
@@ -2238,7 +2224,7 @@ static int mcan_setup(FAR struct can_dev_s *dev)
ret = irq_attach(config->irq1, config->handler);
if (ret < 0)
{
- canlldbg("Failed to attach MCAN%d line 1 IRQ (%d)",
+ canerr("ERROR: Failed to attach MCAN%d line 1 IRQ (%d)",
config->port, config->irq1);
return ret;
}
@@ -2285,7 +2271,7 @@ static void mcan_shutdown(FAR struct can_dev_s *dev)
config = priv->config;
DEBUGASSERT(config);
- canllvdbg("MCAN%d\n", config->port);
+ caninfo("MCAN%d\n", config->port);
/* Get exclusive access to the MCAN peripheral */
@@ -2334,7 +2320,7 @@ static void mcan_rxint(FAR struct can_dev_s *dev, bool enable)
DEBUGASSERT(priv && priv->config);
- canllvdbg("MCAN%d enable: %d\n", priv->config->port, enable);
+ caninfo("MCAN%d enable: %d\n", priv->config->port, enable);
/* Enable/disable the receive interrupts */
@@ -2376,7 +2362,7 @@ static void mcan_txint(FAR struct can_dev_s *dev, bool enable)
DEBUGASSERT(priv && priv->config);
- canllvdbg("MCAN%d enable: %d\n", priv->config->port, enable);
+ caninfo("MCAN%d enable: %d\n", priv->config->port, enable);
/* Enable/disable the receive interrupts */
@@ -2415,7 +2401,7 @@ static int mcan_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg)
FAR struct sam_mcan_s *priv;
int ret = -ENOTTY;
- canvdbg("cmd=%04x arg=%lu\n", cmd, arg);
+ caninfo("cmd=%04x arg=%lu\n", cmd, arg);
DEBUGASSERT(dev && dev->cd_priv);
priv = dev->cd_priv;
@@ -2612,12 +2598,10 @@ static int mcan_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg)
/* Unsupported/unrecognized command */
default:
- candbg("ERROR: Unrecognized command: %04x\n", cmd);
+ canerr("ERROR: Unrecognized command: %04x\n", cmd);
break;
}
- /* No CAN ioctls are supported */
-
return ret;
}
@@ -2683,9 +2667,9 @@ static int mcan_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
DEBUGASSERT(priv && priv->config);
config = priv->config;
- canllvdbg("MCAN%d\n", config->port);
- canllvdbg("MCAN%d ID: %d DLC: %d\n",
- config->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
+ caninfo("MCAN%d\n", config->port);
+ caninfo("MCAN%d ID: %d DLC: %d\n",
+ config->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
/* That that FIFO elements were configured.
*
@@ -2756,7 +2740,7 @@ static int mcan_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
}
txbuffer[0] = regval;
- canregdbg("T0: %08x\n", regval);
+ reginfo("T0: %08x\n", regval);
/* Format word T1:
* Data Length Code (DLC) - Value from message structure
@@ -2765,7 +2749,7 @@ static int mcan_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
*/
txbuffer[1] = BUFFER_R1_DLC(msg->cm_hdr.ch_dlc);
- canregdbg("T1: %08x\n", txbuffer[1]);
+ reginfo("T1: %08x\n", txbuffer[1]);
/* Followed by the amount of data corresponding to the DLC (T2..) */
@@ -2829,7 +2813,7 @@ static bool mcan_txready(FAR struct can_dev_s *dev)
FAR struct sam_mcan_s *priv = dev->cd_priv;
uint32_t regval;
bool notfull;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
int sval;
#endif
@@ -2846,7 +2830,7 @@ static bool mcan_txready(FAR struct can_dev_s *dev)
regval = mcan_getreg(priv, SAM_MCAN_TXFQS_OFFSET);
notfull = ((regval & MCAN_TXFQS_TFQF) == 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
/* As a sanity check, the txfsem should also track the number of elements
* the TX FIFO/queue. Make sure that they are consistent.
*/
@@ -2905,6 +2889,7 @@ static bool mcan_txempty(FAR struct can_dev_s *dev)
regval = mcan_getreg(priv, SAM_MCAN_TXFQS_OFFSET);
if (((regval & MCAN_TXFQS_TFQF) != 0))
{
+ mcan_dev_unlock(priv);
return false;
}
@@ -3154,7 +3139,7 @@ static void mcan_error(FAR struct can_dev_s *dev, uint32_t status,
ret = can_receive(dev, &hdr, data);
if (ret < 0)
{
- canlldbg("ERROR: can_receive failed: %d\n", ret);
+ canerr("ERROR: can_receive failed: %d\n", ret);
}
}
}
@@ -3193,7 +3178,7 @@ static void mcan_receive(FAR struct can_dev_s *dev, FAR uint32_t *rxbuffer,
/* Work R0 contains the CAN ID */
regval = *rxbuffer++;
- canregdbg("R0: %08x\n", regval);
+ reginfo("R0: %08x\n", regval);
#ifdef CONFIG_CAN_ERRORS
hdr.ch_error = 0;
@@ -3239,7 +3224,7 @@ static void mcan_receive(FAR struct can_dev_s *dev, FAR uint32_t *rxbuffer,
/* Word R1 contains the DLC and timestamp */
regval = *rxbuffer++;
- canregdbg("R1: %08x\n", regval);
+ reginfo("R1: %08x\n", regval);
hdr.ch_dlc = (regval & BUFFER_R1_DLC_MASK) >> BUFFER_R1_DLC_SHIFT;
@@ -3248,7 +3233,7 @@ static void mcan_receive(FAR struct can_dev_s *dev, FAR uint32_t *rxbuffer,
ret = can_receive(dev, &hdr, (FAR uint8_t *)rxbuffer);
if (ret < 0)
{
- canlldbg("ERROR: can_receive failed: %d\n", ret);
+ canerr("ERROR: can_receive failed: %d\n", ret);
}
}
@@ -3301,7 +3286,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
if ((pending & MCAN_CMNERR_INTS) != 0)
{
- canlldbg("ERROR: Common %08x\n", pending & MCAN_CMNERR_INTS);
+ canerr("ERROR: Common %08x\n", pending & MCAN_CMNERR_INTS);
/* Clear the error indications */
@@ -3312,7 +3297,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
if ((pending & MCAN_TXERR_INTS) != 0)
{
- canlldbg("ERROR: TX %08x\n", pending & MCAN_TXERR_INTS);
+ canerr("ERROR: TX %08x\n", pending & MCAN_TXERR_INTS);
/* Clear the error indications */
@@ -3333,7 +3318,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
if ((pending & MCAN_RXERR_INTS) != 0)
{
- canlldbg("ERROR: RX %08x\n", pending & MCAN_RXERR_INTS);
+ canerr("ERROR: RX %08x\n", pending & MCAN_RXERR_INTS);
/* Clear the error indications */
@@ -3354,7 +3339,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
{
/* All (old) errors cleared */
- canlldbg("ERROR: CLEARED\n");
+ canerr("ERROR: CLEARED\n");
mcan_error(dev, 0, priv->olderrors);
@@ -3479,7 +3464,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
if ((regval & MCAN_RXF0S_RF0L) != 0)
{
- canlldbg("ERROR: Message lost: %08x\n", regval);
+ canerr("ERROR: Message lost: %08x\n", regval);
}
else
{
@@ -3513,7 +3498,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
if ((regval & MCAN_RXF0S_RF0L) != 0)
{
- canlldbg("ERROR: Message lost: %08x\n", regval);
+ canerr("ERROR: Message lost: %08x\n", regval);
}
else
{
@@ -3607,7 +3592,7 @@ static int mcan_hw_initialize(struct sam_mcan_s *priv)
uint32_t cntr;
uint32_t cmr;
- canllvdbg("MCAN%d\n", config->port);
+ caninfo("MCAN%d\n", config->port);
/* Configure MCAN pins */
@@ -3882,7 +3867,7 @@ FAR struct can_dev_s *sam_mcan_initialize(int port)
FAR const struct sam_config_s *config;
uint32_t regval;
- canvdbg("MCAN%d\n", port);
+ caninfo("MCAN%d\n", port);
/* Select PCK5 clock source and pre-scaler value. Both MCAN controllers
* use PCK5 to derive bit rate.
@@ -3934,7 +3919,7 @@ FAR struct can_dev_s *sam_mcan_initialize(int port)
else
#endif
{
- candbg("ERROR: Unsupported port %d\n", port);
+ canerr("ERROR: Unsupported port %d\n", port);
return NULL;
}
diff --git a/arch/arm/src/samv7/sam_oneshot.c b/arch/arm/src/samv7/sam_oneshot.c
index 76c4ee1a41b418c310ba3df047ba2413c29f9b3a..4ee2467a61ed967fa3abe15f5720792392c1f458 100644
--- a/arch/arm/src/samv7/sam_oneshot.c
+++ b/arch/arm/src/samv7/sam_oneshot.c
@@ -109,7 +109,7 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
oneshot_handler_t oneshot_handler;
void *oneshot_arg;
- tcllvdbg("Expired...\n");
+ tmrinfo("Expired...\n");
DEBUGASSERT(oneshot && oneshot->handler);
/* The clock was stopped, but not disabled when the RC match occurred.
@@ -166,7 +166,7 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
uint32_t cmr;
int ret;
- tcvdbg("chan=%d resolution=%d usec\n", chan, resolution);
+ tmrinfo("chan=%d resolution=%d usec\n", chan, resolution);
DEBUGASSERT(oneshot && resolution > 0);
/* Get the TC frequency the corresponds to the requested resolution */
@@ -178,13 +178,13 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
ret = sam_tc_clockselect(frequency, &cmr, &actual);
if (ret < 0)
{
- tcdbg("ERROR: sam_tc_clockselect failed: %d\n", ret);
+ tmrerr("ERROR: sam_tc_clockselect failed: %d\n", ret);
return ret;
}
- tcvdbg("frequency=%lu, actual=%lu, cmr=%08lx\n",
- (unsigned long)frequency, (unsigned long)actual,
- (unsigned long)cmr);
+ tmrinfo("frequency=%lu, actual=%lu, cmr=%08lx\n",
+ (unsigned long)frequency, (unsigned long)actual,
+ (unsigned long)cmr);
/* Allocate the timer/counter and select its mode of operation
*
@@ -218,7 +218,7 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
oneshot->tch = sam_tc_allocate(chan, cmr);
if (!oneshot->tch)
{
- tcdbg("ERROR: Failed to allocate timer channel %d\n", chan);
+ tmrerr("ERROR: Failed to allocate timer channel %d\n", chan);
return -EBUSY;
}
@@ -261,8 +261,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
uint64_t regval;
irqstate_t flags;
- tcvdbg("handler=%p arg=%p, ts=(%lu, %lu)\n",
- handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
+ tmrinfo("handler=%p arg=%p, ts=(%lu, %lu)\n",
+ handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
DEBUGASSERT(oneshot && handler && ts);
/* Was the oneshot already running? */
@@ -272,7 +272,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
{
/* Yes.. then cancel it */
- tcvdbg("Already running... cancelling\n");
+ tmrinfo("Already running... cancelling\n");
(void)sam_oneshot_cancel(oneshot, freerun, NULL);
}
@@ -294,7 +294,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
regval = (usec * (uint64_t)sam_tc_divfreq(oneshot->tch)) / USEC_PER_SEC;
- tcvdbg("usec=%llu regval=%08llx\n", usec, regval);
+ tmrinfo("usec=%llu regval=%08llx\n", usec, regval);
DEBUGASSERT(regval <= UINT16_MAX);
/* Set up to receive the callback when the interrupt occurs */
@@ -403,7 +403,7 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
* REVISIT: This does not appear to be the case.
*/
- tcvdbg("Cancelling...\n");
+ tmrinfo("Cancelling...\n");
count = sam_tc_getcounter(oneshot->tch);
rc = sam_tc_getregister(oneshot->tch, TC_REGC);
@@ -439,8 +439,8 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
* oneshot timer.
*/
- tcvdbg("rc=%lu count=%lu usec=%lu\n",
- (unsigned long)rc, (unsigned long)count, (unsigned long)usec);
+ tmrinfo("rc=%lu count=%lu usec=%lu\n",
+ (unsigned long)rc, (unsigned long)count, (unsigned long)usec);
/* REVISIT: I am not certain why the timer counter value sometimes
* exceeds RC. Might be a bug, or perhaps the counter does not stop
@@ -484,8 +484,8 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
ts->tv_nsec = (unsigned long)nsec;
}
- tcvdbg("remaining (%lu, %lu)\n",
- (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
+ tmrinfo("remaining (%lu, %lu)\n",
+ (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
}
return OK;
diff --git a/arch/arm/src/samv7/sam_pck.c b/arch/arm/src/samv7/sam_pck.c
index c4dc27d0295f051496b6ffe238810cfce2e636a4..3511d0d9ce9c2ad7a24e9f637ab18ae5ae3e5c10 100644
--- a/arch/arm/src/samv7/sam_pck.c
+++ b/arch/arm/src/samv7/sam_pck.c
@@ -128,7 +128,7 @@ uint32_t sam_pck_configure(enum pckid_e pckid, enum pckid_clksrc_e clksrc,
break;
default:
- dbg("ERROR: Unknown clock source\n");
+ _err("ERROR: Unknown clock source\n");
return 0;
}
@@ -272,7 +272,7 @@ uint32_t sam_pck_frequency(enum pckid_e pckid)
break;
default:
- dbg("ERROR: Unknown clock source\n");
+ _err("ERROR: Unknown clock source\n");
return 0;
}
diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c
index e63a6ce22b16a6419c1e71181d49e465bb260caf..b90a515d8b00efb6f645a5010076e2d0317b33b3 100644
--- a/arch/arm/src/samv7/sam_qspi.c
+++ b/arch/arm/src/samv7/sam_qspi.c
@@ -85,6 +85,10 @@
# define CONFIG_SAMV7_QSPI_DLYBCT 0
#endif
+#ifndef CONFIG_DEBUG_SPI_INFO
+# undef CONFIG_SAMV7_QSPI_REGDEBUG
+#endif
+
/* When QSPI DMA is enabled, small DMA transfers will still be performed by
* polling logic. But we need a threshold value to determine what is small.
* That value is provided by CONFIG_SAMV7_QSPI_DMATHRESHOLD.
@@ -138,33 +142,12 @@
#define IS_ALIGNED(n) (((uint32_t)(n) & ALIGN_MASK) == 0)
/* Debug *******************************************************************/
-/* Check if QSPI debug is enabled (non-standard.. no support in
- * include/debug.h
- */
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# undef CONFIG_DEBUG_SPI
-# undef CONFIG_SAMV7_QSPI_DMADEBUG
-# undef CONFIG_SAMV7_QSPI_REGDEBUG
-#endif
+/* Check if QSPI debug is enabled */
#ifndef CONFIG_DEBUG_DMA
# undef CONFIG_SAMV7_QSPI_DMADEBUG
#endif
-#ifdef CONFIG_DEBUG_SPI
-# define qspidbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define qspivdbg lldbg
-# else
-# define qspivdbg(x...)
-# endif
-#else
-# define qspidbg(x...)
-# define qspivdbg(x...)
-#endif
-
#define DMA_INITIAL 0
#define DMA_AFTER_SETUP 1
#define DMA_AFTER_START 2
@@ -243,7 +226,7 @@ static inline uint32_t qspi_getreg(struct sam_qspidev_s *priv,
static inline void qspi_putreg(struct sam_qspidev_s *priv, uint32_t value,
unsigned int offset);
-#if defined(CONFIG_DEBUG_SPI) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_SPI_INFO
static void qspi_dumpregs(struct sam_qspidev_s *priv, const char *msg);
#else
# define qspi_dumpregs(priv,msg)
@@ -395,7 +378,7 @@ static bool qspi_checkreg(struct sam_qspidev_s *priv, bool wr, uint32_t value,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", priv->ntimes);
+ spiinfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@@ -429,7 +412,7 @@ static inline uint32_t qspi_getreg(struct sam_qspidev_s *priv,
#ifdef CONFIG_SAMV7_QSPI_REGDEBUG
if (qspi_checkreg(priv, false, value, address))
{
- lldbg("%08x->%08x\n", address, value);
+ spiinfo("%08x->%08x\n", address, value);
}
#endif
@@ -452,7 +435,7 @@ static inline void qspi_putreg(struct sam_qspidev_s *priv, uint32_t value,
#ifdef CONFIG_SAMV7_QSPI_REGDEBUG
if (qspi_checkreg(priv, true, value, address))
{
- lldbg("%08x<-%08x\n", address, value);
+ spiinfo("%08x<-%08x\n", address, value);
}
#endif
@@ -474,23 +457,23 @@ static inline void qspi_putreg(struct sam_qspidev_s *priv, uint32_t value,
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_SPI) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_SPI_INFO
static void qspi_dumpregs(struct sam_qspidev_s *priv, const char *msg)
{
- qspivdbg("%s:\n", msg);
- qspivdbg(" MR:%08x SR:%08x IMR:%08x SCR:%08x\n",
- getreg32(priv->base + SAM_QSPI_MR_OFFSET),
- getreg32(priv->base + SAM_QSPI_SR_OFFSET),
- getreg32(priv->base + SAM_QSPI_IMR_OFFSET),
- getreg32(priv->base + SAM_QSPI_SCR_OFFSET));
- qspivdbg(" IAR:%08x ICR:%08x IFR:%08x SMR:%08x\n",
- getreg32(priv->base + SAM_QSPI_IAR_OFFSET),
- getreg32(priv->base + SAM_QSPI_ICR_OFFSET),
- getreg32(priv->base + SAM_QSPI_IFR_OFFSET),
- getreg32(priv->base + SAM_QSPI_SMR_OFFSET));
- qspivdbg(" WPCR:%08x WPSR:%08x\n",
- getreg32(priv->base + SAM_QSPI_WPCR_OFFSET),
- getreg32(priv->base + SAM_QSPI_WPSR_OFFSET));
+ spiinfo("%s:\n", msg);
+ spiinfo(" MR:%08x SR:%08x IMR:%08x SCR:%08x\n",
+ getreg32(priv->base + SAM_QSPI_MR_OFFSET),
+ getreg32(priv->base + SAM_QSPI_SR_OFFSET),
+ getreg32(priv->base + SAM_QSPI_IMR_OFFSET),
+ getreg32(priv->base + SAM_QSPI_SCR_OFFSET));
+ spiinfo(" IAR:%08x ICR:%08x IFR:%08x SMR:%08x\n",
+ getreg32(priv->base + SAM_QSPI_IAR_OFFSET),
+ getreg32(priv->base + SAM_QSPI_ICR_OFFSET),
+ getreg32(priv->base + SAM_QSPI_IFR_OFFSET),
+ getreg32(priv->base + SAM_QSPI_SMR_OFFSET));
+ spiinfo(" WPCR:%08x WPSR:%08x\n",
+ getreg32(priv->base + SAM_QSPI_WPCR_OFFSET),
+ getreg32(priv->base + SAM_QSPI_WPSR_OFFSET));
}
#endif
@@ -866,7 +849,7 @@ static int qspi_memory_dma(struct sam_qspidev_s *priv,
if (ret < 0)
{
- qspidbg("ERROR: DMA setup failed: %d\n", ret);
+ spierr("ERROR: DMA setup failed: %d\n", ret);
return ret;
}
@@ -882,7 +865,7 @@ static int qspi_memory_dma(struct sam_qspidev_s *priv,
ret = sam_dmastart(priv->dmach, qspi_dma_callback, (void *)priv);
if (ret < 0)
{
- qspidbg("ERROR: sam_dmastart failed: %d\n", ret);
+ spierr("ERROR: sam_dmastart failed: %d\n", ret);
return ret;
}
@@ -903,7 +886,7 @@ static int qspi_memory_dma(struct sam_qspidev_s *priv,
(wdentry_t)qspi_dma_timeout, 1, (uint32_t)priv);
if (ret != OK)
{
- qspidbg("ERROR: wd_start failed: %d\n", ret);
+ spierr("ERROR: wd_start failed: %d\n", ret);
}
/* Wait for the DMA complete */
@@ -961,7 +944,7 @@ static int qspi_memory_dma(struct sam_qspidev_s *priv,
if (priv->result)
{
- qspidbg("ERROR: DMA failed with result: %d\n", priv->result);
+ spierr("ERROR: DMA failed with result: %d\n", priv->result);
}
return priv->result;
@@ -1078,7 +1061,7 @@ static int qspi_lock(struct qspi_dev_s *dev, bool lock)
{
struct sam_qspidev_s *priv = (struct sam_qspidev_s *)dev;
- qspivdbg("lock=%d\n", lock);
+ spiinfo("lock=%d\n", lock);
if (lock)
{
/* Take the semaphore (perhaps waiting) */
@@ -1128,7 +1111,7 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency)
#endif
uint32_t regval;
- qspivdbg("frequency=%d\n", frequency);
+ spiinfo("frequency=%d\n", frequency);
DEBUGASSERT(priv);
/* Check if the requested frequency is the same as the frequency selection */
@@ -1215,14 +1198,14 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency)
/* Calculate the new actual frequency */
actual = SAM_QSPI_CLOCK / scbr;
- qspivdbg("SCBR=%d actual=%d\n", scbr, actual);
+ spiinfo("SCBR=%d actual=%d\n", scbr, actual);
/* Save the frequency setting */
priv->frequency = frequency;
priv->actual = actual;
- qspivdbg("Frequency %d->%d\n", frequency, actual);
+ spiinfo("Frequency %d->%d\n", frequency, actual);
return actual;
}
@@ -1246,7 +1229,7 @@ static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode)
struct sam_qspidev_s *priv = (struct sam_qspidev_s *)dev;
uint32_t regval;
- qspivdbg("mode=%d\n", mode);
+ spiinfo("mode=%d\n", mode);
/* Has the mode changed? */
@@ -1288,7 +1271,7 @@ static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode)
}
qspi_putreg(priv, regval, SAM_QSPI_SCR_OFFSET);
- qspivdbg("SCR=%08x\n", regval);
+ spiinfo("SCR=%08x\n", regval);
/* Save the mode so that subsequent re-configurations will be faster */
@@ -1316,7 +1299,7 @@ static void qspi_setbits(struct qspi_dev_s *dev, int nbits)
struct sam_qspidev_s *priv = (struct sam_qspidev_s *)dev;
uint32_t regval;
- qspivdbg("nbits=%d\n", nbits);
+ spiinfo("nbits=%d\n", nbits);
DEBUGASSERT(priv != NULL);
DEBUGASSERT(nbits >= SAM_QSPI_MINBITS && nbits <= SAM_QSPI_MAXBITS);
@@ -1331,7 +1314,7 @@ static void qspi_setbits(struct qspi_dev_s *dev, int nbits)
regval |= QSPI_MR_NBBITS(nbits);
qspi_putreg(priv, regval, SAM_QSPI_MR_OFFSET);
- qspivdbg("MR=%08x\n", regval);
+ spiinfo("MR=%08x\n", regval);
/* Save the selection so the subsequence re-configurations will be faster */
@@ -1363,21 +1346,21 @@ static int qspi_command(struct qspi_dev_s *dev,
DEBUGASSERT(priv != NULL && cmdinfo != NULL);
-#ifdef CONFIG_DEBUG_SPI
- qspivdbg("Transfer:\n");
- qspivdbg(" flags: %02x\n", cmdinfo->flags);
- qspivdbg(" cmd: %04x\n", cmdinfo->cmd);
+#ifdef CONFIG_DEBUG_SPI_INFO
+ spiinfo("Transfer:\n");
+ spiinfo(" flags: %02x\n", cmdinfo->flags);
+ spiinfo(" cmd: %04x\n", cmdinfo->cmd);
if (QSPICMD_ISADDRESS(cmdinfo->flags))
{
- qspivdbg(" address/length: %08lx/%d\n",
+ spiinfo(" address/length: %08lx/%d\n",
(unsigned long)cmdinfo->addr, cmdinfo->addrlen);
}
if (QSPICMD_ISDATA(cmdinfo->flags))
{
- qspivdbg(" %s Data:\n", QSPICMD_ISWRITE(cmdinfo->flags) ? "Write" : "Read");
- qspivdbg(" buffer/length: %p/%d\n", cmdinfo->buffer, cmdinfo->buflen);
+ spiinfo(" %s Data:\n", QSPICMD_ISWRITE(cmdinfo->flags) ? "Write" : "Read");
+ spiinfo(" buffer/length: %p/%d\n", cmdinfo->buffer, cmdinfo->buflen);
}
#endif
@@ -1572,13 +1555,13 @@ static int qspi_memory(struct qspi_dev_s *dev,
DEBUGASSERT(priv != NULL && meminfo != NULL);
- qspivdbg("Transfer:\n");
- qspivdbg(" flags: %02x\n", meminfo->flags);
- qspivdbg(" cmd: %04x\n", meminfo->cmd);
- qspivdbg(" address/length: %08lx/%d\n",
- (unsigned long)meminfo->addr, meminfo->addrlen);
- qspivdbg(" %s Data:\n", QSPIMEM_ISWRITE(meminfo->flags) ? "Write" : "Read");
- qspivdbg(" buffer/length: %p/%d\n", meminfo->buffer, meminfo->buflen);
+ spiinfo("Transfer:\n");
+ spiinfo(" flags: %02x\n", meminfo->flags);
+ spiinfo(" cmd: %04x\n", meminfo->cmd);
+ spiinfo(" address/length: %08lx/%d\n",
+ (unsigned long)meminfo->addr, meminfo->addrlen);
+ spiinfo(" %s Data:\n", QSPIMEM_ISWRITE(meminfo->flags) ? "Write" : "Read");
+ spiinfo(" buffer/length: %p/%d\n", meminfo->buffer, meminfo->buflen);
#ifdef CONFIG_SAMV7_QSPI_DMA
/* Can we perform DMA? Should we perform DMA? */
@@ -1746,7 +1729,7 @@ struct qspi_dev_s *sam_qspi_initialize(int intf)
/* The supported SAM parts have only a single QSPI port */
- qspivdbg("intf: %d\n", intf);
+ spiinfo("intf: %d\n", intf);
DEBUGASSERT(intf >= 0 && intf < SAMV7_NQSPI);
/* Select the QSPI interface */
@@ -1778,7 +1761,7 @@ struct qspi_dev_s *sam_qspi_initialize(int intf)
else
#endif
{
- qspidbg("ERROR: QSPI%d not supported\n", intf);
+ spierr("ERROR: QSPI%d not supported\n", intf);
return NULL;
}
@@ -1801,7 +1784,7 @@ struct qspi_dev_s *sam_qspi_initialize(int intf)
priv->dmach = sam_dmachannel(0, 0);
if (!priv->dmach)
{
- qspidbg("ERROR: Failed to allocate the DMA channel\n");
+ spierr("ERROR: Failed to allocate the DMA channel\n");
priv->candma = false;
}
}
@@ -1817,7 +1800,7 @@ struct qspi_dev_s *sam_qspi_initialize(int intf)
priv->dmadog = wd_create();
if (priv->dmadog == NULL)
{
- qspidbg("ERROR: Failed to create wdog\n");
+ spierr("ERROR: Failed to create wdog\n");
goto errout_with_dmahandles;
}
#endif
@@ -1828,7 +1811,7 @@ struct qspi_dev_s *sam_qspi_initialize(int intf)
ret = irq_attach(priv->irq, priv->handler);
if (ret < 0)
{
- qspidbg("ERROR: Failed to attach irq %d\n", priv->irq);
+ spierr("ERROR: Failed to attach irq %d\n", priv->irq);
goto errout_with_dmadog;
}
#endif
@@ -1840,7 +1823,7 @@ struct qspi_dev_s *sam_qspi_initialize(int intf)
ret = qspi_hw_initialize(priv);
if (ret < 0)
{
- qspidbg("ERROR: Failed to initialize QSPI hardware\n");
+ spierr("ERROR: Failed to initialize QSPI hardware\n");
goto errout_with_irq;
}
diff --git a/arch/arm/src/samv7/sam_rswdt.c b/arch/arm/src/samv7/sam_rswdt.c
index 20ea3c2183402877cfabd7f1d8c22ebeb0481381..980ecd5b037369ea1f511434a08fb3ed45ce0d08 100644
--- a/arch/arm/src/samv7/sam_rswdt.c
+++ b/arch/arm/src/samv7/sam_rswdt.c
@@ -57,6 +57,11 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
+
+#ifndef CONFIG_DEBUG_WATCHDOG_INFO
+# undef CONFIG_SAMV7_RSWDT_REGDEBUG
+#endif
+
/* The Watchdog Timer uses the Slow Clock divided by 128 to establish the
* maximum Watchdog period to be 16 seconds (with a typical Slow Clock of
* 32768 kHz).
@@ -80,20 +85,6 @@
#define RSWDT_MINTIMEOUT ((1000 + RSWDT_FREQUENCY - 1) / RSWDT_FREQUENCY)
#define RSWDT_MAXTIMEOUT ((4096 * 1000) / RSWDT_FREQUENCY)
-/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing the watchdog
- * driver. NOTE: that only lldbg types are used so that the output is
- * immediately available.
- */
-
-#ifdef CONFIG_DEBUG_WATCHDOG
-# define wddbg lldbg
-# define wdvdbg llvdbg
-#else
-# define wddbg(x...)
-# define wdvdbg(x...)
-#endif
-
/****************************************************************************
* Private Types
****************************************************************************/
@@ -118,7 +109,7 @@ struct sam_lowerhalf_s
****************************************************************************/
/* Register operations ******************************************************/
-#if defined(CONFIG_SAMV7_RSWDT_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAMV7_RSWDT_REGDEBUG
static uint32_t sam_getreg(uintptr_t regaddr);
static void sam_putreg(uint32_t regval, uintptr_t regaddr);
#else
@@ -178,7 +169,7 @@ static struct sam_lowerhalf_s g_wdtdev;
*
****************************************************************************/
-#if defined(CONFIG_SAMV7_RSWDT_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAMV7_RSWDT_REGDEBUG
static uint32_t sam_getreg(uintptr_t regaddr)
{
static uint32_t prevaddr = 0;
@@ -199,7 +190,7 @@ static uint32_t sam_getreg(uintptr_t regaddr)
{
if (count == 4)
{
- lldbg("...\n");
+ wdinfo("...\n");
}
return regval;
@@ -216,7 +207,7 @@ static uint32_t sam_getreg(uintptr_t regaddr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ wdinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -228,7 +219,7 @@ static uint32_t sam_getreg(uintptr_t regaddr)
/* Show the register value read */
- lldbg("%08x->%048\n", regaddr, regval);
+ wdinfo("%08x->%048\n", regaddr, regval);
return regval;
}
#endif
@@ -241,12 +232,12 @@ static uint32_t sam_getreg(uintptr_t regaddr)
*
****************************************************************************/
-#if defined(CONFIG_SAMV7_RSWDT_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAMV7_RSWDT_REGDEBUG
static void sam_putreg(uint32_t regval, uintptr_t regaddr)
{
/* Show the register value being written */
- lldbg("%08x<-%08x\n", regaddr, regval);
+ wdinfo("%08x<-%08x\n", regaddr, regval);
/* Write the value */
@@ -315,7 +306,7 @@ static int sam_start(FAR struct watchdog_lowerhalf_s *lower)
* timer with the newly programmed mode parameters.
*/
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
return priv->started ? OK : -ENOSYS;
}
@@ -343,7 +334,7 @@ static int sam_stop(FAR struct watchdog_lowerhalf_s *lower)
* timer with the newly programmed mode parameters.
*/
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
return -ENOSYS;
}
@@ -366,7 +357,7 @@ static int sam_stop(FAR struct watchdog_lowerhalf_s *lower)
static int sam_keepalive(FAR struct watchdog_lowerhalf_s *lower)
{
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
/* Write RSWDT_CR_WDRSTT to the RSWDT CR regiser (along with the KEY value)
* will restart the watchdog timer.
@@ -397,7 +388,7 @@ static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower,
{
FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower;
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
DEBUGASSERT(priv);
/* Return the status bit */
@@ -426,10 +417,10 @@ static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower,
status->timeleft = 0;
- wdvdbg("Status :\n");
- wdvdbg(" flags : %08x\n", status->flags);
- wdvdbg(" timeout : %d\n", status->timeout);
- wdvdbg(" timeleft : %d\n", status->timeleft);
+ wdinfo("Status :\n");
+ wdinfo(" flags : %08x\n", status->flags);
+ wdinfo(" timeout : %d\n", status->timeout);
+ wdinfo(" timeleft : %d\n", status->timeleft);
return OK;
}
@@ -457,13 +448,13 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower,
uint32_t regval;
DEBUGASSERT(priv);
- wdvdbg("Entry: timeout=%d\n", timeout);
+ wdinfo("Entry: timeout=%d\n", timeout);
/* Can this timeout be represented? */
if (timeout < RSWDT_MINTIMEOUT || timeout >= RSWDT_MAXTIMEOUT)
{
- wddbg("Cannot represent timeout: %d < %d > %d\n",
+ wderr("ERROR: Cannot represent timeout: %d < %d > %d\n",
RSWDT_MINTIMEOUT, timeout, RSWDT_MAXTIMEOUT);
return -ERANGE;
}
@@ -496,7 +487,7 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower,
priv->reload = reload;
- wdvdbg("reload=%d timout: %d->%d\n",
+ wdinfo("reload=%d timout: %d->%d\n",
reload, timeout, priv->timeout);
/* Set the RSWDT_MR according to calculated value
@@ -541,7 +532,7 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower,
priv->started = true;
- wdvdbg("Setup: CR: %08x MR: %08x SR: %08x\n",
+ wdinfo("Setup: CR: %08x MR: %08x SR: %08x\n",
sam_getreg(SAM_RSWDT_CR), sam_getreg(SAM_RSWDT_MR),
sam_getreg(SAM_RSWDT_SR));
@@ -574,7 +565,7 @@ static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower,
xcpt_t handler)
{
#ifndef CONFIG_SAMV7_RSWDT_INTERRUPT
- wddbg("ERROR: Not configured for this mode\n");
+ wderr("ERROR: Not configured for this mode\n");
return NULL;
#else
FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower;
@@ -582,7 +573,7 @@ static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower,
xcpt_t oldhandler;
DEBUGASSERT(priv);
- wdvdbg("Entry: handler=%p\n", handler);
+ wdinfo("Entry: handler=%p\n", handler);
/* Get the old handler return value */
@@ -636,7 +627,7 @@ static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower,
static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
unsigned long arg)
{
- wdvdbg("cmd=%d arg=%ld\n", cmd, arg);
+ wdinfo("cmd=%d arg=%ld\n", cmd, arg);
/* No ioctls are supported */
@@ -667,7 +658,7 @@ int sam_rswdt_initialize(void)
{
FAR struct sam_lowerhalf_s *priv = &g_wdtdev;
- wdvdbg("Entry: CR: %08x MR: %08x SR: %08x\n",
+ wdinfo("Entry: CR: %08x MR: %08x SR: %08x\n",
sam_getreg(SAM_RSWDT_CR), sam_getreg(SAM_RSWDT_MR),
sam_getreg(SAM_RSWDT_SR));
diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c
index 0d9f1ec32a114158e17c99b619a4323b251d4b2f..df176330991389ad75ddc58dd80f418e2ce05d71 100644
--- a/arch/arm/src/samv7/sam_spi.c
+++ b/arch/arm/src/samv7/sam_spi.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/samv7/sam_spi.c
*
- * Copyright (C) 2015=2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt
* Diego Sanchez
*
@@ -105,6 +105,14 @@
# undef CONFIG_SAMV7_SPI_DMADEBUG
#endif
+#ifndef CONFIG_DEBUG_DMA_INFO
+# undef CONFIG_SAMV7_SPI_DMADEBUG
+#endif
+
+#ifndef CONFIG_DEBUG_SPI_INFO
+# undef CONFIG_SAMV7_SPI_REGDEBUG
+#endif
+
/* Clocking *****************************************************************/
/* The SPI Baud rate clock is generated by dividing the peripheral clock by
* a value between 1 and 255
@@ -120,33 +128,12 @@
#define DMA_TIMEOUT_TICKS MSEC2TICK(DMA_TIMEOUT_MS)
/* Debug *******************************************************************/
-/* Check if SPI debug is enabled (non-standard.. no support in
- * include/debug.h
- */
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# undef CONFIG_DEBUG_SPI
-# undef CONFIG_SAMV7_SPI_DMADEBUG
-# undef CONFIG_SAMV7_SPI_REGDEBUG
-#endif
+/* Check if SPI debug is enabled */
#ifndef CONFIG_DEBUG_DMA
# undef CONFIG_SAMV7_SPI_DMADEBUG
#endif
-#ifdef CONFIG_DEBUG_SPI
-# define spidbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define spivdbg lldbg
-# else
-# define spivdbg(x...)
-# endif
-#else
-# define spidbg(x...)
-# define spivdbg(x...)
-#endif
-
#define DMA_INITIAL 0
#define DMA_AFTER_SETUP 1
#define DMA_AFTER_START 2
@@ -205,6 +192,7 @@ struct sam_spidev_s
sem_t spisem; /* Assures mutually exclusive access to SPI */
select_t select; /* SPI select call-out */
bool initialized; /* TRUE: Controller has been initialized */
+ bool escape_lastxfer; /* Dont set LASTXFER-Bit in the next transfer */
#ifdef CONFIG_SAMV7_SPI_DMA
uint8_t pid; /* SPI peripheral ID */
#endif
@@ -238,7 +226,7 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value,
unsigned int offset);
static inline struct sam_spidev_s *spi_device(struct sam_spics_s *spics);
-#if defined(CONFIG_DEBUG_SPI) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_SPI_INFO
static void spi_dumpregs(struct sam_spidev_s *spi, const char *msg);
#else
# define spi_dumpregs(spi,msg)
@@ -277,6 +265,12 @@ static int spi_lock(struct spi_dev_s *dev, bool lock);
static void spi_select(struct spi_dev_s *dev, enum spi_dev_e devid,
bool selected);
static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency);
+#ifdef CONFIG_SPI_CS_DELAY_CONTROL
+static int spi_setdelay(struct spi_dev_s *dev, uint32_t a, uint32_t b, uint32_t c);
+#endif
+#ifdef CONFIG_SPI_HWFEATURES
+static int spi_hwfeatures(struct spi_dev_s *dev, uint8_t features);
+#endif
static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode);
static void spi_setbits(struct spi_dev_s *dev, int nbits);
static uint16_t spi_send(struct spi_dev_s *dev, uint16_t ch);
@@ -324,10 +318,13 @@ static const struct spi_ops_s g_spi0ops =
.lock = spi_lock,
.select = spi_select,
.setfrequency = spi_setfrequency,
+#ifdef CONFIG_SPI_CS_DELAY_CONTROL
+ .setdelay = spi_setdelay,
+#endif
.setmode = spi_setmode,
.setbits = spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
- .hwfeatures = 0, /* Not supported */
+ .hwfeatures = spi_hwfeatures,
#endif
.status = sam_spi0status,
#ifdef CONFIG_SPI_CMDDATA
@@ -363,6 +360,9 @@ static const struct spi_ops_s g_spi1ops =
.lock = spi_lock,
.select = spi_select,
.setfrequency = spi_setfrequency,
+#ifdef CONFIG_SPI_CS_DELAY_CONTROL
+ .setdelay = spi_setdelay,
+#endif
.setmode = spi_setmode,
.setbits = spi_setbits,
.status = sam_spi1status,
@@ -436,7 +436,7 @@ static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, uint32_t value,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", spi->ntimes);
+ spiinfo("...[Repeats %d times]...\n", spi->ntimes);
}
/* Save information about the new access */
@@ -470,7 +470,7 @@ static inline uint32_t spi_getreg(struct sam_spidev_s *spi,
#ifdef CONFIG_SAMV7_SPI_REGDEBUG
if (spi_checkreg(spi, false, value, address))
{
- lldbg("%08x->%08x\n", address, value);
+ spiinfo("%08x->%08x\n", address, value);
}
#endif
@@ -493,7 +493,7 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value,
#ifdef CONFIG_SAMV7_SPI_REGDEBUG
if (spi_checkreg(spi, true, value, address))
{
- lldbg("%08x<-%08x\n", address, value);
+ spiinfo("%08x<-%08x\n", address, value);
}
#endif
@@ -515,20 +515,20 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value,
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_SPI) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_SPI_INFO
static void spi_dumpregs(struct sam_spidev_s *spi, const char *msg)
{
- spivdbg("%s:\n", msg);
- spivdbg(" MR:%08x SR:%08x IMR:%08x\n",
+ spiinfo("%s:\n", msg);
+ spiinfo(" MR:%08x SR:%08x IMR:%08x\n",
getreg32(spi->base + SAM_SPI_MR_OFFSET),
getreg32(spi->base + SAM_SPI_SR_OFFSET),
getreg32(spi->base + SAM_SPI_IMR_OFFSET));
- spivdbg(" CSR0:%08x CSR1:%08x CSR2:%08x CSR3:%08x\n",
+ spiinfo(" CSR0:%08x CSR1:%08x CSR2:%08x CSR3:%08x\n",
getreg32(spi->base + SAM_SPI_CSR0_OFFSET),
getreg32(spi->base + SAM_SPI_CSR1_OFFSET),
getreg32(spi->base + SAM_SPI_CSR2_OFFSET),
getreg32(spi->base + SAM_SPI_CSR3_OFFSET));
- spivdbg(" WPCR:%08x WPSR:%08x\n",
+ spiinfo(" WPCR:%08x WPSR:%08x\n",
getreg32(spi->base + SAM_SPI_WPCR_OFFSET),
getreg32(spi->base + SAM_SPI_WPSR_OFFSET));
}
@@ -903,7 +903,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock)
struct sam_spics_s *spics = (struct sam_spics_s *)dev;
struct sam_spidev_s *spi = spi_device(spics);
- spivdbg("lock=%d\n", lock);
+ spiinfo("lock=%d\n", lock);
if (lock)
{
/* Take the semaphore (perhaps waiting) */
@@ -951,10 +951,10 @@ static void spi_select(struct spi_dev_s *dev, enum spi_dev_e devid,
/* Are we selecting or de-selecting the device? */
- spivdbg("selected=%d\n", selected);
+ spiinfo("selected=%d\n", selected);
if (selected)
{
- spivdbg("cs=%d\n", spics->cs);
+ spiinfo("cs=%d\n", spics->cs);
/* Before writing the TDR, the PCS field in the SPI_MR register must be set
* in order to select a slave.
@@ -962,7 +962,18 @@ static void spi_select(struct spi_dev_s *dev, enum spi_dev_e devid,
regval = spi_getreg(spi, SAM_SPI_MR_OFFSET);
regval &= ~SPI_MR_PCS_MASK;
+
+ /* SPI_VARSELECT means, that the ChipSelect for each device is set within
+ * the transferred data (SAM_SPI_TDR) instead inside the mode register
+ * (SAM_SPI_MR).
+ * In addition, the LASTXFER flag is also set within the transferred data
+ * (SAM_SPI_TDR) instead inside the control register (SAM_SPI_CR).
+ * (see spi_exchange)
+ */
+
+#ifndef CONFIG_SAMV7_SPI_VARSELECT
regval |= (spi_cs2pcs(spics) << SPI_MR_PCS_SHIFT);
+#endif
spi_putreg(spi, regval, SAM_SPI_MR_OFFSET);
}
@@ -1009,7 +1020,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
uint32_t regval;
unsigned int offset;
- spivdbg("cs=%d frequency=%d\n", spics->cs, frequency);
+ spiinfo("cs=%d frequency=%d\n", spics->cs, frequency);
/* Check if the requested frequency is the same as the frequency selection */
@@ -1027,9 +1038,9 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
scbr = SAM_SPI_CLOCK / frequency;
- if (scbr < 8)
+ if (scbr < 2)
{
- scbr = 8;
+ scbr = 2;
}
else if (scbr > 254)
{
@@ -1079,17 +1090,200 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
/* Calculate the new actual frequency */
actual = SAM_SPI_CLOCK / scbr;
- spivdbg("csr[offset=%02x]=%08x actual=%d\n", offset, regval, actual);
+ spiinfo("csr[offset=%02x]=%08x actual=%d\n", offset, regval, actual);
/* Save the frequency setting */
spics->frequency = frequency;
spics->actual = actual;
- spidbg("Frequency %d->%d\n", frequency, actual);
+ spiinfo("Frequency %d->%d\n", frequency, actual);
return actual;
}
+/****************************************************************************
+ * Name: spi_setdelay
+ *
+ * Description:
+ * Set the SPI Delays in nanoseconds. Optional.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * startdelay - The delay between CS active and first CLK
+ * stopdelay - The delay between last CLK and CS inactive
+ * csdelay - The delay between CS inactive and CS active again
+ *
+ * Returned Value:
+ * Returns 0 if ok
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_CS_DELAY_CONTROL
+static int spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
+ uint32_t stopdelay, uint32_t csdelay)
+{
+ struct sam_spics_s *spics = (struct sam_spics_s *)dev;
+ struct sam_spidev_s *spi = spi_device(spics);
+ uint64_t dlybs;
+ uint64_t dlybct;
+ uint64_t dlybcs;
+ uint32_t regval;
+ unsigned int offset;
+
+ spiinfo("cs=%d startdelay=%d\n", spics->cs, startdelay);
+ spiinfo("cs=%d stopdelay=%d\n", spics->cs, stopdelay);
+ spiinfo("cs=%d csdelay=%d\n", spics->cs, csdelay);
+
+ offset = (unsigned int)g_csroffset[spics->cs];
+
+ /* startdelay = DLYBS: Delay Before SPCK.
+ * This field defines the delay from NPCS valid to the first valid SPCK
+ * transition. When DLYBS equals zero, the NPCS valid to SPCK transition is
+ * 1/2 the SPCK clock period.
+ * Otherwise, the following equations determine the delay:
+ *
+ * Delay Before SPCK = DLYBS / SPI_CLK
+ *
+ * For a 2uS delay
+ *
+ * DLYBS = SPI_CLK * 0.000002 = SPI_CLK / 500000
+ *
+ * TODO: Check for boundaries!
+ */
+
+ dlybs = SAM_SPI_CLOCK;
+ dlybs *= startdelay;
+ dlybs /= 1000000000;
+ regval = spi_getreg(spi, offset);
+ regval &= ~SPI_CSR_DLYBS_MASK;
+ regval |= (uint32_t) dlybs << SPI_CSR_DLYBS_SHIFT;
+
+ /* stopdelay = DLYBCT: Delay Between Consecutive Transfers.
+ * This field defines the delay between two consecutive transfers with the
+ * same peripheral without removing the chip select. The delay is always
+ * inserted after each transfer and before removing the chip select if
+ * needed.
+ *
+ * Delay Between Consecutive Transfers = (32 x DLYBCT) / SPI_CLK
+ *
+ * For a 5uS delay:
+ *
+ * DLYBCT = SPI_CLK * 0.000005 / 32 = SPI_CLK / 200000 / 32
+ */
+
+ dlybct = SAM_SPI_CLOCK;
+ dlybct *= stopdelay;
+ dlybct /= 1000000000;
+ dlybct /= 32;
+ regval = spi_getreg(spi, offset);
+ regval &= ~SPI_CSR_DLYBCT_MASK;
+ regval |= (uint32_t) dlybct << SPI_CSR_DLYBCT_SHIFT;
+ spi_putreg(spi, regval, offset);
+
+ /* csdelay = DLYBCS: Delay Between Chip Selects.
+ * This field defines the delay between the inactivation and the activation
+ * of NPCS. The DLYBCS time guarantees non-overlapping chip selects and
+ * solves bus contentions in case of peripherals having long data float
+ * times. If DLYBCS is lower than 6, six peripheral clock periods are
+ * inserted by default.
+ *
+ * Delay Between Chip Selects = DLYBCS / SPI_CLK
+ *
+ * DLYBCS = SPI_CLK * Delay
+ */
+ dlybcs = SAM_SPI_CLOCK;
+ dlybcs *= csdelay;
+ dlybcs /= 1000000000;
+ regval = spi_getreg(spi, SAM_SPI_MR_OFFSET);
+ regval &= ~SPI_MR_DLYBCS_MASK;
+ regval |= dlybcs << SPI_MR_DLYBCS_SHIFT;
+ spi_putreg(spi, regval, SAM_SPI_MR_OFFSET);
+
+ return 0;
+}
+#endif
+
+/****************************************************************************
+ * Name: spi_hwfeatures
+ *
+ * Description:
+ * Use some super-special hardware Features. Optional.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * features - Bitmask of the activated features
+ *
+ * Returned Value:
+ * Returns 0 if ok
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_HWFEATURES
+static int spi_hwfeatures(struct spi_dev_s *dev, uint8_t features)
+{
+ struct sam_spics_s *spics = (struct sam_spics_s *)dev;
+ struct sam_spidev_s *spi = spi_device(spics);
+ uint32_t regval;
+ unsigned int offset;
+
+ /* CS rises after every Transmission, also if we provide new data
+ * immediately.
+ */
+
+ if (features & HWFEAT_FORCE_CS_INACTIVE_AFTER_TRANSFER)
+ {
+ offset = (unsigned int)g_csroffset[spics->cs];
+ regval = spi_getreg(spi, offset);
+ regval |= SPI_CSR_CSNAAT; /* Chip Select Not Active After Transfer */
+ regval &= ~SPI_CSR_CSAAT; /* Chip Select Active After Transfer */
+ spi_putreg(spi, regval, offset);
+ }
+ else
+ {
+ offset = (unsigned int)g_csroffset[spics->cs];
+ regval = spi_getreg(spi, offset);
+ regval &= ~SPI_CSR_CSNAAT; /* Chip Select Not Active After Transfer */
+ spi_putreg(spi, regval, offset);
+ }
+
+ /* CS does not rise automatically after a transmission, also if the spi runs
+ * out of data (for a long time)
+ */
+
+ if ((features & HWFEAT_FORCE_CS_ACTIVE_AFTER_TRANSFER) != 0)
+ {
+ offset = (unsigned int)g_csroffset[spics->cs];
+ regval = spi_getreg(spi, offset);
+ regval &= ~SPI_CSR_CSNAAT; /* Chip Select Not Active After Transfer */
+ regval |= SPI_CSR_CSAAT; /* Chip Select Active After Transfer */
+ spi_putreg(spi, regval, offset);
+ }
+ else
+ {
+ offset = (unsigned int)g_csroffset[spics->cs];
+ regval = spi_getreg(spi, offset);
+ regval &= ~SPI_CSR_CSAAT; /* Chip Select Not Active After Transfer */
+ spi_putreg(spi, regval, offset);
+ }
+
+ /* Do not set the LASTXFER-Bit at the last word of the next exchange,
+ * Flag is auto-resetting after the next LASTXFER condition.
+ * (see spi_exchange)
+ */
+
+ if ((features & HWFEAT_ESCAPE_LASTXFER) != 0)
+ {
+ spi->escape_lastxfer = true;
+ }
+ else
+ {
+ spi->escape_lastxfer = false;
+ }
+
+ return 0;
+}
+#endif
+
/****************************************************************************
* Name: spi_setmode
*
@@ -1112,7 +1306,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
uint32_t regval;
unsigned int offset;
- spivdbg("cs=%d mode=%d\n", spics->cs, mode);
+ spiinfo("cs=%d mode=%d\n", spics->cs, mode);
/* Has the mode changed? */
@@ -1155,7 +1349,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
}
spi_putreg(spi, regval, offset);
- spivdbg("csr[offset=%02x]=%08x\n", offset, regval);
+ spiinfo("csr[offset=%02x]=%08x\n", offset, regval);
/* Save the mode so that subsequent re-configurations will be faster */
@@ -1185,7 +1379,7 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
uint32_t regval;
unsigned int offset;
- spivdbg("cs=%d nbits=%d\n", spics->cs, nbits);
+ spiinfo("cs=%d nbits=%d\n", spics->cs, nbits);
DEBUGASSERT(spics && nbits > 7 && nbits < 17);
/* Has the number of bits changed? */
@@ -1200,9 +1394,11 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
regval |= SPI_CSR_BITS(nbits);
spi_putreg(spi, regval, offset);
- spivdbg("csr[offset=%02x]=%08x\n", offset, regval);
+ spiinfo("csr[offset=%02x]=%08x\n", offset, regval);
- /* Save the selection so the subsequence re-configurations will be faster */
+ /* Save the selection so the subsequence re-configurations will be
+ * faster.
+ */
spics->nbits = nbits;
}
@@ -1238,7 +1434,7 @@ static uint16_t spi_send(struct spi_dev_s *dev, uint16_t wd)
rxbyte = (uint8_t)0;
spi_exchange(dev, &txbyte, &rxbyte, 1);
- spivdbg("Sent %02x received %02x\n", txbyte, rxbyte);
+ spiinfo("Sent %02x received %02x\n", txbyte, rxbyte);
return (uint16_t)rxbyte;
}
@@ -1286,7 +1482,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
uint8_t *rxptr8;
uint8_t *txptr8;
- spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
+ spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
/* Set up PCS bits */
@@ -1358,16 +1554,37 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
data = 0xffff;
}
+ /* SPI_VARSELECT means, that the ChipSelect for each device is set within
+ * the transferred data (SAM_SPI_TDR) instead inside the mode register
+ * (SAM_SPI_MR).
+ * In addition, the LASTXFER flag is also set within the transferred data
+ * (SAM_SPI_TDR) instead inside the control register (SAM_SPI_CR).
+ */
+
+#ifdef CONFIG_SAMV7_SPI_VARSELECT
/* Set the PCS field in the value written to the TDR */
data |= pcs;
/* Do we need to set the LASTXFER bit in the TDR value too? */
-#ifdef CONFIG_SPI_VARSELECT
if (nwords == 1)
{
- data |= SPI_TDR_LASTXFER;
+ if (spi->escape_lastxfer == false)
+ {
+ /* According the data sheet (SAME70 Rev. 2016-01) this LASTXFER
+ * bit has no effect without also setting CSAAT.
+ * (see HWFEAT_FORCE_CS_ACTIVE_AFTER_TRANSFER)
+ */
+
+ data |= SPI_TDR_LASTXFER;
+ }
+ else
+ {
+ /* the escaping should only prevent ONE last-xfer */
+
+ spi->escape_lastxfer = false;
+ }
}
#endif
@@ -1381,6 +1598,32 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
spi_putreg(spi, data, SAM_SPI_TDR_OFFSET);
+#ifndef CONFIG_SAMV7_SPI_VARSELECT
+ /* To de-assert the chip select line at the end of the transfer, the
+ * Last Transfer (LASTXFER) bit in SPI_CR must be set after writing the
+ * last data to transmit into SPI_TDR.
+ */
+
+ if (nwords == 1)
+ {
+ if (spi->escape_lastxfer == false)
+ {
+ /* According the datasheet (SAME70 Rev. 2016-01) this LASTXFER
+ * bit has no effect without also setting CSAAT.
+ * (see HWFEAT_FORCE_CS_ACTIVE_AFTER_TRANSFER)
+ */
+
+ spi_putreg(spi, SPI_CR_LASTXFER, SAM_SPI_CR_OFFSET);
+ }
+ else
+ {
+ /* the escaping should only prevent ONE last-xfer */
+
+ spi->escape_lastxfer = false;
+ }
+ }
+#endif
+
/* Wait for the read data to be available in the RDR.
* TODO: Data transfer rates would be improved using the RX FIFO
* (and also DMA)
@@ -1432,7 +1675,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
return;
}
- spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
+ spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
spics = (struct sam_spics_s *)dev;
spi = spi_device(spics);
@@ -1549,7 +1792,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
ret = sam_dmarxsetup(spics->rxdma, regaddr, memaddr, nwords);
if (ret < 0)
{
- dmadbg("ERROR: sam_dmarxsetup failed: %d\n", ret);
+ dmaerr("ERROR: sam_dmarxsetup failed: %d\n", ret);
return;
}
@@ -1563,7 +1806,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
ret = sam_dmatxsetup(spics->txdma, regaddr, memaddr, nwords);
if (ret < 0)
{
- dmadbg("ERROR: sam_dmatxsetup failed: %d\n", ret);
+ dmaerr("ERROR: sam_dmatxsetup failed: %d\n", ret);
return;
}
@@ -1575,7 +1818,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
ret = sam_dmastart(spics->rxdma, spi_rxcallback, (void *)spics);
if (ret < 0)
{
- dmadbg("ERROR: RX sam_dmastart failed: %d\n", ret);
+ dmaerr("ERROR: RX sam_dmastart failed: %d\n", ret);
return;
}
@@ -1584,7 +1827,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
ret = sam_dmastart(spics->txdma, spi_txcallback, (void *)spics);
if (ret < 0)
{
- dmadbg("ERROR: RX sam_dmastart failed: %d\n", ret);
+ dmaerr("ERROR: RX sam_dmastart failed: %d\n", ret);
sam_dmastop(spics->rxdma);
return;
}
@@ -1606,7 +1849,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
(wdentry_t)spi_dmatimeout, 1, (uint32_t)spics);
if (ret != OK)
{
- spidbg("ERROR: wd_start failed: %d\n", ret);
+ spierr("ERROR: wd_start failed: %d\n", ret);
}
/* Wait for the DMA complete */
@@ -1657,7 +1900,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
if (spics->result)
{
- spidbg("ERROR: DMA failed with result: %d\n", spics->result);
+ spierr("ERROR: DMA failed with result: %d\n", spics->result);
}
}
#endif /* CONFIG_SAMV7_SPI_DMA */
@@ -1751,7 +1994,7 @@ FAR struct spi_dev_s *sam_spibus_initialize(int port)
/* The support SAM parts have only a single SPI port */
- spivdbg("port: %d csno: %d spino: %d\n", port, csno, spino);
+ spiinfo("port: %d csno: %d spino: %d\n", port, csno, spino);
DEBUGASSERT(csno >= 0 && csno <= SAM_SPI_NCS);
#if defined(CONFIG_SAMV7_SPI0_MASTER) && defined(CONFIG_SAMV7_SPI1_MASTER)
@@ -1770,7 +2013,7 @@ FAR struct spi_dev_s *sam_spibus_initialize(int port)
spics = (struct sam_spics_s *)zalloc(sizeof(struct sam_spics_s));
if (!spics)
{
- spidbg("ERROR: Failed to allocate a chip select structure\n");
+ spierr("ERROR: Failed to allocate a chip select structure\n");
return NULL;
}
@@ -1790,7 +2033,7 @@ FAR struct spi_dev_s *sam_spibus_initialize(int port)
spics->rxdma = sam_dmachannel(0, 0);
if (!spics->rxdma)
{
- spidbg("ERROR: Failed to allocate the RX DMA channel\n");
+ spierr("ERROR: Failed to allocate the RX DMA channel\n");
spics->candma = false;
}
}
@@ -1800,7 +2043,7 @@ FAR struct spi_dev_s *sam_spibus_initialize(int port)
spics->txdma = sam_dmachannel(0, 0);
if (!spics->txdma)
{
- spidbg("ERROR: Failed to allocate the TX DMA channel\n");
+ spierr("ERROR: Failed to allocate the TX DMA channel\n");
sam_dmafree(spics->rxdma);
spics->rxdma = NULL;
spics->candma = false;
@@ -1881,15 +2124,22 @@ FAR struct spi_dev_s *sam_spibus_initialize(int port)
/* Configure the SPI mode register */
+ regval = SPI_MR_MSTR | SPI_MR_MODFDIS;
+
#if defined(CONFIG_SAMV7_SPI_CS_DECODING)
/* Enable Peripheral Chip Select Decoding? */
- spi_putreg(spi, SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PCSDEC,
- SAM_SPI_MR_OFFSET);
-#else
- spi_putreg(spi, SPI_MR_MSTR | SPI_MR_MODFDIS, SAM_SPI_MR_OFFSET);
+ regval |= SPI_MR_PCSDEC;
#endif
+# ifdef CONFIG_SAMV7_SPI_VARSELECT
+ /* Enable Variable Peripheral Selection? */
+
+ regval |= SPI_MR_PS;
+#endif
+
+ spi_putreg(spi, regval, SAM_SPI_MR_OFFSET);
+
/* And enable the SPI */
spi_putreg(spi, SPI_CR_SPIEN, SAM_SPI_CR_OFFSET);
@@ -1905,6 +2155,7 @@ FAR struct spi_dev_s *sam_spibus_initialize(int port)
*/
sem_init(&spi->spisem, 0, 1);
+ spi->escape_lastxfer = false;
spi->initialized = true;
#ifdef CONFIG_SAMV7_SPI_DMA
@@ -1934,7 +2185,7 @@ FAR struct spi_dev_s *sam_spibus_initialize(int port)
spi_putreg(spi, regval, offset);
spics->nbits = 8;
- spivdbg("csr[offset=%02x]=%08x\n", offset, regval);
+ spiinfo("csr[offset=%02x]=%08x\n", offset, regval);
return &spics->spidev;
}
diff --git a/arch/arm/src/samv7/sam_spi_slave.c b/arch/arm/src/samv7/sam_spi_slave.c
index a210541ce695f19126de993a8660928f42752629..d2856cd2e998e13a2ab9a6ef9465ab4224f62cf9 100644
--- a/arch/arm/src/samv7/sam_spi_slave.c
+++ b/arch/arm/src/samv7/sam_spi_slave.c
@@ -74,26 +74,8 @@
# define CONFIG_SAMV7_SPI_SLAVE_QSIZE 8
#endif
-/* Debug *******************************************************************/
-/* Check if SPI debug is enabled (non-standard.. no support in
- * include/debug.h
- */
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# undef CONFIG_DEBUG_SPI
-#endif
-
-#ifdef CONFIG_DEBUG_SPI
-# define spidbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define spivdbg lldbg
-# else
-# define spivdbg(x...)
-# endif
-#else
-# define spidbg(x...)
-# define spivdbg(x...)
+#ifndef CONFIG_DEBUG_SPI_INFO
+# undef CONFIG_SAMV7_SPI_REGDEBUG
#endif
/****************************************************************************
@@ -153,7 +135,7 @@ static uint32_t spi_getreg(struct sam_spidev_s *priv,
static void spi_putreg(struct sam_spidev_s *priv, uint32_t value,
unsigned int offset);
-#if defined(CONFIG_DEBUG_SPI) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_SPI_INFO
static void spi_dumpregs(struct sam_spidev_s *priv, const char *msg);
#else
# define spi_dumpregs(priv,msg)
@@ -270,7 +252,7 @@ static bool spi_checkreg(struct sam_spidev_s *priv, bool wr, uint32_t value,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", priv->ntimes);
+ spiinfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@@ -303,7 +285,7 @@ static uint32_t spi_getreg(struct sam_spidev_s *priv, unsigned int offset)
#ifdef CONFIG_SAMV7_SPI_REGDEBUG
if (spi_checkreg(priv, false, value, address))
{
- lldbg("%08x->%08x\n", address, value);
+ spiinfo("%08x->%08x\n", address, value);
}
#endif
@@ -326,7 +308,7 @@ static void spi_putreg(struct sam_spidev_s *priv, uint32_t value,
#ifdef CONFIG_SAMV7_SPI_REGDEBUG
if (spi_checkreg(priv, true, value, address))
{
- lldbg("%08x<-%08x\n", address, value);
+ spiinfo("%08x<-%08x\n", address, value);
}
#endif
@@ -348,20 +330,20 @@ static void spi_putreg(struct sam_spidev_s *priv, uint32_t value,
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_SPI) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_SPI_INFO
static void spi_dumpregs(struct sam_spidev_s *priv, const char *msg)
{
- spivdbg("%s:\n", msg);
- spivdbg(" MR:%08x SR:%08x IMR:%08x\n",
+ spiinfo("%s:\n", msg);
+ spiinfo(" MR:%08x SR:%08x IMR:%08x\n",
getreg32(priv->base + SAM_SPI_MR_OFFSET),
getreg32(priv->base + SAM_SPI_SR_OFFSET),
getreg32(priv->base + SAM_SPI_IMR_OFFSET));
- spivdbg(" CSR0:%08x CSR1:%08x CSR2:%08x CSR3:%08x\n",
+ spiinfo(" CSR0:%08x CSR1:%08x CSR2:%08x CSR3:%08x\n",
getreg32(priv->base + SAM_SPI_CSR0_OFFSET),
getreg32(priv->base + SAM_SPI_CSR1_OFFSET),
getreg32(priv->base + SAM_SPI_CSR2_OFFSET),
getreg32(priv->base + SAM_SPI_CSR3_OFFSET));
- spivdbg(" WPCR:%08x WPSR:%08x\n",
+ spiinfo(" WPCR:%08x WPSR:%08x\n",
getreg32(priv->base + SAM_SPI_WPCR_OFFSET),
getreg32(priv->base + SAM_SPI_WPSR_OFFSET));
}
@@ -457,14 +439,14 @@ static int spi_interrupt(struct sam_spidev_s *priv)
* bit.
*/
-#ifdef CONFIG_DEBUG_SPI
+#ifdef CONFIG_DEBUG_SPI_ERROR
/* Check the RX data overflow condition */
if ((pending & SPI_INT_OVRES) != 0)
{
/* If debug is enabled, report any overrun errors */
- spidbg("Error: Overrun (OVRES): %08x\n", pending);
+ spierr("ERROR: Overrun (OVRES): %08x\n", pending);
/* OVRES was cleared by the status read. */
}
@@ -524,14 +506,14 @@ static int spi_interrupt(struct sam_spidev_s *priv)
* Underrun Error Status Flag (UNDES) is set in the SPI_SR.
*/
-#ifdef CONFIG_DEBUG_SPI
+#ifdef CONFIG_DEBUG_SPI_ERROR
/* Check the TX data underflow condition */
if ((pending & SPI_INT_UNDES) != 0)
{
/* If debug is enabled, report any overrun errors */
- spidbg("Error: Underrun (UNDEX): %08x\n", pending);
+ spierr("ERROR: Underrun (UNDEX): %08x\n", pending);
/* UNDES was cleared by the status read. */
}
@@ -699,7 +681,7 @@ static void spi_setmode(struct sam_spidev_s *priv, enum spi_smode_e mode)
{
uint32_t regval;
- spivdbg("mode=%d\n", mode);
+ spiinfo("mode=%d\n", mode);
/* Has the mode changed? */
@@ -741,7 +723,7 @@ static void spi_setmode(struct sam_spidev_s *priv, enum spi_smode_e mode)
}
spi_putreg(priv, regval, SAM_SPI_CSR0_OFFSET);
- spivdbg("csr0=%08x\n", regval);
+ spiinfo("csr0=%08x\n", regval);
/* Save the mode so that subsequent re-configurations will be faster */
@@ -768,7 +750,7 @@ static void spi_setbits(struct sam_spidev_s *priv, int nbits)
{
uint32_t regval;
- spivdbg("nbits=%d\n", nbits);
+ spiinfo("nbits=%d\n", nbits);
DEBUGASSERT(priv && nbits > 7 && nbits < 17);
/* Has the number of bits changed? */
@@ -782,7 +764,7 @@ static void spi_setbits(struct sam_spidev_s *priv, int nbits)
regval |= SPI_CSR_BITS(nbits);
spi_putreg(priv, regval, SAM_SPI_CSR0_OFFSET);
- spivdbg("csr0=%08x\n", regval);
+ spiinfo("csr0=%08x\n", regval);
/* Save the selection so the subsequence re-configurations will be faster */
@@ -819,7 +801,7 @@ static void spi_bind(struct spi_sctrlr_s *sctrlr,
struct sam_spidev_s *priv = (struct sam_spidev_s *)sctrlr;
uint32_t regval;
- spivdbg("sdev=%p mode=%d nbits=%d\n", sdv, mode, nbits);
+ spiinfo("sdev=%p mode=%d nbits=%d\n", sdv, mode, nbits);
DEBUGASSERT(priv != NULL && priv->sdev == NULL && sdev != NULL);
@@ -891,7 +873,7 @@ static void spi_bind(struct spi_sctrlr_s *sctrlr,
*/
regval = (SPI_INT_RDRF | SPI_INT_NSSR);
-#ifdef CONFIG_DEBUG_SPI
+#ifdef CONFIG_DEBUG_SPI_ERROR
regval |= SPI_INT_OVRES;
#endif
@@ -921,7 +903,7 @@ static void spi_unbind(struct spi_sctrlr_s *sctrlr)
struct sam_spidev_s *priv = (struct sam_spidev_s *)sctrlr;
DEBUGASSERT(priv != NULL);
- spivdbg("Unbinding %p\n", priv->sdev);
+ spiinfo("Unbinding %p\n", priv->sdev);
DEBUGASSERT(priv->sdev != NULL);
@@ -978,7 +960,7 @@ static int spi_enqueue(struct spi_sctrlr_s *sctrlr, uint16_t data)
int next;
int ret;
- spivdbg("data=%04x\n", data);
+ spiinfo("data=%04x\n", data);
DEBUGASSERT(priv != NULL && priv->sdev != NULL);
/* Get exclusive access to the SPI device */
@@ -1095,7 +1077,7 @@ static void spi_qflush(struct spi_sctrlr_s *sctrlr)
struct sam_spidev_s *priv = (struct sam_spidev_s *)sctrlr;
irqstate_t flags;
- spivdbg("data=%04x\n", data);
+ spiinfo("data=%04x\n", data);
DEBUGASSERT(priv != NULL && priv->sdev != NULL);
@@ -1140,7 +1122,7 @@ struct spi_sctrlr_s *sam_spi_slave_initialize(int port)
/* The support SAM parts have only a single SPI port */
- spivdbg("port: %d spino: %d\n", port, spino);
+ spiinfo("port: %d spino: %d\n", port, spino);
#if defined(CONFIG_SAMV7_SPI0_SLAVE) && defined(CONFIG_SAMV7_SPI1_SLAVE)
DEBUGASSERT(spino >= 0 && spino <= 1);
@@ -1287,7 +1269,7 @@ struct spi_sctrlr_s *sam_spi_slave_initialize(int port)
spi_putreg(priv, regval, SAM_SPI_CSR0_OFFSET);
priv->nbits = 8;
- spivdbg("csr[offset=%02x]=%08x\n", offset, regval);
+ spiinfo("csr[offset=%02x]=%08x\n", offset, regval);
return &priv->sctrlr;
}
diff --git a/arch/arm/src/samv7/sam_ssc.c b/arch/arm/src/samv7/sam_ssc.c
index 107d120de7a35f462f369aacc0031033b2ad31e4..11ae76c9f07bbaa678d542874ce75fa704c87a41 100644
--- a/arch/arm/src/samv7/sam_ssc.c
+++ b/arch/arm/src/samv7/sam_ssc.c
@@ -91,6 +91,10 @@
# define CONFIG_SAMV7_SSC_MAXINFLIGHT 16
#endif
+#ifndef CONFIG_DEBUG_I2S_INFO
+# undef CONFIG_SAMV7_SSC_REGDEBUG
+#endif
+
/* Assume no RX/TX support until we learn better */
#undef SSC_HAVE_RX
@@ -366,16 +370,9 @@
#define DMA_TIMEOUT_TICKS MSEC2TICK(DMA_TIMEOUT_MS)
/* Debug *******************************************************************/
-/* Check if SSC debug is enabled (non-standard.. no support in
- * include/debug.h
- */
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# undef CONFIG_DEBUG_I2S
-#endif
+/* Check if SSC debug is enabled */
-#ifndef CONFIG_DEBUG_I2S
+#ifndef CONFIG_DEBUG_I2S_INFO
# undef CONFIG_SAMV7_SSC_DMADEBUG
# undef CONFIG_SAMV7_SSC_REGDEBUG
# undef CONFIG_SAMV7_SSC_QDEBUG
@@ -386,22 +383,6 @@
# undef CONFIG_SAMV7_SSC_DMADEBUG
#endif
-#ifdef CONFIG_DEBUG_I2S
-# define i2sdbg dbg
-# define i2slldbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define i2svdbg dbg
-# define i2sllvdbg lldbg
-# else
-# define i2svdbg(x...)
-# endif
-#else
-# define i2sdbg(x...)
-# define i2slldbg(x...)
-# define i2svdbg(x...)
-# define i2sllvdbg(x...)
-#endif
-
#define DMA_INITIAL 0
#define DMA_AFTER_SETUP 1
#define DMA_AFTER_START 2
@@ -449,7 +430,7 @@ struct sam_ssc_s
uintptr_t base; /* SSC controller register base address */
sem_t exclsem; /* Assures mutually exclusive acess to SSC */
uint8_t datalen; /* Data width (8, 16, or 32) */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
uint8_t align; /* Log2 of data width (0, 1, or 3) */
#endif
uint8_t pid; /* Peripheral ID */
@@ -512,7 +493,7 @@ static inline void ssc_putreg(struct sam_ssc_s *priv, unsigned int offset,
static inline uintptr_t ssc_regaddr(struct sam_ssc_s *priv,
unsigned int offset);
-#if defined(CONFIG_DEBUG_I2S) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_I2S_INFO
static void scc_dump_regs(struct sam_ssc_s *priv, const char *msg);
#else
# define scc_dump_regs(s,m)
@@ -697,7 +678,7 @@ static bool ssc_checkreg(struct sam_ssc_s *priv, bool wr, uint32_t regval,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", priv->count);
+ i2sinfo("...[Repeats %d times]...\n", priv->count);
}
/* Save information about the new access */
@@ -731,7 +712,7 @@ static inline uint32_t ssc_getreg(struct sam_ssc_s *priv,
#ifdef CONFIG_SAMV7_SSC_REGDEBUG
if (ssc_checkreg(priv, false, regval, regaddr))
{
- lldbg("%08x->%08x\n", regaddr, regval);
+ i2sinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@@ -754,7 +735,7 @@ static inline void ssc_putreg(struct sam_ssc_s *priv, unsigned int offset,
#ifdef CONFIG_SAMV7_SSC_REGDEBUG
if (ssc_checkreg(priv, true, regval, regaddr))
{
- lldbg("%08x<-%08x\n", regaddr, regval);
+ i2sinfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@@ -789,21 +770,21 @@ static inline uintptr_t ssc_regaddr(struct sam_ssc_s *priv, unsigned int offset)
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_I2S) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_I2S_INFO
static void scc_dump_regs(struct sam_ssc_s *priv, const char *msg)
{
- i2svdbg("SSC%d: %s\n", priv->sscno, msg);
- i2svdbg(" CMR:%08x RCMR:%08x RFMR:%08x TCMR:%08x\n",
+ i2sinfo("SSC%d: %s\n", priv->sscno, msg);
+ i2sinfo(" CMR:%08x RCMR:%08x RFMR:%08x TCMR:%08x\n",
getreg32(priv->base + SAM_SSC_CMR_OFFSET),
getreg32(priv->base + SAM_SSC_RCMR_OFFSET),
getreg32(priv->base + SAM_SSC_RFMR_OFFSET),
getreg32(priv->base + SAM_SSC_TCMR_OFFSET));
- i2svdbg(" TFMR:%08x RC0R:%08x RC1R:%08x SR:%08x\n",
+ i2sinfo(" TFMR:%08x RC0R:%08x RC1R:%08x SR:%08x\n",
getreg32(priv->base + SAM_SSC_TFMR_OFFSET),
getreg32(priv->base + SAM_SSC_RC0R_OFFSET),
getreg32(priv->base + SAM_SSC_RC1R_OFFSET),
getreg32(priv->base + SAM_SSC_SR_OFFSET));
- i2svdbg(" IMR:%08x WPMR:%08x WPSR:%08x\n",
+ i2sinfo(" IMR:%08x WPMR:%08x WPSR:%08x\n",
getreg32(priv->base + SAM_SSC_IMR_OFFSET),
getreg32(priv->base + SAM_SSC_WPMR_OFFSET),
getreg32(priv->base + SAM_SSC_WPSR_OFFSET));
@@ -840,12 +821,12 @@ static void ssc_dump_queue(sq_queue_t *queue)
if (!apb)
{
- i2sllvdbg(" %p: No buffer\n", bfcontainer);
+ i2sinfo(" %p: No buffer\n", bfcontainer);
}
else
{
- i2sllvdbg(" %p: buffer=%p nmaxbytes=%d nbytes=%d\n",
- bfcontainer, apb, apb->nmaxbytes, apb->nbytes);
+ i2sinfo(" %p: buffer=%p nmaxbytes=%d nbytes=%d\n",
+ bfcontainer, apb, apb->nmaxbytes, apb->nbytes);
}
}
}
@@ -855,12 +836,12 @@ static void ssc_dump_queues(struct sam_transport_s *xpt, const char *msg)
irqstate_t flags;
flags = enter_critical_section();
- i2sllvdbg("%s\n", msg);
- i2sllvdbg(" Pending:\n");
+ i2sinfo("%s\n", msg);
+ i2sinfo(" Pending:\n");
ssc_dump_queue(&xpt->pend);
- i2sllvdbg(" Active:\n");
+ i2sinfo(" Active:\n");
ssc_dump_queue(&xpt->act);
- i2sllvdbg(" Done:\n");
+ i2sinfo(" Done:\n");
ssc_dump_queue(&xpt->done);
leave_critical_section(flags);
}
@@ -1083,7 +1064,7 @@ static void ssc_dma_sampleinit(struct sam_ssc_s *priv,
#if defined(CONFIG_SAMV7_SSC_DMADEBUG) && defined(SSC_HAVE_RX)
static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result)
{
- lldbg("result: %d\n", result);
+ i2llsinfo("result: %d\n", result);
/* Sample the final registers */
@@ -1148,7 +1129,7 @@ static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result)
#if defined(CONFIG_SAMV7_SSC_DMADEBUG) && defined(SSC_HAVE_TX)
static void ssc_txdma_sampledone(struct sam_ssc_s *priv, int result)
{
- lldbg("result: %d\n", result);
+ i2sinfo("result: %d\n", result);
/* Sample the final registers */
@@ -1371,7 +1352,7 @@ static int ssc_rxdma_setup(struct sam_ssc_s *priv)
if (ret < 0)
{
- i2slldbg("ERROR: wd_start failed: %d\n", errno);
+ i2serr("ERROR: wd_start failed: %d\n", errno);
}
}
@@ -1420,7 +1401,7 @@ static void ssc_rx_worker(void *arg)
* So we have to start the next DMA here.
*/
- i2svdbg("rx.act.head=%p rx.done.head=%p\n",
+ i2sinfo("rx.act.head=%p rx.done.head=%p\n",
priv->rx.act.head, priv->rx.done.head);
ssc_dump_rxqueues(priv, "RX worker start");
@@ -1559,7 +1540,7 @@ static void ssc_rx_schedule(struct sam_ssc_s *priv, int result)
ret = work_queue(HPWORK, &priv->rx.work, ssc_rx_worker, priv, 0);
if (ret != 0)
{
- i2slldbg("ERROR: Failed to queue RX work: %d\n", ret);
+ i2serr("ERROR: Failed to queue RX work: %d\n", ret);
}
}
}
@@ -1788,7 +1769,7 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv)
if (ret < 0)
{
- i2slldbg("ERROR: wd_start failed: %d\n", errno);
+ i2serr("ERROR: wd_start failed: %d\n", errno);
}
}
@@ -1836,7 +1817,7 @@ static void ssc_tx_worker(void *arg)
* So we have to start the next DMA here.
*/
- i2svdbg("tx.act.head=%p tx.done.head=%p\n",
+ i2sinfo("tx.act.head=%p tx.done.head=%p\n",
priv->tx.act.head, priv->tx.done.head);
ssc_dump_txqueues(priv, "TX worker start");
@@ -1963,7 +1944,7 @@ static void ssc_tx_schedule(struct sam_ssc_s *priv, int result)
ret = work_queue(HPWORK, &priv->tx.work, ssc_tx_worker, priv, 0);
if (ret != 0)
{
- i2slldbg("ERROR: Failed to queue TX work: %d\n", ret);
+ i2serr("ERROR: Failed to queue TX work: %d\n", ret);
}
}
}
@@ -2036,25 +2017,25 @@ static int ssc_checkwidth(struct sam_ssc_s *priv, int bits)
switch (bits)
{
case 8:
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
priv->align = 0;
#endif
break;
case 16:
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
priv->align = 1;
#endif
break;
case 32:
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
priv->align = 3;
#endif
break;
default:
- i2sdbg("ERROR: Unsupported or invalid data width: %d\n", bits);
+ i2serr("ERROR: Unsupported or invalid data width: %d\n", bits);
return (bits < 2 || bits > 32) ? -EINVAL : -ENOSYS;
}
@@ -2132,7 +2113,7 @@ static uint32_t ssc_rxdatawidth(struct i2s_dev_s *dev, int bits)
ret = ssc_checkwidth(priv, bits);
if (ret < 0)
{
- i2sdbg("ERROR: ssc_checkwidth failed: %d\n", ret);
+ i2serr("ERROR: ssc_checkwidth failed: %d\n", ret);
return 0;
}
@@ -2141,7 +2122,7 @@ static uint32_t ssc_rxdatawidth(struct i2s_dev_s *dev, int bits)
ret = ssc_dma_flags(priv, &dmaflags);
if (ret < 0)
{
- i2sdbg("ERROR: ssc_dma_flags failed: %d\n", ret);
+ i2serr("ERROR: ssc_dma_flags failed: %d\n", ret);
return 0;
}
@@ -2211,7 +2192,7 @@ static int ssc_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb,
#endif
DEBUGASSERT(priv && apb && ((uintptr_t)apb->samp & priv->align) == 0);
- i2svdbg("apb=%p nmaxbytes=%d arg=%p timeout=%d\n",
+ i2sinfo("apb=%p nmaxbytes=%d arg=%p timeout=%d\n",
apb, apb->nmaxbytes, arg, timeout);
ssc_init_buffer(apb->samp, apb->nmaxbytes);
@@ -2230,7 +2211,7 @@ static int ssc_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb,
if (!priv->rxenab)
{
- i2sdbg("ERROR: SSC%d has no receiver\n", priv->sscno);
+ i2serr("ERROR: SSC%d has no receiver\n", priv->sscno);
ret = -EAGAIN;
goto errout_with_exclsem;
}
@@ -2269,7 +2250,7 @@ errout_with_exclsem:
return ret;
#else
- i2sdbg("ERROR: SSC%d has no receiver\n", priv->sscno);
+ i2serr("ERROR: SSC%d has no receiver\n", priv->sscno);
UNUSED(priv);
return -ENOSYS;
#endif
@@ -2343,7 +2324,7 @@ static uint32_t ssc_txdatawidth(struct i2s_dev_s *dev, int bits)
ret = ssc_checkwidth(priv, bits);
if (ret < 0)
{
- i2sdbg("ERROR: ssc_checkwidth failed: %d\n", ret);
+ i2serr("ERROR: ssc_checkwidth failed: %d\n", ret);
return 0;
}
@@ -2352,7 +2333,7 @@ static uint32_t ssc_txdatawidth(struct i2s_dev_s *dev, int bits)
ret = ssc_dma_flags(priv, &dmaflags);
if (ret < 0)
{
- i2sdbg("ERROR: ssc_dma_flags failed: %d\n", ret);
+ i2serr("ERROR: ssc_dma_flags failed: %d\n", ret);
return 0;
}
@@ -2426,7 +2407,7 @@ static int ssc_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb,
*/
DEBUGASSERT(priv && apb);
- i2svdbg("apb=%p nbytes=%d arg=%p timeout=%d\n",
+ i2sinfo("apb=%p nbytes=%d arg=%p timeout=%d\n",
apb, apb->nbytes - apb->curbyte, arg, timeout);
ssc_dump_buffer("Sending", &apb->samp[apb->curbyte],
@@ -2447,7 +2428,7 @@ static int ssc_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb,
if (!priv->txenab)
{
- i2sdbg("ERROR: SSC%d has no transmitter\n", priv->sscno);
+ i2serr("ERROR: SSC%d has no transmitter\n", priv->sscno);
ret = -EAGAIN;
goto errout_with_exclsem;
}
@@ -2486,7 +2467,7 @@ errout_with_exclsem:
return ret;
#else
- i2sdbg("ERROR: SSC%d has no transmitter\n", priv->sscno);
+ i2serr("ERROR: SSC%d has no transmitter\n", priv->sscno);
UNUSED(priv);
return -ENOSYS;
#endif
@@ -2540,7 +2521,7 @@ static int ssc_rx_configure(struct sam_ssc_s *priv)
case SSC_CLKSRC_NONE: /* No clock */
default:
- i2sdbg("ERROR: No receiver clock\n");
+ i2serr("ERROR: No receiver clock\n");
return -EINVAL;
}
@@ -2561,7 +2542,7 @@ static int ssc_rx_configure(struct sam_ssc_s *priv)
break;
default:
- i2sdbg("ERROR: Invalid clock output selection\n");
+ i2serr("ERROR: Invalid clock output selection\n");
return -EINVAL;
}
@@ -2665,7 +2646,7 @@ static int ssc_tx_configure(struct sam_ssc_s *priv)
case SSC_CLKSRC_NONE: /* No clock */
default:
- i2sdbg("ERROR: No transmitter clock\n");
+ i2serr("ERROR: No transmitter clock\n");
return -EINVAL;
}
@@ -2686,7 +2667,7 @@ static int ssc_tx_configure(struct sam_ssc_s *priv)
break;
default:
- i2sdbg("ERROR: Invalid clock output selection\n");
+ i2serr("ERROR: Invalid clock output selection\n");
return -EINVAL;
}
@@ -2906,7 +2887,7 @@ static void ssc_clocking(struct sam_ssc_s *priv)
sam_enableperiph1(priv->pid);
- i2svdbg("PCSR1=%08x PCR=%08x CMR=%08x\n",
+ i2sinfo("PCSR1=%08x PCR=%08x CMR=%08x\n",
getreg32(SAM_PMC_PCSR1), regval,
ssc_getreg(priv, SAM_SSC_CMR_OFFSET));
}
@@ -2945,7 +2926,7 @@ static int ssc_dma_flags(struct sam_ssc_s *priv, uint32_t *dmaflags)
break;
default:
- i2sdbg("ERROR: Unsupported data width: %d\n", priv->datalen);
+ i2serr("ERROR: Unsupported data width: %d\n", priv->datalen);
return -ENOSYS;
}
@@ -2978,7 +2959,7 @@ static int ssc_dma_allocate(struct sam_ssc_s *priv)
ret = ssc_dma_flags(priv, &dmaflags);
if (ret < 0)
{
- i2sdbg("ERROR: ssc_dma_flags failed: %d\n", ret);
+ i2serr("ERROR: ssc_dma_flags failed: %d\n", ret);
return ret;
}
@@ -2992,7 +2973,7 @@ static int ssc_dma_allocate(struct sam_ssc_s *priv)
priv->rx.dma = sam_dmachannel(0, dmaflags);
if (!priv->rx.dma)
{
- i2sdbg("ERROR: Failed to allocate the RX DMA channel\n");
+ i2serr("ERROR: Failed to allocate the RX DMA channel\n");
goto errout;
}
@@ -3001,7 +2982,7 @@ static int ssc_dma_allocate(struct sam_ssc_s *priv)
priv->rx.dog = wd_create();
if (!priv->rx.dog)
{
- i2sdbg("ERROR: Failed to create the RX DMA watchdog\n");
+ i2serr("ERROR: Failed to create the RX DMA watchdog\n");
goto errout;
}
}
@@ -3015,7 +2996,7 @@ static int ssc_dma_allocate(struct sam_ssc_s *priv)
priv->tx.dma = sam_dmachannel(0, dmaflags);
if (!priv->tx.dma)
{
- i2sdbg("ERROR: Failed to allocate the TX DMA channel\n");
+ i2serr("ERROR: Failed to allocate the TX DMA channel\n");
goto errout;
}
@@ -3024,7 +3005,7 @@ static int ssc_dma_allocate(struct sam_ssc_s *priv)
priv->tx.dog = wd_create();
if (!priv->tx.dog)
{
- i2sdbg("ERROR: Failed to create the TX DMA watchdog\n");
+ i2serr("ERROR: Failed to create the TX DMA watchdog\n");
goto errout;
}
}
@@ -3231,7 +3212,7 @@ static void ssc0_configure(struct sam_ssc_s *priv)
priv->base = SAM_SSC0_BASE;
priv->datalen = CONFIG_SAMV7_SSC0_DATALEN;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
priv->align = SAMV7_SSC0_DATAMASK;
#endif
priv->pid = SAM_PID_SSC0;
@@ -3372,7 +3353,7 @@ static void ssc1_configure(struct sam_ssc_s *priv)
priv->base = SAM_SSC1_BASE;
priv->datalen = CONFIG_SAMV7_SSC1_DATALEN;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
priv->align = SAMV7_SSC1_DATAMASK;
#endif
priv->pid = SAM_PID_SSC1;
@@ -3405,7 +3386,7 @@ struct i2s_dev_s *sam_ssc_initialize(int port)
/* The support SAM parts have only a single SSC port */
- i2svdbg("port: %d\n", port);
+ i2sinfo("port: %d\n", port);
/* Allocate a new state structure for this chip select. NOTE that there
* is no protection if the same chip select is used in two different
@@ -3415,7 +3396,7 @@ struct i2s_dev_s *sam_ssc_initialize(int port)
priv = (struct sam_ssc_s *)zalloc(sizeof(struct sam_ssc_s));
if (!priv)
{
- i2sdbg("ERROR: Failed to allocate a chip select structure\n");
+ i2serr("ERROR: Failed to allocate a chip select structure\n");
return NULL;
}
@@ -3449,7 +3430,7 @@ struct i2s_dev_s *sam_ssc_initialize(int port)
else
#endif /* CONFIG_SAMV7_SSC1 */
{
- i2sdbg("ERROR: Unsupported I2S port: %d\n", port);
+ i2serr("ERROR: Unsupported I2S port: %d\n", port);
goto errout_with_alloc;
}
@@ -3470,7 +3451,7 @@ struct i2s_dev_s *sam_ssc_initialize(int port)
ret = ssc_rx_configure(priv);
if (ret < 0)
{
- i2sdbg("ERROR: Failed to configure the receiver: %d\n", ret);
+ i2serr("ERROR: Failed to configure the receiver: %d\n", ret);
goto errout_with_clocking;
}
@@ -3479,7 +3460,7 @@ struct i2s_dev_s *sam_ssc_initialize(int port)
ret = ssc_tx_configure(priv);
if (ret < 0)
{
- i2sdbg("ERROR: Failed to configure the transmitter: %d\n", ret);
+ i2serr("ERROR: Failed to configure the transmitter: %d\n", ret);
goto errout_with_clocking;
}
diff --git a/arch/arm/src/samv7/sam_tc.c b/arch/arm/src/samv7/sam_tc.c
index 03569857765ab3d2f74d711f04e53c02384a0940..691366af8f8a9224024efe6155daa3f3e02c5307 100644
--- a/arch/arm/src/samv7/sam_tc.c
+++ b/arch/arm/src/samv7/sam_tc.c
@@ -77,6 +77,10 @@
* Pre-processor Definitions
****************************************************************************/
+#ifndef CONFIG_DEBUG_TIMER_INFO
+# undef CONFIG_SAMV7_TC_REGDEBUG
+#endif
+
/****************************************************************************
* Private Types
****************************************************************************/
@@ -643,19 +647,19 @@ static void sam_regdump(struct sam_chan_s *chan, const char *msg)
uintptr_t base;
base = tc->base;
- lldbg("TC%d [%08x]: %s\n", tc->tc, (int)base, msg);
- lldbg(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n",
- getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET),
- getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET));
+ tmrinfo("TC%d [%08x]: %s\n", tc->tc, (int)base, msg);
+ tmrinfo(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n",
+ getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET),
+ getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET));
base = chan->base;
- lldbg("TC%d Channel %d [%08x]: %s\n", tc->tc, chan->chan, (int)base, msg);
- lldbg(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n",
- getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET),
- getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET));
- lldbg(" RA: %08x RB: %08x RC: %08x IMR: %08x\n",
- getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET),
- getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_IMR_OFFSET));
+ tmrinfo("TC%d Channel %d [%08x]: %s\n", tc->tc, chan->chan, (int)base, msg);
+ tmrinfo(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n",
+ getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET),
+ getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET));
+ tmrinfo(" RA: %08x RB: %08x RC: %08x IMR: %08x\n",
+ getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET),
+ getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_IMR_OFFSET));
}
#endif
@@ -698,7 +702,7 @@ static bool sam_checkreg(struct sam_tc_s *tc, bool wr, uint32_t regaddr,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", tc->ntimes);
+ tmrinfo("...[Repeats %d times]...\n", tc->ntimes);
}
/* Save information about the new access */
@@ -733,7 +737,7 @@ static inline uint32_t sam_tc_getreg(struct sam_chan_s *chan,
#ifdef CONFIG_SAMV7_TC_REGDEBUG
if (sam_checkreg(tc, false, regaddr, regval))
{
- lldbg("%08x->%08x\n", regaddr, regval);
+ tmrinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@@ -757,7 +761,7 @@ static inline void sam_tc_putreg(struct sam_chan_s *chan, uint32_t regval,
#ifdef CONFIG_SAMV7_TC_REGDEBUG
if (sam_checkreg(tc, true, regaddr, regval))
{
- lldbg("%08x<-%08x\n", regaddr, regval);
+ tmrinfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@@ -781,7 +785,7 @@ static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan,
#ifdef CONFIG_SAMV7_TC_REGDEBUG
if (sam_checkreg(chan->tc, false, regaddr, regval))
{
- lldbg("%08x->%08x\n", regaddr, regval);
+ tmrinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@@ -804,7 +808,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset,
#ifdef CONFIG_SAMV7_TC_REGDEBUG
if (sam_checkreg(chan->tc, true, regaddr, regval))
{
- lldbg("%08x<-%08x\n", regaddr, regval);
+ tmrinfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@@ -841,8 +845,8 @@ static int sam_tc_interrupt(struct sam_tc_s *tc, struct sam_chan_s *chan)
imr = sam_chan_getreg(chan, SAM_TC_IMR_OFFSET);
pending = sr & imr;
- tcllvdbg("TC%d Channel %d: pending=%08lx\n",
- tc->tc, chan->chan, (unsigned long)pending);
+ tmrinfo("TC%d Channel %d: pending=%08lx\n",
+ tc->tc, chan->chan, (unsigned long)pending);
/* Are there any pending interrupts for this channel? */
@@ -1046,7 +1050,7 @@ static int sam_tc_mcksrc(uint32_t frequency, uint32_t *tcclks,
uint32_t fnext;
int ndx = 0;
- tcvdbg("frequency=%d\n", frequency);
+ tmrinfo("frequency=%d\n", frequency);
/* Satisfy lower bound. That is, the value of the divider such that:
*
@@ -1066,7 +1070,7 @@ static int sam_tc_mcksrc(uint32_t frequency, uint32_t *tcclks,
{
/* If no divisor can be found, return -ERANGE */
- tcdbg("Lower bound search failed\n");
+ tmrerr("ERROR: Lower bound search failed\n");
return -ERANGE;
}
@@ -1169,7 +1173,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel)
{
/* Timer/counter is not invalid or not enabled */
- tcdbg("ERROR: Bad channel number: %d\n", channel);
+ tmrerr("ERROR: Bad channel number: %d\n", channel);
return NULL;
}
@@ -1225,7 +1229,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel)
{
/* Yes.. return a failure */
- tcdbg("Channel %d is in-use\n", channel);
+ tmrerr("ERROR: Channel %d is in-use\n", channel);
sam_givesem(tc);
return NULL;
}
@@ -1318,7 +1322,7 @@ TC_HANDLE sam_tc_allocate(int channel, int mode)
* access to the requested channel.
*/
- tcvdbg("channel=%d mode=%08x\n", channel, mode);
+ tmrinfo("channel=%d mode=%08x\n", channel, mode);
chan = sam_tc_initialize(channel);
if (chan)
@@ -1344,7 +1348,7 @@ TC_HANDLE sam_tc_allocate(int channel, int mode)
/* Return an opaque reference to the channel */
- tcvdbg("Returning %p\n", chan);
+ tmrinfo("Returning %p\n", chan);
return (TC_HANDLE)chan;
}
@@ -1366,7 +1370,7 @@ void sam_tc_free(TC_HANDLE handle)
{
struct sam_chan_s *chan = (struct sam_chan_s *)handle;
- tcvdbg("Freeing %p channel=%d inuse=%d\n", chan, chan->chan, chan->inuse);
+ tmrinfo("Freeing %p channel=%d inuse=%d\n", chan, chan->chan, chan->inuse);
DEBUGASSERT(chan && chan->inuse);
/* Make sure that interrupts are detached and disabled and that the channel
@@ -1399,7 +1403,7 @@ void sam_tc_start(TC_HANDLE handle)
{
struct sam_chan_s *chan = (struct sam_chan_s *)handle;
- tcvdbg("Starting channel %d inuse=%d\n", chan->chan, chan->inuse);
+ tmrinfo("Starting channel %d inuse=%d\n", chan->chan, chan->inuse);
DEBUGASSERT(chan && chan->inuse);
/* Read the SR to clear any pending interrupts on this channel */
@@ -1431,7 +1435,7 @@ void sam_tc_stop(TC_HANDLE handle)
{
struct sam_chan_s *chan = (struct sam_chan_s *)handle;
- tcvdbg("Stopping channel %d inuse=%d\n", chan->chan, chan->inuse);
+ tmrinfo("Stopping channel %d inuse=%d\n", chan->chan, chan->inuse);
DEBUGASSERT(chan && chan->inuse);
sam_chan_putreg(chan, SAM_TC_CCR_OFFSET, TC_CCR_CLKDIS);
@@ -1538,8 +1542,8 @@ void sam_tc_setregister(TC_HANDLE handle, int regid, uint32_t regval)
DEBUGASSERT(chan && regid < TC_NREGISTERS);
- tcvdbg("Channel %d: Set register RC%d to %08lx\n",
- chan->chan, regid, (unsigned long)regval);
+ tmrinfo("Channel %d: Set register RC%d to %08lx\n",
+ chan->chan, regid, (unsigned long)regval);
sam_chan_putreg(chan, g_regoffset[regid], regval);
sam_regdump(chan, "Set register");
@@ -1717,7 +1721,7 @@ int sam_tc_clockselect(uint32_t frequency, uint32_t *tcclks,
if (actual)
{
- tcvdbg("return actual=%lu\n", (unsigned long)fselect);
+ tmrinfo("return actual=%lu\n", (unsigned long)fselect);
*actual = pck6_actual;
}
@@ -1725,7 +1729,7 @@ int sam_tc_clockselect(uint32_t frequency, uint32_t *tcclks,
if (tcclks)
{
- tcvdbg("return tcclks=%08lx\n", (unsigned long)TC_CMR_TCCLKS_PCK6);
+ tmrinfo("return tcclks=%08lx\n", (unsigned long)TC_CMR_TCCLKS_PCK6);
*tcclks = TC_CMR_TCCLKS_PCK6;
}
@@ -1739,7 +1743,7 @@ int sam_tc_clockselect(uint32_t frequency, uint32_t *tcclks,
if (actual)
{
- tcvdbg("return actual=%lu\n", (unsigned long)mck_actual);
+ tmrinfo("return actual=%lu\n", (unsigned long)mck_actual);
*actual = mck_actual;
}
@@ -1747,7 +1751,7 @@ int sam_tc_clockselect(uint32_t frequency, uint32_t *tcclks,
if (tcclks)
{
- tcvdbg("return tcclks=%08lx\n", (unsigned long)mck_tcclks);
+ tmrinfo("return tcclks=%08lx\n", (unsigned long)mck_tcclks);
*tcclks = mck_tcclks;
}
diff --git a/arch/arm/src/samv7/sam_tc.h b/arch/arm/src/samv7/sam_tc.h
index 5dda45ece993f7e0f17d4b7ea323ee55b701c5b3..d62ac212520d39e890db7bf6b5d3f1fcbae31ff2 100644
--- a/arch/arm/src/samv7/sam_tc.h
+++ b/arch/arm/src/samv7/sam_tc.h
@@ -75,8 +75,7 @@
/* Timer debug is enabled if any timer client is enabled */
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_ANALOG
+#ifndef CONFIG_DEBUG_TIMER_INFO
# undef CONFIG_SAMV7_TC_REGDEBUG
#endif
@@ -84,20 +83,6 @@
# define CONFIG_SAMV7_TC_DEBUG 1
#endif
-/* Timer/counter debug output */
-
-#ifdef CONFIG_SAMV7_TC_DEBUG
-# define tcdbg dbg
-# define tcvdbg vdbg
-# define tclldbg lldbg
-# define tcllvdbg llvdbg
-#else
-# define tcdbg(x...)
-# define tcvdbg(x...)
-# define tclldbg(x...)
-# define tcllvdbg(x...)
-#endif
-
/****************************************************************************
* Public Types
****************************************************************************/
diff --git a/arch/arm/src/samv7/sam_tickless.c b/arch/arm/src/samv7/sam_tickless.c
index 3d1a7ad95ac40d32986c5593dfb1d1c37715ab9b..95f4b8754f30a92986629ae3e2d4b911dbd529e3 100644
--- a/arch/arm/src/samv7/sam_tickless.c
+++ b/arch/arm/src/samv7/sam_tickless.c
@@ -221,7 +221,7 @@ static struct sam_tickless_s g_tickless;
static void sam_oneshot_handler(void *arg)
{
- tcllvdbg("Expired...\n");
+ tmrinfo("Expired...\n");
sched_timer_expiration();
}
@@ -265,7 +265,7 @@ void up_timer_initialize(void)
CONFIG_USEC_PER_TICK);
if (ret < 0)
{
- tclldbg("ERROR: sam_oneshot_initialize failed\n");
+ tmrerr("ERROR: sam_oneshot_initialize failed\n");
PANIC();
}
@@ -278,7 +278,7 @@ void up_timer_initialize(void)
CONFIG_USEC_PER_TICK);
if (ret < 0)
{
- tclldbg("ERROR: sam_freerun_initialize failed\n");
+ tmrerr("ERROR: sam_freerun_initialize failed\n");
PANIC();
}
diff --git a/arch/arm/src/samv7/sam_trng.c b/arch/arm/src/samv7/sam_trng.c
index 3a76b924e1fac122c4a213f013aabdaaabe02729..7dc29a77d83626b591250ddb5f8f2ceba56eb710 100644
--- a/arch/arm/src/samv7/sam_trng.c
+++ b/arch/arm/src/samv7/sam_trng.c
@@ -244,7 +244,7 @@ static ssize_t sam_read(struct file *filep, char *buffer, size_t buflen)
ssize_t retval;
int ret;
- fvdbg("buffer=%p buflen=%d\n", buffer, (int)buflen);
+ finfo("buffer=%p buflen=%d\n", buffer, (int)buflen);
/* Get exclusive access to the TRNG harware */
@@ -284,7 +284,7 @@ static ssize_t sam_read(struct file *filep, char *buffer, size_t buflen)
{
ret = sem_wait(&g_trngdev.waitsem);
- fvdbg("Awakened: nsamples=%d maxsamples=%d ret=%d\n",
+ finfo("Awakened: nsamples=%d maxsamples=%d ret=%d\n",
g_trngdev.nsamples, g_trngdev.maxsamples, ret);
if (ret < 0)
@@ -321,7 +321,7 @@ errout:
sem_post(&g_trngdev.exclsem);
- fvdbg("Return %d\n", (int)retval);
+ finfo("Return %d\n", (int)retval);
return retval;
}
@@ -347,7 +347,7 @@ void up_rnginitialize(void)
{
int ret;
- fvdbg("Initializing TRNG hardware\n");
+ finfo("Initializing TRNG hardware\n");
/* Initialize the device structure */
@@ -363,7 +363,7 @@ void up_rnginitialize(void)
if (irq_attach(SAM_IRQ_TRNG, sam_interrupt))
{
- fdbg("ERROR: Failed to attach to IRQ%d\n", SAM_IRQ_TRNG);
+ ferr("ERROR: Failed to attach to IRQ%d\n", SAM_IRQ_TRNG);
return;
}
@@ -380,7 +380,7 @@ void up_rnginitialize(void)
ret = register_driver("/dev/random", &g_trngops, 0644, NULL);
if (ret < 0)
{
- fdbg("ERROR: Failed to register /dev/random\n");
+ ferr("ERROR: Failed to register /dev/random\n");
return;
}
diff --git a/arch/arm/src/samv7/sam_twihs.c b/arch/arm/src/samv7/sam_twihs.c
index fa5a8b2a525665ec7b354eb8b56781c3f66c5e2b..032d2eaa4a4b3361e015b45b8387d2d1031efc0d 100644
--- a/arch/arm/src/samv7/sam_twihs.c
+++ b/arch/arm/src/samv7/sam_twihs.c
@@ -91,6 +91,10 @@
# define CONFIG_SAMV7_TWIHS2_FREQUENCY 100000
#endif
+#ifndef CONFIG_DEBUG_I2C_INFO
+# undef CONFIG_SAMV7_TWIHSHS_REGDEBUG
+#endif
+
/* Driver internal definitions *************************************************/
/* If verbose I2C debug output is enable, then allow more time before we declare
* a timeout. The debug output from twi_interrupt will really slow things down!
@@ -99,7 +103,7 @@
* to transfer on byte. So these define a "long" timeout.
*/
-#if defined(CONFIG_DEBUG_I2C) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_I2C_INFO
# define TWIHS_TIMEOUT_MSPB (50) /* 50 msec/byte */
#else
# define TWIHS_TIMEOUT_MSPB (5) /* 5 msec/byte */
@@ -112,28 +116,13 @@
#define TWIHS_MAX_FREQUENCY 66000000 /* Maximum TWIHS frequency */
-/* Macros to convert a I2C pin to a PIO open-drain output */
+/* Macros to convert a I2C pin to a GPIO open-drain output */
-#define I2C_INPUT (PIO_INPUT | PIO_CFG_PULLUP)
-#define I2C_OUTPUT (PIO_OUTPUT | PIO_CFG_OPENDRAIN | PIO_OUTPUT_SET)
+#define I2C_INPUT (GPIO_INPUT | GPIO_CFG_PULLUP)
+#define I2C_OUTPUT (GPIO_OUTPUT | GPIO_CFG_OPENDRAIN | GPIO_OUTPUT_SET)
-#define MKI2C_INPUT(p) (((p) & (PIO_PORT_MASK | PIO_PIN_MASK)) | I2C_INPUT)
-#define MKI2C_OUTPUT(p) (((p) & (PIO_PORT_MASK | PIO_PIN_MASK)) | I2C_OUTPUT)
-
-/* Debug ***********************************************************************/
-/* CONFIG_DEBUG_I2C + CONFIG_DEBUG enables general I2C debug output. */
-
-#ifdef CONFIG_DEBUG_I2C
-# define i2cdbg dbg
-# define i2cvdbg vdbg
-# define i2clldbg lldbg
-# define i2cllvdbg llvdbg
-#else
-# define i2cdbg(x...)
-# define i2cvdbg(x...)
-# define i2clldbg(x...)
-# define i2cllvdbg(x...)
-#endif
+#define MKI2C_INPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_INPUT)
+#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT)
/****************************************************************************
* Private Types
@@ -145,6 +134,8 @@ struct twi_attr_s
uint8_t twi; /* TWIHS device number (for debug output) */
uint8_t pid; /* TWIHS peripheral ID */
uint16_t irq; /* IRQ number for this TWIHS bus */
+ uint8_t glitchfltr; /* Pulse width of a glich to be suppressed by the filter */
+ uint8_t s_master; /* Single-Master Mode active */
gpio_pinset_t sclcfg; /* TWIHS CK pin configuration (SCL in I2C-ese) */
gpio_pinset_t sdacfg; /* TWIHS D pin configuration (SDA in I2C-ese) */
uintptr_t base; /* Base address of TWIHS registers */
@@ -230,6 +221,7 @@ static void twi_startmessage(struct twi_dev_s *priv, struct i2c_msg_s *msg);
static int twi_transfer(FAR struct i2c_master_s *dev,
FAR struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
+static int twi_reset_internal(FAR struct i2c_master_s *dev);
static int twi_reset(FAR struct i2c_master_s * dev);
#endif
@@ -248,6 +240,12 @@ static const struct twi_attr_s g_twi0attr =
.twi = 0,
.pid = SAM_PID_TWIHS0,
.irq = SAM_IRQ_TWIHS0,
+ .glitchfltr = CONFIG_SAMV7_TWIHS0_GLITCH_FILTER,
+#ifdef CONFIG_SAMV7_TWIHS0_SINGLE_MASTER
+ .s_master = 1,
+#else
+ .s_master = 0,
+#endif
.sclcfg = GPIO_TWIHS0_CK,
.sdacfg = GPIO_TWIHS0_D,
.base = SAM_TWIHS0_BASE,
@@ -263,6 +261,12 @@ static const struct twi_attr_s g_twi1attr =
.twi = 1,
.pid = SAM_PID_TWIHS1,
.irq = SAM_IRQ_TWIHS1,
+ .glitchfltr = CONFIG_SAMV7_TWIHS1_GLITCH_FILTER,
+#ifdef CONFIG_SAMV7_TWIHS1_SINGLE_MASTER
+ .s_master = 1,
+#else
+ .s_master = 0,
+#endif
.sclcfg = GPIO_TWIHS1_CK,
.sdacfg = GPIO_TWIHS1_D,
.base = SAM_TWIHS1_BASE,
@@ -278,6 +282,12 @@ static const struct twi_attr_s g_twi2attr =
.twi = 2,
.pid = SAM_PID_TWIHS2,
.irq = SAM_IRQ_TWIHS2,
+ .glitchfltr = CONFIG_SAMV7_TWIHS2_GLITCH_FILTER,
+#ifdef CONFIG_SAMV7_TWIHS0_SINGLE_MASTER
+ .s_master = 1,
+#else
+ .s_master = 0,
+#endif
.sclcfg = GPIO_TWIHS2_CK,
.sdacfg = GPIO_TWIHS2_D,
.base = SAM_TWIHS2_BASE,
@@ -323,7 +333,7 @@ static void twi_takesem(sem_t *sem)
* awakened by a signal.
*/
- ASSERT(errno == EINTR);
+ DEBUGASSERT(errno == EINTR);
}
}
@@ -364,7 +374,7 @@ static bool twi_checkreg(struct twi_dev_s *priv, bool wr, uint32_t value,
{
/* Yes... show how many times we did it */
- lldbg("...[Repeats %d times]...\n", priv->ntimes);
+ i2cinfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@@ -396,7 +406,7 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address)
if (twi_checkreg(priv, false, value, address))
{
- lldbg("%08x->%08x\n", address, value);
+ i2cinfo("%08x->%08x\n", address, value);
}
return value;
@@ -417,7 +427,7 @@ static void twi_putabs(struct twi_dev_s *priv, uintptr_t address,
{
if (twi_checkreg(priv, true, value, address))
{
- lldbg("%08x<-%08x\n", address, value);
+ i2cinfo("%08x<-%08x\n", address, value);
}
putreg32(value, address);
@@ -494,9 +504,9 @@ static int twi_wait(struct twi_dev_s *priv, unsigned int size)
do
{
- i2cvdbg("TWIHS%d Waiting...\n", priv->attr->twi);
+ i2cinfo("TWIHS%d Waiting...\n", priv->attr->twi);
twi_takesem(&priv->waitsem);
- i2cvdbg("TWIHS%d Awakened with result: %d\n",
+ i2cinfo("TWIHS%d Awakened with result: %d\n",
priv->attr->twi, priv->result);
}
while (priv->result == -EBUSY);
@@ -505,6 +515,24 @@ static int twi_wait(struct twi_dev_s *priv, unsigned int size)
* all further interrupts for the TWIHS have been disabled.
*/
+ /* Check if an Arbitration Lost has occured */
+
+ if (priv->result == -EUSERS)
+ {
+ /* Something bad happened on the bus so force a reset */
+
+ priv->result = twi_reset_internal(&priv->dev);
+
+ /* Although the reset was successful tell the higher driver that it's
+ * transfer has failed and should be repeated.
+ */
+
+ if (priv->result == OK)
+ {
+ priv->result = -EIO;
+ }
+ }
+
return priv->result;
}
@@ -554,7 +582,7 @@ static int twi_interrupt(struct twi_dev_s *priv)
imr = twi_getrel(priv, SAM_TWIHS_IMR_OFFSET);
pending = sr & imr;
- i2cllvdbg("TWIHS%d pending: %08x\n", priv->attr->twi, pending);
+ i2cinfo("TWIHS%d pending: %08x\n", priv->attr->twi, pending);
/* Byte received */
@@ -618,6 +646,20 @@ static int twi_interrupt(struct twi_dev_s *priv)
}
}
+ /* If Single-Master Mode is enabled and we lost arbitration (someone else or
+ * an EMC-Pulse did something on the bus) something went very wrong. So we end
+ * the current transfer with an EUSERS. The wait function will then reset
+ * the bus so further communication can take place.
+ */
+
+ else if ((priv->attr->s_master) && ((pending & TWIHS_INT_ARBLST) != 0))
+ {
+ /* Wake up the thread with an Arbitration Lost error indication */
+
+ i2cllerr("ERROR: TWIHS%d Arbitration Lost\n");
+ twi_wakeup(priv, -EUSERS);
+ }
+
/* Check for errors. We must check for errors *before* checking TXRDY or
* TXCMP because the error can be signaled in combination with TXRDY or
* TXCOMP.
@@ -627,7 +669,7 @@ static int twi_interrupt(struct twi_dev_s *priv)
{
/* Wake up the thread with an I/O error indication */
- i2clldbg("ERROR: TWIHS%d pending: %08x\n", priv->attr->twi, pending);
+ i2cerr("ERROR: TWIHS%d pending: %08x\n", priv->attr->twi, pending);
twi_wakeup(priv, -EIO);
}
@@ -750,7 +792,7 @@ static void twi_timeout(int argc, uint32_t arg, ...)
{
struct twi_dev_s *priv = (struct twi_dev_s *)arg;
- i2clldbg("ERROR: TWIHS%d Timeout!\n", priv->attr->twi);
+ i2cerr("ERROR: TWIHS%d Timeout!\n", priv->attr->twi);
twi_wakeup(priv, -ETIMEDOUT);
}
@@ -867,11 +909,12 @@ static int twi_transfer(FAR struct i2c_master_s *dev,
struct twi_dev_s *priv = (struct twi_dev_s *)dev;
irqstate_t flags;
unsigned int size;
+ uint32_t sr;
int i;
int ret;
DEBUGASSERT(dev != NULL && msgs != NULL && count > 0);
- i2cvdbg("TWIHS%d count: %d\n", priv->attr->twi, count);
+ i2cinfo("TWIHS%d count: %d\n", priv->attr->twi, count);
/* Calculate the total transfer size so that we can calculate a reasonable
* timeout value.
@@ -902,6 +945,22 @@ static int twi_transfer(FAR struct i2c_master_s *dev,
twi_setfrequency(priv, msgs->frequency);
+ /* When we are in Single Master Mode check if the bus is ready (no stuck
+ * DATA or CLK line).
+ * Otherwise initiate a bus reset.
+ */
+
+ if (priv->attr->s_master)
+ {
+ sr = twi_getrel(priv, SAM_TWIHS_SR_OFFSET);
+ if (((sr & TWIHS_INT_SDA) == 0) || ((sr & TWIHS_INT_SCL) == 0))
+ {
+ ret = twi_reset_internal(&priv->dev);
+ if (ret != OK)
+ goto errout;
+ }
+ }
+
/* Initiate the transfer. The rest will be handled from interrupt
* logic. Interrupts must be disabled to prevent re-entrance from the
* interrupt level.
@@ -915,46 +974,46 @@ static int twi_transfer(FAR struct i2c_master_s *dev,
*/
ret = twi_wait(priv, size);
+ leave_critical_section(flags);
+
+errout:
if (ret < 0)
{
- i2cdbg("ERROR: Transfer failed: %d\n", ret);
+ i2cerr("ERROR: Transfer failed: %d\n", ret);
}
- leave_critical_section(flags);
twi_givesem(&priv->exclsem);
return ret;
}
/************************************************************************************
- * Name: twi_reset
- *
- * Description:
- * Perform an I2C bus reset in an attempt to break loose stuck I2C devices.
- *
- * Input Parameters:
- * dev - Device-specific state data
- *
- * Returned Value:
- * Zero (OK) on success; a negated errno value on failure.
- *
- ************************************************************************************/
+* Name: twi_reset_internal
+*
+* Description:
+* Perform an I2C bus reset in an attempt to break loose stuck I2C devices.
+* This function can be called from inside the driver while the TWIHS device is
+* already locked, so we must not handle any semapores inside.
+* To initiate a bus reset from outside the driver use twi_reset(dev).
+*
+* Input Parameters:
+* dev - Device-specific state data
+*
+* Returned Value:
+* Zero (OK) on success; a negated errno value on failure.
+*
+************************************************************************************/
#ifdef CONFIG_I2C_RESET
-static int twi_reset(FAR struct i2c_master_s *dev)
+static int twi_reset_internal(FAR struct i2c_master_s *dev)
{
struct twi_dev_s *priv = (struct twi_dev_s *)dev;
unsigned int clockcnt;
unsigned int stretchcnt;
uint32_t sclpin;
uint32_t sdapin;
+ uint8_t wait_us;
int ret;
- ASSERT(priv);
-
- /* Get exclusive access to the TWIHS device */
-
- twi_takesem(&priv->exclsem);
-
/* Disable TWIHS interrupts */
up_disable_irq(priv->attr->irq);
@@ -971,28 +1030,31 @@ static int twi_reset(FAR struct i2c_master_s *dev)
sam_configgpio(sclpin);
sam_configgpio(sdapin);
- /* Peripheral clocking must be enabled in order to read valid data from
- * the output pin (clocking is enabled automatically for pins configured
- * as inputs).
- */
-
- sam_pio_forceclk(sclpin, true);
- sam_pio_forceclk(sdapin, true);
-
/* Clock the bus until any slaves currently driving it low let it float.
* Reading from the output will return the actual sensed level on the
* SDA pin (not the level that we wrote).
*/
+ /* Set the wait-time according to the TWI-Bus-Frequency */
+
+ if (priv->frequency >= 330000)
+ {
+ wait_us = 3;
+ }
+ else
+ {
+ wait_us = 10;
+ }
+
clockcnt = 0;
- while (sam_pioread(sdapin) == false)
+ while (sam_gpioread(sdapin) == false)
{
/* Give up if we have tried too hard */
if (clockcnt++ > 10)
{
ret = -ETIMEDOUT;
- goto errout_with_lock;
+ goto errout;
}
/* Sniff to make sure that clock stretching has finished. SCL should
@@ -1002,55 +1064,85 @@ static int twi_reset(FAR struct i2c_master_s *dev)
*/
stretchcnt = 0;
- while (sam_pioread(sclpin) == false)
+ while (sam_gpioread(sclpin) == false)
{
/* Give up if we have tried too hard */
if (stretchcnt++ > 10)
{
ret = -EAGAIN;
- goto errout_with_lock;
+ goto errout;
}
- up_udelay(10);
+ up_udelay(wait_us);
}
/* Drive SCL low */
- sam_piowrite(sclpin, false);
- up_udelay(10);
+ sam_gpiowrite(sclpin, false);
+ up_udelay(wait_us);
/* Drive SCL high (floating) again */
- sam_piowrite(sclpin, true);
- up_udelay(10);
+ sam_gpiowrite(sclpin, true);
+ up_udelay(wait_us);
}
/* Generate a start followed by a stop to reset slave
* state machines.
*/
- sam_piowrite(sdapin, false);
- up_udelay(10);
- sam_piowrite(sclpin, false);
- up_udelay(10);
-
- sam_piowrite(sclpin, true);
- up_udelay(10);
- sam_piowrite(sdapin, true);
- up_udelay(10);
+ sam_gpiowrite(sdapin, false);
+ up_udelay(wait_us);
+ sam_gpiowrite(sclpin, false);
+ up_udelay(wait_us);
- /* Clocking is no longer forced */
-
- sam_pio_forceclk(sclpin, false);
- sam_pio_forceclk(sdapin, false);
+ sam_gpiowrite(sclpin, true);
+ up_udelay(wait_us);
+ sam_gpiowrite(sdapin, true);
+ up_udelay(wait_us);
/* Re-initialize the port hardware */
twi_hw_initialize(priv, priv->frequency);
ret = OK;
-errout_with_lock:
+errout:
+ return ret;
+}
+#endif /* CONFIG_I2C_RESET */
+
+/************************************************************************************
+ * Name: twi_reset
+ *
+ * Description:
+ * Perform an I2C bus reset in an attempt to break loose stuck I2C devices.
+ * This function can be called from outside the driver, so lock the TWIHS Device
+ * and then let the internal reset function do the work.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno value on failure.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_I2C_RESET
+static int twi_reset(FAR struct i2c_master_s *dev)
+{
+ struct twi_dev_s *priv = (struct twi_dev_s *)dev;
+ int ret;
+
+ DEBUGASSERT(priv != NULL);
+
+ /* Get exclusive access to the TWIHS device */
+
+ twi_takesem(&priv->exclsem);
+
+ /* Do the reset-procedure */
+
+ ret = twi_reset_internal(dev);
/* Release our lock on the bus */
@@ -1157,7 +1249,7 @@ static void twi_hw_initialize(struct twi_dev_s *priv, uint32_t frequency)
uint32_t regval;
uint32_t mck;
- i2cvdbg("TWIHS%d Initializing\n", priv->attr->twi);
+ i2cinfo("TWIHS%d Initializing\n", priv->attr->twi);
/* Configure PIO pins */
@@ -1228,6 +1320,19 @@ static void twi_hw_initialize(struct twi_dev_s *priv, uint32_t frequency)
regval |= PMC_PCR_PID(priv->attr->pid) | PMC_PCR_CMD | PMC_PCR_EN;
twi_putabs(priv, SAM_PMC_PCR, regval);
+ /* Set the TWIHS Input Filters */
+
+ if (priv->attr->glitchfltr)
+ {
+ regval = TWIHS_FILTR_FILT | TWIHS_FILTR_THRES(priv->attr->glitchfltr);
+ }
+ else
+ {
+ regval = 0;
+ }
+
+ twi_putrel(priv, SAM_TWIHS_FILTR_OFFSET, regval);
+
/* Set the initial TWIHS data transfer frequency */
priv->frequency = 0;
@@ -1258,7 +1363,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
irqstate_t flags;
int ret;
- i2cvdbg("Initializing TWIHS%d\n", bus);
+ i2cinfo("Initializing TWIHS%d\n", bus);
#ifdef CONFIG_SAMV7_TWIHS0
if (bus == 0)
@@ -1303,7 +1408,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
else
#endif
{
- i2cdbg("ERROR: Unsupported bus: TWIHS%d\n", bus);
+ i2cerr("ERROR: Unsupported bus: TWIHS%d\n", bus);
return NULL;
}
@@ -1320,7 +1425,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
priv->timeout = wd_create();
if (priv->timeout == NULL)
{
- idbg("ERROR: Failed to allocate a timer\n");
+ ierr("ERROR: Failed to allocate a timer\n");
goto errout_with_irq;
}
@@ -1329,7 +1434,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
ret = irq_attach(priv->attr->irq, priv->attr->handler);
if (ret < 0)
{
- idbg("ERROR: Failed to attach irq %d\n", priv->attr->irq);
+ ierr("ERROR: Failed to attach irq %d\n", priv->attr->irq);
goto errout_with_wdog;
}
@@ -1374,7 +1479,7 @@ int sam_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
struct twi_dev_s *priv = (struct twi_dev_s *) dev;
irqstate_t flags;
- i2cvdbg("TWIHS%d Un-initializing\n", priv->attr->twi);
+ i2cinfo("TWIHS%d Un-initializing\n", priv->attr->twi);
/* Disable TWIHS interrupts */
diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c
index de6872e92ee45eae79663d37cd3e4e4d391a5154..07bfe1d2d4bf20a2d14998fd3bbf5ab97ae4dc7d 100644
--- a/arch/arm/src/samv7/sam_usbdevhs.c
+++ b/arch/arm/src/samv7/sam_usbdevhs.c
@@ -90,6 +90,10 @@
# define CONFIG_USBDEV_EP0_MAXSIZE 64
#endif
+#ifndef CONFIG_DEBUG_USB_INFO
+# undef CONFIG_SAMV7_USBHS_REGDEBUG
+#endif
+
/* Number of DMA transfer descriptors. Default: 8 */
#ifndef CONFIG_SAMV7_USBDEVHS_NDTDS
@@ -108,14 +112,6 @@
# warning CONFIG_USBDEV_DUALSPEED should be defined for high speed support
#endif
-/* Extremely detailed register debug that you would normally never want
- * enabled.
- */
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_SAMV7_USBHS_REGDEBUG
-#endif
-
/* Not yet supported */
#undef CONFIG_SAMV7_USBDEVHS_SCATTERGATHER
@@ -721,10 +717,6 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] =
};
#endif
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
/****************************************************************************
* Private Private Functions
****************************************************************************/
@@ -732,6 +724,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] =
/****************************************************************************
* Register Operations
****************************************************************************/
+
/****************************************************************************
* Name: sam_printreg
*
@@ -743,7 +736,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] =
#ifdef CONFIG_SAMV7_USBHS_REGDEBUG
static void sam_printreg(uintptr_t regaddr, uint32_t regval, bool iswrite)
{
- lldbg("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval);
+ uinfo("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval);
}
#endif
@@ -794,7 +787,7 @@ static void sam_checkreg(uintptr_t regaddr, uint32_t regval, bool iswrite)
{
/* No.. More than one. */
- lldbg("[repeats %d more times]\n", count);
+ uinfo("[repeats %d more times]\n", count);
}
}
@@ -869,36 +862,36 @@ static inline void sam_putreg(uint32_t regval, uint32_t regaddr)
* Name: sam_dumpep
****************************************************************************/
-#if defined(CONFIG_SAMV7_USBHS_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAMV7_USBHS_REGDEBUG
static void sam_dumpep(struct sam_usbdev_s *priv, int epno)
{
/* Global Registers */
- lldbg("Global Register:\n");
- lldbg(" CTRL: %08x\n", sam_getreg(SAM_USBHS_DEVCTRL));
- lldbg(" ISR: %08x\n", sam_getreg(SAM_USBHS_DEVISR));
- lldbg(" IMR: %08x\n", sam_getreg(SAM_USBHS_DEVIMR));
- lldbg(" EPT: %08x\n", sam_getreg(SAM_USBHS_DEVEPT));
- lldbg(" FNUM: %08x\n", sam_getreg(SAM_USBHS_DEVFNUM));
+ uinfo("Global Register:\n");
+ uinfo(" CTRL: %08x\n", sam_getreg(SAM_USBHS_DEVCTRL));
+ uinfo(" ISR: %08x\n", sam_getreg(SAM_USBHS_DEVISR));
+ uinfo(" IMR: %08x\n", sam_getreg(SAM_USBHS_DEVIMR));
+ uinfo(" EPT: %08x\n", sam_getreg(SAM_USBHS_DEVEPT));
+ uinfo(" FNUM: %08x\n", sam_getreg(SAM_USBHS_DEVFNUM));
/* Endpoint registers */
- lldbg("Endpoint %d Register:\n", epno);
- lldbg(" CFG: %08x\n", sam_getreg(SAM_USBHS_DEVEPTCFG(epno)));
- lldbg(" ISR: %08x\n", sam_getreg(SAM_USBHS_DEVEPTISR(epno)));
- lldbg(" IMR: %08x\n", sam_getreg(SAM_USBHS_DEVEPTIMR(epno)));
+ uinfo("Endpoint %d Register:\n", epno);
+ uinfo(" CFG: %08x\n", sam_getreg(SAM_USBHS_DEVEPTCFG(epno)));
+ uinfo(" ISR: %08x\n", sam_getreg(SAM_USBHS_DEVEPTISR(epno)));
+ uinfo(" IMR: %08x\n", sam_getreg(SAM_USBHS_DEVEPTIMR(epno)));
- lldbg("DMA %d Register:\n", epno);
+ uinfo("DMA %d Register:\n", epno);
if ((SAM_EPSET_DMA & SAM_EP_BIT(epno)) != 0)
{
- lldbg(" NXTDSC: %08x\n", sam_getreg(SAM_USBHS_DEVDMANXTDSC(epno)));
- lldbg(" ADDRESS: %08x\n", sam_getreg(SAM_USBHS_DEVDMAADDR(epno)));
- lldbg(" CONTROL: %08x\n", sam_getreg(SAM_USBHS_DEVDMACTRL(epno)));
- lldbg(" STATUS: %08x\n", sam_getreg(SAM_USBHS_DEVDMASTA(epno)));
+ uinfo(" NXTDSC: %08x\n", sam_getreg(SAM_USBHS_DEVDMANXTDSC(epno)));
+ uinfo(" ADDRESS: %08x\n", sam_getreg(SAM_USBHS_DEVDMAADDR(epno)));
+ uinfo(" CONTROL: %08x\n", sam_getreg(SAM_USBHS_DEVDMACTRL(epno)));
+ uinfo(" STATUS: %08x\n", sam_getreg(SAM_USBHS_DEVDMASTA(epno)));
}
else
{
- lldbg(" None\n");
+ uinfo(" None\n");
}
}
#endif
@@ -1412,9 +1405,9 @@ static int sam_req_write(struct sam_usbdev_s *priv, struct sam_ep_s *privep)
return -ENOENT;
}
- ullvdbg("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
- epno, privreq, privreq->req.len, privreq->req.xfrd,
- privreq->inflight, privep->zlpneeded);
+ uinfo("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
+ epno, privreq, privreq->req.len, privreq->req.xfrd,
+ privreq->inflight, privep->zlpneeded);
/* Handle any bytes in flight. */
@@ -1647,8 +1640,8 @@ static int sam_req_read(struct sam_usbdev_s *priv, struct sam_ep_s *privep,
return -ENOENT;
}
- ullvdbg("EP%d: len=%d xfrd=%d\n",
- epno, privreq->req.len, privreq->req.xfrd);
+ uinfo("EP%d: len=%d xfrd=%d\n",
+ epno, privreq->req.len, privreq->req.xfrd);
/* Ignore any attempt to receive a zero length packet */
@@ -1982,8 +1975,8 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
index.w = GETUINT16(priv->ctrl.index);
len.w = GETUINT16(priv->ctrl.len);
- ullvdbg("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
+ uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
/* Dispatch any non-standard requests */
@@ -2146,7 +2139,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
{
/* Special case recipient=device test mode */
- ullvdbg("test mode: %d\n", index.w);
+ uinfo("test mode: %d\n", index.w);
}
else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@@ -3489,7 +3482,7 @@ static int sam_ep_configure_internal(struct sam_ep_s *privep,
uint8_t nbtrans;
bool dirin;
- uvdbg("len: %02x type: %02x addr: %02x attr: %02x "
+ uinfo("len: %02x type: %02x addr: %02x attr: %02x "
"maxpacketsize: %02x %02x interval: %02x\n",
desc->len, desc->type, desc->addr, desc->attr,
desc->mxpacketsize[0], desc->mxpacketsize[1],
@@ -3730,7 +3723,7 @@ static int sam_ep_configure(struct usbdev_ep_s *ep,
/* Verify parameters. Endpoint 0 is not available at this interface */
-#if defined(CONFIG_DEBUG) || defined(CONFIG_USBDEV_TRACE)
+#if defined(CONFIG_DEBUG_FEATURES) || defined(CONFIG_USBDEV_TRACE)
uint8_t epno = USB_EPNO(desc->addr);
usbtrace(TRACE_EPCONFIGURE, (uint16_t)epno);
@@ -3909,7 +3902,7 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
if (privep->stalled)
{
sam_req_abort(privep, privreq, -EBUSY);
- ulldbg("ERROR: stalled\n");
+ uerr("ERROR: stalled\n");
ret = -EPERM;
}
else
@@ -4692,7 +4685,7 @@ static void sam_sw_setup(struct sam_usbdev_s *priv)
kmm_memalign(16, CONFIG_SAMV7_USBDEVHS_NDTDS * sizeof(struct sam_dtd_s));
if (!priv->dtdpool)
{
- udbg("ERROR: Failed to allocate the DMA transfer descriptor pool\n");
+ uerr("ERROR: Failed to allocate the DMA transfer descriptor pool\n");
return NULL;
}
diff --git a/arch/arm/src/samv7/sam_wdt.c b/arch/arm/src/samv7/sam_wdt.c
index 8d638066820678e6a7bdff2ee2cf068502926975..d317bbd74d34e8d21c45a3c4dcd8f6967337ad99 100644
--- a/arch/arm/src/samv7/sam_wdt.c
+++ b/arch/arm/src/samv7/sam_wdt.c
@@ -57,6 +57,11 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
+
+#ifndef CONFIG_DEBUG_WATCHDOG_INFO
+# undef CONFIG_SAMV7_WDT_REGDEBUG
+#endif
+
/* The Watchdog Timer uses the Slow Clock divided by 128 to establish the
* maximum Watchdog period to be 16 seconds (with a typical Slow Clock of
* 32768 kHz).
@@ -80,20 +85,6 @@
#define WDT_MINTIMEOUT ((1000 + WDT_FREQUENCY - 1) / WDT_FREQUENCY)
#define WDT_MAXTIMEOUT ((4096 * 1000) / WDT_FREQUENCY)
-/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing the watchdog
- * driver. NOTE: that only lldbg types are used so that the output is
- * immediately available.
- */
-
-#ifdef CONFIG_DEBUG_WATCHDOG
-# define wddbg lldbg
-# define wdvdbg llvdbg
-#else
-# define wddbg(x...)
-# define wdvdbg(x...)
-#endif
-
/****************************************************************************
* Private Types
****************************************************************************/
@@ -118,7 +109,7 @@ struct sam_lowerhalf_s
****************************************************************************/
/* Register operations ******************************************************/
-#if defined(CONFIG_SAMV7_WDT_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAMV7_WDT_REGDEBUG
static uint32_t sam_getreg(uintptr_t regaddr);
static void sam_putreg(uint32_t regval, uintptr_t regaddr);
#else
@@ -178,7 +169,7 @@ static struct sam_lowerhalf_s g_wdtdev;
*
****************************************************************************/
-#if defined(CONFIG_SAMV7_WDT_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAMV7_WDT_REGDEBUG
static uint32_t sam_getreg(uintptr_t regaddr)
{
static uint32_t prevaddr = 0;
@@ -199,7 +190,7 @@ static uint32_t sam_getreg(uintptr_t regaddr)
{
if (count == 4)
{
- lldbg("...\n");
+ wdinfo("...\n");
}
return regval;
@@ -216,7 +207,7 @@ static uint32_t sam_getreg(uintptr_t regaddr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ wdinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -228,7 +219,7 @@ static uint32_t sam_getreg(uintptr_t regaddr)
/* Show the register value read */
- lldbg("%08x->%048\n", regaddr, regval);
+ wdinfo("%08x->%048\n", regaddr, regval);
return regval;
}
#endif
@@ -241,12 +232,12 @@ static uint32_t sam_getreg(uintptr_t regaddr)
*
****************************************************************************/
-#if defined(CONFIG_SAMV7_WDT_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_SAMV7_WDT_REGDEBUG
static void sam_putreg(uint32_t regval, uintptr_t regaddr)
{
/* Show the register value being written */
- lldbg("%08x<-%08x\n", regaddr, regval);
+ wdinfo("%08x<-%08x\n", regaddr, regval);
/* Write the value */
@@ -315,7 +306,7 @@ static int sam_start(FAR struct watchdog_lowerhalf_s *lower)
* timer with the newly programmed mode parameters.
*/
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
return priv->started ? OK : -ENOSYS;
}
@@ -343,7 +334,7 @@ static int sam_stop(FAR struct watchdog_lowerhalf_s *lower)
* timer with the newly programmed mode parameters.
*/
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
return -ENOSYS;
}
@@ -366,7 +357,7 @@ static int sam_stop(FAR struct watchdog_lowerhalf_s *lower)
static int sam_keepalive(FAR struct watchdog_lowerhalf_s *lower)
{
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
/* Write WDT_CR_WDRSTT to the WDT CR regiser (along with the KEY value)
* will restart the watchdog timer.
@@ -397,7 +388,7 @@ static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower,
{
FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower;
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
DEBUGASSERT(priv);
/* Return the status bit */
@@ -426,10 +417,10 @@ static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower,
status->timeleft = 0;
- wdvdbg("Status :\n");
- wdvdbg(" flags : %08x\n", status->flags);
- wdvdbg(" timeout : %d\n", status->timeout);
- wdvdbg(" timeleft : %d\n", status->timeleft);
+ wdinfo("Status :\n");
+ wdinfo(" flags : %08x\n", status->flags);
+ wdinfo(" timeout : %d\n", status->timeout);
+ wdinfo(" timeleft : %d\n", status->timeleft);
return OK;
}
@@ -457,13 +448,13 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower,
uint32_t regval;
DEBUGASSERT(priv);
- wdvdbg("Entry: timeout=%d\n", timeout);
+ wdinfo("Entry: timeout=%d\n", timeout);
/* Can this timeout be represented? */
if (timeout < WDT_MINTIMEOUT || timeout >= WDT_MAXTIMEOUT)
{
- wddbg("Cannot represent timeout: %d < %d > %d\n",
+ wderr("ERROR: Cannot represent timeout: %d < %d > %d\n",
WDT_MINTIMEOUT, timeout, WDT_MAXTIMEOUT);
return -ERANGE;
}
@@ -496,7 +487,7 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower,
priv->reload = reload;
- wdvdbg("reload=%d timout: %d->%d\n",
+ wdinfo("reload=%d timout: %d->%d\n",
reload, timeout, priv->timeout);
/* Set the WDT_MR according to calculated value
@@ -541,7 +532,7 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower,
priv->started = true;
- wdvdbg("Setup: CR: %08x MR: %08x SR: %08x\n",
+ wdinfo("Setup: CR: %08x MR: %08x SR: %08x\n",
sam_getreg(SAM_WDT_CR), sam_getreg(SAM_WDT_MR),
sam_getreg(SAM_WDT_SR));
@@ -574,7 +565,7 @@ static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower,
xcpt_t handler)
{
#ifndef CONFIG_SAMV7_WDT_INTERRUPT
- wddbg("ERROR: Not configured for this mode\n");
+ wderr("ERROR: Not configured for this mode\n");
return NULL;
#else
FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower;
@@ -582,7 +573,7 @@ static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower,
xcpt_t oldhandler;
DEBUGASSERT(priv);
- wdvdbg("Entry: handler=%p\n", handler);
+ wdinfo("Entry: handler=%p\n", handler);
/* Get the old handler return value */
@@ -636,7 +627,7 @@ static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower,
static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
unsigned long arg)
{
- wdvdbg("cmd=%d arg=%ld\n", cmd, arg);
+ wdinfo("cmd=%d arg=%ld\n", cmd, arg);
/* No ioctls are supported */
@@ -667,7 +658,7 @@ int sam_wdt_initialize(void)
{
FAR struct sam_lowerhalf_s *priv = &g_wdtdev;
- wdvdbg("Entry: CR: %08x MR: %08x SR: %08x\n",
+ wdinfo("Entry: CR: %08x MR: %08x SR: %08x\n",
sam_getreg(SAM_WDT_CR), sam_getreg(SAM_WDT_MR),
sam_getreg(SAM_WDT_SR));
diff --git a/arch/arm/src/samv7/sam_xdmac.c b/arch/arm/src/samv7/sam_xdmac.c
index 886de898fe428b8a2bdabe852861a2d887931cd0..206ecb5d0f14ef53ef3be0dc96c0f7e0b0131d7a 100644
--- a/arch/arm/src/samv7/sam_xdmac.c
+++ b/arch/arm/src/samv7/sam_xdmac.c
@@ -551,7 +551,7 @@ static uint8_t sam_channel(uint8_t pid, const struct sam_pidmap_s *table,
}
}
- dmadbg("No channel found for pid %d\n", pid);
+ dmaerr("ERROR: No channel found for pid %d\n", pid);
DEBUGPANIC();
return 0x3f;
}
@@ -1020,7 +1020,7 @@ sam_allocdesc(struct sam_xdmach_s *xdmach, struct chnext_view1_s *prev,
* Obviously setting it to zero would break that usage.
*/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (csa != 0)
#endif
{
@@ -1340,7 +1340,7 @@ static inline int sam_single(struct sam_xdmach_s *xdmach)
static inline int sam_multiple(struct sam_xdmach_s *xdmach)
{
struct sam_xdmac_s *xdmac = sam_controller(xdmach);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_ASSERTIONS
struct chnext_view1_s *llhead = xdmach->llhead;
#endif
uintptr_t paddr;
@@ -1542,7 +1542,7 @@ static int sam_xdmac_interrupt(int irq, void *context)
{
/* Yes... Terminate the transfer with an error? */
- dmalldbg("ERROR: DMA failed: %08x\n", chpending);
+ dmaerr("ERROR: DMA failed: %08x\n", chpending);
sam_dmaterminate(xdmach, -EIO);
}
@@ -1559,7 +1559,7 @@ static int sam_xdmac_interrupt(int irq, void *context)
else
{
- dmalldbg("ERROR: Unexpected interrupt: %08x\n", chpending);
+ dmaerr("ERROR: Unexpected interrupt: %08x\n", chpending);
DEBUGPANIC();
}
@@ -1616,7 +1616,7 @@ void sam_dmainitialize(struct sam_xdmac_s *xdmac)
void weak_function up_dmainitialize(void)
{
- dmallvdbg("Initialize XDMAC\n");
+ dmainfo("Initialize XDMAC\n");
/* Enable peripheral clock */
@@ -1697,12 +1697,12 @@ DMA_HANDLE sam_dmachannel(uint8_t dmacno, uint32_t chflags)
if (xdmach)
{
- dmavdbg("XDMAC%d CH%d: chflags: %08x returning xdmach: %p\n",
+ dmainfo("XDMAC%d CH%d: chflags: %08x returning xdmach: %p\n",
(int)dmacno, xdmach->chan, (int)chflags, xdmach);
}
else
{
- dmadbg("ERROR: Failed allocate XDMAC%d channel\n", (int)dmacno);
+ dmaerr("ERROR: Failed allocate XDMAC%d channel\n", (int)dmacno);
}
return (DMA_HANDLE)xdmach;
@@ -1731,7 +1731,7 @@ void sam_dmaconfig(DMA_HANDLE handle, uint32_t chflags)
/* Set the new DMA channel flags. */
xdmach->flags = chflags;
- dmavdbg("XDMAC CH%d: chflags: %08x\n", xdmach->chan, (int)chflags);
+ dmainfo("XDMAC CH%d: chflags: %08x\n", xdmach->chan, (int)chflags);
}
/****************************************************************************
@@ -1752,7 +1752,7 @@ void sam_dmafree(DMA_HANDLE handle)
struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle;
struct sam_xdmac_s *xdmac;
- dmavdbg("xdmach: %p\n", xdmach);
+ dmainfo("xdmach: %p\n", xdmach);
DEBUGASSERT((xdmach != NULL) && (xdmach->inuse));
xdmac = sam_controller(xdmach);
@@ -1790,10 +1790,10 @@ int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
size_t remaining;
int ret = OK;
- dmavdbg("xdmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
+ dmainfo("xdmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
xdmach, (int)paddr, (int)maddr, (int)nbytes);
DEBUGASSERT(xdmach);
- dmavdbg("llhead: %p lltail: %p\n", xdmach->llhead, xdmach->lltail);
+ dmainfo("llhead: %p lltail: %p\n", xdmach->llhead, xdmach->lltail);
/* The maximum transfer size in bytes depends upon the maximum number of
* transfers and the number of bytes per transfer.
@@ -1869,10 +1869,10 @@ int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
size_t remaining;
int ret = OK;
- dmavdbg("xdmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
+ dmainfo("xdmach: %p paddr: %08x maddr: %08x nbytes: %d\n",
xdmach, (int)paddr, (int)maddr, (int)nbytes);
DEBUGASSERT(xdmach);
- dmavdbg("llhead: %p lltail: %p\n", xdmach->llhead, xdmach->lltail);
+ dmainfo("llhead: %p lltail: %p\n", xdmach->llhead, xdmach->lltail);
/* The maximum transfer size in bytes depends upon the maximum number of
* transfers and the number of bytes per transfer.
@@ -1944,7 +1944,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle;
int ret = -EINVAL;
- dmavdbg("xdmach: %p callback: %p arg: %p\n", xdmach, callback, arg);
+ dmainfo("xdmach: %p callback: %p arg: %p\n", xdmach, callback, arg);
DEBUGASSERT(xdmach != NULL);
/* Verify that the DMA has been setup (i.e., at least one entry in the
@@ -1998,7 +1998,7 @@ void sam_dmastop(DMA_HANDLE handle)
struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle;
irqstate_t flags;
- dmavdbg("xdmach: %p\n", xdmach);
+ dmainfo("xdmach: %p\n", xdmach);
DEBUGASSERT(xdmach != NULL);
flags = enter_critical_section();
@@ -2017,7 +2017,7 @@ void sam_dmastop(DMA_HANDLE handle)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
{
struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle;
@@ -2057,7 +2057,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
leave_critical_section(flags);
}
-#endif /* CONFIG_DEBUG_DMA */
+#endif /* CONFIG_DEBUG_DMA_INFO */
/****************************************************************************
* Name: sam_dmadump
@@ -2070,34 +2070,34 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
const char *msg)
{
struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle;
- dmadbg("%s\n", msg);
- dmadbg(" DMA Global Registers:\n");
- dmadbg(" GTYPE[%08x]: %08x\n", SAM_XDMAC_GTYPE, regs->gtype);
- dmadbg(" GCFG[%08x]: %08x\n", SAM_XDMAC_GCFG, regs->gcfg);
- dmadbg(" GWAC[%08x]: %08x\n", SAM_XDMAC_GWAC, regs->gwac);
- dmadbg(" GIM[%08x]: %08x\n", SAM_XDMAC_GIM, regs->gim);
- dmadbg(" GS[%08x]: %08x\n", SAM_XDMAC_GS, regs->gs);
- dmadbg(" GRS[%08x]: %08x\n", SAM_XDMAC_GRS, regs->grs);
- dmadbg(" GWS[%08x]: %08x\n", SAM_XDMAC_GWS, regs->gws);
- dmadbg(" GSWS[%08x]: %08x\n", SAM_XDMAC_GSWS, regs->gsws);
- dmadbg(" DMA Channel Registers:\n");
- dmadbg(" CIM[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIM_OFFSET, regs->cim);
- dmadbg(" CSA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSA_OFFSET, regs->csa);
- dmadbg(" CDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDA_OFFSET, regs->cda);
- dmadbg(" CNDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDA_OFFSET, regs->cnda);
- dmadbg(" CNDC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDC_OFFSET, regs->cndc);
- dmadbg(" CUBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CUBC_OFFSET, regs->cubc);
- dmadbg(" CBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CBC_OFFSET, regs->cbc);
- dmadbg(" CC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CC_OFFSET, regs->cc);
- dmadbg(" CDSMSP[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDSMSP_OFFSET, regs->cdsmsp);
- dmadbg(" CSUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSUS_OFFSET, regs->csus);
- dmadbg(" CDUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDUS_OFFSET, regs->cdus);
+ dmainfo("%s\n", msg);
+ dmainfo(" DMA Global Registers:\n");
+ dmainfo(" GTYPE[%08x]: %08x\n", SAM_XDMAC_GTYPE, regs->gtype);
+ dmainfo(" GCFG[%08x]: %08x\n", SAM_XDMAC_GCFG, regs->gcfg);
+ dmainfo(" GWAC[%08x]: %08x\n", SAM_XDMAC_GWAC, regs->gwac);
+ dmainfo(" GIM[%08x]: %08x\n", SAM_XDMAC_GIM, regs->gim);
+ dmainfo(" GS[%08x]: %08x\n", SAM_XDMAC_GS, regs->gs);
+ dmainfo(" GRS[%08x]: %08x\n", SAM_XDMAC_GRS, regs->grs);
+ dmainfo(" GWS[%08x]: %08x\n", SAM_XDMAC_GWS, regs->gws);
+ dmainfo(" GSWS[%08x]: %08x\n", SAM_XDMAC_GSWS, regs->gsws);
+ dmainfo(" DMA Channel Registers:\n");
+ dmainfo(" CIM[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIM_OFFSET, regs->cim);
+ dmainfo(" CSA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSA_OFFSET, regs->csa);
+ dmainfo(" CDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDA_OFFSET, regs->cda);
+ dmainfo(" CNDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDA_OFFSET, regs->cnda);
+ dmainfo(" CNDC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDC_OFFSET, regs->cndc);
+ dmainfo(" CUBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CUBC_OFFSET, regs->cubc);
+ dmainfo(" CBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CBC_OFFSET, regs->cbc);
+ dmainfo(" CC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CC_OFFSET, regs->cc);
+ dmainfo(" CDSMSP[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDSMSP_OFFSET, regs->cdsmsp);
+ dmainfo(" CSUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSUS_OFFSET, regs->csus);
+ dmainfo(" CDUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDUS_OFFSET, regs->cdus);
}
-#endif /* CONFIG_DEBUG_DMA */
+#endif /* CONFIG_DEBUG_DMA_INFO */
#endif /* CONFIG_SAMV7_XDMAC */
diff --git a/arch/arm/src/samv7/sam_xdmac.h b/arch/arm/src/samv7/sam_xdmac.h
index fe98581d08b7ecad25863eafbd2a630f483b7456..cfbf14fe0dd002ca98cbace12f9a11d534f520eb 100644
--- a/arch/arm/src/samv7/sam_xdmac.h
+++ b/arch/arm/src/samv7/sam_xdmac.h
@@ -50,12 +50,6 @@
* Pre-processor Definitions
************************************************************************************/
-/* Configuration ********************************************************************/
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_DMA
-#endif
-
/* DMA ******************************************************************************/
/* Flags used to characterize the DMA channel. The naming convention is that one
@@ -172,7 +166,7 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
struct sam_dmaregs_s
{
/* Global Registers.
@@ -210,7 +204,7 @@ struct sam_dmaregs_s
uint32_t csus; /* Channel Source Microblock Stride */
uint32_t cdus; /* Channel Destination Microblock Stride */
};
-#endif /* CONFIG_DEBUG_DMA */
+#endif /* CONFIG_DEBUG_DMA_INFO */
/************************************************************************************
* Inline Functions
@@ -342,7 +336,7 @@ void sam_dmastop(DMA_HANDLE handle);
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs);
#else
# define sam_dmasample(handle,regs)
@@ -356,7 +350,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs);
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, const char *msg);
#else
# define sam_dmadump(handle,regs,msg)
diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig
index 1da3821f825b2227c481faed883114121a353b7c..4a838eb07d6a3cef477984d896e5b04f5e905cfc 100644
--- a/arch/arm/src/stm32/Kconfig
+++ b/arch/arm/src/stm32/Kconfig
@@ -484,6 +484,16 @@ config ARCH_CHIP_STM32F105VB
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
+config ARCH_CHIP_STM32F105RB
+ bool "STM32F105RB"
+ select ARCH_CORTEXM3
+ select STM32_STM32F10XX
+ select STM32_CONNECTIVITYLINE
+ select STM32_HAVE_DAC1
+ select STM32_HAVE_DAC2
+ select STM32_HAVE_I2C2
+ select STM32_HAVE_TIM4
+
config ARCH_CHIP_STM32F107VC
bool "STM32F107VC"
select ARCH_CORTEXM3
@@ -1182,7 +1192,6 @@ config STM32_VALUELINE
select STM32_HAVE_TIM15
select STM32_HAVE_TIM16
select STM32_HAVE_TIM17
- select STM32_HAVE_ADC2
select STM32_HAVE_SPI2 if STM32_HIGHDENSITY
select STM32_HAVE_SPI3 if STM32_HIGHDENSITY
@@ -2533,6 +2542,8 @@ config STM32_FSMC_SRAM
---help---
In addition to internal SRAM, SRAM may also be available through the FSMC.
+menu "Timer Configuration"
+
config STM32_TIM1_PWM
bool "TIM1 PWM"
default n
@@ -5300,6 +5311,8 @@ config STM32_TIM14_CAP
Timer devices may be used for different purposes. One special purpose is
to capture input.
+endmenu # Timer Configuration
+
menu "ADC Configuration"
depends on STM32_ADC
@@ -6202,9 +6215,9 @@ endchoice
config STM32_ETHMAC_REGDEBUG
bool "Register-Level Debug"
default n
- depends on DEBUG
+ depends on DEBUG_NET_INFO
---help---
- Enable very low-level register access debug. Depends on DEBUG.
+ Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES.
endmenu
endif
@@ -6292,16 +6305,16 @@ menu "USB Host Debug Configuration"
config STM32_USBHOST_REGDEBUG
bool "Register-Level Debug"
default n
- depends on USBHOST && (STM32_OTGFS || STM32_OTGHS)
+ depends on USBHOST && DEBUG_USB_INFO && (STM32_OTGFS || STM32_OTGHS)
---help---
- Enable very low-level register access debug. Depends on DEBUG.
+ Enable very low-level register access debug.
config STM32_USBHOST_PKTDUMP
bool "Packet Dump Debug"
default n
- depends on USBHOST && (STM32_OTGFS || STM32_OTGHS)
+ depends on USBHOST && DEBUG_USB_INFO && (STM32_OTGFS || STM32_OTGHS)
---help---
- Dump all incoming and outgoing USB packets. Depends on DEBUG.
+ Dump all incoming and outgoing USB packets.
endmenu
@@ -6320,21 +6333,21 @@ config STM32_USB_ITRMP
F3 family and selects the use of the dedicated USB interrupts.
menu "CAN driver configuration"
- depends on STM32_CAN1 || STM32_CAN2
+ depends on STM32_CAN
config CAN1_BAUD
int "CAN1 BAUD"
default 250000
depends on STM32_CAN1
---help---
- CAN1 BAUD rate. Required if STM32_CAN1 is defined.
+ CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined.
config CAN2_BAUD
int "CAN2 BAUD"
default 250000
depends on STM32_CAN2
---help---
- CAN2 BAUD rate. Required if STM32_CAN2 is defined.
+ CAN2 BAUD rate. Required if CONFIG_STM32_CAN2 is defined.
config CAN_TSEG1
int "TSEG1 quanta"
@@ -6347,6 +6360,15 @@ config CAN_TSEG2
default 7
---help---
The number of CAN time quanta in segment 2. Default: 7
+
+config STM32_CAN_REGDEBUG
+ bool "CAN Register level debug"
+ depends on DEBUG_CAN_INFO
+ default n
+ ---help---
+ Output detailed register-level CAN device debug information.
+ Requires also CONFIG_DEBUG_CAN_INFO.
+
endmenu
if STM32_LTDC
diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs
index 98c1bad6463b166be2c28848399bb40c8b297d09..1a3355d24d446ddf1b0e7e5c0d3c096207cdc355 100644
--- a/arch/arm/src/stm32/Make.defs
+++ b/arch/arm/src/stm32/Make.defs
@@ -109,10 +109,10 @@ endif
CHIP_ASRCS =
CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c
-CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c stm32_irq.c
-CHIP_CSRCS += stm32_dma.c stm32_lowputc.c stm32_serial.c stm32_spi.c
-CHIP_CSRCS += stm32_sdio.c stm32_tim.c stm32_waste.c stm32_ccm.c stm32_uid.c
-CHIP_CSRCS += stm32_capture.c
+CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c
+CHIP_CSRCS += stm32_irq.c stm32_dma.c stm32_lowputc.c stm32_getc.c
+CHIP_CSRCS += stm32_serial.c stm32_spi.c stm32_sdio.c stm32_tim.c
+CHIP_CSRCS += stm32_waste.c stm32_ccm.c stm32_uid.c stm32_capture.c
ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += stm32_tim_lowerhalf.c
@@ -247,7 +247,7 @@ ifeq ($(CONFIG_STM32_WWDG),y)
CHIP_CSRCS += stm32_wwdg.c
endif
-ifeq ($(CONFIG_DEBUG),y)
+ifeq ($(CONFIG_DEBUG_FEATURES),y)
CHIP_CSRCS += stm32_dumpgpio.c
endif
diff --git a/arch/arm/src/stm32/chip.h b/arch/arm/src/stm32/chip.h
index bba330edfaf7741f1a4d150cbefa3e63f2c1dc8f..4542a3885f02a6fee8f26ca3df9318b006ba30c4 100644
--- a/arch/arm/src/stm32/chip.h
+++ b/arch/arm/src/stm32/chip.h
@@ -109,6 +109,9 @@
# elif defined(CONFIG_ARCH_CHIP_STM32F105VB)
# include "chip/stm32f105v_pinmap.h"
+# elif defined(CONFIG_ARCH_CHIP_STM32F105RB)
+# include "chip/stm32f105r_pinmap.h"
+
# elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
# include "chip/stm32f107v_pinmap.h"
# else
diff --git a/arch/arm/src/stm32/chip/stm32_adc.h b/arch/arm/src/stm32/chip/stm32_adc.h
index 3a59ba25a8879f260bc86a38cb35f96e6dc27ba6..8a9eb956b673056b324dacac856b3f0c8315a0e7 100644
--- a/arch/arm/src/stm32/chip/stm32_adc.h
+++ b/arch/arm/src/stm32/chip/stm32_adc.h
@@ -1,7 +1,7 @@
/****************************************************************************************************
* arch/arm/src/stm32/chip/stm32_adc.h
*
- * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009, 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -261,6 +261,7 @@
# define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles. For STM32L15XX: 9 ADCCLK cycles */
# define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles. For STM32L15XX: 7 ADCCLK cycles */
# define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */
+# define ADC_CR1_RESERVED (0xfb3f0000)
#endif
/* ADC control register 2 */
@@ -391,7 +392,7 @@
# define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
# define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */
-
+# define ADC_CR2_RESERVED (0x8080f0fc)
#else
# define ADC_CR2_JEXTSEL_SHIFT (12) /* Bits 12-14: External event select for injected group */
# define ADC_CR2_JEXTSEL_MASK (7 << ADC_CR2_JEXTSEL_SHIFT)
@@ -477,7 +478,7 @@
# define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
# define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
-# define ADC_SMPR1_SMP18_SHIFT (21) /* Bits 24-26: Channel 18 Sample time selection */
+# define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */
# define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
# endif
#else
diff --git a/arch/arm/src/stm32/chip/stm32_flash.h b/arch/arm/src/stm32/chip/stm32_flash.h
index c031492752724b6b63f0fa54a58d77ab14923135..70e6d62d97607717a3baa12d6c1ed198feaaef4d 100644
--- a/arch/arm/src/stm32/chip/stm32_flash.h
+++ b/arch/arm/src/stm32/chip/stm32_flash.h
@@ -3,7 +3,7 @@
*
* Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
- * David Sidrane
+ * David Sidrane
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/arch/arm/src/stm32/chip/stm32f105r_pinmap.h b/arch/arm/src/stm32/chip/stm32f105r_pinmap.h
new file mode 100644
index 0000000000000000000000000000000000000000..ffd3ef35c45d11703629bfafd295d7efc4373586
--- /dev/null
+++ b/arch/arm/src/stm32/chip/stm32f105r_pinmap.h
@@ -0,0 +1,328 @@
+/************************************************************************************
+ * arch/arm/src/stm32/chip/stm32f105r_pinmap.h
+ *
+ * Copyright (C) 2009, 2011, 2014, 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F105R_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_CHIP_STM32F105R_PINMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include "stm32_gpio.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Alternate Pin Functions: */
+
+#define GPIO_ADC12_IN0 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_ADC12_IN1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_ADC12_IN10 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
+#define GPIO_ADC12_IN11 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
+#define GPIO_ADC12_IN12 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
+#define GPIO_ADC12_IN13 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)
+#define GPIO_ADC12_IN14 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN4)
+#define GPIO_ADC12_IN15 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5)
+#define GPIO_ADC12_IN2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_ADC12_IN3 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_ADC12_IN4 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_ADC12_IN5 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_ADC12_IN6 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_ADC12_IN7 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_ADC12_IN8 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_ADC12_IN9 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
+
+#if defined(CONFIG_STM32_CAN1_REMAP1)
+# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN8)
+# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
+#else
+# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
+# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
+#endif
+
+#if defined(CONFIG_STM32_CAN2_REMAP)
+# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN5)
+# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
+#else
+# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
+# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
+#endif
+
+#if 0 /* Needs further investigation */
+#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
+#endif
+
+#if defined(CONFIG_STM32_I2C1_REMAP)
+# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
+# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
+#else
+# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
+# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
+#endif
+#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+
+#define GPIO_I2C2_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_I2C2_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_I2C2_SMBA (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_I2S2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_I2S2_MCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
+#define GPIO_I2S2_WS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
+
+#define GPIO_I2S3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_I2S3_MCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
+#define GPIO_I2S3_SD (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_I2S3_WS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
+
+#define GPIO_MCO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
+
+#define GPIO_OTGFS_DM (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_OTGFS_DP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_OTGFS_ID (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_OTGFS_SOF (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_OTGFS_VBUS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
+
+#if defined(CONFIG_STM32_SPI1_REMAP)
+# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
+# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
+# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
+# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+#else
+# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
+# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN5)
+# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
+# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
+#endif
+
+#define GPIO_SPI2_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_SPI2_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_SPI2_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_SPI2_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
+
+#if defined(CONFIG_STM32_SPI3_REMAP)
+# define GPIO_SPI3_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
+# define GPIO_SPI3_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
+# define GPIO_SPI3_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
+# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
+#else
+# define GPIO_SPI3_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
+# define GPIO_SPI3_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
+# define GPIO_SPI3_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
+# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+#endif
+
+#if 0 /* Needs further investigation */
+#define GPIO_TAMPER_RTC (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN13)
+#endif
+
+#if defined(CONFIG_STM32_TIM1_PARTIAL_REMAP)
+# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
+# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
+# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
+# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
+# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
+# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
+#else
+# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
+# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
+# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
+# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
+# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
+# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
+# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
+#endif
+
+#if defined(CONFIG_STM32_TIM2_FULL_REMAP)
+# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
+# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
+# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
+# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3)
+# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
+# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10)
+# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
+# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
+# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
+#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_1)
+# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
+# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
+# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
+# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3)
+# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
+# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
+# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
+#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_2)
+# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
+# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
+# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10)
+# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
+# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
+# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
+#else
+# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
+# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
+# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
+# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
+#endif
+
+#if defined(CONFIG_STM32_TIM3_FULL_REMAP)
+# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN6)
+# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
+# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN7)
+# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
+# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN8)
+# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
+# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN9)
+# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
+#elif defined(CONFIG_STM32_TIM3_PARTIAL_REMAP)
+# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
+# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
+# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN5)
+# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
+# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
+#else
+# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
+# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
+# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
+# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
+# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
+# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
+#endif
+#define GPIO_TIM3_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN2)
+
+#define GPIO_TIM4_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_TIM4_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_TIM4_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_TIM4_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_TIM4_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_TIM4_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_TIM4_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_TIM4_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
+
+#define GPIO_TIM5_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TIM5_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TIM5_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_TIM5_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_TIM5_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_TIM5_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_TIM5_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_TIM5_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
+
+#if 0 /* Needs further investigation */
+#if defined(CONFIG_STM32_TRACESWO_REMAP)
+# define GPIO_TRACESWO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
+#endif
+#endif
+
+#define GPIO_USART1_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_USART1_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_USART1_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
+#if defined(CONFIG_STM32_USART1_REMAP)
+# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
+#else
+# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
+#endif
+
+#define GPIO_USART2_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_USART2_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_USART2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_USART2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_USART2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
+
+#if defined(CONFIG_STM32_USART3_PARTIAL_REMAP)
+# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
+# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
+# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
+# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
+# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
+#else
+# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
+# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
+# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
+# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
+# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
+#endif
+
+#define GPIO_UART4_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
+#define GPIO_UART4_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
+
+#define GPIO_UART5_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN2)
+#define GPIO_UART5_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
+
+#define GPIO_WKUP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
+
+/* Some GPIOs are accessible only as remapped, alternate functions */
+
+#if 0 /* Needs further investigation */
+#define GPIO_PA13 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN13)
+#define GPIO_PA14 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN14)
+#define GPIO_PA15 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_PB3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_PB4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
+#endif
+
+#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F105R_PINMAP_H */
diff --git a/arch/arm/src/stm32/chip/stm32f105v_pinmap.h b/arch/arm/src/stm32/chip/stm32f105v_pinmap.h
index 71ffe846487cb26032143e1d9ae69ff2cc282caa..5fd7029e2c1b096f7cb5b7f13a5aa1592c6426f1 100644
--- a/arch/arm/src/stm32/chip/stm32f105v_pinmap.h
+++ b/arch/arm/src/stm32/chip/stm32f105v_pinmap.h
@@ -91,44 +91,6 @@
#define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
#endif
-#if 0 /* Needs further investigation */
-#define GPIO_ETH_MDC (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN1)
-#define GPIO_ETH_MDIO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
-#define GPIO_ETH_MIICOL (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
-#define GPIO_ETH_MIICRSWKUP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
-#define GPIO_ETH_MIIRXCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
-
-#if defined(CONFIG_STM32_ETH_REMAP)
-# define GPIO_ETH_MIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN9)
-# define GPIO_ETH_MIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
-# define GPIO_ETH_MIIRXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN11)
-# define GPIO_ETH_MIIRXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
-# define GPIO_ETH_MIIRXDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
-#else
-# define GPIO_ETH_MIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
-# define GPIO_ETH_MIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
-# define GPIO_ETH_MIIRXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
-# define GPIO_ETH_MIIRXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
-# define GPIO_ETH_MIIRXDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
-#endif
-
-#define GPIO_ETH_MIIRXER (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
-#define GPIO_ETH_MIITXCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN3)
-#define GPIO_ETH_MIITXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
-#define GPIO_ETH_MIITXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
-#define GPIO_ETH_MIITXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN2)
-#define GPIO_ETH_MIITXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
-#define GPIO_ETH_MIITXEN (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
-#define GPIO_ETH_PPSOUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
-#define GPIO_ETH_RMIICRSDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
-#define GPIO_ETH_RMIIREFCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
-#define GPIO_ETH_RMIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
-#define GPIO_ETH_RMIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
-#define GPIO_ETH_RMIITXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
-#define GPIO_ETH_RMIITXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
-#define GPIO_ETH_RMIITXEN (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
-#endif
-
#if defined(CONFIG_STM32_I2C1_REMAP)
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h b/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
index c0f675aa023438995441c15d895ba3b0b6fa2da9..ff75a5d0ad9edc07851b66e97516d33462a74197 100644
--- a/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
+++ b/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
@@ -413,8 +413,10 @@
#define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
#define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN2)
#define GPIO_I2C2_SMBA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6)
-#if defined(CONFIG_STM32_STM32F446)
+#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F411)
# define GPIO_I2C2_SDA_4 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN3)
+#endif
+#if defined(CONFIG_STM32_STM32F446)
# define GPIO_I2C2_SDA_5 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN12)
#endif
diff --git a/arch/arm/src/stm32/stm32.h b/arch/arm/src/stm32/stm32.h
index ee5a6497f80424894ead8d26249269bd600409e9..af91ea4ea60368069646936440981a6531c95d0c 100644
--- a/arch/arm/src/stm32/stm32.h
+++ b/arch/arm/src/stm32/stm32.h
@@ -53,21 +53,6 @@
* Pre-processor Definitions
************************************************************************************/
-/* Additional Configuration *********************************************************/
-/* Custom debug settings used in the STM32 port. These are managed by STM32-specific
- * logic and not the common logic in include/debug.h. NOTE: Some of these also
- * depend on CONFIG_DEBUG_VERBOSE
- */
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_DMA
-# undef CONFIG_DEBUG_RTC
-# undef CONFIG_DEBUG_I2C
-# undef CONFIG_DEBUG_CAN
-# undef CONFIG_DEBUG_PWM
-# undef CONFIG_DEBUG_SENSORS
-#endif
-
/* Peripherals **********************************************************************/
#include "chip.h"
@@ -92,6 +77,7 @@
#include "stm32_usbdev.h"
#include "stm32_wdg.h"
#include "stm32_lowputc.h"
+#include "stm32_getc.h"
#include "stm32_eth.h"
#endif /* __ARCH_ARM_SRC_STM32_STM32_H */
diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c
index c24a98dbc75b0d6b02356a66b79ac8d6ab780dcb..31109fd8f50aa28d706cbc8f7770894b9b38e052 100644
--- a/arch/arm/src/stm32/stm32_adc.c
+++ b/arch/arm/src/stm32/stm32_adc.c
@@ -344,22 +344,20 @@ static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset);
/* ADC Interrupt Handler */
static int adc_interrupt(FAR struct adc_dev_s *dev);
-#ifdef CONFIG_STM32_STM32L15XX
+#if defined(STM32_IRQ_ADC1) && defined(CONFIG_STM32_ADC1)
static int adc1_interrupt(int irq, FAR void *context);
#endif
-#if (defined(CONFIG_STM32_STM32F10XX) || \
- defined(CONFIG_STM32_STM32F30XX)) && \
- (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2))
+#if defined(STM32_IRQ_ADC12) && (defined(CONFIG_STM32_ADC1) || \
+ defined(CONFIG_STM32_ADC2))
static int adc12_interrupt(int irq, FAR void *context);
#endif
-#if (defined(CONFIG_STM32_STM32F10XX) || \
- defined(CONFIG_STM32_STM32F30XX)) && defined(CONFIG_STM32_ADC3)
+#if (defined(STM32_IRQ_ADC3) && defined(CONFIG_STM32_ADC3))
static int adc3_interrupt(int irq, FAR void *context);
#endif
-#if defined(CONFIG_STM32_STM32F30XX) && defined(CONFIG_STM32_ADC4)
+#if defined(STM32_IRQ_ADC4) && defined(CONFIG_STM32_ADC4)
static int adc4_interrupt(int irq, FAR void *context);
#endif
-#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+#if defined(STM32_IRQ_ADC)
static int adc123_interrupt(int irq, FAR void *context);
#endif
@@ -433,15 +431,17 @@ static const struct adc_ops_s g_adcops =
#ifdef CONFIG_STM32_ADC1
static struct stm32_dev_s g_adcpriv1 =
{
-#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
- .irq = STM32_IRQ_ADC12,
- .isr = adc12_interrupt,
-#elif defined(CONFIG_STM32_STM32L15XX)
+#if defined(STM32_IRQ_ADC1)
.irq = STM32_IRQ_ADC1,
.isr = adc1_interrupt,
-#else
+#elif defined(STM32_IRQ_ADC12)
+ .irq = STM32_IRQ_ADC12,
+ .isr = adc12_interrupt,
+#elif defined(STM32_IRQ_ADC)
.irq = STM32_IRQ_ADC,
.isr = adc123_interrupt,
+#else
+# error "No STM32_IRQ_ADC1 STM32_IRQ_ADC12 or STM32_IRQ_ADC defined for CONFIG_STM32_ADC1"
#endif
.intf = 1,
.base = STM32_ADC1_BASE,
@@ -470,12 +470,14 @@ static struct adc_dev_s g_adcdev1 =
#ifdef CONFIG_STM32_ADC2
static struct stm32_dev_s g_adcpriv2 =
{
-#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
+#if defined(STM32_IRQ_ADC12)
.irq = STM32_IRQ_ADC12,
.isr = adc12_interrupt,
-#else
+#elif defined(STM32_IRQ_ADC)
.irq = STM32_IRQ_ADC,
.isr = adc123_interrupt,
+#else
+# error "No STM32_IRQ_ADC12 or STM32_IRQ_ADC defined for CONFIG_STM32_ADC2"
#endif
.intf = 2,
.base = STM32_ADC2_BASE,
@@ -504,12 +506,14 @@ static struct adc_dev_s g_adcdev2 =
#ifdef CONFIG_STM32_ADC3
static struct stm32_dev_s g_adcpriv3 =
{
-#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
+#if defined(STM32_IRQ_ADC3)
.irq = STM32_IRQ_ADC3,
.isr = adc3_interrupt,
-#else
+#elif defined(STM32_IRQ_ADC)
.irq = STM32_IRQ_ADC,
.isr = adc123_interrupt,
+#else
+# error "No STM32_IRQ_ADC3 or STM32_IRQ_ADC defined for CONFIG_STM32_ADC3"
#endif
.intf = 3,
.base = STM32_ADC3_BASE,
@@ -744,22 +748,22 @@ static void tim_modifyreg(FAR struct stm32_dev_s *priv, int offset,
#ifdef ADC_HAVE_TIMER
static void tim_dumpregs(FAR struct stm32_dev_s *priv, FAR const char *msg)
{
- avdbg("%s:\n", msg);
- avdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
+ ainfo("%s:\n", msg);
+ ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
tim_getreg(priv, STM32_GTIM_CR1_OFFSET),
tim_getreg(priv, STM32_GTIM_CR2_OFFSET),
tim_getreg(priv, STM32_GTIM_SMCR_OFFSET),
tim_getreg(priv, STM32_GTIM_DIER_OFFSET));
- avdbg(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n",
+ ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n",
tim_getreg(priv, STM32_GTIM_SR_OFFSET),
tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET),
tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET));
- avdbg(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
+ ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
tim_getreg(priv, STM32_GTIM_CCER_OFFSET),
tim_getreg(priv, STM32_GTIM_CNT_OFFSET),
tim_getreg(priv, STM32_GTIM_PSC_OFFSET),
tim_getreg(priv, STM32_GTIM_ARR_OFFSET));
- avdbg(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
+ ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
tim_getreg(priv, STM32_GTIM_CCR1_OFFSET),
tim_getreg(priv, STM32_GTIM_CCR2_OFFSET),
tim_getreg(priv, STM32_GTIM_CCR3_OFFSET),
@@ -767,7 +771,7 @@ static void tim_dumpregs(FAR struct stm32_dev_s *priv, FAR const char *msg)
#ifndef CONFIG_STM32_STM32L15XX
if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
{
- avdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
+ ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
tim_getreg(priv, STM32_ATIM_RCR_OFFSET),
tim_getreg(priv, STM32_ATIM_BDTR_OFFSET),
tim_getreg(priv, STM32_ATIM_DCR_OFFSET),
@@ -775,7 +779,7 @@ static void tim_dumpregs(FAR struct stm32_dev_s *priv, FAR const char *msg)
}
else
{
- avdbg(" DCR: %04x DMAR: %04x\n",
+ ainfo(" DCR: %04x DMAR: %04x\n",
tim_getreg(priv, STM32_GTIM_DCR_OFFSET),
tim_getreg(priv, STM32_GTIM_DMAR_OFFSET));
}
@@ -800,7 +804,7 @@ static void tim_dumpregs(FAR struct stm32_dev_s *priv, FAR const char *msg)
#ifdef ADC_HAVE_TIMER
static void adc_timstart(FAR struct stm32_dev_s *priv, bool enable)
{
- avdbg("enable: %d\n", enable ? 1 : 0);
+ ainfo("enable: %d\n", enable ? 1 : 0);
if (enable)
{
@@ -869,7 +873,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
* position.
*/
- avdbg("Initializing timers extsel = 0x%08x\n", priv->extsel);
+ ainfo("Initializing timers extsel = 0x%08x\n", priv->extsel);
adc_modifyreg(priv, STM32_ADC_EXTREG_OFFSET,
ADC_EXTREG_EXTEN_MASK | ADC_EXTREG_EXTSEL_MASK,
@@ -902,7 +906,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
if (prescaler < 1)
{
- adbg("WARNING: Prescaler underflowed.\n");
+ awarn("WARNING: Prescaler underflowed.\n");
prescaler = 1;
}
@@ -910,7 +914,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
else if (prescaler > 65536)
{
- adbg("WARNING: Prescaler overflowed.\n");
+ awarn("WARNING: Prescaler overflowed.\n");
prescaler = 65536;
}
@@ -919,12 +923,12 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
reload = timclk / priv->freq;
if (reload < 1)
{
- adbg("WARNING: Reload value underflowed.\n");
+ awarn("WARNING: Reload value underflowed.\n");
reload = 1;
}
else if (reload > 65535)
{
- adbg("WARNING: Reload value overflowed.\n");
+ awarn("WARNING: Reload value overflowed.\n");
reload = 65535;
}
@@ -1066,7 +1070,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
break;
default:
- adbg("No such trigger: %d\n", priv->trigger);
+ aerr("ERROR: No such trigger: %d\n", priv->trigger);
return -EINVAL;
}
@@ -1201,7 +1205,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
#if defined(CONFIG_STM32_STM32F10XX)
static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable)
{
- avdbg("enable: %d\n", enable ? 1 : 0);
+ ainfo("enable: %d\n", enable ? 1 : 0);
if (!enable)
{
@@ -1223,7 +1227,7 @@ static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable)
{
uint32_t regval;
- avdbg("enable: %d\n", enable ? 1 : 0);
+ ainfo("enable: %d\n", enable ? 1 : 0);
if (enable)
{
@@ -1252,7 +1256,7 @@ static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable)
#else
static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable)
{
- avdbg("enable: %d\n", enable ? 1 : 0);
+ ainfo("enable: %d\n", enable ? 1 : 0);
if (enable)
{
@@ -1360,7 +1364,7 @@ static void adc_power_down_idle(FAR struct stm32_dev_s *priv, bool pdi_high)
{
uint32_t regval;
- avdbg("PDI: %d\n", pdi_high ? 1 : 0);
+ ainfo("PDI: %d\n", pdi_high ? 1 : 0);
regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET);
@@ -1401,7 +1405,7 @@ static void adc_power_down_delay(FAR struct stm32_dev_s *priv, bool pdd_high)
{
uint32_t regval;
- avdbg("PDD: %d\n", pdd_high ? 1 : 0);
+ ainfo("PDD: %d\n", pdd_high ? 1 : 0);
regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET);
@@ -1441,7 +1445,7 @@ static void adc_power_down_delay(FAR struct stm32_dev_s *priv, bool pdd_high)
static void adc_dels_after_conversion(FAR struct stm32_dev_s *priv,
uint32_t delay)
{
- avdbg("Delay selected: 0x%08x\n", delay);
+ ainfo("Delay selected: 0x%08x\n", delay);
adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_DELS_MASK, delay);
}
@@ -1467,7 +1471,7 @@ static void adc_dels_after_conversion(FAR struct stm32_dev_s *priv,
static void adc_select_ch_bank(FAR struct stm32_dev_s *priv,
bool chb_selected)
{
- avdbg("Bank of channels selected: %c\n", chb_selected ? 'B' : 'A');
+ ainfo("Bank of channels selected: %c\n", chb_selected ? 'B' : 'A');
if (chb_selected)
{
@@ -1501,7 +1505,7 @@ static void adc_enable(FAR struct stm32_dev_s *priv, bool enable)
{
uint32_t regval;
- avdbg("enable: %d\n", enable ? 1 : 0);
+ ainfo("enable: %d\n", enable ? 1 : 0);
regval = adc_getreg(priv, STM32_ADC_CR_OFFSET);
@@ -1539,7 +1543,7 @@ static void adc_enable(FAR struct stm32_dev_s *priv, bool enable)
bool enabled = false;
#endif
- avdbg("enable: %d\n", enable ? 1 : 0);
+ ainfo("enable: %d\n", enable ? 1 : 0);
if (!enabled && enable)
{
@@ -1713,7 +1717,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
int ret;
#endif
- allvdbg("intf: %d\n", priv->intf);
+ ainfo("intf: %d\n", priv->intf);
flags = enter_critical_section();
#if defined(CONFIG_STM32_STM32L15XX) && \
@@ -1998,7 +2002,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
ret = adc_timinit(priv);
if (ret < 0)
{
- adbg("adc_timinit failed: %d\n", ret);
+ aerr("ERROR: adc_timinit failed: %d\n", ret);
}
}
#ifndef CONFIG_ADC_NO_STARTUP_CONV
@@ -2014,26 +2018,26 @@ static void adc_reset(FAR struct adc_dev_s *dev)
leave_critical_section(flags);
#ifdef CONFIG_STM32_STM32F30XX
- avdbg("ISR: 0x%08x CR: 0x%08x CFGR: 0x%08x\n",
+ ainfo("ISR: 0x%08x CR: 0x%08x CFGR: 0x%08x\n",
adc_getreg(priv, STM32_ADC_ISR_OFFSET),
adc_getreg(priv, STM32_ADC_CR_OFFSET),
adc_getreg(priv, STM32_ADC_CFGR_OFFSET));
#else
- avdbg("SR: 0x%08x CR1: 0x%08x CR2: 0x%08x\n",
+ ainfo("SR: 0x%08x CR1: 0x%08x CR2: 0x%08x\n",
adc_getreg(priv, STM32_ADC_SR_OFFSET),
adc_getreg(priv, STM32_ADC_CR1_OFFSET),
adc_getreg(priv, STM32_ADC_CR2_OFFSET));
#endif
- avdbg("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n",
+ ainfo("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n",
adc_getreg(priv, STM32_ADC_SQR1_OFFSET),
adc_getreg(priv, STM32_ADC_SQR2_OFFSET),
adc_getreg(priv, STM32_ADC_SQR3_OFFSET));
#if defined(CONFIG_STM32_STM32F30XX)
- avdbg("SQR4: 0x%08x\n", adc_getreg(priv, STM32_ADC_SQR4_OFFSET));
+ ainfo("SQR4: 0x%08x\n", adc_getreg(priv, STM32_ADC_SQR4_OFFSET));
#elif defined(CONFIG_STM32_STM32L15XX)
- avdbg("SQR4: 0x%08x SQR5: 0x%08x\n",
+ ainfo("SQR4: 0x%08x SQR5: 0x%08x\n",
adc_getreg(priv, STM32_ADC_SQR4_OFFSET)
adc_getreg(priv, STM32_ADC_SQR5_OFFSET));
#endif
@@ -2041,16 +2045,16 @@ static void adc_reset(FAR struct adc_dev_s *dev)
#if defined(CONFIG_STM32_STM32F30XX)
if (priv->base == STM32_ADC1_BASE || priv->base == STM32_ADC2_BASE)
{
- avdbg("CCR: 0x%08x\n", getreg32(STM32_ADC12_CCR));
+ ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC12_CCR));
}
else
{
- avdbg("CCR: 0x%08x\n", getreg32(STM32_ADC34_CCR));
+ ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC34_CCR));
}
#elif defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F40XX) || \
defined(CONFIG_STM32_STM32L15XX)
- avdbg("CCR: 0x%08x\n", getreg32(STM32_ADC_CCR));
+ ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC_CCR));
#endif
}
@@ -2103,7 +2107,7 @@ static int adc_setup(FAR struct adc_dev_s *dev)
ret = irq_attach(priv->irq, priv->isr);
if (ret < 0)
{
- avdbg("irq_attach failed: %d\n", ret);
+ ainfo("irq_attach failed: %d\n", ret);
return ret;
}
@@ -2113,7 +2117,7 @@ static int adc_setup(FAR struct adc_dev_s *dev)
/* Enable the ADC interrupt */
- avdbg("Enable the ADC interrupt: irq=%d\n", priv->irq);
+ ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq);
up_enable_irq(priv->irq);
return ret;
@@ -2168,7 +2172,7 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
{
FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
- avdbg("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0);
+ ainfo("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0);
if (enable)
{
@@ -2215,7 +2219,7 @@ static void adc_ioc_enable_tvref_register(FAR struct adc_dev_s *dev,
stm32_modifyreg32(STM32_ADC_CCR, ADC_CCR_TSVREFE, 0);
}
- avdbg("STM32_ADC_CCR value: 0x%08x\n", getreg32(STM32_ADC_CCR));
+ ainfo("STM32_ADC_CCR value: 0x%08x\n", getreg32(STM32_ADC_CCR));
}
#endif
@@ -2259,7 +2263,7 @@ static int adc_ioc_change_sleep_between_opers(FAR struct adc_dev_s *dev,
break;
default:
- avdbg("unknown cmd: %d\n", cmd);
+ ainfo("unknown cmd: %d\n", cmd);
break;
}
@@ -2432,7 +2436,7 @@ static int adc_ioc_change_ints(FAR struct adc_dev_s *dev, int cmd, bool arg)
break;
default:
- avdbg("unknown cmd: %d\n", cmd);
+ ainfo("unknown cmd: %d\n", cmd);
break;
}
@@ -2676,7 +2680,7 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
#endif /* CONFIG_STM32_STM32L15XX */
default:
- adbg("ERROR: Unknown cmd: %d\n", cmd);
+ aerr("ERROR: Unknown cmd: %d\n", cmd);
ret = -ENOTTY;
break;
}
@@ -2714,12 +2718,12 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
if ((regval & ADC_ISR_AWD) != 0)
{
- alldbg("WARNING: Analog Watchdog, Value converted out of range!\n");
+ awarn("WARNING: Analog Watchdog, Value converted out of range!\n");
}
if ((regval & ADC_ISR_OVR) != 0)
{
- alldbg("WARNING: Overrun has occurred!\n");
+ awarn("WARNING: Overrun has occurred!\n");
}
/* EOC: End of conversion */
@@ -2781,7 +2785,7 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
*
****************************************************************************/
-#ifdef CONFIG_STM32_STM32L15XX
+#if defined(STM32_IRQ_ADC1)
static int adc1_interrupt(int irq, FAR void *context)
{
adc_interrupt(&g_adcdev1);
@@ -2802,8 +2806,7 @@ static int adc1_interrupt(int irq, FAR void *context)
*
****************************************************************************/
-#if (defined(CONFIG_STM32_STM32F10XX) || \
- defined(CONFIG_STM32_STM32F30XX)) && \
+#if defined(STM32_IRQ_ADC12) && \
(defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2))
static int adc12_interrupt(int irq, FAR void *context)
{
@@ -2831,8 +2834,7 @@ static int adc12_interrupt(int irq, FAR void *context)
*
****************************************************************************/
-#if (defined(CONFIG_STM32_STM32F10XX) || \
- defined(CONFIG_STM32_STM32F30XX)) && defined(CONFIG_STM32_ADC3)
+#if defined(STM32_IRQ_ADC3) && defined(CONFIG_STM32_ADC3)
static int adc3_interrupt(int irq, FAR void *context)
{
adc_interrupt(&g_adcdev3);
@@ -2853,13 +2855,10 @@ static int adc3_interrupt(int irq, FAR void *context)
*
****************************************************************************/
-#if defined(CONFIG_STM32_STM32F30XX) && defined(CONFIG_STM32_ADC4)
+#if defined(STM32_IRQ_ADC4) && defined(CONFIG_STM32_ADC4)
static int adc4_interrupt(int irq, FAR void *context)
{
-#ifdef CONFIG_STM32_ADC4
adc_interrupt(&g_adcdev4);
-#endif
-
return OK;
}
#endif
@@ -2876,7 +2875,7 @@ static int adc4_interrupt(int irq, FAR void *context)
*
****************************************************************************/
-#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+#if defined(STM32_IRQ_ADC)
static int adc123_interrupt(int irq, FAR void *context)
{
#ifdef CONFIG_STM32_ADC1
@@ -2984,36 +2983,36 @@ struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
FAR struct adc_dev_s *dev;
FAR struct stm32_dev_s *priv;
- avdbg("intf: %d cchannels: %d\n", intf, cchannels);
+ ainfo("intf: %d cchannels: %d\n", intf, cchannels);
switch (intf)
{
#ifdef CONFIG_STM32_ADC1
case 1:
- avdbg("ADC1 selected\n");
+ ainfo("ADC1 selected\n");
dev = &g_adcdev1;
break;
#endif
#ifdef CONFIG_STM32_ADC2
case 2:
- avdbg("ADC2 selected\n");
+ ainfo("ADC2 selected\n");
dev = &g_adcdev2;
break;
#endif
#ifdef CONFIG_STM32_ADC3
case 3:
- avdbg("ADC3 selected\n");
+ ainfo("ADC3 selected\n");
dev = &g_adcdev3;
break;
#endif
#ifdef CONFIG_STM32_ADC4
case 4:
- avdbg("ADC4 selected\n");
+ ainfo("ADC4 selected\n");
dev = &g_adcdev4;
break;
#endif
default:
- adbg("No ADC interface defined\n");
+ aerr("ERROR: No ADC interface defined\n");
return NULL;
}
diff --git a/arch/arm/src/stm32/stm32_allocateheap.c b/arch/arm/src/stm32/stm32_allocateheap.c
index 8a844b6d22d21f7fc357f921d2bbd202ef0ade2c..a222253af5e04379f842657f6d5587c969a9c2d6 100644
--- a/arch/arm/src/stm32/stm32_allocateheap.c
+++ b/arch/arm/src/stm32/stm32_allocateheap.c
@@ -41,6 +41,7 @@
#include
#include
+#include
#include
#include
@@ -438,7 +439,7 @@
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_HEAP
+#ifdef CONFIG_HEAP_COLORATION
static inline void up_heap_color(FAR void *start, size_t size)
{
memset(start, HEAP_COLOR, size);
diff --git a/arch/arm/src/stm32/stm32_bbsram.c b/arch/arm/src/stm32/stm32_bbsram.c
index 507f5a4d4a22b5e136fd1f3b7b1f5980b9da843d..e35f5e05a7ec83189cc95f5554a1dc7291d558c4 100644
--- a/arch/arm/src/stm32/stm32_bbsram.c
+++ b/arch/arm/src/stm32/stm32_bbsram.c
@@ -75,6 +75,10 @@
#define MAX_OPENCNT (255) /* Limit of uint8_t */
+#ifndef CONFIG_DEBUG_INFO
+# undef CONFIG_BBSRAM_DEBUG
+#endif
+
#if defined(CONFIG_BBSRAM_DEBUG)
# define BBSRAM_DEBUG_READ() stm32_bbsram_rd()
# define BBSRAM_DUMP(p,s) stm32_bbsram_dump(p,s)
@@ -183,15 +187,15 @@ static void stm32_bbsram_rd(void)
static void stm32_bbsram_dump(FAR struct bbsramfh_s *bbf, char *op)
{
BBSRAM_DEBUG_READ();
- lldbg("%s:\n", op);
- lldbg(" File Address:0x%8x\n", bbf);
- lldbg(" crc:0x%8x\n", bbf->crc);
- lldbg(" fileno:%d\n", (int) bbf->fileno);
- lldbg(" dirty:%d\n", (int) bbf->dirty);
- lldbg(" length:%d\n", (int) bbf->len);
- lldbg(" time:%ld:%ld\n", bbf->lastwrite.tv_sec, bbf->lastwrite.tv_nsec);
- lldbg(" data: 0x%2x 0x%2x 0x%2x 0x%2x 0x%2x\n",
- bbf->data[0], bbf->data[1], bbf->data[2], bbf->data[3], bbf->data[4]);
+ _info("%s:\n", op);
+ _info(" File Address:0x%8x\n", bbf);
+ _info(" crc:0x%8x\n", bbf->crc);
+ _info(" fileno:%d\n", (int) bbf->fileno);
+ _info(" dirty:%d\n", (int) bbf->dirty);
+ _info(" length:%d\n", (int) bbf->len);
+ _info(" time:%ld:%ld\n", bbf->lastwrite.tv_sec, bbf->lastwrite.tv_nsec);
+ _info(" data: 0x%2x 0x%2x 0x%2x 0x%2x 0x%2x\n",
+ bbf->data[0], bbf->data[1], bbf->data[2], bbf->data[3], bbf->data[4]);
}
#endif
diff --git a/arch/arm/src/stm32/stm32_can.c b/arch/arm/src/stm32/stm32_can.c
index 8cb61decf14778fad1de5dd64b0803defa42196a..c8193f65f4048b96f54c9e4dd2382d5e305c3519 100644
--- a/arch/arm/src/stm32/stm32_can.c
+++ b/arch/arm/src/stm32/stm32_can.c
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/stm32/stm32_can.c
*
* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
@@ -34,7 +34,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
/****************************************************************************
* Included Files
@@ -81,23 +81,8 @@
#define CAN_BIT_QUANTA (CONFIG_CAN_TSEG1 + CONFIG_CAN_TSEG2 + 1)
-/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing CAN */
-
-#ifdef CONFIG_DEBUG_CAN
-# define candbg dbg
-# define canvdbg vdbg
-# define canlldbg lldbg
-# define canllvdbg llvdbg
-#else
-# define candbg(x...)
-# define canvdbg(x...)
-# define canlldbg(x...)
-# define canllvdbg(x...)
-#endif
-
-#if !defined(CONFIG_DEBUG) || !defined(CONFIG_DEBUG_CAN)
-# undef CONFIG_CAN_REGDEBUG
+#ifndef CONFIG_DEBUG_CAN_INFO
+# undef CONFIG_STM32_CAN_REGDEBUG
#endif
/****************************************************************************
@@ -121,50 +106,63 @@ struct stm32_can_s
/* CAN Register access */
-static uint32_t can_getreg(FAR struct stm32_can_s *priv, int offset);
-static uint32_t can_getfreg(FAR struct stm32_can_s *priv, int offset);
-static void can_putreg(FAR struct stm32_can_s *priv, int offset,
- uint32_t value);
-static void can_putfreg(FAR struct stm32_can_s *priv, int offset,
- uint32_t value);
-#ifdef CONFIG_CAN_REGDEBUG
-static void can_dumpctrlregs(FAR struct stm32_can_s *priv,
- FAR const char *msg);
-static void can_dumpmbregs(FAR struct stm32_can_s *priv,
- FAR const char *msg);
-static void can_dumpfiltregs(FAR struct stm32_can_s *priv,
- FAR const char *msg);
+static uint32_t stm32can_getreg(FAR struct stm32_can_s *priv, int offset);
+static uint32_t stm32can_getfreg(FAR struct stm32_can_s *priv, int offset);
+static void stm32can_putreg(FAR struct stm32_can_s *priv, int offset,
+ uint32_t value);
+static void stm32can_putfreg(FAR struct stm32_can_s *priv, int offset,
+ uint32_t value);
+#ifdef CONFIG_STM32_CAN_REGDEBUG
+static void stm32can_dumpctrlregs(FAR struct stm32_can_s *priv,
+ FAR const char *msg);
+static void stm32can_dumpmbregs(FAR struct stm32_can_s *priv,
+ FAR const char *msg);
+static void stm32can_dumpfiltregs(FAR struct stm32_can_s *priv,
+ FAR const char *msg);
#else
-# define can_dumpctrlregs(priv,msg)
-# define can_dumpmbregs(priv,msg)
-# define can_dumpfiltregs(priv,msg)
+# define stm32can_dumpctrlregs(priv,msg)
+# define stm32can_dumpmbregs(priv,msg)
+# define stm32can_dumpfiltregs(priv,msg)
#endif
+/* Filtering (todo) */
+
+static int stm32l4can_addextfilter(FAR struct stm32l4_can_s *priv,
+ FAR struct canioc_extfilter_s *arg);
+static int stm32l4can_delextfilter(FAR struct stm32l4_can_s *priv,
+ int arg);
+static int stm32l4can_addstdfilter(FAR struct stm32l4_can_s *priv,
+ FAR struct canioc_stdfilter_s *arg);
+static int stm32l4can_delstdfilter(FAR struct stm32l4_can_s *priv,
+ int arg);
+
/* CAN driver methods */
-static void can_reset(FAR struct can_dev_s *dev);
-static int can_setup(FAR struct can_dev_s *dev);
-static void can_shutdown(FAR struct can_dev_s *dev);
-static void can_rxint(FAR struct can_dev_s *dev, bool enable);
-static void can_txint(FAR struct can_dev_s *dev, bool enable);
-static int can_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg);
-static int can_remoterequest(FAR struct can_dev_s *dev, uint16_t id);
-static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg);
-static bool can_txready(FAR struct can_dev_s *dev);
-static bool can_txempty(FAR struct can_dev_s *dev);
+static void stm32can_reset(FAR struct can_dev_s *dev);
+static int stm32can_setup(FAR struct can_dev_s *dev);
+static void stm32can_shutdown(FAR struct can_dev_s *dev);
+static void stm32can_rxint(FAR struct can_dev_s *dev, bool enable);
+static void stm32can_txint(FAR struct can_dev_s *dev, bool enable);
+static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd,
+ unsigned long arg);
+static int stm32can_remoterequest(FAR struct can_dev_s *dev, uint16_t id);
+static int stm32can_send(FAR struct can_dev_s *dev,
+ FAR struct can_msg_s *msg);
+static bool stm32can_txready(FAR struct can_dev_s *dev);
+static bool stm32can_txempty(FAR struct can_dev_s *dev);
/* CAN interrupt handling */
-static int can_rxinterrupt(int irq, FAR void *context, int rxmb);
-static int can_rx0interrupt(int irq, FAR void *context);
-static int can_rx1interrupt(int irq, FAR void *context);
-static int can_txinterrupt(int irq, FAR void *context);
+static int stm32can_rxinterrupt(int irq, FAR void *context, int rxmb);
+static int stm32can_rx0interrupt(int irq, FAR void *context);
+static int stm32can_rx1interrupt(int irq, FAR void *context);
+static int stm32can_txinterrupt(int irq, FAR void *context);
/* Initialization */
-static int can_bittiming(FAR struct stm32_can_s *priv);
-static int can_cellinit(FAR struct stm32_can_s *priv);
-static int can_filterinit(FAR struct stm32_can_s *priv);
+static int stm32can_bittiming(FAR struct stm32_can_s *priv);
+static int stm32can_cellinit(FAR struct stm32_can_s *priv);
+static int stm32can_filterinit(FAR struct stm32_can_s *priv);
/****************************************************************************
* Private Data
@@ -172,16 +170,16 @@ static int can_filterinit(FAR struct stm32_can_s *priv);
static const struct can_ops_s g_canops =
{
- .co_reset = can_reset,
- .co_setup = can_setup,
- .co_shutdown = can_shutdown,
- .co_rxint = can_rxint,
- .co_txint = can_txint,
- .co_ioctl = can_ioctl,
- .co_remoterequest = can_remoterequest,
- .co_send = can_send,
- .co_txready = can_txready,
- .co_txempty = can_txempty,
+ .co_reset = stm32can_reset,
+ .co_setup = stm32can_setup,
+ .co_shutdown = stm32can_shutdown,
+ .co_rxint = stm32can_rxint,
+ .co_txint = stm32can_txint,
+ .co_ioctl = stm32can_ioctl,
+ .co_remoterequest = stm32can_remoterequest,
+ .co_send = stm32can_send,
+ .co_txready = stm32can_txready,
+ .co_txempty = stm32can_txempty,
};
#ifdef CONFIG_STM32_CAN1
@@ -235,8 +233,8 @@ static struct can_dev_s g_can2dev =
****************************************************************************/
/****************************************************************************
- * Name: can_getreg
- * Name: can_getfreg
+ * Name: stm32can_getreg
+ * Name: stm32can_getfreg
*
* Description:
* Read the value of a CAN register or filter block register.
@@ -249,8 +247,8 @@ static struct can_dev_s g_can2dev =
*
****************************************************************************/
-#ifdef CONFIG_CAN_REGDEBUG
-static uint32_t can_vgetreg(uint32_t addr)
+#ifdef CONFIG_STM32_CAN_REGDEBUG
+static uint32_t stm32can_vgetreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
static uint32_t preval = 0;
@@ -270,7 +268,7 @@ static uint32_t can_vgetreg(uint32_t addr)
{
if (count == 4)
{
- lldbg("...\n");
+ caninfo("...\n");
}
return val;
@@ -287,7 +285,7 @@ static uint32_t can_vgetreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ caninfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -299,27 +297,27 @@ static uint32_t can_vgetreg(uint32_t addr)
/* Show the register value read */
- lldbg("%08x->%08x\n", addr, val);
+ caninfo("%08x->%08x\n", addr, val);
return val;
}
-static uint32_t can_getreg(FAR struct stm32_can_s *priv, int offset)
+static uint32_t stm32can_getreg(FAR struct stm32_can_s *priv, int offset)
{
- return can_vgetreg(priv->base + offset);
+ return stm32can_vgetreg(priv->base + offset);
}
-static uint32_t can_getfreg(FAR struct stm32_can_s *priv, int offset)
+static uint32_t stm32can_getfreg(FAR struct stm32_can_s *priv, int offset)
{
- return can_vgetreg(priv->fbase + offset);
+ return stm32can_vgetreg(priv->fbase + offset);
}
#else
-static uint32_t can_getreg(FAR struct stm32_can_s *priv, int offset)
+static uint32_t stm32can_getreg(FAR struct stm32_can_s *priv, int offset)
{
return getreg32(priv->base + offset);
}
-static uint32_t can_getfreg(FAR struct stm32_can_s *priv, int offset)
+static uint32_t stm32can_getfreg(FAR struct stm32_can_s *priv, int offset)
{
return getreg32(priv->fbase + offset);
}
@@ -327,8 +325,8 @@ static uint32_t can_getfreg(FAR struct stm32_can_s *priv, int offset)
#endif
/****************************************************************************
- * Name: can_putreg
- * Name: can_putfreg
+ * Name: stm32can_putreg
+ * Name: stm32can_putfreg
*
* Description:
* Set the value of a CAN register or filter block register.
@@ -343,47 +341,47 @@ static uint32_t can_getfreg(FAR struct stm32_can_s *priv, int offset)
*
****************************************************************************/
-#ifdef CONFIG_CAN_REGDEBUG
-static void can_vputreg(uint32_t addr, uint32_t value)
+#ifdef CONFIG_STM32_CAN_REGDEBUG
+static void stm32can_vputreg(uint32_t addr, uint32_t value)
{
/* Show the register value being written */
- lldbg("%08x<-%08x\n", addr, value);
+ caninfo("%08x<-%08x\n", addr, value);
/* Write the value */
putreg32(value, addr);
}
-static void can_putreg(FAR struct stm32_can_s *priv, int offset,
- uint32_t value)
+static void stm32can_putreg(FAR struct stm32_can_s *priv, int offset,
+ uint32_t value)
{
- can_vputreg(priv->base + offset, value);
+ stm32can_vputreg(priv->base + offset, value);
}
-static void can_putfreg(FAR struct stm32_can_s *priv, int offset,
- uint32_t value)
+static void stm32can_putfreg(FAR struct stm32_can_s *priv, int offset,
+ uint32_t value)
{
- can_vputreg(priv->fbase + offset, value);
+ stm32can_vputreg(priv->fbase + offset, value);
}
#else
-static void can_putreg(FAR struct stm32_can_s *priv, int offset,
- uint32_t value)
+static void stm32can_putreg(FAR struct stm32_can_s *priv, int offset,
+ uint32_t value)
{
putreg32(value, priv->base + offset);
}
-static void can_putfreg(FAR struct stm32_can_s *priv, int offset,
- uint32_t value)
+static void stm32can_putfreg(FAR struct stm32_can_s *priv, int offset,
+ uint32_t value)
{
putreg32(value, priv->fbase + offset);
}
#endif
/****************************************************************************
- * Name: can_dumpctrlregs
+ * Name: stm32can_dumpctrlregs
*
* Description:
* Dump the contents of all CAN control registers
@@ -396,39 +394,39 @@ static void can_putfreg(FAR struct stm32_can_s *priv, int offset,
*
****************************************************************************/
-#ifdef CONFIG_CAN_REGDEBUG
-static void can_dumpctrlregs(FAR struct stm32_can_s *priv,
+#ifdef CONFIG_STM32_CAN_REGDEBUG
+static void stm32can_dumpctrlregs(FAR struct stm32_can_s *priv,
FAR const char *msg)
{
if (msg)
{
- canlldbg("Control Registers: %s\n", msg);
+ caninfo("Control Registers: %s\n", msg);
}
else
{
- canlldbg("Control Registers:\n");
+ caninfo("Control Registers:\n");
}
/* CAN control and status registers */
- lldbg(" MCR: %08x MSR: %08x TSR: %08x\n",
- getreg32(priv->base + STM32_CAN_MCR_OFFSET),
- getreg32(priv->base + STM32_CAN_MSR_OFFSET),
- getreg32(priv->base + STM32_CAN_TSR_OFFSET));
+ caninfo(" MCR: %08x MSR: %08x TSR: %08x\n",
+ getreg32(priv->base + STM32_CAN_MCR_OFFSET),
+ getreg32(priv->base + STM32_CAN_MSR_OFFSET),
+ getreg32(priv->base + STM32_CAN_TSR_OFFSET));
- lldbg(" RF0R: %08x RF1R: %08x\n",
- getreg32(priv->base + STM32_CAN_RF0R_OFFSET),
- getreg32(priv->base + STM32_CAN_RF1R_OFFSET));
+ caninfo(" RF0R: %08x RF1R: %08x\n",
+ getreg32(priv->base + STM32_CAN_RF0R_OFFSET),
+ getreg32(priv->base + STM32_CAN_RF1R_OFFSET));
- lldbg(" IER: %08x ESR: %08x BTR: %08x\n",
- getreg32(priv->base + STM32_CAN_IER_OFFSET),
- getreg32(priv->base + STM32_CAN_ESR_OFFSET),
- getreg32(priv->base + STM32_CAN_BTR_OFFSET));
+ caninfo(" IER: %08x ESR: %08x BTR: %08x\n",
+ getreg32(priv->base + STM32_CAN_IER_OFFSET),
+ getreg32(priv->base + STM32_CAN_ESR_OFFSET),
+ getreg32(priv->base + STM32_CAN_BTR_OFFSET));
}
#endif
/****************************************************************************
- * Name: can_dumpmbregs
+ * Name: stm32can_dumpmbregs
*
* Description:
* Dump the contents of all CAN mailbox registers
@@ -441,55 +439,55 @@ static void can_dumpctrlregs(FAR struct stm32_can_s *priv,
*
****************************************************************************/
-#ifdef CONFIG_CAN_REGDEBUG
-static void can_dumpmbregs(FAR struct stm32_can_s *priv,
+#ifdef CONFIG_STM32_CAN_REGDEBUG
+static void stm32can_dumpmbregs(FAR struct stm32_can_s *priv,
FAR const char *msg)
{
if (msg)
{
- canlldbg("Mailbox Registers: %s\n", msg);
+ caninfo("Mailbox Registers: %s\n", msg);
}
else
{
- canlldbg("Mailbox Registers:\n");
+ caninfo("Mailbox Registers:\n");
}
/* CAN mailbox registers (3 TX and 2 RX) */
- lldbg(" TI0R: %08x TDT0R: %08x TDL0R: %08x TDH0R: %08x\n",
- getreg32(priv->base + STM32_CAN_TI0R_OFFSET),
- getreg32(priv->base + STM32_CAN_TDT0R_OFFSET),
- getreg32(priv->base + STM32_CAN_TDL0R_OFFSET),
- getreg32(priv->base + STM32_CAN_TDH0R_OFFSET));
-
- lldbg(" TI1R: %08x TDT1R: %08x TDL1R: %08x TDH1R: %08x\n",
- getreg32(priv->base + STM32_CAN_TI1R_OFFSET),
- getreg32(priv->base + STM32_CAN_TDT1R_OFFSET),
- getreg32(priv->base + STM32_CAN_TDL1R_OFFSET),
- getreg32(priv->base + STM32_CAN_TDH1R_OFFSET));
-
- lldbg(" TI2R: %08x TDT2R: %08x TDL2R: %08x TDH2R: %08x\n",
- getreg32(priv->base + STM32_CAN_TI2R_OFFSET),
- getreg32(priv->base + STM32_CAN_TDT2R_OFFSET),
- getreg32(priv->base + STM32_CAN_TDL2R_OFFSET),
- getreg32(priv->base + STM32_CAN_TDH2R_OFFSET));
-
- lldbg(" RI0R: %08x RDT0R: %08x RDL0R: %08x RDH0R: %08x\n",
- getreg32(priv->base + STM32_CAN_RI0R_OFFSET),
- getreg32(priv->base + STM32_CAN_RDT0R_OFFSET),
- getreg32(priv->base + STM32_CAN_RDL0R_OFFSET),
- getreg32(priv->base + STM32_CAN_RDH0R_OFFSET));
-
- lldbg(" RI1R: %08x RDT1R: %08x RDL1R: %08x RDH1R: %08x\n",
- getreg32(priv->base + STM32_CAN_RI1R_OFFSET),
- getreg32(priv->base + STM32_CAN_RDT1R_OFFSET),
- getreg32(priv->base + STM32_CAN_RDL1R_OFFSET),
- getreg32(priv->base + STM32_CAN_RDH1R_OFFSET));
+ caninfo(" TI0R: %08x TDT0R: %08x TDL0R: %08x TDH0R: %08x\n",
+ getreg32(priv->base + STM32_CAN_TI0R_OFFSET),
+ getreg32(priv->base + STM32_CAN_TDT0R_OFFSET),
+ getreg32(priv->base + STM32_CAN_TDL0R_OFFSET),
+ getreg32(priv->base + STM32_CAN_TDH0R_OFFSET));
+
+ caninfo(" TI1R: %08x TDT1R: %08x TDL1R: %08x TDH1R: %08x\n",
+ getreg32(priv->base + STM32_CAN_TI1R_OFFSET),
+ getreg32(priv->base + STM32_CAN_TDT1R_OFFSET),
+ getreg32(priv->base + STM32_CAN_TDL1R_OFFSET),
+ getreg32(priv->base + STM32_CAN_TDH1R_OFFSET));
+
+ caninfo(" TI2R: %08x TDT2R: %08x TDL2R: %08x TDH2R: %08x\n",
+ getreg32(priv->base + STM32_CAN_TI2R_OFFSET),
+ getreg32(priv->base + STM32_CAN_TDT2R_OFFSET),
+ getreg32(priv->base + STM32_CAN_TDL2R_OFFSET),
+ getreg32(priv->base + STM32_CAN_TDH2R_OFFSET));
+
+ caninfo(" RI0R: %08x RDT0R: %08x RDL0R: %08x RDH0R: %08x\n",
+ getreg32(priv->base + STM32_CAN_RI0R_OFFSET),
+ getreg32(priv->base + STM32_CAN_RDT0R_OFFSET),
+ getreg32(priv->base + STM32_CAN_RDL0R_OFFSET),
+ getreg32(priv->base + STM32_CAN_RDH0R_OFFSET));
+
+ caninfo(" RI1R: %08x RDT1R: %08x RDL1R: %08x RDH1R: %08x\n",
+ getreg32(priv->base + STM32_CAN_RI1R_OFFSET),
+ getreg32(priv->base + STM32_CAN_RDT1R_OFFSET),
+ getreg32(priv->base + STM32_CAN_RDL1R_OFFSET),
+ getreg32(priv->base + STM32_CAN_RDH1R_OFFSET));
}
#endif
/****************************************************************************
- * Name: can_dumpfiltregs
+ * Name: stm32can_dumpfiltregs
*
* Description:
* Dump the contents of all CAN filter registers
@@ -502,43 +500,43 @@ static void can_dumpmbregs(FAR struct stm32_can_s *priv,
*
****************************************************************************/
-#ifdef CONFIG_CAN_REGDEBUG
-static void can_dumpfiltregs(FAR struct stm32_can_s *priv,
+#ifdef CONFIG_STM32_CAN_REGDEBUG
+static void stm32can_dumpfiltregs(FAR struct stm32_can_s *priv,
FAR const char *msg)
{
int i;
if (msg)
{
- canlldbg("Filter Registers: %s\n", msg);
+ caninfo("Filter Registers: %s\n", msg);
}
else
{
- canlldbg("Filter Registers:\n");
+ caninfo("Filter Registers:\n");
}
- lldbg(" FMR: %08x FM1R: %08x FS1R: %08x FFA1R: %08x FA1R: %08x\n",
- getreg32(priv->base + STM32_CAN_FMR_OFFSET),
- getreg32(priv->base + STM32_CAN_FM1R_OFFSET),
- getreg32(priv->base + STM32_CAN_FS1R_OFFSET),
- getreg32(priv->base + STM32_CAN_FFA1R_OFFSET),
- getreg32(priv->base + STM32_CAN_FA1R_OFFSET));
+ caninfo(" FMR: %08x FM1R: %08x FS1R: %08x FFA1R: %08x FA1R: %08x\n",
+ getreg32(priv->base + STM32_CAN_FMR_OFFSET),
+ getreg32(priv->base + STM32_CAN_FM1R_OFFSET),
+ getreg32(priv->base + STM32_CAN_FS1R_OFFSET),
+ getreg32(priv->base + STM32_CAN_FFA1R_OFFSET),
+ getreg32(priv->base + STM32_CAN_FA1R_OFFSET));
for (i = 0; i < CAN_NFILTERS; i++)
{
- lldbg(" F%dR1: %08x F%dR2: %08x\n",
- i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 1)),
- i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 2)));
+ caninfo(" F%dR1: %08x F%dR2: %08x\n",
+ i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 1)),
+ i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 2)));
}
}
#endif
/****************************************************************************
- * Name: can_reset
+ * Name: stm32can_reset
*
* Description:
* Reset the CAN device. Called early to initialize the hardware. This
- * function is called, before can_setup() and on error conditions.
+ * function is called, before stm32can_setup() and on error conditions.
*
* Input Parameters:
* dev - An instance of the "upper half" can driver state structure.
@@ -548,14 +546,14 @@ static void can_dumpfiltregs(FAR struct stm32_can_s *priv,
*
****************************************************************************/
-static void can_reset(FAR struct can_dev_s *dev)
+static void stm32can_reset(FAR struct can_dev_s *dev)
{
FAR struct stm32_can_s *priv = dev->cd_priv;
uint32_t regval;
uint32_t regbit = 0;
irqstate_t flags;
- canllvdbg("CAN%d\n", priv->port);
+ caninfo("CAN%d\n", priv->port);
/* Get the bits in the AHB1RSTR register needed to reset this CAN device */
@@ -574,7 +572,7 @@ static void can_reset(FAR struct can_dev_s *dev)
else
#endif
{
- canlldbg("Unsupported port %d\n", priv->port);
+ canerr("ERROR: Unsupported port %d\n", priv->port);
return;
}
@@ -596,7 +594,7 @@ static void can_reset(FAR struct can_dev_s *dev)
}
/****************************************************************************
- * Name: can_setup
+ * Name: stm32can_setup
*
* Description:
* Configure the CAN. This method is called the first time that the CAN
@@ -612,61 +610,62 @@ static void can_reset(FAR struct can_dev_s *dev)
*
****************************************************************************/
-static int can_setup(FAR struct can_dev_s *dev)
+static int stm32can_setup(FAR struct can_dev_s *dev)
{
FAR struct stm32_can_s *priv = dev->cd_priv;
int ret;
- canllvdbg("CAN%d RX0 irq: %d RX1 irq: %d TX irq: %d\n",
- priv->port, priv->canrx[0], priv->canrx[1], priv->cantx);
+ caninfo("CAN%d RX0 irq: %d RX1 irq: %d TX irq: %d\n",
+ priv->port, priv->canrx[0], priv->canrx[1], priv->cantx);
/* CAN cell initialization */
- ret = can_cellinit(priv);
+ ret = stm32can_cellinit(priv);
if (ret < 0)
{
- canlldbg("CAN%d cell initialization failed: %d\n", priv->port, ret);
+ canerr("ERROR: CAN%d cell initialization failed: %d\n", priv->port, ret);
return ret;
}
- can_dumpctrlregs(priv, "After cell initialization");
- can_dumpmbregs(priv, NULL);
+ stm32can_dumpctrlregs(priv, "After cell initialization");
+ stm32can_dumpmbregs(priv, NULL);
/* CAN filter initialization */
- ret = can_filterinit(priv);
+ ret = stm32can_filterinit(priv);
if (ret < 0)
{
- canlldbg("CAN%d filter initialization failed: %d\n", priv->port, ret);
+ canerr("ERROR: CAN%d filter initialization failed: %d\n", priv->port, ret);
return ret;
}
- can_dumpfiltregs(priv, "After filter initialization");
+
+ stm32can_dumpfiltregs(priv, "After filter initialization");
/* Attach the CAN RX FIFO 0/1 interrupts and TX interrupts.
* The others are not used.
*/
- ret = irq_attach(priv->canrx[0], can_rx0interrupt);
+ ret = irq_attach(priv->canrx[0], stm32can_rx0interrupt);
if (ret < 0)
{
- canlldbg("Failed to attach CAN%d RX0 IRQ (%d)",
- priv->port, priv->canrx[0]);
+ canerr(ERROR: "Failed to attach CAN%d RX0 IRQ (%d)",
+ priv->port, priv->canrx[0]);
return ret;
}
- ret = irq_attach(priv->canrx[1], can_rx1interrupt);
+ ret = irq_attach(priv->canrx[1], stm32can_rx1interrupt);
if (ret < 0)
{
- canlldbg("Failed to attach CAN%d RX1 IRQ (%d)",
- priv->port, priv->canrx[1]);
+ canerr("ERROR: Failed to attach CAN%d RX1 IRQ (%d)",
+ priv->port, priv->canrx[1]);
return ret;
}
- ret = irq_attach(priv->cantx, can_txinterrupt);
+ ret = irq_attach(priv->cantx, stm32can_txinterrupt);
if (ret < 0)
{
- canlldbg("Failed to attach CAN%d TX IRQ (%d)",
- priv->port, priv->cantx);
+ canerr("ERROR: Failed to attach CAN%d TX IRQ (%d)",
+ priv->port, priv->cantx);
return ret;
}
@@ -682,7 +681,7 @@ static int can_setup(FAR struct can_dev_s *dev)
}
/****************************************************************************
- * Name: can_shutdown
+ * Name: stm32can_shutdown
*
* Description:
* Disable the CAN. This method is called when the CAN device is closed.
@@ -696,11 +695,11 @@ static int can_setup(FAR struct can_dev_s *dev)
*
****************************************************************************/
-static void can_shutdown(FAR struct can_dev_s *dev)
+static void stm32can_shutdown(FAR struct can_dev_s *dev)
{
FAR struct stm32_can_s *priv = dev->cd_priv;
- canllvdbg("CAN%d\n", priv->port);
+ caninfo("CAN%d\n", priv->port);
/* Disable the RX FIFO 0/1 and TX interrupts */
@@ -716,11 +715,11 @@ static void can_shutdown(FAR struct can_dev_s *dev)
/* And reset the hardware */
- can_reset(dev);
+ stm32can_reset(dev);
}
/****************************************************************************
- * Name: can_rxint
+ * Name: stm32can_rxint
*
* Description:
* Call to enable or disable RX interrupts.
@@ -733,16 +732,16 @@ static void can_shutdown(FAR struct can_dev_s *dev)
*
****************************************************************************/
-static void can_rxint(FAR struct can_dev_s *dev, bool enable)
+static void stm32can_rxint(FAR struct can_dev_s *dev, bool enable)
{
FAR struct stm32_can_s *priv = dev->cd_priv;
uint32_t regval;
- canllvdbg("CAN%d enable: %d\n", priv->port, enable);
+ caninfo("CAN%d enable: %d\n", priv->port, enable);
/* Enable/disable the FIFO 0/1 message pending interrupt */
- regval = can_getreg(priv, STM32_CAN_IER_OFFSET);
+ regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET);
if (enable)
{
regval |= CAN_IER_FMPIE0 | CAN_IER_FMPIE1;
@@ -751,11 +750,11 @@ static void can_rxint(FAR struct can_dev_s *dev, bool enable)
{
regval &= ~(CAN_IER_FMPIE0 | CAN_IER_FMPIE1);
}
- can_putreg(priv, STM32_CAN_IER_OFFSET, regval);
+ stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval);
}
/****************************************************************************
- * Name: can_txint
+ * Name: stm32can_txint
*
* Description:
* Call to enable or disable TX interrupts.
@@ -768,25 +767,25 @@ static void can_rxint(FAR struct can_dev_s *dev, bool enable)
*
****************************************************************************/
-static void can_txint(FAR struct can_dev_s *dev, bool enable)
+static void stm32can_txint(FAR struct can_dev_s *dev, bool enable)
{
FAR struct stm32_can_s *priv = dev->cd_priv;
uint32_t regval;
- canllvdbg("CAN%d enable: %d\n", priv->port, enable);
+ caninfo("CAN%d enable: %d\n", priv->port, enable);
/* Support only disabling the transmit mailbox interrupt */
if (!enable)
{
- regval = can_getreg(priv, STM32_CAN_IER_OFFSET);
+ regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET);
regval &= ~CAN_IER_TMEIE;
- can_putreg(priv, STM32_CAN_IER_OFFSET, regval);
+ stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval);
}
}
/****************************************************************************
- * Name: can_ioctl
+ * Name: stm32can_ioctl
*
* Description:
* All ioctl calls will be routed through this method
@@ -799,15 +798,302 @@ static void can_txint(FAR struct can_dev_s *dev, bool enable)
*
****************************************************************************/
-static int can_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg)
+static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd,
+ unsigned long arg)
{
- /* No CAN ioctls are supported */
+ FAR struct stm32_can_s *priv;
+ int ret = -ENOTTY;
- return -ENOTTY;
+ caninfo("cmd=%04x arg=%lu\n", cmd, arg);
+
+ DEBUGASSERT(dev && dev->cd_priv);
+ priv = dev->cd_priv;
+
+ /* Handle the command */
+
+ switch (cmd)
+ {
+ /* CANIOC_GET_BITTIMING:
+ * Description: Return the current bit timing settings
+ * Argument: A pointer to a write-able instance of struct
+ * canioc_bittiming_s in which current bit timing
+ * values will be returned.
+ * Returned Value: Zero (OK) is returned on success. Otherwise -1
+ * (ERROR) is returned with the errno variable set
+ * to indicate the nature of the error.
+ * Dependencies: None
+ */
+
+ case CANIOC_GET_BITTIMING:
+ {
+ FAR struct canioc_bittiming_s *bt =
+ (FAR struct canioc_bittiming_s *)arg;
+ uint32_t regval;
+ uint32_t brp;
+
+ DEBUGASSERT(bt != NULL);
+ regval = stm32can_getreg(priv, STM32_CAN_BTR_OFFSET);
+ bt->bt_sjw = ((regval & CAN_BTR_SJW_MASK) >> CAN_BTR_SJW_SHIFT) + 1;
+ bt->bt_tseg1 = ((regval & CAN_BTR_TS1_MASK) >> CAN_BTR_TS1_SHIFT) + 1;
+ bt->bt_tseg2 = ((regval & CAN_BTR_TS2_MASK) >> CAN_BTR_TS2_SHIFT) + 1;
+
+ brp = ((regval & CAN_BTR_BRP_MASK) >> CAN_BTR_BRP_SHIFT) + 1;
+ bt->bt_baud = STM32_PCLK1_FREQUENCY /
+ (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1));
+ ret = OK;
+ }
+ break;
+
+ /* CANIOC_SET_BITTIMING:
+ * Description: Set new current bit timing values
+ * Argument: A pointer to a read-able instance of struct
+ * canioc_bittiming_s in which the new bit timing
+ * values are provided.
+ * Returned Value: Zero (OK) is returned on success. Otherwise -1
+ * (ERROR)is returned with the errno variable set
+ * to indicate thenature of the error.
+ * Dependencies: None
+ *
+ * REVISIT: There is probably a limitation here: If there are multiple
+ * threads trying to send CAN packets, when one of these threads
+ * reconfigures the bitrate, the MCAN hardware will be reset and the
+ * context of operation will be lost. Hence, this IOCTL can only safely
+ * be executed in quiescent time periods.
+ */
+
+ case CANIOC_SET_BITTIMING:
+ {
+ FAR const struct canioc_bittiming_s *bt =
+ (FAR const struct canioc_bittiming_s *)arg;
+ uint32_t brp;
+ uint32_t can_bit_quanta;
+ uint32_t tmp;
+ uint32_t regval;
+
+ DEBUGASSERT(bt != NULL);
+ DEBUGASSERT(bt->bt_baud < STM32_PCLK1_FREQUENCY);
+ DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 4);
+ DEBUGASSERT(bt->bt_tseg1 > 0 && bt->bt_tseg1 <= 16);
+ DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 8);
+
+ regval = stm32can_getreg(priv, STM32_CAN_BTR_OFFSET);
+
+ /* Extract bit timing data */
+ /* tmp is in clocks per bit time */
+
+ tmp = STM32_PCLK1_FREQUENCY / bt->bt_baud;
+
+ /* This value is dynamic as requested by user */
+
+ can_bit_quanta = bt->bt_tseg1 + bt->bt_tseg2 + 1;
+
+ if (tmp < can_bit_quanta)
+ {
+ /* This timing is not possible */
+
+ ret = -EINVAL;
+ }
+
+ /* Otherwise, nquanta is can_bit_quanta, ts1 and ts2 are
+ * provided by the user and we calculate brp to achieve
+ * can_bit_quanta quanta in the bit times
+ */
+
+ else
+ {
+ brp = (tmp + (can_bit_quanta/2)) / can_bit_quanta;
+ DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX);
+ }
+
+ caninfo("TS1: %d TS2: %d BRP: %d\n", bt->bt_tseg1, bt->bt_tseg2, brp);
+
+ /* Configure bit timing. */
+
+ regval &= ~(CAN_BTR_BRP_MASK | CAN_BTR_TS1_MASK | CAN_BTR_TS2_MASK | CAN_BTR_SJW_MASK);
+ regval |= ((brp - 1) << CAN_BTR_BRP_SHIFT) |
+ ((bt->bt_tseg1 - 1) << CAN_BTR_TS1_SHIFT) |
+ ((bt->bt_tseg2 - 1) << CAN_BTR_TS2_SHIFT) |
+ ((bt->bt_sjw - 1) << CAN_BTR_SJW_SHIFT);
+
+ /* Bit timing can only be configured in init mode. */
+
+ ret = stm32can_enterinitmode(priv);
+ if (ret != 0)
+ {
+ break;
+ }
+
+ stm32can_putreg(priv, STM32_CAN_BTR_OFFSET, regval);
+
+ ret = stm32can_exitinitmode(priv);
+
+ if (ret == 0)
+ {
+ priv->baud = STM32_PCLK1_FREQUENCY / (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1));
+ }
+ }
+ break;
+
+ /* CANIOC_GET_CONNMODES:
+ * Description: Get the current bus connection modes
+ * Argument: A pointer to a write-able instance of struct
+ * canioc_connmodes_s in which the new bus modes will
+ * be returned.
+ * Returned Value: Zero (OK) is returned on success. Otherwise -1
+ * (ERROR)is returned with the errno variable set
+ * to indicate the nature of the error.
+ * Dependencies: None
+ */
+
+ case CANIOC_GET_CONNMODES:
+ {
+ FAR struct canioc_connmodes_s *bm =
+ (FAR struct canioc_connmodes_s *)arg;
+ uint32_t regval;
+
+ DEBUGASSERT(bm != NULL);
+
+ regval = stm32can_getreg(priv, STM32_CAN_BTR_OFFSET);
+
+ bm->bm_loopback = ((regval & CAN_BTR_LBKM) == CAN_BTR_LBKM);
+ bm->bm_silent = ((regval & CAN_BTR_SILM) == CAN_BTR_SILM);
+ ret = OK;
+ break;
+ }
+
+ /* CANIOC_SET_CONNMODES:
+ * Description: Set new bus connection modes values
+ * Argument: A pointer to a read-able instance of struct
+ * canioc_connmodes_s in which the new bus modes
+ * are provided.
+ * Returned Value: Zero (OK) is returned on success. Otherwise -1
+ * (ERROR) is returned with the errno variable set
+ * to indicate the nature of the error.
+ * Dependencies: None
+ */
+
+ case CANIOC_SET_CONNMODES:
+ {
+ FAR struct canioc_connmodes_s *bm =
+ (FAR struct canioc_connmodes_s *)arg;
+ uint32_t regval;
+
+ DEBUGASSERT(bm != NULL);
+
+ regval = stm32can_getreg(priv, STM32_CAN_BTR_OFFSET);
+
+ if (bm->bm_loopback)
+ {
+ regval |= CAN_BTR_LBKM;
+ }
+ else
+ {
+ regval &= ~CAN_BTR_LBKM;
+ }
+
+ if (bm->bm_silent)
+ {
+ regval |= CAN_BTR_SILM;
+ }
+ else
+ {
+ regval &= ~CAN_BTR_SILM;
+ }
+
+ /* This register can only be configured in init mode. */
+
+ ret = stm32can_enterinitmode(priv);
+ if (ret != 0)
+ {
+ break;
+ }
+
+ stm32can_putreg(priv, STM32_CAN_BTR_OFFSET, regval);
+
+ ret = stm32can_exitinitmode(priv);
+ }
+ break;
+
+#ifdef CONFIG_CAN_EXTID
+ /* CANIOC_ADD_EXTFILTER:
+ * Description: Add an address filter for a extended 29 bit
+ * address.
+ * Argument: A reference to struct canioc_extfilter_s
+ * Returned Value: A non-negative filter ID is returned on success.
+ * Otherwise -1 (ERROR) is returned with the errno
+ * variable set to indicate the nature of the error.
+ */
+
+ case CANIOC_ADD_EXTFILTER:
+ {
+ DEBUGASSERT(arg != 0);
+ ret = stm32can_addextfilter(priv, (FAR struct canioc_extfilter_s *)arg);
+ }
+ break;
+
+ /* CANIOC_DEL_EXTFILTER:
+ * Description: Remove an address filter for a standard 29 bit
+ * address.
+ * Argument: The filter index previously returned by the
+ * CANIOC_ADD_EXTFILTER command
+ * Returned Value: Zero (OK) is returned on success. Otherwise -1
+ * (ERROR)is returned with the errno variable set
+ * to indicate the nature of the error.
+ */
+
+ case CANIOC_DEL_EXTFILTER:
+ {
+ DEBUGASSERT(arg <= priv->config->nextfilters);
+ ret = stm32can_delextfilter(priv, (int)arg);
+ }
+ break;
+#endif
+
+ /* CANIOC_ADD_STDFILTER:
+ * Description: Add an address filter for a standard 11 bit
+ * address.
+ * Argument: A reference to struct canioc_stdfilter_s
+ * Returned Value: A non-negative filter ID is returned on success.
+ * Otherwise -1 (ERROR) is returned with the errno
+ * variable set to indicate the nature of the error.
+ */
+
+ case CANIOC_ADD_STDFILTER:
+ {
+ DEBUGASSERT(arg != 0);
+ ret = stm32can_addstdfilter(priv, (FAR struct canioc_stdfilter_s *)arg);
+ }
+ break;
+
+ /* CANIOC_DEL_STDFILTER:
+ * Description: Remove an address filter for a standard 11 bit
+ * address.
+ * Argument: The filter index previously returned by the
+ * CANIOC_ADD_STDFILTER command
+ * Returned Value: Zero (OK) is returned on success. Otherwise -1
+ * (ERROR) is returned with the errno variable set
+ * to indicate the nature of the error.
+ */
+
+ case CANIOC_DEL_STDFILTER:
+ {
+ DEBUGASSERT(arg <= priv->config->nstdfilters);
+ ret = stm32can_delstdfilter(priv, (int)arg);
+ }
+ break;
+
+ /* Unsupported/unrecognized command */
+
+ default:
+ canerr("ERROR: Unrecognized command: %04x\n", cmd);
+ break;
+ }
+
+ return ret;
}
/****************************************************************************
- * Name: can_remoterequest
+ * Name: stm32can_remoterequest
*
* Description:
* Send a remote request
@@ -820,14 +1106,14 @@ static int can_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg)
*
****************************************************************************/
-static int can_remoterequest(FAR struct can_dev_s *dev, uint16_t id)
+static int stm32can_remoterequest(FAR struct can_dev_s *dev, uint16_t id)
{
#warning "Remote request not implemented"
return -ENOSYS;
}
/****************************************************************************
- * Name: can_send
+ * Name: stm32can_send
*
* Description:
* Send one can message.
@@ -849,7 +1135,7 @@ static int can_remoterequest(FAR struct can_dev_s *dev, uint16_t id)
*
****************************************************************************/
-static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
+static int stm32can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
{
FAR struct stm32_can_s *priv = dev->cd_priv;
FAR uint8_t *ptr;
@@ -858,12 +1144,12 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
int dlc;
int txmb;
- canllvdbg("CAN%d ID: %d DLC: %d\n",
- priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
+ caninfo("CAN%d ID: %d DLC: %d\n",
+ priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
/* Select one empty transmit mailbox */
- regval = can_getreg(priv, STM32_CAN_TSR_OFFSET);
+ regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET);
if ((regval & CAN_TSR_TME0) != 0 && (regval & CAN_TSR_RQCP0) == 0)
{
txmb = 0;
@@ -878,16 +1164,16 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
}
else
{
- canlldbg("ERROR: No available mailbox\n");
+ canerr("ERROR: No available mailbox\n");
return -EBUSY;
}
/* Clear TXRQ, RTR, IDE, EXID, and STID fields */
- regval = can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb));
+ regval = stm32can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb));
regval &= ~(CAN_TIR_TXRQ | CAN_TIR_RTR | CAN_TIR_IDE |
CAN_TIR_EXID_MASK | CAN_TIR_STID_MASK);
- can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval);
+ stm32can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval);
/* Set up the ID, standard 11-bit or extended 29-bit. */
@@ -907,15 +1193,15 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
regval &= ~CAN_TIR_STID_MASK;
regval |= (uint32_t)msg->cm_hdr.ch_id << CAN_TIR_STID_SHIFT;
#endif
- can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval);
+ stm32can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval);
/* Set up the DLC */
dlc = msg->cm_hdr.ch_dlc;
- regval = can_getreg(priv, STM32_CAN_TDTR_OFFSET(txmb));
+ regval = stm32can_getreg(priv, STM32_CAN_TDTR_OFFSET(txmb));
regval &= ~(CAN_TDTR_DLC_MASK | CAN_TDTR_TGT);
regval |= (uint32_t)dlc << CAN_TDTR_DLC_SHIFT;
- can_putreg(priv, STM32_CAN_TDTR_OFFSET(txmb), regval);
+ stm32can_putreg(priv, STM32_CAN_TDTR_OFFSET(txmb), regval);
/* Set up the data fields */
@@ -945,7 +1231,7 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
}
}
}
- can_putreg(priv, STM32_CAN_TDLR_OFFSET(txmb), regval);
+ stm32can_putreg(priv, STM32_CAN_TDLR_OFFSET(txmb), regval);
regval = 0;
if (dlc > 4)
@@ -971,26 +1257,26 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
}
}
}
- can_putreg(priv, STM32_CAN_TDHR_OFFSET(txmb), regval);
+ stm32can_putreg(priv, STM32_CAN_TDHR_OFFSET(txmb), regval);
/* Enable the transmit mailbox empty interrupt (may already be enabled) */
- regval = can_getreg(priv, STM32_CAN_IER_OFFSET);
+ regval = stm32can_getreg(priv, STM32_CAN_IER_OFFSET);
regval |= CAN_IER_TMEIE;
- can_putreg(priv, STM32_CAN_IER_OFFSET, regval);
+ stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval);
/* Request transmission */
- regval = can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb));
+ regval = stm32can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb));
regval |= CAN_TIR_TXRQ; /* Transmit Mailbox Request */
- can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval);
+ stm32can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval);
- can_dumpmbregs(priv, "After send");
+ stm32can_dumpmbregs(priv, "After send");
return OK;
}
/****************************************************************************
- * Name: can_txready
+ * Name: stm32can_txready
*
* Description:
* Return true if the CAN hardware can accept another TX message.
@@ -1003,21 +1289,21 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
*
****************************************************************************/
-static bool can_txready(FAR struct can_dev_s *dev)
+static bool stm32can_txready(FAR struct can_dev_s *dev)
{
FAR struct stm32_can_s *priv = dev->cd_priv;
uint32_t regval;
/* Return true if any mailbox is available */
- regval = can_getreg(priv, STM32_CAN_TSR_OFFSET);
- canllvdbg("CAN%d TSR: %08x\n", priv->port, regval);
+ regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET);
+ caninfo("CAN%d TSR: %08x\n", priv->port, regval);
return (regval & CAN_ALL_MAILBOXES) != 0;
}
/****************************************************************************
- * Name: can_txempty
+ * Name: stm32can_txempty
*
* Description:
* Return true if all message have been sent. If for example, the CAN
@@ -1034,21 +1320,21 @@ static bool can_txready(FAR struct can_dev_s *dev)
*
****************************************************************************/
-static bool can_txempty(FAR struct can_dev_s *dev)
+static bool stm32can_txempty(FAR struct can_dev_s *dev)
{
FAR struct stm32_can_s *priv = dev->cd_priv;
uint32_t regval;
/* Return true if all mailboxes are available */
- regval = can_getreg(priv, STM32_CAN_TSR_OFFSET);
- canllvdbg("CAN%d TSR: %08x\n", priv->port, regval);
+ regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET);
+ caninfo("CAN%d TSR: %08x\n", priv->port, regval);
return (regval & CAN_ALL_MAILBOXES) == CAN_ALL_MAILBOXES;
}
/****************************************************************************
- * Name: can_rxinterrupt
+ * Name: stm32can_rxinterrupt
*
* Description:
* CAN RX FIFO 0/1 interrupt handler
@@ -1063,7 +1349,7 @@ static bool can_txempty(FAR struct can_dev_s *dev)
*
****************************************************************************/
-static int can_rxinterrupt(int irq, FAR void *context, int rxmb)
+static int stm32can_rxinterrupt(int irq, FAR void *context, int rxmb)
{
FAR struct can_dev_s *dev = NULL;
FAR struct stm32_can_s *priv;
@@ -1095,26 +1381,26 @@ static int can_rxinterrupt(int irq, FAR void *context, int rxmb)
/* Verify that a message is pending in the FIFO */
- regval = can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb));
+ regval = stm32can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb));
npending = (regval & CAN_RFR_FMP_MASK) >> CAN_RFR_FMP_SHIFT;
if (npending < 1)
{
- canlldbg("WARNING: No messages pending\n");
+ canwarn("WARNING: No messages pending\n");
return OK;
}
if (rxmb == 0)
{
- can_dumpmbregs(priv, "RX0 interrupt");
+ stm32can_dumpmbregs(priv, "RX0 interrupt");
}
else
{
- can_dumpmbregs(priv, "RX1 interrupt");
+ stm32can_dumpmbregs(priv, "RX1 interrupt");
}
/* Get the CAN identifier. */
- regval = can_getreg(priv, STM32_CAN_RIR_OFFSET(rxmb));
+ regval = stm32can_getreg(priv, STM32_CAN_RIR_OFFSET(rxmb));
#ifdef CONFIG_CAN_EXTID
if ((regval & CAN_RIR_IDE) != 0)
@@ -1130,7 +1416,7 @@ static int can_rxinterrupt(int irq, FAR void *context, int rxmb)
#else
if ((regval & CAN_RIR_IDE) != 0)
{
- canlldbg("ERROR: Received message with extended identifier. Dropped\n");
+ canerr("ERROR: Received message with extended identifier. Dropped\n");
ret = -ENOSYS;
goto errout;
}
@@ -1151,18 +1437,18 @@ static int can_rxinterrupt(int irq, FAR void *context, int rxmb)
/* Get the DLC */
- regval = can_getreg(priv, STM32_CAN_RDTR_OFFSET(rxmb));
+ regval = stm32can_getreg(priv, STM32_CAN_RDTR_OFFSET(rxmb));
hdr.ch_dlc = (regval & CAN_RDTR_DLC_MASK) >> CAN_RDTR_DLC_SHIFT;
/* Save the message data */
- regval = can_getreg(priv, STM32_CAN_RDLR_OFFSET(rxmb));
+ regval = stm32can_getreg(priv, STM32_CAN_RDLR_OFFSET(rxmb));
data[0] = (regval & CAN_RDLR_DATA0_MASK) >> CAN_RDLR_DATA0_SHIFT;
data[1] = (regval & CAN_RDLR_DATA1_MASK) >> CAN_RDLR_DATA1_SHIFT;
data[2] = (regval & CAN_RDLR_DATA2_MASK) >> CAN_RDLR_DATA2_SHIFT;
data[3] = (regval & CAN_RDLR_DATA3_MASK) >> CAN_RDLR_DATA3_SHIFT;
- regval = can_getreg(priv, STM32_CAN_RDHR_OFFSET(rxmb));
+ regval = stm32can_getreg(priv, STM32_CAN_RDHR_OFFSET(rxmb));
data[4] = (regval & CAN_RDHR_DATA4_MASK) >> CAN_RDHR_DATA4_SHIFT;
data[5] = (regval & CAN_RDHR_DATA5_MASK) >> CAN_RDHR_DATA5_SHIFT;
data[6] = (regval & CAN_RDHR_DATA6_MASK) >> CAN_RDHR_DATA6_SHIFT;
@@ -1177,14 +1463,14 @@ static int can_rxinterrupt(int irq, FAR void *context, int rxmb)
#ifndef CONFIG_CAN_EXTID
errout:
#endif
- regval = can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb));
+ regval = stm32can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb));
regval |= CAN_RFR_RFOM;
- can_putreg(priv, STM32_CAN_RFR_OFFSET(rxmb), regval);
+ stm32can_putreg(priv, STM32_CAN_RFR_OFFSET(rxmb), regval);
return ret;
}
/****************************************************************************
- * Name: can_rx0interrupt
+ * Name: stm32can_rx0interrupt
*
* Description:
* CAN RX FIFO 0 interrupt handler
@@ -1198,13 +1484,13 @@ errout:
*
****************************************************************************/
-static int can_rx0interrupt(int irq, FAR void *context)
+static int stm32can_rx0interrupt(int irq, FAR void *context)
{
- return can_rxinterrupt(irq, context, 0);
+ return stm32can_rxinterrupt(irq, context, 0);
}
/****************************************************************************
- * Name: can_rx1interrupt
+ * Name: stm32can_rx1interrupt
*
* Description:
* CAN RX FIFO 1 interrupt handler
@@ -1218,13 +1504,13 @@ static int can_rx0interrupt(int irq, FAR void *context)
*
****************************************************************************/
-static int can_rx1interrupt(int irq, FAR void *context)
+static int stm32can_rx1interrupt(int irq, FAR void *context)
{
- return can_rxinterrupt(irq, context, 1);
+ return stm32can_rxinterrupt(irq, context, 1);
}
/****************************************************************************
- * Name: can_txinterrupt
+ * Name: stm32can_txinterrupt
*
* Description:
* CAN TX mailbox complete interrupt handler
@@ -1238,7 +1524,7 @@ static int can_rx1interrupt(int irq, FAR void *context)
*
****************************************************************************/
-static int can_txinterrupt(int irq, FAR void *context)
+static int stm32can_txinterrupt(int irq, FAR void *context)
{
FAR struct can_dev_s *dev = NULL;
FAR struct stm32_can_s *priv;
@@ -1266,7 +1552,7 @@ static int can_txinterrupt(int irq, FAR void *context)
/* Get the transmit status */
- regval = can_getreg(priv, STM32_CAN_TSR_OFFSET);
+ regval = stm32can_getreg(priv, STM32_CAN_TSR_OFFSET);
/* Check for RQCP0: Request completed mailbox 0 */
@@ -1276,7 +1562,7 @@ static int can_txinterrupt(int irq, FAR void *context)
* ALST0 and TERR0) for Mailbox 0.
*/
- can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP0);
+ stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP0);
/* Check for errors */
@@ -1296,7 +1582,7 @@ static int can_txinterrupt(int irq, FAR void *context)
* ALST1 and TERR1) for Mailbox 1.
*/
- can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP1);
+ stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP1);
/* Check for errors */
@@ -1316,7 +1602,7 @@ static int can_txinterrupt(int irq, FAR void *context)
* ALST2 and TERR2) for Mailbox 2.
*/
- can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP2);
+ stm32can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP2);
/* Check for errors */
@@ -1332,7 +1618,7 @@ static int can_txinterrupt(int irq, FAR void *context)
}
/****************************************************************************
- * Name: can_bittiming
+ * Name: stm32can_bittiming
*
* Description:
* Set the CAN bit timing register (BTR) based on the configured BAUD.
@@ -1387,15 +1673,15 @@ static int can_txinterrupt(int irq, FAR void *context)
*
****************************************************************************/
-static int can_bittiming(FAR struct stm32_can_s *priv)
+static int stm32can_bittiming(FAR struct stm32_can_s *priv)
{
uint32_t tmp;
uint32_t brp;
uint32_t ts1;
uint32_t ts2;
- canllvdbg("CAN%d PCLK1: %d baud: %d\n",
- priv->port, STM32_PCLK1_FREQUENCY, priv->baud);
+ caninfo("CAN%d PCLK1: %d baud: %d\n",
+ priv->port, STM32_PCLK1_FREQUENCY, priv->baud);
/* Try to get CAN_BIT_QUANTA quanta in one bit_time.
*
@@ -1447,7 +1733,7 @@ static int can_bittiming(FAR struct stm32_can_s *priv)
DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX);
}
- canllvdbg("TS1: %d TS2: %d BRP: %d\n", ts1, ts2, brp);
+ caninfo("TS1: %d TS2: %d BRP: %d\n", ts1, ts2, brp);
/* Configure bit timing. This also does the following, less obvious
* things. Unless loopback mode is enabled, it:
@@ -1466,12 +1752,12 @@ static int can_bittiming(FAR struct stm32_can_s *priv)
tmp |= CAN_BTR_LBKM;
#endif
- can_putreg(priv, STM32_CAN_BTR_OFFSET, tmp);
+ stm32can_putreg(priv, STM32_CAN_BTR_OFFSET, tmp);
return OK;
}
/****************************************************************************
- * Name: can_cellinit
+ * Name: stm32can_cellinit
*
* Description:
* CAN cell initialization
@@ -1484,30 +1770,30 @@ static int can_bittiming(FAR struct stm32_can_s *priv)
*
****************************************************************************/
-static int can_cellinit(FAR struct stm32_can_s *priv)
+static int stm32can_cellinit(FAR struct stm32_can_s *priv)
{
volatile uint32_t timeout;
uint32_t regval;
int ret;
- canllvdbg("CAN%d\n", priv->port);
+ caninfo("CAN%d\n", priv->port);
/* Exit from sleep mode */
- regval = can_getreg(priv, STM32_CAN_MCR_OFFSET);
+ regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET);
regval &= ~CAN_MCR_SLEEP;
- can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
+ stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
/* Enter initialization mode */
regval |= CAN_MCR_INRQ;
- can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
+ stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
/* Wait until initialization mode is acknowledged */
for (timeout = INAK_TIMEOUT; timeout > 0; timeout--)
{
- regval = can_getreg(priv, STM32_CAN_MSR_OFFSET);
+ regval = stm32can_getreg(priv, STM32_CAN_MSR_OFFSET);
if ((regval & CAN_MSR_INAK) != 0)
{
/* We are in initialization mode */
@@ -1520,7 +1806,7 @@ static int can_cellinit(FAR struct stm32_can_s *priv)
if (timeout < 1)
{
- canlldbg("ERROR: Timed out waiting to enter initialization mode\n");
+ canerr("ERROR: Timed out waiting to enter initialization mode\n");
return -ETIMEDOUT;
}
@@ -1534,31 +1820,31 @@ static int can_cellinit(FAR struct stm32_can_s *priv)
* - Transmit FIFO priority
*/
- regval = can_getreg(priv, STM32_CAN_MCR_OFFSET);
+ regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET);
regval &= ~(CAN_MCR_TXFP | CAN_MCR_RFLM | CAN_MCR_NART |
CAN_MCR_AWUM | CAN_MCR_ABOM | CAN_MCR_TTCM);
- can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
+ stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
/* Configure bit timing. */
- ret = can_bittiming(priv);
+ ret = stm32can_bittiming(priv);
if (ret < 0)
{
- canlldbg("ERROR: Failed to set bit timing: %d\n", ret);
+ canerr("ERROR: Failed to set bit timing: %d\n", ret);
return ret;
}
/* Exit initialization mode */
- regval = can_getreg(priv, STM32_CAN_MCR_OFFSET);
+ regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET);
regval &= ~CAN_MCR_INRQ;
- can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
+ stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
/* Wait until the initialization mode exit is acknowledged */
for (timeout = INAK_TIMEOUT; timeout > 0; timeout--)
{
- regval = can_getreg(priv, STM32_CAN_MSR_OFFSET);
+ regval = stm32can_getreg(priv, STM32_CAN_MSR_OFFSET);
if ((regval & CAN_MSR_INAK) == 0)
{
/* We are out of initialization mode */
@@ -1571,15 +1857,15 @@ static int can_cellinit(FAR struct stm32_can_s *priv)
if (timeout < 1)
{
- canlldbg("ERROR: Timed out waiting to exit initialization mode: %08x\n",
- regval);
+ canerr("ERROR: Timed out waiting to exit initialization mode: %08x\n",
+ regval);
return -ETIMEDOUT;
}
return OK;
}
/****************************************************************************
- * Name: can_filterinit
+ * Name: stm32can_filterinit
*
* Description:
* CAN filter initialization. CAN filters are not currently used by this
@@ -1611,12 +1897,12 @@ static int can_cellinit(FAR struct stm32_can_s *priv)
*
****************************************************************************/
-static int can_filterinit(FAR struct stm32_can_s *priv)
+static int stm32can_filterinit(FAR struct stm32_can_s *priv)
{
uint32_t regval;
uint32_t bitmask;
- canllvdbg("CAN%d filter: %d\n", priv->port, priv->filter);
+ caninfo("CAN%d filter: %d\n", priv->port, priv->filter);
/* Get the bitmask associated with the filter used by this CAN block */
@@ -1624,66 +1910,158 @@ static int can_filterinit(FAR struct stm32_can_s *priv)
/* Enter filter initialization mode */
- regval = can_getfreg(priv, STM32_CAN_FMR_OFFSET);
+ regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET);
regval |= CAN_FMR_FINIT;
- can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval);
+ stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval);
/* Assign half the filters to CAN1, half to CAN2 */
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || \
defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F40XX)
- regval = can_getfreg(priv, STM32_CAN_FMR_OFFSET);
+ regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET);
regval &= CAN_FMR_CAN2SB_MASK;
regval |= (CAN_NFILTERS / 2) << CAN_FMR_CAN2SB_SHIFT;
- can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval);
+ stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval);
#endif
/* Disable the filter */
- regval = can_getfreg(priv, STM32_CAN_FA1R_OFFSET);
+ regval = stm32can_getfreg(priv, STM32_CAN_FA1R_OFFSET);
regval &= ~bitmask;
- can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval);
+ stm32can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval);
/* Select the 32-bit scale for the filter */
- regval = can_getfreg(priv, STM32_CAN_FS1R_OFFSET);
+ regval = stm32can_getfreg(priv, STM32_CAN_FS1R_OFFSET);
regval |= bitmask;
- can_putfreg(priv, STM32_CAN_FS1R_OFFSET, regval);
+ stm32can_putfreg(priv, STM32_CAN_FS1R_OFFSET, regval);
/* There are 14 or 28 filter banks (depending) on the device.
* Each filter bank is composed of two 32-bit registers, CAN_FiR:
*/
- can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 1), 0);
- can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 2), 0);
+ stm32can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 1), 0);
+ stm32can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 2), 0);
/* Set Id/Mask mode for the filter */
- regval = can_getfreg(priv, STM32_CAN_FM1R_OFFSET);
+ regval = stm32can_getfreg(priv, STM32_CAN_FM1R_OFFSET);
regval &= ~bitmask;
- can_putfreg(priv, STM32_CAN_FM1R_OFFSET, regval);
+ stm32can_putfreg(priv, STM32_CAN_FM1R_OFFSET, regval);
/* Assign FIFO 0 for the filter */
- regval = can_getfreg(priv, STM32_CAN_FFA1R_OFFSET);
+ regval = stm32can_getfreg(priv, STM32_CAN_FFA1R_OFFSET);
regval &= ~bitmask;
- can_putfreg(priv, STM32_CAN_FFA1R_OFFSET, regval);
+ stm32can_putfreg(priv, STM32_CAN_FFA1R_OFFSET, regval);
/* Enable the filter */
- regval = can_getfreg(priv, STM32_CAN_FA1R_OFFSET);
+ regval = stm32can_getfreg(priv, STM32_CAN_FA1R_OFFSET);
regval |= bitmask;
- can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval);
+ stm32can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval);
/* Exit filter initialization mode */
- regval = can_getfreg(priv, STM32_CAN_FMR_OFFSET);
+ regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET);
regval &= ~CAN_FMR_FINIT;
- can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval);
+ stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval);
return OK;
}
+/****************************************************************************
+ * Name: stm32can_addextfilter
+ *
+ * Description:
+ * Add a filter for extended CAN IDs
+ *
+ * Input Parameter:
+ * priv - A pointer to the private data structure for this CAN block
+ * arg - A pointer to a structure describing the filter
+ *
+ * Returned Value:
+ * A non-negative filter ID is returned on success.
+ * Otherwise -1 (ERROR) is returned with the errno
+ * set to indicate the nature of the error.
+ *
+ ****************************************************************************/
+
+static int stm32can_addextfilter(FAR struct stm32_can_s *priv,
+ FAR struct canioc_extfilter_s *arg)
+{
+ return -ENOTTY;
+}
+
+/****************************************************************************
+ * Name: stm32can_delextfilter
+ *
+ * Description:
+ * Remove a filter for extended CAN IDs
+ *
+ * Input Parameter:
+ * priv - A pointer to the private data structure for this CAN block
+ * arg - The filter index previously returned by the
+ * CANIOC_ADD_EXTFILTER command
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. Otherwise -1 (ERROR)
+ * returned with the errno variable set to indicate the
+ * of the error.
+ *
+ ****************************************************************************/
+
+static int stm32can_delextfilter(FAR struct stm32_can_s *priv, int arg)
+{
+ return -ENOTTY;
+}
+
+/****************************************************************************
+ * Name: stm32can_addextfilter
+ *
+ * Description:
+ * Add a filter for standard CAN IDs
+ *
+ * Input Parameter:
+ * priv - A pointer to the private data structure for this CAN block
+ * arg - A pointer to a structure describing the filter
+ *
+ * Returned Value:
+ * A non-negative filter ID is returned on success.
+ * Otherwise -1 (ERROR) is returned with the errno
+ * set to indicate the nature of the error.
+ *
+ ****************************************************************************/
+
+static int stm32can_addstdfilter(FAR struct stm32_can_s *priv,
+ FAR struct canioc_stdfilter_s *arg)
+{
+ return -ENOTTY;
+}
+
+/****************************************************************************
+ * Name: stm32can_delstdfilter
+ *
+ * Description:
+ * Remove a filter for standard CAN IDs
+ *
+ * Input Parameter:
+ * priv - A pointer to the private data structure for this CAN block
+ * arg - The filter index previously returned by the
+ * CANIOC_ADD_STDFILTER command
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. Otherwise -1 (ERROR)
+ * returned with the errno variable set to indicate the
+ * of the error.
+ *
+ ****************************************************************************/
+
+static int stm32can_delstdfilter(FAR struct stm32_can_s *priv, int arg)
+{
+ return -ENOTTY;
+}
+
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -1706,7 +2084,7 @@ FAR struct can_dev_s *stm32_caninitialize(int port)
{
FAR struct can_dev_s *dev = NULL;
- canvdbg("CAN%d\n", port);
+ caninfo("CAN%d\n", port);
/* NOTE: Peripherical clocking for CAN1 and/or CAN2 was already provided
* by stm32_clockconfig() early in the reset sequence.
@@ -1745,7 +2123,7 @@ FAR struct can_dev_s *stm32_caninitialize(int port)
else
#endif
{
- candbg("ERROR: Unsupported port %d\n", port);
+ canerr("ERROR: Unsupported port %d\n", port);
return NULL;
}
diff --git a/arch/arm/src/stm32/stm32_capture.c b/arch/arm/src/stm32/stm32_capture.c
index 55864281a9ccb17a1c1ecb9d7c0e7876bd1677c5..e5fefa74cfc27a2fbb93a735df4d4c6ab6379731 100644
--- a/arch/arm/src/stm32/stm32_capture.c
+++ b/arch/arm/src/stm32/stm32_capture.c
@@ -185,7 +185,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
{
switch(priv->base)
{
-#ifdef CONFIG_STM32_TIM1
+#ifdef CONFIG_STM32_TIM1_CAP
case STM32_TIM1_BASE:
switch (channel)
{
@@ -212,7 +212,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
}
break;
#endif
-#ifdef CONFIG_STM32_TIM2
+#ifdef CONFIG_STM32_TIM2_CAP
case STM32_TIM2_BASE:
switch (channel)
{
@@ -239,7 +239,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
}
break;
#endif
-#ifdef CONFIG_STM32_TIM3
+#ifdef CONFIG_STM32_TIM3_CAP
case STM32_TIM3_BASE:
switch (channel)
{
@@ -266,7 +266,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
}
break;
#endif
-#ifdef CONFIG_STM32_TIM4
+#ifdef CONFIG_STM32_TIM4_CAP
case STM32_TIM4_BASE:
switch (channel)
{
@@ -293,7 +293,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
}
break;
#endif
-#ifdef CONFIG_STM32_TIM5
+#ifdef CONFIG_STM32_TIM5_CAP
case STM32_TIM5_BASE:
switch (channel)
{
@@ -323,7 +323,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
/* TIM6 and TIM7 cannot be used in capture */
-#ifdef CONFIG_STM32_TIM8
+#ifdef CONFIG_STM32_TIM8_CAP
case STM32_TIM8_BASE:
switch (channel)
{
@@ -351,7 +351,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
break;
#endif
-#ifdef CONFIG_STM32_TIM9
+#ifdef CONFIG_STM32_TIM9_CAP
case STM32_TIM9_BASE:
switch (channel)
{
@@ -379,7 +379,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
break;
#endif
-#ifdef CONFIG_STM32_TIM10
+#ifdef CONFIG_STM32_TIM10_CAP
case STM32_TIM10_BASE:
switch (channel)
{
@@ -407,7 +407,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
break;
#endif
-#ifdef CONFIG_STM32_TIM11
+#ifdef CONFIG_STM32_TIM11_CAP
case STM32_TIM11_BASE:
switch (channel)
{
@@ -435,7 +435,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
break;
#endif
-#ifdef CONFIG_STM32_TIM12
+#ifdef CONFIG_STM32_TIM12_CAP
case STM32_TIM12_BASE:
switch (channel)
{
@@ -463,7 +463,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
break;
#endif
-#ifdef CONFIG_STM32_TIM13
+#ifdef CONFIG_STM32_TIM13_CAP
case STM32_TIM13_BASE:
switch (channel)
{
@@ -491,7 +491,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
break;
#endif
-#ifdef CONFIG_STM32_TIM14
+#ifdef CONFIG_STM32_TIM14_CAP
case STM32_TIM14_BASE:
switch (channel)
{
@@ -531,31 +531,31 @@ static inline int stm32_cap_set_rcc(FAR const struct stm32_cap_priv_s *priv,
switch (priv->base)
{
#ifdef CONFIG_STM32_TIM1_CAP
- case 1:
+ case STM32_TIM1_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM1EN;
break;
#endif
#ifdef CONFIG_STM32_TIM2_CAP
- case 2:
+ case STM32_TIM2_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM2EN;
break;
#endif
#ifdef CONFIG_STM32_TIM3_CAP
- case 3:
+ case STM32_TIM3_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM3EN;
break;
#endif
#ifdef CONFIG_STM32_TIM4_CAP
- case 4:
+ case STM32_TIM4_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM4EN;
break;
#endif
#ifdef CONFIG_STM32_TIM5_CAP
- case 5:
+ case STM32_TIM5_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM5EN;
break;
@@ -564,43 +564,43 @@ static inline int stm32_cap_set_rcc(FAR const struct stm32_cap_priv_s *priv,
/* TIM6 and TIM7 cannot be used in capture */
#ifdef CONFIG_STM32_TIM8_CAP
- case 8:
+ case STM32_TIM8_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM8EN;
break;
#endif
#ifdef CONFIG_STM32_TIM9_CAP
- case 9:
+ case STM32_TIM9_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM9EN;
break;
#endif
#ifdef CONFIG_STM32_TIM10_CAP
- case 10:
+ case STM32_TIM10_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM10EN;
break;
#endif
#ifdef CONFIG_STM32_TIM11_CAP
- case 11:
+ case STM32_TIM11_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM11EN;
break;
#endif
#ifdef CONFIG_STM32_TIM12_CAP
- case 12:
+ case STM32_TIM12_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB2ENR_TIM12EN;
break;
#endif
#ifdef CONFIG_STM32_TIM13_CAP
- case 13:
+ case STM32_TIM13_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB2ENR_TIM13EN;
break;
#endif
#ifdef CONFIG_STM32_TIM14_CAP
- case 14:
+ case STM32_TIM14_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB2ENR_TIM14EN;
break;
@@ -1097,9 +1097,9 @@ const struct stm32_cap_priv_s stm32_tim1_priv =
{
.ops = &stm32_cap_ops,
.base = STM32_TIM1_BASE,
- .irq = STM32_IRQ_TIM1,
+ .irq = STM32_IRQ_TIM1CC,
#ifdef USE_ADVENCED_TIM
- .irg_of = STM32_IRQ_TIM1UP,
+ .irq_of = STM32_IRQ_TIM1UP,
#endif
};
#endif
@@ -1111,7 +1111,7 @@ const struct stm32_cap_priv_s stm32_tim2_priv =
.base = STM32_TIM2_BASE,
.irq = STM32_IRQ_TIM2,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
@@ -1123,7 +1123,7 @@ const struct stm32_cap_priv_s stm32_tim3_priv =
.base = STM32_TIM3_BASE,
.irq = STM32_IRQ_TIM3,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
@@ -1135,7 +1135,7 @@ const struct stm32_cap_priv_s stm32_tim4_priv =
.base = STM32_TIM4_BASE,
.irq = STM32_IRQ_TIM4,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
@@ -1147,7 +1147,7 @@ const struct stm32_cap_priv_s stm32_tim5_priv =
.base = STM32_TIM5_BASE,
.irq = STM32_IRQ_TIM5,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
@@ -1159,9 +1159,9 @@ const struct stm32_cap_priv_s stm32_tim8_priv =
{
.ops = &stm32_cap_ops,
.base = STM32_TIM8_BASE,
- .irq = STM32_IRQ_TIM8,
+ .irq = STM32_IRQ_TIM8CC,
#ifdef USE_ADVENCED_TIM
- .irg_of = STM32_IRQ_TIM8UP,
+ .irq_of = STM32_IRQ_TIM8UP,
#endif
};
#endif
@@ -1173,7 +1173,7 @@ const struct stm32_cap_priv_s stm32_tim9_priv =
.base = STM32_TIM9_BASE,
.irq = STM32_IRQ_TIM9,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
@@ -1185,7 +1185,7 @@ const struct stm32_cap_priv_s stm32_tim10_priv =
.base = STM32_TIM10_BASE,
.irq = STM32_IRQ_TIM10,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
@@ -1197,7 +1197,7 @@ const struct stm32_cap_priv_s stm32_tim11_priv =
.base = STM32_TIM11_BASE,
.irq = STM32_IRQ_TIM11,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
@@ -1209,7 +1209,7 @@ const struct stm32_cap_priv_s stm32_tim12_priv =
.base = STM32_TIM12_BASE,
.irq = STM32_IRQ_TIM12,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
@@ -1221,7 +1221,7 @@ const struct stm32_cap_priv_s stm32_tim13_priv =
.base = STM32_TIM13_BASE,
.irq = STM32_IRQ_TIM13,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
@@ -1233,7 +1233,7 @@ const struct stm32_cap_priv_s stm32_tim14_priv =
.base = STM32_TIM14_BASE,
.irq = STM32_IRQ_TIM14,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
diff --git a/arch/arm/src/stm32/stm32_dac.c b/arch/arm/src/stm32/stm32_dac.c
index 77213af264971e7cc0b98e923e11f3ba3bad1634..528faf1786c90821ea60005ff5cca22d6e5f40ea 100644
--- a/arch/arm/src/stm32/stm32_dac.c
+++ b/arch/arm/src/stm32/stm32_dac.c
@@ -848,11 +848,11 @@ static int dac_timinit(FAR struct stm32_chan_s *chan)
case 8:
regaddr = STM32_RCC_APB2ENR;
setbits = RCC_APB2ENR_TIM8EN;
- pclk = STM32_TIM18_FREQUENCY;
+ pclk = BOARD_TIM8_FREQUENCY;
break;
#endif
default:
- adbg("Could not enable timer\n");
+ aerr("ERROR: Could not enable timer\n");
break;
}
@@ -1016,7 +1016,7 @@ static int dac_chaninit(FAR struct stm32_chan_s *chan)
chan->dma = stm32_dmachannel(chan->dmachan);
if (!chan->dma)
{
- adbg("Failed to allocate a DMA channel\n");
+ aerr("ERROR: Failed to allocate a DMA channel\n");
return -EBUSY;
}
@@ -1025,7 +1025,7 @@ static int dac_chaninit(FAR struct stm32_chan_s *chan)
ret = dac_timinit(chan);
if (ret < 0)
{
- adbg("Failed to initialize the DMA timer: %d\n", ret);
+ aerr("ERROR: Failed to initialize the DMA timer: %d\n", ret);
return ret;
}
}
@@ -1114,7 +1114,7 @@ FAR struct dac_dev_s *stm32_dacinitialize(int intf)
#ifdef CONFIG_STM32_DAC1
if (intf == 1)
{
- avdbg("DAC1 Selected\n");
+ ainfo("DAC1 Selected\n");
dev = &g_dac1dev;
}
else
@@ -1122,13 +1122,13 @@ FAR struct dac_dev_s *stm32_dacinitialize(int intf)
#ifdef CONFIG_STM32_DAC2
if (intf == 2)
{
- avdbg("DAC2 Selected\n");
+ ainfo("DAC2 Selected\n");
dev = &g_dac2dev;
}
else
#endif
{
- adbg("No such DAC interface: %d\n", intf);
+ aerr("ERROR: No such DAC interface: %d\n", intf);
errno = ENODEV;
return NULL;
}
@@ -1138,7 +1138,7 @@ FAR struct dac_dev_s *stm32_dacinitialize(int intf)
ret = dac_blockinit();
if (ret < 0)
{
- adbg("Failed to initialize the DAC block: %d\n", ret);
+ aerr("ERROR: Failed to initialize the DAC block: %d\n", ret);
errno = -ret;
return NULL;
}
@@ -1149,7 +1149,7 @@ FAR struct dac_dev_s *stm32_dacinitialize(int intf)
ret = dac_chaninit(chan);
if (ret < 0)
{
- adbg("Failed to initialize DAC channel %d: %d\n", intf, ret);
+ aerr("ERROR: Failed to initialize DAC channel %d: %d\n", intf, ret);
errno = -ret;
return NULL;
}
diff --git a/arch/arm/src/stm32/stm32_dma.c b/arch/arm/src/stm32/stm32_dma.c
index ff7135840e414814c0776f2bbd761fc0974c9ea0..4b694e7ccb9de6ddbf582e2e848c631e7da1ef58 100644
--- a/arch/arm/src/stm32/stm32_dma.c
+++ b/arch/arm/src/stm32/stm32_dma.c
@@ -56,7 +56,7 @@
*/
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
- defined(CONFIG_STM32_STM32F30XX)
+ defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
# include "stm32f10xxx_dma.c"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "stm32f20xxx_dma.c"
diff --git a/arch/arm/src/stm32/stm32_dma.h b/arch/arm/src/stm32/stm32_dma.h
index b2f968fe1f7c0e6110b1d60cf43f342c17d14d0a..d26428c35bbc758d714345ed998aff76f7614a51 100644
--- a/arch/arm/src/stm32/stm32_dma.h
+++ b/arch/arm/src/stm32/stm32_dma.h
@@ -104,7 +104,7 @@ typedef FAR void *DMA_HANDLE;
typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
struct stm32_dmaregs_s
@@ -299,7 +299,7 @@ bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr);
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs);
#else
# define stm32_dmasample(handle,regs)
@@ -316,7 +316,7 @@ void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs);
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
const char *msg);
#else
diff --git a/arch/arm/src/stm32/stm32_dma2d.c b/arch/arm/src/stm32/stm32_dma2d.c
index e951e8916dbeb36546b098a793d07b564ab5af4b..5e5740e27b8438e1c33edbea037c9119309cae42 100644
--- a/arch/arm/src/stm32/stm32_dma2d.c
+++ b/arch/arm/src/stm32/stm32_dma2d.c
@@ -137,11 +137,11 @@
/* Debug option */
#ifdef CONFIG_STM32_DMA2D_REGDEBUG
-# define regdbg dbg
-# define regvdbg vdbg
+# define regerr lcderr
+# define reginfo lcdinfo
#else
-# define regdbg(x...)
-# define regvdbg(x...)
+# define regerr(x...)
+# define reginfo(x...)
#endif
/* check clut support */
@@ -408,7 +408,7 @@ static void stm32_dma2d_control(uint32_t setbits, uint32_t clrbits)
{
uint32_t cr;
- gvdbg("setbits=%08x, clrbits=%08x\n", setbits, clrbits);
+ lcdinfo("setbits=%08x, clrbits=%08x\n", setbits, clrbits);
cr = getreg32(STM32_DMA2D_CR);
cr &= ~clrbits;
@@ -429,7 +429,7 @@ static int stm32_dma2dirq(int irq, void *context)
uint32_t regval = getreg32(STM32_DMA2D_ISR);
FAR struct stm32_interrupt_s *priv = &g_interrupt;
- regvdbg("irq = %d, regval = %08x\n", irq, regval);
+ reginfo("irq = %d, regval = %08x\n", irq, regval);
if (regval & DMA2D_ISR_TCIF)
{
@@ -469,7 +469,7 @@ static int stm32_dma2dirq(int irq, void *context)
if (ret != OK)
{
- dbg("sem_post() failed\n");
+ lcderr("ERROR: sem_post() failed\n");
return ret;
}
}
@@ -512,7 +512,7 @@ static int stm32_dma2d_waitforirq(void)
if (ret != OK)
{
- dbg("sem_wait() failed\n");
+ lcderr("ERROR: sem_wait() failed\n");
return ret;
}
}
@@ -558,9 +558,9 @@ static int stm32_dma2d_loadclut(uintptr_t pfcreg)
regval = getreg32(pfcreg);
regval |= DMA2D_xGPFCCR_START;
- regvdbg("set regval=%08x\n", regval);
+ reginfo("set regval=%08x\n", regval);
putreg32(regval, pfcreg);
- regvdbg("configured regval=%08x\n", getreg32(pfcreg));
+ reginfo("configured regval=%08x\n", getreg32(pfcreg));
}
leave_critical_section(flags);
@@ -632,7 +632,7 @@ static uint32_t stm32_dma2d_memaddress(FAR const struct stm32_dma2d_s *layer,
offset = xpos * DMA2D_PF_BYPP(layer->pinfo.bpp) + layer->pinfo.stride * ypos;
- gvdbg("%p\n", ((uint32_t) pinfo->fbmem) + offset);
+ lcdinfo("%p\n", ((uint32_t) pinfo->fbmem) + offset);
return ((uint32_t) pinfo->fbmem) + offset;
}
@@ -655,7 +655,7 @@ static fb_coord_t stm32_dma2d_lineoffset(FAR const struct stm32_dma2d_s *layer,
{
/* offset at the end of each line in the context to the area layer */
- gvdbg("%d\n", layer->vinfo.xres - area->xres);
+ lcdinfo("%d\n", layer->vinfo.xres - area->xres);
return layer->vinfo.xres - area->xres;
}
@@ -677,7 +677,7 @@ static fb_coord_t stm32_dma2d_lineoffset(FAR const struct stm32_dma2d_s *layer,
static int stm32_dma2d_pixelformat(uint8_t fmt, uint8_t *fmtmap)
{
- gvdbg("fmt=%d, fmtmap=%p\n", fmt, fmtmap);
+ lcdinfo("fmt=%d, fmtmap=%p\n", fmt, fmtmap);
/* Map to the controller known format
*
@@ -711,7 +711,7 @@ static int stm32_dma2d_pixelformat(uint8_t fmt, uint8_t *fmtmap)
break;
#endif
default:
- gdbg("ERROR: Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -736,7 +736,7 @@ static int stm32_dma2d_pixelformat(uint8_t fmt, uint8_t *fmtmap)
static int stm32_dma2d_bpp(uint8_t fmt, uint8_t *bpp)
{
- gvdbg("fmt=%d, bpp=%p\n", fmt, bpp);
+ lcdinfo("fmt=%d, bpp=%p\n", fmt, bpp);
switch (fmt)
{
@@ -756,7 +756,7 @@ static int stm32_dma2d_bpp(uint8_t fmt, uint8_t *bpp)
break;
#endif
default:
- gdbg("ERROR: Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -937,7 +937,7 @@ static void stm32_dma2d_linit(FAR struct stm32_dma2d_s *layer,
{
FAR struct dma2d_layer_s *priv = &layer->dma2d;
- gvdbg("layer=%p, lid=%d, fmt=%02x\n", layer, lid, fmt);
+ lcdinfo("layer=%p, lid=%d, fmt=%02x\n", layer, lid, fmt);
/* initialize the layer interface */
@@ -985,8 +985,8 @@ static void stm32_dma2d_lfifo(FAR const struct stm32_dma2d_s *layer, int lid,
fb_coord_t xpos, fb_coord_t ypos,
FAR const struct ltdc_area_s *area)
{
- gvdbg("layer=%p, lid=%d, xpos=%d, ypos=%d, area=%p\n",
- layer, lid, xpos, ypos, area);
+ lcdinfo("layer=%p, lid=%d, xpos=%d, ypos=%d, area=%p\n",
+ layer, lid, xpos, ypos, area);
putreg32(stm32_dma2d_memaddress(layer, xpos, ypos), stm32_mar_layer_t[lid]);
putreg32(stm32_dma2d_lineoffset(layer, area), stm32_or_layer_t[lid]);
@@ -1006,7 +1006,7 @@ static void stm32_dma2d_lfifo(FAR const struct stm32_dma2d_s *layer, int lid,
static void stm32_dma2d_lcolor(FAR const struct stm32_dma2d_s *layer,
int lid, uint32_t color)
{
- gvdbg("layer=%p, lid=%d, color=%08x\n", layer, lid, color);
+ lcdinfo("layer=%p, lid=%d, color=%08x\n", layer, lid, color);
putreg32(color, stm32_color_layer_t[lid]);
}
@@ -1027,7 +1027,7 @@ static void stm32_dma2d_llnr(FAR struct stm32_dma2d_s *layer,
{
uint32_t nlrreg;
- gvdbg("pixel per line: %d, number of lines: %d\n", area->xres, area->yres);
+ lcdinfo("pixel per line: %d, number of lines: %d\n", area->xres, area->yres);
nlrreg = getreg32(STM32_DMA2D_NLR);
nlrreg = (DMA2D_NLR_PL(area->xres) | DMA2D_NLR_NL(area->yres));
@@ -1047,7 +1047,7 @@ static void stm32_dma2d_llnr(FAR struct stm32_dma2d_s *layer,
static int stm32_dma2d_loutpfc(FAR const struct stm32_dma2d_s *layer)
{
- gvdbg("layer=%p\n", layer);
+ lcdinfo("layer=%p\n", layer);
/* CLUT format isn't supported by the dma2d controller */
@@ -1055,8 +1055,8 @@ static int stm32_dma2d_loutpfc(FAR const struct stm32_dma2d_s *layer)
{
/* Destination layer doesn't support CLUT output */
- gdbg("ERROR: Returning ENOSYS, "
- "output to layer with CLUT format not supported.\n");
+ lcderr("ERROR: Returning ENOSYS, "
+ "output to layer with CLUT format not supported.\n");
return -ENOSYS;
}
@@ -1083,7 +1083,7 @@ static void stm32_dma2d_lpfc(FAR const struct stm32_dma2d_s *layer,
{
uint32_t pfccrreg;
- gvdbg("layer=%p, lid=%d, blendmode=%08x\n", layer, lid, blendmode);
+ lcdinfo("layer=%p, lid=%d, blendmode=%08x\n", layer, lid, blendmode);
/* Set color format */
@@ -1172,7 +1172,7 @@ static int stm32_dma2dgetvideoinfo(FAR struct dma2d_layer_s *layer,
{
FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer;
- gvdbg("layer=%p, vinfo=%p\n", layer, vinfo);
+ lcdinfo("layer=%p, vinfo=%p\n", layer, vinfo);
if (stm32_dma2d_lvalidate(priv) && vinfo)
{
@@ -1183,7 +1183,7 @@ static int stm32_dma2dgetvideoinfo(FAR struct dma2d_layer_s *layer,
return OK;
}
- gdbg("ERROR: Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -ENOSYS;
}
@@ -1209,7 +1209,7 @@ static int stm32_dma2dgetplaneinfo(FAR struct dma2d_layer_s *layer, int planeno,
{
FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer;
- gvdbg("layer=%p, planeno=%d, pinfo=%p\n", layer, planeno, pinfo);
+ lcdinfo("layer=%p, planeno=%d, pinfo=%p\n", layer, planeno, pinfo);
if (stm32_dma2d_lvalidate(priv) && pinfo && planeno == 0)
{
@@ -1220,7 +1220,7 @@ static int stm32_dma2dgetplaneinfo(FAR struct dma2d_layer_s *layer, int planeno,
return OK;
}
- gdbg("ERROR: Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -1244,7 +1244,7 @@ static int stm32_dma2dgetlid(FAR struct dma2d_layer_s *layer, int *lid)
{
FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer;
- gvdbg("layer=%p, lid=%p\n", layer, lid);
+ lcdinfo("layer=%p, lid=%p\n", layer, lid);
if (stm32_dma2d_lvalidate(priv) && lid)
{
@@ -1254,7 +1254,7 @@ static int stm32_dma2dgetlid(FAR struct dma2d_layer_s *layer, int *lid)
return OK;
}
- gdbg("ERROR: Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -1282,7 +1282,7 @@ static int stm32_dma2dsetclut(FAR struct dma2d_layer_s *layer,
int ret;
FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer;
- gvdbg("layer=%p, cmap=%p\n", layer, cmap);
+ lcdinfo("layer=%p, cmap=%p\n", layer, cmap);
if (stm32_dma2d_lvalidate(priv) && cmap)
{
@@ -1320,14 +1320,14 @@ static int stm32_dma2dsetclut(FAR struct dma2d_layer_s *layer,
if (priv->fmt != DMA2D_PF_L8)
{
- gdbg("Error: CLUT is not supported for the pixel format: %d\n",
- priv->vinfo.fmt);
+ lcderr("ERROR: CLUT is not supported for the pixel format: %d\n",
+ priv->vinfo.fmt);
ret = -EINVAL;
}
else if (cmap->first >= STM32_DMA2D_NCLUT)
{
- gdbg("Error: only %d color table entries supported\n",
- STM32_DMA2D_NCLUT);
+ lcderr("ERROR: only %d color table entries supported\n",
+ STM32_DMA2D_NCLUT);
ret = -EINVAL;
}
else
@@ -1349,7 +1349,7 @@ static int stm32_dma2dsetclut(FAR struct dma2d_layer_s *layer,
clut888[offset + 1] = cmap->green[n];
clut888[offset + 2] = cmap->red[n];
- regvdbg("n=%d, red=%02x, green=%02x, blue=%02x\n", n,
+ reginfo("n=%d, red=%02x, green=%02x, blue=%02x\n", n,
clut888[offset], clut888[offset + 1],
clut888[offset + 2]);
#else
@@ -1358,7 +1358,7 @@ static int stm32_dma2dsetclut(FAR struct dma2d_layer_s *layer,
(uint32_t)DMA2D_CLUT_GREEN(cmap->green[n]) |
(uint32_t)DMA2D_CLUT_BLUE(cmap->blue[n]);
- regvdbg("n=%d, alpha=%02x, red=%02x, green=%02x, blue=%02x\n", n,
+ reginfo("n=%d, alpha=%02x, red=%02x, green=%02x, blue=%02x\n", n,
DMA2D_CLUT_ALPHA(cmap->alpha[n]),
DMA2D_CLUT_RED(cmap->red[n]),
DMA2D_CLUT_GREEN(cmap->green[n]),
@@ -1374,7 +1374,7 @@ static int stm32_dma2dsetclut(FAR struct dma2d_layer_s *layer,
return ret;
}
- gdbg("ERROR: Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -1401,7 +1401,7 @@ static int stm32_dma2dgetclut(FAR struct dma2d_layer_s *layer,
int ret;
FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer;
- gvdbg("layer=%p, cmap=%p\n", layer, cmap);
+ lcdinfo("layer=%p, cmap=%p\n", layer, cmap);
if (stm32_dma2d_lvalidate(priv) && cmap)
{
@@ -1409,14 +1409,14 @@ static int stm32_dma2dgetclut(FAR struct dma2d_layer_s *layer,
if (priv->fmt != DMA2D_PF_L8)
{
- gdbg("Error: CLUT is not supported for the pixel format: %d\n",
- priv->vinfo.fmt);
+ lcderr("ERROR: CLUT is not supported for the pixel format: %d\n",
+ priv->vinfo.fmt);
ret = -EINVAL;
}
else if (cmap->first >= STM32_DMA2D_NCLUT)
{
- gdbg("Error: only %d color table entries supported\n",
- STM32_DMA2D_NCLUT);
+ lcderr("ERROR: only %d color table entries supported\n",
+ STM32_DMA2D_NCLUT);
ret = -EINVAL;
}
else
@@ -1438,7 +1438,7 @@ static int stm32_dma2dgetclut(FAR struct dma2d_layer_s *layer,
cmap->green[n] = clut888[offset + 1];
cmap->red[n] = clut888[offset + 2];
- regvdbg("n=%d, red=%02x, green=%02x, blue=%02x\n", n,
+ reginfo("n=%d, red=%02x, green=%02x, blue=%02x\n", n,
clut888[offset], clut888[offset + 1],
clut888[offset + 2]);
#else
@@ -1447,7 +1447,7 @@ static int stm32_dma2dgetclut(FAR struct dma2d_layer_s *layer,
cmap->green[n] = (uint8_t)DMA2D_CMAP_GREEN(clut[n]);
cmap->blue[n] = (uint8_t)DMA2D_CMAP_BLUE(clut[n]);
- regvdbg("n=%d, alpha=%02x, red=%02x, green=%02x, blue=%02x\n", n,
+ reginfo("n=%d, alpha=%02x, red=%02x, green=%02x, blue=%02x\n", n,
DMA2D_CMAP_ALPHA(clut[n]), DMA2D_CMAP_RED(clut[n]),
DMA2D_CMAP_GREEN(clut[n]), DMA2D_CMAP_BLUE(clut[n]));
#endif
@@ -1461,7 +1461,7 @@ static int stm32_dma2dgetclut(FAR struct dma2d_layer_s *layer,
return ret;
}
- gdbg("ERROR: Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
#endif
@@ -1491,7 +1491,7 @@ static int stm32_dma2dsetalpha(FAR struct dma2d_layer_s *layer, uint8_t alpha)
{
FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer;
- gvdbg("layer=%p, alpha=%02x\n", layer, alpha);
+ lcdinfo("layer=%p, alpha=%02x\n", layer, alpha);
if (stm32_dma2d_lvalidate(priv))
{
@@ -1502,7 +1502,7 @@ static int stm32_dma2dsetalpha(FAR struct dma2d_layer_s *layer, uint8_t alpha)
return OK;
}
- gdbg("ERROR: Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -1526,7 +1526,7 @@ static int stm32_dma2dgetalpha(FAR struct dma2d_layer_s *layer, uint8_t *alpha)
{
FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer;
- gvdbg("layer=%p, alpha=%p\n", layer, alpha);
+ lcdinfo("layer=%p, alpha=%p\n", layer, alpha);
if (stm32_dma2d_lvalidate(priv))
{
@@ -1537,7 +1537,7 @@ static int stm32_dma2dgetalpha(FAR struct dma2d_layer_s *layer, uint8_t *alpha)
return OK;
}
- gdbg("ERROR: Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -1577,7 +1577,7 @@ static int stm32_dma2dsetblendmode(FAR struct dma2d_layer_s *layer,
{
FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer;
- gvdbg("layer=%p, mode=%08x\n", layer, mode);
+ lcdinfo("layer=%p, mode=%08x\n", layer, mode);
if (stm32_dma2d_lvalidate(priv))
{
@@ -1588,7 +1588,7 @@ static int stm32_dma2dsetblendmode(FAR struct dma2d_layer_s *layer,
return OK;
}
- gdbg("ERROR: Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -1613,7 +1613,7 @@ static int stm32_dma2dgetblendmode(FAR struct dma2d_layer_s *layer,
{
FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer;
- gvdbg("layer=%p, mode=%p\n", layer, mode);
+ lcdinfo("layer=%p, mode=%p\n", layer, mode);
if (stm32_dma2d_lvalidate(priv) && mode)
{
@@ -1624,7 +1624,7 @@ static int stm32_dma2dgetblendmode(FAR struct dma2d_layer_s *layer,
return OK;
}
- gdbg("ERROR: Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -1661,8 +1661,8 @@ static int stm32_dma2dblit(FAR struct dma2d_layer_s *dest,
FAR struct stm32_dma2d_s * destlayer = (FAR struct stm32_dma2d_s *)dest;
FAR struct stm32_dma2d_s * srclayer = (FAR struct stm32_dma2d_s *)src;
- gvdbg("dest=%p, destxpos=%d, destypos=%d, src=%p, srcarea=%p\n",
- dest, destxpos, destypos, src, srcarea);
+ lcdinfo("dest=%p, destxpos=%d, destypos=%d, src=%p, srcarea=%p\n",
+ dest, destxpos, destypos, src, srcarea);
if (stm32_dma2d_lvalidatesize(destlayer, destxpos, destypos, srcarea) &&
stm32_dma2d_lvalidatesize(srclayer, srcarea->xpos,
@@ -1718,7 +1718,7 @@ static int stm32_dma2dblit(FAR struct dma2d_layer_s *dest,
if (ret != OK)
{
ret = -ECANCELED;
- gdbg("ERROR: Returning ECANCELED\n");
+ lcderr("ERROR: Returning ECANCELED\n");
}
}
@@ -1727,7 +1727,7 @@ static int stm32_dma2dblit(FAR struct dma2d_layer_s *dest,
else
{
ret = -EINVAL;
- gdbg("ERROR: Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
}
return ret;
@@ -1772,10 +1772,10 @@ static int stm32_dma2dblend(FAR struct dma2d_layer_s *dest,
FAR struct stm32_dma2d_s * forelayer = (FAR struct stm32_dma2d_s *)fore;
FAR struct stm32_dma2d_s * backlayer = (FAR struct stm32_dma2d_s *)back;
- gvdbg("dest=%p, destxpos=%d, destypos=%d, "
- "fore=%p, forexpos=%d, foreypos=%d, "
- "back=%p, backarea=%p\n",
- dest, destxpos, destypos, fore, forexpos, foreypos, back, backarea);
+ lcdinfo("dest=%p, destxpos=%d, destypos=%d, "
+ "fore=%p, forexpos=%d, foreypos=%d, "
+ "back=%p, backarea=%p\n",
+ dest, destxpos, destypos, fore, forexpos, foreypos, back, backarea);
if (stm32_dma2d_lvalidatesize(destlayer, destxpos, destypos, backarea) &&
stm32_dma2d_lvalidatesize(forelayer, forexpos, foreypos, backarea) &&
@@ -1832,7 +1832,7 @@ static int stm32_dma2dblend(FAR struct dma2d_layer_s *dest,
if (ret != OK)
{
ret = -ECANCELED;
- gdbg("ERROR: Returning ECANCELED\n");
+ lcderr("ERROR: Returning ECANCELED\n");
}
}
@@ -1841,7 +1841,7 @@ static int stm32_dma2dblend(FAR struct dma2d_layer_s *dest,
else
{
ret = -EINVAL;
- gdbg("ERROR: Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
}
return ret;
@@ -1874,7 +1874,7 @@ static int stm32_dma2dfillarea(FAR struct dma2d_layer_s *layer,
int ret;
FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer;
- gvdbg("layer=%p, area=%p, color=%08x\n", layer, area, color);
+ lcdinfo("layer=%p, area=%p, color=%08x\n", layer, area, color);
if (stm32_dma2d_lvalidatesize(priv, area->xpos, area->ypos, area))
{
@@ -1912,7 +1912,7 @@ static int stm32_dma2dfillarea(FAR struct dma2d_layer_s *layer,
if (ret != OK)
{
ret = -ECANCELED;
- gdbg("ERROR: Returning ECANCELED\n");
+ lcderr("ERROR: Returning ECANCELED\n");
}
}
@@ -1921,7 +1921,7 @@ static int stm32_dma2dfillarea(FAR struct dma2d_layer_s *layer,
else
{
ret = -EINVAL;
- gdbg("ERROR: Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
}
return ret;
@@ -1954,7 +1954,7 @@ FAR struct dma2d_layer_s * up_dma2dgetlayer(int lid)
return &priv->dma2d;
}
- gdbg("ERROR: EINVAL, Unknown layer identifier\n");
+ lcderr("ERROR: EINVAL, Unknown layer identifier\n");
errno = EINVAL;
return NULL;
}
@@ -1989,7 +1989,7 @@ FAR struct dma2d_layer_s *up_dma2dcreatelayer(fb_coord_t width,
uint8_t bpp = 0;
FAR struct stm32_dma2d_s *layer = NULL;
- gvdbg("width=%d, height=%d, fmt=%02x \n", width, height, fmt);
+ lcdinfo("width=%d, height=%d, fmt=%02x \n", width, height, fmt);
/* Validate if pixel format supported */
@@ -2069,19 +2069,19 @@ FAR struct dma2d_layer_s *up_dma2dcreatelayer(fb_coord_t width,
/* free the layer struture */
kmm_free(layer);
- gdbg("ERROR: ENOMEM, Unable to allocate layer buffer\n");
+ lcderr("ERROR: ENOMEM, Unable to allocate layer buffer\n");
errno = ENOMEM;
}
}
else
{
- gdbg("ERROR: ENOMEM, unable to allocate layer structure\n");
+ lcderr("ERROR: ENOMEM, unable to allocate layer structure\n");
errno = ENOMEM;
}
}
else
{
- gdbg("ERROR: EINVAL, no free layer available\n");
+ lcderr("ERROR: EINVAL, no free layer available\n");
errno = EINVAL;
}
@@ -2148,7 +2148,7 @@ int up_dma2dremovelayer(FAR struct dma2d_layer_s *layer)
int up_dma2dinitialize(void)
{
- dbg("Initialize DMA2D driver\n");
+ lcdinfo("Initialize DMA2D driver\n");
if (g_initialized == false)
{
@@ -2265,15 +2265,15 @@ FAR struct dma2d_layer_s * stm32_dma2dinitltdc(FAR struct stm32_ltdc_s *layer)
uint8_t fmt = 0;
FAR struct stm32_ltdc_dma2d_s *priv;
- gvdbg("layer=%p\n", layer);
+ lcdinfo("layer=%p\n", layer);
DEBUGASSERT(layer && layer->lid >= 0 && layer->lid < DMA2D_SHADOW_LAYER);
ret = stm32_dma2d_pixelformat(layer->vinfo.fmt, &fmt);
if (ret != OK)
{
- dbg("Returning -EINVAL, unsupported pixel format: %d\n",
- layer->vinfo.fmt);
+ lcderr("ERROR: Returning -EINVAL, unsupported pixel format: %d\n",
+ layer->vinfo.fmt);
errno = -EINVAL;
return NULL;
}
diff --git a/arch/arm/src/stm32/stm32_dumpgpio.c b/arch/arm/src/stm32/stm32_dumpgpio.c
index 77d49ffa084d67a2ce431536d5ca47d79883e39d..a8da3160d1950403a3bd50ba19b2539e6fad5a47 100644
--- a/arch/arm/src/stm32/stm32_dumpgpio.c
+++ b/arch/arm/src/stm32/stm32_dumpgpio.c
@@ -39,6 +39,11 @@
#include
+/* Output debug info even if debug output is not selected. */
+
+#undef CONFIG_DEBUG_INFO
+#define CONFIG_DEBUG_INFO 1
+
#include
#include
@@ -49,14 +54,13 @@
#include "stm32_gpio.h"
#include "stm32_rcc.h"
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
/****************************************************************************
* Private Data
****************************************************************************/
/* Port letters for prettier debug output */
-#ifdef CONFIG_DEBUG
static const char g_portchar[STM32_NGPIO_PORTS] =
{
#if STM32_NGPIO_PORTS > 11
@@ -87,15 +91,6 @@ static const char g_portchar[STM32_NGPIO_PORTS] =
# error "Bad number of GPIOs"
#endif
};
-#endif
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
/****************************************************************************
* Public Functions
@@ -125,110 +120,106 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
flags = enter_critical_section();
#if defined(CONFIG_STM32_STM32F10XX)
-
- lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
- g_portchar[port], pinset, base, msg);
+ _info("GPIO%c pinset: %08x base: %08x -- %s\n",
+ g_portchar[port], pinset, base, msg);
if ((getreg32(STM32_RCC_APB2ENR) & RCC_APB2ENR_IOPEN(port)) != 0)
{
- lldbg(" CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n",
- getreg32(base + STM32_GPIO_CRH_OFFSET),
- getreg32(base + STM32_GPIO_CRL_OFFSET),
- getreg32(base + STM32_GPIO_IDR_OFFSET),
- getreg32(base + STM32_GPIO_ODR_OFFSET),
- getreg32(base + STM32_GPIO_LCKR_OFFSET));
- lldbg(" EVCR: %02x MAPR: %08x CR: %04x %04x %04x %04x\n",
- getreg32(STM32_AFIO_EVCR), getreg32(STM32_AFIO_MAPR),
- getreg32(STM32_AFIO_EXTICR1),
- getreg32(STM32_AFIO_EXTICR2),
- getreg32(STM32_AFIO_EXTICR3),
- getreg32(STM32_AFIO_EXTICR4));
+ _info(" CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n",
+ getreg32(base + STM32_GPIO_CRH_OFFSET),
+ getreg32(base + STM32_GPIO_CRL_OFFSET),
+ getreg32(base + STM32_GPIO_IDR_OFFSET),
+ getreg32(base + STM32_GPIO_ODR_OFFSET),
+ getreg32(base + STM32_GPIO_LCKR_OFFSET));
+ _info(" EVCR: %02x MAPR: %08x CR: %04x %04x %04x %04x\n",
+ getreg32(STM32_AFIO_EVCR), getreg32(STM32_AFIO_MAPR),
+ getreg32(STM32_AFIO_EXTICR1),
+ getreg32(STM32_AFIO_EXTICR2),
+ getreg32(STM32_AFIO_EXTICR3),
+ getreg32(STM32_AFIO_EXTICR4));
}
else
{
- lldbg(" GPIO%c not enabled: APB2ENR: %08x\n",
- g_portchar[port], getreg32(STM32_RCC_APB2ENR));
+ _info(" GPIO%c not enabled: APB2ENR: %08x\n",
+ g_portchar[port], getreg32(STM32_RCC_APB2ENR));
}
#elif defined(CONFIG_STM32_STM32L15XX)
-
DEBUGASSERT(port < STM32_NGPIO_PORTS);
- lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
+ _info("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
if ((getreg32(STM32_RCC_AHBENR) & RCC_AHBENR_GPIOEN(port)) != 0)
{
- lldbg(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
- getreg32(base + STM32_GPIO_MODER_OFFSET),
- getreg32(base + STM32_GPIO_OTYPER_OFFSET),
- getreg32(base + STM32_GPIO_OSPEED_OFFSET),
- getreg32(base + STM32_GPIO_PUPDR_OFFSET));
- lldbg(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
- getreg32(base + STM32_GPIO_IDR_OFFSET),
- getreg32(base + STM32_GPIO_ODR_OFFSET),
- getreg32(base + STM32_GPIO_BSRR_OFFSET),
- getreg32(base + STM32_GPIO_LCKR_OFFSET));
- lldbg(" AFRH: %08x AFRL: %08x\n",
- getreg32(base + STM32_GPIO_AFRH_OFFSET),
- getreg32(base + STM32_GPIO_AFRL_OFFSET));
+ _info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
+ getreg32(base + STM32_GPIO_MODER_OFFSET),
+ getreg32(base + STM32_GPIO_OTYPER_OFFSET),
+ getreg32(base + STM32_GPIO_OSPEED_OFFSET),
+ getreg32(base + STM32_GPIO_PUPDR_OFFSET));
+ _info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
+ getreg32(base + STM32_GPIO_IDR_OFFSET),
+ getreg32(base + STM32_GPIO_ODR_OFFSET),
+ getreg32(base + STM32_GPIO_BSRR_OFFSET),
+ getreg32(base + STM32_GPIO_LCKR_OFFSET));
+ _info(" AFRH: %08x AFRL: %08x\n",
+ getreg32(base + STM32_GPIO_AFRH_OFFSET),
+ getreg32(base + STM32_GPIO_AFRL_OFFSET));
}
else
{
- lldbg(" GPIO%c not enabled: AHBENR: %08x\n",
+ _info(" GPIO%c not enabled: AHBENR: %08x\n",
g_portchar[port], getreg32(STM32_RCC_AHBENR));
}
#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
-
DEBUGASSERT(port < STM32_NGPIO_PORTS);
- lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
+ _info("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
/* GPIOs are always enabled */
- lldbg(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
+ _info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
getreg32(base + STM32_GPIO_MODER_OFFSET),
getreg32(base + STM32_GPIO_OTYPER_OFFSET),
getreg32(base + STM32_GPIO_OSPEED_OFFSET),
getreg32(base + STM32_GPIO_PUPDR_OFFSET));
- lldbg(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
+ _info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
getreg32(base + STM32_GPIO_IDR_OFFSET),
getreg32(base + STM32_GPIO_ODR_OFFSET),
getreg32(base + STM32_GPIO_BSRR_OFFSET),
getreg32(base + STM32_GPIO_LCKR_OFFSET));
- lldbg(" AFRH: %08x AFRL: %08x BRR: %04x\n",
+ _info(" AFRH: %08x AFRL: %08x BRR: %04x\n",
getreg32(base + STM32_GPIO_AFRH_OFFSET),
getreg32(base + STM32_GPIO_AFRL_OFFSET),
getreg32(base + STM32_GPIO_BRR_OFFSET));
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
-
DEBUGASSERT(port < STM32_NGPIO_PORTS);
- lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
+ _info("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
if ((getreg32(STM32_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0)
{
- lldbg(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
+ _info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
getreg32(base + STM32_GPIO_MODER_OFFSET),
getreg32(base + STM32_GPIO_OTYPER_OFFSET),
getreg32(base + STM32_GPIO_OSPEED_OFFSET),
getreg32(base + STM32_GPIO_PUPDR_OFFSET));
- lldbg(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
+ _info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
getreg32(base + STM32_GPIO_IDR_OFFSET),
getreg32(base + STM32_GPIO_ODR_OFFSET),
getreg32(base + STM32_GPIO_BSRR_OFFSET),
getreg32(base + STM32_GPIO_LCKR_OFFSET));
- lldbg(" AFRH: %08x AFRL: %08x\n",
+ _info(" AFRH: %08x AFRL: %08x\n",
getreg32(base + STM32_GPIO_AFRH_OFFSET),
getreg32(base + STM32_GPIO_AFRL_OFFSET));
}
else
{
- lldbg(" GPIO%c not enabled: AHB1ENR: %08x\n",
+ _info(" GPIO%c not enabled: AHB1ENR: %08x\n",
g_portchar[port], getreg32(STM32_RCC_AHB1ENR));
}
#else
@@ -238,4 +229,4 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
return OK;
}
-#endif /* CONFIG_DEBUG */
+#endif /* CONFIG_DEBUG_FEATURES */
diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c
index 7b06b9a3680d296a6e3d254d3aa2d02bcdf320e8..bced5def66102aadb0b09c1545e518e2fd27681c 100644
--- a/arch/arm/src/stm32/stm32_eth.c
+++ b/arch/arm/src/stm32/stm32_eth.c
@@ -240,7 +240,7 @@
* enabled.
*/
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_NET_INFO
# undef CONFIG_STM32_ETHMAC_REGDEBUG
#endif
@@ -585,9 +585,9 @@ struct stm32_ethmac_s
struct work_s work; /* For deferring work to the work queue */
#endif
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
/* Used to track transmit and receive descriptors */
@@ -622,7 +622,7 @@ static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET];
****************************************************************************/
/* Register operations ******************************************************/
-#if defined(CONFIG_STM32_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG)
+#if defined(CONFIG_STM32_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
static uint32_t stm32_getreg(uint32_t addr);
static void stm32_putreg(uint32_t val, uint32_t addr);
static void stm32_checksetup(void);
@@ -748,7 +748,7 @@ static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv);
*
****************************************************************************/
-#if defined(CONFIG_STM32_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_STM32_ETHMAC_REGDEBUG
static uint32_t stm32_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@@ -769,7 +769,7 @@ static uint32_t stm32_getreg(uint32_t addr)
{
if (count == 4)
{
- lldbg("...\n");
+ ninfo("...\n");
}
return val;
@@ -786,7 +786,7 @@ static uint32_t stm32_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ ninfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -798,7 +798,7 @@ static uint32_t stm32_getreg(uint32_t addr)
/* Show the register value read */
- lldbg("%08x->%08x\n", addr, val);
+ ninfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@@ -820,12 +820,12 @@ static uint32_t stm32_getreg(uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_STM32_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG)
+#if defined(CONFIG_STM32_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
static void stm32_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- lldbg("%08x<-%08x\n", addr, val);
+ ninfo("%08x<-%08x\n", addr, val);
/* Write the value */
@@ -847,7 +847,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_STM32_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_STM32_ETHMAC_REGDEBUG
static void stm32_checksetup(void)
{
}
@@ -993,7 +993,7 @@ static int stm32_transmit(FAR struct stm32_ethmac_s *priv)
struct eth_txdesc_s *txdesc;
struct eth_txdesc_s *txfirst;
- /* The internal (optimal) uIP buffer size may be configured to be larger
+ /* The internal (optimal) network buffer size may be configured to be larger
* than the Ethernet buffer size.
*/
@@ -1012,8 +1012,8 @@ static int stm32_transmit(FAR struct stm32_ethmac_s *priv)
txdesc = priv->txhead;
txfirst = txdesc;
- nllvdbg("d_len: %d d_buf: %p txhead: %p tdes0: %08x\n",
- priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0);
+ ninfo("d_len: %d d_buf: %p txhead: %p tdes0: %08x\n",
+ priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0);
DEBUGASSERT(txdesc && (txdesc->tdes0 & ETH_TDES0_OWN) == 0);
@@ -1029,7 +1029,7 @@ static int stm32_transmit(FAR struct stm32_ethmac_s *priv)
bufcount = (priv->dev.d_len + (CONFIG_STM32_ETH_BUFSIZE-1)) / CONFIG_STM32_ETH_BUFSIZE;
lastsize = priv->dev.d_len - (bufcount - 1) * CONFIG_STM32_ETH_BUFSIZE;
- nllvdbg("bufcount: %d lastsize: %d\n", bufcount, lastsize);
+ ninfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
/* Set the first segment bit in the first TX descriptor */
@@ -1139,8 +1139,8 @@ static int stm32_transmit(FAR struct stm32_ethmac_s *priv)
priv->inflight++;
- nllvdbg("txhead: %p txtail: %p inflight: %d\n",
- priv->txhead, priv->txtail, priv->inflight);
+ ninfo("txhead: %p txtail: %p inflight: %d\n",
+ priv->txhead, priv->txtail, priv->inflight);
/* If all TX descriptors are in-flight, then we have to disable receive interrupts
* too. This is because receive events can trigger more un-stoppable transmit
@@ -1179,7 +1179,7 @@ static int stm32_transmit(FAR struct stm32_ethmac_s *priv)
* Function: stm32_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -1321,7 +1321,7 @@ static void stm32_dopoll(FAR struct stm32_ethmac_s *priv)
if ((priv->txhead->tdes0 & ETH_TDES0_OWN) == 0 &&
priv->txhead->tdes2 == 0)
{
- /* If we have the descriptor, then poll uIP for new XMIT data.
+ /* If we have the descriptor, then poll the network for new XMIT data.
* Allocate a buffer for the poll.
*/
@@ -1438,7 +1438,7 @@ static void stm32_freesegment(FAR struct stm32_ethmac_s *priv,
struct eth_rxdesc_s *rxdesc;
int i;
- nllvdbg("rxfirst: %p segments: %d\n", rxfirst, segments);
+ ninfo("rxfirst: %p segments: %d\n", rxfirst, segments);
/* Set OWN bit in RX descriptors. This gives the buffers back to DMA */
@@ -1496,8 +1496,8 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
uint8_t *buffer;
int i;
- nllvdbg("rxhead: %p rxcurr: %p segments: %d\n",
- priv->rxhead, priv->rxcurr, priv->segments);
+ ninfo("rxhead: %p rxcurr: %p segments: %d\n",
+ priv->rxhead, priv->rxcurr, priv->segments);
/* Check if there are free buffers. We cannot receive new frames in this
* design unless there is at least one free buffer.
@@ -1505,7 +1505,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
if (!stm32_isfreebuffer(priv))
{
- nlldbg("No free buffers\n");
+ nerr("ERROR: No free buffers\n");
return -ENOMEM;
}
@@ -1562,7 +1562,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
rxcurr = priv->rxcurr;
}
- nllvdbg("rxhead: %p rxcurr: %p segments: %d\n",
+ ninfo("rxhead: %p rxcurr: %p segments: %d\n",
priv->rxhead, priv->rxcurr, priv->segments);
/* Check if any errors are reported in the frame */
@@ -1585,7 +1585,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
buffer = stm32_allocbuffer(priv);
/* Take the buffer from the RX descriptor of the first free
- * segment, put it into the uIP device structure, then replace
+ * segment, put it into the network device structure, then replace
* the buffer in the RX descriptor with the newly allocated
* buffer.
*/
@@ -1601,8 +1601,8 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
priv->rxhead = (struct eth_rxdesc_s *)rxdesc->rdes3;
stm32_freesegment(priv, rxcurr, priv->segments);
- nllvdbg("rxhead: %p d_buf: %p d_len: %d\n",
- priv->rxhead, dev->d_buf, dev->d_len);
+ ninfo("rxhead: %p d_buf: %p d_len: %d\n",
+ priv->rxhead, dev->d_buf, dev->d_len);
return OK;
}
@@ -1612,7 +1612,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
* scanning logic, and continue scanning with the next frame.
*/
- nlldbg("DROPPED: RX descriptor errors: %08x\n", rxdesc->rdes0);
+ nerr("ERROR: Dropped, RX descriptor errors: %08x\n", rxdesc->rdes0);
stm32_freesegment(priv, rxcurr, priv->segments);
}
}
@@ -1628,8 +1628,8 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
priv->rxhead = rxdesc;
- nllvdbg("rxhead: %p rxcurr: %p segments: %d\n",
- priv->rxhead, priv->rxcurr, priv->segments);
+ ninfo("rxhead: %p rxcurr: %p segments: %d\n",
+ priv->rxhead, priv->rxcurr, priv->segments);
return -EAGAIN;
}
@@ -1667,13 +1667,13 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
pkt_input(&priv->dev);
#endif
- /* Check if the packet is a valid size for the uIP buffer configuration
+ /* Check if the packet is a valid size for the network buffer configuration
* (this should not happen)
*/
if (dev->d_len > CONFIG_NET_ETH_MTU)
{
- nlldbg("DROPPED: Too big: %d\n", dev->d_len);
+ nerr("ERROR: Dropped, Too big: %d\n", dev->d_len);
/* Free dropped packet buffer */
@@ -1698,7 +1698,7 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
- nllvdbg("IPv4 frame\n");
+ ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@@ -1738,7 +1738,7 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
- nllvdbg("Iv6 frame\n");
+ ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@@ -1775,7 +1775,7 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
- nllvdbg("ARP frame\n");
+ ninfo("ARP frame\n");
/* Handle ARP packet */
@@ -1793,7 +1793,7 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
else
#endif
{
- nlldbg("DROPPED: Unknown type: %04x\n", BUF->type);
+ nerr("ERROR: Dropped, Unknown type: %04x\n", BUF->type);
}
/* We are finished with the RX buffer. NOTE: If the buffer is
@@ -1834,8 +1834,8 @@ static void stm32_freeframe(FAR struct stm32_ethmac_s *priv)
struct eth_txdesc_s *txdesc;
int i;
- nllvdbg("txhead: %p txtail: %p inflight: %d\n",
- priv->txhead, priv->txtail, priv->inflight);
+ ninfo("txhead: %p txtail: %p inflight: %d\n",
+ priv->txhead, priv->txtail, priv->inflight);
/* Scan for "in-flight" descriptors owned by the CPU */
@@ -1850,8 +1850,8 @@ static void stm32_freeframe(FAR struct stm32_ethmac_s *priv)
* TX descriptors.
*/
- nllvdbg("txtail: %p tdes0: %08x tdes2: %08x tdes3: %08x\n",
- txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3);
+ ninfo("txtail: %p tdes0: %08x tdes2: %08x tdes3: %08x\n",
+ txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3);
DEBUGASSERT(txdesc->tdes2 != 0);
@@ -1903,8 +1903,8 @@ static void stm32_freeframe(FAR struct stm32_ethmac_s *priv)
priv->txtail = txdesc;
- nllvdbg("txhead: %p txtail: %p inflight: %d\n",
- priv->txhead, priv->txtail, priv->inflight);
+ ninfo("txhead: %p txtail: %p inflight: %d\n",
+ priv->txhead, priv->txtail, priv->inflight);
}
}
@@ -1955,7 +1955,7 @@ static void stm32_txdone(FAR struct stm32_ethmac_s *priv)
stm32_disableint(priv, ETH_DMAINT_TI);
}
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
stm32_dopoll(priv);
}
@@ -2042,7 +2042,7 @@ static inline void stm32_interrupt_process(FAR struct stm32_ethmac_s *priv)
{
/* Just let the user know what happened */
- nlldbg("Abormal event(s): %08x\n", dmasr);
+ nerr("ERROR: Abormal event(s): %08x\n", dmasr);
/* Clear all pending abnormal events */
@@ -2246,7 +2246,7 @@ static void stm32_txtimeout_expiry(int argc, uint32_t arg, ...)
{
FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)arg;
- nlldbg("Timeout!\n");
+ nerr("ERROR: Timeout!\n");
#ifdef CONFIG_NET_NOINTS
/* Disable further Ethernet interrupts. This will prevent some race
@@ -2321,7 +2321,7 @@ static inline void stm32_poll_process(FAR struct stm32_ethmac_s *priv)
if (dev->d_buf)
{
- /* Update TCP timing states and poll uIP for new XMIT data.
+ /* Update TCP timing states and poll the network for new XMIT data.
*/
(void)devif_timer(dev, stm32_txpoll);
@@ -2447,15 +2447,15 @@ static int stm32_ifup(struct net_driver_s *dev)
int ret;
#ifdef CONFIG_NET_IPv4
- ndbg("Bringing up: %d.%d.%d.%d\n",
- dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+ ninfo("Bringing up: %d.%d.%d.%d\n",
+ dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
#endif
#ifdef CONFIG_NET_IPv6
- ndbg("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n",
- dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2],
- dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5],
- dev->d_ipv6addr[6], dev->d_ipv6addr[7]);
+ ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n",
+ dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2],
+ dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5],
+ dev->d_ipv6addr[6], dev->d_ipv6addr[7]);
#endif
/* Configure the Ethernet interface for DMA operation. */
@@ -2500,7 +2500,7 @@ static int stm32_ifdown(struct net_driver_s *dev)
FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)dev->d_private;
irqstate_t flags;
- ndbg("Taking the network down\n");
+ ninfo("Taking the network down\n");
/* Disable the Ethernet interrupt */
@@ -2545,13 +2545,13 @@ static int stm32_ifdown(struct net_driver_s *dev)
static inline void stm32_txavail_process(FAR struct stm32_ethmac_s *priv)
{
- nvdbg("ifup: %d\n", priv->ifup);
+ ninfo("ifup: %d\n", priv->ifup);
/* Ignore the notification if the interface is not yet up */
if (priv->ifup)
{
- /* Poll uIP for new XMIT data */
+ /* Poll the network for new XMIT data */
stm32_dopoll(priv);
}
@@ -2712,8 +2712,8 @@ static int stm32_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
uint32_t temp;
uint32_t registeraddress;
- nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Add the MAC address to the hardware multicast hash table */
@@ -2769,8 +2769,8 @@ static int stm32_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
uint32_t temp;
uint32_t registeraddress;
- nllvdbg("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Remove the MAC address to the hardware multicast hash table */
@@ -3129,7 +3129,7 @@ static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *val
}
}
- ndbg("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x\n",
+ nerr("ERROR: MII transfer timed out: phydevaddr: %04x phyregaddr: %04x\n",
phydevaddr, phyregaddr);
return -ETIMEDOUT;
@@ -3188,7 +3188,7 @@ static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t val
}
}
- ndbg("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x value: %04x\n",
+ nerr("ERROR: MII transfer timed out: phydevaddr: %04x phyregaddr: %04x value: %04x\n",
phydevaddr, phyregaddr, value);
return -ETIMEDOUT;
@@ -3225,7 +3225,7 @@ static inline int stm32_dm9161(FAR struct stm32_ethmac_s *priv)
ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval);
if (ret < 0)
{
- ndbg("Failed to read the PHY ID1: %d\n", ret);
+ nerr("ERROR: Failed to read the PHY ID1: %d\n", ret);
return ret;
}
@@ -3236,14 +3236,14 @@ static inline int stm32_dm9161(FAR struct stm32_ethmac_s *priv)
up_systemreset();
}
- nvdbg("PHY ID1: 0x%04X\n", phyval);
+ ninfo("PHY ID1: 0x%04X\n", phyval);
/* Now check the "DAVICOM Specified Configuration Register (DSCR)", Register 16 */
ret = stm32_phyread(CONFIG_STM32_PHYADDR, 16, &phyval);
if (ret < 0)
{
- ndbg("Failed to read the PHY Register 0x10: %d\n", ret);
+ nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret);
return ret;
}
@@ -3300,7 +3300,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_RESET);
if (ret < 0)
{
- ndbg("Failed to reset the PHY: %d\n", ret);
+ nerr("ERROR: Failed to reset the PHY: %d\n", ret);
return ret;
}
up_mdelay(PHY_RESET_DELAY);
@@ -3311,7 +3311,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
ret = stm32_phy_boardinitialize(0);
if (ret < 0)
{
- ndbg("Failed to initialize the PHY: %d\n", ret);
+ nerr("ERROR: Failed to initialize the PHY: %d\n", ret);
return ret;
}
#endif
@@ -3336,7 +3336,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval);
if (ret < 0)
{
- ndbg("Failed to read the PHY MSR: %d\n", ret);
+ nerr("ERROR: Failed to read the PHY MSR: %d\n", ret);
return ret;
}
else if ((phyval & MII_MSR_LINKSTATUS) != 0)
@@ -3347,7 +3347,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
if (timeout >= PHY_RETRY_TIMEOUT)
{
- ndbg("Timed out waiting for link status: %04x\n", phyval);
+ nerr("ERROR: Timed out waiting for link status: %04x\n", phyval);
return -ETIMEDOUT;
}
@@ -3356,7 +3356,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_ANENABLE);
if (ret < 0)
{
- ndbg("Failed to enable auto-negotiation: %d\n", ret);
+ nerr("ERROR: Failed to enable auto-negotiation: %d\n", ret);
return ret;
}
@@ -3367,7 +3367,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval);
if (ret < 0)
{
- ndbg("Failed to read the PHY MSR: %d\n", ret);
+ nerr("ERROR: Failed to read the PHY MSR: %d\n", ret);
return ret;
}
else if ((phyval & MII_MSR_ANEGCOMPLETE) != 0)
@@ -3378,7 +3378,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
if (timeout >= PHY_RETRY_TIMEOUT)
{
- ndbg("Timed out waiting for auto-negotiation\n");
+ nerr("ERROR: Timed out waiting for auto-negotiation\n");
return -ETIMEDOUT;
}
@@ -3387,13 +3387,13 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
ret = stm32_phyread(CONFIG_STM32_PHYADDR, CONFIG_STM32_PHYSR, &phyval);
if (ret < 0)
{
- ndbg("Failed to read PHY status register\n");
+ nerr("ERROR: Failed to read PHY status register\n");
return ret;
}
/* Remember the selected speed and duplex modes */
- nvdbg("PHYSR[%d]: %04x\n", CONFIG_STM32_PHYSR, phyval);
+ ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32_PHYSR, phyval);
/* Different PHYs present speed and mode information in different ways. IF
* This CONFIG_STM32_PHYSR_ALTCONFIG is selected, this indicates that the PHY
@@ -3457,7 +3457,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, phyval);
if (ret < 0)
{
- ndbg("Failed to write the PHY MCR: %d\n", ret);
+ nerr("ERROR: Failed to write the PHY MCR: %d\n", ret);
return ret;
}
up_mdelay(PHY_CONFIG_DELAY);
@@ -3472,9 +3472,9 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
#endif
#endif
- ndbg("Duplex: %s Speed: %d MBps\n",
- priv->fduplex ? "FULL" : "HALF",
- priv->mbps100 ? 100 : 10);
+ ninfo("Duplex: %s Speed: %d MBps\n",
+ priv->fduplex ? "FULL" : "HALF",
+ priv->mbps100 ? 100 : 10);
return OK;
}
@@ -3853,11 +3853,11 @@ static void stm32_macaddress(FAR struct stm32_ethmac_s *priv)
FAR struct net_driver_s *dev = &priv->dev;
uint32_t regval;
- nllvdbg("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- dev->d_ifname,
- dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
- dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
- dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
+ ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ dev->d_ifname,
+ dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+ dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+ dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
/* Set the MAC address high register */
@@ -3921,7 +3921,7 @@ static void stm32_ipv6multicast(FAR struct stm32_ethmac_s *priv)
mac[4] = tmp16 & 0xff;
mac[5] = tmp16 >> 8;
- nvdbg("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
(void)stm32_addmac(dev, mac);
@@ -4059,12 +4059,12 @@ static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv)
/* Reset the Ethernet block */
- nllvdbg("Reset the Ethernet block\n");
+ ninfo("Reset the Ethernet block\n");
stm32_ethreset(priv);
/* Initialize the PHY */
- nllvdbg("Initialize the PHY\n");
+ ninfo("Initialize the PHY\n");
ret = stm32_phyinit(priv);
if (ret < 0)
{
@@ -4073,7 +4073,7 @@ static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv)
/* Initialize the MAC and DMA */
- nllvdbg("Initialize the MAC and DMA\n");
+ ninfo("Initialize the MAC and DMA\n");
ret = stm32_macconfig(priv);
if (ret < 0)
{
@@ -4094,7 +4094,7 @@ static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv)
/* Enable normal MAC operation */
- nllvdbg("Enable normal operation\n");
+ ninfo("Enable normal operation\n");
return stm32_macenable(priv);
}
@@ -4130,7 +4130,7 @@ int stm32_ethinitialize(int intf)
{
struct stm32_ethmac_s *priv;
- nvdbg("intf: %d\n", intf);
+ ninfo("intf: %d\n", intf);
/* Get the interface structure associated with this interface number. */
diff --git a/arch/arm/src/stm32/stm32_getc.c b/arch/arm/src/stm32/stm32_getc.c
new file mode 100644
index 0000000000000000000000000000000000000000..de9020bab40cab8fd0a06dcaba3011ed72d7c847
--- /dev/null
+++ b/arch/arm/src/stm32/stm32_getc.c
@@ -0,0 +1,121 @@
+/****************************************************************************
+ * arch/arm/src/stm32/stm32_getc.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+
+#include
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+
+#include "stm32.h"
+#include "stm32_rcc.h"
+#include "stm32_gpio.h"
+#include "stm32_uart.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Select U[S]ART console base address */
+
+#ifdef HAVE_CONSOLE
+# if defined(CONFIG_USART1_SERIAL_CONSOLE)
+# define STM32_CONSOLE_BASE STM32_USART1_BASE
+# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
+# define STM32_CONSOLE_BASE STM32_USART2_BASE
+# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
+# define STM32_CONSOLE_BASE STM32_USART3_BASE
+# elif defined(CONFIG_UART4_SERIAL_CONSOLE)
+# define STM32_CONSOLE_BASE STM32_UART4_BASE
+# elif defined(CONFIG_UART5_SERIAL_CONSOLE)
+# define STM32_CONSOLE_BASE STM32_UART5_BASE
+# elif defined(CONFIG_USART6_SERIAL_CONSOLE)
+# define STM32_CONSOLE_BASE STM32_USART6_BASE
+# elif defined(CONFIG_UART7_SERIAL_CONSOLE)
+# define STM32_CONSOLE_BASE STM32_UART7_BASE
+# elif defined(CONFIG_UART8_SERIAL_CONSOLE)
+# define STM32_CONSOLE_BASE STM32_UART8_BASE
+# endif
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_getc
+ *
+ * Description:
+ * Read one byte from the serial console
+ *
+ * REVIST: If used with the serial driver enabled, then this could
+ * interfere with the serial driver operations. Serial interrupts should
+ * be disabled when this function executes in that case.
+ *
+ ****************************************************************************/
+
+int up_getc(void)
+{
+ uint32_t ch = 0;
+
+#ifdef HAVE_CONSOLE
+ /* While there is any error, read and discard bytes to clear the errors */
+
+ while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) &
+ (USART_SR_ORE | USART_SR_NE | USART_SR_FE | USART_SR_PE)) != 0)
+ {
+ (void)getreg32(STM32_CONSOLE_BASE + STM32_USART_RDR_OFFSET);
+ }
+
+ /* Wait until the RX data register has a character to be read */
+
+ while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & USART_SR_RXNE) == 0);
+
+ /* Then read the character */
+
+ ch = getreg32(STM32_CONSOLE_BASE + STM32_USART_RDR_OFFSET);
+#endif /* HAVE_CONSOLE */
+
+ return (int)ch;
+}
diff --git a/arch/arm/src/stm32/stm32_getc.h b/arch/arm/src/stm32/stm32_getc.h
new file mode 100644
index 0000000000000000000000000000000000000000..651165fba5ed562dcb856275ff70482068bb5750
--- /dev/null
+++ b/arch/arm/src/stm32/stm32_getc.h
@@ -0,0 +1,47 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_getc.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_GETC_H
+#define __ARCH_ARM_SRC_STM32_STM32_GETC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_GETC_H */
diff --git a/arch/arm/src/stm32/stm32_gpio.c b/arch/arm/src/stm32/stm32_gpio.c
index 6426107b3b490130526aa6cc525e9ece4114a2d8..63d09e982e48ddafb33674c357827e3238fa39fb 100644
--- a/arch/arm/src/stm32/stm32_gpio.c
+++ b/arch/arm/src/stm32/stm32_gpio.c
@@ -469,6 +469,7 @@ int stm32_configgpio(uint32_t cfgset)
break;
case GPIO_OUTPUT: /* General purpose output mode */
+ stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */
pinmode = GPIO_MODER_OUTPUT;
break;
@@ -619,17 +620,9 @@ int stm32_configgpio(uint32_t cfgset)
putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET);
- /* If it is an output... set the pin to the correct initial state. */
-
- if (pinmode == GPIO_MODER_OUTPUT)
- {
- bool value = ((cfgset & GPIO_OUTPUT_SET) != 0);
- stm32_gpiowrite(cfgset, value);
- }
-
/* Otherwise, it is an input pin. Should it configured as an EXTI interrupt? */
- else if ((cfgset & GPIO_EXTI) != 0)
+ if (pinmode != GPIO_MODER_OUTPUT && (cfgset & GPIO_EXTI) != 0)
{
/* "In STM32 F1 the selection of the EXTI line source is performed through
* the EXTIx bits in the AFIO_EXTICRx registers, while in F2 series this
diff --git a/arch/arm/src/stm32/stm32_gpio.h b/arch/arm/src/stm32/stm32_gpio.h
index c1790eaaaa3f8693950edbbb1a1cc68a89bb273a..34b49bf0d6da1d2dc9e2f5b31f167de6ca18114d 100644
--- a/arch/arm/src/stm32/stm32_gpio.h
+++ b/arch/arm/src/stm32/stm32_gpio.h
@@ -510,7 +510,7 @@ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
*
************************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
int stm32_dumpgpio(uint32_t pinset, const char *msg);
#else
# define stm32_dumpgpio(p,m)
diff --git a/arch/arm/src/stm32/stm32_i2c.c b/arch/arm/src/stm32/stm32_i2c.c
index 6d06098b018b18db0785a0004d8677ac3ce499ee..9f41597f04d4340806ff5341af9869b8a0c27f9c 100644
--- a/arch/arm/src/stm32/stm32_i2c.c
+++ b/arch/arm/src/stm32/stm32_i2c.c
@@ -162,15 +162,6 @@
#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT)
/* Debug ****************************************************************************/
-/* CONFIG_DEBUG_I2C + CONFIG_DEBUG enables general I2C debug output. */
-
-#ifdef CONFIG_DEBUG_I2C
-# define i2cdbg dbg
-# define i2cvdbg vdbg
-#else
-# define i2cdbg(x...)
-# define i2cvdbg(x...)
-#endif
/* I2C event trace logic. NOTE: trace uses the internal, non-standard, low-level
* debug interface syslog() but does not require that any other debug
@@ -693,7 +684,7 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
while (priv->intstate != INTSTATE_DONE && elapsed < timeout);
- i2cvdbg("intstate: %d elapsed: %ld threshold: %ld status: %08x\n",
+ i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: %08x\n",
priv->intstate, (long)elapsed, (long)timeout, priv->status);
/* Set the interrupt state back to IDLE */
@@ -766,7 +757,7 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
* still pending.
*/
- i2cvdbg("Timeout with CR1: %04x SR1: %04x\n", cr1, sr1);
+ i2cinfo("Timeout with CR1: %04x SR1: %04x\n", cr1, sr1);
}
/************************************************************************************
@@ -859,7 +850,7 @@ static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t statu
if (priv->tndx >= (CONFIG_I2C_NTRACE-1))
{
- i2cdbg("Trace table overflow\n");
+ i2cerr("ERROR: Trace table overflow\n");
return;
}
@@ -900,7 +891,7 @@ static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv,
if (priv->tndx >= (CONFIG_I2C_NTRACE-1))
{
- i2cdbg("Trace table overflow\n");
+ i2cerr("ERROR: Trace table overflow\n");
return;
}
@@ -1695,7 +1686,7 @@ static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
status = stm32_i2c_getstatus(priv);
ret = -ETIMEDOUT;
- i2cdbg("Timed out: CR1: 0x%04x status: 0x%08x\n",
+ i2cerr("ERROR: Timed out: CR1: 0x%04x status: 0x%08x\n",
stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status);
/* "Note: When the STOP, START or PEC bit is set, the software must
diff --git a/arch/arm/src/stm32/stm32_i2c_alt.c b/arch/arm/src/stm32/stm32_i2c_alt.c
index da50a9c263508f6aa96817462596fe2e88ba2c7b..ac2ea5f6071174095d67621a837a235850e3993a 100644
--- a/arch/arm/src/stm32/stm32_i2c_alt.c
+++ b/arch/arm/src/stm32/stm32_i2c_alt.c
@@ -169,15 +169,6 @@
#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT)
/* Debug ****************************************************************************/
-/* CONFIG_DEBUG_I2C + CONFIG_DEBUG enables general I2C debug output. */
-
-#ifdef CONFIG_DEBUG_I2C
-# define i2cdbg dbg
-# define i2cvdbg vdbg
-#else
-# define i2cdbg(x...)
-# define i2cvdbg(x...)
-#endif
/* I2C event trace logic. NOTE: trace uses the internal, non-standard, low-level
* debug interface syslog() but does not require that any other debug
@@ -701,7 +692,7 @@ static int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
while (priv->intstate != INTSTATE_DONE && elapsed < timeout);
- i2cvdbg("intstate: %d elapsed: %ld threshold: %ld status: %08x\n",
+ i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: %08x\n",
priv->intstate, (long)elapsed, (long)timeout, priv->status);
/* Set the interrupt state back to IDLE */
@@ -774,7 +765,7 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
* still pending.
*/
- i2cvdbg("Timeout with CR1: %04x SR1: %04x\n", cr1, sr1);
+ i2cinfo("Timeout with CR1: %04x SR1: %04x\n", cr1, sr1);
}
/************************************************************************************
@@ -867,7 +858,7 @@ static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint16_t statu
if (priv->tndx >= (CONFIG_I2C_NTRACE-1))
{
- i2cdbg("Trace table overflow\n");
+ i2cerr("ERROR: Trace table overflow\n");
return;
}
@@ -908,7 +899,7 @@ static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv,
if (priv->tndx >= (CONFIG_I2C_NTRACE-1))
{
- i2cdbg("Trace table overflow\n");
+ i2cerr("ERROR: Trace table overflow\n");
return;
}
@@ -1208,7 +1199,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
{
uint32_t status;
- i2cvdbg("I2C ISR called\n");
+ i2cinfo("I2C ISR called\n");
/* Get state of the I2C controller (register SR1 only)
*
@@ -1252,7 +1243,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
if (priv->dcnt == -1 && priv->msgc > 0)
{
- i2cvdbg("Switch to new message\n");
+ i2cinfo("Switch to new message\n");
/* Get current message to process data and copy to private structure */
@@ -1261,7 +1252,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
priv->total_msg_len = priv->msgv->length; /* Set total msg length */
priv->flags = priv->msgv->flags; /* Copy flags to private struct */
- i2cvdbg("Current flags %i\n", priv->flags);
+ i2cinfo("Current flags %i\n", priv->flags);
/* Decrease counter to indicate the number of messages left to process */
@@ -1314,7 +1305,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
{
/* Start bit is set */
- i2cvdbg("Entering address handling, status = %i\n", status);
+ i2cinfo("Entering address handling, status = %i\n", status);
/* Check for empty message (for robustness) */
@@ -1326,7 +1317,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
if (priv->total_msg_len == 1 && (priv->flags & I2C_M_READ))
{
- i2cvdbg("short read N=1: setting NACK\n");
+ i2cinfo("short read N=1: setting NACK\n");
/* Set POS bit to zero (can be up from a previous 2 byte receive) */
@@ -1339,7 +1330,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
}
else if (priv->total_msg_len == 2 && (priv->flags & I2C_M_READ))
{
- i2cvdbg("short read N=2: setting POS and ACK bits\n");
+ i2cinfo("short read N=2: setting POS and ACK bits\n");
stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_POS);
stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_ACK);
@@ -1349,7 +1340,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
{
/* Enable ACK after address byte */
- i2cvdbg("setting ACK\n");
+ i2cinfo("setting ACK\n");
/* Set POS bit to zero (can be up from a previous 2 byte receive) */
@@ -1369,7 +1360,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
(priv->flags & I2C_M_TEN) ?
0 :((priv->msgv->addr << 1) | (priv->flags & I2C_M_READ)));
- i2cvdbg("Address sent. Addr=%#02x Write/Read bit=%i\n",
+ i2cinfo("Address sent. Addr=%#02x Write/Read bit=%i\n",
priv->msgv->addr, (priv->flags & I2C_M_READ));
/* Flag that address has just been sent */
@@ -1382,7 +1373,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
{
/* TODO: untested!! */
- i2cdbg(" An empty message has been detected, ignoring and passing to next message.\n");
+ i2cwarn("WARNING: An empty message has been detected, ignoring and passing to next message.\n");
/* Trace event */
@@ -1428,15 +1419,15 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
else if ((status & I2C_SR1_ADDR) == 0 && priv->check_addr_ACK)
{
- i2cvdbg("Invalid Address. Setting stop bit and clearing message\n");
- i2cvdbg("status %i\n", status);
+ i2cinfo("Invalid Address. Setting stop bit and clearing message\n");
+ i2cinfo("status %i\n", status);
/* Set condition to terminate msg chain transmission as address is invalid. */
priv->dcnt = -1;
priv->msgc = 0;
- i2cvdbg("dcnt %i , msgc %i\n", priv->dcnt, priv->msgc);
+ i2cinfo("dcnt %i , msgc %i\n", priv->dcnt, priv->msgc);
/* Reset flag to check for valid address */
@@ -1482,8 +1473,8 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN);
stm32_i2c_sendstop(priv);
- i2cvdbg("Address ACKed beginning data reception\n");
- i2cvdbg("short read N=1: programming stop bit\n");
+ i2cinfo("Address ACKed beginning data reception\n");
+ i2cinfo("short read N=1: programming stop bit\n");
priv->dcnt--;
/* Trace */
@@ -1498,8 +1489,8 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0);
- i2cvdbg("Address ACKed beginning data reception\n");
- i2cvdbg("short read N=2: programming NACK\n");
+ i2cinfo("Address ACKed beginning data reception\n");
+ i2cinfo("short read N=2: programming NACK\n");
/* Trace */
@@ -1507,7 +1498,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
}
else
{
- i2cvdbg("Address ACKed beginning data reception\n");
+ i2cinfo("Address ACKed beginning data reception\n");
/* Trace */
@@ -1530,7 +1521,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
* transmit the next byte.
*/
- i2cvdbg("Entering write mode dcnt = %i msgc = %i\n",
+ i2cinfo("Entering write mode dcnt = %i msgc = %i\n",
priv->dcnt, priv->msgc);
/* Clear ADDR flag by reading SR2 and adding it to status */
@@ -1567,12 +1558,12 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
/* If last message send stop bit */
stm32_i2c_sendstop(priv);
- i2cvdbg("Stop sent dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc);
+ i2cinfo("Stop sent dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc);
/* Decrease counter to get to next message */
priv->dcnt--;
- i2cvdbg("dcnt %i\n", priv->dcnt);
+ i2cinfo("dcnt %i\n", priv->dcnt);
stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, priv->dcnt);
}
@@ -1586,13 +1577,13 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
{
stm32_i2c_sendstart(priv);
- i2cvdbg("Restart detected!\n");
- i2cvdbg("Nextflag %i\n", priv->msgv[0].flags);
+ i2cinfo("Restart detected!\n");
+ i2cinfo("Nextflag %i\n", priv->msgv[0].flags);
/* Decrease counter to get to next message */
priv->dcnt--;
- i2cvdbg("dcnt %i\n", priv->dcnt);
+ i2cinfo("dcnt %i\n", priv->dcnt);
stm32_i2c_traceevent(priv, I2CEVENT_WRITE_RESTART, priv->dcnt);
}
@@ -1609,14 +1600,14 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
}
else
{
- i2cdbg("Write mode: next message has an unrecognized flag.\n");
+ i2cerr("ERROR: Write mode: next message has an unrecognized flag.\n");
stm32_i2c_traceevent(priv, I2CEVENT_WRITE_FLAG_ERROR, priv->msgv->flags);
}
}
else
{
- i2cdbg("Write mode error.\n");
+ i2cerr("ERROR: Write mode error.\n");
stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0);
}
}
@@ -1654,7 +1645,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
* (RXNE is set) then the driver can read from the data register.
*/
- i2cvdbg("Entering read mode dcnt = %i msgc = %i, status %i\n",
+ i2cinfo("Entering read mode dcnt = %i msgc = %i, status %i\n",
priv->dcnt, priv->msgc, status);
/* Implementation of method 2 for receiving data following
@@ -1665,7 +1656,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
if (priv->dcnt == 0 && priv->total_msg_len == 1)
{
- i2cvdbg("short read N=1: Read data from data register(DR)\n");
+ i2cinfo("short read N=1: Read data from data register(DR)\n");
*priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET);
priv->dcnt--;
@@ -1676,12 +1667,12 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
else if (priv->dcnt == 2 && priv->total_msg_len == 2 && !(status & I2C_SR1_BTF))
{
- i2cvdbg("short read N=2: DR full, SR empty. Waiting for more bytes.\n");
+ i2cinfo("short read N=2: DR full, SR empty. Waiting for more bytes.\n");
stm32_i2c_traceevent(priv, I2CEVENT_READ_SR_EMPTY, 0);
}
else if (priv->dcnt == 2 && priv->total_msg_len == 2 && (status & I2C_SR1_BTF))
{
- i2cvdbg("short read N=2: DR and SR full setting stop bit and reading twice\n");
+ i2cinfo("short read N=2: DR and SR full setting stop bit and reading twice\n");
stm32_i2c_sendstop(priv);
*priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET);
@@ -1708,7 +1699,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
* this should be able to handle it).
*/
- i2cvdbg("DR full, SR empty. Waiting for more bytes.\n");
+ i2cinfo("DR full, SR empty. Waiting for more bytes.\n");
stm32_i2c_traceevent(priv, I2CEVENT_READ_SR_EMPTY, 0);
}
else if (priv->dcnt >= 4 && priv->total_msg_len >= 3 && (status & I2C_SR1_BTF))
@@ -1717,7 +1708,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
* RXNE(receive buffer not empty) flag.
*/
- i2cvdbg("Read data from data register(DR)\n");
+ i2cinfo("Read data from data register(DR)\n");
*priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET);
/* Decrease current message length */
@@ -1732,8 +1723,8 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
* This coincides with EV7_2 in the reference manual.
*/
- i2cvdbg("Program NACK\n");
- i2cvdbg("Read data from data register(DR) dcnt=3\n");
+ i2cinfo("Program NACK\n");
+ i2cinfo("Read data from data register(DR) dcnt=3\n");
stm32_i2c_traceevent(priv, I2CEVENT_READ_3, priv->dcnt);
@@ -1753,10 +1744,10 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
}
else if (priv->dcnt == 2 && (status & I2C_SR1_BTF) && priv->total_msg_len >= 3)
{
- i2cvdbg("Program stop\n");
- i2cvdbg("Read data from data register(DR) dcnt=2\n");
- i2cvdbg("Read data from data register(SR) dcnt=1\n");
- i2cvdbg("Setting condition to stop ISR dcnt = -1\n");
+ i2cinfo("Program stop\n");
+ i2cinfo("Read data from data register(DR) dcnt=2\n");
+ i2cinfo("Read data from data register(SR) dcnt=1\n");
+ i2cinfo("Setting condition to stop ISR dcnt = -1\n");
stm32_i2c_traceevent(priv, I2CEVENT_READ_3, priv->dcnt);
@@ -1783,8 +1774,8 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
else
{
- i2cdbg("I2C read mode no correct state detected\n");
- i2cdbg(" state %i, dcnt=%i\n", status, priv->dcnt);
+ i2cerr("ERROR: I2C read mode no correct state detected\n");
+ i2cerr(" state %i, dcnt=%i\n", status, priv->dcnt);
/* set condition to terminate ISR and wake waiting thread */
@@ -1809,7 +1800,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
/* Read rest of the state */
status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16);
- i2cdbg("Empty call to ISR: Stopping ISR\n");
+ i2cwarn("WARNING: Empty call to ISR: Stopping ISR\n");
stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0);
}
@@ -1833,8 +1824,8 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16);
- i2cdbg(" No correct state detected(start bit, read or write) \n");
- i2cdbg(" state %i\n", status);
+ i2cerr("ERROR: No correct state detected(start bit, read or write) \n");
+ i2cerr(" state %i\n", status);
/* set condition to terminate ISR and wake waiting thread */
@@ -1853,7 +1844,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
if (priv->dcnt == -1 && priv->msgc == 0)
{
- i2cvdbg("Shutting down I2C ISR\n");
+ i2cinfo("Shutting down I2C ISR\n");
stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0);
@@ -2126,7 +2117,7 @@ static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
status = stm32_i2c_getstatus(priv);
ret = -ETIMEDOUT;
- i2cdbg("Timed out: CR1: 0x%04x status: 0x%08x\n",
+ i2cerr("ERROR: Timed out: CR1: 0x%04x status: 0x%08x\n",
stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status);
/* "Note: When the STOP, START or PEC bit is set, the software must
@@ -2156,7 +2147,8 @@ static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
* Note: this commentary is found in both places.
*
*/
- i2cdbg("Check if the address was valid\n");
+
+ i2cinfo("Check if the address was valid\n");
stm32_i2c_sendstop(priv);
#endif
/* Clear busy flag in case of timeout */
diff --git a/arch/arm/src/stm32/stm32_idle.c b/arch/arm/src/stm32/stm32_idle.c
index 0786f2ac99cb917bc10c9f6d7ee70a9545effb6f..648c0c1521f4576841e90dbc168a420f4eb60374 100644
--- a/arch/arm/src/stm32/stm32_idle.c
+++ b/arch/arm/src/stm32/stm32_idle.c
@@ -101,7 +101,7 @@ static void up_idlepm(void)
/* Perform board-specific, state-dependent logic here */
- llvdbg("newstate= %d oldstate=%d\n", newstate, oldstate);
+ _info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/stm32/stm32_irq.c
index e6a347c00ac3e26e11c2571e81b2bd308a08769e..062d63fb7499afddac41d1dfac7f9b0b31f45e7e 100644
--- a/arch/arm/src/stm32/stm32_irq.c
+++ b/arch/arm/src/stm32/stm32_irq.c
@@ -107,40 +107,42 @@ extern uint32_t _vectors[];
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_IRQ)
+#if defined(CONFIG_DEBUG_IRQ_INFO)
static void stm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
- lldbg("NVIC (%s, irq=%d):\n", msg, irq);
- lldbg(" INTCTRL: %08x VECTAB: %08x\n",
- getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
+
+ irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
+ irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
+ getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
- lldbg(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
- getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
- getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
+ irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
+ getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
+ getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
- lldbg(" IRQ ENABLE: %08x %08x %08x\n",
- getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
- getreg32(NVIC_IRQ64_95_ENABLE));
- lldbg(" SYSH_PRIO: %08x %08x %08x\n",
- getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
- getreg32(NVIC_SYSH12_15_PRIORITY));
- lldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
- getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
- getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
- getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
- lldbg(" %08x %08x %08x %08x\n",
- getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
- getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
- lldbg(" %08x\n",
- getreg32(NVIC_IRQ64_67_PRIORITY));
+ irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
+ getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
+ getreg32(NVIC_IRQ64_95_ENABLE));
+ irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
+ getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
+ getreg32(NVIC_SYSH12_15_PRIORITY));
+ irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
+ getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
+ getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
+ getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
+ getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
+ irqinfo(" %08x\n",
+ getreg32(NVIC_IRQ64_67_PRIORITY));
+
leave_critical_section(flags);
}
#else
@@ -158,11 +160,11 @@ static void stm32_dumpnvic(const char *msg, int irq)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
static int stm32_nmi(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! NMI received\n");
+ _err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
@@ -170,7 +172,7 @@ static int stm32_nmi(int irq, FAR void *context)
static int stm32_busfault(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
+ _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
}
@@ -178,7 +180,7 @@ static int stm32_busfault(int irq, FAR void *context)
static int stm32_usagefault(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
+ _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
}
@@ -186,7 +188,7 @@ static int stm32_usagefault(int irq, FAR void *context)
static int stm32_pendsv(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! PendSV received\n");
+ _err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
@@ -194,7 +196,7 @@ static int stm32_pendsv(int irq, FAR void *context)
static int stm32_dbgmonitor(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Debug Monitor received\n");
+ _err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
}
@@ -202,7 +204,7 @@ static int stm32_dbgmonitor(int irq, FAR void *context)
static int stm32_reserved(int irq, FAR void *context)
{
(void)up_irq_save();
- dbg("PANIC!!! Reserved interrupt\n");
+ _err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
@@ -408,7 +410,7 @@ void up_irqinitialize(void)
/* Attach all other processor exceptions (except reset and sys tick) */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
irq_attach(STM32_IRQ_NMI, stm32_nmi);
#ifndef CONFIG_ARM_MPU
irq_attach(STM32_IRQ_MEMFAULT, up_memfault);
diff --git a/arch/arm/src/stm32/stm32_iwdg.c b/arch/arm/src/stm32/stm32_iwdg.c
index 80d45be7292a4a8e9c111f6dd5ac49da2f786690..1cdf8e47bc07fc5fd68c88ae9b2917e57c6e0267 100644
--- a/arch/arm/src/stm32/stm32_iwdg.c
+++ b/arch/arm/src/stm32/stm32_iwdg.c
@@ -84,6 +84,10 @@
# define CONFIG_STM32_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT
#endif
+#ifndef CONFIG_DEBUG_WATCHDOG_INFO
+# undef CONFIG_STM32_IWDG_REGDEBUG
+#endif
+
/* REVISIT: It appears that you can only setup the prescaler and reload
* registers once. After that, the SR register's PVU and RVU bits never go
* to zero. So we defer setting up these registers until the watchdog
@@ -105,20 +109,6 @@
# error "Both CONFIG_STM32_IWDG_ONETIMESETUP and CONFIG_STM32_IWDG_DEFERREDSETUP are defined"
#endif
-/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing the watchdog
- * driver. NOTE: that only lldbg types are used so that the output is
- * immediately available.
- */
-
-#ifdef CONFIG_DEBUG_WATCHDOG
-# define wddbg lldbg
-# define wdvdbg llvdbg
-#else
-# define wddbg(x...)
-# define wdvdbg(x...)
-#endif
-
/****************************************************************************
* Private Types
****************************************************************************/
@@ -143,7 +133,7 @@ struct stm32_lowerhalf_s
****************************************************************************/
/* Register operations ******************************************************/
-#if defined(CONFIG_STM32_IWDG_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_STM32_IWDG_REGDEBUG
static uint16_t stm32_getreg(uint32_t addr);
static void stm32_putreg(uint16_t val, uint32_t addr);
#else
@@ -195,7 +185,7 @@ static struct stm32_lowerhalf_s g_wdgdev;
*
****************************************************************************/
-#if defined(CONFIG_STM32_IWDG_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_STM32_IWDG_REGDEBUG
static uint16_t stm32_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@@ -216,7 +206,7 @@ static uint16_t stm32_getreg(uint32_t addr)
{
if (count == 4)
{
- lldbg("...\n");
+ wdinfo("...\n");
}
return val;
@@ -233,7 +223,7 @@ static uint16_t stm32_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ wdinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -245,7 +235,7 @@ static uint16_t stm32_getreg(uint32_t addr)
/* Show the register value read */
- lldbg("%08x->%04x\n", addr, val);
+ wdinfo("%08x->%04x\n", addr, val);
return val;
}
#endif
@@ -258,12 +248,12 @@ static uint16_t stm32_getreg(uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_STM32_IWDG_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_STM32_IWDG_REGDEBUG
static void stm32_putreg(uint16_t val, uint32_t addr)
{
/* Show the register value being written */
- lldbg("%08x<-%04x\n", addr, val);
+ wdinfo("%08x<-%04x\n", addr, val);
/* Write the value */
@@ -339,7 +329,7 @@ static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
irqstate_t flags;
- wdvdbg("Entry: started=%d\n");
+ wdinfo("Entry: started=%d\n");
DEBUGASSERT(priv);
/* Have we already been started? */
@@ -394,7 +384,7 @@ static int stm32_stop(FAR struct watchdog_lowerhalf_s *lower)
{
/* There is no way to disable the IDWG timer once it has been started */
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
return -ENOSYS;
}
@@ -420,7 +410,7 @@ static int stm32_keepalive(FAR struct watchdog_lowerhalf_s *lower)
FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
irqstate_t flags;
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
/* Reload the IWDG timer */
@@ -455,7 +445,7 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
uint32_t ticks;
uint32_t elapsed;
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
DEBUGASSERT(priv);
/* Return the status bit */
@@ -484,10 +474,10 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
status->timeleft = priv->timeout - elapsed;
- wdvdbg("Status :\n");
- wdvdbg(" flags : %08x\n", status->flags);
- wdvdbg(" timeout : %d\n", status->timeout);
- wdvdbg(" timeleft : %d\n", status->timeleft);
+ wdinfo("Status :\n");
+ wdinfo(" flags : %08x\n", status->flags);
+ wdinfo(" timeout : %d\n", status->timeout);
+ wdinfo(" timeleft : %d\n", status->timeleft);
return OK;
}
@@ -516,14 +506,14 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
int prescaler;
int shift;
- wdvdbg("Entry: timeout=%d\n", timeout);
+ wdinfo("Entry: timeout=%d\n", timeout);
DEBUGASSERT(priv);
/* Can this timeout be represented? */
if (timeout < 1 || timeout > IWDG_MAXTIMEOUT)
{
- wddbg("Cannot represent timeout=%d > %d\n",
+ wderr("ERROR: Cannot represent timeout=%d > %d\n",
timeout, IWDG_MAXTIMEOUT);
return -ERANGE;
}
@@ -536,7 +526,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
#ifdef CONFIG_STM32_IWDG_ONETIMESETUP
if (priv->started)
{
- wddbg("Timer is already started\n");
+ wdwarn("WARNING: Timer is already started\n");
return -EBUSY;
}
#endif
@@ -631,7 +621,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
}
#endif
- wdvdbg("prescaler=%d fiwdg=%d reload=%d\n", prescaler, fiwdg, reload);
+ wdinfo("prescaler=%d fiwdg=%d reload=%d\n", prescaler, fiwdg, reload);
return OK;
}
@@ -662,7 +652,7 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
{
FAR struct stm32_lowerhalf_s *priv = &g_wdgdev;
- wdvdbg("Entry: devpath=%s lsifreq=%d\n", devpath, lsifreq);
+ wdinfo("Entry: devpath=%s lsifreq=%d\n", devpath, lsifreq);
/* NOTE we assume that clocking to the IWDG has already been provided by
* the RCC initialization logic.
@@ -682,7 +672,7 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
*/
stm32_rcc_enablelsi();
- wdvdbg("RCC CSR: %08x\n", getreg32(STM32_RCC_CSR));
+ wdinfo("RCC CSR: %08x\n", getreg32(STM32_RCC_CSR));
/* Select an arbitrary initial timeout value. But don't start the watchdog
* yet. NOTE: If the "Hardware watchdog" feature is enabled through the
diff --git a/arch/arm/src/stm32/stm32_ltdc.c b/arch/arm/src/stm32/stm32_ltdc.c
index 8ae8e890fdb99fe1fedfeb73f20c874e4f30b6f2..442af257dd4d7dda0a72edb60e5f5f9f79778e10 100644
--- a/arch/arm/src/stm32/stm32_ltdc.c
+++ b/arch/arm/src/stm32/stm32_ltdc.c
@@ -283,11 +283,11 @@
/* Debug option */
#ifdef CONFIG_STM32_LTDC_REGDEBUG
-# define regdbg dbg
-# define regvdbg vdbg
+# define regerr lcderr
+# define reginfo lcdinfo
#else
-# define regdbg(x...)
-# define regvdbg(x...)
+# define regerr(x...)
+# define reginfo(x...)
#endif
/* Preallocated LTDC framebuffers */
@@ -942,13 +942,13 @@ static void stm32_ltdc_gpioconfig(void)
{
int i;
- gvdbg("Configuring pins\n");
+ lcdinfo("Configuring pins\n");
/* Configure each pin */
for (i = 0; i < STM32_LTDC_NPINCONFIGS; i++)
{
- regvdbg("set gpio%d = %08x\n", i, g_ltdcpins[i]);
+ reginfo("set gpio%d = %08x\n", i, g_ltdcpins[i]);
stm32_configgpio(g_ltdcpins[i]);
}
}
@@ -972,51 +972,51 @@ static void stm32_ltdc_periphconfig(void)
/* Configure APB2 LTDC clock external */
- regvdbg("configured RCC_APB2ENR=%08x\n", getreg32(STM32_RCC_APB2ENR));
+ reginfo("configured RCC_APB2ENR=%08x\n", getreg32(STM32_RCC_APB2ENR));
/* Configure the SAI PLL external to provide the LCD_CLK */
- regvdbg("configured RCC_PLLSAI=%08x\n", getreg32(STM32_RCC_PLLSAICFGR));
+ reginfo("configured RCC_PLLSAI=%08x\n", getreg32(STM32_RCC_PLLSAICFGR));
/* Configure dedicated clock external */
- regvdbg("configured RCC_DCKCFGR=%08x\n", getreg32(STM32_RCC_DCKCFGR));
+ reginfo("configured RCC_DCKCFGR=%08x\n", getreg32(STM32_RCC_DCKCFGR));
/* Configure LTDC_SSCR */
regval = (STM32_LTDC_SSCR_VSH | STM32_LTDC_SSCR_HSW);
- regvdbg("set LTDC_SSCR=%08x\n", regval);
+ reginfo("set LTDC_SSCR=%08x\n", regval);
putreg32(regval, STM32_LTDC_SSCR);
- regvdbg("configured LTDC_SSCR=%08x\n", getreg32(STM32_LTDC_SSCR));
+ reginfo("configured LTDC_SSCR=%08x\n", getreg32(STM32_LTDC_SSCR));
/* Configure LTDC_BPCR */
regval = (STM32_LTDC_BPCR_AVBP | STM32_LTDC_BPCR_AHBP);
- regvdbg("set LTDC_BPCR=%08x\n", regval);
+ reginfo("set LTDC_BPCR=%08x\n", regval);
putreg32(regval, STM32_LTDC_BPCR);
- regvdbg("configured LTDC_BPCR=%08x\n", getreg32(STM32_LTDC_BPCR));
+ reginfo("configured LTDC_BPCR=%08x\n", getreg32(STM32_LTDC_BPCR));
/* Configure LTDC_AWCR */
regval = (STM32_LTDC_AWCR_AAH | STM32_LTDC_AWCR_AAW);
- regvdbg("set LTDC_AWCR=%08x\n", regval);
+ reginfo("set LTDC_AWCR=%08x\n", regval);
putreg32(regval, STM32_LTDC_AWCR);
- regvdbg("configured LTDC_AWCR=%08x\n", getreg32(STM32_LTDC_AWCR));
+ reginfo("configured LTDC_AWCR=%08x\n", getreg32(STM32_LTDC_AWCR));
/* Configure LTDC_TWCR */
regval = (STM32_LTDC_TWCR_TOTALH | STM32_LTDC_TWCR_TOTALW);
- regvdbg("set LTDC_TWCR=%08x\n", regval);
+ reginfo("set LTDC_TWCR=%08x\n", regval);
putreg32(regval, STM32_LTDC_TWCR);
- regvdbg("configured LTDC_TWCR=%08x\n", getreg32(STM32_LTDC_TWCR));
+ reginfo("configured LTDC_TWCR=%08x\n", getreg32(STM32_LTDC_TWCR));
/* Configure LTDC_GCR */
regval = (STM32_LTDC_GCR_PCPOL | STM32_LTDC_GCR_DEPOL
| STM32_LTDC_GCR_VSPOL | STM32_LTDC_GCR_HSPOL);
- regvdbg("set LTDC_GCR=%08x\n", regval);
+ reginfo("set LTDC_GCR=%08x\n", regval);
putreg32(regval, STM32_LTDC_GCR);
- regvdbg("configured LTDC_GCR=%08x\n", getreg32(STM32_LTDC_GCR));
+ reginfo("configured LTDC_GCR=%08x\n", getreg32(STM32_LTDC_GCR));
}
/****************************************************************************
@@ -1032,9 +1032,9 @@ static void stm32_ltdc_periphconfig(void)
static void stm32_ltdc_bgcolor(uint32_t rgb)
{
- regvdbg("set LTDC_BCCR=%08x\n", rgb);
+ reginfo("set LTDC_BCCR=%08x\n", rgb);
putreg32(rgb, STM32_LTDC_BCCR);
- regvdbg("configured LTDC_BCCR=%08x\n", getreg32(STM32_LTDC_BCCR));
+ reginfo("configured LTDC_BCCR=%08x\n", getreg32(STM32_LTDC_BCCR));
}
/****************************************************************************
@@ -1073,9 +1073,9 @@ static void stm32_ltdc_dither(bool enable,
LTDC_GCR_DGW(0) | LTDC_GCR_DBW(0));
regval |= (LTDC_GCR_DRW(red) | LTDC_GCR_DGW(green) | LTDC_GCR_DBW(blue));
- regvdbg("set LTDC_GCR=%08x\n", regval);
+ reginfo("set LTDC_GCR=%08x\n", regval);
putreg32(regval, STM32_LTDC_GCR);
- regvdbg("configured LTDC_GCR=%08x\n", getreg32(STM32_LTDC_GCR));
+ reginfo("configured LTDC_GCR=%08x\n", getreg32(STM32_LTDC_GCR));
}
/****************************************************************************
@@ -1090,9 +1090,9 @@ static void stm32_ltdc_linepos(void)
{
/* Configure LTDC_LIPCR */
- regvdbg("set LTDC_LIPCR=%08x\n", STM32_LTDC_LIPCR_LIPOS);
+ reginfo("set LTDC_LIPCR=%08x\n", STM32_LTDC_LIPCR_LIPOS);
putreg32(STM32_LTDC_LIPCR_LIPOS, STM32_LTDC_LIPCR);
- regvdbg("configured LTDC_LIPCR=%08x\n", getreg32(STM32_LTDC_LIPCR));
+ reginfo("configured LTDC_LIPCR=%08x\n", getreg32(STM32_LTDC_LIPCR));
}
/****************************************************************************
@@ -1114,9 +1114,9 @@ static void stm32_ltdc_irqctrl(uint32_t setirqs, uint32_t clrirqs)
regval = getreg32(STM32_LTDC_IER);
regval &= ~clrirqs;
regval |= setirqs;
- regvdbg("set LTDC_IER=%08x\n", regval);
+ reginfo("set LTDC_IER=%08x\n", regval);
putreg32(regval, STM32_LTDC_IER);
- regvdbg("configured LTDC_IER=%08x\n", getreg32(STM32_LTDC_IER));
+ reginfo("configured LTDC_IER=%08x\n", getreg32(STM32_LTDC_IER));
}
/****************************************************************************
@@ -1133,7 +1133,7 @@ static int stm32_ltdcirq(int irq, void *context)
uint32_t regval = getreg32(STM32_LTDC_ISR);
- regvdbg("irq = %d, regval = %08x\n", irq, regval);
+ reginfo("irq = %d, regval = %08x\n", irq, regval);
if (regval & LTDC_ISR_RRIF)
{
@@ -1155,7 +1155,7 @@ static int stm32_ltdcirq(int irq, void *context)
if (ret != OK)
{
- dbg("sem_post() failed\n");
+ lcderr("ERROR: sem_post() failed\n");
return ret;
}
}
@@ -1202,7 +1202,7 @@ static int stm32_ltdc_waitforirq(void)
if (ret != OK)
{
- dbg("sem_wait() failed\n");
+ lcderr("ERROR: sem_wait() failed\n");
}
}
@@ -1255,9 +1255,9 @@ static int stm32_ltdc_reload(uint8_t value, bool waitvblank)
* immediately reload is set.
*/
- regvdbg("set LTDC_SRCR=%08x\n", value);
+ reginfo("set LTDC_SRCR=%08x\n", value);
putreg32(value, STM32_LTDC_SRCR);
- regvdbg("configured LTDC_SRCR=%08x\n", getreg32(STM32_LTDC_SRCR));
+ reginfo("configured LTDC_SRCR=%08x\n", getreg32(STM32_LTDC_SRCR));
if (waitvblank & (value == LTDC_SRCR_VBR))
{
@@ -1354,7 +1354,7 @@ static void stm32_lcd_enable(bool enable)
uint32_t regval;
regval = getreg32(STM32_LTDC_GCR);
- regvdbg("get LTDC_GCR=%08x\n", regval);
+ reginfo("get LTDC_GCR=%08x\n", regval);
if (enable == true)
{
@@ -1365,9 +1365,9 @@ static void stm32_lcd_enable(bool enable)
regval &= ~LTDC_GCR_LTDCEN;
}
- regvdbg("set LTDC_GCR=%08x\n", regval);
+ reginfo("set LTDC_GCR=%08x\n", regval);
putreg32(regval, STM32_LTDC_GCR);
- regvdbg("configured LTDC_GCR=%08x\n", getreg32(STM32_LTDC_GCR));
+ reginfo("configured LTDC_GCR=%08x\n", getreg32(STM32_LTDC_GCR));
}
/****************************************************************************
@@ -1392,7 +1392,7 @@ static void stm32_ltdc_lclutenable(FAR struct stm32_layer_s *layer, bool enable)
uint32_t regval;
regval = getreg32(stm32_cr_layer_t[layer->state.lid]);
- regvdbg("get LTDC_L%dCR=%08x\n", layer->state.lid + 1, regval);
+ reginfo("get LTDC_L%dCR=%08x\n", layer->state.lid + 1, regval);
/* Disable the clut support during update the color table */
@@ -1405,7 +1405,7 @@ static void stm32_ltdc_lclutenable(FAR struct stm32_layer_s *layer, bool enable)
regval &= ~LTDC_LxCR_CLUTEN;
}
- regvdbg("set LTDC_L%dCR=%08x\n", layer->state.lid + 1, regval);
+ reginfo("set LTDC_L%dCR=%08x\n", layer->state.lid + 1, regval);
putreg32(regval, stm32_cr_layer_t[layer->state.lid]);
}
#endif
@@ -1519,17 +1519,17 @@ static int stm32_ltdc_lvalidatearea(FAR struct stm32_layer_s *layer,
(srcypos > ypos + yres - 1))
{
- gdbg("layer coordinates out of valid area: xpos = %d > %d, \
- ypos = %d > %d, width = %d > %d, height = %d > %d, \
- srcxpos = %d > %d, srcypos = %d > %d",
- xpos, vinfo->xres - 1,
- ypos, vinfo->yres - 1,
- xres, vinfo->xres - xpos,
- yres, vinfo->yres - ypos,
- srcxpos, xpos + xres - 1,
- srcypos, ypos + yres - 1);
-
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: layer coordinates out of valid area: xpos = %d > %d, \
+ ypos = %d > %d, width = %d > %d, height = %d > %d, \
+ srcxpos = %d > %d, srcypos = %d > %d",
+ xpos, vinfo->xres - 1,
+ ypos, vinfo->yres - 1,
+ xres, vinfo->xres - xpos,
+ yres, vinfo->yres - ypos,
+ srcxpos, xpos + xres - 1,
+ srcypos, ypos + yres - 1);
+
+ lcderr(" Returning EINVAL\n");
return -EINVAL;
}
@@ -1615,7 +1615,7 @@ static void stm32_ltdc_larea(struct stm32_layer_s *layer)
FAR struct stm32_ltdc_s *priv = &layer->state;
FAR struct ltdc_area_s *area = &priv->area;
- regvdbg("xpos = %d, ypos = %d, xres = %d, yres = %d\n",
+ reginfo("xpos = %d, ypos = %d, xres = %d, yres = %d\n",
area->xpos, area->ypos, area->xres, area->yres);
lxpos = area->xpos + (STM32_LTDC_LxWHPCR_WHSTPOS + 1);
@@ -1633,9 +1633,9 @@ static void stm32_ltdc_larea(struct stm32_layer_s *layer)
/* Configure LxWHPCR / LxWVPCR register */
- regvdbg("set LTDC_L%dWHPCR=%08x\n", priv->lid + 1, whpcr);
+ reginfo("set LTDC_L%dWHPCR=%08x\n", priv->lid + 1, whpcr);
putreg32(whpcr, stm32_whpcr_layer_t[priv->lid]);
- regvdbg("set LTDC_L%dWVPCR=%08x\n", priv->lid + 1, wvpcr);
+ reginfo("set LTDC_L%dWVPCR=%08x\n", priv->lid + 1, wvpcr);
putreg32(wvpcr, stm32_wvpcr_layer_t[priv->lid]);
/* Configure framebuffer */
@@ -1664,7 +1664,7 @@ static void stm32_ltdc_lpixelformat(FAR struct stm32_layer_s *layer)
{
/* Configure PFCR register */
- regvdbg("set LTDC_L%dPFCR=%08x\n", layer->state.lid + 1,
+ reginfo("set LTDC_L%dPFCR=%08x\n", layer->state.lid + 1,
stm32_fmt_layer_t[layer->state.lid]);
putreg32(stm32_fmt_layer_t[layer->state.lid],
stm32_pfcr_layer_t[layer->state.lid]);
@@ -1698,7 +1698,7 @@ static inline void stm32_ltdc_lframebuffer(FAR struct stm32_layer_s *layer)
offset = priv->xpos * STM32_LTDC_Lx_BYPP(pinfo->bpp) +
pinfo->stride * priv->ypos;
- regvdbg("set LTDC_L%dCFBAR=%08x\n", priv->lid + 1, pinfo->fbmem + offset);
+ reginfo("set LTDC_L%dCFBAR=%08x\n", priv->lid + 1, pinfo->fbmem + offset);
putreg32((uint32_t)pinfo->fbmem + offset, stm32_cfbar_layer_t[priv->lid]);
/* Configure LxCFBLR register */
@@ -1708,12 +1708,12 @@ static inline void stm32_ltdc_lframebuffer(FAR struct stm32_layer_s *layer)
cfblr = LTDC_LxCFBLR_CFBP(pinfo->stride) |
LTDC_LxCFBLR_CFBLL(area->xres * STM32_LTDC_Lx_BYPP(pinfo->bpp) + 3);
- regvdbg("set LTDC_L%dCFBLR=%08x\n", priv->lid + 1, cfblr);
+ reginfo("set LTDC_L%dCFBLR=%08x\n", priv->lid + 1, cfblr);
putreg32(cfblr, stm32_cfblr_layer_t[priv->lid]);
/* Configure LxCFBLNR register */
- regvdbg("set LTDC_L%dCFBLNR=%08x\n", priv->lid + 1, area->yres);
+ reginfo("set LTDC_L%dCFBLNR=%08x\n", priv->lid + 1, area->yres);
putreg32(area->yres, stm32_cfblnr_layer_t[priv->lid]);
}
@@ -1733,7 +1733,7 @@ static inline void stm32_ltdc_lframebuffer(FAR struct stm32_layer_s *layer)
static void stm32_ltdc_lalpha(FAR struct stm32_layer_s *layer)
{
uint8_t opac = stm32_ltdc_lgetopac(layer);
- regvdbg("set LTDC_L%dCACR=%02x\n", layer->state.lid + 1, opac);
+ reginfo("set LTDC_L%dCACR=%02x\n", layer->state.lid + 1, opac);
putreg32(opac, stm32_cacr_layer_t[layer->state.lid]);
/* Clear the constant alpha operation flag */
@@ -1760,7 +1760,7 @@ static void stm32_ltdc_lalpha(FAR struct stm32_layer_s *layer)
static void stm32_ltdc_lblendmode(FAR struct stm32_layer_s *layer,
uint8_t bf1, uint8_t bf2)
{
- regvdbg("set LTDC_L%dBFCR=%08x\n", layer->state.lid + 1,
+ reginfo("set LTDC_L%dBFCR=%08x\n", layer->state.lid + 1,
(LTDC_LxBFCR_BF1(bf1) | LTDC_LxBFCR_BF2(bf2)));
putreg32((LTDC_LxBFCR_BF1(bf1) | LTDC_LxBFCR_BF2(bf2)),
stm32_bfcr_layer_t[layer->state.lid]);
@@ -1785,7 +1785,7 @@ static void stm32_ltdc_lblendmode(FAR struct stm32_layer_s *layer,
static void stm32_ltdc_lcolor(FAR struct stm32_layer_s *layer, uint32_t argb)
{
- regvdbg("set LTDC_L%dDCCR=%08x\n", layer->state.lid + 1, argb);
+ reginfo("set LTDC_L%dDCCR=%08x\n", layer->state.lid + 1, argb);
putreg32(argb, stm32_dccr_layer_t[layer->state.lid]);
/* Clear the color operation flag */
@@ -1816,7 +1816,7 @@ static void stm32_ltdc_lcolorkey(FAR struct stm32_layer_s *layer)
{
/* Set colorkey */
- regvdbg("set LTDC_L%dCKCR=%08x\n",
+ reginfo("set LTDC_L%dCKCR=%08x\n",
layer->state.lid + 1, layer->state.colorkey);
putreg32(layer->state.colorkey, stm32_ckcr_layer_t[layer->state.lid]);
@@ -1831,7 +1831,7 @@ static void stm32_ltdc_lcolorkey(FAR struct stm32_layer_s *layer)
regval &= ~LTDC_LxCR_COLKEN;
}
- regvdbg("set LTDC_L%dCR=%08x\n", layer->state.lid + 1, regval);
+ reginfo("set LTDC_L%dCR=%08x\n", layer->state.lid + 1, regval);
putreg32(regval, stm32_cr_layer_t[layer->state.lid]);
/* Clear the colorkey operation flag */
@@ -1903,7 +1903,7 @@ static void stm32_ltdc_lclut(FAR struct stm32_layer_s *layer,
#endif
- regvdbg("set LTDC_L%dCLUTWR = %08x, cmap->first = %d, cmap->len = %d\n",
+ reginfo("set LTDC_L%dCLUTWR = %08x, cmap->first = %d, cmap->len = %d\n",
layer->state.lid + 1, regval, cmap->first, cmap->len);
putreg32(regval, stm32_clutwr_layer_t[layer->state.lid]);
}
@@ -1950,7 +1950,7 @@ static void stm32_ltdc_lenable(FAR struct stm32_layer_s *layer)
regval &= ~LTDC_LxCR_LEN;
}
- regvdbg("set LTDC_L%dCR=%08x\n", layer->state.lid + 1, regval);
+ reginfo("set LTDC_L%dCR=%08x\n", layer->state.lid + 1, regval);
putreg32(regval, stm32_cr_layer_t[layer->state.lid]);
/* Clear the enable operation flag */
@@ -1985,8 +1985,8 @@ static void stm32_ltdc_lclear(FAR struct stm32_layer_s *layer,
uint8_t *dest = (uint8_t *)priv->pinfo.fbmem;
int i;
- gvdbg("Clearing display: BPP=%d color=%04x framebuffer=%08x size=%d\n",
- priv->pinfo.bpp, color, dest, priv->pinfo.fblen);
+ lcdinfo("Clearing display: BPP=%d color=%04x framebuffer=%08x size=%d\n",
+ priv->pinfo.bpp, color, dest, priv->pinfo.fblen);
for (i = 0; i < priv->pinfo.fblen; i += sizeof(uint8_t))
{
@@ -2003,8 +2003,8 @@ static void stm32_ltdc_lclear(FAR struct stm32_layer_s *layer,
uint16_t *dest = (uint16_t *)priv->pinfo.fbmem;
int i;
- gvdbg("Clearing display: BPP=%d color=%04x framebuffer=%08x size=%d\n",
- priv->pinfo.bpp, color, dest, priv->pinfo.fblen);
+ lcdinfo("Clearing display: BPP=%d color=%04x framebuffer=%08x size=%d\n",
+ priv->pinfo.bpp, color, dest, priv->pinfo.fblen);
for (i = 0; i < priv->pinfo.fblen; i += sizeof(uint16_t))
{
@@ -2024,8 +2024,8 @@ static void stm32_ltdc_lclear(FAR struct stm32_layer_s *layer,
uint8_t b;
int i;
- gvdbg("Clearing display: BPP=%d color=%04x framebuffer=%08x size=%d\n",
- priv->pinfo.bpp, color, dest, priv->pinfo.fblen);
+ lcdinfo("Clearing display: BPP=%d color=%04x framebuffer=%08x size=%d\n",
+ priv->pinfo.bpp, color, dest, priv->pinfo.fblen);
r = (uint8_t) color;
g = (uint8_t) (color >> 8);
@@ -2048,8 +2048,8 @@ static void stm32_ltdc_lclear(FAR struct stm32_layer_s *layer,
uint32_t *dest = (uint32_t *)priv->pinfo.fbmem;
int i;
- gvdbg("Clearing display: BPP=%d color=%04x framebuffer=%08x size=%d\n",
- priv->pinfo.bpp, color, dest, priv->pinfo.fblen);
+ lcdinfo("Clearing display: BPP=%d color=%04x framebuffer=%08x size=%d\n",
+ priv->pinfo.bpp, color, dest, priv->pinfo.fblen);
for (i = 0; i < priv->pinfo.fblen; i += sizeof(uint32_t))
{
@@ -2191,7 +2191,7 @@ static void stm32_ltdc_linit(int lid)
static int stm32_getvideoinfo(struct fb_vtable_s *vtable,
struct fb_videoinfo_s *vinfo)
{
- gvdbg("vtable=%p vinfo=%p\n", vtable, vinfo);
+ lcdinfo("vtable=%p vinfo=%p\n", vtable, vinfo);
if (vtable)
{
FAR struct ltdc_layer_s *ltdc;
@@ -2203,7 +2203,7 @@ static int stm32_getvideoinfo(struct fb_vtable_s *vtable,
return stm32_lgetvideoinfo(ltdc, vinfo);
}
- gdbg("ERROR: Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -2226,7 +2226,7 @@ static int stm32_getvideoinfo(struct fb_vtable_s *vtable,
static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno,
struct fb_planeinfo_s *pinfo)
{
- gvdbg("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo);
+ lcdinfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo);
if (vtable)
{
FAR struct ltdc_layer_s *ltdc;
@@ -2238,7 +2238,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno,
return stm32_lgetplaneinfo(ltdc, planeno, pinfo);
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -2315,7 +2315,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable,
static int stm32_lgetvideoinfo(struct ltdc_layer_s *layer,
struct fb_videoinfo_s *vinfo)
{
- gvdbg("layer=%p vinfo=%p\n", layer, vinfo);
+ lcdinfo("layer=%p vinfo=%p\n", layer, vinfo);
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer;
if (stm32_ltdc_lvalidate(priv))
@@ -2325,7 +2325,7 @@ static int stm32_lgetvideoinfo(struct ltdc_layer_s *layer,
return OK;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -2349,16 +2349,16 @@ static int stm32_lgetvideoinfo(struct ltdc_layer_s *layer,
static int stm32_lgetplaneinfo(struct ltdc_layer_s *layer, int planeno,
struct fb_planeinfo_s *pinfo)
{
- gvdbg("layer=%p planeno=%d pinfo=%p\n", layer, planeno, pinfo);
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer;
+ lcdinfo("layer=%p planeno=%d pinfo=%p\n", layer, planeno, pinfo);
if (stm32_ltdc_lvalidate(priv) && planeno == 0)
{
memcpy(pinfo, &priv->state.pinfo, sizeof(struct fb_planeinfo_s));
return OK;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -2384,9 +2384,10 @@ static int stm32_lgetplaneinfo(struct ltdc_layer_s *layer, int planeno,
static int stm32_setclut(struct ltdc_layer_s *layer,
const struct fb_cmap_s *cmap)
{
- int ret;
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer;
- gvdbg("layer=%p cmap=%p\n", layer, cmap);
+ int ret;
+
+ lcdinfo("layer=%p cmap=%p\n", layer, cmap);
if (stm32_ltdc_lvalidate(priv) && cmap)
{
@@ -2394,14 +2395,14 @@ static int stm32_setclut(struct ltdc_layer_s *layer,
if (priv->state.vinfo.fmt != FB_FMT_RGB8)
{
- gdbg("Error: CLUT is not supported for the pixel format: %d\n",
- priv->state.vinfo.fmt);
+ lcderr("ERROR: CLUT is not supported for the pixel format: %d\n",
+ priv->state.vinfo.fmt);
ret = -EINVAL;
}
else if (cmap->first >= STM32_LTDC_NCLUT)
{
- gdbg("Error: only %d color table entries supported\n",
- STM32_LTDC_NCLUT);
+ lcderr("ERROR: only %d color table entries supported\n",
+ STM32_LTDC_NCLUT);
ret = -EINVAL;
}
else
@@ -2418,7 +2419,7 @@ static int stm32_setclut(struct ltdc_layer_s *layer,
return ret;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -2442,9 +2443,10 @@ static int stm32_setclut(struct ltdc_layer_s *layer,
static int stm32_getclut(struct ltdc_layer_s *layer,
struct fb_cmap_s *cmap)
{
- int ret;
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer;
- gvdbg("layer=%p cmap=%p\n", layer, cmap);
+ int ret;
+
+ lcdinfo("layer=%p cmap=%p\n", layer, cmap);
if (priv == &LAYER_L1 || priv == &LAYER_L2)
{
@@ -2460,14 +2462,14 @@ static int stm32_getclut(struct ltdc_layer_s *layer,
#else
if (priv->state.vinfo.fmt != FB_FMT_RGB8)
{
- gdbg("Error: CLUT is not supported for the pixel format: %d\n",
- priv->state.vinfo.fmt);
+ lcderr("ERROR: CLUT is not supported for the pixel format: %d\n",
+ priv->state.vinfo.fmt);
ret = -EINVAL;
}
else if (cmap->first >= STM32_LTDC_NCLUT)
{
- gdbg("Error: only %d color table entries supported\n",
- STM32_LTDC_NCLUT);
+ lcderr("ERROR: only %d color table entries supported\n",
+ STM32_LTDC_NCLUT);
ret = -EINVAL;
}
else
@@ -2489,7 +2491,7 @@ static int stm32_getclut(struct ltdc_layer_s *layer,
cmap->green[n] = clut888[offset + 1];
cmap->red[n] = clut888[offset + 2];
- regvdbg("n=%d, red=%02x, green=%02x, blue=%02x\n", n,
+ reginfo("n=%d, red=%02x, green=%02x, blue=%02x\n", n,
clut888[offset], clut888[offset + 1],
clut888[offset + 2]);
# else
@@ -2498,7 +2500,7 @@ static int stm32_getclut(struct ltdc_layer_s *layer,
cmap->green[n] = (uint8_t)LTDC_CMAP_GREEN(clut[n]);
cmap->blue[n] = (uint8_t)LTDC_CMAP_BLUE(clut[n]);
- regvdbg("n=%d, alpha=%02x, red=%02x, green=%02x, blue=%02x\n", n,
+ reginfo("n=%d, alpha=%02x, red=%02x, green=%02x, blue=%02x\n", n,
DMA2D_CMAP_ALPHA(clut[n]), DMA2D_CMAP_RED(clut[n]),
DMA2D_CMAP_GREEN(clut[n]), DMA2D_CMAP_BLUE(clut[n]));
# endif
@@ -2512,7 +2514,7 @@ static int stm32_getclut(struct ltdc_layer_s *layer,
return ret;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
#endif /* STM32_LAYER_CLUT_SIZE */
@@ -2542,7 +2544,7 @@ static int stm32_getlid(FAR struct ltdc_layer_s *layer, int *lid,
{
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer;
- gvdbg("flag = %08x\n", flag);
+ lcdinfo("flag = %08x\n", flag);
if (stm32_ltdc_lvalidate(priv))
{
@@ -2583,7 +2585,7 @@ static int stm32_getlid(FAR struct ltdc_layer_s *layer, int *lid,
#endif
default:
ret = EINVAL;
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
break;
}
@@ -2592,7 +2594,7 @@ static int stm32_getlid(FAR struct ltdc_layer_s *layer, int *lid,
return ret;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -2617,7 +2619,8 @@ static int stm32_getlid(FAR struct ltdc_layer_s *layer, int *lid,
static int stm32_setcolor(FAR struct ltdc_layer_s *layer, uint32_t argb)
{
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer;
- gvdbg("layer = %p, argb = %08x\n", layer, argb);
+
+ lcdinfo("layer = %p, argb = %08x\n", layer, argb);
if (stm32_ltdc_lvalidate(priv))
{
@@ -2629,7 +2632,7 @@ static int stm32_setcolor(FAR struct ltdc_layer_s *layer, uint32_t argb)
return OK;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -2652,7 +2655,8 @@ static int stm32_setcolor(FAR struct ltdc_layer_s *layer, uint32_t argb)
static int stm32_getcolor(FAR struct ltdc_layer_s *layer, uint32_t *argb)
{
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer;
- gvdbg("layer = %p, argb = %p\n", layer, argb);
+
+ lcdinfo("layer = %p, argb = %p\n", layer, argb);
if (stm32_ltdc_lvalidate(priv))
{
@@ -2663,7 +2667,7 @@ static int stm32_getcolor(FAR struct ltdc_layer_s *layer, uint32_t *argb)
return OK;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -2688,7 +2692,8 @@ static int stm32_getcolor(FAR struct ltdc_layer_s *layer, uint32_t *argb)
static int stm32_setcolorkey(FAR struct ltdc_layer_s *layer, uint32_t rgb)
{
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer;
- gvdbg("layer = %p, argb = %08x\n", layer, rgb);
+
+ lcdinfo("layer = %p, argb = %08x\n", layer, rgb);
if (stm32_ltdc_lvalidate(priv))
{
@@ -2700,7 +2705,7 @@ static int stm32_setcolorkey(FAR struct ltdc_layer_s *layer, uint32_t rgb)
return OK;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -2723,7 +2728,8 @@ static int stm32_setcolorkey(FAR struct ltdc_layer_s *layer, uint32_t rgb)
static int stm32_getcolorkey(FAR struct ltdc_layer_s *layer, uint32_t *rgb)
{
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer;
- gvdbg("layer = %p, argb = %p\n", layer, rgb);
+
+ lcdinfo("layer = %p, argb = %p\n", layer, rgb);
if (stm32_ltdc_lvalidate(priv))
{
@@ -2734,7 +2740,7 @@ static int stm32_getcolorkey(FAR struct ltdc_layer_s *layer, uint32_t *rgb)
return OK;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -2763,7 +2769,8 @@ static int stm32_getcolorkey(FAR struct ltdc_layer_s *layer, uint32_t *rgb)
static int stm32_setalpha(FAR struct ltdc_layer_s *layer, uint8_t alpha)
{
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer;
- gvdbg("layer = %p, alpha = %02x\n", layer, alpha);
+
+ lcdinfo("layer = %p, alpha = %02x\n", layer, alpha);
if (stm32_ltdc_lvalidate(priv))
{
@@ -2775,7 +2782,7 @@ static int stm32_setalpha(FAR struct ltdc_layer_s *layer, uint8_t alpha)
return OK;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -2798,7 +2805,8 @@ static int stm32_setalpha(FAR struct ltdc_layer_s *layer, uint8_t alpha)
static int stm32_getalpha(FAR struct ltdc_layer_s *layer, uint8_t *alpha)
{
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer;
- gvdbg("layer = %p, alpha = %p\n", layer, alpha);
+
+ lcdinfo("layer = %p, alpha = %p\n", layer, alpha);
if (stm32_ltdc_lvalidate(priv))
{
@@ -2809,7 +2817,7 @@ static int stm32_getalpha(FAR struct ltdc_layer_s *layer, uint8_t *alpha)
return OK;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -2856,8 +2864,9 @@ static int stm32_getalpha(FAR struct ltdc_layer_s *layer, uint8_t *alpha)
static int stm32_setblendmode(FAR struct ltdc_layer_s *layer, uint32_t mode)
{
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer;
- uint32_t blendmode = mode;
- gvdbg("layer = %p, mode = %08x\n", layer, mode);
+ uint32_t blendmode = mode;
+
+ lcdinfo("layer = %p, mode = %08x\n", layer, mode);
if (stm32_ltdc_lvalidate(priv))
{
@@ -2926,7 +2935,7 @@ static int stm32_setblendmode(FAR struct ltdc_layer_s *layer, uint32_t mode)
}
if (blendmode)
{
- gdbg("Unknown blendmode %02x\n", blendmode);
+ lcderr("ERROR: Unknown blendmode %02x\n", blendmode);
ret = -EINVAL;
}
@@ -2942,7 +2951,7 @@ static int stm32_setblendmode(FAR struct ltdc_layer_s *layer, uint32_t mode)
return ret;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -2964,7 +2973,8 @@ static int stm32_setblendmode(FAR struct ltdc_layer_s *layer, uint32_t mode)
static int stm32_getblendmode(FAR struct ltdc_layer_s *layer, uint32_t *mode)
{
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer;
- gvdbg("layer = %p, mode = %p\n", layer, mode);
+
+ lcdinfo("layer = %p, mode = %p\n", layer, mode);
if (stm32_ltdc_lvalidate(priv))
{
@@ -2975,7 +2985,7 @@ static int stm32_getblendmode(FAR struct ltdc_layer_s *layer, uint32_t *mode)
return OK;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -3011,8 +3021,9 @@ static int stm32_setarea(FAR struct ltdc_layer_s *layer,
fb_coord_t srcypos)
{
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer;
- gvdbg("layer = %p, area = %p, srcxpos = %d, srcypos = %d\n",
- layer, area, srcxpos, srcypos);
+
+ lcdinfo("layer = %p, area = %p, srcxpos = %d, srcypos = %d\n",
+ layer, area, srcxpos, srcypos);
if (stm32_ltdc_lvalidate(priv))
{
@@ -3039,7 +3050,7 @@ static int stm32_setarea(FAR struct ltdc_layer_s *layer,
return ret;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -3066,8 +3077,9 @@ static int stm32_getarea(FAR struct ltdc_layer_s *layer,
fb_coord_t *srcxpos, fb_coord_t *srcypos)
{
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer;
- gvdbg("layer = %p, area = %p, srcxpos = %p, srcypos = %p\n",
- layer, area, srcxpos, srcypos);
+
+ lcdinfo("layer = %p, area = %p, srcxpos = %p, srcypos = %p\n",
+ layer, area, srcxpos, srcypos);
if (stm32_ltdc_lvalidate(priv))
{
@@ -3080,7 +3092,7 @@ static int stm32_getarea(FAR struct ltdc_layer_s *layer,
return OK;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -3131,7 +3143,7 @@ static int stm32_update(FAR struct ltdc_layer_s *layer, uint32_t mode)
FAR struct stm32_layer_s *inactive = &LAYER(!g_lactive);
#endif
- gvdbg("layer = %p, mode = %08x\n", layer, mode);
+ lcdinfo("layer = %p, mode = %08x\n", layer, mode);
if (stm32_ltdc_lvalidate(priv))
{
@@ -3156,7 +3168,7 @@ static int stm32_update(FAR struct ltdc_layer_s *layer, uint32_t mode)
if (stm32_ltdc_waitforirq() != OK)
{
- gdbg("Returning ECANCELED\n");
+ lcderr("ERROR: Returning ECANCELED\n");
return -ECANCELED;
}
@@ -3238,7 +3250,7 @@ static int stm32_update(FAR struct ltdc_layer_s *layer, uint32_t mode)
return OK;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -3272,8 +3284,8 @@ static int stm32_blit(FAR struct ltdc_layer_s *dest,
{
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)dest;
- gvdbg("dest = %p, destxpos = %d, destypos = %d, src = %p, srcarea = %p\n",
- dest, destxpos, destypos, src, srcarea);
+ lcdinfo("dest = %p, destxpos = %d, destypos = %d, src = %p, srcarea = %p\n",
+ dest, destxpos, destypos, src, srcarea);
if (stm32_ltdc_lvalidate(priv))
{
@@ -3286,7 +3298,7 @@ static int stm32_blit(FAR struct ltdc_layer_s *dest,
return ret;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -3325,10 +3337,10 @@ static int stm32_blend(FAR struct ltdc_layer_s *dest,
{
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)dest;
- gvdbg("dest=%p, destxpos=%d, destypos=%d, "
- "fore=%p, forexpos=%d foreypos=%d, "
- "back=%p, backarea=%p\n",
- dest, destxpos, destypos, fore, forexpos, foreypos, back, backarea);
+ lcdinfo("dest=%p, destxpos=%d, destypos=%d, "
+ "fore=%p, forexpos=%d foreypos=%d, "
+ "back=%p, backarea=%p\n",
+ dest, destxpos, destypos, fore, forexpos, foreypos, back, backarea);
if (stm32_ltdc_lvalidate(priv))
{
@@ -3342,7 +3354,7 @@ static int stm32_blend(FAR struct ltdc_layer_s *dest,
return ret;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
@@ -3370,7 +3382,8 @@ static int stm32_fillarea(FAR struct ltdc_layer_s *layer,
uint32_t color)
{
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer;
- gvdbg("layer = %p, area = %p, color = %08x\n", layer, area, color);
+
+ lcdinfo("layer = %p, area = %p, color = %08x\n", layer, area, color);
if (stm32_ltdc_lvalidate(priv))
{
@@ -3383,7 +3396,7 @@ static int stm32_fillarea(FAR struct ltdc_layer_s *layer,
return ret;
}
- gdbg("Returning EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
return -EINVAL;
}
#endif
@@ -3407,13 +3420,14 @@ static int stm32_fillarea(FAR struct ltdc_layer_s *layer,
FAR struct ltdc_layer_s *stm32_ltdcgetlayer(int lid)
{
- gvdbg("lid: %d\n", lid);
+ lcdinfo("lid: %d\n", lid);
+
if (lid == LTDC_LAYER_L1 || lid == LTDC_LAYER_L2)
{
return (FAR struct ltdc_layer_s *) &LAYER(lid);
}
- gdbg("EINVAL\n");
+ lcderr("ERROR: Returning EINVAL\n");
errno = EINVAL;
return NULL;
}
@@ -3436,7 +3450,7 @@ int stm32_ltdcinitialize(void)
int ret;
#endif
- dbg("Initialize LTDC driver\n");
+ lcdinfo("Initialize LTDC driver\n");
if (g_initialized == true)
{
@@ -3447,16 +3461,16 @@ int stm32_ltdcinitialize(void)
stm32_lcd_enable(false);
- gvdbg("Configuring the LCD controller\n");
+ lcdinfo("Configuring the LCD controller\n");
/* Configure LCD periphery */
- gvdbg("Configure lcd periphery\n");
+ lcdinfo("Configure lcd periphery\n");
stm32_ltdc_periphconfig();
/* Configure global ltdc register */
- gvdbg("Configure global register\n");
+ lcdinfo("Configure global register\n");
stm32_global_configure();
#ifdef CONFIG_STM32_DMA2D
@@ -3472,7 +3486,7 @@ int stm32_ltdcinitialize(void)
/* Initialize ltdc layer */
- gvdbg("Initialize ltdc layer\n");
+ lcdinfo("Initialize ltdc layer\n");
stm32_ltdc_linit(LTDC_LAYER_L1);
#ifdef CONFIG_STM32_LTDC_L2
stm32_ltdc_linit(LTDC_LAYER_L2);
@@ -3493,12 +3507,12 @@ int stm32_ltdcinitialize(void)
/* Reload shadow register */
- gvdbg("Reload shadow register\n");
+ lcdinfo("Reload shadow register\n");
stm32_ltdc_reload(LTDC_SRCR_IMR, false);
/* Turn the LCD on */
- gvdbg("Enabling the display\n");
+ lcdinfo("Enabling the display\n");
stm32_lcd_enable(true);
/* Set initialized state */
@@ -3524,7 +3538,7 @@ int stm32_ltdcinitialize(void)
struct fb_vtable_s *stm32_ltdcgetvplane(int vplane)
{
- gvdbg("vplane: %d\n", vplane);
+ lcdinfo("vplane: %d\n", vplane);
if (vplane == 0)
{
@@ -3600,6 +3614,6 @@ void stm32_backlight(bool blon)
{
/* Set default backlight level CONFIG_STM32_LTDC_DEFBACKLIGHT */
- gdbg("Not supported\n");
+ lcderr("ERROR: Not supported\n");
}
#endif
diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/stm32/stm32_otgfsdev.c
index 81fb004fbce49ee81cbc050ead8cbdfba63fad59..231d091a0cc8bbaedb1ce40af8638d31e9de05b7 100644
--- a/arch/arm/src/stm32/stm32_otgfsdev.c
+++ b/arch/arm/src/stm32/stm32_otgfsdev.c
@@ -81,6 +81,10 @@
# define CONFIG_USBDEV_MAXPOWER 100 /* mA */
#endif
+#ifndef CONFIG_DEBUG_USB_INFO
+# undef CONFIG_STM32_USBDEV_REGDEBUG
+#endif
+
/* There is 1.25Kb of FIFO memory. The default partitions this memory
* so that there is a TxFIFO allocated for each endpoint and with more
* memory provided for the common RxFIFO. A more knowledge-able
@@ -472,7 +476,7 @@ struct stm32_usbdev_s
/* Register operations ********************************************************/
-#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_STM32_USBDEV_REGDEBUG
static uint32_t stm32_getreg(uint32_t addr);
static void stm32_putreg(uint32_t val, uint32_t addr);
#else
@@ -792,7 +796,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] =
*
****************************************************************************/
-#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_STM32_USBDEV_REGDEBUG
static uint32_t stm32_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@@ -813,7 +817,7 @@ static uint32_t stm32_getreg(uint32_t addr)
{
if (count == 4)
{
- lldbg("...\n");
+ uinfo("...\n");
}
return val;
@@ -830,7 +834,7 @@ static uint32_t stm32_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -842,7 +846,7 @@ static uint32_t stm32_getreg(uint32_t addr)
/* Show the register value read */
- lldbg("%08x->%08x\n", addr, val);
+ uinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@@ -855,12 +859,12 @@ static uint32_t stm32_getreg(uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_STM32_USBDEV_REGDEBUG
static void stm32_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- lldbg("%08x<-%08x\n", addr, val);
+ uinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@@ -1218,9 +1222,9 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
return;
}
- ullvdbg("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
- privep->epphy, privreq, privreq->req.len,
- privreq->req.xfrd, privep->zlp);
+ uinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
+ privep->epphy, privreq, privreq->req.len,
+ privreq->req.xfrd, privep->zlp);
/* Check for a special case: If we are just starting a request (xfrd==0) and
* the class driver is trying to send a zero-length packet (len==0). Then set
@@ -1484,8 +1488,8 @@ static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv,
return;
}
- ullvdbg("EP%d: len=%d xfrd=%d\n",
- privep->epphy, privreq->req.len, privreq->req.xfrd);
+ uinfo("EP%d: len=%d xfrd=%d\n",
+ privep->epphy, privreq->req.len, privreq->req.xfrd);
/* Return the completed read request to the class driver and mark the state
* IDLE.
@@ -1519,7 +1523,7 @@ static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt)
DEBUGASSERT(privep && privep->ep.priv);
priv = (FAR struct stm32_usbdev_s *)privep->ep.priv;
- ullvdbg("EP0: bcnt=%d\n", bcnt);
+ uinfo("EP0: bcnt=%d\n", bcnt);
usbtrace(TRACE_READ(EP0), bcnt);
/* Verify that an OUT SETUP request as received before this data was
@@ -1612,7 +1616,8 @@ static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt)
return;
}
- ullvdbg("EP%d: len=%d xfrd=%d\n", privep->epphy, privreq->req.len, privreq->req.xfrd);
+ uinfo("EP%d: len=%d xfrd=%d\n",
+ privep->epphy, privreq->req.len, privreq->req.xfrd);
usbtrace(TRACE_READ(privep->epphy), bcnt);
/* Get the number of bytes to transfer from the RxFIFO */
@@ -1696,7 +1701,7 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv,
return;
}
- ullvdbg("EP%d: len=%d\n", privep->epphy, privreq->req.len);
+ uinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len);
/* Ignore any attempt to receive a zero length packet (this really
* should not happen.
@@ -2490,8 +2495,8 @@ static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv)
ctrlreq.index = GETUINT16(priv->ctrlreq.index);
ctrlreq.len = GETUINT16(priv->ctrlreq.len);
- ullvdbg("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len);
+ uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len);
/* Check for a standard request */
@@ -2625,7 +2630,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv)
if ((daint & 1) != 0)
{
regval = stm32_getreg(STM32_OTGFS_DOEPINT(epno));
- ulldbg("DOEPINT(%d) = %08x\n", epno, regval);
+ uinfo("DOEPINT(%d) = %08x\n", epno, regval);
stm32_putreg(0xFF, STM32_OTGFS_DOEPINT(epno));
}
@@ -2855,8 +2860,8 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv)
{
if ((daint & 1) != 0)
{
- ulldbg("DIEPINT(%d) = %08x\n",
- epno, stm32_getreg(STM32_OTGFS_DIEPINT(epno)));
+ uinfo("DIEPINT(%d) = %08x\n",
+ epno, stm32_getreg(STM32_OTGFS_DIEPINT(epno)));
stm32_putreg(0xFF, STM32_OTGFS_DIEPINT(epno));
}
@@ -3801,7 +3806,7 @@ static int stm32_epout_configure(FAR struct stm32_ep_s *privep, uint8_t eptype,
break;
default:
- udbg("Unsupported maxpacket: %d\n", maxpacket);
+ uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket);
return -EINVAL;
}
}
@@ -3896,7 +3901,7 @@ static int stm32_epin_configure(FAR struct stm32_ep_s *privep, uint8_t eptype,
break;
default:
- udbg("Unsupported maxpacket: %d\n", maxpacket);
+ uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket);
return -EINVAL;
}
}
@@ -4185,7 +4190,7 @@ static int stm32_ep_disable(FAR struct usbdev_ep_s *ep)
{
FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
@@ -4225,7 +4230,7 @@ static FAR struct usbdev_req_s *stm32_ep_allocreq(FAR struct usbdev_ep_s *ep)
{
FAR struct stm32_req_s *privreq;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
@@ -4258,7 +4263,7 @@ static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s
{
FAR struct stm32_req_s *privreq = (FAR struct stm32_req_s *)req;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
@@ -4330,11 +4335,11 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
/* Some sanity checking */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
- ullvdbg("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+ uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
@@ -4342,7 +4347,7 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
usbtrace(TRACE_EPSUBMIT, privep->epphy);
priv = privep->dev;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!priv->driver)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
@@ -4419,7 +4424,7 @@ static int stm32_ep_cancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep;
irqstate_t flags;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
@@ -4877,7 +4882,7 @@ static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered)
usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!dev)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
@@ -5447,7 +5452,7 @@ void up_usbinitialize(void)
ret = irq_attach(STM32_IRQ_OTGFS, stm32_usbinterrupt);
if (ret < 0)
{
- udbg("irq_attach failed\n", ret);
+ uerr("ERROR: irq_attach failed\n", ret);
goto errout;
}
@@ -5560,7 +5565,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
usbtrace(TRACE_DEVREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!driver || !driver->ops->bind || !driver->ops->unbind ||
!driver->ops->disconnect || !driver->ops->setup)
{
@@ -5631,7 +5636,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
usbtrace(TRACE_DEVUNREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (driver != priv->driver)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
diff --git a/arch/arm/src/stm32/stm32_otgfshost.c b/arch/arm/src/stm32/stm32_otgfshost.c
index 81f6ded2697d4c576038b7bc699d319771118fb8..6c340c81fb10511aaa1bdf7544b624d2332f0e34 100644
--- a/arch/arm/src/stm32/stm32_otgfshost.c
+++ b/arch/arm/src/stm32/stm32_otgfshost.c
@@ -93,9 +93,9 @@
* CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever
* want to do that?
* CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access
- * debug. Depends on CONFIG_DEBUG.
+ * debug. Depends on CONFIG_DEBUG_FEATURES.
* CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB
- * packets. Depends on CONFIG_DEBUG.
+ * packets. Depends on CONFIG_DEBUG_FEATURES.
*/
/* Pre-requisites (partial) */
@@ -128,9 +128,9 @@
# define CONFIG_STM32_OTGFS_DESCSIZE 128
#endif
-/* Register/packet debug depends on CONFIG_DEBUG */
+/* Register/packet debug depends on CONFIG_DEBUG_FEATURES */
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_USB_INFO
# undef CONFIG_STM32_USBHOST_REGDEBUG
# undef CONFIG_STM32_USBHOST_PKTDUMP
#endif
@@ -506,7 +506,7 @@ static struct usbhost_connection_s g_usbconn =
#ifdef CONFIG_STM32_USBHOST_REGDEBUG
static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite)
{
- lldbg("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
+ uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
}
#endif
@@ -556,7 +556,7 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite)
{
/* No.. More than one. */
- lldbg("[repeats %d more times]\n", count);
+ uinfo("[repeats %d more times]\n", count);
}
}
@@ -1284,7 +1284,7 @@ static int stm32_ctrlep_alloc(FAR struct stm32_usbhost_s *priv,
ctrlep = (FAR struct stm32_ctrlinfo_s *)kmm_malloc(sizeof(struct stm32_ctrlinfo_s));
if (ctrlep == NULL)
{
- udbg("ERROR: Failed to allocate control endpoint container\n");
+ uerr("ERROR: Failed to allocate control endpoint container\n");
return -ENOMEM;
}
@@ -1294,7 +1294,7 @@ static int stm32_ctrlep_alloc(FAR struct stm32_usbhost_s *priv,
hport->funcaddr, hport->speed, ctrlep);
if (ret < 0)
{
- udbg("ERROR: stm32_ctrlchan_alloc failed: %d\n", ret);
+ uerr("ERROR: stm32_ctrlchan_alloc failed: %d\n", ret);
kmm_free(ctrlep);
return ret;
}
@@ -1346,7 +1346,7 @@ static int stm32_xfrep_alloc(FAR struct stm32_usbhost_s *priv,
chidx = stm32_chan_alloc(priv);
if (chidx < 0)
{
- udbg("ERROR: Failed to allocate a host channel\n");
+ uerr("ERROR: Failed to allocate a host channel\n");
return -ENOMEM;
}
@@ -1856,7 +1856,7 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
ret = stm32_in_setup(priv, chidx);
if (ret < 0)
{
- udbg("ERROR: stm32_in_setup failed: %d\n", ret);
+ uerr("ERROR: stm32_in_setup failed: %d\n", ret);
return (ssize_t)ret;
}
@@ -1887,7 +1887,7 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
{
/* Break out and return the error */
- udbg("ERROR: stm32_chan_wait failed: %d\n", ret);
+ uerr("ERROR: stm32_chan_wait failed: %d\n", ret);
return (ssize_t)ret;
}
}
@@ -1932,13 +1932,13 @@ static void stm32_in_next(FAR struct stm32_usbhost_s *priv,
return;
}
- udbg("ERROR: stm32_in_setup failed: %d\n", ret);
+ uerr("ERROR: stm32_in_setup failed: %d\n", ret);
result = ret;
}
/* The transfer is complete, with or without an error */
- uvdbg("Transfer complete: %d\n", result);
+ uinfo("Transfer complete: %d\n", result);
/* Extract the callback information */
@@ -1990,7 +1990,7 @@ static int stm32_in_asynch(FAR struct stm32_usbhost_s *priv, int chidx,
ret = stm32_chan_asynchsetup(priv, chan, callback, arg);
if (ret < 0)
{
- udbg("ERROR: stm32_chan_asynchsetup failed: %d\n", ret);
+ uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret);
return ret;
}
@@ -1999,7 +1999,7 @@ static int stm32_in_asynch(FAR struct stm32_usbhost_s *priv, int chidx,
ret = stm32_in_setup(priv, chidx);
if (ret < 0)
{
- udbg("ERROR: stm32_in_setup failed: %d\n", ret);
+ uerr("ERROR: stm32_in_setup failed: %d\n", ret);
}
/* And return with the transfer pending */
@@ -2125,7 +2125,7 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
ret = stm32_out_setup(priv, chidx);
if (ret < 0)
{
- udbg("ERROR: stm32_out_setup failed: %d\n", ret);
+ uerr("ERROR: stm32_out_setup failed: %d\n", ret);
return (ssize_t)ret;
}
@@ -2153,7 +2153,7 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
{
/* Break out and return the error */
- udbg("ERROR: stm32_chan_wait failed: %d\n", ret);
+ uerr("ERROR: stm32_chan_wait failed: %d\n", ret);
return (ssize_t)ret;
}
@@ -2218,13 +2218,13 @@ static void stm32_out_next(FAR struct stm32_usbhost_s *priv,
return;
}
- udbg("ERROR: stm32_out_setup failed: %d\n", ret);
+ uerr("ERROR: stm32_out_setup failed: %d\n", ret);
result = ret;
}
/* The transfer is complete, with or without an error */
- uvdbg("Transfer complete: %d\n", result);
+ uinfo("Transfer complete: %d\n", result);
/* Extract the callback information */
@@ -2276,7 +2276,7 @@ static int stm32_out_asynch(FAR struct stm32_usbhost_s *priv, int chidx,
ret = stm32_chan_asynchsetup(priv, chan, callback, arg);
if (ret < 0)
{
- udbg("ERROR: stm32_chan_asynchsetup failed: %d\n", ret);
+ uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret);
return ret;
}
@@ -2285,7 +2285,7 @@ static int stm32_out_asynch(FAR struct stm32_usbhost_s *priv, int chidx,
ret = stm32_out_setup(priv, chidx);
if (ret < 0)
{
- udbg("ERROR: stm32_out_setup failed: %d\n", ret);
+ uerr("ERROR: stm32_out_setup failed: %d\n", ret);
}
/* And return with the transfer pending */
@@ -2370,7 +2370,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
/* AND the two to get the set of enabled, pending HC interrupts */
pending &= regval;
- ullvdbg("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
+ uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
@@ -2631,7 +2631,7 @@ static inline void stm32_gint_hcoutisr(FAR struct stm32_usbhost_s *priv,
/* AND the two to get the set of enabled, pending HC interrupts */
pending &= regval;
- ullvdbg("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
+ uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
@@ -2949,7 +2949,7 @@ static inline void stm32_gint_rxflvlisr(FAR struct stm32_usbhost_s *priv)
/* Read and pop the next status from the Rx FIFO */
grxsts = stm32_getreg(STM32_OTGFS_GRXSTSP);
- ullvdbg("GRXSTS: %08x\n", grxsts);
+ uinfo("GRXSTS: %08x\n", grxsts);
/* Isolate the channel number/index in the status word */
@@ -3102,8 +3102,8 @@ static inline void stm32_gint_nptxfeisr(FAR struct stm32_usbhost_s *priv)
/* Write the next group of packets into the Tx FIFO */
- ullvdbg("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
- regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
+ uinfo("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
+ regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize);
}
@@ -3190,8 +3190,8 @@ static inline void stm32_gint_ptxfeisr(FAR struct stm32_usbhost_s *priv)
/* Write the next group of packets into the Tx FIFO */
- ullvdbg("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
- regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
+ uinfo("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
+ regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize);
}
@@ -3760,7 +3760,7 @@ static int stm32_wait(FAR struct usbhost_connection_s *conn,
*hport = connport;
leave_critical_section(flags);
- uvdbg("RHport Connected: %s\n", connport->connected ? "YES" : "NO");
+ uinfo("RHport Connected: %s\n", connport->connected ? "YES" : "NO");
return OK;
}
@@ -3777,7 +3777,7 @@ static int stm32_wait(FAR struct usbhost_connection_s *conn,
*hport = connport;
leave_critical_section(flags);
- uvdbg("Hub port Connected: %s\n", connport->connected ? "YES" : "NO");
+ uinfo("Hub port Connected: %s\n", connport->connected ? "YES" : "NO");
return OK;
}
#endif
@@ -3865,7 +3865,7 @@ static int stm32_rh_enumerate(FAR struct stm32_usbhost_s *priv,
ret = stm32_ctrlchan_alloc(priv, 0, 0, priv->rhport.hport.speed, &priv->ep0);
if (ret < 0)
{
- udbg("ERROR: Failed to allocate a control endpoint: %d\n", ret);
+ uerr("ERROR: Failed to allocate a control endpoint: %d\n", ret);
}
return ret;
@@ -3897,7 +3897,7 @@ static int stm32_enumerate(FAR struct usbhost_connection_s *conn,
/* Then let the common usbhost_enumerate do the real enumeration. */
- uvdbg("Enumerate the device\n");
+ uinfo("Enumerate the device\n");
priv->smstate = SMSTATE_ENUM;
ret = usbhost_enumerate(hport, &hport->devclass);
@@ -3911,7 +3911,7 @@ static int stm32_enumerate(FAR struct usbhost_connection_s *conn,
{
/* Return to the disconnected state */
- udbg("ERROR: Enumeration failed: %d\n", ret);
+ uerr("ERROR: Enumeration failed: %d\n", ret);
stm32_gint_disconnected(priv);
}
@@ -4312,7 +4312,7 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL);
usbhost_vtrace2(OTGFS_VTRACE2_CTRLIN, req->type, req->req);
- uvdbg("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
+ uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
req->type, req->req, req->value[1], req->value[0],
req->index[1], req->index[0], req->len[1], req->len[0]);
@@ -4397,7 +4397,7 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL);
usbhost_vtrace2(OTGFS_VTRACE2_CTRLOUT, req->type, req->req);
- uvdbg("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
+ uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
req->type, req->req, req->value[1], req->value[0],
req->index[1], req->index[0], req->len[1], req->len[0]);
@@ -4515,7 +4515,7 @@ static ssize_t stm32_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep
unsigned int chidx = (unsigned int)ep;
ssize_t nbytes;
- uvdbg("chidx: %d buflen: %d\n", (unsigned int)ep, buflen);
+ uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen);
DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0);
@@ -4582,7 +4582,7 @@ static int stm32_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
unsigned int chidx = (unsigned int)ep;
int ret;
- uvdbg("chidx: %d buflen: %d\n", (unsigned int)ep, buflen);
+ uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen);
DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0);
@@ -4632,7 +4632,7 @@ static int stm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
unsigned int chidx = (unsigned int)ep;
irqstate_t flags;
- uvdbg("chidx: %u: %d\n", chidx);
+ uinfo("chidx: %u: %d\n", chidx);
DEBUGASSERT(priv && chidx < STM32_MAX_TX_FIFOS);
chan = &priv->chan[chidx];
@@ -4727,7 +4727,7 @@ static int stm32_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
- ullvdbg("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+ uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */
diff --git a/arch/arm/src/stm32/stm32_otghsdev.c b/arch/arm/src/stm32/stm32_otghsdev.c
index 07e9f0af1ca694661d14f28d6947f6dde2ce3628..97d71aa0aa900daa6243fc78d40ea1c87e079a13 100644
--- a/arch/arm/src/stm32/stm32_otghsdev.c
+++ b/arch/arm/src/stm32/stm32_otghsdev.c
@@ -81,6 +81,10 @@
# define CONFIG_USBDEV_MAXPOWER 100 /* mA */
#endif
+#ifndef CONFIG_DEBUG_USB_INFO
+# undef CONFIG_STM32_USBDEV_REGDEBUG
+#endif
+
/* There is 1.25Kb of FIFO memory. The default partitions this memory
* so that there is a TxFIFO allocated for each endpoint and with more
* memory provided for the common RxFIFO. A more knowledge-able
@@ -472,7 +476,7 @@ struct stm32_usbdev_s
/* Register operations ********************************************************/
-#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_STM32_USBDEV_REGDEBUG
static uint32_t stm32_getreg(uint32_t addr);
static void stm32_putreg(uint32_t val, uint32_t addr);
#else
@@ -792,7 +796,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] =
*
****************************************************************************/
-#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_STM32_USBDEV_REGDEBUG
static uint32_t stm32_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@@ -813,7 +817,7 @@ static uint32_t stm32_getreg(uint32_t addr)
{
if (count == 4)
{
- lldbg("...\n");
+ uinfo("...\n");
}
return val;
@@ -830,7 +834,7 @@ static uint32_t stm32_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -842,7 +846,7 @@ static uint32_t stm32_getreg(uint32_t addr)
/* Show the register value read */
- lldbg("%08x->%08x\n", addr, val);
+ uinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@@ -855,12 +859,12 @@ static uint32_t stm32_getreg(uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_STM32_USBDEV_REGDEBUG
static void stm32_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- lldbg("%08x<-%08x\n", addr, val);
+ uinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@@ -1218,9 +1222,9 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
return;
}
- ullvdbg("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
- privep->epphy, privreq, privreq->req.len,
- privreq->req.xfrd, privep->zlp);
+ uinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
+ privep->epphy, privreq, privreq->req.len,
+ privreq->req.xfrd, privep->zlp);
/* Check for a special case: If we are just starting a request (xfrd==0) and
* the class driver is trying to send a zero-length packet (len==0). Then set
@@ -1484,8 +1488,8 @@ static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv,
return;
}
- ullvdbg("EP%d: len=%d xfrd=%d\n",
- privep->epphy, privreq->req.len, privreq->req.xfrd);
+ uinfo("EP%d: len=%d xfrd=%d\n",
+ privep->epphy, privreq->req.len, privreq->req.xfrd);
/* Return the completed read request to the class driver and mark the state
* IDLE.
@@ -1519,7 +1523,7 @@ static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt)
DEBUGASSERT(privep && privep->ep.priv);
priv = (FAR struct stm32_usbdev_s *)privep->ep.priv;
- ullvdbg("EP0: bcnt=%d\n", bcnt);
+ uinfo("EP0: bcnt=%d\n", bcnt);
usbtrace(TRACE_READ(EP0), bcnt);
/* Verify that an OUT SETUP request as received before this data was
@@ -1612,7 +1616,8 @@ static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt)
return;
}
- ullvdbg("EP%d: len=%d xfrd=%d\n", privep->epphy, privreq->req.len, privreq->req.xfrd);
+ uinfo("EP%d: len=%d xfrd=%d\n",
+ privep->epphy, privreq->req.len, privreq->req.xfrd);
usbtrace(TRACE_READ(privep->epphy), bcnt);
/* Get the number of bytes to transfer from the RxFIFO */
@@ -1696,7 +1701,7 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv,
return;
}
- ullvdbg("EP%d: len=%d\n", privep->epphy, privreq->req.len);
+ uinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len);
/* Ignore any attempt to receive a zero length packet (this really
* should not happen.
@@ -2490,8 +2495,8 @@ static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv)
ctrlreq.index = GETUINT16(priv->ctrlreq.index);
ctrlreq.len = GETUINT16(priv->ctrlreq.len);
- ullvdbg("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len);
+ uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len);
/* Check for a standard request */
@@ -2625,7 +2630,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv)
if ((daint & 1) != 0)
{
regval = stm32_getreg(STM32_OTGHS_DOEPINT(epno));
- ulldbg("DOEPINT(%d) = %08x\n", epno, regval);
+ uinfo("DOEPINT(%d) = %08x\n", epno, regval);
stm32_putreg(0xFF, STM32_OTGHS_DOEPINT(epno));
}
@@ -2855,8 +2860,8 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv)
{
if ((daint & 1) != 0)
{
- ulldbg("DIEPINT(%d) = %08x\n",
- epno, stm32_getreg(STM32_OTGHS_DIEPINT(epno)));
+ uinfo("DIEPINT(%d) = %08x\n",
+ epno, stm32_getreg(STM32_OTGHS_DIEPINT(epno)));
stm32_putreg(0xFF, STM32_OTGHS_DIEPINT(epno));
}
@@ -3801,7 +3806,7 @@ static int stm32_epout_configure(FAR struct stm32_ep_s *privep, uint8_t eptype,
break;
default:
- udbg("Unsupported maxpacket: %d\n", maxpacket);
+ uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket);
return -EINVAL;
}
}
@@ -3896,7 +3901,7 @@ static int stm32_epin_configure(FAR struct stm32_ep_s *privep, uint8_t eptype,
break;
default:
- udbg("Unsupported maxpacket: %d\n", maxpacket);
+ uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket);
return -EINVAL;
}
}
@@ -4185,7 +4190,7 @@ static int stm32_ep_disable(FAR struct usbdev_ep_s *ep)
{
FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
@@ -4225,7 +4230,7 @@ static FAR struct usbdev_req_s *stm32_ep_allocreq(FAR struct usbdev_ep_s *ep)
{
FAR struct stm32_req_s *privreq;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
@@ -4258,7 +4263,7 @@ static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s
{
FAR struct stm32_req_s *privreq = (FAR struct stm32_req_s *)req;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
@@ -4330,11 +4335,11 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
/* Some sanity checking */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
- ullvdbg("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+ uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
@@ -4342,7 +4347,7 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
usbtrace(TRACE_EPSUBMIT, privep->epphy);
priv = privep->dev;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!priv->driver)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
@@ -4419,7 +4424,7 @@ static int stm32_ep_cancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep;
irqstate_t flags;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
@@ -4877,7 +4882,7 @@ static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered)
usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!dev)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
@@ -5436,7 +5441,7 @@ void up_usbinitialize(void)
ret = irq_attach(STM32_IRQ_OTGHS, stm32_usbinterrupt);
if (ret < 0)
{
- udbg("irq_attach failed\n", ret);
+ uerr("ERROR: irq_attach failed\n", ret);
goto errout;
}
@@ -5549,7 +5554,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
usbtrace(TRACE_DEVREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!driver || !driver->ops->bind || !driver->ops->unbind ||
!driver->ops->disconnect || !driver->ops->setup)
{
@@ -5620,7 +5625,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
usbtrace(TRACE_DEVUNREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (driver != priv->driver)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
diff --git a/arch/arm/src/stm32/stm32_otghshost.c b/arch/arm/src/stm32/stm32_otghshost.c
index 4c6252a0291e9d5b05404c052bbaca26b15e2862..12a511415bde8bde6d3bf4b9c97ba80f78d4efdb 100644
--- a/arch/arm/src/stm32/stm32_otghshost.c
+++ b/arch/arm/src/stm32/stm32_otghshost.c
@@ -93,9 +93,9 @@
* CONFIG_STM32_OTGHS_SOFINTR - Enable SOF interrupts. Why would you ever
* want to do that?
* CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access
- * debug. Depends on CONFIG_DEBUG.
+ * debug. Depends on CONFIG_DEBUG_FEATURES.
* CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB
- * packets. Depends on CONFIG_DEBUG.
+ * packets. Depends on CONFIG_DEBUG_FEATURES.
*/
/* Pre-requisites (partial) */
@@ -128,9 +128,9 @@
# define CONFIG_STM32_OTGHS_DESCSIZE 128
#endif
-/* Register/packet debug depends on CONFIG_DEBUG */
+/* Register/packet debug depends on CONFIG_DEBUG_FEATURES */
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_USB_INFO
# undef CONFIG_STM32_USBHOST_REGDEBUG
# undef CONFIG_STM32_USBHOST_PKTDUMP
#endif
@@ -506,7 +506,7 @@ static struct usbhost_connection_s g_usbconn =
#ifdef CONFIG_STM32_USBHOST_REGDEBUG
static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite)
{
- lldbg("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
+ uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
}
#endif
@@ -556,7 +556,7 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite)
{
/* No.. More than one. */
- lldbg("[repeats %d more times]\n", count);
+ uinfo("[repeats %d more times]\n", count);
}
}
@@ -1284,7 +1284,7 @@ static int stm32_ctrlep_alloc(FAR struct stm32_usbhost_s *priv,
ctrlep = (FAR struct stm32_ctrlinfo_s *)kmm_malloc(sizeof(struct stm32_ctrlinfo_s));
if (ctrlep == NULL)
{
- udbg("ERROR: Failed to allocate control endpoint container\n");
+ uerr("ERROR: Failed to allocate control endpoint container\n");
return -ENOMEM;
}
@@ -1294,7 +1294,7 @@ static int stm32_ctrlep_alloc(FAR struct stm32_usbhost_s *priv,
hport->funcaddr, hport->speed, ctrlep);
if (ret < 0)
{
- udbg("ERROR: stm32_ctrlchan_alloc failed: %d\n", ret);
+ uerr("ERROR: stm32_ctrlchan_alloc failed: %d\n", ret);
kmm_free(ctrlep);
return ret;
}
@@ -1346,7 +1346,7 @@ static int stm32_xfrep_alloc(FAR struct stm32_usbhost_s *priv,
chidx = stm32_chan_alloc(priv);
if (chidx < 0)
{
- udbg("ERROR: Failed to allocate a host channel\n");
+ uerr("ERROR: Failed to allocate a host channel\n");
return -ENOMEM;
}
@@ -1856,7 +1856,7 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
ret = stm32_in_setup(priv, chidx);
if (ret < 0)
{
- udbg("ERROR: stm32_in_setup failed: %d\n", ret);
+ uerr("ERROR: stm32_in_setup failed: %d\n", ret);
return (ssize_t)ret;
}
@@ -1887,7 +1887,7 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
{
/* Break out and return the error */
- udbg("ERROR: stm32_chan_wait failed: %d\n", ret);
+ uerr("ERROR: stm32_chan_wait failed: %d\n", ret);
return (ssize_t)ret;
}
}
@@ -1932,13 +1932,13 @@ static void stm32_in_next(FAR struct stm32_usbhost_s *priv,
return;
}
- udbg("ERROR: stm32_in_setup failed: %d\n", ret);
+ uerr("ERROR: stm32_in_setup failed: %d\n", ret);
result = ret;
}
/* The transfer is complete, with or without an error */
- uvdbg("Transfer complete: %d\n", result);
+ uinfo("Transfer complete: %d\n", result);
/* Extract the callback information */
@@ -1990,7 +1990,7 @@ static int stm32_in_asynch(FAR struct stm32_usbhost_s *priv, int chidx,
ret = stm32_chan_asynchsetup(priv, chan, callback, arg);
if (ret < 0)
{
- udbg("ERROR: stm32_chan_asynchsetup failed: %d\n", ret);
+ uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret);
return ret;
}
@@ -1999,7 +1999,7 @@ static int stm32_in_asynch(FAR struct stm32_usbhost_s *priv, int chidx,
ret = stm32_in_setup(priv, chidx);
if (ret < 0)
{
- udbg("ERROR: stm32_in_setup failed: %d\n", ret);
+ uerr("ERROR: stm32_in_setup failed: %d\n", ret);
}
/* And return with the transfer pending */
@@ -2125,7 +2125,7 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
ret = stm32_out_setup(priv, chidx);
if (ret < 0)
{
- udbg("ERROR: stm32_out_setup failed: %d\n", ret);
+ uerr("ERROR: stm32_out_setup failed: %d\n", ret);
return (ssize_t)ret;
}
@@ -2153,7 +2153,7 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
{
/* Break out and return the error */
- udbg("ERROR: stm32_chan_wait failed: %d\n", ret);
+ uerr("ERROR: stm32_chan_wait failed: %d\n", ret);
return (ssize_t)ret;
}
@@ -2218,13 +2218,13 @@ static void stm32_out_next(FAR struct stm32_usbhost_s *priv,
return;
}
- udbg("ERROR: stm32_out_setup failed: %d\n", ret);
+ uerr("ERROR: stm32_out_setup failed: %d\n", ret);
result = ret;
}
/* The transfer is complete, with or without an error */
- uvdbg("Transfer complete: %d\n", result);
+ uinfo("Transfer complete: %d\n", result);
/* Extract the callback information */
@@ -2276,7 +2276,7 @@ static int stm32_out_asynch(FAR struct stm32_usbhost_s *priv, int chidx,
ret = stm32_chan_asynchsetup(priv, chan, callback, arg);
if (ret < 0)
{
- udbg("ERROR: stm32_chan_asynchsetup failed: %d\n", ret);
+ uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret);
return ret;
}
@@ -2285,7 +2285,7 @@ static int stm32_out_asynch(FAR struct stm32_usbhost_s *priv, int chidx,
ret = stm32_out_setup(priv, chidx);
if (ret < 0)
{
- udbg("ERROR: stm32_out_setup failed: %d\n", ret);
+ uerr("ERROR: stm32_out_setup failed: %d\n", ret);
}
/* And return with the transfer pending */
@@ -2370,7 +2370,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
/* AND the two to get the set of enabled, pending HC interrupts */
pending &= regval;
- ullvdbg("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
+ uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
@@ -2631,7 +2631,7 @@ static inline void stm32_gint_hcoutisr(FAR struct stm32_usbhost_s *priv,
/* AND the two to get the set of enabled, pending HC interrupts */
pending &= regval;
- ullvdbg("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
+ uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
@@ -2949,7 +2949,7 @@ static inline void stm32_gint_rxflvlisr(FAR struct stm32_usbhost_s *priv)
/* Read and pop the next status from the Rx FIFO */
grxsts = stm32_getreg(STM32_OTGHS_GRXSTSP);
- ullvdbg("GRXSTS: %08x\n", grxsts);
+ uinfo("GRXSTS: %08x\n", grxsts);
/* Isolate the channel number/index in the status word */
@@ -3102,8 +3102,8 @@ static inline void stm32_gint_nptxfeisr(FAR struct stm32_usbhost_s *priv)
/* Write the next group of packets into the Tx FIFO */
- ullvdbg("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %dwrsize: %d\n",
- regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
+ uinfo("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %dwrsize: %d\n",
+ regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize);
}
@@ -3190,8 +3190,8 @@ static inline void stm32_gint_ptxfeisr(FAR struct stm32_usbhost_s *priv)
/* Write the next group of packets into the Tx FIFO */
- ullvdbg("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
- regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
+ uinfo("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
+ regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize);
}
@@ -3760,7 +3760,7 @@ static int stm32_wait(FAR struct usbhost_connection_s *conn,
*hport = connport;
leave_critical_section(flags);
- uvdbg("RHport Connected: %s\n", connport->connected ? "YES" : "NO");
+ uinfo("RHport Connected: %s\n", connport->connected ? "YES" : "NO");
return OK;
}
@@ -3777,7 +3777,7 @@ static int stm32_wait(FAR struct usbhost_connection_s *conn,
*hport = connport;
leave_critical_section(flags);
- uvdbg("Hub port Connected: %s\n", connport->connected ? "YES" : "NO");
+ uinfo("Hub port Connected: %s\n", connport->connected ? "YES" : "NO");
return OK;
}
#endif
@@ -3865,7 +3865,7 @@ static int stm32_rh_enumerate(FAR struct stm32_usbhost_s *priv,
ret = stm32_ctrlchan_alloc(priv, 0, 0, priv->rhport.hport.speed, &priv->ep0);
if (ret < 0)
{
- udbg("ERROR: Failed to allocate a control endpoint: %d\n", ret);
+ uerr("ERROR: Failed to allocate a control endpoint: %d\n", ret);
}
return ret;
@@ -3897,7 +3897,7 @@ static int stm32_enumerate(FAR struct usbhost_connection_s *conn,
/* Then let the common usbhost_enumerate do the real enumeration. */
- uvdbg("Enumerate the device\n");
+ uinfo("Enumerate the device\n");
priv->smstate = SMSTATE_ENUM;
ret = usbhost_enumerate(hport, &hport->devclass);
@@ -3911,7 +3911,7 @@ static int stm32_enumerate(FAR struct usbhost_connection_s *conn,
{
/* Return to the disconnected state */
- udbg("ERROR: Enumeration failed: %d\n", ret);
+ uerr("ERROR: Enumeration failed: %d\n", ret);
stm32_gint_disconnected(priv);
}
@@ -4312,7 +4312,7 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL);
usbhost_vtrace2(OTGHS_VTRACE2_CTRLIN, req->type, req->req);
- uvdbg("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
+ uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
req->type, req->req, req->value[1], req->value[0],
req->index[1], req->index[0], req->len[1], req->len[0]);
@@ -4397,7 +4397,7 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL);
usbhost_vtrace2(OTGHS_VTRACE2_CTRLOUT, req->type, req->req);
- uvdbg("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
+ uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
req->type, req->req, req->value[1], req->value[0],
req->index[1], req->index[0], req->len[1], req->len[0]);
@@ -4515,7 +4515,7 @@ static ssize_t stm32_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep
unsigned int chidx = (unsigned int)ep;
ssize_t nbytes;
- uvdbg("chidx: %d buflen: %d\n", (unsigned int)ep, buflen);
+ uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen);
DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0);
@@ -4582,7 +4582,7 @@ static int stm32_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
unsigned int chidx = (unsigned int)ep;
int ret;
- uvdbg("chidx: %d buflen: %d\n", (unsigned int)ep, buflen);
+ uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen);
DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0);
@@ -4632,7 +4632,7 @@ static int stm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
unsigned int chidx = (unsigned int)ep;
irqstate_t flags;
- uvdbg("chidx: %u: %d\n", chidx);
+ uinfo("chidx: %u: %d\n", chidx);
DEBUGASSERT(priv && chidx < STM32_MAX_TX_FIFOS);
chan = &priv->chan[chidx];
@@ -4727,7 +4727,7 @@ static int stm32_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
- ullvdbg("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+ uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */
diff --git a/arch/arm/src/stm32/stm32_procfs_ccm.c b/arch/arm/src/stm32/stm32_procfs_ccm.c
index 231f37dd9c4c7fe7c9108edf9d3e3cfd364f1089..51d1022146dce79d7246673ec378d5ee82dc5abd 100644
--- a/arch/arm/src/stm32/stm32_procfs_ccm.c
+++ b/arch/arm/src/stm32/stm32_procfs_ccm.c
@@ -142,7 +142,7 @@ static int ccm_open(FAR struct file *filep, FAR const char *relpath,
{
FAR struct ccm_file_s *priv;
- fvdbg("Open '%s'\n", relpath);
+ finfo("Open '%s'\n", relpath);
/* PROCFS is read-only. Any attempt to open with any kind of write
* access is not permitted.
@@ -152,7 +152,7 @@ static int ccm_open(FAR struct file *filep, FAR const char *relpath,
if ((oflags & O_WRONLY) != 0 || (oflags & O_RDONLY) == 0)
{
- fdbg("ERROR: Only O_RDONLY supported\n");
+ ferr("ERROR: Only O_RDONLY supported\n");
return -EACCES;
}
@@ -160,7 +160,7 @@ static int ccm_open(FAR struct file *filep, FAR const char *relpath,
if (strcmp(relpath, "ccm") != 0)
{
- fdbg("ERROR: relpath is '%s'\n", relpath);
+ ferr("ERROR: relpath is '%s'\n", relpath);
return -ENOENT;
}
@@ -169,7 +169,7 @@ static int ccm_open(FAR struct file *filep, FAR const char *relpath,
priv = (FAR struct ccm_file_s *)kmm_zalloc(sizeof(struct ccm_file_s));
if (!priv)
{
- fdbg("ERROR: Failed to allocate file attributes\n");
+ ferr("ERROR: Failed to allocate file attributes\n");
return -ENOMEM;
}
@@ -214,7 +214,7 @@ static ssize_t ccm_read(FAR struct file *filep, FAR char *buffer,
struct mallinfo mem;
off_t offset = filep->f_pos;
- fvdbg("buffer=%p buflen=%d\n", buffer, (int)buflen);
+ finfo("buffer=%p buflen=%d\n", buffer, (int)buflen);
/* Recover our private data from the struct file instance */
@@ -273,7 +273,7 @@ static int ccm_dup(FAR const struct file *oldp, FAR struct file *newp)
FAR struct ccm_file_s *oldpriv;
FAR struct ccm_file_s *newpriv;
- fvdbg("Dup %p->%p\n", oldp, newp);
+ finfo("Dup %p->%p\n", oldp, newp);
/* Recover our private data from the old struct file instance */
@@ -285,7 +285,7 @@ static int ccm_dup(FAR const struct file *oldp, FAR struct file *newp)
newpriv = (FAR struct ccm_file_s *)kmm_zalloc(sizeof(struct ccm_file_s));
if (!newpriv)
{
- fdbg("ERROR: Failed to allocate file attributes\n");
+ ferr("ERROR: Failed to allocate file attributes\n");
return -ENOMEM;
}
@@ -303,7 +303,7 @@ static int ccm_stat(const char *relpath, struct stat *buf)
{
if (strcmp(relpath, "ccm") != 0)
{
- fdbg("ERROR: relpath is '%s'\n", relpath);
+ ferr("ERROR: relpath is '%s'\n", relpath);
return -ENOENT;
}
diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c
index 8779d18692fa9108f2cb09ee314747d513463951..7b8f4224e0889b29ca6d412ed7f2097970607023 100644
--- a/arch/arm/src/stm32/stm32_pwm.c
+++ b/arch/arm/src/stm32/stm32_pwm.c
@@ -115,29 +115,10 @@
#define TIMTYPE_TIM17 TIMTYPE_COUNTUP16
/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing PWM */
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_PWM
-#endif
-
-#ifdef CONFIG_DEBUG_PWM
-# define pwmdbg dbg
-# define pwmlldbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define pwmvdbg vdbg
-# define pwmllvdbg llvdbg
-# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
-# else
-# define pwmlldbg(x...)
-# define pwmllvdbg(x...)
-# define pwm_dumpgpio(p,m)
-# endif
+
+#ifdef CONFIG_DEBUG_PWM_INFO
+# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
#else
-# define pwmdbg(x...)
-# define pwmlldbg(x...)
-# define pwmvdbg(x...)
-# define pwmllvdbg(x...)
# define pwm_dumpgpio(p,m)
#endif
@@ -166,8 +147,8 @@ enum stm32_chanmode_e
struct stm32_pwmchan_s
{
- uint8_t channel; /* Timer output channel: {1,..4} */
- uint32_t pincfg; /* Output pin configuration */
+ uint8_t channel; /* Timer output channel: {1,..4} */
+ uint32_t pincfg; /* Output pin configuration */
enum stm32_chanmode_e mode;
};
@@ -176,21 +157,23 @@ struct stm32_pwmchan_s
struct stm32_pwmtimer_s
{
FAR const struct pwm_ops_s *ops; /* PWM operations */
- uint8_t timid; /* Timer ID {1,...,17} */
- struct stm32_pwmchan_s channels[PWM_NCHANNELS];
- uint8_t timtype; /* See the TIMTYPE_* definitions */
- enum stm32_timmode_e mode;
+ uint8_t timid; /* Timer ID {1,...,17} */
+ struct stm32_pwmchan_s channels[PWM_NCHANNELS];
+ uint8_t timtype; /* See the TIMTYPE_* definitions */
+ enum stm32_timmode_e mode;
#ifdef CONFIG_PWM_PULSECOUNT
- uint8_t irq; /* Timer update IRQ */
- uint8_t prev; /* The previous value of the RCR (pre-loaded) */
- uint8_t curr; /* The current value of the RCR (pre-loaded) */
- uint32_t count; /* Remaining pluse count */
+ uint8_t irq; /* Timer update IRQ */
+ uint8_t prev; /* The previous value of the RCR (pre-loaded) */
+ uint8_t curr; /* The current value of the RCR (pre-loaded) */
+ uint32_t count; /* Remaining pluse count */
+#else
+ uint32_t frequency; /* Current frequency setting */
#endif
- uint32_t base; /* The base address of the timer */
- uint32_t pclk; /* The frequency of the peripheral clock
+ uint32_t base; /* The base address of the timer */
+ uint32_t pclk; /* The frequency of the peripheral clock
* that drives the timer module. */
#ifdef CONFIG_PWM_PULSECOUNT
- FAR void *handle; /* Handle used for upper-half callback */
+ FAR void *handle; /* Handle used for upper-half callback */
#endif
};
@@ -202,7 +185,7 @@ struct stm32_pwmtimer_s
static uint16_t pwm_getreg(struct stm32_pwmtimer_s *priv, int offset);
static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, uint16_t value);
-#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_PWM_INFO
static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg);
#else
# define pwm_dumpregs(priv,msg)
@@ -758,7 +741,7 @@ static struct stm32_pwmtimer_s g_pwm13dev =
.irq = STM32_IRQ_TIM13,
#endif
.base = STM32_TIM13_BASE,
- .pclk = STM32_APB1_TIM13_CLKIN,
+ .pclk = STM32_APB1_TIM13_CLKIN,
};
#endif
@@ -967,26 +950,26 @@ static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, uint16_t value
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE)
+#ifdef CONFIG_DEBUG_PWM_INFO
static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg)
{
- pwmvdbg("%s:\n", msg);
- pwmvdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
+ pwminfo("%s:\n", msg);
+ pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
pwm_getreg(priv, STM32_GTIM_CR1_OFFSET),
pwm_getreg(priv, STM32_GTIM_CR2_OFFSET),
pwm_getreg(priv, STM32_GTIM_SMCR_OFFSET),
pwm_getreg(priv, STM32_GTIM_DIER_OFFSET));
- pwmvdbg(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n",
+ pwminfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n",
pwm_getreg(priv, STM32_GTIM_SR_OFFSET),
pwm_getreg(priv, STM32_GTIM_EGR_OFFSET),
pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET),
pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET));
- pwmvdbg(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
+ pwminfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
pwm_getreg(priv, STM32_GTIM_CCER_OFFSET),
pwm_getreg(priv, STM32_GTIM_CNT_OFFSET),
pwm_getreg(priv, STM32_GTIM_PSC_OFFSET),
pwm_getreg(priv, STM32_GTIM_ARR_OFFSET));
- pwmvdbg(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
+ pwminfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET),
pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET),
pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET),
@@ -994,7 +977,7 @@ static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg)
#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM)
if (priv->timtype == TIMTYPE_ADVANCED)
{
- pwmvdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
+ pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
pwm_getreg(priv, STM32_ATIM_RCR_OFFSET),
pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET),
pwm_getreg(priv, STM32_ATIM_DCR_OFFSET),
@@ -1003,7 +986,7 @@ static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg)
else
#endif
{
- pwmvdbg(" DCR: %04x DMAR: %04x\n",
+ pwminfo(" DCR: %04x DMAR: %04x\n",
pwm_getreg(priv, STM32_GTIM_DCR_OFFSET),
pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET));
}
@@ -1066,15 +1049,15 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
DEBUGASSERT(priv != NULL && info != NULL);
#if defined(CONFIG_PWM_MULTICHAN)
- pwmvdbg("TIM%d frequency: %d\n",
+ pwminfo("TIM%u frequency: %u\n",
priv->timid, info->frequency);
#elif defined(CONFIG_PWM_PULSECOUNT)
- pwmvdbg("TIM%d channel: %d frequency: %d duty: %08x count: %d\n",
- priv->timid, priv->channel, info->frequency,
+ pwminfo("TIM%u channel: %u frequency: %u duty: %08x count: %u\n",
+ priv->timid, priv->channels[0].channel, info->frequency,
info->duty, info->count);
#else
- pwmvdbg("TIM%d channel: %d frequency: %d duty: %08x\n",
- priv->timid, priv->channel, info->frequency, info->duty);
+ pwminfo("TIM%u channel: %u frequency: %u duty: %08x\n",
+ priv->timid, priv->channels[0].channel, info->frequency, info->duty);
#endif
DEBUGASSERT(info->frequency > 0);
@@ -1144,7 +1127,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
reload = 65535;
}
- pwmvdbg("TIM%d PCLK: %d frequency: %d TIMCLK: %d prescaler: %d reload: %d\n",
+ pwminfo("TIM%u PCLK: %u frequency: %u TIMCLK: %u prescaler: %u reload: %u\n",
priv->timid, priv->pclk, info->frequency, timclk, prescaler, reload);
/* Set up the timer CR1 register:
@@ -1207,7 +1190,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
break;
default:
- pwmdbg("No such timer mode: %d\n", (int)priv->mode);
+ pwmerr("ERROR: No such timer mode: %u\n", (unsigned int)priv->mode);
return -EINVAL;
}
}
@@ -1314,6 +1297,15 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
duty = info->channels[i].duty;
channel = info->channels[i].channel;
+ /* A value of zero means to skip this channel */
+
+ if (channel == 0)
+ {
+ continue;
+ }
+
+ /* Find the channel */
+
for (j = 0; j < PWM_NCHANNELS; j++)
{
if (priv->channels[j].channel == channel)
@@ -1325,7 +1317,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
if (j >= PWM_NCHANNELS)
{
- pwmdbg("No such channel: %d\n", channel);
+ pwmerr("ERROR: No such channel: %u\n", channel);
return -EINVAL;
}
#else
@@ -1341,7 +1333,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
ccr = b16toi(duty * reload + b16HALF);
- pwmvdbg("ccr: %d\n", ccr);
+ pwminfo("ccr: %u\n", ccr);
switch (mode)
{
@@ -1376,7 +1368,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
#endif
default:
- pwmdbg("No such mode: %d\n", (int)mode);
+ pwmerr("ERROR: No such mode: %u\n", (unsigned int)mode);
return -EINVAL;
}
@@ -1483,7 +1475,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
break;
default:
- pwmdbg("No such channel: %d\n", channel);
+ pwmerr("ERROR: No such channel: %u\n", channel);
return -EINVAL;
}
}
@@ -1625,6 +1617,89 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
return OK;
}
+#ifndef CONFIG_PWM_PULSECOUNT
+/****************************************************************************
+ * Name: pwm_update_duty
+ *
+ * Description:
+ * Try to change only channel duty.
+ *
+ * Input parameters:
+ * priv - A reference to the lower half PWM driver state structure
+ * channel - Channel to by updated
+ * duty - New duty.
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_update_duty(FAR struct stm32_pwmtimer_s *priv, uint8_t channel,
+ ub16_t duty)
+{
+ /* Register offset */
+
+ int ccr_offset;
+
+ /* Calculated values */
+
+ uint32_t reload;
+ uint32_t ccr;
+
+ DEBUGASSERT(priv != NULL);
+
+ pwminfo("TIM%u channel: %u duty: %08x\n",
+ priv->timid, channel, duty);
+
+#ifndef CONFIG_PWM_MULTICHAN
+ DEBUGASSERT(channel == priv->channels[0].channel);
+ DEBUGASSERT(duty >= 0 && duty < uitoub16(100));
+#endif
+
+ /* Get the reload values */
+
+ reload = pwm_getreg(priv, STM32_GTIM_ARR_OFFSET);
+
+ /* Duty cycle:
+ *
+ * duty cycle = ccr / reload (fractional value)
+ */
+
+ ccr = b16toi(duty * reload + b16HALF);
+
+ pwminfo("ccr: %u\n", ccr);
+
+ switch (channel)
+ {
+ case 1: /* Register offset for Channel 1 */
+ ccr_offset = STM32_GTIM_CCR1_OFFSET;
+ break;
+
+ case 2: /* Register offset for Channel 2 */
+ ccr_offset = STM32_GTIM_CCR2_OFFSET;
+ break;
+
+ case 3: /* Register offset for Channel 3 */
+ ccr_offset = STM32_GTIM_CCR3_OFFSET;
+ break;
+
+ case 4: /* Register offset for Channel 4 */
+ ccr_offset = STM32_GTIM_CCR4_OFFSET;
+ break;
+
+ default:
+ pwmerr("ERROR: No such channel: %u\n", channel);
+ return -EINVAL;
+ }
+
+ /* Set the duty cycle by writing to the CCR register for this channel */
+
+ pwm_putreg(priv, ccr_offset, (uint16_t)ccr);
+
+ return OK;
+}
+#endif
+
/****************************************************************************
* Name: pwm_interrupt
*
@@ -1701,8 +1776,8 @@ static int pwm_interrupt(struct stm32_pwmtimer_s *priv)
/* Now all of the time critical stuff is done so we can do some debug output */
- pwmllvdbg("Update interrupt SR: %04x prev: %d curr: %d count: %d\n",
- regval, priv->prev, priv->curr, priv->count);
+ pwminfo("Update interrupt SR: %04x prev: %u curr: %u count: %u\n",
+ regval, priv->prev, priv->curr, priv->count);
return OK;
}
@@ -1894,6 +1969,8 @@ static void pwm_set_apb_clock(FAR struct stm32_pwmtimer_s *priv, bool on)
en_bit = RCC_APB2ENR_TIM17EN;
break;
#endif
+ default:
+ return;
}
/* Enable/disable APB 1/2 clock for timer */
@@ -1934,7 +2011,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
uint32_t pincfg;
int i;
- pwmvdbg("TIM%d\n", priv->timid);
+ pwminfo("TIM%u\n", priv->timid);
pwm_dumpregs(priv, "Initially");
/* Enable APB1/2 clocking for timer. */
@@ -1951,7 +2028,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
continue;
}
- pwmvdbg("pincfg: %08x\n", pincfg);
+ pwminfo("pincfg: %08x\n", pincfg);
stm32_configgpio(pincfg);
pwm_dumpgpio(pincfg, "PWM setup");
@@ -1982,7 +2059,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
uint32_t pincfg;
int i;
- pwmvdbg("TIM%d\n", priv->timid);
+ pwminfo("TIM%u\n", priv->timid);
/* Make sure that the output has been stopped */
@@ -2002,7 +2079,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
continue;
}
- pwmvdbg("pincfg: %08x\n", pincfg);
+ pwminfo("pincfg: %08x\n", pincfg);
pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK);
@@ -2053,7 +2130,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
if (priv->timtype != TIMTYPE_ADVANCED)
{
- pwmdbg("ERROR: TIM%d cannot support pulse count: %d\n",
+ pwmerr("ERROR: TIM%u cannot support pulse count: %u\n",
priv->timid, info->count);
return -EPERM;
}
@@ -2071,8 +2148,42 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
FAR const struct pwm_info_s *info)
{
+ int ret = OK;
FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
- return pwm_timer(priv, info);
+
+#ifndef CONFIG_PWM_PULSECOUNT
+ /* if frequency has not changed we just update duty */
+
+ if (info->frequency == priv->frequency)
+ {
+#ifdef CONFIG_PWM_MULTICHAN
+ int i;
+
+ for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++)
+ {
+ ret = pwm_update_duty(priv,info->channels[i].channel,
+ info->channels[i].duty);
+ }
+#else
+ ret = pwm_update_duty(priv,priv->channels[0].channel,info->duty);
+#endif
+ }
+ else
+#endif
+ {
+ ret = pwm_timer(priv, info);
+
+#ifndef CONFIG_PWM_PULSECOUNT
+ /* Save current frequency */
+
+ if (ret == OK)
+ {
+ priv->frequency = info->frequency;
+ }
+#endif
+ }
+
+ return ret;
}
#endif
@@ -2103,7 +2214,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
uint32_t regval;
irqstate_t flags;
- pwmvdbg("TIM%d\n", priv->timid);
+ pwminfo("TIM%u\n", priv->timid);
/* Disable interrupts momentary to stop any ongoing timer processing and
* to prevent any concurrent access to the reset register.
@@ -2111,6 +2222,10 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
flags = enter_critical_section();
+ /* Stopped so frequency is zero */
+
+ priv->frequency = 0;
+
/* Disable further interrupts and stop the timer */
pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0);
@@ -2210,6 +2325,8 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
resetbit = RCC_APB2RSTR_TIM17RST;
break;
#endif
+ default:
+ return -EINVAL;
}
/* Reset the timer - stopping the output and putting the timer back
@@ -2224,7 +2341,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
putreg32(regval, regaddr);
leave_critical_section(flags);
- pwmvdbg("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
+ pwminfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
pwm_dumpregs(priv, "After stop");
return OK;
}
@@ -2247,12 +2364,12 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg)
{
-#ifdef CONFIG_DEBUG_PWM
+#ifdef CONFIG_DEBUG_PWM_INFO
FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
/* There are no platform-specific ioctl commands */
- pwmvdbg("TIM%d\n", priv->timid);
+ pwminfo("TIM%u\n", priv->timid);
#endif
return -ENOTTY;
}
@@ -2282,7 +2399,7 @@ FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer)
{
FAR struct stm32_pwmtimer_s *lower;
- pwmvdbg("TIM%d\n", timer);
+ pwminfo("TIM%u\n", timer);
switch (timer)
{
@@ -2391,7 +2508,7 @@ FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer)
#endif
default:
- pwmdbg("No such timer configured\n");
+ pwmerr("ERROR: No such timer configured\n");
return NULL;
}
diff --git a/arch/arm/src/stm32/stm32_qencoder.c b/arch/arm/src/stm32/stm32_qencoder.c
index 5cec5e0874d2fdac8bb23999a7173059e3197853..7d87debe334c9b1c324c6000aba5dfca637e1916 100644
--- a/arch/arm/src/stm32/stm32_qencoder.c
+++ b/arch/arm/src/stm32/stm32_qencoder.c
@@ -247,12 +247,12 @@
/* Debug ****************************************************************************/
/* Non-standard debug that may be enabled just for testing the quadrature encoder */
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_FEATURES
# undef CONFIG_DEBUG_SENSORS
#endif
#ifdef CONFIG_DEBUG_SENSORS
-# ifdef CONFIG_DEBUG_VERBOSE
+# ifdef CONFIG_DEBUG_INFO
# define qe_dumpgpio(p,m) stm32_dumpgpio(p,m)
# else
# define qe_dumpgpio(p,m)
@@ -317,7 +317,7 @@ static void stm32_putreg16(FAR struct stm32_lowerhalf_s *priv, int offset, uint1
static uint32_t stm32_getreg32(FAR struct stm32_lowerhalf_s *priv, int offset);
static void stm32_putreg32(FAR struct stm32_lowerhalf_s *priv, int offset, uint32_t value);
-#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_VERBOSE)
+#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO)
static void stm32_dumpregs(FAR struct stm32_lowerhalf_s *priv, FAR const char *msg);
#else
# define stm32_dumpregs(priv,msg)
@@ -631,26 +631,26 @@ static void stm32_putreg32(FAR struct stm32_lowerhalf_s *priv, int offset, uint3
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_VERBOSE)
+#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO)
static void stm32_dumpregs(FAR struct stm32_lowerhalf_s *priv, FAR const char *msg)
{
- snvdbg("%s:\n", msg);
- snvdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
+ sninfo("%s:\n", msg);
+ sninfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET),
stm32_getreg16(priv, STM32_GTIM_CR2_OFFSET),
stm32_getreg16(priv, STM32_GTIM_SMCR_OFFSET),
stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET));
- snvdbg(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n",
+ sninfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n",
stm32_getreg16(priv, STM32_GTIM_SR_OFFSET),
stm32_getreg16(priv, STM32_GTIM_EGR_OFFSET),
stm32_getreg16(priv, STM32_GTIM_CCMR1_OFFSET),
stm32_getreg16(priv, STM32_GTIM_CCMR2_OFFSET));
- snvdbg(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
+ sninfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET),
stm32_getreg16(priv, STM32_GTIM_CNT_OFFSET),
stm32_getreg16(priv, STM32_GTIM_PSC_OFFSET),
stm32_getreg16(priv, STM32_GTIM_ARR_OFFSET));
- snvdbg(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
+ sninfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
stm32_getreg16(priv, STM32_GTIM_CCR1_OFFSET),
stm32_getreg16(priv, STM32_GTIM_CCR2_OFFSET),
stm32_getreg16(priv, STM32_GTIM_CCR3_OFFSET),
@@ -658,7 +658,7 @@ static void stm32_dumpregs(FAR struct stm32_lowerhalf_s *priv, FAR const char *m
#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE)
if (priv->config->timid == 1 || priv->config->timid == 8)
{
- snvdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
+ sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
stm32_getreg16(priv, STM32_ATIM_RCR_OFFSET),
stm32_getreg16(priv, STM32_ATIM_BDTR_OFFSET),
stm32_getreg16(priv, STM32_ATIM_DCR_OFFSET),
@@ -667,7 +667,7 @@ static void stm32_dumpregs(FAR struct stm32_lowerhalf_s *priv, FAR const char *m
else
#endif
{
- snvdbg(" DCR: %04x DMAR: %04x\n",
+ sninfo(" DCR: %04x DMAR: %04x\n",
stm32_getreg16(priv, STM32_GTIM_DCR_OFFSET),
stm32_getreg16(priv, STM32_GTIM_DMAR_OFFSET));
}
@@ -1125,7 +1125,7 @@ static int stm32_shutdown(FAR struct qe_lowerhalf_s *lower)
putreg32(regval, regaddr);
leave_critical_section(flags);
- snvdbg("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
+ sninfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
stm32_dumpregs(priv, "After stop");
/* Put the TI1 GPIO pin back to its default state */
@@ -1203,7 +1203,7 @@ static int stm32_reset(FAR struct qe_lowerhalf_s *lower)
#ifdef HAVE_16BIT_TIMERS
irqstate_t flags;
- snvdbg("Resetting position to zero\n");
+ sninfo("Resetting position to zero\n");
DEBUGASSERT(lower && priv->inuse);
/* Reset the timer and the counter. Interrupts are disabled to make this atomic
@@ -1215,7 +1215,7 @@ static int stm32_reset(FAR struct qe_lowerhalf_s *lower)
priv->position = 0;
leave_critical_section(flags);
#else
- snvdbg("Resetting position to zero\n");
+ sninfo("Resetting position to zero\n");
DEBUGASSERT(lower && priv->inuse);
/* Reset the counter to zero */
@@ -1270,7 +1270,7 @@ int stm32_qeinitialize(FAR const char *devpath, int tim)
priv = stm32_tim2lower(tim);
if (!priv)
{
- sndbg("TIM%d support not configured\n", tim);
+ snerr("ERROR: TIM%d support not configured\n", tim);
return -ENXIO;
}
@@ -1278,7 +1278,7 @@ int stm32_qeinitialize(FAR const char *devpath, int tim)
if (priv->inuse)
{
- sndbg("TIM%d is in-used\n", tim);
+ snerr("ERROR: TIM%d is in-use\n", tim);
return -EBUSY;
}
@@ -1287,7 +1287,7 @@ int stm32_qeinitialize(FAR const char *devpath, int tim)
ret = qe_register(devpath, (FAR struct qe_lowerhalf_s *)priv);
if (ret < 0)
{
- sndbg("qe_register failed: %d\n", ret);
+ snerr("ERROR: qe_register failed: %d\n", ret);
return ret;
}
diff --git a/arch/arm/src/stm32/stm32_rcc.c b/arch/arm/src/stm32/stm32_rcc.c
index 8040af9e1e6b0b1ff04a19637ce2f888c31d66cc..553f76e73df675c7615f740abc47ff39d57813f5 100644
--- a/arch/arm/src/stm32/stm32_rcc.c
+++ b/arch/arm/src/stm32/stm32_rcc.c
@@ -51,6 +51,7 @@
#include "chip.h"
#include "stm32_rcc.h"
+#include "stm32_rtc.h"
#include "stm32_flash.h"
#include "stm32.h"
#include "stm32_waste.h"
@@ -66,10 +67,6 @@
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -92,21 +89,76 @@
# error "Unsupported STM32 chip"
#endif
+#if defined(CONFIG_STM32_STM32L15XX)
+# define STM32_RCC_XXX STM32_RCC_CSR
+# define RCC_XXX_YYYRST RCC_CSR_RTCRST
+#else
+# define STM32_RCC_XXX STM32_RCC_BDCR
+# define RCC_XXX_YYYRST RCC_BDCR_BDRST
+#endif
+
/****************************************************************************
* Public Functions
****************************************************************************/
-/************************************************************************************
+/****************************************************************************
+ * Name: rcc_resetbkp
+ *
+ * Description:
+ * The RTC needs to reset the Backup Domain to change RTCSEL and resetting
+ * the Backup Domain renders to disabling the LSE as consequence. In order
+ * to avoid resetting the Backup Domain when we already configured LSE we
+ * will reset the Backup Domain early (here).
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX)
+static inline void rcc_resetbkp(void)
+{
+ uint32_t regval;
+
+ /* Check if the RTC is already configured */
+
+ regval = getreg32(RTC_MAGIC_REG);
+ if (regval != RTC_MAGIC)
+ {
+ (void)stm32_pwr_enablebkp(true);
+
+ /* We might be changing RTCSEL - to ensure such changes work, we must
+ * reset the backup domain (having backed up the RTC_MAGIC token)
+ */
+
+ modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST);
+ modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0);
+
+ (void)stm32_pwr_enablebkp(false);
+ }
+}
+#else
+# define rcc_resetbkp()
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
* Name: stm32_clockconfig
*
* Description:
- * Called to establish the clock settings based on the values in board.h. This
- * function (by default) will reset most everything, enable the PLL, and enable
- * peripheral clocking for all periperipherals enabled in the NuttX configuration
- * file.
+ * Called to establish the clock settings based on the values in board.h.
+ * This function (by default) will reset most everything, enable the PLL,
+ * and enable peripheral clocking for all peripherals enabled in the NuttX
+ * configuration file.
*
- * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking will
- * be enabled by an externally provided, board-specific function called
+ * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking
+ * will be enabled by an externally provided, board-specific function called
* stm32_board_clockconfig().
*
* Input Parameters:
@@ -115,7 +167,7 @@
* Returned Value:
* None
*
- ************************************************************************************/
+ ****************************************************************************/
void stm32_clockconfig(void)
{
@@ -123,6 +175,10 @@ void stm32_clockconfig(void)
rcc_reset();
+ /* Reset backup domain if appropriate */
+
+ rcc_resetbkp();
+
#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
@@ -185,4 +241,3 @@ void stm32_clockenable(void)
#endif
}
#endif
-
diff --git a/arch/arm/src/stm32/stm32_rng.c b/arch/arm/src/stm32/stm32_rng.c
index 5726f43ef9c83dd3b0e10dd886e92ae40518e369..fce55ebf0a3aecd6ed826a86a6465f2509452af2 100644
--- a/arch/arm/src/stm32/stm32_rng.c
+++ b/arch/arm/src/stm32/stm32_rng.c
@@ -102,7 +102,7 @@ static int stm32_rnginitialize()
{
uint32_t regval;
- vdbg("Initializing RNG\n");
+ _info("Initializing RNG\n");
memset(&g_rngdev, 0, sizeof(struct rng_dev_s));
@@ -112,7 +112,7 @@ static int stm32_rnginitialize()
{
/* We could not attach the ISR to the interrupt */
- vdbg("Could not attach IRQ.\n");
+ _info("Could not attach IRQ.\n");
return -EAGAIN;
}
diff --git a/arch/arm/src/stm32/stm32_rtc.c b/arch/arm/src/stm32/stm32_rtc.c
index 0080b78cd24e869bce115ee4ddb3e590c5d7d989..3e8dc0b0d78a7307ef170d810670cd6eb13cbda6 100644
--- a/arch/arm/src/stm32/stm32_rtc.c
+++ b/arch/arm/src/stm32/stm32_rtc.c
@@ -41,22 +41,6 @@
#include "chip.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
diff --git a/arch/arm/src/stm32/stm32_rtc.h b/arch/arm/src/stm32/stm32_rtc.h
index 731cc2d3b8410b33b1bb67ccf664139535696456..119e5e54dfce5466d294e4a30e108faf69ebae1b 100644
--- a/arch/arm/src/stm32/stm32_rtc.h
+++ b/arch/arm/src/stm32/stm32_rtc.h
@@ -79,6 +79,17 @@
#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */
#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */
+#if !defined(CONFIG_RTC_MAGIC)
+# define CONFIG_RTC_MAGIC (0xfacefeee)
+#endif
+
+#if !defined(CONFIG_RTC_MAGIC_REG)
+# define CONFIG_RTC_MAGIC_REG (0)
+#endif
+
+#define RTC_MAGIC CONFIG_RTC_MAGIC
+#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_RTC_MAGIC_REG)
+
/****************************************************************************
* Public Types
****************************************************************************/
diff --git a/arch/arm/src/stm32/stm32_rtc_lowerhalf.c b/arch/arm/src/stm32/stm32_rtc_lowerhalf.c
index 20275ee92169f720a5b4e554940f9f1e0586be3c..feaa3f53951a1605cc53df3b3015bfdca6aec437 100644
--- a/arch/arm/src/stm32/stm32_rtc_lowerhalf.c
+++ b/arch/arm/src/stm32/stm32_rtc_lowerhalf.c
@@ -178,7 +178,6 @@ static void stm32_alarm_callback(FAR void *arg, unsigned int alarmid)
rtc_alarm_callback_t cb;
FAR void *priv;
- DEBUGASSERT(priv != NULL);
DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB);
lower = (struct stm32_lowerhalf_s *)arg;
@@ -190,6 +189,7 @@ static void stm32_alarm_callback(FAR void *arg, unsigned int alarmid)
cb = (rtc_alarm_callback_t)cbinfo->cb;
priv = (FAR void *)cbinfo->priv;
+ DEBUGASSERT(priv != NULL);
cbinfo->cb = NULL;
cbinfo->priv = NULL;
diff --git a/arch/arm/src/stm32/stm32_rtcc.c b/arch/arm/src/stm32/stm32_rtcc.c
index 7d403ba50415f10e1c1081030fabb645b5558372..da8f57db592cb12dfef09d4bafef0f512bd9cb41 100644
--- a/arch/arm/src/stm32/stm32_rtcc.c
+++ b/arch/arm/src/stm32/stm32_rtcc.c
@@ -76,10 +76,6 @@
# error "CONFIG_STM32_PWR must selected to use this driver"
#endif
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_RTC
-#endif
-
#ifdef CONFIG_STM32_STM32L15XX
# if defined(CONFIG_RTC_HSECLOCK)
# error "RTC with HSE clock not yet implemented for STM32L15XXX"
@@ -88,20 +84,10 @@
# endif
#endif
-#if !defined(CONFIG_RTC_MAGIC)
-# define CONFIG_RTC_MAGIC (0xfacefeee)
-#endif
-
-#if !defined(CONFIG_RTC_MAGIC_REG)
-# define CONFIG_RTC_MAGIC_REG (0)
-#endif
-
/* Constants ************************************************************************/
#define SYNCHRO_TIMEOUT (0x00020000)
#define INITMODE_TIMEOUT (0x00010000)
-#define RTC_MAGIC CONFIG_RTC_MAGIC
-#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_RTC_MAGIC_REG)
/* Proxy definitions to make the same code work for all the STM32 series ************/
@@ -123,24 +109,6 @@
# define RCC_XXX_RTCSEL_HSE RCC_BDCR_RTCSEL_HSE
#endif
-/* Debug ****************************************************************************/
-
-#ifdef CONFIG_DEBUG_RTC
-# define rtcdbg dbg
-# define rtcvdbg vdbg
-# define rtclldbg lldbg
-# define rtcllvdbg llvdbg
-#else
-# define rtcdbg(x...)
-# define rtcvdbg(x...)
-# define rtclldbg(x...)
-# define rtcllvdbg(x...)
-#endif
-
-/************************************************************************************
- * Private Types
- ************************************************************************************/
-
/************************************************************************************
* Private Data
************************************************************************************/
@@ -176,30 +144,30 @@ volatile bool g_rtc_enabled = false;
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_RTC
+#ifdef CONFIG_DEBUG_RTC_INFO
static void rtc_dumpregs(FAR const char *msg)
{
- rtclldbg("%s:\n", msg);
- rtclldbg(" TR: %08x\n", getreg32(STM32_RTC_TR));
- rtclldbg(" DR: %08x\n", getreg32(STM32_RTC_DR));
- rtclldbg(" CR: %08x\n", getreg32(STM32_RTC_CR));
- rtclldbg(" ISR: %08x\n", getreg32(STM32_RTC_ISR));
- rtclldbg(" PRER: %08x\n", getreg32(STM32_RTC_PRER));
- rtclldbg(" WUTR: %08x\n", getreg32(STM32_RTC_WUTR));
+ rtcinfo("%s:\n", msg);
+ rtcinfo(" TR: %08x\n", getreg32(STM32_RTC_TR));
+ rtcinfo(" DR: %08x\n", getreg32(STM32_RTC_DR));
+ rtcinfo(" CR: %08x\n", getreg32(STM32_RTC_CR));
+ rtcinfo(" ISR: %08x\n", getreg32(STM32_RTC_ISR));
+ rtcinfo(" PRER: %08x\n", getreg32(STM32_RTC_PRER));
+ rtcinfo(" WUTR: %08x\n", getreg32(STM32_RTC_WUTR));
#ifndef CONFIG_STM32_STM32F30XX
- rtclldbg(" CALIBR: %08x\n", getreg32(STM32_RTC_CALIBR));
+ rtcinfo(" CALIBR: %08x\n", getreg32(STM32_RTC_CALIBR));
#endif
- rtclldbg(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR));
- rtclldbg(" ALRMBR: %08x\n", getreg32(STM32_RTC_ALRMBR));
- rtclldbg(" SHIFTR: %08x\n", getreg32(STM32_RTC_SHIFTR));
- rtclldbg(" TSTR: %08x\n", getreg32(STM32_RTC_TSTR));
- rtclldbg(" TSDR: %08x\n", getreg32(STM32_RTC_TSDR));
- rtclldbg(" TSSSR: %08x\n", getreg32(STM32_RTC_TSSSR));
- rtclldbg(" CALR: %08x\n", getreg32(STM32_RTC_CALR));
- rtclldbg(" TAFCR: %08x\n", getreg32(STM32_RTC_TAFCR));
- rtclldbg("ALRMASSR: %08x\n", getreg32(STM32_RTC_ALRMASSR));
- rtclldbg("ALRMBSSR: %08x\n", getreg32(STM32_RTC_ALRMBSSR));
- rtclldbg("MAGICREG: %08x\n", getreg32(RTC_MAGIC_REG));
+ rtcinfo(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR));
+ rtcinfo(" ALRMBR: %08x\n", getreg32(STM32_RTC_ALRMBR));
+ rtcinfo(" SHIFTR: %08x\n", getreg32(STM32_RTC_SHIFTR));
+ rtcinfo(" TSTR: %08x\n", getreg32(STM32_RTC_TSTR));
+ rtcinfo(" TSDR: %08x\n", getreg32(STM32_RTC_TSDR));
+ rtcinfo(" TSSSR: %08x\n", getreg32(STM32_RTC_TSSSR));
+ rtcinfo(" CALR: %08x\n", getreg32(STM32_RTC_CALR));
+ rtcinfo(" TAFCR: %08x\n", getreg32(STM32_RTC_TAFCR));
+ rtcinfo("ALRMASSR: %08x\n", getreg32(STM32_RTC_ALRMASSR));
+ rtcinfo("ALRMBSSR: %08x\n", getreg32(STM32_RTC_ALRMBSSR));
+ rtcinfo("MAGICREG: %08x\n", getreg32(RTC_MAGIC_REG));
}
#else
# define rtc_dumpregs(msg)
@@ -219,16 +187,16 @@ static void rtc_dumpregs(FAR const char *msg)
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_RTC
+#ifdef CONFIG_DEBUG_RTC_INFO
static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg)
{
- rtclldbg("%s:\n", msg);
- rtclldbg(" tm_sec: %08x\n", tp->tm_sec);
- rtclldbg(" tm_min: %08x\n", tp->tm_min);
- rtclldbg(" tm_hour: %08x\n", tp->tm_hour);
- rtclldbg(" tm_mday: %08x\n", tp->tm_mday);
- rtclldbg(" tm_mon: %08x\n", tp->tm_mon);
- rtclldbg(" tm_year: %08x\n", tp->tm_year);
+ rtcinfo("%s:\n", msg);
+ rtcinfo(" tm_sec: %08x\n", tp->tm_sec);
+ rtcinfo(" tm_min: %08x\n", tp->tm_min);
+ rtcinfo(" tm_hour: %08x\n", tp->tm_hour);
+ rtcinfo(" tm_mday: %08x\n", tp->tm_mday);
+ rtcinfo(" tm_mon: %08x\n", tp->tm_mon);
+ rtcinfo(" tm_year: %08x\n", tp->tm_year);
}
#else
# define rtc_dumptime(tp, msg)
@@ -634,13 +602,6 @@ int up_rtc_initialize(void)
if (regval != RTC_MAGIC)
{
- /* We might be changing RTCSEL - to ensure such changes work, we must reset the
- * backup domain (having backed up the RTC_MAGIC token)
- */
-
- modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST);
- modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0);
-
/* Some boards do not have the external 32khz oscillator installed, for those
* boards we must fallback to the crummy internal RC clock or the external high
* rate clock
@@ -733,13 +694,13 @@ int up_rtc_initialize(void)
{
case OK:
{
- rtclldbg("rtc_syncwait() okay\n");
+ rtcinfo("rtc_syncwait() okay\n");
break;
}
default:
{
- rtclldbg("rtc_syncwait() failed (%d)\n", ret);
+ rtcerr("ERROR: rtc_syncwait() failed (%d)\n", ret);
break;
}
}
@@ -753,7 +714,7 @@ int up_rtc_initialize(void)
if (regval != RTC_MAGIC)
{
- rtclldbg("Do setup\n");
+ rtcinfo("Do setup\n");
/* Perform the one-time setup of the LSE clocking to the RTC */
@@ -771,7 +732,7 @@ int up_rtc_initialize(void)
}
else
{
- rtclldbg("Do resume\n");
+ rtcinfo("Do resume\n");
/* RTC already set-up, just resume normal operation */
@@ -787,8 +748,8 @@ int up_rtc_initialize(void)
if (ret != OK && nretry > 0)
{
- rtclldbg("setup/resume ran %d times and failed with %d\n",
- nretry, ret);
+ rtcinfo("setup/resume ran %d times and failed with %d\n",
+ nretry, ret);
return -ETIMEDOUT;
}
diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/stm32/stm32_sdio.c
index b9bea99351fb203f29aae8544a454fcc3434a7fa..6cd372b7fd2be7277aa72be1ce19645873160598 100644
--- a/arch/arm/src/stm32/stm32_sdio.c
+++ b/arch/arm/src/stm32/stm32_sdio.c
@@ -95,7 +95,7 @@
* CONFIG_SDM_DMAPRIO - SDIO DMA priority. This can be selecte if
* CONFIG_SDIO_DMA is enabled.
* CONFIG_SDIO_XFRDEBUG - Enables some very low-level debug output
- * This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_VERBOSE
+ * This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO
*/
#if defined(CONFIG_SDIO_DMA) && !defined(CONFIG_STM32_DMA2)
@@ -139,7 +139,7 @@
# undef CONFIG_SDIO_DMAPRIO
#endif
-#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG)
+#ifndef CONFIG_DEBUG_MEMCARD_INFO
# undef CONFIG_SDIO_XFRDEBUG
#endif
@@ -345,7 +345,7 @@ struct stm32_sdioregs_s
struct stm32_sampleregs_s
{
struct stm32_sdioregs_s sdio;
-#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_SDIO_DMA)
+#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA)
struct stm32_dmaregs_s dma;
#endif
};
@@ -596,7 +596,7 @@ static inline void stm32_setclkcr(uint32_t clkcr)
regval |= clkcr;
putreg32(regval, STM32_SDIO_CLKCR);
- fvdbg("CLKCR: %08x PWR: %08x\n",
+ mcinfo("CLKCR: %08x PWR: %08x\n",
getreg32(STM32_SDIO_CLKCR), getreg32(STM32_SDIO_POWER));
}
@@ -789,12 +789,14 @@ static void stm32_sdiosample(struct stm32_sdioregs_s *regs)
static void stm32_sample(struct stm32_dev_s *priv, int index)
{
struct stm32_sampleregs_s *regs = &g_sampleregs[index];
-#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_SDIO_DMA)
+
+#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA)
if (priv->dmamode)
{
stm32_dmasample(priv->dma, ®s->dma);
}
#endif
+
stm32_sdiosample(®s->sdio);
}
#endif
@@ -810,16 +812,16 @@ static void stm32_sample(struct stm32_dev_s *priv, int index)
#ifdef CONFIG_SDIO_XFRDEBUG
static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg)
{
- fdbg("SDIO Registers: %s\n", msg);
- fdbg(" POWER[%08x]: %08x\n", STM32_SDIO_POWER, regs->power);
- fdbg(" CLKCR[%08x]: %08x\n", STM32_SDIO_CLKCR, regs->clkcr);
- fdbg(" DCTRL[%08x]: %08x\n", STM32_SDIO_DCTRL, regs->dctrl);
- fdbg(" DTIMER[%08x]: %08x\n", STM32_SDIO_DTIMER, regs->dtimer);
- fdbg(" DLEN[%08x]: %08x\n", STM32_SDIO_DLEN, regs->dlen);
- fdbg(" DCOUNT[%08x]: %08x\n", STM32_SDIO_DCOUNT, regs->dcount);
- fdbg(" STA[%08x]: %08x\n", STM32_SDIO_STA, regs->sta);
- fdbg(" MASK[%08x]: %08x\n", STM32_SDIO_MASK, regs->mask);
- fdbg("FIFOCNT[%08x]: %08x\n", STM32_SDIO_FIFOCNT, regs->fifocnt);
+ mcinfo("SDIO Registers: %s\n", msg);
+ mcinfo(" POWER[%08x]: %08x\n", STM32_SDIO_POWER, regs->power);
+ mcinfo(" CLKCR[%08x]: %08x\n", STM32_SDIO_CLKCR, regs->clkcr);
+ mcinfo(" DCTRL[%08x]: %08x\n", STM32_SDIO_DCTRL, regs->dctrl);
+ mcinfo(" DTIMER[%08x]: %08x\n", STM32_SDIO_DTIMER, regs->dtimer);
+ mcinfo(" DLEN[%08x]: %08x\n", STM32_SDIO_DLEN, regs->dlen);
+ mcinfo(" DCOUNT[%08x]: %08x\n", STM32_SDIO_DCOUNT, regs->dcount);
+ mcinfo(" STA[%08x]: %08x\n", STM32_SDIO_STA, regs->sta);
+ mcinfo(" MASK[%08x]: %08x\n", STM32_SDIO_MASK, regs->mask);
+ mcinfo("FIFOCNT[%08x]: %08x\n", STM32_SDIO_FIFOCNT, regs->fifocnt);
}
#endif
@@ -835,12 +837,13 @@ static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg)
static void stm32_dumpsample(struct stm32_dev_s *priv,
struct stm32_sampleregs_s *regs, const char *msg)
{
-#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_SDIO_DMA)
+#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA)
if (priv->dmamode)
{
stm32_dmadump(priv->dma, ®s->dma, msg);
}
#endif
+
stm32_sdiodump(®s->sdio, msg);
}
#endif
@@ -857,15 +860,18 @@ static void stm32_dumpsample(struct stm32_dev_s *priv,
static void stm32_dumpsamples(struct stm32_dev_s *priv)
{
stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup");
-#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_SDIO_DMA)
+
+#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA)
if (priv->dmamode)
{
stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_ENABLE], "Before DMA enable");
}
#endif
+
stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_AFTER_SETUP], "After setup");
stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], "End of transfer");
-#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_SDIO_DMA)
+
+#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA)
if (priv->dmamode)
{
stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_DMA_CALLBACK], "DMA Callback");
@@ -901,7 +907,7 @@ static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg)
if ((status & DMA_STATUS_ERROR) != 0)
{
- flldbg("DMA error %02x, remaining: %d\n", status, priv->remaining);
+ mcerr("ERROR: DMA error %02x, remaining: %d\n", status, priv->remaining);
result = SDIOWAIT_ERROR;
}
else
@@ -1166,7 +1172,7 @@ static void stm32_eventtimeout(int argc, uint32_t arg)
/* Yes.. wake up any waiting threads */
stm32_endwait(priv, SDIOWAIT_TIMEOUT);
- flldbg("Timeout: remaining: %d\n", priv->remaining);
+ mcerr("ERROR: Timeout, remaining: %d\n", priv->remaining);
}
}
@@ -1406,7 +1412,7 @@ static int stm32_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
- flldbg("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
+ mcerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
@@ -1416,7 +1422,7 @@ static int stm32_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
- flldbg("ERROR: Data timeout, remaining: %d\n", priv->remaining);
+ mcerr("ERROR: Data timeout, remaining: %d\n", priv->remaining);
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT);
}
@@ -1426,7 +1432,7 @@ static int stm32_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
- flldbg("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining);
+ mcerr("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining);
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
@@ -1436,7 +1442,7 @@ static int stm32_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
- flldbg("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining);
+ mcerr("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining);
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
@@ -1446,7 +1452,7 @@ static int stm32_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
- flldbg("ERROR: Start bit, remaining: %d\n", priv->remaining);
+ mcerr("ERROR: Start bit, remaining: %d\n", priv->remaining);
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
}
@@ -1582,8 +1588,8 @@ static void stm32_reset(FAR struct sdio_dev_s *dev)
stm32_setpwrctrl(SDIO_POWER_PWRCTRL_ON);
leave_critical_section(flags);
- fvdbg("CLCKR: %08x POWER: %08x\n",
- getreg32(STM32_SDIO_CLKCR), getreg32(STM32_SDIO_POWER));
+ mcinfo("CLCKR: %08x POWER: %08x\n",
+ getreg32(STM32_SDIO_CLKCR), getreg32(STM32_SDIO_POWER));
}
/****************************************************************************
@@ -1795,7 +1801,7 @@ static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg)
cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT;
regval |= cmdidx | SDIO_CMD_CPSMEN;
- fvdbg("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
+ mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
/* Write the SDIO CMD */
@@ -2025,7 +2031,7 @@ static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
{
if (--timeout <= 0)
{
- fdbg("ERROR: Timeout cmd: %08x events: %08x STA: %08x\n",
+ mcerr("ERROR: Timeout cmd: %08x events: %08x STA: %08x\n",
cmd, events, getreg32(STM32_SDIO_STA));
return -ETIMEDOUT;
@@ -2060,7 +2066,7 @@ static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort)
{
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_MEMCARD_INFO
uint32_t respcmd;
#endif
uint32_t regval;
@@ -2089,10 +2095,10 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
*/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_MEMCARD_INFO
if (!rshort)
{
- fdbg("ERROR: rshort=NULL\n");
+ mcerr("ERROR: rshort=NULL\n");
ret = -EINVAL;
}
@@ -2102,7 +2108,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1B_RESPONSE &&
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE)
{
- fdbg("ERROR: Wrong response CMD=%08x\n", cmd);
+ mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
ret = -EINVAL;
}
else
@@ -2113,15 +2119,15 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
regval = getreg32(STM32_SDIO_STA);
if ((regval & SDIO_STA_CTIMEOUT) != 0)
{
- fdbg("ERROR: Command timeout: %08x\n", regval);
+ mcerr("ERROR: Command timeout: %08x\n", regval);
ret = -ETIMEDOUT;
}
else if ((regval & SDIO_STA_CCRCFAIL) != 0)
{
- fdbg("ERROR: CRC failure: %08x\n", regval);
+ mcerr("ERROR: CRC failure: %08x\n", regval);
ret = -EIO;
}
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_MEMCARD_INFO
else
{
/* Check response received is of desired command */
@@ -2129,7 +2135,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
respcmd = getreg32(STM32_SDIO_RESPCMD);
if ((uint8_t)(respcmd & SDIO_RESPCMD_MASK) != (cmd & MMCSD_CMDIDX_MASK))
{
- fdbg("ERROR: RESCMD=%02x CMD=%08x\n", respcmd, cmd);
+ mcerr("ERROR: RESCMD=%02x CMD=%08x\n", respcmd, cmd);
ret = -EINVAL;
}
}
@@ -2157,12 +2163,12 @@ static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo
* 0 1 End bit
*/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_MEMCARD_INFO
/* Check that R1 is the correct response to this command */
if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE)
{
- fdbg("ERROR: Wrong response CMD=%08x\n", cmd);
+ mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
ret = -EINVAL;
}
else
@@ -2173,12 +2179,12 @@ static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo
regval = getreg32(STM32_SDIO_STA);
if (regval & SDIO_STA_CTIMEOUT)
{
- fdbg("ERROR: Timeout STA: %08x\n", regval);
+ mcerr("ERROR: Timeout STA: %08x\n", regval);
ret = -ETIMEDOUT;
}
else if (regval & SDIO_STA_CCRCFAIL)
{
- fdbg("ERROR: CRC fail STA: %08x\n", regval);
+ mcerr("ERROR: CRC fail STA: %08x\n", regval);
ret = -EIO;
}
}
@@ -2212,11 +2218,11 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r
/* Check that this is the correct response to this command */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_MEMCARD_INFO
if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE &&
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE)
{
- fdbg("ERROR: Wrong response CMD=%08x\n", cmd);
+ mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
ret = -EINVAL;
}
else
@@ -2229,7 +2235,7 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r
regval = getreg32(STM32_SDIO_STA);
if (regval & SDIO_STA_CTIMEOUT)
{
- fdbg("ERROR: Timeout STA: %08x\n", regval);
+ mcerr("ERROR: Timeout STA: %08x\n", regval);
ret = -ETIMEDOUT;
}
}
@@ -2384,7 +2390,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
1, (uint32_t)priv);
if (ret != OK)
{
- fdbg("ERROR: wd_start failed: %d\n", ret);
+ mcerr("ERROR: wd_start failed: %d\n", ret);
}
}
@@ -2471,7 +2477,7 @@ static void stm32_callbackenable(FAR struct sdio_dev_s *dev,
{
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
- fvdbg("eventset: %02x\n", eventset);
+ mcinfo("eventset: %02x\n", eventset);
DEBUGASSERT(priv != NULL);
priv->cbevents = eventset;
@@ -2507,7 +2513,7 @@ static int stm32_registercallback(FAR struct sdio_dev_s *dev,
/* Disable callbacks and register this callback and is argument */
- fvdbg("Register %p(%p)\n", callback, arg);
+ mcinfo("Register %p(%p)\n", callback, arg);
DEBUGASSERT(priv != NULL);
priv->cbevents = 0;
@@ -2743,8 +2749,8 @@ static void stm32_callback(void *arg)
/* Is a callback registered? */
DEBUGASSERT(priv != NULL);
- fvdbg("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
- priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
+ mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
+ priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
if (priv->callback)
{
@@ -2788,14 +2794,14 @@ static void stm32_callback(void *arg)
{
/* Yes.. queue it */
- fvdbg("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
+ mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
(void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
}
else
{
/* No.. then just call the callback here */
- fvdbg("Callback to %p(%p)\n", priv->callback, priv->cbarg);
+ mcinfo("Callback to %p(%p)\n", priv->callback, priv->cbarg);
priv->callback(priv->cbarg);
}
}
@@ -2925,7 +2931,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
leave_critical_section(flags);
- fvdbg("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
+ mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
/* Perform any requested callback if the status has changed */
@@ -2967,7 +2973,8 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
{
priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED;
}
- fvdbg("cdstatus: %02x\n", priv->cdstatus);
+
+ mcinfo("cdstatus: %02x\n", priv->cdstatus);
leave_critical_section(flags);
}
#endif /* CONFIG_STM32_SDIO */
diff --git a/arch/arm/src/stm32/stm32_spi.c b/arch/arm/src/stm32/stm32_spi.c
index eed9ea9845b58d849bee1db75454ebed984b1e52..807a13127f2243fe10cab221831db3c11bda55a5 100644
--- a/arch/arm/src/stm32/stm32_spi.c
+++ b/arch/arm/src/stm32/stm32_spi.c
@@ -155,27 +155,6 @@
# error "Unknown STM32 DMA"
#endif
-
-/* Debug ****************************************************************************/
-/* Check if (non-standard) SPI debug is enabled */
-
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# undef CONFIG_DEBUG_SPI
-#endif
-
-#ifdef CONFIG_DEBUG_SPI
-# define spidbg lldbg
-# ifdef CONFIG_DEBUG_VERBOSE
-# define spivdbg lldbg
-# else
-# define spivdbg(x...)
-# endif
-#else
-# define spidbg(x...)
-# define spivdbg(x...)
-#endif
-
/************************************************************************************
* Private Types
************************************************************************************/
@@ -1052,7 +1031,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
* faster.
*/
- spivdbg("Frequency %d->%d\n", frequency, actual);
+ spiinfo("Frequency %d->%d\n", frequency, actual);
priv->frequency = frequency;
priv->actual = actual;
@@ -1082,7 +1061,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
uint16_t setbits;
uint16_t clrbits;
- spivdbg("mode=%d\n", mode);
+ spiinfo("mode=%d\n", mode);
/* Has the mode changed? */
@@ -1147,7 +1126,7 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
uint16_t setbits;
uint16_t clrbits;
- spivdbg("nbits=%d\n", nbits);
+ spiinfo("nbits=%d\n", nbits);
/* Has the number of bits changed? */
@@ -1222,7 +1201,7 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
regval = spi_getreg(priv, STM32_SPI_SR_OFFSET);
- spivdbg("Sent: %04x Return: %04x Status: %02x\n", wd, ret, regval);
+ spiinfo("Sent: %04x Return: %04x Status: %02x\n", wd, ret, regval);
UNUSED(regval);
return ret;
@@ -1260,7 +1239,7 @@ static void spi_exchange_nodma(FAR struct spi_dev_s *dev, FAR const void *txbuff
FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev;
DEBUGASSERT(priv && priv->spibase);
- spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
+ spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
/* 8- or 16-bit mode? */
@@ -1373,7 +1352,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
static uint16_t rxdummy = 0xffff;
static const uint16_t txdummy = 0xffff;
- spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
+ spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
DEBUGASSERT(priv && priv->spibase);
/* Setup DMAs */
@@ -1416,7 +1395,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
#ifndef CONFIG_SPI_EXCHANGE
static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer, size_t nwords)
{
- spivdbg("txbuffer=%p nwords=%d\n", txbuffer, nwords);
+ spiinfo("txbuffer=%p nwords=%d\n", txbuffer, nwords);
return spi_exchange(dev, txbuffer, NULL, nwords);
}
#endif
@@ -1443,7 +1422,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer, si
#ifndef CONFIG_SPI_EXCHANGE
static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, size_t nwords)
{
- spivdbg("rxbuffer=%p nwords=%d\n", rxbuffer, nwords);
+ spiinfo("rxbuffer=%p nwords=%d\n", rxbuffer, nwords);
return spi_exchange(dev, NULL, rxbuffer, nwords);
}
#endif
@@ -1692,7 +1671,7 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus)
else
#endif
{
- spidbg("ERROR: Unsupbused SPI bus: %d\n", bus);
+ spierr("ERROR: Unsupbused SPI bus: %d\n", bus);
return NULL;
}
diff --git a/arch/arm/src/stm32/stm32_start.c b/arch/arm/src/stm32/stm32_start.c
index 8e58e862a9ed94ad48523be4c9cf8cbfa5ca0b96..480d5f58b46811e4bbd7320e0854c75bb7894d88 100644
--- a/arch/arm/src/stm32/stm32_start.c
+++ b/arch/arm/src/stm32/stm32_start.c
@@ -81,7 +81,7 @@ static void go_os_start(void *pv, unsigned int nbytes)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) up_lowputc(c)
#else
# define showprogress(c)
diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c
index 14359625f888805236ba74b06c6beb21850c226c..62e2783e3a8ff1281fad5e58e35f2259a7ff0128 100644
--- a/arch/arm/src/stm32/stm32_tim.c
+++ b/arch/arm/src/stm32/stm32_tim.c
@@ -144,57 +144,137 @@
defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE)
# undef CONFIG_STM32_TIM14
#endif
+#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \
+ defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE)
+# undef CONFIG_STM32_TIM15
+#endif
+#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \
+ defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE)
+# undef CONFIG_STM32_TIM16
+#endif
+#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \
+ defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE)
+# undef CONFIG_STM32_TIM17
+#endif
-#if defined(CONFIG_STM32_TIM1)
+#if defined(CONFIG_STM32_TIM1)
# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\
defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)
# define HAVE_TIM1_GPIOCONFIG 1
#endif
#endif
-#if defined(CONFIG_STM32_TIM2)
+#if defined(CONFIG_STM32_TIM2)
# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\
defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT)
# define HAVE_TIM2_GPIOCONFIG 1
#endif
#endif
-#if defined(CONFIG_STM32_TIM3)
+#if defined(CONFIG_STM32_TIM3)
# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\
defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT)
# define HAVE_TIM3_GPIOCONFIG 1
#endif
#endif
-#if defined(CONFIG_STM32_TIM4)
+#if defined(CONFIG_STM32_TIM4)
# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\
defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT)
# define HAVE_TIM4_GPIOCONFIG 1
#endif
#endif
-#if defined(CONFIG_STM32_TIM5)
+#if defined(CONFIG_STM32_TIM5)
# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\
defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT)
# define HAVE_TIM5_GPIOCONFIG 1
#endif
#endif
-#if defined(CONFIG_STM32_TIM8)
+#if defined(CONFIG_STM32_TIM8)
# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\
defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)
# define HAVE_TIM8_GPIOCONFIG 1
#endif
#endif
+#if defined(CONFIG_STM32_TIM9)
+# if defined(GPIO_TIM9_CH1OUT) ||defined(GPIO_TIM9_CH2OUT)||\
+ defined(GPIO_TIM9_CH3OUT) ||defined(GPIO_TIM9_CH4OUT)
+# define HAVE_TIM9_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32_TIM10)
+# if defined(GPIO_TIM10_CH1OUT) ||defined(GPIO_TIM10_CH2OUT)||\
+ defined(GPIO_TIM10_CH3OUT) ||defined(GPIO_TIM10_CH4OUT)
+# define HAVE_TIM10_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32_TIM11)
+# if defined(GPIO_TIM11_CH1OUT) ||defined(GPIO_TIM11_CH2OUT)||\
+ defined(GPIO_TIM11_CH3OUT) ||defined(GPIO_TIM11_CH4OUT)
+# define HAVE_TIM11_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32_TIM12)
+# if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT)||\
+ defined(GPIO_TIM12_CH3OUT) ||defined(GPIO_TIM12_CH4OUT)
+# define HAVE_TIM12_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32_TIM13)
+# if defined(GPIO_TIM13_CH1OUT) ||defined(GPIO_TIM13_CH2OUT)||\
+ defined(GPIO_TIM13_CH3OUT) ||defined(GPIO_TIM13_CH4OUT)
+# define HAVE_TIM13_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32_TIM14)
+# if defined(GPIO_TIM14_CH1OUT) ||defined(GPIO_TIM14_CH2OUT)||\
+ defined(GPIO_TIM14_CH3OUT) ||defined(GPIO_TIM14_CH4OUT)
+# define HAVE_TIM14_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32_TIM15)
+# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\
+ defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT)
+# define HAVE_TIM15_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32_TIM16)
+# if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\
+ defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT)
+# define HAVE_TIM16_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32_TIM17)
+# if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\
+ defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT)
+# define HAVE_TIM17_GPIOCONFIG 1
+#endif
+#endif
/* This module then only compiles if there are enabled timers that are not intended for
* some other purpose.
*/
-#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM3) || \
- defined(CONFIG_STM32_TIM4) || defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
- defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8)
+#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \
+ defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \
+ defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
+ defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \
+ defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \
+ defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \
+ defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14) || \
+ defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \
+ defined(CONFIG_STM32_TIM17)
/************************************************************************************
* Private Types
@@ -312,9 +392,10 @@ static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode)
static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
{
+ uint32_t freqin;
int prescaler;
- ASSERT(dev);
+ DEBUGASSERT(dev != NULL);
/* Disable Timer? */
@@ -324,20 +405,112 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
return 0;
}
-#if STM32_NATIM > 0
- if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE ||
- ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE)
+ /* Get the input clock frequency for this timer. These vary with
+ * different timer clock sources, MCU-specific timer configuration, and
+ * board-specific clock configuration. The correct input clock frequency
+ * must be defined in the board.h header file.
+ */
+
+ switch (((struct stm32_tim_priv_s *)dev)->base)
{
- prescaler = STM32_TIM18_FREQUENCY / freq;
- }
- else
+#ifdef CONFIG_STM32_TIM1
+ case STM32_TIM1_BASE:
+ freqin = BOARD_TIM1_FREQUENCY;
+ break;
#endif
- {
- prescaler = STM32_TIM27_FREQUENCY / freq;
+#ifdef CONFIG_STM32_TIM2
+ case STM32_TIM2_BASE:
+ freqin = BOARD_TIM2_FREQUENCY;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM3
+ case STM32_TIM3_BASE:
+ freqin = BOARD_TIM3_FREQUENCY;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM4
+ case STM32_TIM4_BASE:
+ freqin = BOARD_TIM4_FREQUENCY;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM5
+ case STM32_TIM5_BASE:
+ freqin = BOARD_TIM5_FREQUENCY;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM6
+ case STM32_TIM6_BASE:
+ freqin = BOARD_TIM6_FREQUENCY;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM7
+ case STM32_TIM7_BASE:
+ freqin = BOARD_TIM7_FREQUENCY;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM8
+ case STM32_TIM8_BASE:
+ freqin = BOARD_TIM8_FREQUENCY;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM9
+ case STM32_TIM9_BASE:
+ freqin = BOARD_TIM9_FREQUENCY;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM10
+ case STM32_TIM10_BASE:
+ freqin = BOARD_TIM10_FREQUENCY;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM11
+ case STM32_TIM11_BASE:
+ freqin = BOARD_TIM11_FREQUENCY;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM12
+ case STM32_TIM12_BASE:
+ freqin = BOARD_TIM12_FREQUENCY;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM13
+ case STM32_TIM13_BASE:
+ freqin = BOARD_TIM13_FREQUENCY;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM14
+ case STM32_TIM14_BASE:
+ freqin = BOARD_TIM14_FREQUENCY;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM15
+ case STM32_TIM15_BASE:
+ freqin = BOARD_TIM15_FREQUENCY;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM16
+ case STM32_TIM16_BASE:
+ freqin = BOARD_TIM16_FREQUENCY;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM17
+ case STM32_TIM17_BASE:
+ freqin = BOARD_TIM17_FREQUENCY;
+ break;
+#endif
+
+ default:
+ return -EINVAL;
}
- /* We need to decrement value for '1', but only, if we are allowed to
- * not to cause underflow. Check for overflow.
+ /* Select a pre-scaler value for this timer using the input clock
+ * frequency.
+ */
+
+ prescaler = freqin / freq;
+
+ /* We need to decrement value for '1', but only, if that will not to
+ * cause underflow.
*/
if (prescaler > 0)
@@ -345,6 +518,8 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
prescaler--;
}
+ /* Check for overflow as well. */
+
if (prescaler > 0xffff)
{
prescaler = 0xffff;
@@ -359,7 +534,7 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev,
uint32_t period)
{
- ASSERT(dev);
+ DEBUGASSERT(dev != NULL);
stm32_putreg32(dev, STM32_BTIM_ARR_OFFSET, period);
}
@@ -369,11 +544,16 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
{
int vectorno;
- ASSERT(dev);
- ASSERT(source == 0);
+ DEBUGASSERT(dev != NULL);
+ DEBUGASSERT(source == 0);
switch (((struct stm32_tim_priv_s *)dev)->base)
{
+#ifdef CONFIG_STM32_TIM1
+ case STM32_TIM1_BASE:
+ vectorno = STM32_IRQ_TIM1UP;
+ break;
+#endif
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
vectorno = STM32_IRQ_TIM2;
@@ -394,36 +574,69 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
vectorno = STM32_IRQ_TIM5;
break;
#endif
-#if STM32_NBTIM > 0
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
vectorno = STM32_IRQ_TIM6;
break;
#endif
-#endif
-#if STM32_NBTIM > 1
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
vectorno = STM32_IRQ_TIM7;
break;
#endif
-#endif
-#if STM32_NATIM > 0
- /* TODO: add support for multiple sources and callbacks */
-
-#ifdef CONFIG_STM32_TIM1
- case STM32_TIM1_BASE:
- vectorno = STM32_IRQ_TIM1UP;
- break;
-#endif
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
vectorno = STM32_IRQ_TIM8UP;
break;
#endif
+#ifdef CONFIG_STM32_TIM9
+ case STM32_TIM9_BASE:
+ vectorno = STM32_IRQ_TIM9;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM10
+ case STM32_TIM10_BASE:
+ vectorno = STM32_IRQ_TIM10;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM11
+ case STM32_TIM11_BASE:
+ vectorno = STM32_IRQ_TIM11;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM12
+ case STM32_TIM12_BASE:
+ vectorno = STM32_IRQ_TIM12;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM13
+ case STM32_TIM13_BASE:
+ vectorno = STM32_IRQ_TIM13;
+ break;
#endif
+#ifdef CONFIG_STM32_TIM14
+ case STM32_TIM14_BASE:
+ vectorno = STM32_IRQ_TIM14;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM15
+ case STM32_TIM15_BASE:
+ vectorno = STM32_IRQ_TIM15;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM16
+ case STM32_TIM16_BASE:
+ vectorno = STM32_IRQ_TIM16;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM17
+ case STM32_TIM17_BASE:
+ vectorno = STM32_IRQ_TIM17;
+ break;
+#endif
+
default:
- return ERROR;
+ return -EINVAL;
}
/* Disable interrupt when callback is removed */
@@ -451,13 +664,13 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source)
{
- ASSERT(dev);
+ DEBUGASSERT(dev != NULL);
stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, 0, ATIM_DIER_UIE);
}
static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source)
{
- ASSERT(dev);
+ DEBUGASSERT(dev != NULL);
stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0);
}
@@ -474,7 +687,7 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m
{
uint16_t val = ATIM_CR1_CEN | ATIM_CR1_ARPE;
- ASSERT(dev);
+ DEBUGASSERT(dev != NULL);
/* This function is not supported on basic timers. To enable or
* disable it, simply set its clock to valid frequency or zero.
@@ -489,7 +702,7 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m
#if STM32_NBTIM > 0
)
{
- return ERROR;
+ return -EINVAL;
}
#endif
@@ -517,7 +730,7 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m
break;
default:
- return ERROR;
+ return -EINVAL;
}
stm32_tim_reload_counter(dev);
@@ -545,13 +758,13 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET);
uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET;
- ASSERT(dev);
+ DEBUGASSERT(dev != NULL);
/* Further we use range as 0..3; if channel=0 it will also overflow here */
if (--channel > 4)
{
- return ERROR;
+ return -EINVAL;
}
/* Assume that channel is disabled and polarity is active high */
@@ -571,7 +784,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
#if STM32_NBTIM > 0
)
{
- return ERROR;
+ return -EINVAL;
}
#endif
@@ -588,7 +801,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
break;
default:
- return ERROR;
+ return -EINVAL;
}
/* Set polarity */
@@ -621,6 +834,31 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
switch (((struct stm32_tim_priv_s *)dev)->base)
{
+#ifdef CONFIG_STM32_TIM1
+ case STM32_TIM1_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM1_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break;
+#endif
+#if defined(GPIO_TIM1_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break;
+#endif
+#if defined(GPIO_TIM1_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break;
+#endif
+#if defined(GPIO_TIM1_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break;
+#endif
+ default:
+ return -EINVAL;
+ }
+ break;
+#endif
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
switch (channel)
@@ -646,7 +884,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
break;
#endif
default:
- return ERROR;
+ return -EINVAL;
}
break;
#endif
@@ -675,7 +913,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
break;
#endif
default:
- return ERROR;
+ return -EINVAL;
}
break;
#endif
@@ -704,7 +942,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
break;
#endif
default:
- return ERROR;
+ return -EINVAL;
}
break;
#endif
@@ -733,65 +971,298 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
break;
#endif
default:
- return ERROR;
+ return -EINVAL;
}
break;
#endif
-
-#if STM32_NATIM > 0
-#ifdef CONFIG_STM32_TIM1
- case STM32_TIM1_BASE:
+#ifdef CONFIG_STM32_TIM8
+ case STM32_TIM8_BASE:
switch (channel)
{
-#if defined(GPIO_TIM1_CH1OUT)
+#if defined(GPIO_TIM8_CH1OUT)
case 0:
- stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break;
+ stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break;
#endif
-#if defined(GPIO_TIM1_CH2OUT)
+#if defined(GPIO_TIM8_CH2OUT)
case 1:
- stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break;
+ stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break;
#endif
-#if defined(GPIO_TIM1_CH3OUT)
+#if defined(GPIO_TIM8_CH3OUT)
case 2:
- stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break;
+ stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break;
#endif
-#if defined(GPIO_TIM1_CH4OUT)
+#if defined(GPIO_TIM8_CH4OUT)
case 3:
- stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break;
+ stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break;
#endif
default:
- return ERROR;
+ return -EINVAL;
}
break;
#endif
-#ifdef CONFIG_STM32_TIM8
- case STM32_TIM8_BASE:
+#ifdef CONFIG_STM32_TIM9
+ case STM32_TIM9_BASE:
switch (channel)
{
-#if defined(GPIO_TIM8_CH1OUT)
+#if defined(GPIO_TIM9_CH1OUT)
case 0:
- stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break;
+ stm32_tim_gpioconfig(GPIO_TIM9_CH1OUT, mode);
+ break;
#endif
-#if defined(GPIO_TIM8_CH2OUT)
+#if defined(GPIO_TIM9_CH2OUT)
case 1:
- stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break;
+ stm32_tim_gpioconfig(GPIO_TIM9_CH2OUT, mode);
+ break;
#endif
-#if defined(GPIO_TIM8_CH3OUT)
+#if defined(GPIO_TIM9_CH3OUT)
case 2:
- stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break;
+ stm32_tim_gpioconfig(GPIO_TIM9_CH3OUT, mode);
+ break;
#endif
-#if defined(GPIO_TIM8_CH4OUT)
+#if defined(GPIO_TIM9_CH4OUT)
case 3:
- stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break;
+ stm32_tim_gpioconfig(GPIO_TIM9_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM10
+ case STM32_TIM10_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM10_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM10_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM10_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM10_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM10_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM10_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM10_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM10_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM11
+ case STM32_TIM11_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM11_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM11_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM11_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM11_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM11_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM11_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM11_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM11_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM12
+ case STM32_TIM12_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM12_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM12_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM12_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM12_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM12_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM12_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM12_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM12_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM13
+ case STM32_TIM13_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM13_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM13_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM13_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM13_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM13_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM13_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM13_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM13_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM14
+ case STM32_TIM14_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM14_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM14_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM14_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM14_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM14_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM14_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM14_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM14_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM15
+ case STM32_TIM15_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM15_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM15_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM15_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM15_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode);
+ break;
#endif
default:
- return ERROR;
+ return -EINVAL;
}
break;
#endif
+#ifdef CONFIG_STM32_TIM16
+ case STM32_TIM16_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM16_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM16_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM16_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM16_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM17
+ case STM32_TIM17_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM17_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM17_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM17_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM17_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+ break;
#endif
default:
- return ERROR;
+ return -EINVAL;
}
return OK;
@@ -800,7 +1271,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
uint32_t compare)
{
- ASSERT(dev);
+ DEBUGASSERT(dev != NULL);
switch (channel)
{
@@ -817,14 +1288,14 @@ static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel
stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare);
break;
default:
- return ERROR;
+ return -EINVAL;
}
return OK;
}
static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel)
{
- ASSERT(dev);
+ DEBUGASSERT(dev != NULL);
switch (channel)
{
@@ -838,7 +1309,7 @@ static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel
return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET);
}
- return ERROR;
+ return -EINVAL;
}
/************************************************************************************
@@ -865,6 +1336,14 @@ struct stm32_tim_ops_s stm32_tim_ops =
.ackint = &stm32_tim_ackint
};
+#ifdef CONFIG_STM32_TIM1
+struct stm32_tim_priv_s stm32_tim1_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM1_BASE,
+};
+#endif
#ifdef CONFIG_STM32_TIM2
struct stm32_tim_priv_s stm32_tim2_priv =
{
@@ -901,7 +1380,6 @@ struct stm32_tim_priv_s stm32_tim5_priv =
};
#endif
-#if STM32_NBTIM > 0
#ifdef CONFIG_STM32_TIM6
struct stm32_tim_priv_s stm32_tim6_priv =
{
@@ -910,9 +1388,7 @@ struct stm32_tim_priv_s stm32_tim6_priv =
.base = STM32_TIM6_BASE,
};
#endif
-#endif
-#if STM32_NBTIM > 1
#ifdef CONFIG_STM32_TIM7
struct stm32_tim_priv_s stm32_tim7_priv =
{
@@ -921,28 +1397,95 @@ struct stm32_tim_priv_s stm32_tim7_priv =
.base = STM32_TIM7_BASE,
};
#endif
+
+#ifdef CONFIG_STM32_TIM8
+struct stm32_tim_priv_s stm32_tim8_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM8_BASE,
+};
#endif
-#if STM32_NATIM > 0
+#ifdef CONFIG_STM32_TIM9
+struct stm32_tim_priv_s stm32_tim9_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM9_BASE,
+};
+#endif
-#ifdef CONFIG_STM32_TIM1
-struct stm32_tim_priv_s stm32_tim1_priv =
+#ifdef CONFIG_STM32_TIM10
+struct stm32_tim_priv_s stm32_tim10_priv =
{
.ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED,
- .base = STM32_TIM1_BASE,
+ .base = STM32_TIM10_BASE,
};
#endif
-#ifdef CONFIG_STM32_TIM8
-struct stm32_tim_priv_s stm32_tim8_priv =
+#ifdef CONFIG_STM32_TIM11
+struct stm32_tim_priv_s stm32_tim11_priv =
{
.ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED,
- .base = STM32_TIM8_BASE,
+ .base = STM32_TIM11_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32_TIM12
+struct stm32_tim_priv_s stm32_tim12_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM12_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32_TIM13
+struct stm32_tim_priv_s stm32_tim13_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM13_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32_TIM14
+struct stm32_tim_priv_s stm32_tim14_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM14_BASE,
};
#endif
+#ifdef CONFIG_STM32_TIM15
+struct stm32_tim_priv_s stm32_tim15_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM15_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32_TIM16
+struct stm32_tim_priv_s stm32_tim16_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM16_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32_TIM17
+struct stm32_tim_priv_s stm32_tim17_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM17_BASE,
+};
#endif
/************************************************************************************
@@ -957,6 +1500,12 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer)
switch (timer)
{
+#ifdef CONFIG_STM32_TIM1
+ case 1:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv;
+ modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
+ break;
+#endif
#ifdef CONFIG_STM32_TIM2
case 2:
dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv;
@@ -981,37 +1530,77 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer)
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN);
break;
#endif
-
-#if STM32_NBTIM > 0
#ifdef CONFIG_STM32_TIM6
case 6:
dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN);
break;
#endif
-#endif
-#if STM32_NBTIM > 1
#ifdef CONFIG_STM32_TIM7
case 7:
dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN);
break;
#endif
-#endif
-
-#if STM32_NATIM > 0
-#ifdef CONFIG_STM32_TIM1
- case 1:
- dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv;
- modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
- break;
-#endif
#ifdef CONFIG_STM32_TIM8
case 8:
dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
break;
#endif
+#ifdef CONFIG_STM32_TIM9
+ case 9:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim9_priv;
+ modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM9EN);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM10
+ case 10:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim10_priv;
+ modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM10EN);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM11
+ case 11:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim11_priv;
+ modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM11EN);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM12
+ case 12:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv;
+ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM13
+ case 13:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv;
+ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM14
+ case 14:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv;
+ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM14EN);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM15
+ case 15:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv;
+ modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM16
+ case 16:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv;
+ modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM17
+ case 17:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv;
+ modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN);
+ break;
#endif
default:
return NULL;
@@ -1033,12 +1622,17 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer)
int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
{
- ASSERT(dev);
+ DEBUGASSERT(dev != NULL);
/* Disable power */
switch (((struct stm32_tim_priv_s *)dev)->base)
{
+#ifdef CONFIG_STM32_TIM1
+ case STM32_TIM1_BASE:
+ modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
+ break;
+#endif
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0);
@@ -1059,35 +1653,68 @@ int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0);
break;
#endif
-#if STM32_NBTIM > 0
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0);
break;
#endif
-#endif
-#if STM32_NBTIM > 1
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0);
break;
#endif
-#endif
-
-#if STM32_NATIM > 0
-#ifdef CONFIG_STM32_TIM1
- case STM32_TIM1_BASE:
- modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
- break;
-#endif
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0);
break;
#endif
+#ifdef CONFIG_STM32_TIM9
+ case STM32_TIM9_BASE:
+ modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM9EN, 0);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM10
+ case STM32_TIM10_BASE:
+ modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM10EN, 0);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM11
+ case STM32_TIM11_BASE:
+ modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM11EN, 0);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM12
+ case STM32_TIM12_BASE:
+ modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM13
+ case STM32_TIM13_BASE:
+ modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM14
+ case STM32_TIM14_BASE:
+ modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM14EN, 0);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM15
+ case STM32_TIM15_BASE:
+ modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM16
+ case STM32_TIM16_BASE:
+ modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM17
+ case STM32_TIM17_BASE:
+ modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0);
+ break;
#endif
default:
- return ERROR;
+ return -EINVAL;
}
/* Mark it as free */
@@ -1097,4 +1724,4 @@ int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
return OK;
}
-#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM8) */
+#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */
diff --git a/arch/arm/src/stm32/stm32_usbdev.c b/arch/arm/src/stm32/stm32_usbdev.c
index 27f75be899a0c0deba68a77eb30a55a2c33e37cb..9c69a86b8fecb5cd75be5c7764ef4d4fceb00cf1 100644
--- a/arch/arm/src/stm32/stm32_usbdev.c
+++ b/arch/arm/src/stm32/stm32_usbdev.c
@@ -103,7 +103,7 @@
* enabled.
*/
-#ifndef CONFIG_DEBUG
+#ifndef CONFIG_DEBUG_USB_INFO
# undef CONFIG_STM32_USBDEV_REGDEBUG
#endif
@@ -388,7 +388,7 @@ struct stm32_usbdev_s
/* Register operations ******************************************************/
-#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_STM32_USBDEV_REGDEBUG
static uint16_t stm32_getreg(uint32_t addr);
static void stm32_putreg(uint16_t val, uint32_t addr);
static void stm32_checksetup(void);
@@ -648,11 +648,12 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
/****************************************************************************
* Register Operations
****************************************************************************/
+
/****************************************************************************
* Name: stm32_getreg
****************************************************************************/
-#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_STM32_USBDEV_REGDEBUG
static uint16_t stm32_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@@ -673,7 +674,7 @@ static uint16_t stm32_getreg(uint32_t addr)
{
if (count == 4)
{
- lldbg("...\n");
+ uinfo("...\n");
}
return val;
}
@@ -689,7 +690,7 @@ static uint16_t stm32_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -701,7 +702,7 @@ static uint16_t stm32_getreg(uint32_t addr)
/* Show the register value read */
- lldbg("%08x->%04x\n", addr, val);
+ uinfo("%08x->%04x\n", addr, val);
return val;
}
#endif
@@ -710,12 +711,12 @@ static uint16_t stm32_getreg(uint32_t addr)
* Name: stm32_putreg
****************************************************************************/
-#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_STM32_USBDEV_REGDEBUG
static void stm32_putreg(uint16_t val, uint32_t addr)
{
/* Show the register value being written */
- lldbg("%08x<-%04x\n", addr, val);
+ uinfo("%08x<-%04x\n", addr, val);
/* Write the value */
@@ -727,42 +728,42 @@ static void stm32_putreg(uint16_t val, uint32_t addr)
* Name: stm32_dumpep
****************************************************************************/
-#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_STM32_USBDEV_REGDEBUG
static void stm32_dumpep(int epno)
{
uint32_t addr;
/* Common registers */
- lldbg("CNTR: %04x\n", getreg16(STM32_USB_CNTR));
- lldbg("ISTR: %04x\n", getreg16(STM32_USB_ISTR));
- lldbg("FNR: %04x\n", getreg16(STM32_USB_FNR));
- lldbg("DADDR: %04x\n", getreg16(STM32_USB_DADDR));
- lldbg("BTABLE: %04x\n", getreg16(STM32_USB_BTABLE));
+ uinfo("CNTR: %04x\n", getreg16(STM32_USB_CNTR));
+ uinfo("ISTR: %04x\n", getreg16(STM32_USB_ISTR));
+ uinfo("FNR: %04x\n", getreg16(STM32_USB_FNR));
+ uinfo("DADDR: %04x\n", getreg16(STM32_USB_DADDR));
+ uinfo("BTABLE: %04x\n", getreg16(STM32_USB_BTABLE));
/* Endpoint register */
addr = STM32_USB_EPR(epno);
- lldbg("EPR%d: [%08x] %04x\n", epno, addr, getreg16(addr));
+ uinfo("EPR%d: [%08x] %04x\n", epno, addr, getreg16(addr));
/* Endpoint descriptor */
addr = STM32_USB_BTABLE_ADDR(epno, 0);
- lldbg("DESC: %08x\n", addr);
+ uinfo("DESC: %08x\n", addr);
/* Endpoint buffer descriptor */
addr = STM32_USB_ADDR_TX(epno);
- lldbg(" TX ADDR: [%08x] %04x\n", addr, getreg16(addr));
+ uinfo(" TX ADDR: [%08x] %04x\n", addr, getreg16(addr));
addr = STM32_USB_COUNT_TX(epno);
- lldbg(" COUNT: [%08x] %04x\n", addr, getreg16(addr));
+ uinfo(" COUNT: [%08x] %04x\n", addr, getreg16(addr));
addr = STM32_USB_ADDR_RX(epno);
- lldbg(" RX ADDR: [%08x] %04x\n", addr, getreg16(addr));
+ uinfo(" RX ADDR: [%08x] %04x\n", addr, getreg16(addr));
addr = STM32_USB_COUNT_RX(epno);
- lldbg(" COUNT: [%08x] %04x\n", addr, getreg16(addr));
+ uinfo(" COUNT: [%08x] %04x\n", addr, getreg16(addr));
}
#endif
@@ -770,19 +771,19 @@ static void stm32_dumpep(int epno)
* Name: stm32_checksetup
****************************************************************************/
-#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_STM32_USBDEV_REGDEBUG
static void stm32_checksetup(void)
{
uint32_t cfgr = getreg32(STM32_RCC_CFGR);
uint32_t apb1rstr = getreg32(STM32_RCC_APB1RSTR);
uint32_t apb1enr = getreg32(STM32_RCC_APB1ENR);
- lldbg("CFGR: %08x APB1RSTR: %08x APB1ENR: %08x\n", cfgr, apb1rstr, apb1enr);
+ uinfo("CFGR: %08x APB1RSTR: %08x APB1ENR: %08x\n", cfgr, apb1rstr, apb1enr);
if ((apb1rstr & RCC_APB1RSTR_USBRST) != 0 ||
(apb1enr & RCC_APB1ENR_USBEN) == 0)
{
- lldbg("ERROR: USB is NOT setup correctly\n");
+ uerr("ERROR: USB is NOT setup correctly\n");
}
}
#endif
@@ -1367,8 +1368,8 @@ static int stm32_wrrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *prive
}
epno = USB_EPNO(privep->ep.eplog);
- ullvdbg("epno=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
- epno, privreq, privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
+ uinfo("epno=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
+ epno, privreq, privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
UNUSED(epno);
/* Get the number of bytes left to be sent in the packet */
@@ -1458,7 +1459,7 @@ static inline int stm32_ep0_rdrequest(struct stm32_usbdev_s *priv)
pmalen = stm32_geteprxcount(EP0);
- ullvdbg("EP0: pmalen=%d\n", pmalen);
+ uinfo("EP0: pmalen=%d\n", pmalen);
usbtrace(TRACE_READ(EP0), pmalen);
/* Read the data into our special buffer for SETUP data */
@@ -1510,7 +1511,7 @@ static int stm32_rdrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *prive
return -ENOENT;
}
- ullvdbg("EP%d: len=%d xfrd=%d\n", epno, privreq->req.len, privreq->req.xfrd);
+ uinfo("EP%d: len=%d xfrd=%d\n", epno, privreq->req.len, privreq->req.xfrd);
/* Ignore any attempt to receive a zero length packet */
@@ -1768,8 +1769,8 @@ static void stm32_ep0setup(struct stm32_usbdev_s *priv)
index.w = GETUINT16(priv->ctrl.index);
len.w = GETUINT16(priv->ctrl.len);
- ullvdbg("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
+ uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
/* Is this an setup with OUT and data of length > 0 */
@@ -1959,7 +1960,7 @@ static void stm32_ep0setup(struct stm32_usbdev_s *priv)
{
/* Special case recipient=device test mode */
- ullvdbg("test mode: %d\n", index.w);
+ uinfo("test mode: %d\n", index.w);
}
else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@@ -2840,11 +2841,11 @@ static int stm32_epconfigure(struct usbdev_ep_s *ep,
uint16_t maxpacket;
uint8_t epno;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep || !desc)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
- ulldbg("ERROR: ep=%p desc=%p\n");
+ uerr("ERROR: ep=%p desc=%p\n");
return -EINVAL;
}
#endif
@@ -2936,11 +2937,11 @@ static int stm32_epdisable(struct usbdev_ep_s *ep)
irqstate_t flags;
uint8_t epno;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
- ulldbg("ERROR: ep=%p\n", ep);
+ uerr("ERROR: ep=%p\n", ep);
return -EINVAL;
}
#endif
@@ -2971,7 +2972,7 @@ static struct usbdev_req_s *stm32_epallocreq(struct usbdev_ep_s *ep)
{
struct stm32_req_s *privreq;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
@@ -2999,7 +3000,7 @@ static void stm32_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
{
struct stm32_req_s *privreq = (struct stm32_req_s *)req;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
@@ -3024,11 +3025,12 @@ static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
uint8_t epno;
int ret = OK;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
- ulldbg("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+ uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n",
+ req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
@@ -3036,11 +3038,11 @@ static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
usbtrace(TRACE_EPSUBMIT, USB_EPNO(ep->eplog));
priv = privep->dev;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
if (!priv->driver)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
- ulldbg("ERROR: driver=%p\n", priv->driver);
+ uerr("ERROR: driver=%p\n", priv->driver);
return -ESHUTDOWN;
}
#endif
@@ -3057,7 +3059,7 @@ static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
if (privep->stalled)
{
stm32_abortrequest(privep, privreq, -EBUSY);
- ulldbg("ERROR: stalled\n");
+ uerr("ERROR: stalled\n");
ret = -EBUSY;
}
@@ -3136,7 +3138,7 @@ static int stm32_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
struct stm32_ep_s *privep = (struct stm32_ep_s *)ep;
irqstate_t flags;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!ep || !req)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
@@ -3163,7 +3165,7 @@ static int stm32_epstall(struct usbdev_ep_s *ep, bool resume)
uint16_t status;
irqstate_t flags;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!ep)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
@@ -3305,7 +3307,7 @@ static struct usbdev_ep_s *stm32_allocep(struct usbdev_s *dev, uint8_t epno,
int bufno;
usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!dev)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
@@ -3379,7 +3381,7 @@ static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep)
struct stm32_usbdev_s *priv;
struct stm32_ep_s *privep;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!dev || !ep)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
@@ -3410,7 +3412,7 @@ static int stm32_getframe(struct usbdev_s *dev)
{
uint16_t fnr;
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!dev)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
@@ -3435,7 +3437,7 @@ static int stm32_wakeup(struct usbdev_s *dev)
irqstate_t flags;
usbtrace(TRACE_DEVWAKEUP, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!dev)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
@@ -3473,7 +3475,7 @@ static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered)
usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!dev)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
@@ -3834,7 +3836,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
usbtrace(TRACE_DEVREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (!driver || !driver->ops->bind || !driver->ops->unbind ||
!driver->ops->disconnect || !driver->ops->setup)
{
@@ -3912,7 +3914,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
usbtrace(TRACE_DEVUNREGISTER, 0);
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_USB
if (driver != priv->driver)
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
diff --git a/arch/arm/src/stm32/stm32_usbhost.h b/arch/arm/src/stm32/stm32_usbhost.h
index 2a6a7335446fe83bcd1ecd59f0952667f3cc6fed..7c036a8fa614babbc9c93ba3fa0f7e101e45029f 100644
--- a/arch/arm/src/stm32/stm32_usbhost.h
+++ b/arch/arm/src/stm32/stm32_usbhost.h
@@ -236,7 +236,7 @@ enum usbhost_trace1codes_e
* want to do that?
*
* CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access
- * debug. Depends on CONFIG_DEBUG.
+ * debug. Depends on CONFIG_DEBUG_FEATURES.
*/
/************************************************************************************
diff --git a/arch/arm/src/stm32/stm32_wwdg.c b/arch/arm/src/stm32/stm32_wwdg.c
index 5cab6ce92b6db5030869ce6ef0cb5e6010fcb4ec..6c9829974377e2ad222a5cee5804af63d3deb48f 100644
--- a/arch/arm/src/stm32/stm32_wwdg.c
+++ b/arch/arm/src/stm32/stm32_wwdg.c
@@ -81,18 +81,8 @@
# define CONFIG_STM32_WWDG_DEFTIMOUT WWDG_MAXTIMEOUT
#endif
-/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing the watchdog
- * driver. NOTE: that only lldbg types are used so that the output is
- * immediately available.
- */
-
-#ifdef CONFIG_DEBUG_WATCHDOG
-# define wddbg lldbg
-# define wdvdbg llvdbg
-#else
-# define wddbg(x...)
-# define wdvdbg(x...)
+#ifndef CONFIG_DEBUG_WATCHDOG_INFO
+# undef CONFIG_STM32_WWDG_REGDEBUG
#endif
/****************************************************************************
@@ -119,7 +109,7 @@ struct stm32_lowerhalf_s
****************************************************************************/
/* Register operations ******************************************************/
-#if defined(CONFIG_STM32_WWDG_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_STM32_WWDG_REGDEBUG
static uint16_t stm32_getreg(uint32_t addr);
static void stm32_putreg(uint16_t val, uint32_t addr);
#else
@@ -179,7 +169,7 @@ static struct stm32_lowerhalf_s g_wdgdev;
*
****************************************************************************/
-#if defined(CONFIG_STM32_WWDG_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_STM32_WWDG_REGDEBUG
static uint16_t stm32_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@@ -200,7 +190,7 @@ static uint16_t stm32_getreg(uint32_t addr)
{
if (count == 4)
{
- lldbg("...\n");
+ wdinfo("...\n");
}
return val;
@@ -217,7 +207,7 @@ static uint16_t stm32_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- lldbg("[repeats %d more times]\n", count-3);
+ wdinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -229,7 +219,7 @@ static uint16_t stm32_getreg(uint32_t addr)
/* Show the register value read */
- lldbg("%08x->%04x\n", addr, val);
+ wdinfo("%08x->%04x\n", addr, val);
return val;
}
#endif
@@ -242,12 +232,12 @@ static uint16_t stm32_getreg(uint32_t addr)
*
****************************************************************************/
-#if defined(CONFIG_STM32_WWDG_REGDEBUG) && defined(CONFIG_DEBUG)
+#ifdef CONFIG_STM32_WWDG_REGDEBUG
static void stm32_putreg(uint16_t val, uint32_t addr)
{
/* Show the register value being written */
- lldbg("%08x<-%04x\n", addr, val);
+ wdinfo("%08x<-%04x\n", addr, val);
/* Write the value */
@@ -348,7 +338,7 @@ static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
{
FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
DEBUGASSERT(priv);
/* The watchdog is always disabled after a reset. It is enabled by setting
@@ -383,7 +373,7 @@ static int stm32_stop(FAR struct watchdog_lowerhalf_s *lower)
* except by a reset.
*/
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
return -ENOSYS;
}
@@ -414,7 +404,7 @@ static int stm32_keepalive(FAR struct watchdog_lowerhalf_s *lower)
{
FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
DEBUGASSERT(priv);
/* Write to T[6:0] bits to configure the counter value, no need to do
@@ -448,7 +438,7 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
uint32_t elapsed;
uint16_t reload;
- wdvdbg("Entry\n");
+ wdinfo("Entry\n");
DEBUGASSERT(priv);
/* Return the status bit */
@@ -474,10 +464,10 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
elapsed = priv->reload - reload;
status->timeleft = (priv->timeout * elapsed) / (priv->reload + 1);
- wdvdbg("Status :\n");
- wdvdbg(" flags : %08x\n", status->flags);
- wdvdbg(" timeout : %d\n", status->timeout);
- wdvdbg(" timeleft : %d\n", status->flags);
+ wdinfo("Status :\n");
+ wdinfo(" flags : %08x\n", status->flags);
+ wdinfo(" timeout : %d\n", status->timeout);
+ wdinfo(" timeleft : %d\n", status->flags);
return OK;
}
@@ -507,13 +497,13 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
int wdgtb;
DEBUGASSERT(priv);
- wdvdbg("Entry: timeout=%d\n", timeout);
+ wdinfo("Entry: timeout=%d\n", timeout);
/* Can this timeout be represented? */
if (timeout < 1 || timeout > WWDG_MAXTIMEOUT)
{
- wddbg("Cannot represent timeout=%d > %d\n",
+ wderr("ERROR: Cannot represent timeout=%d > %d\n",
timeout, WWDG_MAXTIMEOUT);
return -ERANGE;
}
@@ -562,7 +552,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
*/
#if 0
- wdvdbg("wdgtb=%d fwwdg=%d reload=%d timout=%d\n",
+ wdinfo("wdgtb=%d fwwdg=%d reload=%d timout=%d\n",
wdgtb, fwwdg, reload, 1000 * (reload + 1) / fwwdg);
#endif
if (reload <= WWDG_CR_T_MAX || wdgtb == 3)
@@ -595,7 +585,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
priv->fwwdg = fwwdg;
priv->reload = reload;
- wdvdbg("wdgtb=%d fwwdg=%d reload=%d timout=%d\n",
+ wdinfo("wdgtb=%d fwwdg=%d reload=%d timout=%d\n",
wdgtb, fwwdg, reload, priv->timeout);
/* Set WDGTB[1:0] bits according to calculated value */
@@ -644,7 +634,7 @@ static xcpt_t stm32_capture(FAR struct watchdog_lowerhalf_s *lower,
uint16_t regval;
DEBUGASSERT(priv);
- wdvdbg("Entry: handler=%p\n", handler);
+ wdinfo("Entry: handler=%p\n", handler);
/* Get the old handler return value */
@@ -708,7 +698,7 @@ static int stm32_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
int ret = -ENOTTY;
DEBUGASSERT(priv);
- wdvdbg("Entry: cmd=%d arg=%ld\n", cmd, arg);
+ wdinfo("Entry: cmd=%d arg=%ld\n", cmd, arg);
/* WDIOC_MINTIME: Set the minimum ping time. If two keepalive ioctls
* are received within this time, a reset event will be generated.
@@ -761,7 +751,7 @@ void stm32_wwdginitialize(FAR const char *devpath)
{
FAR struct stm32_lowerhalf_s *priv = &g_wdgdev;
- wdvdbg("Entry: devpath=%s\n", devpath);
+ wdinfo("Entry: devpath=%s\n", devpath);
/* NOTE we assume that clocking to the IWDG has already been provided by
* the RCC initialization logic.
diff --git a/arch/arm/src/stm32/stm32f10xxx_dma.c b/arch/arm/src/stm32/stm32f10xxx_dma.c
index 8c5bf161e6ae4fcd734e9d19dc38e93e7f05b17a..8a7782773e268a1b025fffcd5c2d7b68cad76a24 100644
--- a/arch/arm/src/stm32/stm32f10xxx_dma.c
+++ b/arch/arm/src/stm32/stm32f10xxx_dma.c
@@ -57,7 +57,7 @@
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
- defined(CONFIG_STM32_STM32L15XX)
+ defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32L15XX)
/****************************************************************************
* Pre-processor Definitions
@@ -157,7 +157,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
{
.chan = 3,
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX) || \
- defined(CONFIG_STM32_STM32L15XX)
+ defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32L15XX)
.irq = STM32_IRQ_DMA2CH4,
#else
.irq = STM32_IRQ_DMA2CH45,
@@ -167,7 +167,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
{
.chan = 4,
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX) || \
- defined(CONFIG_STM32_STM32L15XX)
+ defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32L15XX)
.irq = STM32_IRQ_DMA2CH5,
#else
.irq = STM32_IRQ_DMA2CH45,
@@ -290,7 +290,7 @@ static int stm32_dmainterrupt(int irq, void *context)
else
#if STM32_NDMA > 1
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX) || \
- defined(CONFIG_STM32_STM32L15XX)
+ defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32L15XX)
if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5)
#else
if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH45)
@@ -707,7 +707,7 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs)
{
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
@@ -734,19 +734,19 @@ void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
const char *msg)
{
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
uint32_t dmabase = DMA_BASE(dmach->base);
- dmadbg("DMA Registers: %s\n", msg);
- dmadbg(" ISRC[%08x]: %08x\n", dmabase + STM32_DMA_ISR_OFFSET, regs->isr);
- dmadbg(" CCR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr);
- dmadbg(" CNDTR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr);
- dmadbg(" CPAR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar);
- dmadbg(" CMAR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar);
+ dmainfo("DMA Registers: %s\n", msg);
+ dmainfo(" ISRC[%08x]: %08x\n", dmabase + STM32_DMA_ISR_OFFSET, regs->isr);
+ dmainfo(" CCR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr);
+ dmainfo(" CNDTR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr);
+ dmainfo(" CPAR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar);
+ dmainfo(" CMAR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar);
}
#endif
diff --git a/arch/arm/src/stm32/stm32f20xxx_dma.c b/arch/arm/src/stm32/stm32f20xxx_dma.c
index 39c40f59f65115ae6cb37b36d1bbfc04359eb0a0..8edd31db2cb98aced83bc7b24e0caee1d8252674 100644
--- a/arch/arm/src/stm32/stm32f20xxx_dma.c
+++ b/arch/arm/src/stm32/stm32f20xxx_dma.c
@@ -606,8 +606,8 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
uint32_t regoffset;
uint32_t regval;
- dmadbg("paddr: %08x maddr: %08x ntransfers: %d scr: %08x\n",
- paddr, maddr, ntransfers, scr);
+ dmainfo("paddr: %08x maddr: %08x ntransfers: %d scr: %08x\n",
+ paddr, maddr, ntransfers, scr);
/* "If the stream is enabled, disable it by resetting the EN bit in the
* DMA_SxCR register, then read this bit in order to confirm that there is no
@@ -973,7 +973,7 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs)
{
struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle;
@@ -1003,22 +1003,22 @@ void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
const char *msg)
{
struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle;
uint32_t dmabase = DMA_BASE(dmast->base);
- dmadbg("DMA Registers: %s\n", msg);
- dmadbg(" LISR[%08x]: %08x\n", dmabase + STM32_DMA_LISR_OFFSET, regs->lisr);
- dmadbg(" HISR[%08x]: %08x\n", dmabase + STM32_DMA_HISR_OFFSET, regs->hisr);
- dmadbg(" SCR[%08x]: %08x\n", dmast->base + STM32_DMA_SCR_OFFSET, regs->scr);
- dmadbg(" SNDTR[%08x]: %08x\n", dmast->base + STM32_DMA_SNDTR_OFFSET, regs->sndtr);
- dmadbg(" SPAR[%08x]: %08x\n", dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar);
- dmadbg(" SM0AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar);
- dmadbg(" SM1AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar);
- dmadbg(" SFCR[%08x]: %08x\n", dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr);
+ dmainfo("DMA Registers: %s\n", msg);
+ dmainfo(" LISR[%08x]: %08x\n", dmabase + STM32_DMA_LISR_OFFSET, regs->lisr);
+ dmainfo(" HISR[%08x]: %08x\n", dmabase + STM32_DMA_HISR_OFFSET, regs->hisr);
+ dmainfo(" SCR[%08x]: %08x\n", dmast->base + STM32_DMA_SCR_OFFSET, regs->scr);
+ dmainfo(" SNDTR[%08x]: %08x\n", dmast->base + STM32_DMA_SNDTR_OFFSET, regs->sndtr);
+ dmainfo(" SPAR[%08x]: %08x\n", dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar);
+ dmainfo(" SM0AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar);
+ dmainfo(" SM1AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar);
+ dmainfo(" SFCR[%08x]: %08x\n", dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr);
}
#endif
diff --git a/arch/arm/src/stm32/stm32f30xxx_i2c.c b/arch/arm/src/stm32/stm32f30xxx_i2c.c
index 15b0cb63bb4f65700ac46def29585f5e6d011aaf..141b0deb75c64f2a1d3102c7acef54bba81bb106 100644
--- a/arch/arm/src/stm32/stm32f30xxx_i2c.c
+++ b/arch/arm/src/stm32/stm32f30xxx_i2c.c
@@ -154,15 +154,6 @@
#define STATUS_BUSY(status) (status & I2C_ISR_BUSY)
/* Debug ****************************************************************************/
-/* CONFIG_DEBUG_I2C + CONFIG_DEBUG enables general I2C debug output. */
-
-#ifdef CONFIG_DEBUG_I2C
-# define i2cdbg dbg
-# define i2cvdbg vdbg
-#else
-# define i2cdbg(x...)
-# define i2cvdbg(x...)
-#endif
/* I2C event trace logic. NOTE: trace uses the internal, non-standard, low-level
* debug interface syslog() but does not require that any other debug
@@ -727,7 +718,7 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
while (priv->intstate != INTSTATE_DONE && elapsed < timeout);
- i2cvdbg("intstate: %d elapsed: %ld threshold: %ld status: %08x\n",
+ i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: %08x\n",
priv->intstate, (long)elapsed, (long)timeout, priv->status);
/* Set the interrupt state back to IDLE */
@@ -881,7 +872,7 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
* still pending.
*/
- i2cvdbg("Timeout with CR: %04x SR: %04x\n", cr, sr);
+ i2cinfo("Timeout with CR: %04x SR: %04x\n", cr, sr);
}
/************************************************************************************
@@ -975,7 +966,7 @@ static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv,
if (priv->tndx >= (CONFIG_I2C_NTRACE-1))
{
- i2cdbg("Trace table overflow\n");
+ i2cerr("ERROR: Trace table overflow\n");
return;
}
@@ -1016,7 +1007,7 @@ static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv,
if (priv->tndx >= (CONFIG_I2C_NTRACE-1))
{
- i2cdbg("Trace table overflow\n");
+ i2cerr("ERROR: Trace table overflow\n");
return;
}
@@ -1709,7 +1700,7 @@ static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
status = stm32_i2c_getstatus(priv);
ret = -ETIMEDOUT;
- i2cdbg("Timed out: CR1: %04x status: %08x\n",
+ i2cerr("ERROR: Timed out: CR1: %04x status: %08x\n",
stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status);
/* "Note: When the STOP, START or PEC bit is set, the software must
diff --git a/arch/arm/src/stm32/stm32f40xxx_dma.c b/arch/arm/src/stm32/stm32f40xxx_dma.c
index 41d243685957832fc2581aa9c62c13174fb33e07..f631c6ea4a6aa5ff19a2422cc7eb596dc7f0c0bf 100644
--- a/arch/arm/src/stm32/stm32f40xxx_dma.c
+++ b/arch/arm/src/stm32/stm32f40xxx_dma.c
@@ -605,8 +605,8 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
uint32_t regoffset;
uint32_t regval;
- dmadbg("paddr: %08x maddr: %08x ntransfers: %d scr: %08x\n",
- paddr, maddr, ntransfers, scr);
+ dmainfo("paddr: %08x maddr: %08x ntransfers: %d scr: %08x\n",
+ paddr, maddr, ntransfers, scr);
#ifdef CONFIG_STM32_DMACAPABLE
DEBUGASSERT(stm32_dmacapable(maddr, ntransfers, scr));
@@ -869,7 +869,7 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
uint32_t transfer_size, burst_length;
uint32_t mend;
- dmavdbg("stm32_dmacapable: 0x%08x/%u 0x%08x\n", maddr, count, ccr);
+ dmainfo("stm32_dmacapable: 0x%08x/%u 0x%08x\n", maddr, count, ccr);
/* Verify that the address conforms to the memory transfer size.
* Transfers to/from memory performed by the DMA controller are
@@ -899,13 +899,13 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
break;
default:
- dmavdbg("stm32_dmacapable: bad transfer size in CCR\n");
+ dmainfo("stm32_dmacapable: bad transfer size in CCR\n");
return false;
}
if ((maddr & (transfer_size - 1)) != 0)
{
- dmavdbg("stm32_dmacapable: transfer unaligned\n");
+ dmainfo("stm32_dmacapable: transfer unaligned\n");
return false;
}
@@ -937,13 +937,13 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
break;
default:
- dmavdbg("stm32_dmacapable: bad burst size in CCR\n");
+ dmainfo("stm32_dmacapable: bad burst size in CCR\n");
return false;
}
if ((maddr & (burst_length - 1)) != 0)
{
- dmavdbg("stm32_dmacapable: burst crosses 1KiB\n");
+ dmainfo("stm32_dmacapable: burst crosses 1KiB\n");
return false;
}
}
@@ -952,7 +952,7 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK))
{
- dmavdbg("stm32_dmacapable: transfer crosses memory region\n");
+ dmainfo("stm32_dmacapable: transfer crosses memory region\n");
return false;
}
@@ -973,7 +973,7 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
if (maddr >= STM32_CCMRAM_BASE &&
(maddr - STM32_CCMRAM_BASE) < 65536)
{
- dmavdbg("stm32_dmacapable: transfer targets CCMRAM\n");
+ dmainfo("stm32_dmacapable: transfer targets CCMRAM\n");
return false;
}
break;
@@ -981,11 +981,11 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
default:
/* Everything else is unsupported by DMA */
- dmavdbg("stm32_dmacapable: transfer targets unknown/unsupported region\n");
+ dmainfo("stm32_dmacapable: transfer targets unknown/unsupported region\n");
return false;
}
- dmavdbg("stm32_dmacapable: transfer OK\n");
+ dmainfo("stm32_dmacapable: transfer OK\n");
return true;
}
#endif
@@ -1001,7 +1001,7 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs)
{
struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle;
@@ -1031,22 +1031,22 @@ void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs)
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_DMA
+#ifdef CONFIG_DEBUG_DMA_INFO
void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
const char *msg)
{
struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle;
uint32_t dmabase = DMA_BASE(dmast->base);
- dmadbg("DMA Registers: %s\n", msg);
- dmadbg(" LISR[%08x]: %08x\n", dmabase + STM32_DMA_LISR_OFFSET, regs->lisr);
- dmadbg(" HISR[%08x]: %08x\n", dmabase + STM32_DMA_HISR_OFFSET, regs->hisr);
- dmadbg(" SCR[%08x]: %08x\n", dmast->base + STM32_DMA_SCR_OFFSET, regs->scr);
- dmadbg(" SNDTR[%08x]: %08x\n", dmast->base + STM32_DMA_SNDTR_OFFSET, regs->sndtr);
- dmadbg(" SPAR[%08x]: %08x\n", dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar);
- dmadbg(" SM0AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar);
- dmadbg(" SM1AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar);
- dmadbg(" SFCR[%08x]: %08x\n", dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr);
+ dmainfo("DMA Registers: %s\n", msg);
+ dmainfo(" LISR[%08x]: %08x\n", dmabase + STM32_DMA_LISR_OFFSET, regs->lisr);
+ dmainfo(" HISR[%08x]: %08x\n", dmabase + STM32_DMA_HISR_OFFSET, regs->hisr);
+ dmainfo(" SCR[%08x]: %08x\n", dmast->base + STM32_DMA_SCR_OFFSET, regs->scr);
+ dmainfo(" SNDTR[%08x]: %08x\n", dmast->base + STM32_DMA_SNDTR_OFFSET, regs->sndtr);
+ dmainfo(" SPAR[%08x]: %08x\n", dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar);
+ dmainfo(" SM0AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar);
+ dmainfo(" SM1AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar);
+ dmainfo(" SFCR[%08x]: %08x\n", dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr);
}
#endif
diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32/stm32f40xxx_rcc.c
index d431ce6df7a886fb4465328d22b185fe6cd2642b..3d259ec5c39dbd1e15e50daf8bb51dbc5b2fd336 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c
@@ -911,7 +911,7 @@ static void stm32_stdclockconfig(void)
*
****************************************************************************/
-#if defined(CONFIG_SYSLOG) && defined(CONFIG_ARMV7M_ITMSYSLOG)
+#ifdef CONFIG_ARMV7M_ITMSYSLOG
static inline void rcc_itm_syslog(void)
{
/* Enable SWO output */
diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
index ece81269c6698513f1c9ef42cf7d9b3d1f494c4f..0e55a4ad7dd7976f86c674028b66b8f10da74fb0 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
@@ -38,6 +38,8 @@
* Included Files
************************************************************************************/
+#include
+
#include
#include
#include
@@ -79,24 +81,10 @@
# error "CONFIG_STM32_PWR must selected to use this driver"
#endif
-#ifndef CONFIG_DEBUG
-# undef CONFIG_DEBUG_RTC
-#endif
-
-#if !defined(CONFIG_RTC_MAGIC)
-# define CONFIG_RTC_MAGIC (0xfacefeee)
-#endif
-
-#if !defined(CONFIG_RTC_MAGIC_REG)
-# define CONFIG_RTC_MAGIC_REG (0)
-#endif
-
/* Constants ************************************************************************/
#define SYNCHRO_TIMEOUT (0x00020000)
#define INITMODE_TIMEOUT (0x00010000)
-#define RTC_MAGIC CONFIG_RTC_MAGIC
-#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_RTC_MAGIC_REG)
/* Proxy definitions to make the same code work for all the STM32 series ************/
@@ -108,18 +96,6 @@
# define RCC_XXX_RTCSEL_LSI RCC_BDCR_RTCSEL_LSI
# define RCC_XXX_RTCSEL_HSE RCC_BDCR_RTCSEL_HSE
-/* BCD conversions */
-
-#define rtc_reg_tr_bin2bcd(tp) \
- ((rtc_bin2bcd((tp)->tm_sec) << RTC_TR_SU_SHIFT) | \
- (rtc_bin2bcd((tp)->tm_min) << RTC_TR_MNU_SHIFT) | \
- (rtc_bin2bcd((tp)->tm_hour) << RTC_TR_HU_SHIFT))
-
-#define rtc_reg_alrmr_bin2bcd(tm) \
- ((rtc_bin2bcd((tm)->tm_sec) << RTC_ALRMR_SU_SHIFT) | \
- (rtc_bin2bcd((tm)->tm_min) << RTC_ALRMR_MNU_SHIFT) | \
- (rtc_bin2bcd((tm)->tm_hour) << RTC_ALRMR_HU_SHIFT))
-
/* Time conversions */
#define MINUTES_IN_HOUR 60
@@ -141,20 +117,6 @@
#define RTC_ALRMR_DIS_DATE_MASK (RTC_ALRMR_MSK4)
#define RTC_ALRMR_ENABLE (0)
-/* Debug ****************************************************************************/
-
-#ifdef CONFIG_DEBUG_RTC
-# define rtcdbg dbg
-# define rtcvdbg vdbg
-# define rtclldbg lldbg
-# define rtcllvdbg llvdbg
-#else
-# define rtcdbg(x...)
-# define rtcvdbg(x...)
-# define rtclldbg(x...)
-# define rtcllvdbg(x...)
-#endif
-
/************************************************************************************
* Private Types
************************************************************************************/
@@ -193,10 +155,12 @@ volatile bool g_rtc_enabled = false;
#ifdef CONFIG_RTC_ALARM
static int rtchw_check_alrawf(void);
-static int rtchw_check_alrbwf(void);
static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg);
+#if CONFIG_RTC_NALARMS > 1
+static int rtchw_check_alrbwf(void);
static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg);
#endif
+#endif
/************************************************************************************
* Private Functions
@@ -216,30 +180,36 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg);
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_RTC
+#ifdef CONFIG_DEBUG_RTC_INFO
static void rtc_dumpregs(FAR const char *msg)
{
- rtclldbg("%s:\n", msg);
- rtclldbg(" TR: %08x\n", getreg32(STM32_RTC_TR));
- rtclldbg(" DR: %08x\n", getreg32(STM32_RTC_DR));
- rtclldbg(" CR: %08x\n", getreg32(STM32_RTC_CR));
- rtclldbg(" ISR: %08x\n", getreg32(STM32_RTC_ISR));
- rtclldbg(" PRER: %08x\n", getreg32(STM32_RTC_PRER));
- rtclldbg(" WUTR: %08x\n", getreg32(STM32_RTC_WUTR));
-#ifndef CONFIG_STM32_STM32F30XX
- rtclldbg(" CALIBR: %08x\n", getreg32(STM32_RTC_CALIBR));
-#endif
- rtclldbg(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR));
- rtclldbg(" ALRMBR: %08x\n", getreg32(STM32_RTC_ALRMBR));
- rtclldbg(" SHIFTR: %08x\n", getreg32(STM32_RTC_SHIFTR));
- rtclldbg(" TSTR: %08x\n", getreg32(STM32_RTC_TSTR));
- rtclldbg(" TSDR: %08x\n", getreg32(STM32_RTC_TSDR));
- rtclldbg(" TSSSR: %08x\n", getreg32(STM32_RTC_TSSSR));
- rtclldbg(" CALR: %08x\n", getreg32(STM32_RTC_CALR));
- rtclldbg(" TAFCR: %08x\n", getreg32(STM32_RTC_TAFCR));
- rtclldbg("ALRMASSR: %08x\n", getreg32(STM32_RTC_ALRMASSR));
- rtclldbg("ALRMBSSR: %08x\n", getreg32(STM32_RTC_ALRMBSSR));
- rtclldbg("MAGICREG: %08x\n", getreg32(RTC_MAGIC_REG));
+ int rtc_state;
+
+ rtcinfo("%s:\n", msg);
+ rtcinfo(" TR: %08x\n", getreg32(STM32_RTC_TR));
+ rtcinfo(" DR: %08x\n", getreg32(STM32_RTC_DR));
+ rtcinfo(" CR: %08x\n", getreg32(STM32_RTC_CR));
+ rtcinfo(" ISR: %08x\n", getreg32(STM32_RTC_ISR));
+ rtcinfo(" PRER: %08x\n", getreg32(STM32_RTC_PRER));
+ rtcinfo(" WUTR: %08x\n", getreg32(STM32_RTC_WUTR));
+ rtcinfo(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR));
+ rtcinfo(" ALRMBR: %08x\n", getreg32(STM32_RTC_ALRMBR));
+ rtcinfo(" SHIFTR: %08x\n", getreg32(STM32_RTC_SHIFTR));
+ rtcinfo(" TSTR: %08x\n", getreg32(STM32_RTC_TSTR));
+ rtcinfo(" TSDR: %08x\n", getreg32(STM32_RTC_TSDR));
+ rtcinfo(" TSSSR: %08x\n", getreg32(STM32_RTC_TSSSR));
+ rtcinfo(" CALR: %08x\n", getreg32(STM32_RTC_CALR));
+ rtcinfo(" TAFCR: %08x\n", getreg32(STM32_RTC_TAFCR));
+ rtcinfo("ALRMASSR: %08x\n", getreg32(STM32_RTC_ALRMASSR));
+ rtcinfo("ALRMBSSR: %08x\n", getreg32(STM32_RTC_ALRMBSSR));
+ rtcinfo("MAGICREG: %08x\n", getreg32(RTC_MAGIC_REG));
+
+ rtc_state =
+ ((getreg32(STM32_EXTI_RTSR) & EXTI_RTC_ALARM) ? 0x1000 : 0) |
+ ((getreg32(STM32_EXTI_FTSR) & EXTI_RTC_ALARM) ? 0x0100 : 0) |
+ ((getreg32(STM32_EXTI_IMR) & EXTI_RTC_ALARM) ? 0x0010 : 0) |
+ ((getreg32(STM32_EXTI_EMR) & EXTI_RTC_ALARM) ? 0x0001 : 0);
+ rtcinfo("EXTI (RTSR FTSR ISR EVT): %01x\n",rtc_state);
}
#else
# define rtc_dumpregs(msg)
@@ -259,16 +229,16 @@ static void rtc_dumpregs(FAR const char *msg)
*
************************************************************************************/
-#ifdef CONFIG_DEBUG_RTC
+#ifdef CONFIG_DEBUG_RTC_INFO
static void rtc_dumptime(FAR const struct tm *tp, FAR const char *msg)
{
- rtclldbg("%s:\n", msg);
- rtclldbg(" tm_sec: %08x\n", tp->tm_sec);
- rtclldbg(" tm_min: %08x\n", tp->tm_min);
- rtclldbg(" tm_hour: %08x\n", tp->tm_hour);
- rtclldbg(" tm_mday: %08x\n", tp->tm_mday);
- rtclldbg(" tm_mon: %08x\n", tp->tm_mon);
- rtclldbg(" tm_year: %08x\n", tp->tm_year);
+ rtcinfo("%s:\n", msg);
+ rtcinfo(" tm_sec: %08x\n", tp->tm_sec);
+ rtcinfo(" tm_min: %08x\n", tp->tm_min);
+ rtcinfo(" tm_hour: %08x\n", tp->tm_hour);
+ rtcinfo(" tm_mday: %08x\n", tp->tm_mday);
+ rtcinfo(" tm_mon: %08x\n", tp->tm_mon);
+ rtcinfo(" tm_year: %08x\n", tp->tm_year);
}
#else
# define rtc_dumptime(tp, msg)
@@ -600,9 +570,9 @@ static void rtc_resume(void)
regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF);
putreg32(regval, STM32_RTC_ISR);
- /* Clear the EXTI Line 17 Pending bit (Connected internally to RTC Alarm) */
+ /* Clear the RTC Alarm Pending bit */
- putreg32((1 << 17), STM32_EXTI_PR);
+ putreg32(EXTI_RTC_ALARM, STM32_EXTI_PR);
#endif
}
@@ -659,6 +629,7 @@ static int stm32_rtc_alarm_handler(int irq, void *context)
}
}
+#if CONFIG_RTC_NALARMS > 1
if ((isr & RTC_ISR_ALRBF) != 0)
{
cr = getreg32(STM32_RTC_CR);
@@ -682,6 +653,7 @@ static int stm32_rtc_alarm_handler(int irq, void *context)
putreg32(isr, STM32_RTC_CR);
}
}
+#endif
return ret;
}
@@ -727,7 +699,7 @@ static int rtchw_check_alrawf(void)
}
#endif
-#ifdef CONFIG_RTC_ALARM
+#if defined(CONFIG_RTC_ALARM) && CONFIG_RTC_NALARMS > 1
static int rtchw_check_alrbwf(void)
{
volatile uint32_t timeout;
@@ -792,7 +764,7 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg)
/* Set the RTC Alarm register */
putreg32(alarmreg, STM32_RTC_ALRMAR);
- rtcvdbg(" TR: %08x ALRMAR: %08x\n",
+ rtcinfo(" TR: %08x ALRMAR: %08x\n",
getreg32(STM32_RTC_TR), getreg32(STM32_RTC_ALRMAR));
/* Enable RTC alarm */
@@ -805,7 +777,7 @@ errout_with_wprunlock:
}
#endif
-#ifdef CONFIG_RTC_ALARM
+#if defined(CONFIG_RTC_ALARM) && CONFIG_RTC_NALARMS > 1
static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg)
{
int ret = -EBUSY;
@@ -829,7 +801,7 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg)
/* Set the RTC Alarm register */
putreg32(alarmreg, STM32_RTC_ALRMBR);
- rtcvdbg(" TR: %08x ALRMBR: %08x\n",
+ rtcinfo(" TR: %08x ALRMBR: %08x\n",
getreg32(STM32_RTC_TR), getreg32(STM32_RTC_ALRMBR));
/* Enable RTC alarm B */
@@ -876,8 +848,6 @@ int up_rtc_initialize(void)
* maximum performance.
*/
- rtc_dumpregs("On reset");
-
/* Select the clock source */
/* Save the token before losing it when resetting */
@@ -887,13 +857,6 @@ int up_rtc_initialize(void)
if (regval != RTC_MAGIC)
{
- /* We might be changing RTCSEL - to ensure such changes work, we must reset the
- * backup domain (having backed up the RTC_MAGIC token)
- */
-
- modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST);
- modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0);
-
/* Some boards do not have the external 32khz oscillator installed, for those
* boards we must fallback to the crummy internal RC clock or the external high
* rate clock
@@ -902,16 +865,19 @@ int up_rtc_initialize(void)
#ifdef CONFIG_RTC_HSECLOCK
/* Use the HSE clock as the input to the RTC block */
+ rtc_dumpregs("On reset HSE");
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_HSE);
#elif defined(CONFIG_RTC_LSICLOCK)
/* Use the LSI clock as the input to the RTC block */
+ rtc_dumpregs("On reset LSI");
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSI);
#elif defined(CONFIG_RTC_LSECLOCK)
/* Use the LSE clock as the input to the RTC block */
+ rtc_dumpregs("On reset LSE");
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSE);
#endif
@@ -926,6 +892,8 @@ int up_rtc_initialize(void)
uint32_t clksrc = getreg32(STM32_RCC_XXX);
+ rtc_dumpregs("On reset warm");
+
#if defined(CONFIG_RTC_HSECLOCK)
if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_HSE)
#elif defined(CONFIG_RTC_LSICLOCK)
@@ -986,13 +954,13 @@ int up_rtc_initialize(void)
{
case OK:
{
- rtclldbg("rtc_syncwait() okay\n");
+ rtcinfo("rtc_syncwait() okay\n");
break;
}
default:
{
- rtclldbg("rtc_syncwait() failed (%d)\n", ret);
+ rtcerr("ERROR: rtc_syncwait() failed (%d)\n", ret);
break;
}
}
@@ -1006,7 +974,7 @@ int up_rtc_initialize(void)
if (regval != RTC_MAGIC)
{
- rtclldbg("Do setup\n");
+ rtcinfo("Do setup\n");
/* Perform the one-time setup of the LSE clocking to the RTC */
@@ -1024,7 +992,7 @@ int up_rtc_initialize(void)
}
else
{
- rtclldbg("Do resume\n");
+ rtcinfo("Do resume\n");
/* RTC already set-up, just resume normal operation */
@@ -1040,8 +1008,8 @@ int up_rtc_initialize(void)
if (ret != OK && nretry > 0)
{
- rtclldbg("setup/resume ran %d times and failed with %d\n",
- nretry, ret);
+ rtcinfo("setup/resume ran %d times and failed with %d\n",
+ nretry, ret);
return -ETIMEDOUT;
}
@@ -1060,10 +1028,12 @@ int up_rtc_initialize(void)
*/
stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler);
+ rtc_dumpregs("After InitExtiAlarm");
+#else
+ rtc_dumpregs("After Initialization");
#endif
g_rtc_enabled = true;
- rtc_dumpregs("After Initialization");
return OK;
}
@@ -1249,7 +1219,9 @@ int stm32_rtc_setdatetime(FAR const struct tm *tp)
* register.
*/
- tr = (rtc_reg_tr_bin2bcd(tp) & ~RTC_TR_RESERVED_BITS);
+ tr = (rtc_bin2bcd(tp->tm_sec) << RTC_TR_SU_SHIFT) |
+ (rtc_bin2bcd(tp->tm_min) << RTC_TR_MNU_SHIFT) |
+ (rtc_bin2bcd(tp->tm_hour) << RTC_TR_HU_SHIFT);
/* Now convert the fields in struct tm format to the RTC date register fields:
* Days: 1-31 match in both cases.
@@ -1351,10 +1323,16 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
rtc_dumptime(&alminfo->as_time, "New alarm time");
- /* Break out the values to the HW alarm register format */
-
- alarmreg = rtc_reg_alrmr_bin2bcd(&alminfo->as_time);
+ /* Break out the values to the HW alarm register format. The values in
+ * all STM32 fields match the fields of struct tm in this case. Notice
+ * that the alarm is limited to one month.
+ */
+ alarmreg = (rtc_bin2bcd(alminfo->as_time.tm_sec) << RTC_ALRMR_SU_SHIFT) |
+ (rtc_bin2bcd(alminfo->as_time.tm_min) << RTC_ALRMR_MNU_SHIFT) |
+ (rtc_bin2bcd(alminfo->as_time.tm_hour) << RTC_ALRMR_HU_SHIFT) |
+ (rtc_bin2bcd(alminfo->as_time.tm_mday) << RTC_ALRMR_DU_SHIFT);
+
/* Set the alarm in hardware and enable interrupts */
switch (alminfo->as_id)
@@ -1371,9 +1349,12 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
cbinfo->ac_cb = NULL;
cbinfo->ac_arg = NULL;
}
+
+ rtc_dumpregs("Set AlarmA");
}
break;
+#if CONFIG_RTC_NALARMS > 1
case RTC_ALARMB:
{
cbinfo = &g_alarmcb[RTC_ALARMB];
@@ -1386,11 +1367,14 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
cbinfo->ac_cb = NULL;
cbinfo->ac_arg = NULL;
}
+
+ rtc_dumpregs("Set AlarmB");
}
break;
+#endif
default:
- rtcvdbg("ERROR: Invalid ALARM%d\n", alminfo->as_id);
+ rtcerr("ERROR: Invalid ALARM%d\n", alminfo->as_id);
break;
}
@@ -1454,6 +1438,7 @@ int stm32_rtc_cancelalarm(enum alm_id_e alarmid)
}
break;
+#if CONFIG_RTC_NALARMS > 1
case RTC_ALARMB:
{
/* Cancel the global callback function */
@@ -1484,9 +1469,10 @@ int stm32_rtc_cancelalarm(enum alm_id_e alarmid)
ret = OK;
}
break;
+#endif
default:
- rtcvdbg("ERROR: Invalid ALARM%d\n", alminfo->as_id);
+ rtcerr("ERROR: Invalid ALARM%d\n", alarmid);
break;
}
diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig
index e3a8d2b42cdedb30750d7f51f637e8197662b3b6..0f2f65f84a2a973aa45634b99ccf7f66359525e5 100644
--- a/arch/arm/src/stm32f7/Kconfig
+++ b/arch/arm/src/stm32f7/Kconfig
@@ -12,692 +12,4472 @@ choice
default ARCH_CHIP_STM32F746
depends on ARCH_CHIP_STM32F7
-config ARCH_CHIP_STM32F745
- bool "STM32F745xx"
- select STM32F7_STM32F74XX
+config ARCH_CHIP_STM32F745VG
+ bool "STM32F745VG"
+ select STM32F7_STM32F745XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_V
---help---
- STM32 F7 Cortex M7, 512 or 1024Kb FLASH, 335 (240++16+54) Kb SRAM
+ STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM
-config ARCH_CHIP_STM32F746
- bool "STM32F746xx"
- select STM32F7_STM32F74XX
- select STM32F7_HAVE_LTDC
+config ARCH_CHIP_STM32F745VE
+ bool "STM32F745VE"
+ select STM32F7_STM32F745XX
+ select STM32F7_FLASH_CONFIG_E
+ select STM32F7_IO_CONFIG_V
---help---
- STM32 F7 Cortex M7, 512 or 1024Kb FLASH, 335 (240++16+54) Kb SRAM
+ STM32 F7 Cortex M7, 512 320K FLASH, 320K (240+16+64) Kb SRAM
-config ARCH_CHIP_STM32F756
- bool "STM32F756xx"
- select STM32F7_STM32F75XX
- select STM32F7_HAVE_LTDC
+config ARCH_CHIP_STM32F745IG
+ bool "STM32F745IG"
+ select STM32F7_STM32F745XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_I
---help---
- STM32 F7 Cortex M7, 512 or 1024Kb FLASH, 335 (240++16+54) Kb SRAM
+ STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM
-endchoice # STM32 F7 Chip Selection
+config ARCH_CHIP_STM32F745IE
+ bool "STM32F745IE"
+ select STM32F7_STM32F745XX
+ select STM32F7_FLASH_CONFIG_E
+ select STM32F7_IO_CONFIG_I
+ ---help---
+ STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM
-config STM32F7_STM32F74XX
- bool
- default n
- select ARCH_HAVE_FPU
- select ARCH_HAVE_DPFPU # REVISIT
- select ARMV7M_HAVE_ICACHE
- select ARMV7M_HAVE_DCACHE
- select ARMV7M_HAVE_ITCM
- select ARMV7M_HAVE_DTCM
+config ARCH_CHIP_STM32F745ZE
+ bool "STM32F745ZE"
+ select STM32F7_STM32F745XX
+ select STM32F7_FLASH_CONFIG_E
+ select STM32F7_IO_CONFIG_Z
+ ---help---
+ STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM
-config STM32F7_STM32F75XX
- bool
- default n
- select ARCH_HAVE_FPU
- select ARCH_HAVE_DPFPU # REVISIT
- select ARMV7M_HAVE_ICACHE
- select ARMV7M_HAVE_DCACHE
- select ARMV7M_HAVE_ITCM
- select ARMV7M_HAVE_DTCM
+config ARCH_CHIP_STM32F745ZG
+ bool "STM32F745ZG"
+ select STM32F7_STM32F745XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_Z
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM
-choice
- prompt "Embedded FLASH size"
- default STM32F7_FLASH_1024KB
+config ARCH_CHIP_STM32F746BG
+ bool "STM32F746BG"
+ select STM32F7_STM32F746XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_B
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM
-config STM32F7_FLASH_512KB
- bool "512 KB"
+config ARCH_CHIP_STM32F746VG
+ bool "STM32F746VG"
+ select STM32F7_STM32F746XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_V
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM
-config STM32F7_FLASH_1024KB
- bool "1024 KB"
+config ARCH_CHIP_STM32F746VE
+ bool "STM32F746VE"
+ select STM32F7_STM32F746XX
+ select STM32F7_FLASH_CONFIG_E
+ select STM32F7_IO_CONFIG_V
+ ---help---
+ STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM
-endchoice # Embedded FLASH size
+config ARCH_CHIP_STM32F746BE
+ bool "STM32F746BE"
+ select STM32F7_STM32F746XX
+ select STM32F7_FLASH_CONFIG_E
+ select STM32F7_IO_CONFIG_B
+ ---help---
+ STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM
-menu "STM32 Peripheral Support"
+config ARCH_CHIP_STM32F746ZG
+ bool "STM32F746ZG"
+ select STM32F7_STM32F746XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_Z
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM
-# These "hidden" settings determine is a peripheral option is available for the
-# selection MCU
+config ARCH_CHIP_STM32F746IE
+ bool "STM32F746IE"
+ select STM32F7_STM32F746XX
+ select STM32F7_FLASH_CONFIG_E
+ select STM32F7_IO_CONFIG_I
+ ---help---
+ STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM
-config STM32F7_HAVE_LTDC
- bool
- default n
+config ARCH_CHIP_STM32F746NG
+ bool "STM32F746NG"
+ select STM32F7_STM32F746XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_N
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM
-# These "hidden" settings are the OR of individual peripheral selections
-# indicating that the general capabilitiy is required.
+config ARCH_CHIP_STM32F746NE
+ bool "STM32F746NE"
+ select STM32F7_STM32F746XX
+ select STM32F7_FLASH_CONFIG_E
+ select STM32F7_IO_CONFIG_N
+ ---help---
+ STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM
-config STM32F7_ADC
- bool
- default n
+config ARCH_CHIP_STM32F746ZE
+ bool "STM32F746ZE"
+ select STM32F7_STM32F746XX
+ select STM32F7_FLASH_CONFIG_E
+ select STM32F7_IO_CONFIG_Z
+ ---help---
+ STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM
-config STM32F7_CAN
- bool
- default n
+config ARCH_CHIP_STM32F746IG
+ bool "STM32F746IG"
+ select STM32F7_STM32F746XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_I
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM
-config STM32F7_DAC
- bool
- default n
+config ARCH_CHIP_STM32F756NG
+ bool "STM32F756NG"
+ select STM32F7_STM32F756XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_N
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM
-config STM32F7_DMA
- bool
- default n
+config ARCH_CHIP_STM32F756BG
+ bool "STM32F756BG"
+ select STM32F7_STM32F756XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_B
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM
-config STM32F7_I2C
- bool
- default n
+config ARCH_CHIP_STM32F756IG
+ bool "STM32F756IG"
+ select STM32F7_STM32F756XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_I
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM
-config STM32F7_SAI
- bool
- default n
+config ARCH_CHIP_STM32F756VG
+ bool "STM32F756VG"
+ select STM32F7_STM32F756XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_V
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM
-config STM32F7_SPI
- bool
- default n
+config ARCH_CHIP_STM32F756ZG
+ bool "STM32F756ZG"
+ select STM32F7_STM32F756XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_Z
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM
-config STM32F7_USART
- bool
- default n
+config ARCH_CHIP_STM32F765NI
+ bool "STM32F765NI"
+ select STM32F7_STM32F765XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_N
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
-# These are the peripheral selections proper
+config ARCH_CHIP_STM32F765VI
+ bool "STM32F765VI"
+ select STM32F7_STM32F765XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_V
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_ADC1
- bool "ADC1"
- default n
- select STM32F7_ADC
+config ARCH_CHIP_STM32F765VG
+ bool "STM32F765VG"
+ select STM32F7_STM32F765XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_V
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_ADC2
- bool "ADC2"
- default n
- select STM32F7_ADC
+config ARCH_CHIP_STM32F765BI
+ bool "STM32F765BI"
+ select STM32F7_STM32F765XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_B
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_ADC3
- bool "ADC3"
- default n
- select STM32F7_ADC
+config ARCH_CHIP_STM32F765NG
+ bool "STM32F765NG"
+ select STM32F7_STM32F765XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_N
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_BKPSRAM
- bool "Enable BKP RAM Domain"
- default n
+config ARCH_CHIP_STM32F765ZG
+ bool "STM32F765ZG"
+ select STM32F7_STM32F765XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_Z
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_CAN1
- bool "CAN1"
- default n
- select CAN
- select STM32F7_CAN
+config ARCH_CHIP_STM32F765ZI
+ bool "STM32F765ZI"
+ select STM32F7_STM32F765XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_Z
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_CAN2
- bool "CAN2"
- default n
- select CAN
- select STM32F7_CAN
+config ARCH_CHIP_STM32F765IG
+ bool "STM32F765IG"
+ select STM32F7_STM32F765XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_I
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_CEC
- bool "CEC"
- default n
- depends on STM32F7_VALUELINE
+config ARCH_CHIP_STM32F765BG
+ bool "STM32F765BG"
+ select STM32F7_STM32F765XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_B
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_CRC
- bool "CRC"
- default n
+config ARCH_CHIP_STM32F765II
+ bool "STM32F765II"
+ select STM32F7_STM32F765XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_I
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_CRYP
- bool "CRYP"
- default n
+config ARCH_CHIP_STM32F767NG
+ bool "STM32F767NG"
+ select STM32F7_STM32F767XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_N
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_DMA1
- bool "DMA1"
- default n
- select STM32F7_DMA
- select ARCH_DMA
+config ARCH_CHIP_STM32F767IG
+ bool "STM32F767IG"
+ select STM32F7_STM32F767XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_I
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_DMA2
- bool "DMA2"
- default n
- select STM32F7_DMA
- select ARCH_DMA
+config ARCH_CHIP_STM32F767VG
+ bool "STM32F767VG"
+ select STM32F7_STM32F767XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_V
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_DAC1
- bool "DAC1"
- default n
- select STM32F7_DAC
+config ARCH_CHIP_STM32F767ZG
+ bool "STM32F767ZG"
+ select STM32F7_STM32F767XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_Z
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_DAC2
- bool "DAC2"
- default n
- select STM32F7_DAC
+config ARCH_CHIP_STM32F767NI
+ bool "STM32F767NI"
+ select STM32F7_STM32F767XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_N
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_DCMI
- bool "DCMI"
- default n
+config ARCH_CHIP_STM32F767VI
+ bool "STM32F767VI"
+ select STM32F7_STM32F767XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_V
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_ETHMAC
- bool "Ethernet MAC"
- default n
- select NETDEVICES
- select ARCH_HAVE_PHY
+config ARCH_CHIP_STM32F767BG
+ bool "STM32F767BG"
+ select STM32F7_STM32F767XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_B
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_FSMC
- bool "FSMC"
- default n
+config ARCH_CHIP_STM32F767ZI
+ bool "STM32F767ZI"
+ select STM32F7_STM32F767XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_Z
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_I2C1
- bool "I2C1"
- default n
- select STM32F7_I2C
+config ARCH_CHIP_STM32F767II
+ bool "STM32F767II"
+ select STM32F7_STM32F767XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_I
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_CEC
- bool "HDMI-CEC"
- default n
+config ARCH_CHIP_STM32F769BI
+ bool "STM32F769BI"
+ select STM32F7_STM32F769XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_B
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_I2C2
- bool "I2C2"
- default n
- select STM32F7_I2C
+config ARCH_CHIP_STM32F769II
+ bool "STM32F769II"
+ select STM32F7_STM32F769XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_I
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_I2C3
- bool "I2C3"
- default n
- select STM32F7_I2C
+config ARCH_CHIP_STM32F769BG
+ bool "STM32F769BG"
+ select STM32F7_STM32F769XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_B
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_LPTIM1
- bool "Low-power timer 1"
- default n
+config ARCH_CHIP_STM32F769NI
+ bool "STM32F769NI"
+ select STM32F7_STM32F769XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_N
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_LTDC
- bool "LTDC"
- default n
- depends on STM32F7_HAVE_LTDC
+config ARCH_CHIP_STM32F769AI
+ bool "STM32F769AI"
+ select STM32F7_STM32F769AX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_A
---help---
- The STM32 LTDC is an LCD-TFT Display Controller available on
- the STM32F429 and STM32F439 devices. It is a standard parallel
- video interface (HSYNC, VSYNC, etc.) for controlling TFT
- LCD displays.
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_DMA2D
- bool "DMA2D"
- default n
+config ARCH_CHIP_STM32F769NG
+ bool "STM32F769NG"
+ select STM32F7_STM32F769XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_N
---help---
- The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation
- available on the STM32 F7 devices.
+ STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_OTGFS
- bool "OTG FS"
- default n
- select USBHOST_HAVE_ASYNCH if USBHOST
+config ARCH_CHIP_STM32F769IG
+ bool "STM32F769IG"
+ select STM32F7_STM32F769XX
+ select STM32F7_FLASH_CONFIG_G
+ select STM32F7_IO_CONFIG_I
+ ---help---
+ STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM
-config STM32F7_OTGHS
- bool "OTG HS"
+config ARCH_CHIP_STM32F777ZI
+ bool "STM32F777ZI"
+ select STM32F7_STM32F777XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_Z
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
+
+config ARCH_CHIP_STM32F777VI
+ bool "STM32F777VI"
+ select STM32F7_STM32F777XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_V
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
+
+config ARCH_CHIP_STM32F777NI
+ bool "STM32F777NI"
+ select STM32F7_STM32F777XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_N
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
+
+config ARCH_CHIP_STM32F777BI
+ bool "STM32F777BI"
+ select STM32F7_STM32F777XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_B
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
+
+config ARCH_CHIP_STM32F777II
+ bool "STM32F777II"
+ select STM32F7_STM32F777XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_I
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
+
+config ARCH_CHIP_STM32F778AI
+ bool "STM32F778AI"
+ select STM32F7_STM32F778AX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_A
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
+
+config ARCH_CHIP_STM32F779II
+ bool "STM32F779II"
+ select STM32F7_STM32F779XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_I
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
+
+config ARCH_CHIP_STM32F779NI
+ bool "STM32F779NI"
+ select STM32F7_STM32F779XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_N
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
+
+config ARCH_CHIP_STM32F779BI
+ bool "STM32F779BI"
+ select STM32F7_STM32F779XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_B
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
+
+config ARCH_CHIP_STM32F779AI
+ bool "STM32F779AI"
+ select STM32F7_STM32F779XX
+ select STM32F7_FLASH_CONFIG_I
+ select STM32F7_IO_CONFIG_A
+ ---help---
+ STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM
+
+endchoice # STM32 F7 Chip Selection
+
+config STM32F7_STM32F74XX
+ bool
default n
- select USBHOST_HAVE_ASYNCH if USBHOST
-config STM32F7_QUADSPI
- bool "QuadSPI"
+config STM32F7_STM32F75XX
+ bool
default n
-config STM32F7_SAI1
-config STM32F7_RNG
- bool "RNG"
+config STM32F7_STM32F76XX
+ bool
default n
- select ARCH_HAVE_RNG
-config STM32F7_SAI1
- bool "SAI1"
+config STM32F7_STM32F77XX
+ bool
default n
- select STM32F7_SAI
-config STM32F7_SAI2
- bool "SAI2"
+config STM32F7_IO_CONFIG_V
+ bool
default n
- select STM32F7_SAI
-config STM32F7_SDMMC1
- bool "SDMMC1"
+config STM32F7_IO_CONFIG_I
+ bool
default n
- select ARCH_HAVE_SDIO
-config STM32F7_SPDIFRX
- bool "SPDIFRX"
+config STM32F7_IO_CONFIG_Z
+ bool
default n
-config STM32F7_SPI1
- bool "SPI1"
+config STM32F7_IO_CONFIG_N
+ bool
default n
- select SPI
- select STM32F7_SPI
-config STM32F7_SPI2
- bool "SPI2"
+config STM32F7_IO_CONFIG_B
+ bool
default n
- select SPI
- select STM32F7_SPI
-config STM32F7_SPI3
- bool "SPI3"
+config STM32F7_IO_CONFIG_A
+ bool
default n
- select SPI
- select STM32F7_SPI
-config STM32F7_SPI4
- bool "SPI4"
+config STM32F7_STM32F745XX
+ bool
default n
- select SPI
- select STM32F7_SPI
+ select STM32F7_STM32F74XX
+ select ARCH_HAVE_FPU
+ select ARMV7M_HAVE_ICACHE
+ select ARMV7M_HAVE_DCACHE
+ select ARMV7M_HAVE_ITCM
+ select ARMV7M_HAVE_DTCM
+ select STM32F7_HAVE_FSMC
+ select STM32F7_HAVE_ETHRNET
+ select STM32F7_HAVE_RNG
+ select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_DCMI
+ select STM32F7_HAVE_DMA2D
+
+config STM32F7_STM32F746XX
+ bool
+ default n
+ select STM32F7_STM32F74XX
+ select ARCH_HAVE_FPU
+ select ARMV7M_HAVE_ICACHE
+ select ARMV7M_HAVE_DCACHE
+ select ARMV7M_HAVE_ITCM
+ select ARMV7M_HAVE_DTCM
+ select STM32F7_HAVE_FSMC
+ select STM32F7_HAVE_ETHRNET
+ select STM32F7_HAVE_RNG
+ select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_DCMI
+ select STM32F7_HAVE_LTDC
+ select STM32F7_HAVE_DMA2D
-config STM32F7_SPI5
- bool "SPI5"
+config STM32F7_STM32F756XX
+ bool
default n
- select SPI
- select STM32F7_SPI
+ select STM32F7_STM32F75XX
+ select ARCH_HAVE_FPU
+ select ARMV7M_HAVE_ICACHE
+ select ARMV7M_HAVE_DCACHE
+ select ARMV7M_HAVE_ITCM
+ select ARMV7M_HAVE_DTCM
+ select STM32F7_HAVE_FSMC
+ select STM32F7_HAVE_ETHRNET
+ select STM32F7_HAVE_RNG
+ select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_LTDC
+ select STM32F7_HAVE_DMA2D
+ select STM32F7_HAVE_CRYP
+ select STM32F7_HAVE_HASH
-config STM32F7_SPI6
- bool "SPI6"
+config STM32F7_STM32F765XX
+ bool
default n
- select SPI
- select STM32F7_SPI
+ select STM32F7_STM32F76XX
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_DPFPU
+ select ARMV7M_HAVE_ICACHE
+ select ARMV7M_HAVE_DCACHE
+ select ARMV7M_HAVE_ITCM
+ select ARMV7M_HAVE_DTCM
+ select STM32F7_HAVE_FSMC
+ select STM32F7_HAVE_ETHRNET
+ select STM32F7_HAVE_RNG # data sheet says yes, Product matix says no
+ select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_CAN3
+ select STM32F7_HAVE_DCMI
+ select STM32F7_HAVE_DMA2D
+ select STM32F7_HAVE_DFSDM1
+
+config STM32F7_STM32F767XX
+ bool
+ default n
+ select STM32F7_STM32F76XX
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_DPFPU
+ select ARMV7M_HAVE_ICACHE
+ select ARMV7M_HAVE_DCACHE
+ select ARMV7M_HAVE_ITCM
+ select ARMV7M_HAVE_DTCM
+ select STM32F7_HAVE_FSMC
+ select STM32F7_HAVE_ETHRNET
+ select STM32F7_HAVE_RNG
+ select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_CAN3
+ select STM32F7_HAVE_DCMI
+ select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z)
+ select STM32F7_HAVE_LTDC
+ select STM32F7_HAVE_DMA2D
+ select STM32F7_HAVE_JPEG
+ select STM32F7_HAVE_DFSDM1
-config STM32F7_TIM1
- bool "TIM1"
+config STM32F7_STM32F768XX # Revisit Wehn parts released
+ bool
default n
+ select STM32F7_STM32F76XX
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_DPFPU
+ select ARMV7M_HAVE_ICACHE
+ select ARMV7M_HAVE_DCACHE
+ select ARMV7M_HAVE_ITCM
+ select ARMV7M_HAVE_DTCM
+ select STM32F7_HAVE_FSMC
+ select STM32F7_HAVE_ETHRNET
+ select STM32F7_HAVE_RNG
+ select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_CAN3
+ select STM32F7_HAVE_DCMI
+ select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z)
+ select STM32F7_HAVE_LTDC
+ select STM32F7_HAVE_DMA2D
+ select STM32F7_HAVE_JPEG
+ select STM32F7_HAVE_DFSDM1
-config STM32F7_TIM2
- bool "TIM2"
+config STM32F7_STM32F768AX # Revisit When parts released
+ bool
default n
+ select STM32F7_STM32F76XX
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_DPFPU
+ select ARMV7M_HAVE_ICACHE
+ select ARMV7M_HAVE_DCACHE
+ select ARMV7M_HAVE_ITCM
+ select ARMV7M_HAVE_DTCM
+ select STM32F7_HAVE_FSMC
+ select STM32F7_HAVE_RNG
+ select STM32F7_HAVE_SPI5
+ select STM32F7_HAVE_SPI6
+ select STM32F7_HAVE_SDMMC2
+ select STM32F7_HAVE_CAN3
+ select STM32F7_HAVE_DCMI
+ select STM32F7_HAVE_DSIHOST
+ select STM32F7_HAVE_LTDC
+ select STM32F7_HAVE_DMA2D
+ select STM32F7_HAVE_JPEG
+ select STM32F7_HAVE_DFSDM1
-config STM32F7_TIM3
- bool "TIM3"
+config STM32F7_STM32F769XX
+ bool
default n
+ select STM32F7_STM32F76XX
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_DPFPU
+ select ARMV7M_HAVE_ICACHE
+ select ARMV7M_HAVE_DCACHE
+ select ARMV7M_HAVE_ITCM
+ select ARMV7M_HAVE_DTCM
+ select STM32F7_HAVE_FSMC
+ select STM32F7_HAVE_ETHRNET
+ select STM32F7_HAVE_RNG
+ select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_CAN3
+ select STM32F7_HAVE_DCMI
+ select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z)
+ select STM32F7_HAVE_LTDC
+ select STM32F7_HAVE_DMA2D
+ select STM32F7_HAVE_JPEG
+ select STM32F7_HAVE_DFSDM1
-config STM32F7_TIM4
- bool "TIM4"
+config STM32F7_STM32F769AX # Revisit When parts released
+ bool
default n
+ select STM32F7_STM32F76XX
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_DPFPU
+ select ARMV7M_HAVE_ICACHE
+ select ARMV7M_HAVE_DCACHE
+ select ARMV7M_HAVE_ITCM
+ select ARMV7M_HAVE_DTCM
+ select STM32F7_HAVE_FSMC
+ select STM32F7_HAVE_RNG
+ select STM32F7_HAVE_SPI5
+ select STM32F7_HAVE_SPI6
+ select STM32F7_HAVE_SDMMC2
+ select STM32F7_HAVE_CAN3
+ select STM32F7_HAVE_DCMI
+ select STM32F7_HAVE_DSIHOST
+ select STM32F7_HAVE_LTDC
+ select STM32F7_HAVE_DMA2D
+ select STM32F7_HAVE_JPEG
+ select STM32F7_HAVE_DFSDM1
-config STM32F7_TIM5
- bool "TIM5"
+config STM32F7_STM32F777XX
+ bool
default n
+ select STM32F7_STM32F77XX
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_DPFPU
+ select ARMV7M_HAVE_ICACHE
+ select ARMV7M_HAVE_DCACHE
+ select ARMV7M_HAVE_ITCM
+ select ARMV7M_HAVE_DTCM
+ select STM32F7_HAVE_FSMC
+ select STM32F7_HAVE_ETHRNET
+ select STM32F7_HAVE_RNG
+ select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_CAN3
+ select STM32F7_HAVE_DCMI
+ select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z)
+ select STM32F7_HAVE_LTDC
+ select STM32F7_HAVE_DMA2D
+ select STM32F7_HAVE_JPEG
+ select STM32F7_HAVE_CRYP
+ select STM32F7_HAVE_HASH
+ select STM32F7_HAVE_DFSDM1
-config STM32F7_TIM6
- bool "TIM6"
+config STM32F7_STM32F778XX # Revisit when parts released
+ bool
default n
+ select STM32F7_STM32F77XX
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_DPFPU
+ select ARMV7M_HAVE_ICACHE
+ select ARMV7M_HAVE_DCACHE
+ select ARMV7M_HAVE_ITCM
+ select ARMV7M_HAVE_DTCM
+ select STM32F7_HAVE_FSMC
+ select STM32F7_HAVE_ETHRNET
+ select STM32F7_HAVE_RNG
+ select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_CAN3
+ select STM32F7_HAVE_DCMI
+ select STM32F7_HAVE_DSIHOST
+ select STM32F7_HAVE_LTDC
+ select STM32F7_HAVE_DMA2D
+ select STM32F7_HAVE_JPEG
+ select STM32F7_HAVE_CRYP
+ select STM32F7_HAVE_HASH
+ select STM32F7_HAVE_DFSDM1
-config STM32F7_TIM7
- bool "TIM7"
+config STM32F7_STM32F778AX
+ bool
default n
+ select STM32F7_STM32F77XX
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_DPFPU
+ select ARMV7M_HAVE_ICACHE
+ select ARMV7M_HAVE_DCACHE
+ select ARMV7M_HAVE_ITCM
+ select ARMV7M_HAVE_DTCM
+ select STM32F7_HAVE_FSMC
+ select STM32F7_HAVE_RNG
+ select STM32F7_HAVE_SPI5
+ select STM32F7_HAVE_SPI6
+ select STM32F7_HAVE_SDMMC2
+ select STM32F7_HAVE_CAN3
+ select STM32F7_HAVE_DCMI
+ select STM32F7_HAVE_DSIHOST
+ select STM32F7_HAVE_LTDC
+ select STM32F7_HAVE_DMA2D
+ select STM32F7_HAVE_JPEG
+ select STM32F7_HAVE_CRYP
+ select STM32F7_HAVE_HASH
+ select STM32F7_HAVE_DFSDM1
-config STM32F7_TIM8
- bool "TIM8"
+config STM32F7_STM32F779XX
+ bool
+ default n
+ select STM32F7_STM32F77XX
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_DPFPU
+ select ARMV7M_HAVE_ICACHE
+ select ARMV7M_HAVE_DCACHE
+ select ARMV7M_HAVE_ITCM
+ select ARMV7M_HAVE_DTCM
+ select STM32F7_HAVE_FSMC
+ select STM32F7_HAVE_ETHRNET
+ select STM32F7_HAVE_RNG
+ select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_CAN3
+ select STM32F7_HAVE_DCMI
+ select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z)
+ select STM32F7_HAVE_LTDC
+ select STM32F7_HAVE_DMA2D
+ select STM32F7_HAVE_JPEG
+ select STM32F7_HAVE_CRYP
+ select STM32F7_HAVE_HASH
+ select STM32F7_HAVE_DFSDM1
+
+config STM32F7_STM32F779AX
+ bool
default n
+ select STM32F7_STM32F77XX
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_DPFPU
+ select ARMV7M_HAVE_ICACHE
+ select ARMV7M_HAVE_DCACHE
+ select ARMV7M_HAVE_ITCM
+ select ARMV7M_HAVE_DTCM
+ select STM32F7_HAVE_FSMC
+ select STM32F7_HAVE_RNG
+ select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V
+ select STM32F7_HAVE_CAN3
+ select STM32F7_HAVE_DCMI
+ select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z)
+ select STM32F7_HAVE_LTDC
+ select STM32F7_HAVE_DMA2D
+ select STM32F7_HAVE_JPEG
+ select STM32F7_HAVE_CRYP
+ select STM32F7_HAVE_HASH
+ select STM32F7_HAVE_DFSDM1
-config STM32F7_TIM9
- bool "TIM9"
+config STM32F7_FLASH_CONFIG_E
+ bool
default n
-config STM32F7_TIM10
- bool "TIM10"
+config STM32F7_FLASH_CONFIG_I
+ bool
default n
-config STM32F7_TIM11
- bool "TIM11"
+config STM32F7_FLASH_CONFIG_I
+ bool
default n
-config STM32F7_TIM12
- bool "TIM12"
+choice
+ prompt "Overrdide Flash Size Designator"
+ depends on ARCH_CHIP_STM32F7
+ default STM32F7_FLASH_OVERRIDE_DEFAULT
+ ---help---
+ STM32F7 series parts numbering (sans the package type) ends with a letter
+ that designates the FLASH size.
+
+ Designator Size in KiB
+ E 512
+ G 1024
+ I 2048
+
+ This configuration option defaults to using the configuration based on that designator
+ or the default smaller size if there is no last character designator is present in the
+ STM32 Chip Selection.
+
+ Examples:
+ If the STM32F745VE is chosen, the Flash configuration would be 'E', if a variant of
+ the part with a 2048 KiB Flash is released in the future one could simply select
+ the 'I' designator here.
+
+ If an STM32F7xxx Series parts is chosen the default Flash configuration will be set
+ herein and can be changed.
+
+config STM32F7_FLASH_OVERRIDE_DEFAULT
+ bool "Default"
+
+config STM32F7_FLASH_OVERRIDE_E
+ bool "E 512KiB"
+
+config STM32F7_FLASH_OVERRIDE_G
+ bool "G 1024KiB"
+
+config STM32F7_FLASH_OVERRIDE_I
+ bool "I 2048KiB"
+
+endchoice # "Overrdide Flash Size Designator"
+
+menu "STM32 Peripheral Support"
+
+# These "hidden" settings determine is a peripheral option is available for the
+# selection MCU
+
+config STM32F7_HAVE_LTDC
+ bool
default n
-config STM32F7_TIM13
- bool "TIM13"
+config STM32F7_HAVE_FSMC
+ bool
default n
-config STM32F7_TIM14
- bool "TIM14"
+
+config STM32F7_HAVE_ETHRNET
+ bool
default n
-config STM32F7_TIM15
- bool "TIM15"
+config STM32F7_HAVE_RNG
+ bool
default n
-config STM32F7_USART1
- bool "USART1"
+config STM32F7_HAVE_SPI5
+ bool
default n
- select USART1_SERIALDRIVER
- select ARCH_HAVE_SERIAL_TERMIOS
- select STM32F7_USART
-config STM32F7_USART2
- bool "USART2"
+config STM32F7_HAVE_SPI6
+ bool
default n
- select USART2_SERIALDRIVER
- select ARCH_HAVE_SERIAL_TERMIOS
- select STM32F7_USART
-config STM32F7_USART3
- bool "USART3"
+config STM32F7_HAVE_SDMMC2
+ bool
default n
- select ARCH_HAVE_SERIAL_TERMIOS
- select USART3_SERIALDRIVER
- select STM32F7_USART
-config STM32F7_UART4
- bool "UART4"
+config STM32F7_HAVE_ADC1_DMA
+ bool
default n
- select ARCH_HAVE_SERIAL_TERMIOS
- select UART4_SERIALDRIVER
- select STM32F7_USART
-config STM32F7_UART5
- bool "UART5"
+config STM32F7_HAVE_ADC2_DMA
+ bool
default n
- select ARCH_HAVE_SERIAL_TERMIOS
- select UART5_SERIALDRIVER
- select STM32F7_USART
-config STM32F7_USART6
- bool "USART6"
+config STM32F7_HAVE_ADC3_DMA
+ bool
default n
- select ARCH_HAVE_SERIAL_TERMIOS
- select USART6_SERIALDRIVER
- select STM32F7_USART
-config STM32F7_UART7
- bool "UART7"
- default n
- select ARCH_HAVE_SERIAL_TERMIOS
- select UART7_SERIALDRIVER
- select STM32F7_USART
-config STM32F7_UART8
- bool "UART8"
+config STM32F7_HAVE_CAN3
+ bool
+ default n
+
+config STM32F7_HAVE_DCMI
+ bool
+ default n
+
+config STM32F7_HAVE_DSIHOST
+ bool
+ default n
+
+config STM32F7_HAVE_LTDC
+ bool
+ default n
+
+config STM32F7_HAVE_DMA2D
+ bool
+ default n
+
+config STM32F7_HAVE_JPEG
+ bool
+ default n
+
+config STM32F7_HAVE_CRYP
+ bool
+ default n
+
+config STM32F7_HAVE_HASH
+ bool
+ default n
+
+config STM32F7_HAVE_DFSDM1
+ bool
+ default n
+
+# These "hidden" settings are the OR of individual peripheral selections
+# indicating that the general capabilitiy is required.
+
+config STM32F7_ADC
+ bool
+ default n
+
+config STM32F7_CAN
+ bool
+ default n
+
+config STM32F7_DAC
+ bool
+ default n
+
+config STM32F7_DMA
+ bool
+ default n
+
+config STM32F7_I2C
+ bool
+ default n
+
+config STM32F7_SAI
+ bool
+ default n
+
+config STM32F7_SPI
+ bool
+ default n
+
+config STM32F7_TIM
+ bool
+ default n
+
+config STM32F7_USART
+ bool
+ default n
+
+# These are the peripheral selections proper
+
+
+config STM32F7_ADC1
+ bool "ADC1"
+ default n
+ select STM32F7_ADC
+ select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA1
+ select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA2
+
+config STM32F7_ADC2
+ bool "ADC2"
+ default n
+ select STM32F7_ADC
+ select STM32F7_HAVE_ADC2_DMA if STM32F7_DMA2
+
+config STM32F7_ADC3
+ bool "ADC3"
+ default n
+ select STM32F7_ADC
+ select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA1
+ select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA2
+
+config STM32F7_BKPSRAM
+ bool "Enable BKP RAM Domain"
+ default n
+
+config STM32F7_CAN1
+ bool "CAN1"
+ default n
+ select CAN
+ select STM32F7_CAN
+
+config STM32F7_CAN2
+ bool "CAN2"
+ default n
+ select CAN
+ select STM32F7_CAN
+
+config STM32F7_CAN3
+ bool "CAN3"
+ default n
+ select CAN
+ select STM32F7_CAN
+ depends on STM32F7_HAVE_CAN3
+
+config STM32F7_CEC
+ bool "CEC"
+ default n
+ depends on STM32F7_VALUELINE
+
+config STM32F7_CRC
+ bool "CRC"
+ default n
+
+config STM32F7_CRYP
+ bool "CRYP"
+ depends on STM32F7_HAVE_CRYP
+ default n
+
+config STM32F7_DFSDM1
+ bool "DFSDM1"
+ default n
+ depends on STM32F7_HAVE_DFSDM1
+ select ARCH_HAVE_DFSDM1
+
+config STM32F7_DMA1
+ bool "DMA1"
+ default n
+ select STM32F7_DMA
+ select ARCH_DMA
+
+config STM32F7_DMA2
+ bool "DMA2"
+ default n
+ select STM32F7_DMA
+ select ARCH_DMA
+
+config STM32F7_DAC1
+ bool "DAC1"
+ default n
+ select STM32F7_DAC
+
+config STM32F7_DAC2
+ bool "DAC2"
+ default n
+ select STM32F7_DAC
+
+config STM32F7_DCMI
+ bool "DCMI"
+ default n
+ depends on STM32F7_HAVE_DCMI
+ ---help---
+ The devices embed a camera interface that can connect with camera
+ modules and CMOS sensors through an 8-bit to 14-bit parallel interface,
+ to receive video data.
+
+config STM32F7_DSIHOST
+ bool "DSIHOST"
+ default n
+ depends on STM32F7_HAVE_DSIHOST
+ ---help---
+ The DSI Host is a dedicated peripheral for interfacing with MIPI® DSI
+ compliant displays.
+
+config STM32F7_DMA2D
+ bool "DMA2D"
+ default n
+ depends on STM32F7_HAVE_DMA2D
+ ---help---
+ The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation
+ available on the STM32 F7 devices.
+
+config STM32F7_JPEG
+ bool "JPEG"
+ default n
+ depends on STM32F7_HAVE_JPEG
+ ---help---
+ The JPEG codec provides an fast and simple hardware compressor and
+ decompressor of JPEG images with full management of JPEG headers.
+
+config STM32F7_ETHMAC
+ bool "Ethernet MAC"
+ default n
+ depends on STM32F7_HAVE_ETHRNET
+ select NETDEVICES
+ select ARCH_HAVE_PHY
+
+config STM32F7_FSMC
+ bool "FSMC"
+ depends on STM32F7_HAVE_FSMC
+ default n
+
+config STM32F7_HASH
+ bool "HASH"
+ default n
+ depends on STM32F7_HAVE_HASH
+ select ARCH_HAVE_HASH
+
+config STM32F7_CEC
+ bool "HDMI-CEC"
+ default n
+
+config STM32F7_I2C1
+ bool "I2C1"
+ default n
+ select STM32F7_I2C
+
+config STM32F7_I2C2
+ bool "I2C2"
+ default n
+ select STM32F7_I2C
+
+config STM32F7_I2C3
+ bool "I2C3"
+ default n
+ select STM32F7_I2C
+
+config STM32F7_I2C4
+ bool "I2C4"
+ default n
+ select STM32F7_I2C
+
+config STM32F7_LPTIM1
+ bool "Low-power timer 1"
+ default n
+
+config STM32F7_LTDC
+ bool "LTDC"
+ default n
+ depends on STM32F7_HAVE_LTDC
+ ---help---
+ The STM32 LTDC is an LCD-TFT Display Controller available on
+ the STM32F429 and STM32F439 devices. It is a standard parallel
+ video interface (HSYNC, VSYNC, etc.) for controlling TFT
+ LCD displays.
+
+config STM32F7_OTGFS
+ bool "OTG FS"
+ default n
+ select USBHOST_HAVE_ASYNCH if USBHOST
+
+config STM32F7_OTGHS
+ bool "OTG HS"
+ default n
+ select USBHOST_HAVE_ASYNCH if USBHOST
+
+config STM32F7_QUADSPI
+ bool "QuadSPI"
+ default n
+
+config STM32F7_RNG
+ bool "RNG"
+ default n
+ depends on STM32F7_HAVE_RNG
+ select ARCH_HAVE_RNG
+
+config STM32F7_SAI1
+ bool "SAI1"
+ default n
+ select STM32F7_SAI
+
+config STM32F7_SAI2
+ bool "SAI2"
+ default n
+ select STM32F7_SAI
+
+config STM32F7_SDMMC1
+ bool "SDMMC1"
+ default n
+ select ARCH_HAVE_SDIO
+
+config STM32F7_SDMMC2
+ bool "SDMMC2"
+ default n
+ depends on STM32F7_HAVE_SDMMC2
+ select ARCH_HAVE_SDIO
+
+config STM32F7_SPDIFRX
+ bool "SPDIFRX"
+ default n
+
+config STM32F7_SPI1
+ bool "SPI1"
+ default n
+ select SPI
+ select STM32F7_SPI
+
+config STM32F7_SPI2
+ bool "SPI2"
+ default n
+ select SPI
+ select STM32F7_SPI
+
+config STM32F7_SPI3
+ bool "SPI3"
+ default n
+ select SPI
+ select STM32F7_SPI
+
+config STM32F7_SPI4
+ bool "SPI4"
+ default n
+ select SPI
+ select STM32F7_SPI
+
+config STM32F7_SPI5
+ bool "SPI5"
+ default n
+ depends on STM32F7_HAVE_SPI5
+ select SPI
+ select STM32F7_SPI
+
+config STM32F7_SPI6
+ bool "SPI6"
+ default n
+ depends on STM32F7_HAVE_SPI6
+ select SPI
+ select STM32F7_SPI
+
+config STM32F7_TIM1
+ bool "TIM1"
+ default n
+ select STM32F7_TIM
+
+config STM32F7_TIM2
+ bool "TIM2"
+ default n
+ select STM32F7_TIM
+
+config STM32F7_TIM3
+ bool "TIM3"
+ default n
+ select STM32F7_TIM
+
+config STM32F7_TIM4
+ bool "TIM4"
+ default n
+ select STM32F7_TIM
+
+config STM32F7_TIM5
+ bool "TIM5"
+ default n
+ select STM32F7_TIM
+
+config STM32F7_TIM6
+ bool "TIM6"
+ default n
+ select STM32F7_TIM
+
+config STM32F7_TIM7
+ bool "TIM7"
+ default n
+ select STM32F7_TIM
+
+config STM32F7_TIM8
+ bool "TIM8"
+ default n
+ select STM32F7_TIM
+
+config STM32F7_TIM9
+ bool "TIM9"
+ default n
+ select STM32F7_TIM
+
+config STM32F7_TIM10
+ bool "TIM10"
+ default n
+ select STM32F7_TIM
+
+config STM32F7_TIM11
+ bool "TIM11"
+ default n
+ select STM32F7_TIM
+
+config STM32F7_TIM12
+ bool "TIM12"
+ default n
+ select STM32F7_TIM
+
+config STM32F7_TIM13
+ bool "TIM13"
+ default n
+ select STM32F7_TIM
+
+config STM32F7_TIM14
+ bool "TIM14"
+ default n
+ select STM32F7_TIM
+
+config STM32F7_USART1
+ bool "USART1"
+ default n
+ select USART1_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
+ select STM32F7_USART
+
+config STM32F7_USART2
+ bool "USART2"
+ default n
+ select USART2_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
+ select STM32F7_USART
+
+config STM32F7_USART3
+ bool "USART3"
+ default n
+ select ARCH_HAVE_SERIAL_TERMIOS
+ select USART3_SERIALDRIVER
+ select STM32F7_USART
+
+config STM32F7_UART4
+ bool "UART4"
+ default n
+ select ARCH_HAVE_SERIAL_TERMIOS
+ select UART4_SERIALDRIVER
+ select STM32F7_USART
+
+config STM32F7_UART5
+ bool "UART5"
+ default n
+ select ARCH_HAVE_SERIAL_TERMIOS
+ select UART5_SERIALDRIVER
+ select STM32F7_USART
+
+config STM32F7_USART6
+ bool "USART6"
+ default n
+ select ARCH_HAVE_SERIAL_TERMIOS
+ select USART6_SERIALDRIVER
+ select STM32F7_USART
+
+config STM32F7_UART7
+ bool "UART7"
+ default n
+ select ARCH_HAVE_SERIAL_TERMIOS
+ select UART7_SERIALDRIVER
+ select STM32F7_USART
+
+config STM32F7_UART8
+ bool "UART8"
+ default n
+ select ARCH_HAVE_SERIAL_TERMIOS
+ select UART8_SERIALDRIVER
+ select STM32F7_USART
+
+config STM32F7_IWDG
+ bool "IWDG"
+ default n
+ select WATCHDOG
+
+config STM32F7_WWDG
+ bool "WWDG"
+ default n
+ select WATCHDOG
+
+endmenu
+
+menu "U[S]ART Configuration"
+ depends on STM32F7_USART
+
+config USART1_RS485
+ bool "RS-485 on USART1"
+ default n
+ depends on STM32F7_USART1
+ ---help---
+ Enable RS-485 interface on USART1. Your board config will have to
+ provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be
+ used with USART1_RXDMA.
+
+config USART1_RS485_DIR_POLARITY
+ int "USART1 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on USART1_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config USART1_RXDMA
+ bool "USART1 Rx DMA"
+ default n
+ depends on STM32F7_USART1 && STM32F7_DMA1
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config USART2_RS485
+ bool "RS-485 on USART2"
+ default n
+ depends on STM32F7_USART2
+ ---help---
+ Enable RS-485 interface on USART2. Your board config will have to
+ provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be
+ used with USART2_RXDMA.
+
+config USART2_RS485_DIR_POLARITY
+ int "USART2 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on USART2_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config USART2_RXDMA
+ bool "USART2 Rx DMA"
+ default n
+ depends on STM32F7_USART2 && STM32F7_DMA1
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config USART3_RS485
+ bool "RS-485 on USART3"
+ default n
+ depends on STM32F7_USART3
+ ---help---
+ Enable RS-485 interface on USART3. Your board config will have to
+ provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be
+ used with USART3_RXDMA.
+
+config USART3_RS485_DIR_POLARITY
+ int "USART3 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on USART3_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config USART3_RXDMA
+ bool "USART3 Rx DMA"
+ default n
+ depends on STM32F7_USART3 && STM32F7_DMA1
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config UART4_RS485
+ bool "RS-485 on UART4"
+ default n
+ depends on STM32F7_UART4
+ ---help---
+ Enable RS-485 interface on UART4. Your board config will have to
+ provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be
+ used with UART4_RXDMA.
+
+config UART4_RS485_DIR_POLARITY
+ int "UART4 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on UART4_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config UART4_RXDMA
+ bool "UART4 Rx DMA"
+ default n
+ depends on STM32F7_UART4 && STM32F7_DMA1
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config UART5_RS485
+ bool "RS-485 on UART5"
+ default n
+ depends on STM32F7_UART5
+ ---help---
+ Enable RS-485 interface on UART5. Your board config will have to
+ provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be
+ used with UART5_RXDMA.
+
+config UART5_RS485_DIR_POLARITY
+ int "UART5 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on UART5_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config UART5_RXDMA
+ bool "UART5 Rx DMA"
+ default n
+ depends on STM32F7_UART5 && STM32F7_DMA1
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config USART6_RS485
+ bool "RS-485 on USART6"
+ default n
+ depends on STM32F7_USART6
+ ---help---
+ Enable RS-485 interface on USART6. Your board config will have to
+ provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be
+ used with USART6_RXDMA.
+
+config USART6_RS485_DIR_POLARITY
+ int "USART6 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on USART6_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config USART6_RXDMA
+ bool "USART6 Rx DMA"
+ default n
+ depends on STM32F7_USART6 && STM32F7_DMA2
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config UART7_RS485
+ bool "RS-485 on UART7"
+ default n
+ depends on STM32F7_UART7
+ ---help---
+ Enable RS-485 interface on UART7. Your board config will have to
+ provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be
+ used with UART7_RXDMA.
+
+config UART7_RS485_DIR_POLARITY
+ int "UART7 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on UART7_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config UART7_RXDMA
+ bool "UART7 Rx DMA"
+ default n
+ depends on STM32F7_UART7 && STM32F7_DMA2
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config UART8_RS485
+ bool "RS-485 on UART8"
+ default n
+ depends on STM32F7_UART8
+ ---help---
+ Enable RS-485 interface on UART8. Your board config will have to
+ provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be
+ used with UART8_RXDMA.
+
+config UART8_RS485_DIR_POLARITY
+ int "UART8 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on UART8_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config UART8_RXDMA
+ bool "UART8 Rx DMA"
+ default n
+ depends on STM32F7_UART8 && STM32F7_DMA2
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config SERIAL_DISABLE_REORDERING
+ bool "Disable reordering of ttySx devices."
+ depends on STM32F7_USART1 || STM32F7_USART2 || STM32F7_USART3 || STM32F7_UART4 || STM32F7_UART5 || STM32F7_USART6 || STM32F7_UART7 || STM32F7_UART8
+ default n
+ ---help---
+ NuttX per default reorders the serial ports (/dev/ttySx) so that the
+ console is always on /dev/ttyS0. If more than one UART is in use this
+ can, however, have the side-effect that all port mappings
+ (hardware USART1 -> /dev/ttyS0) change if the console is moved to another
+ UART. This is in particular relevant if a project uses the USB console
+ in some configs and a serial console in other configs, but does not
+ want the side effect of having all serial port names change when just
+ the console is moved from serial to USB.
+
+config STM32F7_FLOWCONTROL_BROKEN
+ bool "Use Software UART RTS flow control"
+ depends on STM32F7_USART
+ default n
+ ---help---
+ Enable UART RTS flow control using Software. Because STM
+ Current STM32 have broken HW based RTS behavior (they assert
+ nRTS after every byte received) Enable this setting workaround
+ this issue by useing software based management of RTS
+
+config STM32F7_USART_BREAKS
+ bool "Add TIOxSBRK to support sending Breaks"
+ depends on STM32F7_USART
+ default n
+ ---help---
+ Add TIOCxBRK routines to send a line break per the STM32 manual, the
+ break will be a pulse based on the value M. This is not a BSD compatible
+ break.
+
+config STM32F7_SERIALBRK_BSDCOMPAT
+ bool "Use GPIO To send Break"
+ depends on STM32F7_USART && STM32F7_USART_BREAKS
+ default n
+ ---help---
+ Enable using GPIO on the TX pin to send a BSD compatible break:
+ TIOCSBRK will start the break and TIOCCBRK will end the break.
+ The current STM32 U[S]ARTS have no way to leave the break (TX=LOW)
+ on because the SW starts the break and then the HW automatically clears
+ the break. This makes it is difficult to sent a long break.
+
+endmenu # U[S]ART Configuration
+
+menu "SPI Configuration"
+ depends on STM32F7_SPI
+
+config STM32F7_SPI_INTERRUPTS
+ bool "Interrupt driver SPI"
+ default n
+ ---help---
+ Select to enable interrupt driven SPI support. Non-interrupt-driven,
+ poll-waiting is recommended if the interrupt rate would be to high in
+ the interrupt driven case.
+
+config STM32F7_SPI_DMA
+ bool "SPI DMA"
+ default n
+ ---help---
+ Use DMA to improve SPI transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT.
+
+endmenu # "SPI Configuration"
+
+menu "I2C Configuration"
+ depends on STM32F7_I2C
+
+config STM32F7_I2C_DYNTIMEO
+ bool "Use dynamic timeouts"
+ default n
+ depends on STM32F7_I2C
+
+config STM32F7_I2C_DYNTIMEO_USECPERBYTE
+ int "Timeout Microseconds per Byte"
+ default 500
+ depends on STM32F7_I2C_DYNTIMEO
+
+config STM32F7_I2C_DYNTIMEO_STARTSTOP
+ int "Timeout for Start/Stop (Milliseconds)"
+ default 1000
+ depends on STM32F7_I2C_DYNTIMEO
+
+config STM32F7_I2CTIMEOSEC
+ int "Timeout seconds"
+ default 0
+ depends on STM32F7_I2C
+
+config STM32F7_I2CTIMEOMS
+ int "Timeout Milliseconds"
+ default 500
+ depends on STM32F7_I2C && !STM32F7_I2C_DYNTIMEO
+
+config STM32F7_I2CTIMEOTICKS
+ int "Timeout for Done and Stop (ticks)"
+ default 500
+ depends on STM32F7_I2C && !STM32F7_I2C_DYNTIMEO
+
+config STM32F7_I2C_DUTY16_9
+ bool "Frequency with Tlow/Thigh = 16/9 "
+ default n
+ depends on STM32F7_I2C
+
+endmenu # "I2C Configuration"
+
+config STM32F7_CUSTOM_CLOCKCONFIG
+ bool "Custom clock configuration"
+ default n
+ ---help---
+ Enables special, board-specific STM32 clock configuration.
+
+config STM32F7_DTCM_PROCFS
+ bool "DTCM SRAM PROCFS support"
+ default n
+ depends on ARMV7M_DTCM && FS_PROCFS
+ ---help---
+ Select to build in support for /proc/dtcm. Reading from /proc/dtcm
+ will provide statistics about DTCM memory use similar to what you
+ would get from mallinfo() for the user heap.
+
+config STM32F7_DMACAPABLE
+ bool "Workaround non-DMA capable memory"
+ depends on ARCH_DMA
+ default y if !STM32F7_CCMEXCLUDE
+ default n if STM32F7_CCMEXCLUDE
+ ---help---
+ This option enables the DMA interface stm32_dmacapable that can be
+ used to check if it is possible to do DMA from the selected address.
+ Drivers then may use this information to determine if they should
+ attempt the DMA or fall back to a different transfer method.
+
+menu "Timer Configuration"
+
+config STM32F7_TIM1_PWM
+ bool "TIM1 PWM"
+ default n
+ depends on STM32F7_TIM1
+ select ARCH_HAVE_PWM_PULSECOUNT
+ ---help---
+ Reserve timer 1 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If STM32F7_TIM1
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM1_PWM
+
+config STM32F7_TIM1_MODE
+ int "TIM1 Mode"
+ default 0
+ range 0 4
+ ---help---
+ Specifies the timer mode.
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM1_CHANNEL1
+ bool "TIM1 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if STM32F7_TIM1_CHANNEL1
+
+config STM32F7_TIM1_CH1MODE
+ int "TIM1 Channel 1 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM1_CH1OUT
+ bool "TIM1 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # STM32F7_TIM1_CHANNEL1
+
+config STM32F7_TIM1_CHANNEL2
+ bool "TIM1 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if STM32F7_TIM1_CHANNEL2
+
+config STM32F7_TIM1_CH2MODE
+ int "TIM1 Channel 2 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM1_CH2OUT
+ bool "TIM1 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # STM32F7_TIM1_CHANNEL2
+
+config STM32F7_TIM1_CHANNEL3
+ bool "TIM1 Channel 3"
+ default n
+ ---help---
+ Enables channel 3.
+
+if STM32F7_TIM1_CHANNEL3
+
+config STM32F7_TIM1_CH3MODE
+ int "TIM1 Channel 3 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM1_CH3OUT
+ bool "TIM1 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # STM32F7_TIM1_CHANNEL3
+
+config STM32F7_TIM1_CHANNEL4
+ bool "TIM1 Channel 4"
+ default n
+ ---help---
+ Enables channel 4.
+
+if STM32F7_TIM1_CHANNEL4
+
+config STM32F7_TIM1_CH4MODE
+ int "TIM1 Channel 4 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM1_CH4OUT
+ bool "TIM1 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # STM32F7_TIM1_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM1_CHANNEL
+ int "TIM1 PWM Output Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM1 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,..,4}
+
+config STM32F7_TIM1_CHMODE
+ int "TIM1 Channel Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM1_PWM
+
+config STM32F7_TIM2_PWM
+ bool "TIM2 PWM"
+ default n
+ depends on STM32F7_TIM2
+ select ARCH_HAVE_PWM_PULSECOUNT
+ ---help---
+ Reserve timer 2 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If STM32F7_TIM2
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM2_PWM
+
+config STM32F7_TIM2_MODE
+ int "TIM2 Mode"
+ default 0
+ range 0 4
+ ---help---
+ Specifies the timer mode.
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM2_CHANNEL1
+ bool "TIM2 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if STM32F7_TIM2_CHANNEL1
+
+config STM32F7_TIM2_CH1MODE
+ int "TIM2 Channel 1 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM2_CH1OUT
+ bool "TIM2 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # STM32F7_TIM2_CHANNEL1
+
+config STM32F7_TIM2_CHANNEL2
+ bool "TIM2 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if STM32F7_TIM2_CHANNEL2
+
+config STM32F7_TIM2_CH2MODE
+ int "TIM2 Channel 2 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM2_CH2OUT
+ bool "TIM2 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # STM32F7_TIM2_CHANNEL2
+
+config STM32F7_TIM2_CHANNEL3
+ bool "TIM2 Channel 3"
+ default n
+ ---help---
+ Enables channel 3.
+
+if STM32F7_TIM2_CHANNEL3
+
+config STM32F7_TIM2_CH3MODE
+ int "TIM2 Channel 3 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM2_CH3OUT
+ bool "TIM2 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # STM32F7_TIM2_CHANNEL3
+
+config STM32F7_TIM2_CHANNEL4
+ bool "TIM2 Channel 4"
+ default n
+ ---help---
+ Enables channel 4.
+
+if STM32F7_TIM2_CHANNEL4
+
+config STM32F7_TIM2_CH4MODE
+ int "TIM2 Channel 4 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM2_CH4OUT
+ bool "TIM2 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # STM32F7_TIM2_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM2_CHANNEL
+ int "TIM2 PWM Output Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM2 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,..,4}
+
+config STM32F7_TIM2_CHMODE
+ int "TIM2 Channel Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM2_PWM
+
+config STM32F7_TIM3_PWM
+ bool "TIM3 PWM"
+ default n
+ depends on STM32F7_TIM3
+ select ARCH_HAVE_PWM_PULSECOUNT
+ ---help---
+ Reserve timer 3 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If STM32F7_TIM3
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM3_PWM
+
+config STM32F7_TIM3_MODE
+ int "TIM3 Mode"
+ default 0
+ range 0 4
+ ---help---
+ Specifies the timer mode.
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM3_CHANNEL1
+ bool "TIM3 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if STM32F7_TIM3_CHANNEL1
+
+config STM32F7_TIM3_CH1MODE
+ int "TIM3 Channel 1 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM3_CH1OUT
+ bool "TIM3 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # STM32F7_TIM3_CHANNEL1
+
+config STM32F7_TIM3_CHANNEL2
+ bool "TIM3 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if STM32F7_TIM3_CHANNEL2
+
+config STM32F7_TIM3_CH2MODE
+ int "TIM3 Channel 2 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM3_CH2OUT
+ bool "TIM3 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # STM32F7_TIM3_CHANNEL2
+
+config STM32F7_TIM3_CHANNEL3
+ bool "TIM3 Channel 3"
+ default n
+ ---help---
+ Enables channel 3.
+
+if STM32F7_TIM3_CHANNEL3
+
+config STM32F7_TIM3_CH3MODE
+ int "TIM3 Channel 3 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM3_CH3OUT
+ bool "TIM3 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # STM32F7_TIM3_CHANNEL3
+
+config STM32F7_TIM3_CHANNEL4
+ bool "TIM3 Channel 4"
+ default n
+ ---help---
+ Enables channel 4.
+
+if STM32F7_TIM3_CHANNEL4
+
+config STM32F7_TIM3_CH4MODE
+ int "TIM3 Channel 4 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM3_CH4OUT
+ bool "TIM3 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # STM32F7_TIM3_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM3_CHANNEL
+ int "TIM3 PWM Output Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM3 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,..,4}
+
+config STM32F7_TIM3_CHMODE
+ int "TIM3 Channel Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM3_PWM
+
+config STM32F7_TIM4_PWM
+ bool "TIM4 PWM"
+ default n
+ depends on STM32F7_TIM4
+ select ARCH_HAVE_PWM_PULSECOUNT
+ ---help---
+ Reserve timer 4 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If STM32F7_TIM4
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM4_PWM
+
+config STM32F7_TIM4_MODE
+ int "TIM4 Mode"
+ default 0
+ range 0 4
+ ---help---
+ Specifies the timer mode.
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM4_CHANNEL1
+ bool "TIM4 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if STM32F7_TIM4_CHANNEL1
+
+config STM32F7_TIM4_CH1MODE
+ int "TIM4 Channel 1 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM4_CH1OUT
+ bool "TIM4 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # STM32F7_TIM4_CHANNEL1
+
+config STM32F7_TIM4_CHANNEL2
+ bool "TIM4 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if STM32F7_TIM4_CHANNEL2
+
+config STM32F7_TIM4_CH2MODE
+ int "TIM4 Channel 2 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM4_CH2OUT
+ bool "TIM4 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # STM32F7_TIM4_CHANNEL2
+
+config STM32F7_TIM4_CHANNEL3
+ bool "TIM4 Channel 3"
+ default n
+ ---help---
+ Enables channel 3.
+
+if STM32F7_TIM4_CHANNEL3
+
+config STM32F7_TIM4_CH3MODE
+ int "TIM4 Channel 3 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM4_CH3OUT
+ bool "TIM4 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # STM32F7_TIM4_CHANNEL3
+
+config STM32F7_TIM4_CHANNEL4
+ bool "TIM4 Channel 4"
+ default n
+ ---help---
+ Enables channel 4.
+
+if STM32F7_TIM4_CHANNEL4
+
+config STM32F7_TIM4_CH4MODE
+ int "TIM4 Channel 4 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM4_CH4OUT
+ bool "TIM4 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # STM32F7_TIM4_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM4_CHANNEL
+ int "TIM4 PWM Output Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM4 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,..,4}
+
+config STM32F7_TIM4_CHMODE
+ int "TIM4 Channel Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM4_PWM
+
+config STM32F7_TIM5_PWM
+ bool "TIM5 PWM"
+ default n
+ depends on STM32F7_TIM5
+ select ARCH_HAVE_PWM_PULSECOUNT
+ ---help---
+ Reserve timer 5 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If STM32F7_TIM5
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM5_PWM
+
+config STM32F7_TIM5_MODE
+ int "TIM5 Mode"
+ default 0
+ range 0 4
+ ---help---
+ Specifies the timer mode.
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM5_CHANNEL1
+ bool "TIM5 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if STM32F7_TIM5_CHANNEL1
+
+config STM32F7_TIM5_CH1MODE
+ int "TIM5 Channel 1 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM5_CH1OUT
+ bool "TIM5 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # STM32F7_TIM5_CHANNEL1
+
+config STM32F7_TIM5_CHANNEL2
+ bool "TIM5 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if STM32F7_TIM5_CHANNEL2
+
+config STM32F7_TIM5_CH2MODE
+ int "TIM5 Channel 2 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM5_CH2OUT
+ bool "TIM5 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # STM32F7_TIM5_CHANNEL2
+
+config STM32F7_TIM5_CHANNEL3
+ bool "TIM5 Channel 3"
+ default n
+ ---help---
+ Enables channel 3.
+
+if STM32F7_TIM5_CHANNEL3
+
+config STM32F7_TIM5_CH3MODE
+ int "TIM5 Channel 3 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM5_CH3OUT
+ bool "TIM5 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # STM32F7_TIM5_CHANNEL3
+
+config STM32F7_TIM5_CHANNEL4
+ bool "TIM5 Channel 4"
+ default n
+ ---help---
+ Enables channel 4.
+
+if STM32F7_TIM5_CHANNEL4
+
+config STM32F7_TIM5_CH4MODE
+ int "TIM5 Channel 4 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM5_CH4OUT
+ bool "TIM5 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # STM32F7_TIM5_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM5_CHANNEL
+ int "TIM5 PWM Output Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM5 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,..,4}
+
+config STM32F7_TIM5_CHMODE
+ int "TIM5 Channel Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM5_PWM
+
+config STM32F7_TIM8_PWM
+ bool "TIM8 PWM"
+ default n
+ depends on STM32F7_TIM8
+ select ARCH_HAVE_PWM_PULSECOUNT
+ ---help---
+ Reserve timer 8 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If STM32F7_TIM8
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM8_PWM
+
+config STM32F7_TIM8_MODE
+ int "TIM8 Mode"
+ default 0
+ range 0 4
+ ---help---
+ Specifies the timer mode.
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM8_CHANNEL1
+ bool "TIM8 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if STM32F7_TIM8_CHANNEL1
+
+config STM32F7_TIM8_CH1MODE
+ int "TIM8 Channel 1 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM8_CH1OUT
+ bool "TIM8 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # STM32F7_TIM8_CHANNEL1
+
+config STM32F7_TIM8_CHANNEL2
+ bool "TIM8 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if STM32F7_TIM8_CHANNEL2
+
+config STM32F7_TIM8_CH2MODE
+ int "TIM8 Channel 2 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM8_CH2OUT
+ bool "TIM8 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # STM32F7_TIM8_CHANNEL2
+
+config STM32F7_TIM8_CHANNEL3
+ bool "TIM8 Channel 3"
+ default n
+ ---help---
+ Enables channel 3.
+
+if STM32F7_TIM8_CHANNEL3
+
+config STM32F7_TIM8_CH3MODE
+ int "TIM8 Channel 3 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM8_CH3OUT
+ bool "TIM8 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # STM32F7_TIM8_CHANNEL3
+
+config STM32F7_TIM8_CHANNEL4
+ bool "TIM8 Channel 4"
+ default n
+ ---help---
+ Enables channel 4.
+
+if STM32F7_TIM8_CHANNEL4
+
+config STM32F7_TIM8_CH4MODE
+ int "TIM8 Channel 4 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM8_CH4OUT
+ bool "TIM8 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # STM32F7_TIM8_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM8_CHANNEL
+ int "TIM8 PWM Output Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM8 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,..,4}
+
+config STM32F7_TIM8_CHMODE
+ int "TIM8 Channel Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM8_PWM
+
+config STM32F7_TIM9_PWM
+ bool "TIM9 PWM"
+ default n
+ depends on STM32F7_TIM9
+ select ARCH_HAVE_PWM_PULSECOUNT
+ ---help---
+ Reserve timer 9 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If STM32F7_TIM9
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM9_PWM
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM9_CHANNEL1
+ bool "TIM9 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if STM32F7_TIM9_CHANNEL1
+
+config STM32F7_TIM9_CH1MODE
+ int "TIM9 Channel 1 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM9_CH1OUT
+ bool "TIM9 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # STM32F7_TIM9_CHANNEL1
+
+config STM32F7_TIM9_CHANNEL2
+ bool "TIM9 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if STM32F7_TIM9_CHANNEL2
+
+config STM32F7_TIM9_CH2MODE
+ int "TIM9 Channel 2 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM9_CH2OUT
+ bool "TIM9 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # STM32F7_TIM9_CHANNEL2
+
+config STM32F7_TIM9_CHANNEL3
+ bool "TIM9 Channel 3"
+ default n
+ ---help---
+ Enables channel 3.
+
+if STM32F7_TIM9_CHANNEL3
+
+config STM32F7_TIM9_CH3MODE
+ int "TIM9 Channel 3 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM9_CH3OUT
+ bool "TIM9 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # STM32F7_TIM9_CHANNEL3
+
+config STM32F7_TIM9_CHANNEL4
+ bool "TIM9 Channel 4"
+ default n
+ ---help---
+ Enables channel 4.
+
+if STM32F7_TIM9_CHANNEL4
+
+config STM32F7_TIM9_CH4MODE
+ int "TIM9 Channel 4 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM9_CH4OUT
+ bool "TIM9 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # STM32F7_TIM9_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM9_CHANNEL
+ int "TIM9 PWM Output Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM9 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,..,4}
+
+config STM32F7_TIM9_CHMODE
+ int "TIM9 Channel Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM9_PWM
+
+config STM32F7_TIM10_PWM
+ bool "TIM10 PWM"
+ default n
+ depends on STM32F7_TIM10
+ select ARCH_HAVE_PWM_PULSECOUNT
+ ---help---
+ Reserve timer 10 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If STM32F7_TIM10
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM10_PWM
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM10_CHANNEL1
+ bool "TIM10 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if STM32F7_TIM10_CHANNEL1
+
+config STM32F7_TIM10_CH1MODE
+ int "TIM10 Channel 1 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM10_CH1OUT
+ bool "TIM10 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # STM32F7_TIM10_CHANNEL1
+
+config STM32F7_TIM10_CHANNEL2
+ bool "TIM10 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if STM32F7_TIM10_CHANNEL2
+
+config STM32F7_TIM10_CH2MODE
+ int "TIM10 Channel 2 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM10_CH2OUT
+ bool "TIM10 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # STM32F7_TIM10_CHANNEL2
+
+config STM32F7_TIM10_CHANNEL3
+ bool "TIM10 Channel 3"
+ default n
+ ---help---
+ Enables channel 3.
+
+if STM32F7_TIM10_CHANNEL3
+
+config STM32F7_TIM10_CH3MODE
+ int "TIM10 Channel 3 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM10_CH3OUT
+ bool "TIM10 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # STM32F7_TIM10_CHANNEL3
+
+config STM32F7_TIM10_CHANNEL4
+ bool "TIM10 Channel 4"
+ default n
+ ---help---
+ Enables channel 4.
+
+if STM32F7_TIM10_CHANNEL4
+
+config STM32F7_TIM10_CH4MODE
+ int "TIM10 Channel 4 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM10_CH4OUT
+ bool "TIM10 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # STM32F7_TIM10_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM10_CHANNEL
+ int "TIM10 PWM Output Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM10 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,..,4}
+
+config STM32F7_TIM10_CHMODE
+ int "TIM10 Channel Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM10_PWM
+
+config STM32F7_TIM11_PWM
+ bool "TIM11 PWM"
+ default n
+ depends on STM32F7_TIM11
+ select ARCH_HAVE_PWM_PULSECOUNT
+ ---help---
+ Reserve timer 11 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If STM32F7_TIM11
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM11_PWM
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM11_CHANNEL1
+ bool "TIM11 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if STM32F7_TIM11_CHANNEL1
+
+config STM32F7_TIM11_CH1MODE
+ int "TIM11 Channel 1 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM11_CH1OUT
+ bool "TIM11 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # STM32F7_TIM11_CHANNEL1
+
+config STM32F7_TIM11_CHANNEL2
+ bool "TIM11 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if STM32F7_TIM11_CHANNEL2
+
+config STM32F7_TIM11_CH2MODE
+ int "TIM11 Channel 2 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM11_CH2OUT
+ bool "TIM11 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # STM32F7_TIM11_CHANNEL2
+
+config STM32F7_TIM11_CHANNEL3
+ bool "TIM11 Channel 3"
+ default n
+ ---help---
+ Enables channel 3.
+
+if STM32F7_TIM11_CHANNEL3
+
+config STM32F7_TIM11_CH3MODE
+ int "TIM11 Channel 3 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM11_CH3OUT
+ bool "TIM11 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # STM32F7_TIM11_CHANNEL3
+
+config STM32F7_TIM11_CHANNEL4
+ bool "TIM11 Channel 4"
+ default n
+ ---help---
+ Enables channel 4.
+
+if STM32F7_TIM11_CHANNEL4
+
+config STM32F7_TIM11_CH4MODE
+ int "TIM11 Channel 4 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM11_CH4OUT
+ bool "TIM11 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # STM32F7_TIM11_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM11_CHANNEL
+ int "TIM11 PWM Output Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM11 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,..,4}
+
+config STM32F7_TIM11_CHMODE
+ int "TIM11 Channel Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM11_PWM
+
+config STM32F7_TIM12_PWM
+ bool "TIM12 PWM"
+ default n
+ depends on STM32F7_TIM12
+ select ARCH_HAVE_PWM_PULSECOUNT
+ ---help---
+ Reserve timer 12 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If STM32F7_TIM12
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM12_PWM
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM12_CHANNEL1
+ bool "TIM12 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if STM32F7_TIM12_CHANNEL1
+
+config STM32F7_TIM12_CH1MODE
+ int "TIM12 Channel 1 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM12_CH1OUT
+ bool "TIM12 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # STM32F7_TIM12_CHANNEL1
+
+config STM32F7_TIM12_CHANNEL2
+ bool "TIM12 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if STM32F7_TIM12_CHANNEL2
+
+config STM32F7_TIM12_CH2MODE
+ int "TIM12 Channel 2 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM12_CH2OUT
+ bool "TIM12 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # STM32F7_TIM12_CHANNEL2
+
+config STM32F7_TIM12_CHANNEL3
+ bool "TIM12 Channel 3"
+ default n
+ ---help---
+ Enables channel 3.
+
+if STM32F7_TIM12_CHANNEL3
+
+config STM32F7_TIM12_CH3MODE
+ int "TIM12 Channel 3 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM12_CH3OUT
+ bool "TIM12 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # STM32F7_TIM12_CHANNEL3
+
+config STM32F7_TIM12_CHANNEL4
+ bool "TIM12 Channel 4"
+ default n
+ ---help---
+ Enables channel 4.
+
+if STM32F7_TIM12_CHANNEL4
+
+config STM32F7_TIM12_CH4MODE
+ int "TIM12 Channel 4 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM12_CH4OUT
+ bool "TIM12 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # STM32F7_TIM12_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM12_CHANNEL
+ int "TIM12 PWM Output Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM12 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,..,4}
+
+config STM32F7_TIM12_CHMODE
+ int "TIM12 Channel Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM12_PWM
+
+config STM32F7_TIM13_PWM
+ bool "TIM13 PWM"
+ default n
+ depends on STM32F7_TIM13
+ select ARCH_HAVE_PWM_PULSECOUNT
+ ---help---
+ Reserve timer 13 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If STM32F7_TIM13
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM13_PWM
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM13_CHANNEL1
+ bool "TIM13 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if STM32F7_TIM13_CHANNEL1
+
+config STM32F7_TIM13_CH1MODE
+ int "TIM13 Channel 1 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM13_CH1OUT
+ bool "TIM13 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # STM32F7_TIM13_CHANNEL1
+
+config STM32F7_TIM13_CHANNEL2
+ bool "TIM13 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if STM32F7_TIM13_CHANNEL2
+
+config STM32F7_TIM13_CH2MODE
+ int "TIM13 Channel 2 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM13_CH2OUT
+ bool "TIM13 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # STM32F7_TIM13_CHANNEL2
+
+config STM32F7_TIM13_CHANNEL3
+ bool "TIM13 Channel 3"
+ default n
+ ---help---
+ Enables channel 3.
+
+if STM32F7_TIM13_CHANNEL3
+
+config STM32F7_TIM13_CH3MODE
+ int "TIM13 Channel 3 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM13_CH3OUT
+ bool "TIM13 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # STM32F7_TIM13_CHANNEL3
+
+config STM32F7_TIM13_CHANNEL4
+ bool "TIM13 Channel 4"
+ default n
+ ---help---
+ Enables channel 4.
+
+if STM32F7_TIM13_CHANNEL4
+
+config STM32F7_TIM13_CH4MODE
+ int "TIM13 Channel 4 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM13_CH4OUT
+ bool "TIM13 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # STM32F7_TIM13_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM13_CHANNEL
+ int "TIM13 PWM Output Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM13 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,..,4}
+
+config STM32F7_TIM13_CHMODE
+ int "TIM13 Channel Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM13_PWM
+
+config STM32F7_TIM14_PWM
+ bool "TIM14 PWM"
+ default n
+ depends on STM32F7_TIM14
+ select ARCH_HAVE_PWM_PULSECOUNT
+ ---help---
+ Reserve timer 14 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If STM32F7_TIM14
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM14_PWM
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM14_CHANNEL1
+ bool "TIM14 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if STM32F7_TIM14_CHANNEL1
+
+config STM32F7_TIM14_CH1MODE
+ int "TIM14 Channel 1 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM14_CH1OUT
+ bool "TIM14 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # STM32F7_TIM14_CHANNEL1
+
+config STM32F7_TIM14_CHANNEL2
+ bool "TIM14 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if STM32F7_TIM14_CHANNEL2
+
+config STM32F7_TIM14_CH2MODE
+ int "TIM14 Channel 2 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM14_CH2OUT
+ bool "TIM14 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # STM32F7_TIM14_CHANNEL2
+
+config STM32F7_TIM14_CHANNEL3
+ bool "TIM14 Channel 3"
+ default n
+ ---help---
+ Enables channel 3.
+
+if STM32F7_TIM14_CHANNEL3
+
+config STM32F7_TIM14_CH3MODE
+ int "TIM14 Channel 3 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM14_CH3OUT
+ bool "TIM14 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # STM32F7_TIM14_CHANNEL3
+
+config STM32F7_TIM14_CHANNEL4
+ bool "TIM14 Channel 4"
+ default n
+ ---help---
+ Enables channel 4.
+
+if STM32F7_TIM14_CHANNEL4
+
+config STM32F7_TIM14_CH4MODE
+ int "TIM14 Channel 4 Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM14_CH4OUT
+ bool "TIM14 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # STM32F7_TIM14_CHANNEL4
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM14_CHANNEL
+ int "TIM14 PWM Output Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM14 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,..,4}
+
+config STM32F7_TIM14_CHMODE
+ int "TIM14 Channel Mode"
+ default 0
+ range 0 5
+ ---help---
+ Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM14_PWM
+
+config STM32F7_TIM15_PWM
+ bool "TIM15 PWM"
+ default n
+ depends on STM32F7_TIM15
+ ---help---
+ Reserve timer 15 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If STM32F7_TIM15
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM15_PWM
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM15_CHANNEL1
+ bool "TIM15 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if STM32F7_TIM15_CHANNEL1
+
+config STM32F7_TIM15_CH1MODE
+ int "TIM15 Channel 1 Mode"
+ default 0
+ range 0 3 if STM32F7_STM32F30XX
+ range 0 1 if !STM32F7_STM32F30XX
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM15_CH1OUT
+ bool "TIM15 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # STM32F7_TIM15_CHANNEL1
+
+config STM32F7_TIM15_CHANNEL2
+ bool "TIM15 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if STM32F7_TIM15_CHANNEL2
+
+config STM32F7_TIM15_CH2MODE
+ int "TIM15 Channel 2 Mode"
+ default 0
+ range 0 3 if STM32F7_STM32F30XX
+ range 0 1 if !STM32F7_STM32F30XX
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM15_CH2OUT
+ bool "TIM15 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # STM32F7_TIM15_CHANNEL2
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM15_CHANNEL
+ int "TIM15 PWM Output Channel"
+ default 1
+ range 1 2
+ ---help---
+ If TIM15 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,2}
+
+config STM32F7_TIM15_CHMODE
+ int "TIM15 Channel Mode"
+ default 0
+ range 0 3 if STM32F7_STM32F30XX
+ range 0 1 if !STM32F7_STM32F30XX
+ ---help---
+ Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM15_PWM
+
+config STM32F7_TIM16_PWM
+ bool "TIM16 PWM"
+ default n
+ depends on STM32F7_TIM16
+ ---help---
+ Reserve timer 16 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If STM32F7_TIM16
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM16_PWM
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM16_CHANNEL1
+ bool "TIM16 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if STM32F7_TIM16_CHANNEL1
+
+config STM32F7_TIM16_CH1MODE
+ int "TIM16 Channel 1 Mode"
+ default 0
+ range 0 1
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM16_CH1OUT
+ bool "TIM16 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # STM32F7_TIM16_CHANNEL1
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM16_CHANNEL
+ int "TIM16 PWM Output Channel"
+ default 1
+ range 1 1
+ ---help---
+ If TIM16 is enabled for PWM usage, you also need specifies the timer output
+ channel {1}
+
+config STM32F7_TIM16_CHMODE
+ int "TIM16 Channel Mode"
+ default 0
+ range 0 1
+ ---help---
+ Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM16_PWM
+
+config STM32F7_TIM17_PWM
+ bool "TIM17 PWM"
+ default n
+ depends on STM32F7_TIM17
+ ---help---
+ Reserve timer 17 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If STM32F7_TIM17
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if STM32F7_TIM17_PWM
+
+if STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM17_CHANNEL1
+ bool "TIM17 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if STM32F7_TIM17_CHANNEL1
+
+config STM32F7_TIM17_CH1MODE
+ int "TIM17 Channel 1 Mode"
+ default 0
+ range 0 1
+ ---help---
+ Specifies the channel mode.
+
+config STM32F7_TIM17_CH1OUT
+ bool "TIM17 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # STM32F7_TIM17_CHANNEL1
+
+endif # STM32F7_PWM_MULTICHAN
+
+if !STM32F7_PWM_MULTICHAN
+
+config STM32F7_TIM17_CHANNEL
+ int "TIM17 PWM Output Channel"
+ default 1
+ range 1 1
+ ---help---
+ If TIM17 is enabled for PWM usage, you also need specifies the timer output
+ channel {1}
+
+config STM32F7_TIM17_CHMODE
+ int "TIM17 Channel Mode"
+ default 0
+ range 0 1
+ ---help---
+ Specifies the channel mode.
+
+endif # !STM32F7_PWM_MULTICHAN
+
+endif # STM32F7_TIM17_PWM
+
+config STM32F7_PWM_MULTICHAN
+ bool "PWM Multiple Output Channels"
+ default n
+ depends on STM32F7_TIM1_PWM || STM32F7_TIM2_PWM || STM32F7_TIM3_PWM || STM32F7_TIM4_PWM || STM32F7_TIM5_PWM || STM32F7_TIM8_PWM || STM32F7_TIM9_PWM || STM32F7_TIM10_PWM || STM32F7_TIM11_PWM || STM32F7_TIM12_PWM || STM32F7_TIM13_PWM || STM32F7_TIM14_PWM || STM32F7_TIM15_PWM || STM32F7_TIM16_PWM || STM32F7_TIM17_PWM
+ select ARCH_HAVE_PWM_MULTICHAN
+ ---help---
+ Specifies that the PWM driver supports multiple output
+ channels per timer.
+
+config STM32F7_TIM1_ADC
+ bool "TIM1 ADC"
+ default n
+ depends on STM32F7_TIM1 && STM32F7_ADC
+ ---help---
+ Reserve timer 1 for use by ADC
+
+ Timer devices may be used for different purposes. If STM32F7_TIM1 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for ADC conversion. Note that ADC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the ADC, but then you also have to configure which ADC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM1 ADC channel"
+ default STM32F7_TIM1_ADC1
+ depends on STM32F7_TIM1_ADC
+
+config STM32F7_TIM1_ADC1
+ bool "TIM1 ADC channel 1"
+ depends on STM32F7_ADC1
+ select HAVE_ADC1_TIMER
+ ---help---
+ Reserve TIM1 to trigger ADC1
+
+config STM32F7_TIM1_ADC2
+ bool "TIM1 ADC channel 2"
+ depends on STM32F7_ADC2
+ select HAVE_ADC2_TIMER
+ ---help---
+ Reserve TIM1 to trigger ADC2
+
+config STM32F7_TIM1_ADC3
+ bool "TIM1 ADC channel 3"
+ depends on STM32F7_ADC3
+ select HAVE_ADC3_TIMER
+ ---help---
+ Reserve TIM1 to trigger ADC3
+
+endchoice
+
+config STM32F7_TIM2_ADC
+ bool "TIM2 ADC"
+ default n
+ depends on STM32F7_TIM2 && STM32F7_ADC
+ ---help---
+ Reserve timer 1 for use by ADC
+
+ Timer devices may be used for different purposes. If STM32F7_TIM2 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for ADC conversion. Note that ADC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the ADC, but then you also have to configure which ADC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM2 ADC channel"
+ default STM32F7_TIM2_ADC1
+ depends on STM32F7_TIM2_ADC
+
+config STM32F7_TIM2_ADC1
+ bool "TIM2 ADC channel 1"
+ depends on STM32F7_ADC1
+ select HAVE_ADC1_TIMER
+ ---help---
+ Reserve TIM2 to trigger ADC1
+
+config STM32F7_TIM2_ADC2
+ bool "TIM2 ADC channel 2"
+ depends on STM32F7_ADC2
+ select HAVE_ADC2_TIMER
+ ---help---
+ Reserve TIM2 to trigger ADC2
+
+config STM32F7_TIM2_ADC3
+ bool "TIM2 ADC channel 3"
+ depends on STM32F7_ADC3
+ select HAVE_ADC3_TIMER
+ ---help---
+ Reserve TIM2 to trigger ADC3
+
+endchoice
+
+config STM32F7_TIM3_ADC
+ bool "TIM3 ADC"
+ default n
+ depends on STM32F7_TIM3 && STM32F7_ADC
+ ---help---
+ Reserve timer 1 for use by ADC
+
+ Timer devices may be used for different purposes. If STM32F7_TIM3 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for ADC conversion. Note that ADC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the ADC, but then you also have to configure which ADC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM3 ADC channel"
+ default STM32F7_TIM3_ADC1
+ depends on STM32F7_TIM3_ADC
+
+config STM32F7_TIM3_ADC1
+ bool "TIM3 ADC channel 1"
+ depends on STM32F7_ADC1
+ select HAVE_ADC1_TIMER
+ ---help---
+ Reserve TIM3 to trigger ADC1
+
+config STM32F7_TIM3_ADC2
+ bool "TIM3 ADC channel 2"
+ depends on STM32F7_ADC2
+ select HAVE_ADC2_TIMER
+ ---help---
+ Reserve TIM3 to trigger ADC2
+
+config STM32F7_TIM3_ADC3
+ bool "TIM3 ADC channel 3"
+ depends on STM32F7_ADC3
+ select HAVE_ADC3_TIMER
+ ---help---
+ Reserve TIM3 to trigger ADC3
+
+endchoice
+
+config STM32F7_TIM4_ADC
+ bool "TIM4 ADC"
+ default n
+ depends on STM32F7_TIM4 && STM32F7_ADC
+ ---help---
+ Reserve timer 1 for use by ADC
+
+ Timer devices may be used for different purposes. If STM32F7_TIM4 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for ADC conversion. Note that ADC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the ADC, but then you also have to configure which ADC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM4 ADC channel"
+ default STM32F7_TIM4_ADC1
+ depends on STM32F7_TIM4_ADC
+
+config STM32F7_TIM4_ADC1
+ bool "TIM4 ADC channel 1"
+ depends on STM32F7_ADC1
+ select HAVE_ADC1_TIMER
+ ---help---
+ Reserve TIM4 to trigger ADC1
+
+config STM32F7_TIM4_ADC2
+ bool "TIM4 ADC channel 2"
+ depends on STM32F7_ADC2
+ select HAVE_ADC2_TIMER
+ ---help---
+ Reserve TIM4 to trigger ADC2
+
+config STM32F7_TIM4_ADC3
+ bool "TIM4 ADC channel 3"
+ depends on STM32F7_ADC3
+ select HAVE_ADC3_TIMER
+ ---help---
+ Reserve TIM4 to trigger ADC3
+
+endchoice
+
+config STM32F7_TIM5_ADC
+ bool "TIM5 ADC"
+ default n
+ depends on STM32F7_TIM5 && STM32F7_ADC
+ ---help---
+ Reserve timer 1 for use by ADC
+
+ Timer devices may be used for different purposes. If STM32F7_TIM5 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for ADC conversion. Note that ADC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the ADC, but then you also have to configure which ADC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM5 ADC channel"
+ default STM32F7_TIM5_ADC1
+ depends on STM32F7_TIM5_ADC
+
+config STM32F7_TIM5_ADC1
+ bool "TIM5 ADC channel 1"
+ depends on STM32F7_ADC1
+ select HAVE_ADC1_TIMER
+ ---help---
+ Reserve TIM5 to trigger ADC1
+
+config STM32F7_TIM5_ADC2
+ bool "TIM5 ADC channel 2"
+ depends on STM32F7_ADC2
+ select HAVE_ADC2_TIMER
+ ---help---
+ Reserve TIM5 to trigger ADC2
+
+config STM32F7_TIM5_ADC3
+ bool "TIM5 ADC channel 3"
+ depends on STM32F7_ADC3
+ select HAVE_ADC3_TIMER
+ ---help---
+ Reserve TIM5 to trigger ADC3
+
+endchoice
+
+config STM32F7_TIM8_ADC
+ bool "TIM8 ADC"
+ default n
+ depends on STM32F7_TIM8 && STM32F7_ADC
+ ---help---
+ Reserve timer 1 for use by ADC
+
+ Timer devices may be used for different purposes. If STM32F7_TIM8 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for ADC conversion. Note that ADC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the ADC, but then you also have to configure which ADC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM8 ADC channel"
+ default STM32F7_TIM8_ADC1
+ depends on STM32F7_TIM8_ADC
+
+config STM32F7_TIM8_ADC1
+ bool "TIM8 ADC channel 1"
+ depends on STM32F7_ADC1
+ select HAVE_ADC1_TIMER
+ ---help---
+ Reserve TIM8 to trigger ADC1
+
+config STM32F7_TIM8_ADC2
+ bool "TIM8 ADC channel 2"
+ depends on STM32F7_ADC2
+ select HAVE_ADC2_TIMER
+ ---help---
+ Reserve TIM8 to trigger ADC2
+
+config STM32F7_TIM8_ADC3
+ bool "TIM8 ADC channel 3"
+ depends on STM32F7_ADC3
+ select HAVE_ADC3_TIMER
+ ---help---
+ Reserve TIM8 to trigger ADC3
+
+endchoice
+
+config HAVE_ADC1_TIMER
+ bool
+
+config HAVE_ADC2_TIMER
+ bool
+
+config HAVE_ADC3_TIMER
+ bool
+
+config STM32F7_ADC1_SAMPLE_FREQUENCY
+ int "ADC1 Sampling Frequency"
+ default 100
+ depends on HAVE_ADC1_TIMER
+ ---help---
+ ADC1 sampling frequency. Default: 100Hz
+
+config STM32F7_ADC1_TIMTRIG
+ int "ADC1 Timer Trigger"
+ default 0
+ range 0 4
+ depends on HAVE_ADC1_TIMER
+ ---help---
+ Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
+
+config STM32F7_ADC2_SAMPLE_FREQUENCY
+ int "ADC2 Sampling Frequency"
+ default 100
+ depends on HAVE_ADC2_TIMER
+ ---help---
+ ADC2 sampling frequency. Default: 100Hz
+
+config STM32F7_ADC2_TIMTRIG
+ int "ADC2 Timer Trigger"
+ default 0
+ range 0 4
+ depends on HAVE_ADC2_TIMER
+ ---help---
+ Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
+
+config STM32F7_ADC3_SAMPLE_FREQUENCY
+ int "ADC3 Sampling Frequency"
+ default 100
+ depends on HAVE_ADC3_TIMER
+ ---help---
+ ADC3 sampling frequency. Default: 100Hz
+
+config STM32F7_ADC3_TIMTRIG
+ int "ADC3 Timer Trigger"
+ default 0
+ range 0 4
+ depends on HAVE_ADC3_TIMER
+ ---help---
+ Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
+
+config STM32F7_TIM1_DAC
+ bool "TIM1 DAC"
+ default n
+ depends on STM32F7_TIM1 && STM32F7_DAC
+ ---help---
+ Reserve timer 1 for use by DAC
+
+ Timer devices may be used for different purposes. If STM32F7_TIM1 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM1 DAC channel"
+ default STM32F7_TIM1_DAC1
+ depends on STM32F7_TIM1_DAC
+
+config STM32F7_TIM1_DAC1
+ bool "TIM1 DAC channel 1"
+ ---help---
+ Reserve TIM1 to trigger DAC1
+
+config STM32F7_TIM1_DAC2
+ bool "TIM1 DAC channel 2"
+ ---help---
+ Reserve TIM1 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM2_DAC
+ bool "TIM2 DAC"
+ default n
+ depends on STM32F7_TIM2 && STM32F7_DAC
+ ---help---
+ Reserve timer 2 for use by DAC
+
+ Timer devices may be used for different purposes. If STM32F7_TIM2 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM2 DAC channel"
+ default STM32F7_TIM2_DAC1
+ depends on STM32F7_TIM2_DAC
+
+config STM32F7_TIM2_DAC1
+ bool "TIM2 DAC channel 1"
+ ---help---
+ Reserve TIM2 to trigger DAC1
+
+config STM32F7_TIM2_DAC2
+ bool "TIM2 DAC channel 2"
+ ---help---
+ Reserve TIM2 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM3_DAC
+ bool "TIM3 DAC"
+ default n
+ depends on STM32F7_TIM3 && STM32F7_DAC
+ ---help---
+ Reserve timer 3 for use by DAC
+
+ Timer devices may be used for different purposes. If STM32F7_TIM3 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM3 DAC channel"
+ default STM32F7_TIM3_DAC1
+ depends on STM32F7_TIM3_DAC
+
+config STM32F7_TIM3_DAC1
+ bool "TIM3 DAC channel 1"
+ ---help---
+ Reserve TIM3 to trigger DAC1
+
+config STM32F7_TIM3_DAC2
+ bool "TIM3 DAC channel 2"
+ ---help---
+ Reserve TIM3 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM4_DAC
+ bool "TIM4 DAC"
+ default n
+ depends on STM32F7_TIM4 && STM32F7_DAC
+ ---help---
+ Reserve timer 4 for use by DAC
+
+ Timer devices may be used for different purposes. If STM32F7_TIM4 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM4 DAC channel"
+ default STM32F7_TIM4_DAC1
+ depends on STM32F7_TIM4_DAC
+
+config STM32F7_TIM4_DAC1
+ bool "TIM4 DAC channel 1"
+ ---help---
+ Reserve TIM4 to trigger DAC1
+
+config STM32F7_TIM4_DAC2
+ bool "TIM4 DAC channel 2"
+ ---help---
+ Reserve TIM4 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM5_DAC
+ bool "TIM5 DAC"
+ default n
+ depends on STM32F7_TIM5 && STM32F7_DAC
+ ---help---
+ Reserve timer 5 for use by DAC
+
+ Timer devices may be used for different purposes. If STM32F7_TIM5 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM5 DAC channel"
+ default STM32F7_TIM5_DAC1
+ depends on STM32F7_TIM5_DAC
+
+config STM32F7_TIM5_DAC1
+ bool "TIM5 DAC channel 1"
+ ---help---
+ Reserve TIM5 to trigger DAC1
+
+config STM32F7_TIM5_DAC2
+ bool "TIM5 DAC channel 2"
+ ---help---
+ Reserve TIM5 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM6_DAC
+ bool "TIM6 DAC"
+ default n
+ depends on STM32F7_TIM6 && STM32F7_DAC
+ ---help---
+ Reserve timer 6 for use by DAC
+
+ Timer devices may be used for different purposes. If STM32F7_TIM6 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM6 DAC channel"
+ default STM32F7_TIM6_DAC1
+ depends on STM32F7_TIM6_DAC
+
+config STM32F7_TIM6_DAC1
+ bool "TIM6 DAC channel 1"
+ ---help---
+ Reserve TIM6 to trigger DAC1
+
+config STM32F7_TIM6_DAC2
+ bool "TIM6 DAC channel 2"
+ ---help---
+ Reserve TIM6 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM7_DAC
+ bool "TIM7 DAC"
+ default n
+ depends on STM32F7_TIM7 && STM32F7_DAC
+ ---help---
+ Reserve timer 7 for use by DAC
+
+ Timer devices may be used for different purposes. If STM32F7_TIM7 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM7 DAC channel"
+ default STM32F7_TIM7_DAC1
+ depends on STM32F7_TIM7_DAC
+
+config STM32F7_TIM7_DAC1
+ bool "TIM7 DAC channel 1"
+ ---help---
+ Reserve TIM7 to trigger DAC1
+
+config STM32F7_TIM7_DAC2
+ bool "TIM7 DAC channel 2"
+ ---help---
+ Reserve TIM7 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM8_DAC
+ bool "TIM8 DAC"
+ default n
+ depends on STM32F7_TIM8 && STM32F7_DAC
+ ---help---
+ Reserve timer 8 for use by DAC
+
+ Timer devices may be used for different purposes. If STM32F7_TIM8 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM8 DAC channel"
+ default STM32F7_TIM8_DAC1
+ depends on STM32F7_TIM8_DAC
+
+config STM32F7_TIM8_DAC1
+ bool "TIM8 DAC channel 1"
+ ---help---
+ Reserve TIM8 to trigger DAC1
+
+config STM32F7_TIM8_DAC2
+ bool "TIM8 DAC channel 2"
+ ---help---
+ Reserve TIM8 to trigger DAC2
+
+endchoice
+
+config STM32F7_TIM9_DAC
+ bool "TIM9 DAC"
default n
- select ARCH_HAVE_SERIAL_TERMIOS
- select UART8_SERIALDRIVER
- select STM32F7_USART
+ depends on STM32F7_TIM9 && STM32F7_DAC
+ ---help---
+ Reserve timer 9 for use by DAC
-config STM32F7_IWDG
- bool "IWDG"
- default n
- select WATCHDOG
+ Timer devices may be used for different purposes. If STM32F7_TIM9 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
-config STM32F7_WWDG
- bool "WWDG"
- default n
- select WATCHDOG
+choice
+ prompt "Select TIM9 DAC channel"
+ default STM32F7_TIM9_DAC1
+ depends on STM32F7_TIM9_DAC
-endmenu
+config STM32F7_TIM9_DAC1
+ bool "TIM9 DAC channel 1"
+ ---help---
+ Reserve TIM9 to trigger DAC1
-menu "U[S]ART Configuration"
- depends on STM32F7_USART
+config STM32F7_TIM9_DAC2
+ bool "TIM9 DAC channel 2"
+ ---help---
+ Reserve TIM9 to trigger DAC2
-config USART1_RS485
- bool "RS-485 on USART1"
+endchoice
+
+config STM32F7_TIM10_DAC
+ bool "TIM10 DAC"
default n
- depends on STM32F7_USART1
+ depends on STM32F7_TIM10 && STM32F7_DAC
---help---
- Enable RS-485 interface on USART1. Your board config will have to
- provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be
- used with USART1_RXDMA.
+ Reserve timer 10 for use by DAC
-config USART1_RS485_DIR_POLARITY
- int "USART1 RS-485 DIR pin polarity"
- default 1
- range 0 1
- depends on USART1_RS485
+ Timer devices may be used for different purposes. If STM32F7_TIM10 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM10 DAC channel"
+ default STM32F7_TIM10_DAC1
+ depends on STM32F7_TIM10_DAC
+
+config STM32F7_TIM10_DAC1
+ bool "TIM10 DAC channel 1"
---help---
- Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which
- enables TX (0 - low / nTXEN, 1 - high / TXEN).
+ Reserve TIM10 to trigger DAC1
-config USART1_RXDMA
- bool "USART1 Rx DMA"
- default n
- depends on STM32F7_USART1 && STM32F7_DMA1
+config STM32F7_TIM10_DAC2
+ bool "TIM10 DAC channel 2"
---help---
- In high data rate usage, Rx DMA may eliminate Rx overrun errors
+ Reserve TIM10 to trigger DAC2
-config USART2_RS485
- bool "RS-485 on USART2"
+endchoice
+
+config STM32F7_TIM11_DAC
+ bool "TIM11 DAC"
default n
- depends on STM32F7_USART2
+ depends on STM32F7_TIM11 && STM32F7_DAC
---help---
- Enable RS-485 interface on USART2. Your board config will have to
- provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be
- used with USART2_RXDMA.
+ Reserve timer 11 for use by DAC
-config USART2_RS485_DIR_POLARITY
- int "USART2 RS-485 DIR pin polarity"
- default 1
- range 0 1
- depends on USART2_RS485
+ Timer devices may be used for different purposes. If STM32F7_TIM11 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM11 DAC channel"
+ default STM32F7_TIM11_DAC1
+ depends on STM32F7_TIM11_DAC
+
+config STM32F7_TIM11_DAC1
+ bool "TIM11 DAC channel 1"
---help---
- Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which
- enables TX (0 - low / nTXEN, 1 - high / TXEN).
+ Reserve TIM11 to trigger DAC1
-config USART2_RXDMA
- bool "USART2 Rx DMA"
- default n
- depends on STM32F7_USART2 && STM32F7_DMA1
+config STM32F7_TIM11_DAC2
+ bool "TIM11 DAC channel 2"
---help---
- In high data rate usage, Rx DMA may eliminate Rx overrun errors
+ Reserve TIM11 to trigger DAC2
-config USART3_RS485
- bool "RS-485 on USART3"
+endchoice
+
+config STM32F7_TIM12_DAC
+ bool "TIM12 DAC"
default n
- depends on STM32F7_USART3
+ depends on STM32F7_TIM12 && STM32F7_DAC
---help---
- Enable RS-485 interface on USART3. Your board config will have to
- provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be
- used with USART3_RXDMA.
+ Reserve timer 12 for use by DAC
-config USART3_RS485_DIR_POLARITY
- int "USART3 RS-485 DIR pin polarity"
- default 1
- range 0 1
- depends on USART3_RS485
+ Timer devices may be used for different purposes. If STM32F7_TIM12 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM12 DAC channel"
+ default STM32F7_TIM12_DAC1
+ depends on STM32F7_TIM12_DAC
+
+config STM32F7_TIM12_DAC1
+ bool "TIM12 DAC channel 1"
---help---
- Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which
- enables TX (0 - low / nTXEN, 1 - high / TXEN).
+ Reserve TIM12 to trigger DAC1
-config USART3_RXDMA
- bool "USART3 Rx DMA"
- default n
- depends on STM32F7_USART3 && STM32F7_DMA1
+config STM32F7_TIM12_DAC2
+ bool "TIM12 DAC channel 2"
---help---
- In high data rate usage, Rx DMA may eliminate Rx overrun errors
+ Reserve TIM12 to trigger DAC2
-config UART4_RS485
- bool "RS-485 on UART4"
+endchoice
+
+config STM32F7_TIM13_DAC
+ bool "TIM13 DAC"
default n
- depends on STM32F7_UART4
+ depends on STM32F7_TIM13 && STM32F7_DAC
---help---
- Enable RS-485 interface on UART4. Your board config will have to
- provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be
- used with UART4_RXDMA.
+ Reserve timer 13 for use by DAC
-config UART4_RS485_DIR_POLARITY
- int "UART4 RS-485 DIR pin polarity"
- default 1
- range 0 1
- depends on UART4_RS485
+ Timer devices may be used for different purposes. If STM32F7_TIM13 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM13 DAC channel"
+ default STM32F7_TIM13_DAC1
+ depends on STM32F7_TIM13_DAC
+
+config STM32F7_TIM13_DAC1
+ bool "TIM13 DAC channel 1"
---help---
- Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which
- enables TX (0 - low / nTXEN, 1 - high / TXEN).
+ Reserve TIM13 to trigger DAC1
-config UART4_RXDMA
- bool "UART4 Rx DMA"
- default n
- depends on STM32F7_UART4 && STM32F7_DMA1
+config STM32F7_TIM13_DAC2
+ bool "TIM13 DAC channel 2"
---help---
- In high data rate usage, Rx DMA may eliminate Rx overrun errors
+ Reserve TIM13 to trigger DAC2
-config UART5_RS485
- bool "RS-485 on UART5"
+endchoice
+
+config STM32F7_TIM14_DAC
+ bool "TIM14 DAC"
default n
- depends on STM32F7_UART5
+ depends on STM32F7_TIM14 && STM32F7_DAC
---help---
- Enable RS-485 interface on UART5. Your board config will have to
- provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be
- used with UART5_RXDMA.
+ Reserve timer 14 for use by DAC
-config UART5_RS485_DIR_POLARITY
- int "UART5 RS-485 DIR pin polarity"
- default 1
- range 0 1
- depends on UART5_RS485
+ Timer devices may be used for different purposes. If STM32F7_TIM14 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM14 DAC channel"
+ default STM32F7_TIM14_DAC1
+ depends on STM32F7_TIM14_DAC
+
+config STM32F7_TIM14_DAC1
+ bool "TIM14 DAC channel 1"
---help---
- Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which
- enables TX (0 - low / nTXEN, 1 - high / TXEN).
+ Reserve TIM14 to trigger DAC1
-config UART5_RXDMA
- bool "UART5 Rx DMA"
- default n
- depends on STM32F7_UART5 && STM32F7_DMA1
+config STM32F7_TIM14_DAC2
+ bool "TIM14 DAC channel 2"
---help---
- In high data rate usage, Rx DMA may eliminate Rx overrun errors
+ Reserve TIM14 to trigger DAC2
-config USART6_RS485
- bool "RS-485 on USART6"
+endchoice
+
+config STM32F7_TIM1_CAP
+ bool "TIM1 Capture"
default n
- depends on STM32F7_USART6
+ depends on STM32F7_HAVE_TIM1
---help---
- Enable RS-485 interface on USART6. Your board config will have to
- provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be
- used with USART6_RXDMA.
+ Reserve timer 1 for use by Capture
-config USART6_RS485_DIR_POLARITY
- int "USART6 RS-485 DIR pin polarity"
- default 1
- range 0 1
- depends on USART6_RS485
- ---help---
- Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which
- enables TX (0 - low / nTXEN, 1 - high / TXEN).
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
-config USART6_RXDMA
- bool "USART6 Rx DMA"
+config STM32F7_TIM2_CAP
+ bool "TIM2 Capture"
default n
- depends on STM32F7_USART6 && STM32F7_DMA2
+ depends on STM32F7_HAVE_TIM2
---help---
- In high data rate usage, Rx DMA may eliminate Rx overrun errors
+ Reserve timer 2 for use by Capture
-config UART7_RS485
- bool "RS-485 on UART7"
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+config STM32F7_TIM3_CAP
+ bool "TIM3 Capture"
default n
- depends on STM32F7_UART7
+ depends on STM32F7_HAVE_TIM3
---help---
- Enable RS-485 interface on UART7. Your board config will have to
- provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be
- used with UART7_RXDMA.
+ Reserve timer 3 for use by Capture
-config UART7_RS485_DIR_POLARITY
- int "UART7 RS-485 DIR pin polarity"
- default 1
- range 0 1
- depends on UART7_RS485
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+config STM32F7_TIM4_CAP
+ bool "TIM4 Capture"
+ default n
+ depends on STM32F7_HAVE_TIM4
---help---
- Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which
- enables TX (0 - low / nTXEN, 1 - high / TXEN).
+ Reserve timer 4 for use by Capture
-config UART7_RXDMA
- bool "UART7 Rx DMA"
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+config STM32F7_TIM5_CAP
+ bool "TIM5 Capture"
default n
- depends on STM32F7_UART7 && STM32F7_DMA2
+ depends on STM32F7_HAVE_TIM5
---help---
- In high data rate usage, Rx DMA may eliminate Rx overrun errors
+ Reserve timer 5 for use by Capture
-config UART8_RS485
- bool "RS-485 on UART8"
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+config STM32F7_TIM8_CAP
+ bool "TIM8 Capture"
default n
- depends on STM32F7_UART8
+ depends on STM32F7_HAVE_TIM8
---help---
- Enable RS-485 interface on UART8. Your board config will have to
- provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be
- used with UART8_RXDMA.
+ Reserve timer 8 for use by Capture
-config UART8_RS485_DIR_POLARITY
- int "UART8 RS-485 DIR pin polarity"
- default 1
- range 0 1
- depends on UART8_RS485
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+config STM32F7_TIM9_CAP
+ bool "TIM9 Capture"
+ default n
+ depends on STM32F7_HAVE_TIM9
---help---
- Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which
- enables TX (0 - low / nTXEN, 1 - high / TXEN).
+ Reserve timer 9 for use by Capture
-config UART8_RXDMA
- bool "UART8 Rx DMA"
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+config STM32F7_TIM10_CAP
+ bool "TIM10 Capture"
default n
- depends on STM32F7_UART8 && STM32F7_DMA2
+ depends on STM32F7_HAVE_TIM10
---help---
- In high data rate usage, Rx DMA may eliminate Rx overrun errors
+ Reserve timer 10 for use by Capture
-config SERIAL_DISABLE_REORDERING
- bool "Disable reordering of ttySx devices."
- depends on STM32F7_USART1 || STM32F7_USART2 || STM32F7_USART3 || STM32F7_UART4 || STM32F7_UART5 || STM32F7_USART6 || STM32F7_UART7 || STM32F7_UART8
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+config STM32F7_TIM11_CAP
+ bool "TIM11 Capture"
default n
+ depends on STM32F7_HAVE_TIM11
---help---
- NuttX per default reorders the serial ports (/dev/ttySx) so that the
- console is always on /dev/ttyS0. If more than one UART is in use this
- can, however, have the side-effect that all port mappings
- (hardware USART1 -> /dev/ttyS0) change if the console is moved to another
- UART. This is in particular relevant if a project uses the USB console
- in some configs and a serial console in other configs, but does not
- want the side effect of having all serial port names change when just
- the console is moved from serial to USB.
+ Reserve timer 11 for use by Capture
-config STM32F7_FLOWCONTROL_BROKEN
- bool "Use Software UART RTS flow control"
- depends on STM32F7_USART
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+config STM32F7_TIM12_CAP
+ bool "TIM12 Capture"
default n
+ depends on STM32F7_HAVE_TIM12
---help---
- Enable UART RTS flow control using Software. Because STM
- Current STM32 have broken HW based RTS behavior (they assert
- nRTS after every byte received) Enable this setting workaround
- this issue by useing software based management of RTS
+ Reserve timer 12 for use by Capture
-config STM32F7_USART_BREAKS
- bool "Add TIOxSBRK to support sending Breaks"
- depends on STM32F7_USART
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+config STM32F7_TIM13_CAP
+ bool "TIM13 Capture"
default n
+ depends on STM32F7_HAVE_TIM13
---help---
- Add TIOCxBRK routines to send a line break per the STM32 manual, the
- break will be a pulse based on the value M. This is not a BSD compatible
- break.
+ Reserve timer 13 for use by Capture
-config STM32F7_SERIALBRK_BSDCOMPAT
- bool "Use GPIO To send Break"
- depends on STM32F7_USART && STM32F7_USART_BREAKS
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+config STM32F7_TIM14_CAP
+ bool "TIM14 Capture"
default n
+ depends on STM32F7_HAVE_TIM14
---help---
- Enable using GPIO on the TX pin to send a BSD compatible break:
- TIOCSBRK will start the break and TIOCCBRK will end the break.
- The current STM32 U[S]ARTS have no way to leave the break (TX=LOW)
- on because the SW starts the break and then the HW automatically clears
- the break. This makes it is difficult to sent a long break.
+ Reserve timer 14 for use by Capture
-endmenu # U[S]ART Configuration
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
-config STM32F7_CUSTOM_CLOCKCONFIG
- bool "Custom clock configuration"
+endmenu # Timer Configuration
+
+menu "ADC Configuration"
+ depends on STM32F7_ADC
+
+config STM32F7_ADC1_DMA
+ bool "ADC1 DMA"
+ depends on STM32F7_ADC1 && STM32F7_HAVE_ADC1_DMA
default n
---help---
- Enables special, board-specific STM32 clock configuration.
+ If DMA is selected, then the ADC may be configured to support
+ DMA transfer, which is necessary if multiple channels are read
+ or if very high trigger frequencies are used.
-config STM32F7_DTCM_PROCFS
- bool "DTCM SRAM PROCFS support"
+config STM32F7_ADC2_DMA
+ bool "ADC2 DMA"
+ depends on STM32F7_ADC2 && STM32F7_HAVE_ADC2_DMA
default n
- depends on ARMV7M_DTCM && FS_PROCFS
---help---
- Select to build in support for /proc/dtcm. Reading from /proc/dtcm
- will provide statistics about DTCM memory use similar to what you
- would get from mallinfo() for the user heap.
+ If DMA is selected, then the ADC may be configured to support
+ DMA transfer, which is necessary if multiple channels are read
+ or if very high trigger frequencies are used.
+
+config STM32F7_ADC3_DMA
+ bool "ADC3 DMA"
+ depends on STM32F7_ADC3 && STM32F7_HAVE_ADC3_DMA
+ default n
+ ---help---
+ If DMA is selected, then the ADC may be configured to support
+ DMA transfer, which is necessary if multiple channels are read
+ or if very high trigger frequencies are used.
+
+endmenu # "ADC Configuration"
if STM32F7_ETHMAC
menu "Ethernet MAC configuration"
@@ -887,9 +4667,9 @@ endchoice
config STM32F7_ETHMAC_REGDEBUG
bool "Register-Level Debug"
default n
- depends on DEBUG
+ depends on DEBUG_NET_INFO
---help---
- Enable very low-level register access debug. Depends on DEBUG.
+ Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES.
endmenu
endif # STM32F7_ETHMAC
diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs
index 2f4b7b251346b339b59bece843d3292169b8f3e7..ba56b9aea41eb1736cdab5f69378f1b21f02d49a 100644
--- a/arch/arm/src/stm32f7/Make.defs
+++ b/arch/arm/src/stm32f7/Make.defs
@@ -51,7 +51,7 @@ CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_idle.c up_initialize.c
CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_memfault.c up_modifyreg8.c
CMN_CSRCS += up_modifyreg16.c up_modifyreg32.c up_releasepending.c
CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c
-CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_unblocktask.c up_usestack.c
+CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_systemreset.c up_unblocktask.c up_usestack.c
CMN_CSRCS += up_doirq.c up_hardfault.c up_svcall.c up_vfork.c
# Configuration-dependent common files
@@ -139,7 +139,27 @@ ifeq ($(CONFIG_STM32_PWR),y)
CHIP_CSRCS += stm32_exti_pwr.c
endif
-ifeq ($(CONFIG_RTC),y)
+ifeq ($(CONFIG_STM32F7_I2C),y)
+CHIP_CSRCS += stm32_i2c.c
+endif
+
+ifeq ($(CONFIG_STM32F7_SPI),y)
+CHIP_CSRCS += stm32_spi.c
+endif
+
+ifeq ($(CONFIG_STM32F7_SDMMC1),y)
+CHIP_CSRCS += stm32_sdmmc.c
+endif
+
+ifeq ($(CONFIG_STM32F7_TIM),y)
+CHIP_CSRCS += stm32_tim.c
+endif
+
+ifeq ($(CONFIG_STM32F7_ADC),y)
+CHIP_CSRCS += stm32_adc.c
+endif
+
+ifeq ($(CONFIG_STM32F7_RTC),y)
ifeq ($(CONFIG_RTC_ALARM),y)
CHIP_CSRCS += stm32_exti_alarm.c
endif
@@ -149,6 +169,6 @@ ifeq ($(CONFIG_STM32F7_ETHMAC),y)
CHIP_CSRCS += stm32_ethernet.c
endif
-ifeq ($(CONFIG_DEBUG),y)
+ifeq ($(CONFIG_DEBUG_FEATURES),y)
CHIP_CSRCS += stm32_dumpgpio.c
endif
diff --git a/arch/arm/src/stm32f7/chip.h b/arch/arm/src/stm32f7/chip.h
index 536b8e001071e25e8cbe4654faa9eac4baabfbef..6a8e21995f5d2c506c33ccfe87d7bda477cc473b 100644
--- a/arch/arm/src/stm32f7/chip.h
+++ b/arch/arm/src/stm32f7/chip.h
@@ -48,6 +48,7 @@
#include
#include
+#include "chip/stm32_pinmap.h"
#include "chip/stm32_memorymap.h"
/* If the common ARMv7-M vector handling logic is used, then it expects the
diff --git a/arch/arm/src/stm32f7/chip/stm32_adc.h b/arch/arm/src/stm32f7/chip/stm32_adc.h
new file mode 100644
index 0000000000000000000000000000000000000000..7b0861d77efbba26a6672482a8fd92e9374d93d9
--- /dev/null
+++ b/arch/arm/src/stm32f7/chip/stm32_adc.h
@@ -0,0 +1,58 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32_adc.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ * David Sidrane
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ADC_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ADC_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+#include
+#include "chip.h"
+
+#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
+ defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+# include "chip/stm32f74xx77xx_adc.h"
+#else
+# error "Unsupported STM32 F7 sub family"
+#endif
+
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ADC_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_dma.h b/arch/arm/src/stm32f7/chip/stm32_dma.h
index 63db15ec9f3e32119711fb5586788ee74ec6e134..64fa967bca6e423f9d7e6dfb43687d6e558ff1bb 100644
--- a/arch/arm/src/stm32f7/chip/stm32_dma.h
+++ b/arch/arm/src/stm32f7/chip/stm32_dma.h
@@ -2,7 +2,8 @@
* arch/arm/src/stm32f7/chip/stm32_dma.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
+ * Authors: Gregory Nutt
+ * David Sidrane
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -45,6 +46,8 @@
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# include "chip/stm32f74xx75xx_dma.h"
+#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+# include "chip/stm32f76xx77xx_dma.h"
#else
# error "Unsupported STM32 F7 part"
#endif
diff --git a/arch/arm/src/stm32f7/chip/stm32_ethernet.h b/arch/arm/src/stm32f7/chip/stm32_ethernet.h
index e5fc6982d2859f9ada3083f35f53fcc484e11962..962cb6d92205d7785f32bc5effff1336a9ccdd65 100644
--- a/arch/arm/src/stm32f7/chip/stm32_ethernet.h
+++ b/arch/arm/src/stm32f7/chip/stm32_ethernet.h
@@ -2,7 +2,8 @@
* arch/arm/src/stm32f7/chip/stm32_ethernet.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
+ * Authors: Gregory Nutt
+ * David Sidrane
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -46,7 +47,8 @@
* families
*/
-#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
+#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \
+ defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
/****************************************************************************************************
* Pre-processor Definitions
@@ -805,6 +807,6 @@ struct eth_rxdesc_s
****************************************************************************************************/
#endif /* __ASSEMBLY__ */
-#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
+#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ETHERNET_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_exti.h b/arch/arm/src/stm32f7/chip/stm32_exti.h
index 1bf43de7931ea7eb3c4604533d51b2ac0ed60970..288f51b228c1e15e84422dd07e303ecd35e76603 100644
--- a/arch/arm/src/stm32f7/chip/stm32_exti.h
+++ b/arch/arm/src/stm32f7/chip/stm32_exti.h
@@ -2,7 +2,8 @@
* arch/arm/src/stm32f7/chip/stm32_exti.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
+ * Authors: Gregory Nutt
+ * David Sidrane
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -47,7 +48,8 @@
* families
*/
-#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
+#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
+ defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
/************************************************************************************
* Pre-processor Definitions
@@ -127,5 +129,5 @@
#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
#define EXTI_IMR_MASK STM32_EXTI_MASK
-#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
+#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_EXTI_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_flash.h b/arch/arm/src/stm32f7/chip/stm32_flash.h
index 965191bdcfbb70b94ca73f0b7776931a2b0972a8..d20bdfe4d33ef60da4151d1b4e9ebab0ad90c49d 100644
--- a/arch/arm/src/stm32f7/chip/stm32_flash.h
+++ b/arch/arm/src/stm32f7/chip/stm32_flash.h
@@ -2,7 +2,8 @@
* arch/arm/src/stm32f7/chip/stm32_flash.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
+ * Authors: Gregory Nutt
+ * David Sidrane
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -45,6 +46,8 @@
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# include "chip/stm32f74xx75xx_flash.h"
+#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+# include "chip/stm32f76xx77xx_flash.h"
#else
# error "Unsupported STM32 F7 part"
#endif
diff --git a/arch/arm/src/stm32f7/chip/stm32_gpio.h b/arch/arm/src/stm32f7/chip/stm32_gpio.h
index 5b89574b0f29130da07c0bc8093a635f7edc666d..06431bb787dd4c73008fbf41490209d064e209e6 100644
--- a/arch/arm/src/stm32f7/chip/stm32_gpio.h
+++ b/arch/arm/src/stm32f7/chip/stm32_gpio.h
@@ -2,7 +2,8 @@
* arch/arm/src/stm32f7/chip/stm32_gpio.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
+ * Authors: Gregory Nutt
+ * David Sidrane
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -45,6 +46,8 @@
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# include "chip/stm32f74xx75xx_gpio.h"
+#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+# include "chip/stm32f76xx77xx_gpio.h"
#else
# error "Unsupported STM32 F7 part"
#endif
diff --git a/arch/arm/src/stm32f7/chip/stm32_i2c.h b/arch/arm/src/stm32f7/chip/stm32_i2c.h
new file mode 100644
index 0000000000000000000000000000000000000000..f615eb6ec18f0e9df6fda4901be642696a23d012
--- /dev/null
+++ b/arch/arm/src/stm32f7/chip/stm32_i2c.h
@@ -0,0 +1,54 @@
+/************************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32_i2c.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ * David Sidrane
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_I2C_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_I2C_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+#include "chip.h"
+
+#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
+ defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+# include "chip/stm32f74xx77xx_i2c.h"
+#else
+# error "Unsupported STM32 F7 sub family"
+#endif
+
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_I2C_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_memorymap.h b/arch/arm/src/stm32f7/chip/stm32_memorymap.h
index f3ef8a1d53b83e38b989b9d342e45977440751fa..eba94016fd1e7202f3888e0040ad3d2f9632ee1c 100644
--- a/arch/arm/src/stm32f7/chip/stm32_memorymap.h
+++ b/arch/arm/src/stm32f7/chip/stm32_memorymap.h
@@ -2,7 +2,8 @@
* arch/arm/src/stm32f7/chip/stm32_memorymap.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
+ * Authors: Gregory Nutt
+ * David Sidrane
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -45,6 +46,8 @@
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# include "chip/stm32f74xx75xx_memorymap.h"
+#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+# include "chip/stm32f76xx77xx_memorymap.h"
#else
# error "Unsupported STM32 F7 memory map"
#endif
diff --git a/arch/arm/src/stm32f7/chip/stm32_pinmap.h b/arch/arm/src/stm32f7/chip/stm32_pinmap.h
index 59903d8d03e21ebf156de17b75476bc3dad7b5e2..034e32166eb229ed25ca0467f989ac741aa4778d 100644
--- a/arch/arm/src/stm32f7/chip/stm32_pinmap.h
+++ b/arch/arm/src/stm32f7/chip/stm32_pinmap.h
@@ -2,7 +2,8 @@
* arch/arm/src/stm32f7/chip/stm32_pinmap.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
+ * Authors: Gregory Nutt
+ * David Sidrane
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -45,8 +46,10 @@
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# include "chip/stm32f74xx75xx_pinmap.h"
+#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+# include "chip/stm32f76xx77xx_pinmap.h"
#else
-# error "Unsupported STM32 F7 memory map"
+# error "Unsupported STM32 F7 Pin map"
#endif
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_PINMAP_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_pwr.h b/arch/arm/src/stm32f7/chip/stm32_pwr.h
index 427fab1f3fcfdfcd3364469c3c92a3180033773e..e9415d800a7c78766d29ade47bf8865b598f9dae 100644
--- a/arch/arm/src/stm32f7/chip/stm32_pwr.h
+++ b/arch/arm/src/stm32f7/chip/stm32_pwr.h
@@ -2,7 +2,8 @@
* arch/arm/src/stm32f7/chip/stm32_pwr.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
+ * Authors: Gregory Nutt
+ * David Sidrane
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -45,6 +46,8 @@
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# include "chip/stm32f74xx75xx_pwr.h"
+#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+# include "chip/stm32f76xx77xx_pwr.h"
#else
# error "Unsupported STM32 F7 part"
#endif
diff --git a/arch/arm/src/stm32f7/chip/stm32_rcc.h b/arch/arm/src/stm32f7/chip/stm32_rcc.h
index 13468a55601d8427c96c4a5f020c417b3eb35923..e2dfc8380f987400cf5130ff1cf5a0a1472a0fae 100644
--- a/arch/arm/src/stm32f7/chip/stm32_rcc.h
+++ b/arch/arm/src/stm32f7/chip/stm32_rcc.h
@@ -1,8 +1,8 @@
/************************************************************************************
* arch/arm/src/stm32f7/chip/stm32_rcc.h
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
+ * Authors: Gregory Nutt
+ * David Sidrane
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -45,6 +45,8 @@
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# include "chip/stm32f74xx75xx_rcc.h"
+#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+# include "chip/stm32f76xx77xx_rcc.h"
#else
# error "Unsupported STM32 F7 part"
#endif
diff --git a/arch/arm/src/stm32f7/chip/stm32_sdmmc.h b/arch/arm/src/stm32f7/chip/stm32_sdmmc.h
new file mode 100644
index 0000000000000000000000000000000000000000..10ed29f2384d09e12473a5140e538e44148e31cb
--- /dev/null
+++ b/arch/arm/src/stm32f7/chip/stm32_sdmmc.h
@@ -0,0 +1,52 @@
+/************************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32_sdmmc.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SDMMC_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SDMMC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+#include "chip.h"
+
+#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
+# include "stm32f74xx75xx_sdmmc.h"
+#else
+# error "Unsupported STM32 F7 part"
+#endif
+
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SDMMC_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_spi.h b/arch/arm/src/stm32f7/chip/stm32_spi.h
new file mode 100644
index 0000000000000000000000000000000000000000..1874d88bca62f4b3c662db89cfd3f211cceedf75
--- /dev/null
+++ b/arch/arm/src/stm32f7/chip/stm32_spi.h
@@ -0,0 +1,53 @@
+/************************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32_spi.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ * David Sidrane
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+#include "chip.h"
+
+#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
+ defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+# include "chip/stm32f74xx77xx_spi.h"
+#else
+# error "Unsupported STM32 F7 sub family"
+#endif
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_syscfg.h b/arch/arm/src/stm32f7/chip/stm32_syscfg.h
index 37c82ec50cf4b6c87316f352cc8cacb4d33759d9..b17bc518aa2cce7ce9ba6ece9adc10b6051c14e1 100644
--- a/arch/arm/src/stm32f7/chip/stm32_syscfg.h
+++ b/arch/arm/src/stm32f7/chip/stm32_syscfg.h
@@ -2,7 +2,8 @@
* arch/arm/src/stm32f7/chip/stm32_syscfg.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
+ * Authors: Gregory Nutt
+ * David Sidrane
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -45,6 +46,8 @@
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# include "chip/stm32f74xx75xx_syscfg.h"
+#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+# include "chip/stm32f76xx77xx_syscfg.h"
#else
# error "Unsupported STM32 F7 part"
#endif
diff --git a/arch/arm/src/stm32f7/chip/stm32_tim.h b/arch/arm/src/stm32f7/chip/stm32_tim.h
new file mode 100644
index 0000000000000000000000000000000000000000..77204d861d813fc912d22e7ada7516ac2beb213b
--- /dev/null
+++ b/arch/arm/src/stm32f7/chip/stm32_tim.h
@@ -0,0 +1,55 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32_tim.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ * David Sidrane
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_TIM_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_TIM_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+#include "chip.h"
+
+#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
+# include "chip/stm32f74xx75xx_tim.h"
+#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+# include "chip/stm32f76xx77xx_tim.h"
+#else
+# error "Unsupported STM32 F7 sub family"
+#endif
+
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_TIM_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_uart.h b/arch/arm/src/stm32f7/chip/stm32_uart.h
index 0d48eaa399a94ae741256cb8cd20327af9624fdc..7669c675cc39162f66ccbf78492dd8c52b6ac005 100644
--- a/arch/arm/src/stm32f7/chip/stm32_uart.h
+++ b/arch/arm/src/stm32f7/chip/stm32_uart.h
@@ -1,8 +1,9 @@
/************************************************************************************
* arch/arm/src/stm32f7/chip/stm32_uart.h
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt