From 5e8d2347acebb133b4c94d2167799e5dbea4a149 Mon Sep 17 00:00:00 2001
From: pkolesnikov
Date: Mon, 23 May 2016 15:05:56 +0200
Subject: [PATCH 001/400] copy nucleo-144 to stm32f746-ws
---
configs/stm32f746-ws/Kconfig | 8 +
configs/stm32f746-ws/include/board.h | 237 +++++
configs/stm32f746-ws/nsh/Make.defs | 113 +++
configs/stm32f746-ws/nsh/defconfig | 908 ++++++++++++++++++
configs/stm32f746-ws/nsh/setenv.sh | 77 ++
configs/stm32f746-ws/scripts/flash.ld | 147 +++
configs/stm32f746-ws/scripts/kernel-space.ld | 109 +++
configs/stm32f746-ws/scripts/memory.ld | 129 +++
configs/stm32f746-ws/scripts/user-space.ld | 111 +++
configs/stm32f746-ws/src/.gitignore | 2 +
configs/stm32f746-ws/src/Makefile | 45 +
.../stm32f746-ws/src/stm32_appinitialize.c | 65 ++
configs/stm32f746-ws/src/stm32_boot.c | 106 ++
configs/stm32f746-ws/src/stm32_spi.c | 238 +++++
configs/stm32f746-ws/src/stm32f746-ws.h | 106 ++
15 files changed, 2401 insertions(+)
create mode 100644 configs/stm32f746-ws/Kconfig
create mode 100644 configs/stm32f746-ws/include/board.h
create mode 100644 configs/stm32f746-ws/nsh/Make.defs
create mode 100644 configs/stm32f746-ws/nsh/defconfig
create mode 100644 configs/stm32f746-ws/nsh/setenv.sh
create mode 100644 configs/stm32f746-ws/scripts/flash.ld
create mode 100644 configs/stm32f746-ws/scripts/kernel-space.ld
create mode 100644 configs/stm32f746-ws/scripts/memory.ld
create mode 100644 configs/stm32f746-ws/scripts/user-space.ld
create mode 100644 configs/stm32f746-ws/src/.gitignore
create mode 100644 configs/stm32f746-ws/src/Makefile
create mode 100644 configs/stm32f746-ws/src/stm32_appinitialize.c
create mode 100644 configs/stm32f746-ws/src/stm32_boot.c
create mode 100644 configs/stm32f746-ws/src/stm32_spi.c
create mode 100644 configs/stm32f746-ws/src/stm32f746-ws.h
diff --git a/configs/stm32f746-ws/Kconfig b/configs/stm32f746-ws/Kconfig
new file mode 100644
index 0000000000..03e46e8266
--- /dev/null
+++ b/configs/stm32f746-ws/Kconfig
@@ -0,0 +1,8 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_STM32F746_WS
+
+endif # ARCH_BOARD_STM32F746_WS
diff --git a/configs/stm32f746-ws/include/board.h b/configs/stm32f746-ws/include/board.h
new file mode 100644
index 0000000000..ab822ce9d2
--- /dev/null
+++ b/configs/stm32f746-ws/include/board.h
@@ -0,0 +1,237 @@
+/************************************************************************************
+ * configs/stm32f746-ws/include/board.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ * Author: Mark Olsson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __CONFIG_STM32F746_WS_INCLUDE_BOARD_H
+#define __CONFIG_STM32F746_WS_INCLUDE_BOARD_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#ifndef __ASSEMBLY__
+# include
+#endif
+
+#ifdef __KERNEL__
+#include "stm32_rcc.h"
+#ifdef CONFIG_STM32F7_SDMMC1
+# include "stm32_sdmmc.h"
+#endif
+#endif
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Clocking *************************************************************************/
+/* The STM32F7 Discovery board provides the following clock sources:
+ *
+ * X1: 24 MHz oscillator for USB OTG HS PHY and camera module (daughter board)
+ * X2: 25 MHz oscillator for STM32F746NGH6 microcontroller and Ethernet PHY.
+ * X3: 32.768 KHz crystal for STM32F746NGH6 embedded RTC
+ *
+ * So we have these clock source available within the STM32
+ *
+ * HSI: 16 MHz RC factory-trimmed
+ * LSI: 32 KHz RC
+ * HSE: On-board crystal frequency is 25MHz
+ * LSE: 32.768 kHz
+ */
+
+#define STM32_BOARD_XTAL 8000000ul
+
+#define STM32_HSI_FREQUENCY 16000000ul
+#define STM32_LSI_FREQUENCY 32000
+#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
+#define STM32_LSE_FREQUENCY 32768
+
+/* Main PLL Configuration.
+ *
+ * PLL source is HSE = 8,000,000
+ *
+ * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
+ * Subject to:
+ *
+ * 2 <= PLLM <= 63
+ * 192 <= PLLN <= 432
+ * 192 MHz <= PLL_VCO <= 432MHz
+ *
+ * SYSCLK = PLL_VCO / PLLP
+ * Subject to
+ *
+ * PLLP = {2, 4, 6, 8}
+ * SYSCLK <= 216 MHz
+ *
+ * USB OTG FS, SDMMC and RNG Clock = PLL_VCO / PLLQ
+ * Subject to
+ * The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC
+ * and the random number generator need a frequency lower than or equal
+ * to 48 MHz to work correctly.
+ *
+ * 2 <= PLLQ <= 15
+ */
+
+/* Highest SYSCLK with USB OTG FS clock <= 48MHz
+ *
+ * PLL_VCO = (8,000,000 / 8) * 432 = 432 MHz
+ * SYSCLK = 432 MHz / 2 = 216 MHz
+ * USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48 MHz
+ */
+
+#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
+#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432)
+#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
+#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(9)
+
+#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 8) * 432)
+#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
+#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9)
+
+/* Several prescalers allow the configuration of the two AHB buses, the
+ * high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
+ * frequency of the two AHB buses is 216 MHz while the maximum frequency of
+ * the high-speed APB domains is 108 MHz. The maximum allowed frequency of
+ * the low-speed APB domain is 54 MHz.
+ */
+
+/* AHB clock (HCLK) is SYSCLK (216 MHz) */
+
+#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
+#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
+#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
+
+/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
+
+#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
+#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
+
+/* Timers driven from APB1 will be twice PCLK1 */
+
+#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
+
+/* APB2 clock (PCLK2) is HCLK/2 (108MHz) */
+
+#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
+#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
+
+/* Timers driven from APB2 will be twice PCLK2 */
+
+#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
+
+/* FLASH wait states
+ *
+ * --------- ---------- -----------
+ * VDD MAX SYSCLK WAIT STATES
+ * --------- ---------- -----------
+ * 1.7-2.1 V 180 MHz 8
+ * 2.1-2.4 V 216 MHz 9
+ * 2.4-2.7 V 216 MHz 8
+ * 2.7-3.6 V 216 MHz 7
+ * --------- ---------- -----------
+ */
+
+#define BOARD_FLASH_WAITSTATES 7
+
+/* Alternate function pin selections ************************************************/
+
+/* USART6:
+ *
+ * These configurations assume that you are using a standard Arduio RS-232 shield
+ * with the serial interface with RX on pin D0 and TX on pin D1:
+ *
+ * -------- ---------------
+ * STM32F7
+ * ARDUIONO FUNCTION GPIO
+ * -- ----- --------- -----
+ * DO RX USART6_RX PC7
+ * D1 TX USART6_TX PC6
+ * -- ----- --------- -----
+ */
+
+ #define GPIO_USART6_RX GPIO_USART6_RX_1
+ #define GPIO_USART6_TX GPIO_USART6_TX_1
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_boardinitialize
+ *
+ * Description:
+ * All STM32 architectures must provide the following entry point. This entry point
+ * is called early in the initialization -- after all memory has been configured
+ * and mapped but before any devices have been initialized.
+ *
+ ************************************************************************************/
+
+void stm32_boardinitialize(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __CONFIG_STM32F746_WS_INCLUDE_BOARD_H */
diff --git a/configs/stm32f746-ws/nsh/Make.defs b/configs/stm32f746-ws/nsh/Make.defs
new file mode 100644
index 0000000000..f2aa3a4d62
--- /dev/null
+++ b/configs/stm32f746-ws/nsh/Make.defs
@@ -0,0 +1,113 @@
+############################################################################
+# configs/stm32f746-ws/nsh/Make.defs
+#
+# Copyright (C) 2016 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
+
+LDSCRIPT = flash.ld
+
+ifeq ($(WINTOOL),y)
+ # Windows-native toolchains
+ DIRLINK = $(TOPDIR)/tools/copydir.sh
+ DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+ MKDEP = $(TOPDIR)/tools/mkwindeps.sh
+ ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+ ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+ ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
+else
+ # Linux/Cygwin-native toolchain
+ MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
+ ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+ ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+ ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
+endif
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+AR = $(ARCROSSDEV)ar rcs
+NM = $(ARCROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ ARCHOPTIMIZATION = -g
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+ ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
+ARCHWARNINGSXX = -Wall -Wshadow -Wundef
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+ASMEXT = .S
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-nuttx-elf-)
+ LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ LDFLAGS += -g
+endif
+
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
+HOSTLDFLAGS =
+
diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig
new file mode 100644
index 0000000000..76656ac848
--- /dev/null
+++ b/configs/stm32f746-ws/nsh/defconfig
@@ -0,0 +1,908 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Nuttx/ Configuration
+#
+
+#
+# Build Setup
+#
+# CONFIG_EXPERIMENTAL is not set
+# CONFIG_DEFAULT_SMALL is not set
+CONFIG_HOST_LINUX=y
+# CONFIG_HOST_OSX is not set
+# CONFIG_HOST_WINDOWS is not set
+# CONFIG_HOST_OTHER is not set
+
+#
+# Build Configuration
+#
+CONFIG_APPS_DIR="../apps"
+CONFIG_BUILD_FLAT=y
+# CONFIG_BUILD_2PASS is not set
+
+#
+# Binary Output Formats
+#
+# CONFIG_RRLOAD_BINARY is not set
+CONFIG_INTELHEX_BINARY=y
+# CONFIG_MOTOROLA_SREC is not set
+CONFIG_RAW_BINARY=y
+# CONFIG_UBOOT_UIMAGE is not set
+
+#
+# Customize Header Files
+#
+# CONFIG_ARCH_STDINT_H is not set
+# CONFIG_ARCH_STDBOOL_H is not set
+# CONFIG_ARCH_MATH_H is not set
+# CONFIG_ARCH_FLOAT_H is not set
+CONFIG_ARCH_STDARG_H=y
+# CONFIG_ARCH_DEBUG_H is not set
+
+#
+# Debug Options
+#
+# CONFIG_DEBUG is not set
+CONFIG_ARCH_HAVE_HEAPCHECK=y
+CONFIG_ARCH_HAVE_STACKCHECK=y
+# CONFIG_STACK_COLORATION is not set
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_ARCH_HAVE_CUSTOMOPT=y
+CONFIG_DEBUG_NOOPT=y
+# CONFIG_DEBUG_CUSTOMOPT is not set
+# CONFIG_DEBUG_FULLOPT is not set
+
+#
+# System Type
+#
+CONFIG_ARCH_ARM=y
+# CONFIG_ARCH_AVR is not set
+# CONFIG_ARCH_HC is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_RGMP is not set
+# CONFIG_ARCH_SH is not set
+# CONFIG_ARCH_SIM is not set
+# CONFIG_ARCH_X86 is not set
+# CONFIG_ARCH_Z16 is not set
+# CONFIG_ARCH_Z80 is not set
+CONFIG_ARCH="arm"
+
+#
+# ARM Options
+#
+# CONFIG_ARCH_CHIP_A1X is not set
+# CONFIG_ARCH_CHIP_C5471 is not set
+# CONFIG_ARCH_CHIP_CALYPSO is not set
+# CONFIG_ARCH_CHIP_DM320 is not set
+# CONFIG_ARCH_CHIP_EFM32 is not set
+# CONFIG_ARCH_CHIP_IMX1 is not set
+# CONFIG_ARCH_CHIP_IMX6 is not set
+# CONFIG_ARCH_CHIP_KINETIS is not set
+# CONFIG_ARCH_CHIP_KL is not set
+# CONFIG_ARCH_CHIP_LM is not set
+# CONFIG_ARCH_CHIP_TIVA is not set
+# CONFIG_ARCH_CHIP_LPC11XX is not set
+# CONFIG_ARCH_CHIP_LPC17XX is not set
+# CONFIG_ARCH_CHIP_LPC214X is not set
+# CONFIG_ARCH_CHIP_LPC2378 is not set
+# CONFIG_ARCH_CHIP_LPC31XX is not set
+# CONFIG_ARCH_CHIP_LPC43XX is not set
+# CONFIG_ARCH_CHIP_NUC1XX is not set
+# CONFIG_ARCH_CHIP_SAMA5 is not set
+# CONFIG_ARCH_CHIP_SAMD is not set
+# CONFIG_ARCH_CHIP_SAML is not set
+# CONFIG_ARCH_CHIP_SAM34 is not set
+# CONFIG_ARCH_CHIP_SAMV7 is not set
+# CONFIG_ARCH_CHIP_STM32 is not set
+CONFIG_ARCH_CHIP_STM32F7=y
+# CONFIG_ARCH_CHIP_STM32L4 is not set
+# CONFIG_ARCH_CHIP_STR71X is not set
+# CONFIG_ARCH_CHIP_TMS570 is not set
+# CONFIG_ARCH_CHIP_MOXART is not set
+# CONFIG_ARCH_ARM7TDMI is not set
+# CONFIG_ARCH_ARM926EJS is not set
+# CONFIG_ARCH_ARM920T is not set
+# CONFIG_ARCH_CORTEXM0 is not set
+# CONFIG_ARCH_CORTEXM3 is not set
+# CONFIG_ARCH_CORTEXM4 is not set
+CONFIG_ARCH_CORTEXM7=y
+# CONFIG_ARCH_CORTEXA5 is not set
+# CONFIG_ARCH_CORTEXA8 is not set
+# CONFIG_ARCH_CORTEXA9 is not set
+# CONFIG_ARCH_CORTEXR4 is not set
+# CONFIG_ARCH_CORTEXR4F is not set
+# CONFIG_ARCH_CORTEXR5 is not set
+# CONFIG_ARCH_CORTEX5F is not set
+# CONFIG_ARCH_CORTEXR7 is not set
+# CONFIG_ARCH_CORTEXR7F is not set
+CONFIG_ARCH_FAMILY="armv7-m"
+CONFIG_ARCH_CHIP="stm32f7"
+# CONFIG_ARM_TOOLCHAIN_IAR is not set
+CONFIG_ARM_TOOLCHAIN_GNU=y
+# CONFIG_ARMV7M_USEBASEPRI is not set
+CONFIG_ARCH_HAVE_CMNVECTOR=y
+CONFIG_ARMV7M_CMNVECTOR=y
+# CONFIG_ARMV7M_LAZYFPU is not set
+CONFIG_ARCH_HAVE_FPU=y
+CONFIG_ARCH_HAVE_DPFPU=y
+# CONFIG_ARCH_FPU is not set
+# CONFIG_ARCH_HAVE_TRUSTZONE is not set
+CONFIG_ARM_HAVE_MPU_UNIFIED=y
+# CONFIG_ARM_MPU is not set
+
+#
+# ARMV7M Configuration Options
+#
+CONFIG_ARMV7M_HAVE_ICACHE=y
+CONFIG_ARMV7M_HAVE_DCACHE=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
+CONFIG_ARMV7M_HAVE_ITCM=y
+CONFIG_ARMV7M_HAVE_DTCM=y
+# CONFIG_ARMV7M_ITCM is not set
+CONFIG_ARMV7M_DTCM=y
+# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set
+# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
+# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
+# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
+CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y
+CONFIG_ARMV7M_HAVE_STACKCHECK=y
+# CONFIG_ARMV7M_STACKCHECK is not set
+# CONFIG_ARMV7M_ITMSYSLOG is not set
+# CONFIG_SERIAL_TERMIOS is not set
+
+#
+# STM32 F7 Configuration Options
+#
+# CONFIG_ARCH_CHIP_STM32F745 is not set
+CONFIG_ARCH_CHIP_STM32F746=y
+# CONFIG_ARCH_CHIP_STM32F756 is not set
+CONFIG_STM32F7_STM32F74XX=y
+# CONFIG_STM32F7_STM32F75XX is not set
+# CONFIG_STM32F7_FLASH_512KB is not set
+CONFIG_STM32F7_FLASH_1024KB=y
+
+#
+# STM32 Peripheral Support
+#
+CONFIG_STM32F7_HAVE_LTDC=y
+# CONFIG_STM32F7_ADC is not set
+# CONFIG_STM32F7_CAN is not set
+# CONFIG_STM32F7_DAC is not set
+# CONFIG_STM32F7_DMA is not set
+# CONFIG_STM32F7_I2C is not set
+# CONFIG_STM32F7_SAI is not set
+# CONFIG_STM32F7_SPI is not set
+CONFIG_STM32F7_USART=y
+# CONFIG_STM32F7_ADC1 is not set
+# CONFIG_STM32F7_ADC2 is not set
+# CONFIG_STM32F7_ADC3 is not set
+# CONFIG_STM32F7_BKPSRAM is not set
+# CONFIG_STM32F7_CAN1 is not set
+# CONFIG_STM32F7_CAN2 is not set
+# CONFIG_STM32F7_CEC is not set
+# CONFIG_STM32F7_CRC is not set
+# CONFIG_STM32F7_CRYP is not set
+# CONFIG_STM32F7_DMA1 is not set
+# CONFIG_STM32F7_DMA2 is not set
+# CONFIG_STM32F7_DAC1 is not set
+# CONFIG_STM32F7_DAC2 is not set
+# CONFIG_STM32F7_DCMI is not set
+# CONFIG_STM32F7_ETHMAC is not set
+# CONFIG_STM32F7_FSMC is not set
+# CONFIG_STM32F7_I2C1 is not set
+# CONFIG_STM32F7_I2C2 is not set
+# CONFIG_STM32F7_I2C3 is not set
+# CONFIG_STM32F7_LPTIM1 is not set
+# CONFIG_STM32F7_LTDC is not set
+# CONFIG_STM32F7_DMA2D is not set
+# CONFIG_STM32F7_OTGFS is not set
+# CONFIG_STM32F7_OTGHS is not set
+# CONFIG_STM32F7_QUADSPI is not set
+# CONFIG_STM32F7_SAI1 is not set
+# CONFIG_STM32F7_RNG is not set
+# CONFIG_STM32F7_SAI2 is not set
+# CONFIG_STM32F7_SDMMC1 is not set
+# CONFIG_STM32F7_SPDIFRX is not set
+# CONFIG_STM32F7_SPI1 is not set
+# CONFIG_STM32F7_SPI2 is not set
+# CONFIG_STM32F7_SPI3 is not set
+# CONFIG_STM32F7_SPI4 is not set
+# CONFIG_STM32F7_SPI5 is not set
+# CONFIG_STM32F7_SPI6 is not set
+# CONFIG_STM32F7_TIM1 is not set
+# CONFIG_STM32F7_TIM2 is not set
+# CONFIG_STM32F7_TIM3 is not set
+# CONFIG_STM32F7_TIM4 is not set
+# CONFIG_STM32F7_TIM5 is not set
+# CONFIG_STM32F7_TIM6 is not set
+# CONFIG_STM32F7_TIM7 is not set
+# CONFIG_STM32F7_TIM8 is not set
+# CONFIG_STM32F7_TIM9 is not set
+# CONFIG_STM32F7_TIM10 is not set
+# CONFIG_STM32F7_TIM11 is not set
+# CONFIG_STM32F7_TIM12 is not set
+# CONFIG_STM32F7_TIM13 is not set
+# CONFIG_STM32F7_TIM14 is not set
+# CONFIG_STM32F7_TIM15 is not set
+# CONFIG_STM32F7_USART1 is not set
+# CONFIG_STM32F7_USART2 is not set
+# CONFIG_STM32F7_USART3 is not set
+# CONFIG_STM32F7_UART4 is not set
+# CONFIG_STM32F7_UART5 is not set
+CONFIG_STM32F7_USART6=y
+# CONFIG_STM32F7_UART7 is not set
+# CONFIG_STM32F7_UART8 is not set
+# CONFIG_STM32F7_IWDG is not set
+# CONFIG_STM32F7_WWDG is not set
+# CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set
+
+#
+# Architecture Options
+#
+# CONFIG_ARCH_NOINTC is not set
+# CONFIG_ARCH_VECNOTIRQ is not set
+# CONFIG_ARCH_DMA is not set
+CONFIG_ARCH_HAVE_IRQPRIO=y
+# CONFIG_ARCH_L2CACHE is not set
+# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set
+# CONFIG_ARCH_HAVE_ADDRENV is not set
+# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set
+# CONFIG_ARCH_HAVE_MULTICPU is not set
+CONFIG_ARCH_HAVE_VFORK=y
+# CONFIG_ARCH_HAVE_MMU is not set
+CONFIG_ARCH_HAVE_MPU=y
+# CONFIG_ARCH_NAND_HWECC is not set
+# CONFIG_ARCH_HAVE_EXTCLK is not set
+# CONFIG_ARCH_HAVE_POWEROFF is not set
+# CONFIG_ARCH_HAVE_RESET is not set
+# CONFIG_ARCH_USE_MPU is not set
+# CONFIG_ARCH_IRQPRIO is not set
+CONFIG_ARCH_STACKDUMP=y
+# CONFIG_ENDIAN_BIG is not set
+# CONFIG_ARCH_IDLE_CUSTOM is not set
+# CONFIG_ARCH_HAVE_RAMFUNCS is not set
+CONFIG_ARCH_HAVE_RAMVECTORS=y
+# CONFIG_ARCH_RAMVECTORS is not set
+
+#
+# Board Settings
+#
+CONFIG_BOARD_LOOPSPERMSEC=43103
+# CONFIG_ARCH_CALIBRATION is not set
+
+#
+# Interrupt options
+#
+CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
+CONFIG_ARCH_INTERRUPTSTACK=0
+CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y
+# CONFIG_ARCH_HIPRI_INTERRUPT is not set
+
+#
+# Boot options
+#
+# CONFIG_BOOT_RUNFROMEXTSRAM is not set
+CONFIG_BOOT_RUNFROMFLASH=y
+# CONFIG_BOOT_RUNFROMISRAM is not set
+# CONFIG_BOOT_RUNFROMSDRAM is not set
+# CONFIG_BOOT_COPYTORAM is not set
+
+#
+# Boot Memory Configuration
+#
+CONFIG_RAM_START=0x20010000
+CONFIG_RAM_SIZE=245760
+# CONFIG_ARCH_HAVE_SDRAM is not set
+
+#
+# Board Selection
+#
+# CONFIG_ARCH_BOARD_STM32F746G_DISCO is not set
+CONFIG_ARCH_BOARD_STM32F746_WS=y
+# CONFIG_ARCH_BOARD_CUSTOM is not set
+CONFIG_ARCH_BOARD="stm32f746-ws"
+
+#
+# Common Board Options
+#
+# CONFIG_ARCH_HAVE_LEDS is not set
+# CONFIG_ARCH_LEDS is not set
+# CONFIG_ARCH_HAVE_BUTTONS is not set
+# CONFIG_ARCH_BUTTONS is not set
+# CONFIG_ARCH_HAVE_IRQBUTTONS is not set
+# CONFIG_ARCH_IRQBUTTONS is not set
+CONFIG_NSH_MMCSDMINOR=0
+
+#
+# Board-Specific Options
+#
+# CONFIG_LIB_BOARDCTL is not set
+
+#
+# RTOS Features
+#
+CONFIG_DISABLE_OS_API=y
+# CONFIG_DISABLE_POSIX_TIMERS is not set
+# CONFIG_DISABLE_PTHREAD is not set
+# CONFIG_DISABLE_SIGNALS is not set
+# CONFIG_DISABLE_MQUEUE is not set
+# CONFIG_DISABLE_ENVIRON is not set
+
+#
+# Clocks and Timers
+#
+CONFIG_USEC_PER_TICK=10000
+# CONFIG_SYSTEM_TIME64 is not set
+# CONFIG_CLOCK_MONOTONIC is not set
+# CONFIG_JULIAN_TIME is not set
+CONFIG_START_YEAR=2011
+CONFIG_START_MONTH=12
+CONFIG_START_DAY=6
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_PREALLOC_WDOGS=4
+CONFIG_WDOG_INTRESERVE=0
+CONFIG_PREALLOC_TIMERS=4
+
+#
+# Tasks and Scheduling
+#
+# CONFIG_INIT_NONE is not set
+CONFIG_INIT_ENTRYPOINT=y
+# CONFIG_INIT_FILEPATH is not set
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_RR_INTERVAL=200
+# CONFIG_SCHED_SPORADIC is not set
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_MAX_TASKS=16
+# CONFIG_SCHED_HAVE_PARENT is not set
+CONFIG_SCHED_WAITPID=y
+
+#
+# Pthread Options
+#
+# CONFIG_MUTEX_TYPES is not set
+CONFIG_NPTHREAD_KEYS=4
+
+#
+# Performance Monitoring
+#
+# CONFIG_SCHED_CPULOAD is not set
+# CONFIG_SCHED_INSTRUMENTATION is not set
+
+#
+# Files and I/O
+#
+CONFIG_DEV_CONSOLE=y
+# CONFIG_FDCLONE_DISABLE is not set
+# CONFIG_FDCLONE_STDIO is not set
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NAME_MAX=32
+# CONFIG_PRIORITY_INHERITANCE is not set
+
+#
+# RTOS hooks
+#
+# CONFIG_BOARD_INITIALIZE is not set
+# CONFIG_SCHED_STARTHOOK is not set
+# CONFIG_SCHED_ATEXIT is not set
+# CONFIG_SCHED_ONEXIT is not set
+
+#
+# Signal Numbers
+#
+CONFIG_SIG_SIGUSR1=1
+CONFIG_SIG_SIGUSR2=2
+CONFIG_SIG_SIGALARM=3
+CONFIG_SIG_SIGCONDTIMEDOUT=16
+
+#
+# POSIX Message Queue Options
+#
+CONFIG_PREALLOC_MQ_MSGS=4
+CONFIG_MQ_MAXMSGSIZE=32
+# CONFIG_MODULE is not set
+
+#
+# Work queue support
+#
+# CONFIG_SCHED_WORKQUEUE is not set
+# CONFIG_SCHED_HPWORK is not set
+# CONFIG_SCHED_LPWORK is not set
+
+#
+# Stack and heap information
+#
+CONFIG_IDLETHREAD_STACKSIZE=1024
+CONFIG_USERMAIN_STACKSIZE=2048
+CONFIG_PTHREAD_STACK_MIN=256
+CONFIG_PTHREAD_STACK_DEFAULT=2048
+# CONFIG_LIB_SYSCALL is not set
+
+#
+# Device Drivers
+#
+CONFIG_DISABLE_POLL=y
+CONFIG_DEV_NULL=y
+# CONFIG_DEV_ZERO is not set
+# CONFIG_DEV_LOOP is not set
+
+#
+# Buffering
+#
+# CONFIG_DRVR_WRITEBUFFER is not set
+# CONFIG_DRVR_READAHEAD is not set
+# CONFIG_RAMDISK is not set
+# CONFIG_CAN is not set
+# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set
+# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set
+# CONFIG_PWM is not set
+CONFIG_ARCH_HAVE_I2CRESET=y
+# CONFIG_I2C is not set
+CONFIG_SPI=y
+# CONFIG_SPI_SLAVE is not set
+CONFIG_SPI_EXCHANGE=y
+# CONFIG_SPI_CMDDATA is not set
+# CONFIG_SPI_CALLBACK is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_HWFEATURES is not set
+# CONFIG_SPI_CRCGENERATION is not set
+# CONFIG_I2S is not set
+
+#
+# Timer Driver Support
+#
+# CONFIG_TIMER is not set
+# CONFIG_RTC is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_ANALOG is not set
+# CONFIG_AUDIO_DEVICES is not set
+# CONFIG_VIDEO_DEVICES is not set
+# CONFIG_BCH is not set
+# CONFIG_INPUT is not set
+# CONFIG_IOEXPANDER is not set
+# CONFIG_LCD is not set
+
+#
+# LED Support
+#
+# CONFIG_USERLED is not set
+# CONFIG_RGBLED is not set
+# CONFIG_PCA9635PW is not set
+# CONFIG_MMCSD is not set
+# CONFIG_MODEM is not set
+# CONFIG_MTD is not set
+# CONFIG_EEPROM is not set
+# CONFIG_PIPES is not set
+# CONFIG_PM is not set
+# CONFIG_POWER is not set
+# CONFIG_SENSORS is not set
+# CONFIG_SERCOMM_CONSOLE is not set
+CONFIG_SERIAL=y
+# CONFIG_DEV_LOWCONSOLE is not set
+# CONFIG_16550_UART is not set
+# CONFIG_ARCH_HAVE_UART is not set
+# CONFIG_ARCH_HAVE_UART0 is not set
+# CONFIG_ARCH_HAVE_UART1 is not set
+# CONFIG_ARCH_HAVE_UART2 is not set
+# CONFIG_ARCH_HAVE_UART3 is not set
+# CONFIG_ARCH_HAVE_UART4 is not set
+# CONFIG_ARCH_HAVE_UART5 is not set
+# CONFIG_ARCH_HAVE_UART6 is not set
+# CONFIG_ARCH_HAVE_UART7 is not set
+# CONFIG_ARCH_HAVE_UART8 is not set
+# CONFIG_ARCH_HAVE_SCI0 is not set
+# CONFIG_ARCH_HAVE_SCI1 is not set
+# CONFIG_ARCH_HAVE_USART0 is not set
+# CONFIG_ARCH_HAVE_USART1 is not set
+# CONFIG_ARCH_HAVE_USART2 is not set
+# CONFIG_ARCH_HAVE_USART3 is not set
+# CONFIG_ARCH_HAVE_USART4 is not set
+# CONFIG_ARCH_HAVE_USART5 is not set
+CONFIG_ARCH_HAVE_USART6=y
+# CONFIG_ARCH_HAVE_USART7 is not set
+# CONFIG_ARCH_HAVE_USART8 is not set
+# CONFIG_ARCH_HAVE_OTHER_UART is not set
+
+#
+# USART Configuration
+#
+CONFIG_USART6_ISUART=y
+CONFIG_MCU_SERIAL=y
+CONFIG_STANDARD_SERIAL=y
+# CONFIG_SERIAL_IFLOWCONTROL is not set
+# CONFIG_SERIAL_OFLOWCONTROL is not set
+# CONFIG_SERIAL_DMA is not set
+CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y
+CONFIG_USART6_SERIAL_CONSOLE=y
+# CONFIG_OTHER_SERIAL_CONSOLE is not set
+# CONFIG_NO_SERIAL_CONSOLE is not set
+
+#
+# USART6 Configuration
+#
+CONFIG_USART6_RXBUFSIZE=256
+CONFIG_USART6_TXBUFSIZE=256
+CONFIG_USART6_BAUD=115200
+CONFIG_USART6_BITS=8
+CONFIG_USART6_PARITY=0
+CONFIG_USART6_2STOP=0
+# CONFIG_USART6_IFLOWCONTROL is not set
+# CONFIG_USART6_OFLOWCONTROL is not set
+# CONFIG_USART6_DMA is not set
+# CONFIG_USBDEV is not set
+# CONFIG_USBHOST is not set
+# CONFIG_DRIVERS_WIRELESS is not set
+
+#
+# System Logging Device Options
+#
+
+#
+# System Logging
+#
+# CONFIG_RAMLOG is not set
+# CONFIG_SYSLOG_CONSOLE is not set
+
+#
+# Networking Support
+#
+# CONFIG_ARCH_HAVE_NET is not set
+# CONFIG_ARCH_HAVE_PHY is not set
+# CONFIG_NET is not set
+
+#
+# Crypto API
+#
+# CONFIG_CRYPTO is not set
+
+#
+# File Systems
+#
+
+#
+# File system configuration
+#
+# CONFIG_DISABLE_MOUNTPOINT is not set
+# CONFIG_FS_AUTOMOUNTER is not set
+# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set
+# CONFIG_FS_READABLE is not set
+# CONFIG_FS_WRITABLE is not set
+# CONFIG_FS_NAMED_SEMAPHORES is not set
+CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
+# CONFIG_FS_RAMMAP is not set
+# CONFIG_FS_FAT is not set
+# CONFIG_FS_NXFFS is not set
+# CONFIG_FS_ROMFS is not set
+# CONFIG_FS_TMPFS is not set
+# CONFIG_FS_SMARTFS is not set
+# CONFIG_FS_BINFS is not set
+# CONFIG_FS_PROCFS is not set
+# CONFIG_FS_UNIONFS is not set
+
+#
+# System Logging
+#
+# CONFIG_SYSLOG is not set
+# CONFIG_SYSLOG_TIMESTAMP is not set
+
+#
+# Graphics Support
+#
+# CONFIG_NX is not set
+
+#
+# Memory Management
+#
+# CONFIG_MM_SMALL is not set
+CONFIG_MM_REGIONS=2
+# CONFIG_ARCH_HAVE_HEAP2 is not set
+# CONFIG_GRAN is not set
+
+#
+# Audio Support
+#
+# CONFIG_AUDIO is not set
+
+#
+# Wireless Support
+#
+
+#
+# Binary Loader
+#
+# CONFIG_BINFMT_DISABLE is not set
+# CONFIG_BINFMT_EXEPATH is not set
+# CONFIG_NXFLAT is not set
+# CONFIG_ELF is not set
+CONFIG_BUILTIN=y
+# CONFIG_PIC is not set
+# CONFIG_SYMTAB_ORDEREDBYNAME is not set
+
+#
+# Library Routines
+#
+
+#
+# Standard C Library Options
+#
+CONFIG_STDIO_BUFFER_SIZE=64
+CONFIG_STDIO_LINEBUFFER=y
+CONFIG_NUNGET_CHARS=2
+CONFIG_LIB_HOMEDIR="/"
+# CONFIG_LIBM is not set
+# CONFIG_NOPRINTF_FIELDWIDTH is not set
+# CONFIG_LIBC_FLOATINGPOINT is not set
+CONFIG_LIBC_LONG_LONG=y
+# CONFIG_LIBC_IOCTL_VARIADIC is not set
+CONFIG_LIB_RAND_ORDER=1
+# CONFIG_EOL_IS_CR is not set
+# CONFIG_EOL_IS_LF is not set
+# CONFIG_EOL_IS_BOTH_CRLF is not set
+CONFIG_EOL_IS_EITHER_CRLF=y
+# CONFIG_LIBC_EXECFUNCS is not set
+CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024
+CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048
+# CONFIG_LIBC_STRERROR is not set
+# CONFIG_LIBC_PERROR_STDOUT is not set
+CONFIG_ARCH_LOWPUTC=y
+# CONFIG_LIBC_LOCALTIME is not set
+# CONFIG_TIME_EXTENDED is not set
+CONFIG_LIB_SENDFILE_BUFSIZE=512
+# CONFIG_ARCH_ROMGETC is not set
+# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
+CONFIG_ARCH_HAVE_TLS=y
+# CONFIG_TLS is not set
+# CONFIG_LIBC_NETDB is not set
+
+#
+# Non-standard Library Support
+#
+# CONFIG_LIB_KBDCODEC is not set
+# CONFIG_LIB_SLCDCODEC is not set
+
+#
+# Basic CXX Support
+#
+# CONFIG_C99_BOOL8 is not set
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+# CONFIG_CXX_NEWLONG is not set
+
+#
+# uClibc++ Standard C++ Library
+#
+# CONFIG_UCLIBCXX is not set
+
+#
+# Application Configuration
+#
+
+#
+# Built-In Applications
+#
+CONFIG_BUILTIN_PROXY_STACKSIZE=1024
+
+#
+# CAN Utilities
+#
+
+#
+# Examples
+#
+# CONFIG_EXAMPLES_BUTTONS is not set
+# CONFIG_EXAMPLES_CHAT is not set
+# CONFIG_EXAMPLES_CONFIGDATA is not set
+# CONFIG_EXAMPLES_CPUHOG is not set
+# CONFIG_EXAMPLES_CXXTEST is not set
+# CONFIG_EXAMPLES_DHCPD is not set
+# CONFIG_EXAMPLES_ELF is not set
+# CONFIG_EXAMPLES_FTPC is not set
+# CONFIG_EXAMPLES_FTPD is not set
+# CONFIG_EXAMPLES_HELLO is not set
+# CONFIG_EXAMPLES_HELLOXX is not set
+# CONFIG_EXAMPLES_JSON is not set
+# CONFIG_EXAMPLES_HIDKBD is not set
+# CONFIG_EXAMPLES_KEYPADTEST is not set
+# CONFIG_EXAMPLES_IGMP is not set
+# CONFIG_EXAMPLES_MEDIA is not set
+# CONFIG_EXAMPLES_MM is not set
+# CONFIG_EXAMPLES_MODBUS is not set
+# CONFIG_EXAMPLES_MOUNT is not set
+# CONFIG_EXAMPLES_NRF24L01TERM is not set
+CONFIG_EXAMPLES_NSH=y
+# CONFIG_EXAMPLES_NSH_CXXINITIALIZE is not set
+# CONFIG_EXAMPLES_NULL is not set
+# CONFIG_EXAMPLES_NX is not set
+# CONFIG_EXAMPLES_NXTERM is not set
+# CONFIG_EXAMPLES_NXFFS is not set
+# CONFIG_EXAMPLES_NXHELLO is not set
+# CONFIG_EXAMPLES_NXIMAGE is not set
+# CONFIG_EXAMPLES_NXLINES is not set
+# CONFIG_EXAMPLES_NXTEXT is not set
+# CONFIG_EXAMPLES_OSTEST is not set
+# CONFIG_EXAMPLES_PCA9635 is not set
+# CONFIG_EXAMPLES_PIPE is not set
+# CONFIG_EXAMPLES_PPPD is not set
+# CONFIG_EXAMPLES_POSIXSPAWN is not set
+# CONFIG_EXAMPLES_RGBLED is not set
+# CONFIG_EXAMPLES_RGMP is not set
+# CONFIG_EXAMPLES_SENDMAIL is not set
+# CONFIG_EXAMPLES_SERIALBLASTER is not set
+# CONFIG_EXAMPLES_SERIALRX is not set
+# CONFIG_EXAMPLES_SERLOOP is not set
+# CONFIG_EXAMPLES_SLCD is not set
+# CONFIG_EXAMPLES_SMART_TEST is not set
+# CONFIG_EXAMPLES_SMART is not set
+# CONFIG_EXAMPLES_SMP is not set
+# CONFIG_EXAMPLES_TCPECHO is not set
+# CONFIG_EXAMPLES_TELNETD is not set
+# CONFIG_EXAMPLES_TIFF is not set
+# CONFIG_EXAMPLES_TOUCHSCREEN is not set
+# CONFIG_EXAMPLES_WEBSERVER is not set
+# CONFIG_EXAMPLES_USBTERM is not set
+# CONFIG_EXAMPLES_WATCHDOG is not set
+
+#
+# File System Utilities
+#
+# CONFIG_FSUTILS_INIFILE is not set
+
+#
+# GPS Utilities
+#
+# CONFIG_GPSUTILS_MINMEA_LIB is not set
+
+#
+# Graphics Support
+#
+# CONFIG_TIFF is not set
+# CONFIG_GRAPHICS_TRAVELER is not set
+
+#
+# Interpreters
+#
+# CONFIG_INTERPRETERS_FICL is not set
+# CONFIG_INTERPRETERS_PCODE is not set
+# CONFIG_INTERPRETERS_MICROPYTHON is not set
+
+#
+# FreeModBus
+#
+# CONFIG_MODBUS is not set
+
+#
+# Network Utilities
+#
+# CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_FTPC is not set
+# CONFIG_NETUTILS_JSON is not set
+# CONFIG_NETUTILS_SMTP is not set
+
+#
+# NSH Library
+#
+CONFIG_NSH_LIBRARY=y
+# CONFIG_NSH_MOTD is not set
+
+#
+# Command Line Configuration
+#
+CONFIG_NSH_READLINE=y
+# CONFIG_NSH_CLE is not set
+CONFIG_NSH_LINELEN=64
+# CONFIG_NSH_DISABLE_SEMICOLON is not set
+CONFIG_NSH_CMDPARMS=y
+CONFIG_NSH_MAXARGUMENTS=6
+CONFIG_NSH_ARGCAT=y
+CONFIG_NSH_NESTDEPTH=3
+# CONFIG_NSH_DISABLEBG is not set
+CONFIG_NSH_BUILTIN_APPS=y
+
+#
+# Disable Individual commands
+#
+# CONFIG_NSH_DISABLE_ADDROUTE is not set
+# CONFIG_NSH_DISABLE_BASENAME is not set
+# CONFIG_NSH_DISABLE_CAT is not set
+# CONFIG_NSH_DISABLE_CD is not set
+# CONFIG_NSH_DISABLE_CP is not set
+# CONFIG_NSH_DISABLE_CMP is not set
+CONFIG_NSH_DISABLE_DATE=y
+# CONFIG_NSH_DISABLE_DD is not set
+# CONFIG_NSH_DISABLE_DF is not set
+# CONFIG_NSH_DISABLE_DELROUTE is not set
+# CONFIG_NSH_DISABLE_DIRNAME is not set
+# CONFIG_NSH_DISABLE_ECHO is not set
+# CONFIG_NSH_DISABLE_EXEC is not set
+# CONFIG_NSH_DISABLE_EXIT is not set
+# CONFIG_NSH_DISABLE_FREE is not set
+# CONFIG_NSH_DISABLE_GET is not set
+# CONFIG_NSH_DISABLE_HELP is not set
+# CONFIG_NSH_DISABLE_HEXDUMP is not set
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+# CONFIG_NSH_DISABLE_KILL is not set
+# CONFIG_NSH_DISABLE_LOSETUP is not set
+CONFIG_NSH_DISABLE_LOSMART=y
+# CONFIG_NSH_DISABLE_LS is not set
+# CONFIG_NSH_DISABLE_MB is not set
+# CONFIG_NSH_DISABLE_MKDIR is not set
+# CONFIG_NSH_DISABLE_MKFIFO is not set
+# CONFIG_NSH_DISABLE_MKRD is not set
+# CONFIG_NSH_DISABLE_MH is not set
+# CONFIG_NSH_DISABLE_MOUNT is not set
+# CONFIG_NSH_DISABLE_MV is not set
+# CONFIG_NSH_DISABLE_MW is not set
+# CONFIG_NSH_DISABLE_PS is not set
+# CONFIG_NSH_DISABLE_PUT is not set
+# CONFIG_NSH_DISABLE_PWD is not set
+# CONFIG_NSH_DISABLE_RM is not set
+# CONFIG_NSH_DISABLE_RMDIR is not set
+# CONFIG_NSH_DISABLE_SET is not set
+# CONFIG_NSH_DISABLE_SH is not set
+# CONFIG_NSH_DISABLE_SLEEP is not set
+# CONFIG_NSH_DISABLE_TIME is not set
+# CONFIG_NSH_DISABLE_TEST is not set
+# CONFIG_NSH_DISABLE_UMOUNT is not set
+# CONFIG_NSH_DISABLE_UNAME is not set
+# CONFIG_NSH_DISABLE_UNSET is not set
+# CONFIG_NSH_DISABLE_USLEEP is not set
+# CONFIG_NSH_DISABLE_WGET is not set
+# CONFIG_NSH_DISABLE_XD is not set
+
+#
+# Configure Command Options
+#
+CONFIG_NSH_CMDOPT_DF_H=y
+CONFIG_NSH_CODECS_BUFSIZE=128
+CONFIG_NSH_CMDOPT_HEXDUMP=y
+CONFIG_NSH_FILEIOSIZE=512
+
+#
+# Scripting Support
+#
+# CONFIG_NSH_DISABLESCRIPT is not set
+# CONFIG_NSH_DISABLE_ITEF is not set
+# CONFIG_NSH_DISABLE_LOOPS is not set
+
+#
+# Console Configuration
+#
+CONFIG_NSH_CONSOLE=y
+# CONFIG_NSH_ALTCONDEV is not set
+# CONFIG_NSH_ARCHINIT is not set
+# CONFIG_NSH_LOGIN is not set
+# CONFIG_NSH_CONSOLE_LOGIN is not set
+
+#
+# NxWidgets/NxWM
+#
+
+#
+# Platform-specific Support
+#
+# CONFIG_PLATFORM_CONFIGDATA is not set
+
+#
+# System Libraries and NSH Add-Ons
+#
+# CONFIG_SYSTEM_FREE is not set
+# CONFIG_SYSTEM_CLE is not set
+# CONFIG_SYSTEM_CUTERM is not set
+# CONFIG_SYSTEM_INSTALL is not set
+# CONFIG_SYSTEM_HEX2BIN is not set
+# CONFIG_SYSTEM_HEXED is not set
+# CONFIG_SYSTEM_RAMTEST is not set
+CONFIG_READLINE_HAVE_EXTMATCH=y
+CONFIG_SYSTEM_READLINE=y
+CONFIG_READLINE_ECHO=y
+# CONFIG_READLINE_TABCOMPLETION is not set
+# CONFIG_READLINE_CMD_HISTORY is not set
+# CONFIG_SYSTEM_SUDOKU is not set
+# CONFIG_SYSTEM_VI is not set
+# CONFIG_SYSTEM_UBLOXMODEM is not set
+# CONFIG_SYSTEM_ZMODEM is not set
diff --git a/configs/stm32f746-ws/nsh/setenv.sh b/configs/stm32f746-ws/nsh/setenv.sh
new file mode 100644
index 0000000000..2d66398c3b
--- /dev/null
+++ b/configs/stm32f746-ws/nsh/setenv.sh
@@ -0,0 +1,77 @@
+#!/bin/bash
+# configs/stm32f746-ws/nsh/setenv.sh
+#
+# Copyright (C) 2016 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+if [ "$_" = "$0" ] ; then
+ echo "You must source this script, not run it!" 1>&2
+ exit 1
+fi
+
+WD=`pwd`
+if [ ! -x "setenv.sh" ]; then
+ echo "This script must be executed from the top-level NuttX build directory"
+ exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then
+ export PATH_ORIG="${PATH}"
+fi
+
+# This is the Cygwin path to the location where I installed the Atmel GCC
+# toolchain under Windows. You will also have to edit this if you install
+# this toolchain in any other location
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin"
+
+# This is the Cygwin path to the location where I installed the CodeSourcery
+# toolchain under windows. You will also have to edit this if you install
+# the CodeSourcery toolchain in any other location
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
+# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
+
+# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors"
+# You can this free toolchain here https://launchpad.net/gcc-arm-embedded
+export TOOLCHAIN_BIN="/cygdrive/c/Users/Public/tools/bin"
+
+# This is the path to the location where I installed the devkitARM toolchain
+# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin"
+
+# This is the Cygwin path to the location where I build the buildroot
+# toolchain.
+# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin"
+
+# Add the path to the toolchain to the PATH varialble
+export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
+
+echo "PATH : ${PATH}"
diff --git a/configs/stm32f746-ws/scripts/flash.ld b/configs/stm32f746-ws/scripts/flash.ld
new file mode 100644
index 0000000000..09378918de
--- /dev/null
+++ b/configs/stm32f746-ws/scripts/flash.ld
@@ -0,0 +1,147 @@
+/****************************************************************************
+ * configs/stm32f746-ws/scripts/flash.ld
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Modified 11/4/2013 for STM32F429 support
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The STM32F746NGH6 has 1024Kb of main FLASH memory. This FLASH memory can
+ * be accessed from either the AXIM interface at address 0x0800:0000 or from
+ * the ITCM interface at address 0x0020:0000.
+ *
+ * Additional information, including the option bytes, is available at at
+ * FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM).
+ *
+ * In the STM32F746NGH6, two different boot spaces can be selected through
+ * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and
+ * BOOT_ADD1 option bytes:
+ *
+ * 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].
+ * ST programmed value: Flash on ITCM at 0x0020:0000
+ * 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
+ * ST programmed value: System bootloader at 0x0010:0000
+ *
+ * NuttX does not modify these option byes. On the unmodified STM32F746G
+ * DISCO board, the BOOT0 pin is at ground so by default, the STM32 will boot
+ * to address 0x0020:0000 in ITCM FLASH.
+ *
+ * The STM32F746NGH6 also has 320Kb of data SRAM (in addition to ITCM SRAM).
+ * SRAM is split up into three blocks:
+ *
+ * 1) 64Kb of DTCM SRM beginning at address 0x2000:0000
+ * 2) 240Kb of SRAM1 beginning at address 0x2001:0000
+ * 3) 16Kb of SRAM2 beginning at address 0x2004:c000
+ *
+ * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
+ * where the code expects to begin execution by jumping to the entry point in
+ * the 0x0800:0000 address range.
+ */
+
+MEMORY
+{
+ itcm (rwx) : ORIGIN = 0x00200000, LENGTH = 1024K
+ flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+ dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+ sram1 (rwx) : ORIGIN = 0x20010000, LENGTH = 240K
+ sram2 (rwx) : ORIGIN = 0x2004c000, LENGTH = 16K
+}
+
+OUTPUT_ARCH(arm)
+EXTERN(_vectors)
+ENTRY(_stext)
+SECTIONS
+{
+ .text : {
+ _stext = ABSOLUTE(.);
+ *(.vectors)
+ *(.text .text.*)
+ *(.fixup)
+ *(.gnu.warning)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.got)
+ *(.gcc_except_table)
+ *(.gnu.linkonce.r.*)
+ _etext = ABSOLUTE(.);
+ } > flash
+
+ .init_section : {
+ _sinit = ABSOLUTE(.);
+ *(.init_array .init_array.*)
+ _einit = ABSOLUTE(.);
+ } > flash
+
+ .ARM.extab : {
+ *(.ARM.extab*)
+ } > flash
+
+ __exidx_start = ABSOLUTE(.);
+ .ARM.exidx : {
+ *(.ARM.exidx*)
+ } > flash
+ __exidx_end = ABSOLUTE(.);
+
+ _eronly = ABSOLUTE(.);
+
+ .data : {
+ _sdata = ABSOLUTE(.);
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ CONSTRUCTORS
+ _edata = ABSOLUTE(.);
+ } > sram1 AT > flash
+
+ .bss : {
+ _sbss = ABSOLUTE(.);
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ _ebss = ABSOLUTE(.);
+ } > sram1
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_info 0 : { *(.debug_info) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ .debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/configs/stm32f746-ws/scripts/kernel-space.ld b/configs/stm32f746-ws/scripts/kernel-space.ld
new file mode 100644
index 0000000000..8d471a57ba
--- /dev/null
+++ b/configs/stm32f746-ws/scripts/kernel-space.ld
@@ -0,0 +1,109 @@
+/****************************************************************************
+ * configs/stm32f746-ws/scripts/kernel-space.ld
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* NOTE: This depends on the memory.ld script having been included prior to
+ * this script.
+ */
+
+OUTPUT_ARCH(arm)
+ENTRY(_stext)
+SECTIONS
+{
+ .text : {
+ _stext = ABSOLUTE(.);
+ *(.vectors)
+ *(.text .text.*)
+ *(.fixup)
+ *(.gnu.warning)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.got)
+ *(.gcc_except_table)
+ *(.gnu.linkonce.r.*)
+ _etext = ABSOLUTE(.);
+ } > kflash
+
+ .init_section : {
+ _sinit = ABSOLUTE(.);
+ *(.init_array .init_array.*)
+ _einit = ABSOLUTE(.);
+ } > kflash
+
+ .ARM.extab : {
+ *(.ARM.extab*)
+ } > kflash
+
+ __exidx_start = ABSOLUTE(.);
+ .ARM.exidx : {
+ *(.ARM.exidx*)
+ } > kflash
+
+ __exidx_end = ABSOLUTE(.);
+
+ _eronly = ABSOLUTE(.);
+
+ .data : {
+ _sdata = ABSOLUTE(.);
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ CONSTRUCTORS
+ _edata = ABSOLUTE(.);
+ } > ksram AT > kflash
+
+ .bss : {
+ _sbss = ABSOLUTE(.);
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ _ebss = ABSOLUTE(.);
+ } > ksram
+
+ /* Stabs debugging sections */
+
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_info 0 : { *(.debug_info) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ .debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/configs/stm32f746-ws/scripts/memory.ld b/configs/stm32f746-ws/scripts/memory.ld
new file mode 100644
index 0000000000..7371dc061b
--- /dev/null
+++ b/configs/stm32f746-ws/scripts/memory.ld
@@ -0,0 +1,129 @@
+/****************************************************************************
+ * configs/stm32f746-ws/scripts/memory.ld
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The STM32F746NGH6 has 1024Kb of main FLASH memory. This FLASH memory can
+ * be accessed from either the AXIM interface at address 0x0800:0000 or from
+ * the ITCM interface at address 0x0020:0000.
+ *
+ * Additional information, including the option bytes, is available at at
+ * FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM).
+ *
+ * In the STM32F746NGH6, two different boot spaces can be selected through
+ * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and
+ * BOOT_ADD1 option bytes:
+ *
+ * 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].
+ * ST programmed value: Flash on ITCM at 0x0020:0000
+ * 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
+ * ST programmed value: System bootloader at 0x0010:0000
+ *
+ * NuttX does not modify these option byes. On the unmodified STM32F746G
+ * DISCO board, the BOOT0 pin is at ground so by default, the STM32 will boot
+ * to address 0x0020:0000 in ITCM FLASH.
+ *
+ * The STM32F746NGH6 also has 320Kb of data SRAM (in addition to ITCM SRAM).
+ * SRAM is split up into three blocks:
+ *
+ * 1) 64Kb of DTCM SRM beginning at address 0x2000:0000
+ * 2) 240Kb of SRAM1 beginning at address 0x2001:0000
+ * 3) 16Kb of SRAM2 beginning at address 0x2004:c000
+ *
+ * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
+ * where the code expects to begin execution by jumping to the entry point in
+ * the 0x0800:0000 address range.
+ *
+ * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of
+ * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which
+ * should fit into 64KB and, of course, can be optimized as needed (See
+ * also configs/stm32f746g-disco/scripts/kernel-space.ld). Allowing the
+ * additional does permit addition debug instrumentation to be added to the
+ * kernel space without overflowing the partition.
+ *
+ * Alignment of the user space FLASH partition is also a critical factor:
+ * The user space FLASH partition will be spanned with a single region of
+ * size 2**n bytes. The alignment of the user-space region must be the same.
+ * As a consequence, as the user-space increases in size, the alignment
+ * requirement also increases.
+ *
+ * This alignment requirement means that the largest user space FLASH region
+ * you can have will be 512KB at it would have to be positioned at
+ * 0x08800000. If you change this address, don't forget to change the
+ * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify
+ * the check in kernel/userspace.c.
+ *
+ * For the same reasons, the maximum size of the SRAM mapping is limited to
+ * 4KB. Both of these alignment limitations could be reduced by using
+ * multiple regions to map the FLASH/SDRAM range or perhaps with some
+ * clever use of subregions.
+ *
+ * A detailed memory map for the 112KB SRAM region is as follows:
+ *
+ * 0x20001 0000: Kernel .data region. Typical size: 0.1KB
+ * ------- ---- Kernel .bss region. Typical size: 1.8KB
+ * 0x20001 0800: Kernel IDLE thread stack (approximate). Size is
+ * determined by CONFIG_IDLETHREAD_STACKSIZE and
+ * adjustments for alignment. Typical is 1KB.
+ * ------- ---- Padded to 4KB
+ * 0x20001 1000: User .data region. Size is variable.
+ * ------- ---- User .bss region Size is variable.
+ * 0x20001 2000: Beginning of kernel heap. Size determined by
+ * CONFIG_MM_KERNEL_HEAPSIZE.
+ * ------- ---- Beginning of user heap. Can vary with other settings.
+ * 0x20004 c000: End+1 of SRAM1
+ */
+
+MEMORY
+{
+ /* ITCM boot address */
+
+ itcm (rwx) : ORIGIN = 0x00200000, LENGTH = 1024K
+
+ /* 1024KB FLASH */
+
+ kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+ uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K
+ xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K
+
+ /* 240KB of contiguous SRAM1 */
+
+ ksram (rwx) : ORIGIN = 0x20010000, LENGTH = 4K
+ usram (rwx) : ORIGIN = 0x20011000, LENGTH = 4K
+ xsram (rwx) : ORIGIN = 0x20012000, LENGTH = 240K - 8K
+
+ /* DTCM SRAM */
+
+ dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+ sram2 (rwx) : ORIGIN = 0x2004c000, LENGTH = 16K
+}
diff --git a/configs/stm32f746-ws/scripts/user-space.ld b/configs/stm32f746-ws/scripts/user-space.ld
new file mode 100644
index 0000000000..ebf30ef9da
--- /dev/null
+++ b/configs/stm32f746-ws/scripts/user-space.ld
@@ -0,0 +1,111 @@
+/****************************************************************************
+ * configs/stm32f746-ws/scripts/user-space.ld
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* NOTE: This depends on the memory.ld script having been included prior to
+ * this script.
+ */
+
+OUTPUT_ARCH(arm)
+SECTIONS
+{
+ .userspace : {
+ *(.userspace)
+ } > uflash
+
+ .text : {
+ _stext = ABSOLUTE(.);
+ *(.text .text.*)
+ *(.fixup)
+ *(.gnu.warning)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.got)
+ *(.gcc_except_table)
+ *(.gnu.linkonce.r.*)
+ _etext = ABSOLUTE(.);
+ } > uflash
+
+ .init_section : {
+ _sinit = ABSOLUTE(.);
+ *(.init_array .init_array.*)
+ _einit = ABSOLUTE(.);
+ } > uflash
+
+ .ARM.extab : {
+ *(.ARM.extab*)
+ } > uflash
+
+ __exidx_start = ABSOLUTE(.);
+ .ARM.exidx : {
+ *(.ARM.exidx*)
+ } > uflash
+
+ __exidx_end = ABSOLUTE(.);
+
+ _eronly = ABSOLUTE(.);
+
+ .data : {
+ _sdata = ABSOLUTE(.);
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ CONSTRUCTORS
+ _edata = ABSOLUTE(.);
+ } > usram AT > uflash
+
+ .bss : {
+ _sbss = ABSOLUTE(.);
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ _ebss = ABSOLUTE(.);
+ } > usram
+
+ /* Stabs debugging sections */
+
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_info 0 : { *(.debug_info) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ .debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/configs/stm32f746-ws/src/.gitignore b/configs/stm32f746-ws/src/.gitignore
new file mode 100644
index 0000000000..726d936e1e
--- /dev/null
+++ b/configs/stm32f746-ws/src/.gitignore
@@ -0,0 +1,2 @@
+/.depend
+/Make.dep
diff --git a/configs/stm32f746-ws/src/Makefile b/configs/stm32f746-ws/src/Makefile
new file mode 100644
index 0000000000..b20f916b7e
--- /dev/null
+++ b/configs/stm32f746-ws/src/Makefile
@@ -0,0 +1,45 @@
+############################################################################
+# configs/stm32f746-ws/src/Makefile
+#
+# Copyright (C) 2015 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+
+ASRCS =
+CSRCS = stm32_boot.c stm32_spi.c
+
+ifeq ($(CONFIG_LIB_BOARDCTL),y)
+CSRCS += stm32_appinitialize.c
+endif
+
+include $(TOPDIR)/configs/Board.mk
diff --git a/configs/stm32f746-ws/src/stm32_appinitialize.c b/configs/stm32f746-ws/src/stm32_appinitialize.c
new file mode 100644
index 0000000000..610f4978e2
--- /dev/null
+++ b/configs/stm32f746-ws/src/stm32_appinitialize.c
@@ -0,0 +1,65 @@
+/****************************************************************************
+ * config/stm32f746-ws/src/stm32_appinitilaize.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ * Author: Mark Olsson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+#include
+
+#include "stm32f746-ws.h"
+#include
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ * Perform application specific initialization. This function is never
+ * called directly from application code, but only indirectly via the
+ * (non-standard) boardctl() interface using the command BOARDIOC_INIT.
+ *
+ ****************************************************************************/
+
+int board_app_initialize(void)
+{
+
+ return OK;
+}
diff --git a/configs/stm32f746-ws/src/stm32_boot.c b/configs/stm32f746-ws/src/stm32_boot.c
new file mode 100644
index 0000000000..5b41bd6d38
--- /dev/null
+++ b/configs/stm32f746-ws/src/stm32_boot.c
@@ -0,0 +1,106 @@
+/************************************************************************************
+ * configs/stm32f746-ws/src/stm32_boot.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include
+
+#include
+#include
+
+#include "up_arch.h"
+#include "stm32f746-ws.h"
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_boardinitialize
+ *
+ * Description:
+ * All STM32 architectures must provide the following entry point. This entry point
+ * is called early in the initialization -- after all memory has been configured
+ * and mapped but before any devices have been initialized.
+ *
+ ************************************************************************************/
+
+void stm32_boardinitialize(void)
+{
+#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \
+ defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \
+ defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6)
+ /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function
+ * stm32_spidev_initialize() has been brought into the link.
+ */
+
+ if (stm32_spidev_initialize)
+ {
+ stm32_spidev_initialize();
+ }
+#endif
+
+}
+
+/************************************************************************************
+ * Name: board_initialize
+ *
+ * Description:
+ * If CONFIG_BOARD_INITIALIZE is selected, then an additional initialization call
+ * will be performed in the boot-up sequence to a function called
+ * board_initialize(). board_initialize() will be called immediately after
+ * up_initialize() is called and just before the initial application is started.
+ * This additional initialization phase may be used, for example, to initialize
+ * board-specific device drivers.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_BOARD_INITIALIZE
+void board_initialize(void)
+{
+#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL)
+ /* Perform NSH initialization here instead of from the NSH. This
+ * alternative NSH initialization is necessary when NSH is ran in user-space
+ * but the initialization function must run in kernel space.
+ */
+
+ (void)board_app_initialize();
+#endif
+}
+#endif
diff --git a/configs/stm32f746-ws/src/stm32_spi.c b/configs/stm32f746-ws/src/stm32_spi.c
new file mode 100644
index 0000000000..e31a63a11d
--- /dev/null
+++ b/configs/stm32f746-ws/src/stm32_spi.c
@@ -0,0 +1,238 @@
+/************************************************************************************
+ * configs/nucleo-144/src/stm32_spi.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "up_arch.h"
+#include "chip.h"
+#include "stm32_spi.h"
+
+#include "nucleo-144.h"
+
+#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \
+ defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \
+ defined(CONFIG_STM32F7_SPI5)
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+#ifdef CONFIG_DEBUG_SPI
+# define spidbg lldbg
+# ifdef SPI_VERBOSE
+# define spivdbg lldbg
+# else
+# define spivdbg(x...)
+# endif
+#else
+# undef SPI_VERBOSE
+# define spidbg(x...)
+# define spivdbg(x...)
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_spidev_initialize
+ *
+ * Description:
+ * Called to configure SPI chip select GPIO pins for the stm32f746g-disco board.
+ *
+ ************************************************************************************/
+
+void weak_function stm32_spidev_initialize(void)
+{
+}
+
+/****************************************************************************
+ * Name: stm32_spi1/2/3/4/5select and stm32_spi1/2/3/4/5status
+ *
+ * Description:
+ * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be
+ * provided by board-specific logic. They are implementations of the select
+ * and status methods of the SPI interface defined by struct spi_ops_s (see
+ * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize())
+ * are provided by common STM32 logic. To use this common SPI logic on your
+ * board:
+ *
+ * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select
+ * pins.
+ * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your
+ * board-specific logic. These functions will perform chip selection and
+ * status operations using GPIOs in the way your board is configured.
+ * 3. Add a calls to stm32_spibus_initialize() in your low level application
+ * initialization logic
+ * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the
+ * SPI driver to higher level logic (e.g., calling
+ * mmcsd_spislotinitialize(), for example, will bind the SPI driver to
+ * the SPI MMC/SD driver).
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32F7_SPI1
+void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+{
+ spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
+}
+
+uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_STM32F7_SPI2
+void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+{
+ spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
+}
+
+uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_STM32F7_SPI3
+void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+{
+ spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
+}
+
+uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_STM32F7_SPI4
+void stm32_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+{
+ spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
+}
+
+uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_STM32F7_SPI5
+void stm32_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+{
+ spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
+}
+
+uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+ return 0;
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_spi1cmddata
+ *
+ * Description:
+ * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true)
+ * or command (false). This function must be provided by platform-specific
+ * logic. This is an implementation of the cmddata method of the SPI
+ * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h).
+ *
+ * Input Parameters:
+ *
+ * spi - SPI device that controls the bus the device that requires the CMD/
+ * DATA selection.
+ * devid - If there are multiple devices on the bus, this selects which one
+ * to select cmd or data. NOTE: This design restricts, for example,
+ * one one SPI display per SPI bus.
+ * cmd - true: select command; false: select data
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_CMDDATA
+#ifdef CONFIG_STM32F7_SPI1
+int stm32_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
+{
+ return -ENODEV;
+}
+#endif
+
+#ifdef CONFIG_STM32F7_SPI2
+int stm32_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
+{
+ return -ENODEV;
+}
+#endif
+
+#ifdef CONFIG_STM32F7_SPI3
+int stm32_spi3cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
+{
+ return -ENODEV;
+}
+#endif
+
+#ifdef CONFIG_STM32F7_SPI4
+int stm32_spi4cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
+{
+ return -ENODEV;
+}
+#endif
+
+#ifdef CONFIG_STM32F7_SPI5
+int stm32_spi5cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
+{
+ return -ENODEV;
+}
+#endif
+
+#endif /* CONFIG_SPI_CMDDATA */
+#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI5 */
diff --git a/configs/stm32f746-ws/src/stm32f746-ws.h b/configs/stm32f746-ws/src/stm32f746-ws.h
new file mode 100644
index 0000000000..07d2c6c11f
--- /dev/null
+++ b/configs/stm32f746-ws/src/stm32f746-ws.h
@@ -0,0 +1,106 @@
+/****************************************************************************************************
+ * configs/stm32f746-ws/src/stm32f746-ws.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ * Author: Mark Olsson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __CONFIGS_STM32F746_WS_SRC_STM32F746_WS_H
+#define __CONFIGS_STM32F746_WS_SRC_STM32F746_WS_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include
+#include
+#include
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+/* procfs File System */
+
+#ifdef CONFIG_FS_PROCFS
+# ifdef CONFIG_NSH_PROC_MOUNTPOINT
+# define STM32_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT
+# else
+# define STM32_PROCFS_MOUNTPOINT "/proc"
+# endif
+#endif
+
+/* STM32F736G Discovery GPIOs ***********************************************************************/
+/* The STM32F746G-DISCO board has numerous LEDs but only one, LD1 located near the reset button, that
+ * can be controlled by software (LD2 is a power indicator, LD3-6 indicate USB status, LD7 is
+ * controlled by the ST-Link).
+ *
+ * LD1 is controlled by PI1 which is also the SPI2_SCK at the Arduino interface. One end of LD1 is
+ * grounded so a high output on PI1 will illuminate the LED.
+ */
+
+#define GPIO_LD1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
+ GPIO_PORTB | GPIO_PIN0)
+#define GPIO_LD2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
+ GPIO_PORTB | GPIO_PIN7)
+#define GPIO_LD3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
+ GPIO_PORTB | GPIO_PIN14)
+
+#define LED_DRIVER_PATH "/dev/userleds"
+
+/* Pushbutton B1, labelled "User", is connected to GPIO PC13. A high value will be sensed when the
+ * button is depressed. Note that the EXTI interrupt is configured.
+ */
+
+#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13)
+
+/****************************************************************************************************
+ * Public data
+ ****************************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Name: stm32_spidev_initialize
+ *
+ * Description:
+ * Called to configure SPI chip select GPIO pins for the stm32f746g-disco board.
+ *
+ ****************************************************************************************************/
+
+void weak_function stm32_spidev_initialize(void);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __CONFIGS_STM32F746_WS_SRC_STM32F746_WS_H */
--
GitLab
From 7630b9db5d128778c79d3b932c694a406e8fcf59 Mon Sep 17 00:00:00 2001
From: pkolesnikov
Date: Mon, 23 May 2016 15:56:56 +0200
Subject: [PATCH 002/400] i2c copy
---
arch/arm/src/stm32f7/chip/stm32_i2c.h | 52 +
.../arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h | 249 ++
arch/arm/src/stm32f7/stm32_i2c.c | 2059 +++++++++++++++++
arch/arm/src/stm32f7/stm32_i2c.h | 104 +
configs/stm32f746-ws/src/stm32_spi.c | 2 +-
5 files changed, 2465 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/src/stm32f7/chip/stm32_i2c.h
create mode 100644 arch/arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h
create mode 100644 arch/arm/src/stm32f7/stm32_i2c.c
create mode 100644 arch/arm/src/stm32f7/stm32_i2c.h
diff --git a/arch/arm/src/stm32f7/chip/stm32_i2c.h b/arch/arm/src/stm32f7/chip/stm32_i2c.h
new file mode 100644
index 0000000000..976b936422
--- /dev/null
+++ b/arch/arm/src/stm32f7/chip/stm32_i2c.h
@@ -0,0 +1,52 @@
+/************************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32_i2c.h
+ *
+ * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_I2C_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_I2C_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+#include "chip.h"
+
+#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
+# include "chip/stm32f74xx75xx_i2c.h"
+#else
+# error "Unsupported STM32 F7 part"
+#endif
+
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_I2C_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h
new file mode 100644
index 0000000000..e2d4b40e6d
--- /dev/null
+++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h
@@ -0,0 +1,249 @@
+/************************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h
+ *
+ * Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_STM32F74XX75XX_I2C_H
+#define __ARCH_ARM_SRC_STM32F7_STM32F74XX75XX_I2C_H
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32F7_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */
+#define STM32F7_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */
+#define STM32F7_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
+#define STM32F7_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
+#define STM32F7_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */
+#define STM32F7_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */
+#define STM32F7_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */
+#define STM32F7_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */
+#define STM32F7_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */
+#define STM32F7_I2C_RXDR_OFFSET 0x0024 /* Receive data register */
+#define STM32F7_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */
+
+/* Register Addresses ***************************************************************/
+
+#if STM32F7_NI2C > 0
+# define STM32F7_I2C1_CR1 (STM32F7_I2C1_BASE+STM32F7_I2C_CR1_OFFSET)
+# define STM32F7_I2C1_CR2 (STM32F7_I2C1_BASE+STM32F7_I2C_CR2_OFFSET)
+# define STM32F7_I2C1_OAR1 (STM32F7_I2C1_BASE+STM32F7_I2C_OAR1_OFFSET)
+# define STM32F7_I2C1_OAR2 (STM32F7_I2C1_BASE+STM32F7_I2C_OAR2_OFFSET)
+# define STM32F7_I2C1_TIMINGR (STM32F7_I2C1_BASE+STM32F7_I2C_TIMINGR_OFFSET)
+# define STM32F7_I2C1_TIMEOUTR (STM32F7_I2C1_BASE+STM32F7_I2C_TIMEOUTR_OFFSET)
+# define STM32F7_I2C1_ISR (STM32F7_I2C1_BASE+STM32F7_I2C_ISR_OFFSET)
+# define STM32F7_I2C1_ICR (STM32F7_I2C1_BASE+STM32F7_I2C_ICR_OFFSET)
+# define STM32F7_I2C1_PECR (STM32F7_I2C1_BASE+STM32F7_I2C_PECR_OFFSET)
+# define STM32F7_I2C1_RXDR (STM32F7_I2C1_BASE+STM32F7_I2C_RXDR_OFFSET)
+# define STM32F7_I2C1_TXDR (STM32F7_I2C1_BASE+STM32F7_I2C_TXDR_OFFSET)
+#endif
+
+#if STM32F7_NI2C > 1
+# define STM32F7_I2C2_CR1 (STM32F7_I2C2_BASE+STM32F7_I2C_CR1_OFFSET)
+# define STM32F7_I2C2_CR2 (STM32F7_I2C2_BASE+STM32F7_I2C_CR2_OFFSET)
+# define STM32F7_I2C2_OAR1 (STM32F7_I2C2_BASE+STM32F7_I2C_OAR1_OFFSET)
+# define STM32F7_I2C2_OAR2 (STM32F7_I2C2_BASE+STM32F7_I2C_OAR2_OFFSET)
+# define STM32F7_I2C2_TIMINGR (STM32F7_I2C2_BASE+STM32F7_I2C_TIMINGR_OFFSET)
+# define STM32F7_I2C2_TIMEOUTR (STM32F7_I2C2_BASE+STM32F7_I2C_TIMEOUTR_OFFSET)
+# define STM32F7_I2C2_ISR (STM32F7_I2C2_BASE+STM32F7_I2C_ISR_OFFSET)
+# define STM32F7_I2C2_ICR (STM32F7_I2C2_BASE+STM32F7_I2C_ICR_OFFSET)
+# define STM32F7_I2C2_PECR (STM32F7_I2C2_BASE+STM32F7_I2C_PECR_OFFSET)
+# define STM32F7_I2C2_RXDR (STM32F7_I2C2_BASE+STM32F7_I2C_RXDR_OFFSET)
+# define STM32F7_I2C2_TXDR (STM32F7_I2C2_BASE+STM32F7_I2C_TXDR_OFFSET)
+#endif
+
+#if STM32F7_NI2C > 2
+# define STM32F7_I2C3_CR1 (STM32F7_I2C3_BASE+STM32F7_I2C_CR1_OFFSET)
+# define STM32F7_I2C3_CR2 (STM32F7_I2C3_BASE+STM32F7_I2C_CR2_OFFSET)
+# define STM32F7_I2C3_OAR1 (STM32F7_I2C3_BASE+STM32F7_I2C_OAR1_OFFSET)
+# define STM32F7_I2C3_OAR2 (STM32F7_I2C3_BASE+STM32F7_I2C_OAR2_OFFSET)
+# define STM32F7_I2C3_TIMINGR (STM32F7_I2C3_BASE+STM32F7_I2C_TIMINGR_OFFSET)
+# define STM32F7_I2C3_TIMEOUTR (STM32F7_I2C3_BASE+STM32F7_I2C_TIMEOUTR_OFFSET)
+# define STM32F7_I2C3_ISR (STM32F7_I2C3_BASE+STM32F7_I2C_ISR_OFFSET)
+# define STM32F7_I2C3_ICR (STM32F7_I2C3_BASE+STM32F7_I2C_ICR_OFFSET)
+# define STM32F7_I2C3_PECR (STM32F7_I2C3_BASE+STM32F7_I2C_PECR_OFFSET)
+# define STM32F7_I2C3_RXDR (STM32F7_I2C3_BASE+STM32F7_I2C_RXDR_OFFSET)
+# define STM32F7_I2C3_TXDR (STM32F7_I2C3_BASE+STM32F7_I2C_TXDR_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* Control register 1 */
+
+#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */
+#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */
+#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */
+#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */
+#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */
+#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */
+#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */
+#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */
+#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */
+#define I2C_CR1_DNF_MASK (15 << I2C_CR1_DNF_SHIFT)
+# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT)
+# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */
+#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */
+#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */
+#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */
+#define I2C_CR1_WUPEN (1 << 18) /* Bit 18: Wakeup from STOP enable */
+#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */
+#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */
+#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */
+#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */
+#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */
+
+/* Control register 2 */
+
+#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */
+#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT)
+#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */
+#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT)
+#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */
+#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */
+#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */
+#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */
+#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */
+#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */
+#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */
+#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT)
+#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */
+#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */
+#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */
+
+/* Own address register 1 */
+
+#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */
+#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT)
+#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */
+#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT)
+#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */
+#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */
+
+/* Own address register 2 */
+
+#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */
+#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT)
+#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */
+#define I2C_OAR2_OA2MSK_MASK (7 << I2C_OAR2_OA2MSK_SHIFT)
+# define I2C_OAR2_OA2MSK_NONE (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */
+# define I2C_OAR2_OA2MSK_2_7 (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */
+# define I2C_OAR2_OA2MSK_3_7 (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */
+# define I2C_OAR2_OA2MSK_4_7 (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */
+# define I2C_OAR2_OA2MSK_5_7 (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */
+# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */
+# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */
+# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */
+#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */
+
+/* Timing register */
+
+#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */
+#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT)
+# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */
+
+#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */
+#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT)
+# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */
+
+#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */
+#define I2C_TIMINGR_SDADEL_MASK (15 << I2C_TIMINGR_SDADEL_SHIFT)
+# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */
+
+#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */
+#define I2C_TIMINGR_SCLDEL_MASK (15 << I2C_TIMINGR_SCLDEL_SHIFT)
+# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */
+
+#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */
+#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT)
+# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */
+
+/* Timeout register */
+
+#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */
+#define I2C_TIMEOUTR_A_MASK (0x0fff << I2C_TIMEOUTR_A_SHIFT)
+# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT)
+#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */
+#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */
+#define I2C_TIMEOUTR_B_MASK (0x0fff << I2C_TIMEOUTR_B_SHIFT)
+# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT)
+#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */
+
+/* Interrupt and Status register and interrupt clear register */
+/* Common interrupt bits */
+
+#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */
+#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */
+#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */
+#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */
+#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */
+#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */
+#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */
+#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */
+#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */
+
+/* Fields unique to the Interrupt and Status register */
+
+#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */
+#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */
+#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */
+#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */
+#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */
+#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */
+#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */
+#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */
+#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT)
+
+#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT)
+
+#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \
+ | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT | I2C_INT_ALERT)
+
+/* Packet error checking register */
+
+#define I2C_PECR_MASK (0xff)
+
+/* Receive data register */
+
+#define I2C_RXDR_MASK (0xff)
+
+/* Transmit data register */
+
+#define I2C_TXDR_MASK (0xff)
+
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_I2C_H */
+
diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c
new file mode 100644
index 0000000000..01a5995996
--- /dev/null
+++ b/arch/arm/src/stm32f7/stm32_i2c.c
@@ -0,0 +1,2059 @@
+/************************************************************************************
+ * arch/arm/src/stm32f7/stm32f3xx_i2c.c
+ * STM32F7 I2C driver - based on STM32L4 I2C Hardware Layer - Device Driver
+ *
+ * Copyright (C) 2011 Uros Platise. All rights reserved.
+ * Author: Uros Platise
+ *
+ * With extensions and modifications for the F1, F2, and F4 by:
+ *
+ * Copyright (C) 2011-2013, 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregroy Nutt
+ *
+ * And this version for the STM32 F3 by
+ *
+ * Author: John Wharington
+ *
+ * Modified for STM32L4 by
+ *
+ * Author: Sebastien Lorquet
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/* Supports:
+ * - Master operation, 100 kHz (standard) and 400 kHz (full speed)
+ * - Multiple instances (shared bus)
+ * - Interrupt based operation
+ *
+ * Structure naming:
+ * - Device: structure as defined by the nuttx/i2c/i2c.h
+ * - Instance: represents each individual access to the I2C driver, obtained by
+ * the i2c_init(); it extends the Device structure from the nuttx/i2c/i2c.h;
+ * Instance points to OPS, to common I2C Hardware private data and contains
+ * its own private data, as frequency, address, mode of operation (in the future)
+ * - Private: Private data of an I2C Hardware
+ *
+ * TODO
+ * - Check for all possible deadlocks (as BUSY='1' I2C needs to be reset in HW using the I2C_CR1_SWRST)
+ * - SMBus support (hardware layer timings are already supported) and add SMBA gpio pin
+ * - Slave support with multiple addresses (on multiple instances):
+ * - 2 x 7-bit address or
+ * - 1 x 10 bit adresses + 1 x 7 bit address (?)
+ * - plus the broadcast address (general call)
+ * - Multi-master support
+ * - DMA (to get rid of too many CPU wake-ups and interventions)
+ * - Be ready for IPMI
+ */
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+
+#include "up_arch.h"
+
+#include "stm32f7_rcc.h"
+#include "stm32f7_i2c.h"
+#include "stm32f7_waste.h"
+
+/* At least one I2C peripheral must be enabled */
+
+#if defined(CONFIG_STM32F7_I2C1) || defined(CONFIG_STM32F7_I2C2) || defined(CONFIG_STM32F7_I2C3)
+/* This implementation is for the STM32 F1, F2, and F4 only */
+
+#if defined(CONFIG_STM32F7_STM32F30XX)
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Configuration ********************************************************************/
+/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. Instead,
+ * CPU-intensive polling will be used.
+ */
+
+/* Interrupt wait timeout in seconds and milliseconds */
+
+#if !defined(CONFIG_STM32F7_I2CTIMEOSEC) && !defined(CONFIG_STM32F7_I2CTIMEOMS)
+# define CONFIG_STM32F7_I2CTIMEOSEC 0
+# define CONFIG_STM32F7_I2CTIMEOMS 500 /* Default is 500 milliseconds */
+#elif !defined(CONFIG_STM32F7_I2CTIMEOSEC)
+# define CONFIG_STM32F7_I2CTIMEOSEC 0 /* User provided milliseconds */
+#elif !defined(CONFIG_STM32F7_I2CTIMEOMS)
+# define CONFIG_STM32F7_I2CTIMEOMS 0 /* User provided seconds */
+#endif
+
+/* Interrupt wait time timeout in system timer ticks */
+
+#ifndef CONFIG_STM32F7_I2CTIMEOTICKS
+# define CONFIG_STM32F7_I2CTIMEOTICKS \
+ (SEC2TICK(CONFIG_STM32F7_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32F7_I2CTIMEOMS))
+#endif
+
+#ifndef CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP
+# define CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32F7_I2CTIMEOTICKS)
+#endif
+
+#define I2C_OUTPUT \
+ (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | GPIO_MODE_50MHz)
+#define MKI2C_OUTPUT(p) \
+ (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT)
+
+/* Register setting unique to the STM32F30xx */
+
+#define I2C_CR1_TXRX \
+ (I2C_CR1_RXIE | I2C_CR1_TXIE)
+#define I2C_CR1_ALLINTS \
+ (I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ADDRIE | I2C_CR1_ERRIE)
+
+#define STATUS_NACK(status) (status & I2C_INT_NACK)
+#define STATUS_ADDR(status) (status & I2C_INT_ADDR)
+#define STATUS_ADDR_TX(status) (status & (I2C_INT_ADDR | I2C_ISR_TXIS))
+#define STATUS_ADD10(status) (0)
+#define STATUS_RXNE(status) (status & I2C_ISR_RXNE)
+#define STATUS_TC(status) (status & I2C_ISR_TC)
+#define STATUS_BUSY(status) (status & I2C_ISR_BUSY)
+
+/* Debug ****************************************************************************/
+/* CONFIG_DEBUG_I2C + CONFIG_DEBUG enables general I2C debug output. */
+
+#ifdef CONFIG_DEBUG_I2C
+# define i2cdbg dbg
+# define i2cvdbg vdbg
+#else
+# define i2cdbg(x...)
+# define i2cvdbg(x...)
+#endif
+
+/* I2C event trace logic. NOTE: trace uses the internal, non-standard, low-level
+ * debug interface syslog() but does not require that any other debug
+ * is enabled.
+ */
+
+#ifndef CONFIG_I2C_TRACE
+# define stm32f7_i2c_tracereset(p)
+# define stm32f7_i2c_tracenew(p,s)
+# define stm32f7_i2c_traceevent(p,e,a)
+# define stm32f7_i2c_tracedump(p)
+#endif
+
+#ifndef CONFIG_I2C_NTRACE
+# define CONFIG_I2C_NTRACE 32
+#endif
+
+/************************************************************************************
+ * Private Types
+ ************************************************************************************/
+/* Interrupt state */
+
+enum stm32f7_intstate_e
+{
+ INTSTATE_IDLE = 0, /* No I2C activity */
+ INTSTATE_WAITING, /* Waiting for completion of interrupt activity */
+ INTSTATE_DONE, /* Interrupt activity complete */
+};
+
+/* Trace events */
+
+enum stm32f7_trace_e
+{
+ I2CEVENT_NONE = 0, /* No events have occurred with this status */
+ I2CEVENT_SENDADDR, /* Start/Master bit set and address sent, param = msgc */
+ I2CEVENT_SENDBYTE, /* Send byte, param = dcnt */
+ I2CEVENT_ITBUFEN, /* Enable buffer interrupts, param = 0 */
+ I2CEVENT_RCVBYTE, /* Read more dta, param = dcnt */
+ I2CEVENT_REITBUFEN, /* Re-enable buffer interrupts, param = 0 */
+ I2CEVENT_DISITBUFEN, /* Disable buffer interrupts, param = 0 */
+ I2CEVENT_BTFNOSTART, /* BTF on last byte with no restart, param = msgc */
+ I2CEVENT_BTFRESTART, /* Last byte sent, re-starting, param = msgc */
+ I2CEVENT_BTFSTOP, /* Last byte sten, send stop, param = 0 */
+ I2CEVENT_ERROR /* Error occurred, param = 0 */
+};
+
+/* Trace data */
+
+struct stm32f7_trace_s
+{
+ uint32_t status; /* I2C 32-bit SR2|SR1 status */
+ uint32_t count; /* Interrupt count when status change */
+ enum stm32f7_intstate_e event; /* Last event that occurred with this status */
+ uint32_t parm; /* Parameter associated with the event */
+ systime_t time; /* First of event or first status */
+};
+
+/* I2C Device hardware configuration */
+
+struct stm32f7_i2c_config_s
+{
+ uint32_t base; /* I2C base address */
+ uint32_t clk_bit; /* Clock enable bit */
+ uint32_t reset_bit; /* Reset bit */
+ uint32_t scl_pin; /* GPIO configuration for SCL as SCL */
+ uint32_t sda_pin; /* GPIO configuration for SDA as SDA */
+#ifndef CONFIG_I2C_POLLED
+ int (*isr)(int, void *); /* Interrupt handler */
+ uint32_t ev_irq; /* Event IRQ */
+ uint32_t er_irq; /* Error IRQ */
+#endif
+};
+
+/* I2C Device Private Data */
+
+struct stm32f7_i2c_priv_s
+{
+ const struct i2c_ops_s *ops; /* Standard I2C operations */
+ const struct stm32f7_i2c_config_s *config; /* Port configuration */
+ int refs; /* Referernce count */
+ sem_t sem_excl; /* Mutual exclusion semaphore */
+#ifndef CONFIG_I2C_POLLED
+ sem_t sem_isr; /* Interrupt wait semaphore */
+#endif
+ volatile uint8_t intstate; /* Interrupt handshake (see enum stm32f7_intstate_e) */
+
+ uint8_t msgc; /* Message count */
+ struct i2c_msg_s *msgv; /* Message list */
+ uint8_t *ptr; /* Current message buffer */
+ uint32_t frequency; /* Current I2C frequency */
+ int dcnt; /* Current message length */
+ uint16_t flags; /* Current message flags */
+ bool astart; /* START sent */
+
+ /* I2C trace support */
+
+#ifdef CONFIG_I2C_TRACE
+ int tndx; /* Trace array index */
+ systime_t start_time; /* Time when the trace was started */
+
+ /* The actual trace data */
+
+ struct stm32f7_trace_s trace[CONFIG_I2C_NTRACE];
+#endif
+
+ uint32_t status; /* End of transfer SR2|SR1 status */
+};
+
+/************************************************************************************
+ * Private Function Prototypes
+ ************************************************************************************/
+
+static inline uint16_t stm32f7_i2c_getreg(FAR struct stm32f7_i2c_priv_s *priv,
+ uint8_t offset);
+static inline void stm32f7_i2c_putreg(FAR struct stm32f7_i2c_priv_s *priv, uint8_t offset,
+ uint16_t value);
+static inline void stm32f7_i2c_putreg32(FAR struct stm32f7_i2c_priv_s *priv, uint8_t offset,
+ uint32_t value);
+static inline void stm32f7_i2c_modifyreg(FAR struct stm32f7_i2c_priv_s *priv,
+ uint8_t offset, uint16_t clearbits,
+ uint16_t setbits);
+static inline void stm32f7_i2c_modifyreg32(FAR struct stm32f7_i2c_priv_s *priv,
+ uint8_t offset, uint32_t clearbits,
+ uint32_t setbits);
+static inline void stm32f7_i2c_sem_wait(FAR struct stm32f7_i2c_priv_s *priv);
+#ifdef CONFIG_STM32F7_I2C_DYNTIMEO
+static useconds_t stm32f7_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs);
+#endif /* CONFIG_STM32F7_I2C_DYNTIMEO */
+static inline int stm32f7_i2c_sem_waitdone(FAR struct stm32f7_i2c_priv_s *priv);
+static inline void stm32f7_i2c_sem_waitstop(FAR struct stm32f7_i2c_priv_s *priv);
+static inline void stm32f7_i2c_sem_post(FAR struct stm32f7_i2c_priv_s *priv);
+static inline void stm32f7_i2c_sem_init(FAR struct stm32f7_i2c_priv_s *priv);
+static inline void stm32f7_i2c_sem_destroy(FAR struct stm32f7_i2c_priv_s *priv);
+#ifdef CONFIG_I2C_TRACE
+static void stm32f7_i2c_tracereset(FAR struct stm32f7_i2c_priv_s *priv);
+static void stm32f7_i2c_tracenew(FAR struct stm32f7_i2c_priv_s *priv, uint32_t status);
+static void stm32f7_i2c_traceevent(FAR struct stm32f7_i2c_priv_s *priv,
+ enum stm32f7_trace_e event, uint32_t parm);
+static void stm32f7_i2c_tracedump(FAR struct stm32f7_i2c_priv_s *priv);
+#endif /* CONFIG_I2C_TRACE */
+static void stm32f7_i2c_setclock(FAR struct stm32f7_i2c_priv_s *priv,
+ uint32_t frequency);
+static inline void stm32f7_i2c_sendstart(FAR struct stm32f7_i2c_priv_s *priv);
+static inline void stm32f7_i2c_clrstart(FAR struct stm32f7_i2c_priv_s *priv);
+static inline void stm32f7_i2c_sendstop(FAR struct stm32f7_i2c_priv_s *priv);
+static inline uint32_t stm32f7_i2c_getstatus(FAR struct stm32f7_i2c_priv_s *priv);
+static int stm32f7_i2c_isr(struct stm32f7_i2c_priv_s * priv);
+#ifndef CONFIG_I2C_POLLED
+#ifdef CONFIG_STM32F7_I2C1
+static int stm32f7_i2c1_isr(int irq, void *context);
+#endif
+#ifdef CONFIG_STM32F7_I2C2
+static int stm32f7_i2c2_isr(int irq, void *context);
+#endif
+#ifdef CONFIG_STM32F7_I2C3
+static int stm32f7_i2c3_isr(int irq, void *context);
+#endif
+#endif
+static int stm32f7_i2c_init(FAR struct stm32f7_i2c_priv_s *priv);
+static int stm32f7_i2c_deinit(FAR struct stm32f7_i2c_priv_s *priv);
+static int stm32f7_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
+ int count);
+#ifdef CONFIG_I2C_RESET
+static int stm32f7_i2c_reset(FAR struct i2c_master_s *dev);
+#endif
+
+/************************************************************************************
+ * Private Data
+ ************************************************************************************/
+
+/* Device Structures, Instantiation */
+
+const struct i2c_ops_s stm32f7_i2c_ops =
+{
+ .transfer = stm32f7_i2c_transfer
+#ifdef CONFIG_I2C_RESET
+ , .reset = stm32f7_i2c_reset
+#endif
+};
+
+#ifdef CONFIG_STM32F7_I2C1
+static const struct stm32f7_i2c_config_s stm32f7_i2c1_config =
+{
+ .base = STM32F7_I2C1_BASE,
+ .clk_bit = RCC_APB1ENR_I2C1EN,
+ .reset_bit = RCC_APB1RSTR_I2C1RST,
+ .scl_pin = GPIO_I2C1_SCL,
+ .sda_pin = GPIO_I2C1_SDA,
+#ifndef CONFIG_I2C_POLLED
+ .isr = stm32f7_i2c1_isr,
+ .ev_irq = STM32F7_IRQ_I2C1EV,
+ .er_irq = STM32F7_IRQ_I2C1ER
+#endif
+};
+
+struct stm32f7_i2c_priv_s stm32f7_i2c1_priv =
+{
+ .ops = &stm32f7_i2c_ops,
+ .config = &stm32f7_i2c1_config,
+ .refs = 0,
+ .intstate = INTSTATE_IDLE,
+ .msgc = 0,
+ .msgv = NULL,
+ .ptr = NULL,
+ .dcnt = 0,
+ .flags = 0,
+ .status = 0
+};
+#endif
+
+#ifdef CONFIG_STM32F7_I2C2
+static const struct stm32f7_i2c_config_s stm32f7_i2c2_config =
+{
+ .base = STM32F7_I2C2_BASE,
+ .clk_bit = RCC_APB1ENR_I2C2EN,
+ .reset_bit = RCC_APB1RSTR_I2C2RST,
+ .scl_pin = GPIO_I2C2_SCL,
+ .sda_pin = GPIO_I2C2_SDA,
+#ifndef CONFIG_I2C_POLLED
+ .isr = stm32f7_i2c2_isr,
+ .ev_irq = STM32F7_IRQ_I2C2EV,
+ .er_irq = STM32F7_IRQ_I2C2ER
+#endif
+};
+
+struct stm32f7_i2c_priv_s stm32f7_i2c2_priv =
+{
+ .ops = &stm32f7_i2c_ops,
+ .config = &stm32f7_i2c2_config,
+ .refs = 0,
+ .intstate = INTSTATE_IDLE,
+ .msgc = 0,
+ .msgv = NULL,
+ .ptr = NULL,
+ .dcnt = 0,
+ .flags = 0,
+ .status = 0
+};
+#endif
+
+#ifdef CONFIG_STM32F7_I2C3
+static const struct stm32f7_i2c_config_s stm32f7_i2c3_config =
+{
+ .base = STM32F7_I2C3_BASE,
+ .clk_bit = RCC_APB1ENR_I2C3EN,
+ .reset_bit = RCC_APB1RSTR_I2C3RST,
+ .scl_pin = GPIO_I2C3_SCL,
+ .sda_pin = GPIO_I2C3_SDA,
+#ifndef CONFIG_I2C_POLLED
+ .isr = stm32f7_i2c3_isr,
+ .ev_irq = STM32F7_IRQ_I2C3EV,
+ .er_irq = STM32F7_IRQ_I2C3ER
+#endif
+};
+
+struct stm32f7_i2c_priv_s stm32f7_i2c3_priv =
+{
+ .ops = &stm32f7_i2c_ops,
+ .config = &stm32f7_i2c3_config,
+ .refs = 0,
+ .intstate = INTSTATE_IDLE,
+ .msgc = 0,
+ .msgv = NULL,
+ .ptr = NULL,
+ .dcnt = 0,
+ .flags = 0,
+ .status = 0
+};
+#endif
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32f7_i2c_getreg
+ *
+ * Description:
+ * Get a 16-bit register value by offset
+ *
+ ************************************************************************************/
+
+static inline uint16_t stm32f7_i2c_getreg(FAR struct stm32f7_i2c_priv_s *priv,
+ uint8_t offset)
+{
+ return getreg16(priv->config->base + offset);
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_getreg32
+ *
+ * Description:
+ * Get a 32-bit register value by offset
+ *
+ ************************************************************************************/
+
+static inline uint32_t stm32f7_i2c_getreg32(FAR struct stm32f7_i2c_priv_s *priv,
+ uint8_t offset)
+{
+ return getreg32(priv->config->base + offset);
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_putreg
+ *
+ * Description:
+ * Put a 16-bit register value by offset
+ *
+ ************************************************************************************/
+
+static inline void stm32f7_i2c_putreg(FAR struct stm32f7_i2c_priv_s *priv, uint8_t offset,
+ uint16_t value)
+{
+ putreg16(value, priv->config->base + offset);
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_putreg32
+ *
+ * Description:
+ * Put a 32-bit register value by offset
+ *
+ ************************************************************************************/
+
+static inline void stm32f7_i2c_putreg32(FAR struct stm32f7_i2c_priv_s *priv,
+ uint8_t offset, uint32_t value)
+{
+ putreg32(value, priv->config->base + offset);
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_modifyreg
+ *
+ * Description:
+ * Modify a 16-bit register value by offset
+ *
+ ************************************************************************************/
+
+static inline void stm32f7_i2c_modifyreg(FAR struct stm32f7_i2c_priv_s *priv,
+ uint8_t offset, uint16_t clearbits,
+ uint16_t setbits)
+{
+ modifyreg16(priv->config->base + offset, clearbits, setbits);
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_modifyreg32
+ *
+ * Description:
+ * Modify a 32-bit register value by offset
+ *
+ ************************************************************************************/
+
+static inline void stm32f7_i2c_modifyreg32(FAR struct stm32f7_i2c_priv_s *priv,
+ uint8_t offset, uint32_t clearbits,
+ uint32_t setbits)
+{
+ modifyreg32(priv->config->base + offset, clearbits, setbits);
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_sem_wait
+ *
+ * Description:
+ * Take the exclusive access, waiting as necessary
+ *
+ ************************************************************************************/
+
+static inline void stm32f7_i2c_sem_wait(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ while (sem_wait(&priv->sem_excl) != 0)
+ {
+ ASSERT(errno == EINTR);
+ }
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_tousecs
+ *
+ * Description:
+ * Return a micro-second delay based on the number of bytes left to be processed.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F7_I2C_DYNTIMEO
+static useconds_t stm32f7_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs)
+{
+ size_t bytecount = 0;
+ int i;
+
+ /* Count the number of bytes left to process */
+
+ for (i = 0; i < msgc; i++)
+ {
+ bytecount += msgs[i].length;
+ }
+
+ /* Then return a number of microseconds based on a user provided scaling
+ * factor.
+ */
+
+ return (useconds_t)(CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE * bytecount);
+}
+#endif
+
+/************************************************************************************
+ * Name: stm32f7_i2c_enableinterrupts
+ *
+ * Description:
+ * Enable I2C interrupts
+ *
+ ************************************************************************************/
+
+#ifndef CONFIG_I2C_POLLED
+static inline void stm32f7_i2c_enableinterrupts(struct stm32f7_i2c_priv_s *priv)
+{
+ stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, I2C_CR1_TXRX);
+}
+#endif
+
+/************************************************************************************
+ * Name: stm32f7_i2c_disableinterrupts
+ *
+ * Description:
+ * Enable I2C interrupts
+ *
+ ************************************************************************************/
+
+#ifndef CONFIG_I2C_POLLED
+static inline void stm32f7_i2c_disableinterrupts(struct stm32f7_i2c_priv_s *priv)
+{
+ stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, I2C_CR1_TXRX, 0);
+}
+#endif
+
+/************************************************************************************
+ * Name: stm32f7_i2c_sem_waitdone
+ *
+ * Description:
+ * Wait for a transfer to complete
+ *
+ ************************************************************************************/
+
+#ifndef CONFIG_I2C_POLLED
+static inline int stm32f7_i2c_sem_waitdone(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ struct timespec abstime;
+ irqstate_t flags;
+ uint32_t regval;
+ int ret;
+
+ flags = enter_critical_section();
+
+ /* Enable I2C interrupts */
+
+ stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0,
+ (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX));
+
+ /* Signal the interrupt handler that we are waiting. NOTE: Interrupts
+ * are currently disabled but will be temporarily re-enabled below when
+ * sem_timedwait() sleeps.
+ */
+
+ priv->intstate = INTSTATE_WAITING;
+ do
+ {
+ /* Get the current time */
+
+ (void)clock_gettime(CLOCK_REALTIME, &abstime);
+
+ /* Calculate a time in the future */
+
+#if CONFIG_STM32F7_I2CTIMEOSEC > 0
+ abstime.tv_sec += CONFIG_STM32F7_I2CTIMEOSEC;
+#endif
+
+ /* Add a value proportional to the number of bytes in the transfer */
+
+#ifdef CONFIG_STM32F7_I2C_DYNTIMEO
+ abstime.tv_nsec += 1000 * stm32f7_i2c_tousecs(priv->msgc, priv->msgv);
+ if (abstime.tv_nsec >= 1000 * 1000 * 1000)
+ {
+ abstime.tv_sec++;
+ abstime.tv_nsec -= 1000 * 1000 * 1000;
+ }
+
+#elif CONFIG_STM32F7_I2CTIMEOMS > 0
+ abstime.tv_nsec += CONFIG_STM32F7_I2CTIMEOMS * 1000 * 1000;
+ if (abstime.tv_nsec >= 1000 * 1000 * 1000)
+ {
+ abstime.tv_sec++;
+ abstime.tv_nsec -= 1000 * 1000 * 1000;
+ }
+#endif
+ /* Wait until either the transfer is complete or the timeout expires */
+
+ ret = sem_timedwait(&priv->sem_isr, &abstime);
+ if (ret != OK && errno != EINTR)
+ {
+ /* Break out of the loop on irrecoverable errors. This would
+ * include timeouts and mystery errors reported by sem_timedwait.
+ * NOTE that we try again if we are awakened by a signal (EINTR).
+ */
+
+ break;
+ }
+ }
+
+ /* Loop until the interrupt level transfer is complete. */
+
+ while (priv->intstate != INTSTATE_DONE);
+
+ /* Set the interrupt state back to IDLE */
+
+ priv->intstate = INTSTATE_IDLE;
+
+ /* Disable I2C interrupts */
+
+ stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0);
+
+ leave_critical_section(flags);
+ return ret;
+}
+#else
+static inline int stm32f7_i2c_sem_waitdone(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ systime_t timeout;
+ systime_t start;
+ systime_t elapsed;
+ int ret;
+
+ /* Get the timeout value */
+
+#ifdef CONFIG_STM32F7_I2C_DYNTIMEO
+ timeout = USEC2TICK(stm32f7_i2c_tousecs(priv->msgc, priv->msgv));
+#else
+ timeout = CONFIG_STM32F7_I2CTIMEOTICKS;
+#endif
+
+ /* Signal the interrupt handler that we are waiting. NOTE: Interrupts
+ * are currently disabled but will be temporarily re-enabled below when
+ * sem_timedwait() sleeps.
+ */
+
+ priv->intstate = INTSTATE_WAITING;
+ start = clock_systimer();
+
+ do
+ {
+ /* Poll by simply calling the timer interrupt handler until it
+ * reports that it is done.
+ */
+
+ stm32f7_i2c_isr(priv);
+
+ /* Calculate the elapsed time */
+
+ elapsed = clock_systimer() - start;
+ }
+
+ /* Loop until the transfer is complete. */
+
+ while (priv->intstate != INTSTATE_DONE && elapsed < timeout);
+
+ i2cvdbg("intstate: %d elapsed: %ld threshold: %ld status: %08x\n",
+ priv->intstate, (long)elapsed, (long)timeout, priv->status);
+
+ /* Set the interrupt state back to IDLE */
+
+ ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT;
+ priv->intstate = INTSTATE_IDLE;
+ return ret;
+}
+#endif
+
+/************************************************************************************
+ * Name: stm32f7_i2c_set_7bit_address
+ *
+ * Description:
+ *
+ ************************************************************************************/
+
+static inline void
+stm32f7_i2c_set_7bit_address(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK,
+ ((priv->msgv->addr & 0x7F) << I2C_CR2_SADD7_SHIFT));
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_set_bytes_to_transfer
+ *
+ * Description:
+ *
+ ************************************************************************************/
+
+static inline void
+stm32f7_i2c_set_bytes_to_transfer(FAR struct stm32f7_i2c_priv_s *priv,
+ uint8_t n_bytes)
+{
+ stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK,
+ (n_bytes << I2C_CR2_NBYTES_SHIFT));
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_set_write_transfer_dir
+ *
+ * Description:
+ *
+ ************************************************************************************/
+
+static inline void
+stm32f7_i2c_set_write_transfer_dir(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0);
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_set_read_transfer_dir
+ *
+ * Description:
+ *
+ ************************************************************************************/
+
+static inline void
+stm32f7_i2c_set_read_transfer_dir(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN);
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_enable_autoend
+ *
+ * Description:
+ *
+ ************************************************************************************/
+
+static inline void
+stm32f7_i2c_enable_autoend(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_AUTOEND);
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_disable_autoend
+ *
+ * Description:
+ *
+ ************************************************************************************/
+
+static inline void
+stm32f7_i2c_disable_autoend(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_AUTOEND, 0);
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_sem_waitstop
+ *
+ * Description:
+ * Wait for a STOP to complete
+ *
+ ************************************************************************************/
+
+static inline void stm32f7_i2c_sem_waitstop(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ systime_t start;
+ systime_t elapsed;
+ systime_t timeout;
+ uint32_t cr;
+ uint32_t sr;
+
+ /* Select a timeout */
+
+#ifdef CONFIG_STM32F7_I2C_DYNTIMEO
+ timeout = USEC2TICK(CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP);
+#else
+ timeout = CONFIG_STM32F7_I2CTIMEOTICKS;
+#endif
+
+ /* Wait as stop might still be in progress; but stop might also
+ * be set because of a timeout error: "The [STOP] bit is set and
+ * cleared by software, cleared by hardware when a Stop condition is
+ * detected, set by hardware when a timeout error is detected."
+ */
+
+ start = clock_systimer();
+ do
+ {
+ /* Check for STOP condition */
+
+ cr = stm32f7_i2c_getreg32(priv, STM32F7_I2C_CR2_OFFSET);
+ if ((cr & I2C_CR2_STOP) == 0)
+ {
+ return;
+ }
+
+ /* Check for timeout error */
+
+ sr = stm32f7_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET);
+ if ((sr & I2C_INT_TIMEOUT) != 0)
+ {
+ return;
+ }
+
+ /* Calculate the elapsed time */
+
+ elapsed = clock_systimer() - start;
+ }
+
+ /* Loop until the stop is complete or a timeout occurs. */
+
+ while (elapsed < timeout);
+
+ /* If we get here then a timeout occurred with the STOP condition
+ * still pending.
+ */
+
+ i2cvdbg("Timeout with CR: %04x SR: %04x\n", cr, sr);
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_sem_post
+ *
+ * Description:
+ * Release the mutual exclusion semaphore
+ *
+ ************************************************************************************/
+
+static inline void stm32f7_i2c_sem_post(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ sem_post(&priv->sem_excl);
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_sem_init
+ *
+ * Description:
+ * Initialize semaphores
+ *
+ ************************************************************************************/
+
+static inline void stm32f7_i2c_sem_init(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ sem_init(&priv->sem_excl, 0, 1);
+#ifndef CONFIG_I2C_POLLED
+ sem_init(&priv->sem_isr, 0, 0);
+#endif
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_sem_destroy
+ *
+ * Description:
+ * Destroy semaphores.
+ *
+ ************************************************************************************/
+
+static inline void stm32f7_i2c_sem_destroy(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ sem_destroy(&priv->sem_excl);
+#ifndef CONFIG_I2C_POLLED
+ sem_destroy(&priv->sem_isr);
+#endif
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_trace*
+ *
+ * Description:
+ * I2C trace instrumentation
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_I2C_TRACE
+static void stm32f7_i2c_traceclear(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ struct stm32f7_trace_s *trace = &priv->trace[priv->tndx];
+
+ trace->status = 0; /* I2C 32-bit SR2|SR1 status */
+ trace->count = 0; /* Interrupt count when status change */
+ trace->event = I2CEVENT_NONE; /* Last event that occurred with this status */
+ trace->parm = 0; /* Parameter associated with the event */
+ trace->time = 0; /* Time of first status or event */
+}
+
+static void stm32f7_i2c_tracereset(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ /* Reset the trace info for a new data collection */
+
+ priv->tndx = 0;
+ priv->start_time = clock_systimer();
+ stm32f7_i2c_traceclear(priv);
+}
+
+static void stm32f7_i2c_tracenew(FAR struct stm32f7_i2c_priv_s *priv,
+ uint32_t status)
+{
+ struct stm32f7_trace_s *trace = &priv->trace[priv->tndx];
+
+ /* Is the current entry uninitialized? Has the status changed? */
+
+ if (trace->count == 0 || status != trace->status)
+ {
+ /* Yes.. Was it the status changed? */
+
+ if (trace->count != 0)
+ {
+ /* Yes.. bump up the trace index (unless we are out of trace entries) */
+
+ if (priv->tndx >= (CONFIG_I2C_NTRACE-1))
+ {
+ i2cdbg("Trace table overflow\n");
+ return;
+ }
+
+ priv->tndx++;
+ trace = &priv->trace[priv->tndx];
+ }
+
+ /* Initialize the new trace entry */
+
+ stm32f7_i2c_traceclear(priv);
+ trace->status = status;
+ trace->count = 1;
+ trace->time = clock_systimer();
+ }
+ else
+ {
+ /* Just increment the count of times that we have seen this status */
+
+ trace->count++;
+ }
+}
+
+static void stm32f7_i2c_traceevent(FAR struct stm32f7_i2c_priv_s *priv,
+ enum stm32f7_trace_e event, uint32_t parm)
+{
+ struct stm32f7_trace_s *trace;
+
+ if (event != I2CEVENT_NONE)
+ {
+ trace = &priv->trace[priv->tndx];
+
+ /* Initialize the new trace entry */
+
+ trace->event = event;
+ trace->parm = parm;
+
+ /* Bump up the trace index (unless we are out of trace entries) */
+
+ if (priv->tndx >= (CONFIG_I2C_NTRACE-1))
+ {
+ i2cdbg("Trace table overflow\n");
+ return;
+ }
+
+ priv->tndx++;
+ stm32f7_i2c_traceclear(priv);
+ }
+}
+
+static void stm32f7_i2c_tracedump(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ struct stm32f7_trace_s *trace;
+ int i;
+
+ syslog(LOG_DEBUG, "Elapsed time: %ld\n",
+ (long)(clock_systimer() - priv->start_time));
+
+ for (i = 0; i <= priv->tndx; i++)
+ {
+ trace = &priv->trace[i];
+ syslog(LOG_DEBUG,
+ "%2d. STATUS: %08x COUNT: %3d EVENT: %2d PARM: %08x TIME: %d\n",
+ i+1, trace->status, trace->count, trace->event, trace->parm,
+ trace->time - priv->start_time);
+ }
+}
+#endif /* CONFIG_I2C_TRACE */
+
+/************************************************************************************
+ * Name: stm32f7_i2c_setclock
+ *
+ * Description:
+ * Set the I2C clock
+ *
+ ************************************************************************************/
+
+static void stm32f7_i2c_setclock(FAR struct stm32f7_i2c_priv_s *priv, uint32_t frequency)
+{
+ uint32_t pe;
+ uint8_t presc;
+ uint8_t s_time;
+ uint8_t h_time;
+ uint8_t scl_h_period;
+ uint8_t scl_l_period;
+
+ /* Has the I2C bus frequency changed? */
+
+ if (frequency != priv->frequency)
+ {
+ /* Disable the selected I2C peripheral to configure TRISE */
+
+ pe = (stm32f7_i2c_getreg32(priv, STM32F7_I2C_CR1_OFFSET) & I2C_CR1_PE);
+ if (pe)
+ {
+ stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
+ }
+
+ /* Update timing and control registers */
+
+ /* TODO: speed/timing calcs */
+#warning "check set filters before timing, see RM0316"
+
+ /* values from 100khz at 8mhz i2c clock */
+
+ /* prescaler */
+ /* t_presc= (presc+1)*t_i2cclk */
+ /* RM0316 */
+
+ if (frequency == 10000)
+ {
+ presc = 0x01;
+ scl_l_period = 0xc7;
+ scl_h_period = 0xc3;
+ h_time = 0x02;
+ s_time = 0x04;
+ }
+ else if (frequency == 100000)
+ {
+ /* values from datasheet with clock 8mhz */
+
+ presc = 0x01;
+ scl_l_period = 0x13;
+ scl_h_period = 0x0f;
+ h_time = 0x02;
+ s_time = 0x04;
+ }
+ else
+ {
+ presc = 0x00;
+ scl_l_period = 0x09;
+ scl_h_period = 0x03;
+ h_time = 0x01;
+ s_time = 0x03;
+ }
+
+ uint32_t timingr =
+ (presc << I2C_TIMINGR_PRESC_SHIFT) |
+ (s_time << I2C_TIMINGR_SCLDEL_SHIFT) |
+ (h_time << I2C_TIMINGR_SDADEL_SHIFT) |
+ (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) |
+ (scl_l_period << I2C_TIMINGR_SCLL_SHIFT);
+
+ stm32f7_i2c_putreg32(priv, STM32F7_I2C_TIMINGR_OFFSET, timingr);
+
+ /* Bit 14 of OAR1 must be configured and kept at 1 */
+
+ stm32f7_i2c_putreg(priv, STM32F7_I2C_OAR1_OFFSET, I2C_OAR1_ONE);
+
+ /* Re-enable the peripheral (or not) */
+
+ if (pe)
+ {
+ stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
+ }
+
+ /* Save the new I2C frequency */
+
+ priv->frequency = frequency;
+ }
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_sendstart
+ *
+ * Description:
+ * Send the START conditions/force Master mode
+ *
+ ************************************************************************************/
+
+static inline void stm32f7_i2c_sendstart(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ /* Get run-time data */
+
+ priv->astart = true;
+ priv->ptr = priv->msgv->buffer;
+ priv->dcnt = priv->msgv->length;
+ priv->flags = priv->msgv->flags;
+
+ /* Disable ACK on receive by default and generate START */
+
+ stm32f7_i2c_set_bytes_to_transfer(priv, priv->dcnt);
+ stm32f7_i2c_set_7bit_address(priv);
+ if (priv->flags & I2C_M_READ)
+ {
+ stm32f7_i2c_set_read_transfer_dir(priv);
+ }
+ else
+ {
+ stm32f7_i2c_set_write_transfer_dir(priv);
+ }
+
+ if (priv->msgc == 1)
+ {
+ /* stm32f7_i2c_enable_autoend(priv); */
+ }
+ else
+ {
+ /* stm32f7_i2c_disable_autoend(priv); */
+ }
+
+ /* TODO check NACK */
+ /* TODO handle NACKR? */
+
+ stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_START);
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_clrstart
+ *
+ * Description:
+ * Clear the STOP, START or PEC condition on certain error recovery steps.
+ *
+ ************************************************************************************/
+
+static inline void stm32f7_i2c_clrstart(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ /* "Note: When the STOP, START or PEC bit is set, the software must
+ * not perform any write access to I2C_CR1 before this bit is
+ * cleared by hardware. Otherwise there is a risk of setting a
+ * second STOP, START or PEC request."
+ *
+ * "The [STOP] bit is set and cleared by software, cleared by hardware
+ * when a Stop condition is detected, set by hardware when a timeout
+ * error is detected.
+ *
+ * "This [START] bit is set and cleared by software and cleared by hardware
+ * when start is sent or PE=0." The bit must be cleared by software if the
+ * START is never sent.
+ *
+ * "This [PEC] bit is set and cleared by software, and cleared by hardware
+ * when PEC is transferred or by a START or Stop condition or when PE=0."
+ */
+
+ /* TODO check PEC (32 bit separate reg) */
+
+ stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET,
+ I2C_CR2_START | I2C_CR2_STOP, 0);
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_sendstop
+ *
+ * Description:
+ * Send the STOP conditions
+ *
+ ************************************************************************************/
+
+static inline void stm32f7_i2c_sendstop(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ /* TODO check NACK */
+
+ stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_STOP);
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_getstatus
+ *
+ * Description:
+ * Get 32-bit status (SR1 and SR2 combined)
+ *
+ ************************************************************************************/
+
+static inline uint32_t stm32f7_i2c_getstatus(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ return getreg32(priv->config->base + STM32F7_I2C_ISR_OFFSET);
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_isr
+ *
+ * Description:
+ * Common logic when a message is started. Just adds the even to the trace buffer
+ * if enabled and adjusts the message pointer and count.
+ *
+ ************************************************************************************/
+
+static inline void stm32f7_i2c_isr_startmessage(struct stm32f7_i2c_priv_s *priv)
+{
+ stm32f7_i2c_traceevent(priv, I2CEVENT_SENDADDR, priv->msgc);
+
+ /* Increment to next pointer and decrement message count */
+
+ priv->msgv++;
+ priv->msgc--;
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_clearinterrupts
+ *
+ * Description:
+ * Clear all interrupts
+ *
+ ************************************************************************************/
+
+static inline void stm32f7_i2c_clearinterrupts(struct stm32f7_i2c_priv_s *priv)
+{
+#warning "check this clears interrupts?"
+ stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK);
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_isr
+ *
+ * Description:
+ * Common Interrupt Service Routine
+ *
+ ************************************************************************************/
+
+static int stm32f7_i2c_isr(struct stm32f7_i2c_priv_s *priv)
+{
+ uint32_t status = stm32f7_i2c_getstatus(priv);
+
+ /* Check for new trace setup */
+
+ stm32f7_i2c_tracenew(priv, status);
+
+#warning "TODO: check clear interrupts after all actions"
+
+ if (STATUS_NACK(status))
+ {
+ /* wait, reset this? */
+ }
+ else if (priv->astart)
+ {
+ stm32f7_i2c_isr_startmessage(priv);
+ priv->astart = false;
+ }
+
+ /* Was address sent, continue with either sending or reading data */
+
+ if ((priv->flags & I2C_M_READ) == 0 && STATUS_ADDR_TX(status))
+ {
+#warning "TODO: ADDRCF clear address interrupt flag"
+ if (priv->dcnt > 0)
+ {
+ /* Send a byte */
+
+ stm32f7_i2c_traceevent(priv, I2CEVENT_SENDBYTE, priv->dcnt);
+ stm32f7_i2c_putreg(priv, STM32F7_I2C_TXDR_OFFSET, *priv->ptr++);
+ priv->dcnt--;
+ }
+ }
+
+ else if ((priv->flags & I2C_M_READ) != 0 && STATUS_ADDR(status))
+ {
+ /* Enable RxNE and TxE buffers in order to receive one or multiple bytes */
+
+#warning "TODO: ADDRCF clear address interrupt flag"
+
+#ifndef CONFIG_I2C_POLLED
+ stm32f7_i2c_traceevent(priv, I2CEVENT_ITBUFEN, 0);
+ stm32f7_i2c_enableinterrupts(priv);
+#endif
+ }
+
+ /* More bytes to read */
+ else if (STATUS_RXNE(status))
+ {
+ /* Read a byte, if dcnt goes < 0, then read dummy bytes to ack ISRs */
+
+ if (priv->dcnt > 0)
+ {
+ stm32f7_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt);
+
+ /* No interrupts or context switches may occur in the following
+ * sequence. Otherwise, additional bytes may be sent by the
+ * device.
+ */
+
+#ifdef CONFIG_I2C_POLLED
+ irqstate_t flags = enter_critical_section();
+#endif
+ /* Receive a byte */
+
+ *priv->ptr++ = stm32f7_i2c_getreg(priv, STM32F7_I2C_RXDR_OFFSET);
+
+ /* Disable acknowledge when last byte is to be received */
+
+ priv->dcnt--;
+ if (priv->dcnt == 1)
+ {
+ /* autoend? */
+ }
+
+#ifdef CONFIG_I2C_POLLED
+ leave_critical_section(flags);
+#endif
+ }
+ }
+
+ /* Do we have more bytes to send, enable/disable buffer interrupts
+ * (these ISRs could be replaced by DMAs)
+ */
+
+#ifndef CONFIG_I2C_POLLED
+ if (priv->dcnt > 0)
+ {
+ stm32f7_i2c_traceevent(priv, I2CEVENT_REITBUFEN, 0);
+ stm32f7_i2c_enableinterrupts(priv);
+ }
+ else if ((priv->dcnt == 0) && (priv->msgc == 0))
+ {
+ stm32f7_i2c_traceevent(priv, I2CEVENT_DISITBUFEN, 0);
+ stm32f7_i2c_disableinterrupts(priv);
+ }
+#endif
+
+ /* Was last byte received or sent? Hmmm... the F2 and F4 seems to differ from
+ * the F1 in that BTF is not set after data is received (only RXNE).
+ */
+
+ if (priv->dcnt <= 0 && STATUS_TC(status))
+ {
+ /* ??? */
+
+ /* Do we need to terminate or restart after this byte?
+ * If there are more messages to send, then we may:
+ *
+ * - continue with repeated start
+ * - or just continue sending writeable part
+ * - or we close down by sending the stop bit
+ */
+
+ if (priv->msgc > 0)
+ {
+ if (priv->msgv->flags & I2C_M_NORESTART)
+ {
+ stm32f7_i2c_traceevent(priv, I2CEVENT_BTFNOSTART, priv->msgc);
+ priv->ptr = priv->msgv->buffer;
+ priv->dcnt = priv->msgv->length;
+ priv->flags = priv->msgv->flags;
+ priv->msgv++;
+ priv->msgc--;
+
+ /* Restart this ISR! */
+
+#ifndef CONFIG_I2C_POLLED
+ stm32f7_i2c_enableinterrupts(priv);
+#endif
+ }
+ else
+ {
+ stm32f7_i2c_traceevent(priv, I2CEVENT_BTFRESTART, priv->msgc);
+ /* ??? */
+ stm32f7_i2c_sendstart(priv);
+ }
+ }
+ else if (priv->msgv)
+ {
+ stm32f7_i2c_traceevent(priv, I2CEVENT_BTFSTOP, 0);
+
+ stm32f7_i2c_sendstop(priv);
+
+ /* Is there a thread waiting for this event (there should be) */
+
+#ifndef CONFIG_I2C_POLLED
+ if (priv->intstate == INTSTATE_WAITING)
+ {
+ /* Yes.. inform the thread that the transfer is complete
+ * and wake it up.
+ */
+
+ sem_post(&priv->sem_isr);
+ priv->intstate = INTSTATE_DONE;
+ }
+#else
+ priv->intstate = INTSTATE_DONE;
+#endif
+
+ /* Mark that we have stopped with this transaction */
+
+ priv->msgv = NULL;
+ }
+ }
+
+ /* Check for errors, in which case, stop the transfer and return
+ * Note that in master reception mode AF becomes set on last byte
+ * since ACK is not returned. We should ignore this error.
+ */
+
+ if ((status & I2C_ISR_ERRORMASK) != 0)
+ {
+ stm32f7_i2c_traceevent(priv, I2CEVENT_ERROR, 0);
+
+ /* Clear interrupt flags */
+
+ stm32f7_i2c_clearinterrupts(priv);
+
+ /* Is there a thread waiting for this event (there should be) */
+
+#ifndef CONFIG_I2C_POLLED
+ if (priv->intstate == INTSTATE_WAITING)
+ {
+ /* Yes.. inform the thread that the transfer is complete
+ * and wake it up.
+ */
+
+ sem_post(&priv->sem_isr);
+ priv->intstate = INTSTATE_DONE;
+ }
+#else
+ priv->intstate = INTSTATE_DONE;
+#endif
+ }
+
+ priv->status = status;
+ return OK;
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c1_isr
+ *
+ * Description:
+ * I2C1 interrupt service routine
+ *
+ ************************************************************************************/
+
+#ifndef CONFIG_I2C_POLLED
+#ifdef CONFIG_STM32F7_I2C1
+static int stm32f7_i2c1_isr(int irq, void *context)
+{
+ return stm32f7_i2c_isr(&stm32f7_i2c1_priv);
+}
+#endif
+
+/************************************************************************************
+ * Name: stm32f7_i2c2_isr
+ *
+ * Description:
+ * I2C2 interrupt service routine
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F7_I2C2
+static int stm32f7_i2c2_isr(int irq, void *context)
+{
+ return stm32f7_i2c_isr(&stm32f7_i2c2_priv);
+}
+#endif
+
+/************************************************************************************
+ * Name: stm32f7_i2c3_isr
+ *
+ * Description:
+ * I2C2 interrupt service routine
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F7_I2C3
+static int stm32f7_i2c3_isr(int irq, void *context)
+{
+ return stm32f7_i2c_isr(&stm32f7_i2c3_priv);
+}
+#endif
+#endif
+
+/************************************************************************************
+ * Private Initialization and Deinitialization
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32f7_i2c_init
+ *
+ * Description:
+ * Setup the I2C hardware, ready for operation with defaults
+ *
+ ************************************************************************************/
+
+static int stm32f7_i2c_init(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ /* Power-up and configure GPIOs */
+
+ /* Enable power and reset the peripheral */
+
+ modifyreg32(STM32F7_RCC_APB1ENR, 0, priv->config->clk_bit);
+ modifyreg32(STM32F7_RCC_APB1RSTR, 0, priv->config->reset_bit);
+ modifyreg32(STM32F7_RCC_APB1RSTR, priv->config->reset_bit, 0);
+
+ /* Configure pins */
+
+ if (stm32f7_configgpio(priv->config->scl_pin) < 0)
+ {
+ return ERROR;
+ }
+
+ if (stm32f7_configgpio(priv->config->sda_pin) < 0)
+ {
+ stm32f7_unconfiggpio(priv->config->scl_pin);
+ return ERROR;
+ }
+
+ /* Attach ISRs */
+
+#ifndef CONFIG_I2C_POLLED
+ irq_attach(priv->config->ev_irq, priv->config->isr);
+ irq_attach(priv->config->er_irq, priv->config->isr);
+ up_enable_irq(priv->config->ev_irq);
+ up_enable_irq(priv->config->er_irq);
+#endif
+
+ /* Set peripheral frequency, where it must be at least 2 MHz for 100 kHz
+ * or 4 MHz for 400 kHz. This also disables all I2C interrupts.
+ */
+
+ /* Force a frequency update */
+
+ priv->frequency = 0;
+
+ /* TODO: f303 i2c clock source RCC_CFGR3 */
+ /* RCC_CFGR3_I2C1SW (default is HSI clock) */
+
+ stm32f7_i2c_setclock(priv, 100000);
+
+ /* Enable I2C */
+
+ stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
+ return OK;
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_deinit
+ *
+ * Description:
+ * Shutdown the I2C hardware
+ *
+ ************************************************************************************/
+
+static int stm32f7_i2c_deinit(FAR struct stm32f7_i2c_priv_s *priv)
+{
+ /* Disable I2C */
+
+ stm32f7_i2c_putreg32(priv, STM32F7_I2C_CR1_OFFSET, 0);
+
+ /* Unconfigure GPIO pins */
+
+ stm32f7_unconfiggpio(priv->config->scl_pin);
+ stm32f7_unconfiggpio(priv->config->sda_pin);
+
+ /* Disable and detach interrupts */
+
+#ifndef CONFIG_I2C_POLLED
+ up_disable_irq(priv->config->ev_irq);
+ up_disable_irq(priv->config->er_irq);
+ irq_detach(priv->config->ev_irq);
+ irq_detach(priv->config->er_irq);
+#endif
+
+ /* Disable clocking */
+
+ modifyreg32(STM32F7_RCC_APB1ENR, priv->config->clk_bit, 0);
+ return OK;
+}
+
+/************************************************************************************
+ * Device Driver Operations
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32f7_i2c_transfer
+ *
+ * Description:
+ * Generic I2C transfer function
+ *
+ ************************************************************************************/
+
+static int stm32f7_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
+ int count)
+{
+ FAR struct stm32f7_i2c_priv_s *priv = (struct stm32f7_i2c_priv_s *)dev;
+ uint32_t status = 0;
+ int ret = OK;
+
+ DEBUGASSERT(dev != NULL && msgs != NULL && count > 0);
+
+ /* Ensure that address or flags don't change meanwhile */
+
+ stm32f7_i2c_sem_wait(priv);
+
+ /* Wait for any STOP in progress. */
+
+ stm32f7_i2c_sem_waitstop(priv);
+
+ /* Clear any pending error interrupts */
+
+ stm32f7_i2c_clearinterrupts(priv);
+
+ /* "Note: When the STOP, START or PEC bit is set, the software must
+ * not perform any write access to I2C_CR1 before this bit is
+ * cleared by hardware. Otherwise there is a risk of setting a
+ * second STOP, START or PEC request." However, if the bits are
+ * not cleared by hardware, then we will have to do that from hardware.
+ */
+
+ stm32f7_i2c_clrstart(priv);
+
+ /* Old transfers are done */
+
+ priv->msgv = msgs;
+ priv->msgc = count;
+
+ /* Reset I2C trace logic */
+
+ stm32f7_i2c_tracereset(priv);
+
+ /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !)
+ * REVISIT: Note that the frequency is set only on the first message.
+ * This could be extended to support different transfer frequencies for
+ * each message segment.
+ */
+
+ stm32f7_i2c_setclock(priv, msgs->frequency);
+
+ /* Trigger start condition, then the process moves into the ISR. I2C
+ * interrupts will be enabled within stm32f7_i2c_waitdone().
+ */
+
+ priv->status = 0;
+
+#ifndef CONFIG_I2C_POLLED
+ stm32f7_i2c_enableinterrupts(priv);
+#endif
+
+ stm32f7_i2c_sendstart(priv);
+
+ /* Wait for an ISR, if there was a timeout, fetch latest status to get
+ * the BUSY flag.
+ */
+
+ if (stm32f7_i2c_sem_waitdone(priv) < 0)
+ {
+ status = stm32f7_i2c_getstatus(priv);
+ ret = -ETIMEDOUT;
+
+ i2cdbg("Timed out: CR1: %04x status: %08x\n",
+ stm32f7_i2c_getreg(priv, STM32F7_I2C_CR1_OFFSET), status);
+
+ /* "Note: When the STOP, START or PEC bit is set, the software must
+ * not perform any write access to I2C_CR1 before this bit is
+ * cleared by hardware. Otherwise there is a risk of setting a
+ * second STOP, START or PEC request."
+ */
+
+ stm32f7_i2c_clrstart(priv);
+
+ /* Clear busy flag in case of timeout */
+
+ status = priv->status & 0xffff;
+ }
+ else
+ {
+ /* clear SR2 (BUSY flag) as we've done successfully */
+
+ status = priv->status & 0xffff;
+ }
+
+ status &= ~I2C_ISR_BUSY;
+#if 0
+ /* Refresh status */
+ do
+ {
+ status = stm32f7_i2c_getstatus(priv);
+ }
+ while (STATUS_BUSY(status));
+#endif
+
+ /* Check for error status conditions */
+
+ if ((status & I2C_ISR_ERRORMASK) != 0)
+ {
+ /* I2C_SR1_ERRORMASK is the 'OR' of the following individual bits: */
+
+ if (status & I2C_INT_BERR)
+ {
+ /* Bus Error */
+
+ ret = -EIO;
+ }
+ else if (status & I2C_INT_ARLO)
+ {
+ /* Arbitration Lost (master mode) */
+
+ ret = -EAGAIN;
+ }
+
+ /* TODO Acknowledge failure */
+
+ else if (status & I2C_INT_OVR)
+ {
+ /* Overrun/Underrun */
+
+ ret = -EIO;
+ }
+ else if (status & I2C_INT_PECERR)
+ {
+ /* PEC Error in reception */
+
+ ret = -EPROTO;
+ }
+ else if (status & I2C_INT_TIMEOUT)
+ {
+ /* Timeout or Tlow Error */
+
+ ret = -ETIME;
+ }
+
+ /* This is not an error and should never happen since SMBus is not
+ * enabled
+ */
+
+ else /* if (status & I2C_INT_ALERT) */
+ {
+ /* SMBus alert is an optional signal with an interrupt line for devices
+ * that want to trade their ability to master for a pin.
+ */
+
+ ret = -EINTR;
+ }
+ }
+
+ /* This is not an error, but should not happen. The BUSY signal can hang,
+ * however, if there are unhealthy devices on the bus that need to be reset.
+ * NOTE: We will only see this buy indication if stm32f7_i2c_sem_waitdone()
+ * fails above; Otherwise it is cleared.
+ */
+
+ else if ((status & I2C_ISR_BUSY) != 0)
+ {
+ /* I2C Bus is for some reason busy */
+
+ ret = -EBUSY;
+ }
+
+ /* Dump the trace result */
+
+ stm32f7_i2c_tracedump(priv);
+ stm32f7_i2c_sem_post(priv);
+ return ret;
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2c_reset
+ *
+ * Description:
+ * Perform an I2C bus reset in an attempt to break loose stuck I2C devices.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno value on failure.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_I2C_RESET
+static int stm32f7_i2c_reset(FAR struct i2c_master_s * dev)
+{
+ unsigned int clock_count;
+ unsigned int stretch_count;
+ uint32_t scl_gpio;
+ uint32_t sda_gpio;
+ uint32_t frequency;
+ int ret = ERROR;
+
+ ASSERT(dev);
+
+ /* Our caller must own a ref */
+
+ ASSERT(priv->refs > 0);
+
+ /* Lock out other clients */
+
+ stm32f7_i2c_sem_wait(priv);
+
+ /* Save the current frequency */
+
+ frequency = priv->frequency;
+
+ /* De-init the port */
+
+ stm32f7_i2c_deinit(priv);
+
+ /* Use GPIO configuration to un-wedge the bus */
+
+ scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin);
+ sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin);
+
+ /* Let SDA go high */
+
+ stm32f7_gpiowrite(sda_gpio, 1);
+
+ /* Clock the bus until any slaves currently driving it let it go. */
+
+ clock_count = 0;
+ while (!stm32f7_gpioread(sda_gpio))
+ {
+ /* Give up if we have tried too hard */
+
+ if (clock_count++ > 10)
+ {
+ goto out;
+ }
+
+ /* Sniff to make sure that clock stretching has finished.
+ *
+ * If the bus never relaxes, the reset has failed.
+ */
+
+ stretch_count = 0;
+ while (!stm32f7_gpioread(scl_gpio))
+ {
+ /* Give up if we have tried too hard */
+
+ if (stretch_count++ > 10)
+ {
+ goto out;
+ }
+
+ up_udelay(10);
+ }
+
+ /* Drive SCL low */
+
+ stm32f7_gpiowrite(scl_gpio, 0);
+ up_udelay(10);
+
+ /* Drive SCL high again */
+
+ stm32f7_gpiowrite(scl_gpio, 1);
+ up_udelay(10);
+ }
+
+ /* Generate a start followed by a stop to reset slave
+ * state machines.
+ */
+
+ stm32f7_gpiowrite(sda_gpio, 0);
+ up_udelay(10);
+ stm32f7_gpiowrite(scl_gpio, 0);
+ up_udelay(10);
+ stm32f7_gpiowrite(scl_gpio, 1);
+ up_udelay(10);
+ stm32f7_gpiowrite(sda_gpio, 1);
+ up_udelay(10);
+
+ /* Revert the GPIO configuration. */
+
+ stm32f7_unconfiggpio(sda_gpio);
+ stm32f7_unconfiggpio(scl_gpio);
+
+ /* Re-init the port */
+
+ stm32f7_i2c_init(priv);
+
+ /* Restore the frequency */
+
+ stm32f7_i2c_setclock(priv, frequency);
+ ret = OK;
+
+out:
+
+ /* Release the port for re-use by other clients */
+
+ stm32f7_i2c_sem_post(priv);
+ return ret;
+}
+#endif /* CONFIG_I2C_RESET */
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32f7_i2cbus_initialize
+ *
+ * Description:
+ * Initialize one I2C bus
+ *
+ ************************************************************************************/
+
+FAR struct i2c_master_s *stm32f7_i2cbus_initialize(int port)
+{
+ struct stm32f7_i2c_priv_s * priv = NULL; /* private data of device with multiple instances */
+ irqtate_t flags;
+
+#if STM32F7_PCLK1_FREQUENCY < 4000000
+# warning STM32F7_I2C_INIT: Peripheral clock must be at least 4 MHz to support 400 kHz operation.
+#endif
+
+#if STM32F7_PCLK1_FREQUENCY < 2000000
+# warning STM32F7_I2C_INIT: Peripheral clock must be at least 2 MHz to support 100 kHz operation.
+ return NULL;
+#endif
+
+ /* Get I2C private structure */
+
+ switch (port)
+ {
+#ifdef CONFIG_STM32F7_I2C1
+ case 1:
+ priv = (struct stm32f7_i2c_priv_s *)&stm32f7_i2c1_priv;
+ break;
+#endif
+#ifdef CONFIG_STM32F7_I2C2
+ case 2:
+ priv = (struct stm32f7_i2c_priv_s *)&stm32f7_i2c2_priv;
+ break;
+#endif
+#ifdef CONFIG_STM32F7_I2C3
+ case 3:
+ priv = (struct stm32f7_i2c_priv_s *)&stm32f7_i2c3_priv;
+ break;
+#endif
+ default:
+ return NULL;
+ }
+
+ /* Init private data for the first time, increment refs count,
+ * power-up hardware and configure GPIOs.
+ */
+
+ flags = enter_critical_section();
+
+ if ((volatile int)priv->refs++ == 0)
+ {
+ stm32f7_i2c_sem_init(priv);
+ stm32f7_i2c_init(priv);
+ }
+
+ leave_critical_section(flags);
+ return (struct i2c_master_s *)priv;
+}
+
+/************************************************************************************
+ * Name: stm32f7_i2cbus_uninitialize
+ *
+ * Description:
+ * Uninitialize an I2C bus
+ *
+ ************************************************************************************/
+
+int stm32f7_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
+{
+ FAR struct stm32f7_i2c_priv_s *priv = (struct stm32f7_i2c_priv_s *)dev;
+ irqstate_t flags;
+
+ ASSERT(dev);
+
+ /* Decrement refs and check for underflow */
+
+ if (priv->refs == 0)
+ {
+ return ERROR;
+ }
+
+ flags = enter_critical_section();
+
+ if (--priv->refs)
+ {
+ leave_critical_section(flags);
+ return OK;
+ }
+
+ leave_critical_section(flags);
+
+ /* Disable power and other HW resource (GPIO's) */
+
+ stm32f7_i2c_deinit(priv);
+
+ /* Release unused resources */
+
+ stm32f7_i2c_sem_destroy(priv);
+ return OK;
+}
+
+#endif /* CONFIG_STM32F7_STM32F30XX */
+#endif /* CONFIG_STM32F7_I2C1 || CONFIG_STM32F7_I2C2 || CONFIG_STM32F7_I2C3 */
+
diff --git a/arch/arm/src/stm32f7/stm32_i2c.h b/arch/arm/src/stm32f7/stm32_i2c.h
new file mode 100644
index 0000000000..9fc26497be
--- /dev/null
+++ b/arch/arm/src/stm32f7/stm32_i2c.h
@@ -0,0 +1,104 @@
+/****************************************************************************
+ * arch/arm/src/stm32f7/stm32_i2c.h
+ *
+ * Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_STM32F7_I2C_H
+#define __ARCH_ARM_SRC_STM32F7_STM32F7_I2C_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+#include
+
+#include "chip.h"
+#include "chip/stm32f7_i2c.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* If a dynamic timeout is selected, then a non-negative, non-zero micro-
+ * seconds per byte value must be provided as well.
+ */
+
+#ifdef CONFIG_STM32F7_I2C_DYNTIMEO
+# if CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE < 1
+# warning "Ignoring CONFIG_STM32F7_I2C_DYNTIMEO because of CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE"
+# undef CONFIG_STM32F7_I2C_DYNTIMEO
+# endif
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32f7_i2cbus_initialize
+ *
+ * Description:
+ * Initialize the selected I2C port. And return a unique instance of struct
+ * struct i2c_master_s. This function may be called to obtain multiple
+ * instances of the interface, each of which may be set up with a
+ * different frequency and slave address.
+ *
+ * Input Parameter:
+ * Port number (for hardware that has multiple I2C interfaces)
+ *
+ * Returned Value:
+ * Valid I2C device structure reference on succcess; a NULL on failure
+ *
+ ****************************************************************************/
+
+FAR struct i2c_master_s *stm32f7_i2cbus_initialize(int port);
+
+/****************************************************************************
+ * Name: stm32f7_i2cbus_uninitialize
+ *
+ * Description:
+ * De-initialize the selected I2C port, and power down the device.
+ *
+ * Input Parameter:
+ * Device structure as returned by the stm32f7_i2cbus_initialize()
+ *
+ * Returned Value:
+ * OK on success, ERROR when internal reference count mismatch or dev
+ * points to invalid hardware device.
+ *
+ ****************************************************************************/
+
+int stm32f7_i2cbus_uninitialize(FAR struct i2c_master_s *dev);
+
+#endif /* __ARCH_ARM_SRC_STM32F7_STM32F7_I2C_H */
diff --git a/configs/stm32f746-ws/src/stm32_spi.c b/configs/stm32f746-ws/src/stm32_spi.c
index e31a63a11d..8544e7d138 100644
--- a/configs/stm32f746-ws/src/stm32_spi.c
+++ b/configs/stm32f746-ws/src/stm32_spi.c
@@ -51,7 +51,7 @@
#include "chip.h"
#include "stm32_spi.h"
-#include "nucleo-144.h"
+#include "stm32f746-ws.h"
#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \
defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \
--
GitLab
From eb9cfd1255e72c74bb8db1965fd09a6085e9a3ff Mon Sep 17 00:00:00 2001
From: pkolesnikov
Date: Mon, 23 May 2016 15:59:24 +0200
Subject: [PATCH 003/400] i2c copy, right include
---
arch/arm/src/stm32f7/Make.defs | 2 +-
arch/arm/src/stm32f7/stm32_i2c.c | 5 ++---
arch/arm/src/stm32f7/stm32_i2c.h | 2 +-
3 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs
index 2f4b7b2513..d8fc2877a9 100644
--- a/arch/arm/src/stm32f7/Make.defs
+++ b/arch/arm/src/stm32f7/Make.defs
@@ -114,7 +114,7 @@ endif
CHIP_ASRCS =
CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c
CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_serial.c
-CHIP_CSRCS += stm32_start.c
+CHIP_CSRCS += stm32_i2c.c stm32_start.c
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += stm32_timerisr.c
diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c
index 01a5995996..ad6724564f 100644
--- a/arch/arm/src/stm32f7/stm32_i2c.c
+++ b/arch/arm/src/stm32f7/stm32_i2c.c
@@ -96,9 +96,8 @@
#include "up_arch.h"
-#include "stm32f7_rcc.h"
-#include "stm32f7_i2c.h"
-#include "stm32f7_waste.h"
+#include "stm32_rcc.h"
+#include "stm32_i2c.h"
/* At least one I2C peripheral must be enabled */
diff --git a/arch/arm/src/stm32f7/stm32_i2c.h b/arch/arm/src/stm32f7/stm32_i2c.h
index 9fc26497be..8829776e63 100644
--- a/arch/arm/src/stm32f7/stm32_i2c.h
+++ b/arch/arm/src/stm32f7/stm32_i2c.h
@@ -44,7 +44,7 @@
#include
#include "chip.h"
-#include "chip/stm32f7_i2c.h"
+#include "chip/stm32_i2c.h"
/****************************************************************************
* Pre-processor Definitions
--
GitLab
From c89a5494b81e793903930f0f67dc7c5d31e57a65 Mon Sep 17 00:00:00 2001
From: unknown
Date: Tue, 24 May 2016 16:57:39 +0100
Subject: [PATCH 004/400] spi, copy
---
arch/arm/src/stm32f7/Make.defs | 2 +-
arch/arm/src/stm32f7/chip/stm32_spi.h | 52 +
.../arm/src/stm32f7/chip/stm32f74xx75xx_spi.h | 207 ++
arch/arm/src/stm32f7/stm32_spi.c | 1846 +++++++++++++++++
arch/arm/src/stm32f7/stm32_spi.h | 122 +-
configs/stm32f746-ws/include/board.h | 9 +-
configs/stm32f746-ws/nsh/defconfig | 4 +-
configs/stm32f746-ws/src/stm32_spi.c | 25 +-
8 files changed, 2201 insertions(+), 66 deletions(-)
create mode 100644 arch/arm/src/stm32f7/chip/stm32_spi.h
create mode 100644 arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h
create mode 100644 arch/arm/src/stm32f7/stm32_spi.c
diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs
index d8fc2877a9..6cce8637eb 100644
--- a/arch/arm/src/stm32f7/Make.defs
+++ b/arch/arm/src/stm32f7/Make.defs
@@ -114,7 +114,7 @@ endif
CHIP_ASRCS =
CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c
CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_serial.c
-CHIP_CSRCS += stm32_i2c.c stm32_start.c
+CHIP_CSRCS += stm32_i2c.c stm32_spi.c stm32_start.c
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += stm32_timerisr.c
diff --git a/arch/arm/src/stm32f7/chip/stm32_spi.h b/arch/arm/src/stm32f7/chip/stm32_spi.h
new file mode 100644
index 0000000000..c6a8d8cd3a
--- /dev/null
+++ b/arch/arm/src/stm32f7/chip/stm32_spi.h
@@ -0,0 +1,52 @@
+/************************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32_spi.h
+ *
+ * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+#include "chip.h"
+
+#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
+# include "chip/stm32f74xx75xx_spi.h"
+#else
+# error "Unsupported STM32 F7 part"
+#endif
+
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h
new file mode 100644
index 0000000000..683acf38ac
--- /dev/null
+++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h
@@ -0,0 +1,207 @@
+/************************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32f7_spi.h
+ *
+ * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SPI_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SPI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Maximum allowed speed as per specifications for all SPIs */
+
+#define STM32F7_SPI_CLK_MAX 27000000UL
+
+/* Register Offsets *****************************************************************/
+
+#define STM32F7_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
+#define STM32F7_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
+#define STM32F7_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
+#define STM32F7_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
+#define STM32F7_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
+#define STM32F7_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
+#define STM32F7_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
+
+/* Register Addresses ***************************************************************/
+
+#if STM32F7_NSPI > 0
+# define STM32F7_SPI1_CR1 (STM32_SPI1_BASE+STM32F7_SPI_CR1_OFFSET)
+# define STM32F7_SPI1_CR2 (STM32_SPI1_BASE+STM32F7_SPI_CR2_OFFSET)
+# define STM32F7_SPI1_SR (STM32_SPI1_BASE+STM32F7_SPI_SR_OFFSET)
+# define STM32F7_SPI1_DR (STM32_SPI1_BASE+STM32F7_SPI_DR_OFFSET)
+# define STM32F7_SPI1_CRCPR (STM32_SPI1_BASE+STM32F7_SPI_CRCPR_OFFSET)
+# define STM32F7_SPI1_RXCRCR (STM32_SPI1_BASE+STM32F7_SPI_RXCRCR_OFFSET)
+# define STM32F7_SPI1_TXCRCR (STM32_SPI1_BASE+STM32F7_SPI_TXCRCR_OFFSET)
+#endif
+
+#if STM32F7_NSPI > 1
+# define STM32F7_SPI2_CR1 (STM32_SPI2_BASE+STM32F7_SPI_CR1_OFFSET)
+# define STM32F7_SPI2_CR2 (STM32_SPI2_BASE+STM32F7_SPI_CR2_OFFSET)
+# define STM32F7_SPI2_SR (STM32_SPI2_BASE+STM32F7_SPI_SR_OFFSET)
+# define STM32F7_SPI2_DR (STM32_SPI2_BASE+STM32F7_SPI_DR_OFFSET)
+# define STM32F7_SPI2_CRCPR (STM32_SPI2_BASE+STM32F7_SPI_CRCPR_OFFSET)
+# define STM32F7_SPI2_RXCRCR (STM32_SPI2_BASE+STM32F7_SPI_RXCRCR_OFFSET)
+# define STM32F7_SPI2_TXCRCR (STM32_SPI2_BASE+STM32F7_SPI_TXCRCR_OFFSET)
+#endif
+
+#if STM32F7_NSPI > 2
+# define STM32F7_SPI3_CR1 (STM32_SPI3_BASE+STM32F7_SPI_CR1_OFFSET)
+# define STM32F7_SPI3_CR2 (STM32_SPI3_BASE+STM32F7_SPI_CR2_OFFSET)
+# define STM32F7_SPI3_SR (STM32_SPI3_BASE+STM32F7_SPI_SR_OFFSET)
+# define STM32F7_SPI3_DR (STM32_SPI3_BASE+STM32F7_SPI_DR_OFFSET)
+# define STM32F7_SPI3_CRCPR (STM32_SPI3_BASE+STM32F7_SPI_CRCPR_OFFSET)
+# define STM32F7_SPI3_RXCRCR (STM32_SPI3_BASE+STM32F7_SPI_RXCRCR_OFFSET)
+# define STM32F7_SPI3_TXCRCR (STM32_SPI3_BASE+STM32F7_SPI_TXCRCR_OFFSET)
+#endif
+
+#if STM32F7_NSPI > 3
+# define STM32F7_SPI4_CR1 (STM32_SPI4_BASE+STM32F7_SPI_CR1_OFFSET)
+# define STM32F7_SPI4_CR2 (STM32_SPI4_BASE+STM32F7_SPI_CR2_OFFSET)
+# define STM32F7_SPI4_SR (STM32_SPI4_BASE+STM32F7_SPI_SR_OFFSET)
+# define STM32F7_SPI4_DR (STM32_SPI4_BASE+STM32F7_SPI_DR_OFFSET)
+# define STM32F7_SPI4_CRCPR (STM32_SPI4_BASE+STM32F7_SPI_CRCPR_OFFSET)
+# define STM32F7_SPI4_RXCRCR (STM32_SPI4_BASE+STM32F7_SPI_RXCRCR_OFFSET)
+# define STM32F7_SPI4_TXCRCR (STM32_SPI4_BASE+STM32F7_SPI_TXCRCR_OFFSET)
+#endif
+
+#if STM32F7_NSPI > 4
+# define STM32F7_SPI5_CR1 (STM32_SPI5_BASE+STM32F7_SPI_CR1_OFFSET)
+# define STM32F7_SPI5_CR2 (STM32_SPI5_BASE+STM32F7_SPI_CR2_OFFSET)
+# define STM32F7_SPI5_SR (STM32_SPI5_BASE+STM32F7_SPI_SR_OFFSET)
+# define STM32F7_SPI5_DR (STM32_SPI5_BASE+STM32F7_SPI_DR_OFFSET)
+# define STM32F7_SPI5_CRCPR (STM32_SPI5_BASE+STM32F7_SPI_CRCPR_OFFSET)
+# define STM32F7_SPI5_RXCRCR (STM32_SPI5_BASE+STM32F7_SPI_RXCRCR_OFFSET)
+# define STM32F7_SPI5_TXCRCR (STM32_SPI5_BASE+STM32F7_SPI_TXCRCR_OFFSET)
+#endif
+
+#if STM32F7_NSPI > 5
+# define STM32F7_SPI6_CR1 (STM32_SPI6_BASE+STM32F7_SPI_CR1_OFFSET)
+# define STM32F7_SPI6_CR2 (STM32_SPI6_BASE+STM32F7_SPI_CR2_OFFSET)
+# define STM32F7_SPI6_SR (STM32_SPI6_BASE+STM32F7_SPI_SR_OFFSET)
+# define STM32F7_SPI6_DR (STM32_SPI6_BASE+STM32F7_SPI_DR_OFFSET)
+# define STM32F7_SPI6_CRCPR (STM32_SPI6_BASE+STM32F7_SPI_CRCPR_OFFSET)
+# define STM32F7_SPI6_RXCRCR (STM32_SPI6_BASE+STM32F7_SPI_RXCRCR_OFFSET)
+# define STM32F7_SPI6_TXCRCR (STM32_SPI6_BASE+STM32F7_SPI_TXCRCR_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* SPI Control Register 1 */
+
+#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */
+#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */
+#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */
+#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */
+#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT)
+# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
+# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
+# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
+# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
+# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
+# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
+# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
+# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
+#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */
+#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */
+#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
+#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
+#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
+#define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */
+#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
+#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */
+
+/* SPI Control Register 2 */
+
+#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
+#define SPI_CR2_NSSP (1 << 3) /* Bit 3: NSS pulse management */
+#define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */
+#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */
+#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */
+#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
+#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */
+#define SPI_CR2_DS_MASK (15 << SPI_CR2_DS_SHIFT)
+# define SPI_CR2_DS_VAL(bits) ( ((bits)-1) << SPI_CR2_DS_SHIFT)
+# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL( 4)
+# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL( 5)
+# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL( 6)
+# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL( 7)
+# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL( 8)
+# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL( 9)
+# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10)
+# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11)
+# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12)
+# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13)
+# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14)
+# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15)
+# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16)
+#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */
+#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */
+#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */
+
+/* SPI status register */
+
+#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */
+#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
+#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */
+#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */
+#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */
+#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
+#define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */
+#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */
+#define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT)
+# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
+# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
+# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
+# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
+#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */
+#define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT)
+# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
+# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
+# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
+# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
+
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SPI_H */
+
diff --git a/arch/arm/src/stm32f7/stm32_spi.c b/arch/arm/src/stm32f7/stm32_spi.c
new file mode 100644
index 0000000000..71b1aa94ec
--- /dev/null
+++ b/arch/arm/src/stm32f7/stm32_spi.c
@@ -0,0 +1,1846 @@
+/************************************************************************************
+ * arm/arm/src/stm32f7/stm32_spi.c
+ *
+ * Copyright (C) 2009-2013, 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * The external functions, stm32f7_spi1/2/3select and stm32f7_spi1/2/3status must be
+ * provided by board-specific logic. They are implementations of the select
+ * and status methods of the SPI interface defined by struct spi_ops_s (see
+ * include/nuttx/spi/spi.h). All other methods (including stm32f7_spibus_initialize())
+ * are provided by common STM32 logic. To use this common SPI logic on your
+ * board:
+ *
+ * 1. Provide logic in stm32f7_boardinitialize() to configure SPI chip select
+ * pins.
+ * 2. Provide stm32f7_spi1/2/3select() and stm32f7_spi1/2/3status() functions in your
+ * board-specific logic. These functions will perform chip selection and
+ * status operations using GPIOs in the way your board is configured.
+ * 3. Add a calls to stm32f7_spibus_initialize() in your low level application
+ * initialization logic
+ * 4. The handle returned by stm32f7_spibus_initialize() may then be used to bind the
+ * SPI driver to higher level logic (e.g., calling
+ * mmcsd_spislotinitialize(), for example, will bind the SPI driver to
+ * the SPI MMC/SD driver).
+ *
+ ****************************************************c********************************/
+
+/* This driver is ported from the stm32 one, which only supports 8 and 16 bits
+ * transfers. The STM32F7 family supports frame size from 4 to 16 bits, but we do not
+ * support that yet. For the moment, we replace uses of the CR1_DFF bit with a check
+ * of the CR2_DS[0..3] bits. If the value is SPI_CR2_DS_16BIT it means 16 bits, else 8 bits.
+ */
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "stm32_gpio.h"
+#include "stm32_dma.h"
+#include "stm32_spi.h"
+#include "chip/stm32_pinmap.h"
+
+#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \
+ defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \
+ defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6)
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Configuration ********************************************************************/
+/* SPI interrupts */
+
+#ifdef CONFIG_STM32F7_SPI_INTERRUPTS
+# error "Interrupt driven SPI not yet supported"
+#endif
+
+/* Can't have both interrupt driven SPI and SPI DMA */
+
+#if defined(CONFIG_STM32F7_SPI_INTERRUPTS) && defined(CONFIG_STM32F7_SPI_DMA)
+# error "Cannot enable both interrupt mode and DMA mode for SPI"
+#endif
+
+/* SPI DMA priority */
+
+#ifdef CONFIG_STM32F7_SPI_DMA
+
+# if defined(CONFIG_SPI_DMAPRIO)
+# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
+# else
+# define SPI_DMA_PRIO DMA_CCR_PRIMED
+# endif
+
+# if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0
+# error "Illegal value for CONFIG_SPI_DMAPRIO"
+# endif
+
+#endif
+
+/* DMA channel configuration */
+
+#define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC )
+#define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC )
+#define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS )
+#define SPI_RXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS )
+#define SPI_TXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC|DMA_CCR_DIR)
+#define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC|DMA_CCR_DIR)
+#define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS |DMA_CCR_DIR)
+#define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_DIR)
+
+
+/* Debug ****************************************************************************/
+/* Check if (non-standard) SPI debug is enabled */
+
+#ifndef CONFIG_DEBUG
+# undef CONFIG_DEBUG_VERBOSE
+# undef CONFIG_DEBUG_SPI
+#endif
+
+#ifdef CONFIG_DEBUG_SPI
+# define spidbg lldbg
+# ifdef CONFIG_DEBUG_VERBOSE
+# define spivdbg lldbg
+# else
+# define spivdbg(x...)
+# endif
+#else
+# define spidbg(x...)
+# define spivdbg(x...)
+#endif
+
+/************************************************************************************
+ * Private Types
+ ************************************************************************************/
+
+struct stm32f7_spidev_s
+{
+ struct spi_dev_s spidev; /* Externally visible part of the SPI interface */
+ uint32_t spibase; /* SPIn base address */
+ uint32_t spiclock; /* Clocking for the SPI module */
+#ifdef CONFIG_STM32F7_SPI_INTERRUPTS
+ uint8_t spiirq; /* SPI IRQ number */
+#endif
+#ifdef CONFIG_STM32F7_SPI_DMA
+ volatile uint8_t rxresult; /* Result of the RX DMA */
+ volatile uint8_t txresult; /* Result of the RX DMA */
+ uint16_t rxch; /* The RX DMA channel number */
+ uint16_t txch; /* The TX DMA channel number */
+ DMA_HANDLE rxdma; /* DMA channel handle for RX transfers */
+ DMA_HANDLE txdma; /* DMA channel handle for TX transfers */
+ sem_t rxsem; /* Wait for RX DMA to complete */
+ sem_t txsem; /* Wait for TX DMA to complete */
+ uint32_t txccr; /* DMA control register for TX transfers */
+ uint32_t rxccr; /* DMA control register for RX transfers */
+#endif
+ sem_t exclsem; /* Held while chip is selected for mutual exclusion */
+ uint32_t frequency; /* Requested clock frequency */
+ uint32_t actual; /* Actual clock frequency */
+ int8_t nbits; /* Width of word in bits (8 or 16) */
+ uint8_t mode; /* Mode 0,1,2,3 */
+};
+
+/************************************************************************************
+ * Private Function Prototypes
+ ************************************************************************************/
+
+/* Helpers */
+
+static inline uint16_t spi_getreg(FAR struct stm32f7_spidev_s *priv, uint8_t offset);
+static inline void spi_putreg(FAR struct stm32f7_spidev_s *priv, uint8_t offset,
+ uint16_t value);
+static inline uint16_t spi_readword(FAR struct stm32f7_spidev_s *priv);
+static inline void spi_writeword(FAR struct stm32f7_spidev_s *priv, uint16_t byte);
+static inline bool spi_16bitmode(FAR struct stm32f7_spidev_s *priv);
+
+/* DMA support */
+
+#ifdef CONFIG_STM32F7_SPI_DMA
+static void spi_dmarxwait(FAR struct stm32f7_spidev_s *priv);
+static void spi_dmatxwait(FAR struct stm32f7_spidev_s *priv);
+static inline void spi_dmarxwakeup(FAR struct stm32f7_spidev_s *priv);
+static inline void spi_dmatxwakeup(FAR struct stm32f7_spidev_s *priv);
+static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg);
+static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg);
+static void spi_dmarxsetup(FAR struct stm32f7_spidev_s *priv,
+ FAR void *rxbuffer, FAR void *rxdummy, size_t nwords);
+static void spi_dmatxsetup(FAR struct stm32f7_spidev_s *priv,
+ FAR const void *txbuffer, FAR const void *txdummy, size_t nwords);
+static inline void spi_dmarxstart(FAR struct stm32f7_spidev_s *priv);
+static inline void spi_dmatxstart(FAR struct stm32f7_spidev_s *priv);
+#endif
+
+/* SPI methods */
+
+static int spi_lock(FAR struct spi_dev_s *dev, bool lock);
+static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency);
+static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode);
+static void spi_setbits(FAR struct spi_dev_s *dev, int nbits);
+static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd);
+static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
+ FAR void *rxbuffer, size_t nwords);
+#ifndef CONFIG_SPI_EXCHANGE
+static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
+ size_t nwords);
+static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer,
+ size_t nwords);
+#endif
+
+/* Initialization */
+
+static void spi_bus_initialize(FAR struct stm32f7_spidev_s *priv);
+
+/************************************************************************************
+ * Private Data
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F7_SPI1
+static const struct spi_ops_s g_spi1ops =
+{
+ .lock = spi_lock,
+ .select = stm32f7_spi1select,
+ .setfrequency = spi_setfrequency,
+ .setmode = spi_setmode,
+ .setbits = spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = 0, /* Not supported */
+#endif
+ .status = stm32f7_spi1status,
+#ifdef CONFIG_SPI_CMDDATA
+ .cmddata = stm32f7_spi1cmddata,
+#endif
+ .send = spi_send,
+#ifdef CONFIG_SPI_EXCHANGE
+ .exchange = spi_exchange,
+#else
+ .sndblock = spi_sndblock,
+ .recvblock = spi_recvblock,
+#endif
+#ifdef CONFIG_SPI_CALLBACK
+ .registercallback = stm32f7_spi1register, /* Provided externally */
+#else
+ .registercallback = 0, /* Not implemented */
+#endif
+};
+
+static struct stm32f7_spidev_s g_spi1dev =
+{
+ .spidev = { &g_spi1ops },
+ .spibase = STM32_SPI1_BASE,
+ .spiclock = STM32_PCLK2_FREQUENCY,
+#ifdef CONFIG_STM32F7_SPI_INTERRUPTS
+ .spiirq = STM32_IRQ_SPI1,
+#endif
+#ifdef CONFIG_STM32F7_SPI_DMA
+ /* lines must be configured in board.h */
+ .rxch = DMACHAN_SPI1_RX,
+ .txch = DMACHAN_SPI1_TX,
+#endif
+};
+#endif
+
+#ifdef CONFIG_STM32F7_SPI2
+static const struct spi_ops_s g_spi2ops =
+{
+ .lock = spi_lock,
+ .select = stm32f7_spi2select,
+ .setfrequency = spi_setfrequency,
+ .setmode = spi_setmode,
+ .setbits = spi_setbits,
+ .status = stm32f7_spi2status,
+#ifdef CONFIG_SPI_CMDDATA
+ .cmddata = stm32f7_spi2cmddata,
+#endif
+ .send = spi_send,
+#ifdef CONFIG_SPI_EXCHANGE
+ .exchange = spi_exchange,
+#else
+ .sndblock = spi_sndblock,
+ .recvblock = spi_recvblock,
+#endif
+#ifdef CONFIG_SPI_CALLBACK
+ .registercallback = stm32f7_spi2register, /* provided externally */
+#else
+ .registercallback = 0, /* not implemented */
+#endif
+};
+
+static struct stm32f7_spidev_s g_spi2dev =
+{
+ .spidev = { &g_spi2ops },
+ .spibase = STM32_SPI2_BASE,
+ .spiclock = STM32_PCLK1_FREQUENCY,
+#ifdef CONFIG_STM32F7_SPI_INTERRUPTS
+ .spiirq = STM32_IRQ_SPI2,
+#endif
+#ifdef CONFIG_STM32F7_SPI_DMA
+ .rxch = DMACHAN_SPI2_RX,
+ .txch = DMACHAN_SPI2_TX,
+#endif
+};
+#endif
+
+#ifdef CONFIG_STM32F7_SPI3
+static const struct spi_ops_s g_spi3ops =
+{
+ .lock = spi_lock,
+ .select = stm32f7_spi3select,
+ .setfrequency = spi_setfrequency,
+ .setmode = spi_setmode,
+ .setbits = spi_setbits,
+ .status = stm32f7_spi3status,
+#ifdef CONFIG_SPI_CMDDATA
+ .cmddata = stm32f7_spi3cmddata,
+#endif
+ .send = spi_send,
+#ifdef CONFIG_SPI_EXCHANGE
+ .exchange = spi_exchange,
+#else
+ .sndblock = spi_sndblock,
+ .recvblock = spi_recvblock,
+#endif
+#ifdef CONFIG_SPI_CALLBACK
+ .registercallback = stm32f7_spi3register, /* provided externally */
+#else
+ .registercallback = 0, /* not implemented */
+#endif
+};
+
+static struct stm32f7_spidev_s g_spi3dev =
+{
+ .spidev = { &g_spi3ops },
+ .spibase = STM32_SPI3_BASE,
+ .spiclock = STM32_PCLK1_FREQUENCY,
+#ifdef CONFIG_STM32F7_SPI_INTERRUPTS
+ .spiirq = STM32_IRQ_SPI3,
+#endif
+#ifdef CONFIG_STM32F7_SPI_DMA
+ .rxch = DMACHAN_SPI3_RX,
+ .txch = DMACHAN_SPI3_TX,
+#endif
+};
+#endif
+
+#ifdef CONFIG_STM32F7_SPI4
+static const struct spi_ops_s g_spi4ops =
+{
+ .lock = spi_lock,
+ .select = stm32f7_spi4select,
+ .setfrequency = spi_setfrequency,
+ .setmode = spi_setmode,
+ .setbits = spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = 0, /* Not supported */
+#endif
+ .status = stm32f7_spi4status,
+#ifdef CONFIG_SPI_CMDDATA
+ .cmddata = stm32f7_spi4cmddata,
+#endif
+ .send = spi_send,
+#ifdef CONFIG_SPI_EXCHANGE
+ .exchange = spi_exchange,
+#else
+ .sndblock = spi_sndblock,
+ .recvblock = spi_recvblock,
+#endif
+#ifdef CONFIG_SPI_CALLBACK
+ .registercallback = stm32f7_spi4register, /* Provided externally */
+#else
+ .registercallback = 0, /* Not implemented */
+#endif
+};
+
+static struct stm32f7_spidev_s g_spi4dev =
+{
+ .spidev = { &g_spi4ops },
+ .spibase = STM32_SPI4_BASE,
+ .spiclock = STM32_PCLK2_FREQUENCY,
+#ifdef CONFIG_STM32F7_SPI_INTERRUPTS
+ .spiirq = STM32_IRQ_SPI4,
+#endif
+#ifdef CONFIG_STM32F7_SPI_DMA
+ /* lines must be configured in board.h */
+ .rxch = DMACHAN_SPI4_RX,
+ .txch = DMACHAN_SPI4_TX,
+#endif
+};
+#endif
+
+#ifdef CONFIG_STM32F7_SPI5
+static const struct spi_ops_s g_spi5ops =
+{
+ .lock = spi_lock,
+ .select = stm32f7_spi5select,
+ .setfrequency = spi_setfrequency,
+ .setmode = spi_setmode,
+ .setbits = spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = 0, /* Not supported */
+#endif
+ .status = stm32f7_spi5status,
+#ifdef CONFIG_SPI_CMDDATA
+ .cmddata = stm32f7_spi5cmddata,
+#endif
+ .send = spi_send,
+#ifdef CONFIG_SPI_EXCHANGE
+ .exchange = spi_exchange,
+#else
+ .sndblock = spi_sndblock,
+ .recvblock = spi_recvblock,
+#endif
+#ifdef CONFIG_SPI_CALLBACK
+ .registercallback = stm32f7_spi5register, /* Provided externally */
+#else
+ .registercallback = 0, /* Not implemented */
+#endif
+};
+
+static struct stm32f7_spidev_s g_spi5dev =
+{
+ .spidev = { &g_spi5ops },
+ .spibase = STM32_SPI5_BASE,
+ .spiclock = STM32_PCLK2_FREQUENCY,
+#ifdef CONFIG_STM32F7_SPI_INTERRUPTS
+ .spiirq = STM32_IRQ_SPI5,
+#endif
+#ifdef CONFIG_STM32F7_SPI_DMA
+ /* lines must be configured in board.h */
+ .rxch = DMACHAN_SPI5_RX,
+ .txch = DMACHAN_SPI5_TX,
+#endif
+};
+#endif
+
+#ifdef CONFIG_STM32F7_SPI6
+static const struct spi_ops_s g_spi6ops =
+{
+ .lock = spi_lock,
+ .select = stm32f7_spi6select,
+ .setfrequency = spi_setfrequency,
+ .setmode = spi_setmode,
+ .setbits = spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = 0, /* Not supported */
+#endif
+ .status = stm32f7_spi6status,
+#ifdef CONFIG_SPI_CMDDATA
+ .cmddata = stm32f7_spi6cmddata,
+#endif
+ .send = spi_send,
+#ifdef CONFIG_SPI_EXCHANGE
+ .exchange = spi_exchange,
+#else
+ .sndblock = spi_sndblock,
+ .recvblock = spi_recvblock,
+#endif
+#ifdef CONFIG_SPI_CALLBACK
+ .registercallback = stm32f7_spi6register, /* Provided externally */
+#else
+ .registercallback = 0, /* Not implemented */
+#endif
+};
+
+static struct stm32f7_spidev_s g_spi6dev =
+{
+ .spidev = { &g_spi6ops },
+ .spibase = STM32_SPI6_BASE,
+ .spiclock = STM32_PCLK2_FREQUENCY,
+#ifdef CONFIG_STM32F7_SPI_INTERRUPTS
+ .spiirq = STM32_IRQ_SPI6,
+#endif
+#ifdef CONFIG_STM32F7_SPI_DMA
+ /* lines must be configured in board.h */
+ .rxch = DMACHAN_SPI6_RX,
+ .txch = DMACHAN_SPI6_TX,
+#endif
+};
+#endif
+
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: spi_getreg
+ *
+ * Description:
+ * Get the contents of the SPI register at offset
+ *
+ * Input Parameters:
+ * priv - private SPI device structure
+ * offset - offset to the register of interest
+ *
+ * Returned Value:
+ * The contents of the 16-bit register
+ *
+ ************************************************************************************/
+
+static inline uint16_t spi_getreg(FAR struct stm32f7_spidev_s *priv, uint8_t offset)
+{
+ return getreg16(priv->spibase + offset);
+}
+
+/************************************************************************************
+ * Name: spi_putreg
+ *
+ * Description:
+ * Write a 16-bit value to the SPI register at offset
+ *
+ * Input Parameters:
+ * priv - private SPI device structure
+ * offset - offset to the register of interest
+ * value - the 16-bit value to be written
+ *
+ * Returned Value:
+ * The contents of the 16-bit register
+ *
+ ************************************************************************************/
+
+static inline void spi_putreg(FAR struct stm32f7_spidev_s *priv, uint8_t offset,
+ uint16_t value)
+{
+ putreg16(value, priv->spibase + offset);
+}
+
+/************************************************************************************
+ * Name: spi_getreg8
+ *
+ * Description:
+ * Get the contents of the SPI register at offset
+ *
+ * Input Parameters:
+ * priv - private SPI device structure
+ * offset - offset to the register of interest
+ *
+ * Returned Value:
+ * The contents of the 8-bit register
+ *
+ ************************************************************************************/
+
+static inline uint8_t spi_getreg8(FAR struct stm32f7_spidev_s *priv, uint8_t offset)
+{
+ return getreg8(priv->spibase + offset);
+}
+
+/************************************************************************************
+ * Name: spi_putreg8
+ *
+ * Description:
+ * Write a 8-bit value to the SPI register at offset
+ *
+ * Input Parameters:
+ * priv - private SPI device structure
+ * offset - offset to the register of interest
+ * value - the 8-bit value to be written
+ *
+ ************************************************************************************/
+
+static inline void spi_putreg8(FAR struct stm32f7_spidev_s *priv, uint8_t offset,
+ uint8_t value)
+{
+ putreg8(value, priv->spibase + offset);
+}
+
+/************************************************************************************
+ * Name: spi_readword
+ *
+ * Description:
+ * Read one word (TWO bytes!) from SPI
+ *
+ * Input Parameters:
+ * priv - Device-specific state data
+ *
+ * Returned Value:
+ * Word as read
+ *
+ ************************************************************************************/
+
+static inline uint16_t spi_readword(FAR struct stm32f7_spidev_s *priv)
+{
+ /* Wait until the receive buffer is not empty */
+
+ while ((spi_getreg(priv, STM32F7_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0);
+
+ /* Then return the received byte */
+
+ return spi_getreg(priv, STM32F7_SPI_DR_OFFSET);
+}
+
+/************************************************************************************
+ * Name: spi_readbyte
+ *
+ * Description:
+ * Read one byte from SPI
+ *
+ * Input Parameters:
+ * priv - Device-specific state data
+ *
+ * Returned Value:
+ * Byte as read
+ *
+ ************************************************************************************/
+
+static inline uint8_t spi_readbyte(FAR struct stm32f7_spidev_s *priv)
+{
+ /* Wait until the receive buffer is not empty */
+
+ while ((spi_getreg(priv, STM32F7_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0);
+
+ /* Then return the received byte */
+
+ return spi_getreg8(priv, STM32F7_SPI_DR_OFFSET);
+}
+
+/************************************************************************************
+ * Name: spi_writeword
+ *
+ * Description:
+ * Write one 16-bit frame to the SPI FIFO
+ *
+ * Input Parameters:
+ * priv - Device-specific state data
+ * byte - Word to send
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+static inline void spi_writeword(FAR struct stm32f7_spidev_s *priv, uint16_t word)
+{
+ /* Wait until the transmit buffer is empty */
+
+ while ((spi_getreg(priv, STM32F7_SPI_SR_OFFSET) & SPI_SR_TXE) == 0);
+
+ /* Then send the byte */
+
+ spi_putreg(priv, STM32F7_SPI_DR_OFFSET, word);
+}
+
+/************************************************************************************
+ * Name: spi_writebyte
+ *
+ * Description:
+ * Write one 8-bit frame to the SPI FIFO
+ *
+ * Input Parameters:
+ * priv - Device-specific state data
+ * byte - Byte to send
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+static inline void spi_writebyte(FAR struct stm32f7_spidev_s *priv, uint8_t byte)
+{
+ /* Wait until the transmit buffer is empty */
+
+ while ((spi_getreg(priv, STM32F7_SPI_SR_OFFSET) & SPI_SR_TXE) == 0);
+
+ /* Then send the byte */
+
+ spi_putreg8(priv, STM32F7_SPI_DR_OFFSET, byte);
+}
+
+/************************************************************************************
+ * Name: spi_16bitmode
+ *
+ * Description:
+ * Check if the SPI is operating in 16-bit mode
+ *
+ * Input Parameters:
+ * priv - Device-specific state data
+ *
+ * Returned Value:
+ * true: 16-bit mode, false: 8-bit mode
+ *
+ ************************************************************************************/
+
+static inline bool spi_16bitmode(FAR struct stm32f7_spidev_s *priv)
+{
+ uint8_t bits = priv->nbits;
+
+ /* Get the real number of bits */
+
+ if (bits < 0)
+ {
+ bits = -bits;
+ }
+
+ return (bits > 8);
+
+ /* Should we read the hardware regs? seems to be equivalent ~~ sebastien lorquet
+ * (20160413)
+ */
+
+// return ((spi_getreg(priv, STM32F7_SPI_CR2_OFFSET) & SPI_CR2_DS_MASK) == SPI_CR2_DS_16BIT);
+}
+
+/************************************************************************************
+ * Name: spi_dmarxwaitw
+ *
+ * Description:
+ * Wait for DMA to complete.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F7_SPI_DMA
+static void spi_dmarxwait(FAR struct stm32f7_spidev_s *priv)
+{
+ /* Take the semaphore (perhaps waiting). If the result is zero, then the DMA
+ * must not really have completed???
+ */
+
+ while (sem_wait(&priv->rxsem) != 0 || priv->rxresult == 0)
+ {
+ /* The only case that an error should occur here is if the wait was awakened
+ * by a signal.
+ */
+
+ ASSERT(errno == EINTR);
+ }
+}
+#endif
+
+/************************************************************************************
+ * Name: spi_dmatxwait
+ *
+ * Description:
+ * Wait for DMA to complete.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F7_SPI_DMA
+static void spi_dmatxwait(FAR struct stm32f7_spidev_s *priv)
+{
+ /* Take the semaphore (perhaps waiting). If the result is zero, then the DMA
+ * must not really have completed???
+ */
+
+ while (sem_wait(&priv->txsem) != 0 || priv->txresult == 0)
+ {
+ /* The only case that an error should occur here is if the wait was awakened
+ * by a signal.
+ */
+
+ ASSERT(errno == EINTR);
+ }
+}
+#endif
+
+/************************************************************************************
+ * Name: spi_dmarxwakeup
+ *
+ * Description:
+ * Signal that DMA is complete
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F7_SPI_DMA
+static inline void spi_dmarxwakeup(FAR struct stm32f7_spidev_s *priv)
+{
+ (void)sem_post(&priv->rxsem);
+}
+#endif
+
+/************************************************************************************
+ * Name: spi_dmatxwakeup
+ *
+ * Description:
+ * Signal that DMA is complete
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F7_SPI_DMA
+static inline void spi_dmatxwakeup(FAR struct stm32f7_spidev_s *priv)
+{
+ (void)sem_post(&priv->txsem);
+}
+#endif
+
+/************************************************************************************
+ * Name: spi_dmarxcallback
+ *
+ * Description:
+ * Called when the RX DMA completes
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F7_SPI_DMA
+static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
+{
+ FAR struct stm32f7_spidev_s *priv = (FAR struct stm32f7_spidev_s *)arg;
+
+ /* Wake-up the SPI driver */
+
+ priv->rxresult = isr | 0x080; /* OR'ed with 0x80 to assure non-zero */
+ spi_dmarxwakeup(priv);
+}
+#endif
+
+/************************************************************************************
+ * Name: spi_dmatxcallback
+ *
+ * Description:
+ * Called when the RX DMA completes
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F7_SPI_DMA
+static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
+{
+ FAR struct stm32f7_spidev_s *priv = (FAR struct stm32f7_spidev_s *)arg;
+
+ /* Wake-up the SPI driver */
+
+ priv->txresult = isr | 0x080; /* OR'ed with 0x80 to assure non-zero */
+ spi_dmatxwakeup(priv);
+}
+#endif
+
+/************************************************************************************
+ * Name: spi_dmarxsetup
+ *
+ * Description:
+ * Setup to perform RX DMA
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F7_SPI_DMA
+static void spi_dmarxsetup(FAR struct stm32f7_spidev_s *priv, FAR void *rxbuffer,
+ FAR void *rxdummy, size_t nwords)
+{
+ /* 8- or 16-bit mode? */
+
+ if (spi_16bitmode(priv))
+ {
+ /* 16-bit mode -- is there a buffer to receive data in? */
+
+ if (rxbuffer)
+ {
+ priv->rxccr = SPI_RXDMA16_CONFIG;
+ }
+ else
+ {
+ rxbuffer = rxdummy;
+ priv->rxccr = SPI_RXDMA16NULL_CONFIG;
+ }
+ }
+ else
+ {
+ /* 8-bit mode -- is there a buffer to receive data in? */
+
+ if (rxbuffer)
+ {
+ priv->rxccr = SPI_RXDMA8_CONFIG;
+ }
+ else
+ {
+ rxbuffer = rxdummy;
+ priv->rxccr = SPI_RXDMA8NULL_CONFIG;
+ }
+ }
+
+ /* Configure the RX DMA */
+
+ stm32f7_dmasetup(priv->rxdma, priv->spibase + STM32F7_SPI_DR_OFFSET,
+ (uint32_t)rxbuffer, nwords, priv->rxccr);
+}
+#endif
+
+/************************************************************************************
+ * Name: spi_dmatxsetup
+ *
+ * Description:
+ * Setup to perform TX DMA
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F7_SPI_DMA
+static void spi_dmatxsetup(FAR struct stm32f7_spidev_s *priv, FAR const void *txbuffer,
+ FAR const void *txdummy, size_t nwords)
+{
+ /* 8- or 16-bit mode? */
+
+ if (spi_16bitmode(priv))
+ {
+ /* 16-bit mode -- is there a buffer to transfer data from? */
+
+ if (txbuffer)
+ {
+ priv->txccr = SPI_TXDMA16_CONFIG;
+ }
+ else
+ {
+ txbuffer = txdummy;
+ priv->txccr = SPI_TXDMA16NULL_CONFIG;
+ }
+ }
+ else
+ {
+ /* 8-bit mode -- is there a buffer to transfer data from? */
+
+ if (txbuffer)
+ {
+ priv->txccr = SPI_TXDMA8_CONFIG;
+ }
+ else
+ {
+ txbuffer = txdummy;
+ priv->txccr = SPI_TXDMA8NULL_CONFIG;
+ }
+ }
+
+ /* Setup the TX DMA */
+
+ stm32f7_dmasetup(priv->txdma, priv->spibase + STM32F7_SPI_DR_OFFSET,
+ (uint32_t)txbuffer, nwords, priv->txccr);
+}
+#endif
+
+/************************************************************************************
+ * Name: spi_dmarxstart
+ *
+ * Description:
+ * Start RX DMA
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F7_SPI_DMA
+static inline void spi_dmarxstart(FAR struct stm32f7_spidev_s *priv)
+{
+ priv->rxresult = 0;
+ stm32f7_dmastart(priv->rxdma, spi_dmarxcallback, priv, false);
+}
+#endif
+
+/************************************************************************************
+ * Name: spi_dmatxstart
+ *
+ * Description:
+ * Start TX DMA
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F7_SPI_DMA
+static inline void spi_dmatxstart(FAR struct stm32f7_spidev_s *priv)
+{
+ priv->txresult = 0;
+ stm32f7_dmastart(priv->txdma, spi_dmatxcallback, priv, false);
+}
+#endif
+
+/************************************************************************************
+ * Name: spi_modifycr
+ *
+ * Description:
+ * Clear and set bits in the CR1 or CR2 register
+ *
+ * Input Parameters:
+ * priv - Device-specific state data
+ * clrbits - The bits to clear
+ * setbits - The bits to set
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+static void spi_modifycr(uint32_t addr, FAR struct stm32f7_spidev_s *priv, uint16_t setbits, uint16_t clrbits)
+{
+ uint16_t cr;
+
+ cr = spi_getreg(priv, addr);
+ cr &= ~clrbits;
+ cr |= setbits;
+ spi_putreg(priv, addr, cr);
+}
+
+/************************************************************************************
+ * Name: spi_lock
+ *
+ * Description:
+ * On SPI busses where there are multiple devices, it will be necessary to
+ * lock SPI to have exclusive access to the busses for a sequence of
+ * transfers. The bus should be locked before the chip is selected. After
+ * locking the SPI bus, the caller should then also call the setfrequency,
+ * setbits, and setmode methods to make sure that the SPI is properly
+ * configured for the device. If the SPI buss is being shared, then it
+ * may have been left in an incompatible state.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * lock - true: Lock spi bus, false: unlock SPI bus
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
+{
+ FAR struct stm32f7_spidev_s *priv = (FAR struct stm32f7_spidev_s *)dev;
+
+ if (lock)
+ {
+ /* Take the semaphore (perhaps waiting) */
+
+ while (sem_wait(&priv->exclsem) != 0)
+ {
+ /* The only case that an error should occur here is if the wait was awakened
+ * by a signal.
+ */
+
+ ASSERT(errno == EINTR);
+ }
+ }
+ else
+ {
+ (void)sem_post(&priv->exclsem);
+ }
+ return OK;
+}
+
+/************************************************************************************
+ * Name: spi_setfrequency
+ *
+ * Description:
+ * Set the SPI frequency.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * frequency - The SPI frequency requested
+ *
+ * Returned Value:
+ * Returns the actual frequency selected
+ *
+ ************************************************************************************/
+
+static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
+{
+ FAR struct stm32f7_spidev_s *priv = (FAR struct stm32f7_spidev_s *)dev;
+ uint16_t setbits;
+ uint32_t actual;
+
+ /* Limit to max possible (if STM32F7_SPI_CLK_MAX is defined in board.h) */
+
+ if (frequency > STM32F7_SPI_CLK_MAX)
+ {
+ frequency = STM32F7_SPI_CLK_MAX;
+ }
+
+ /* Has the frequency changed? */
+
+ if (frequency != priv->frequency)
+ {
+ /* Choices are limited by PCLK frequency with a set of divisors */
+
+ if (frequency >= priv->spiclock >> 1)
+ {
+ /* More than fPCLK/2. This is as fast as we can go */
+
+ setbits = SPI_CR1_FPCLCKd2; /* 000: fPCLK/2 */
+ actual = priv->spiclock >> 1;
+ }
+ else if (frequency >= priv->spiclock >> 2)
+ {
+ /* Between fPCLCK/2 and fPCLCK/4, pick the slower */
+
+ setbits = SPI_CR1_FPCLCKd4; /* 001: fPCLK/4 */
+ actual = priv->spiclock >> 2;
+ }
+ else if (frequency >= priv->spiclock >> 3)
+ {
+ /* Between fPCLCK/4 and fPCLCK/8, pick the slower */
+
+ setbits = SPI_CR1_FPCLCKd8; /* 010: fPCLK/8 */
+ actual = priv->spiclock >> 3;
+ }
+ else if (frequency >= priv->spiclock >> 4)
+ {
+ /* Between fPCLCK/8 and fPCLCK/16, pick the slower */
+
+ setbits = SPI_CR1_FPCLCKd16; /* 011: fPCLK/16 */
+ actual = priv->spiclock >> 4;
+ }
+ else if (frequency >= priv->spiclock >> 5)
+ {
+ /* Between fPCLCK/16 and fPCLCK/32, pick the slower */
+
+ setbits = SPI_CR1_FPCLCKd32; /* 100: fPCLK/32 */
+ actual = priv->spiclock >> 5;
+ }
+ else if (frequency >= priv->spiclock >> 6)
+ {
+ /* Between fPCLCK/32 and fPCLCK/64, pick the slower */
+
+ setbits = SPI_CR1_FPCLCKd64; /* 101: fPCLK/64 */
+ actual = priv->spiclock >> 6;
+ }
+ else if (frequency >= priv->spiclock >> 7)
+ {
+ /* Between fPCLCK/64 and fPCLCK/128, pick the slower */
+
+ setbits = SPI_CR1_FPCLCKd128; /* 110: fPCLK/128 */
+ actual = priv->spiclock >> 7;
+ }
+ else
+ {
+ /* Less than fPCLK/128. This is as slow as we can go */
+
+ setbits = SPI_CR1_FPCLCKd256; /* 111: fPCLK/256 */
+ actual = priv->spiclock >> 8;
+ }
+
+ spi_modifycr(STM32F7_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE);
+ spi_modifycr(STM32F7_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK);
+ spi_modifycr(STM32F7_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0);
+
+ /* Save the frequency selection so that subsequent reconfigurations will be
+ * faster.
+ */
+
+ spivdbg("Frequency %d->%d\n", frequency, actual);
+
+ priv->frequency = frequency;
+ priv->actual = actual;
+ }
+
+ return priv->actual;
+}
+
+/************************************************************************************
+ * Name: spi_setmode
+ *
+ * Description:
+ * Set the SPI mode. see enum spi_mode_e for mode definitions
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * mode - The SPI mode requested
+ *
+ * Returned Value:
+ * Returns the actual frequency selected
+ *
+ ************************************************************************************/
+
+static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
+{
+ FAR struct stm32f7_spidev_s *priv = (FAR struct stm32f7_spidev_s *)dev;
+ uint16_t setbits;
+ uint16_t clrbits;
+
+ spivdbg("mode=%d\n", mode);
+
+ /* Has the mode changed? */
+
+ if (mode != priv->mode)
+ {
+ /* Yes... Set CR1 appropriately */
+
+ switch (mode)
+ {
+ case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
+ setbits = 0;
+ clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
+ break;
+
+ case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
+ setbits = SPI_CR1_CPHA;
+ clrbits = SPI_CR1_CPOL;
+ break;
+
+ case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
+ setbits = SPI_CR1_CPOL;
+ clrbits = SPI_CR1_CPHA;
+ break;
+
+ case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
+ setbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
+ clrbits = 0;
+ break;
+
+ default:
+ return;
+ }
+
+ spi_modifycr(STM32F7_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE);
+ spi_modifycr(STM32F7_SPI_CR1_OFFSET, priv, setbits, clrbits);
+ spi_modifycr(STM32F7_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0);
+
+ /* Save the mode so that subsequent re-configurations will be faster */
+
+ priv->mode = mode;
+ }
+}
+
+/************************************************************************************
+ * Name: spi_setbits
+ *
+ * Description:
+ * Set the number of bits per word. With STM32F7, this is not restricted to 8 or 16,
+ * but can be any value between 4 and 16.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * nbits - The number of bits requested, negative value means LSB first.
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
+{
+ FAR struct stm32f7_spidev_s *priv = (FAR struct stm32f7_spidev_s *)dev;
+ uint16_t setbits1, setbits2;
+ uint16_t clrbits1, clrbits2;
+ int savbits = nbits;
+
+ spivdbg("nbits=%d\n", nbits);
+
+ /* Has the number of bits changed? */
+
+ if (nbits != priv->nbits)
+ {
+ /* Yes... Set CR1/2 appropriately */
+ /* Negative sign means LSBFIRST, set this in CR1*/
+
+ if (nbits < 0)
+ {
+ setbits1 = SPI_CR1_LSBFIRST;
+ clrbits1 = 0;
+ nbits = -nbits;
+ }
+ else
+ {
+ setbits1 = 0;
+ clrbits1 = SPI_CR1_LSBFIRST;
+ }
+
+ /* Set the number of bits (valid range 4-16) */
+
+ if (nbits < 4 || nbits > 16)
+ {
+ return;
+ }
+
+ clrbits2 = SPI_CR2_DS_MASK;
+ setbits2 = SPI_CR2_DS_VAL(nbits);
+
+ /* If nbits is <=8, then we are in byte mode and FRXTH shall be set
+ * (else, transaction will not complete).
+ */
+
+ if (nbits < 9)
+ {
+ setbits2 |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 1 byte */
+ }
+ else
+ {
+ clrbits2 |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */
+ }
+
+ spi_modifycr(STM32F7_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE);
+ spi_modifycr(STM32F7_SPI_CR1_OFFSET, priv, setbits1, clrbits1);
+ spi_modifycr(STM32F7_SPI_CR2_OFFSET, priv, setbits2, clrbits2);
+ spi_modifycr(STM32F7_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0);
+
+ /* Save the selection so the subsequence re-configurations will be faster */
+
+ priv->nbits = savbits; // nbits has been clobbered... save the signed value.
+ }
+}
+
+/************************************************************************************
+ * Name: spi_send
+ *
+ * Description:
+ * Exchange one word on SPI
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * wd - The word to send. the size of the data is determined by the
+ * number of bits selected for the SPI interface.
+ *
+ * Returned Value:
+ * response
+ *
+ ************************************************************************************/
+
+static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
+{
+ FAR struct stm32f7_spidev_s *priv = (FAR struct stm32f7_spidev_s *)dev;
+ uint32_t regval;
+ uint16_t ret;
+
+ DEBUGASSERT(priv && priv->spibase);
+
+ /* According to the number of bits, access data register as word or byte
+ * This is absolutely required because of packing. With <=8 bit frames,
+ * two bytes are received by a 16-bit read of the data register!
+ */
+
+ if (spi_16bitmode(priv))
+ {
+ spi_writeword(priv, wd);
+ ret = spi_readword(priv);
+ }
+ else
+ {
+ spi_writebyte(priv, (uint8_t)(wd & 0xFF));
+ ret = (uint16_t)spi_readbyte(priv);
+ }
+
+ /* Check and clear any error flags (Reading from the SR clears the error
+ * flags).
+ */
+
+ regval = spi_getreg(priv, STM32F7_SPI_SR_OFFSET);
+
+ if (spi_16bitmode(priv))
+ {
+ spivdbg("Sent: %04x Return: %04x Status: %02x\n", wd, ret, regval);
+ }
+ else
+ {
+ spivdbg("Sent: %02x Return: %02x Status: %02x\n", wd, ret, regval);
+ }
+
+ UNUSED(regval);
+ return ret;
+}
+
+/************************************************************************************
+ * Name: spi_exchange (no DMA). aka spi_exchange_nodma
+ *
+ * Description:
+ * Exchange a block of data on SPI without using DMA
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * txbuffer - A pointer to the buffer of data to be sent
+ * rxbuffer - A pointer to a buffer in which to receive data
+ * nwords - the length of data to be exchaned in units of words.
+ * The wordsize is determined by the number of bits-per-word
+ * selected for the SPI interface. If nbits <= 8, the data is
+ * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+#if !defined(CONFIG_STM32F7_SPI_DMA) || defined(CONFIG_STM32F7_DMACAPABLE)
+#if !defined(CONFIG_STM32F7_SPI_DMA)
+static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
+ FAR void *rxbuffer, size_t nwords)
+#else
+static void spi_exchange_nodma(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
+ FAR void *rxbuffer, size_t nwords)
+#endif
+{
+ FAR struct stm32f7_spidev_s *priv = (FAR struct stm32f7_spidev_s *)dev;
+ DEBUGASSERT(priv && priv->spibase);
+
+ spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
+
+ /* 8- or 16-bit mode? */
+
+ if (spi_16bitmode(priv))
+ {
+ /* 16-bit mode */
+
+ const uint16_t *src = (const uint16_t *)txbuffer;
+ uint16_t *dest = (uint16_t *)rxbuffer;
+ uint16_t word;
+
+ while (nwords-- > 0)
+ {
+ /* Get the next word to write. Is there a source buffer? */
+
+ if (src)
+ {
+ word = *src++;
+ }
+ else
+ {
+ word = 0xffff;
+ }
+
+ /* Exchange one word */
+
+ word = spi_send(dev, word);
+
+ /* Is there a buffer to receive the return value? */
+
+ if (dest)
+ {
+ *dest++ = word;
+ }
+ }
+ }
+ else
+ {
+ /* 8-bit mode */
+
+ const uint8_t *src = (const uint8_t *)txbuffer;
+ uint8_t *dest = (uint8_t *)rxbuffer;
+ uint8_t word;
+
+ while (nwords-- > 0)
+ {
+ /* Get the next word to write. Is there a source buffer? */
+
+ if (src)
+ {
+ word = *src++;
+ }
+ else
+ {
+ word = 0xff;
+ }
+
+ /* Exchange one word */
+
+ word = (uint8_t)spi_send(dev, (uint16_t)word);
+
+ /* Is there a buffer to receive the return value? */
+
+ if (dest)
+ {
+ *dest++ = word;
+ }
+ }
+ }
+}
+#endif /* !CONFIG_STM32F7_SPI_DMA || CONFIG_STM32F7_DMACAPABLE */
+
+/****************************************************************************
+ * Name: spi_exchange (with DMA capability)
+ *
+ * Description:
+ * Exchange a block of data on SPI using DMA
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * txbuffer - A pointer to the buffer of data to be sent
+ * rxbuffer - A pointer to a buffer in which to receive data
+ * nwords - the length of data to be exchanged in units of words.
+ * The wordsize is determined by the number of bits-per-word
+ * selected for the SPI interface. If nbits <= 8, the data is
+ * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F7_SPI_DMA
+static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
+ FAR void *rxbuffer, size_t nwords)
+{
+ FAR struct stm32f7_spidev_s *priv = (FAR struct stm32f7_spidev_s *)dev;
+
+#ifdef CONFIG_STM32F7_DMACAPABLE
+ if ((txbuffer && !stm32f7_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) ||
+ (rxbuffer && !stm32f7_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr)))
+ {
+ /* Unsupported memory region, fall back to non-DMA method. */
+
+ spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords);
+ }
+ else
+#endif
+ {
+ static uint16_t rxdummy = 0xffff;
+ static const uint16_t txdummy = 0xffff;
+
+ spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
+ DEBUGASSERT(priv && priv->spibase);
+
+ /* Setup DMAs */
+
+ spi_dmarxsetup(priv, rxbuffer, &rxdummy, nwords);
+ spi_dmatxsetup(priv, txbuffer, &txdummy, nwords);
+
+ /* Start the DMAs */
+
+ spi_dmarxstart(priv);
+ spi_dmatxstart(priv);
+
+ /* Then wait for each to complete */
+
+ spi_dmarxwait(priv);
+ spi_dmatxwait(priv);
+ }
+}
+#endif /* CONFIG_STM32F7_SPI_DMA */
+
+/****************************************************************************
+ * Name: spi_sndblock
+ *
+ * Description:
+ * Send a block of data on SPI
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * txbuffer - A pointer to the buffer of data to be sent
+ * nwords - the length of data to send from the buffer in number of words.
+ * The wordsize is determined by the number of bits-per-word
+ * selected for the SPI interface. If nbits <= 8, the data is
+ * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+#ifndef CONFIG_SPI_EXCHANGE
+static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer, size_t nwords)
+{
+ spivdbg("txbuffer=%p nwords=%d\n", txbuffer, nwords);
+ return spi_exchange(dev, txbuffer, NULL, nwords);
+}
+#endif
+
+/************************************************************************************
+ * Name: spi_recvblock
+ *
+ * Description:
+ * Receive a block of data from SPI
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * rxbuffer - A pointer to the buffer in which to recieve data
+ * nwords - the length of data that can be received in the buffer in number
+ * of words. The wordsize is determined by the number of bits-per-word
+ * selected for the SPI interface. If nbits <= 8, the data is
+ * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+#ifndef CONFIG_SPI_EXCHANGE
+static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, size_t nwords)
+{
+ spivdbg("rxbuffer=%p nwords=%d\n", rxbuffer, nwords);
+ return spi_exchange(dev, NULL, rxbuffer, nwords);
+}
+#endif
+
+/************************************************************************************
+ * Name: spi_bus_initialize
+ *
+ * Description:
+ * Initialize the selected SPI bus in its default state (Master, 8-bit, mode 0, etc.)
+ *
+ * Input Parameter:
+ * priv - private SPI device structure
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+static void spi_bus_initialize(FAR struct stm32f7_spidev_s *priv)
+{
+ uint16_t setbits;
+ uint16_t clrbits;
+
+ /* Configure CR1 and CR2. Default configuration:
+ * Mode 0: CR1.CPHA=0 and CR1.CPOL=0
+ * Master: CR1.MSTR=1
+ * 8-bit: CR2.DS=7
+ * MSB tranmitted first: CR1.LSBFIRST=0
+ * Replace NSS with SSI & SSI=1: CR1.SSI=1 CR1.SSM=1 (prevents MODF error)
+ * Two lines full duplex: CR1.BIDIMODE=0 CR1.BIDIOIE=(Don't care) and CR1.RXONLY=0
+ */
+
+ clrbits = SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_BR_MASK | SPI_CR1_LSBFIRST |
+ SPI_CR1_RXONLY | SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE;
+ setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM;
+ spi_modifycr(STM32F7_SPI_CR1_OFFSET, priv, setbits, clrbits);
+
+ clrbits = SPI_CR2_DS_MASK;
+ setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */
+ spi_modifycr(STM32F7_SPI_CR2_OFFSET, priv, setbits, clrbits);
+
+ priv->frequency = 0;
+ priv->nbits = 8;
+ priv->mode = SPIDEV_MODE0;
+
+ /* Select a default frequency of approx. 400KHz */
+
+ spi_setfrequency((FAR struct spi_dev_s *)priv, 400000);
+
+ /* CRCPOLY configuration */
+
+ spi_putreg(priv, STM32F7_SPI_CRCPR_OFFSET, 7);
+
+ /* Initialize the SPI semaphore that enforces mutually exclusive access */
+
+ sem_init(&priv->exclsem, 0, 1);
+
+#ifdef CONFIG_STM32F7_SPI_DMA
+ /* Initialize the SPI semaphores that is used to wait for DMA completion */
+
+ sem_init(&priv->rxsem, 0, 0);
+ sem_init(&priv->txsem, 0, 0);
+
+ /* Get DMA channels. NOTE: stm32f7_dmachannel() will always assign the DMA channel.
+ * if the channel is not available, then stm32f7_dmachannel() will block and wait
+ * until the channel becomes available. WARNING: If you have another device sharing
+ * a DMA channel with SPI and the code never releases that channel, then the call
+ * to stm32f7_dmachannel() will hang forever in this function! Don't let your
+ * design do that!
+ */
+
+ priv->rxdma = stm32f7_dmachannel(priv->rxch);
+ priv->txdma = stm32f7_dmachannel(priv->txch);
+ DEBUGASSERT(priv->rxdma && priv->txdma);
+
+ spi_putreg(priv, STM32F7_SPI_CR2_OFFSET, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN);
+#endif
+
+ /* Enable spi */
+
+ spi_modifycr(STM32F7_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0);
+}
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32f7_spibus_initialize
+ *
+ * Description:
+ * Initialize the selected SPI bus
+ *
+ * Input Parameter:
+ * Port number (for hardware that has mutiple SPI interfaces)
+ *
+ * Returned Value:
+ * Valid SPI device structure reference on succcess; a NULL on failure
+ *
+ ************************************************************************************/
+
+FAR struct spi_dev_s *stm32f7_spibus_initialize(int bus)
+{
+ FAR struct stm32f7_spidev_s *priv = NULL;
+
+ irqstate_t flags = enter_critical_section();
+
+#ifdef CONFIG_STM32F7_SPI1
+ if (bus == 1)
+ {
+ /* Select SPI1 */
+
+ priv = &g_spi1dev;
+
+ /* Only configure if the bus is not already configured */
+
+ if ((spi_getreg(priv, STM32F7_SPI_CR1_OFFSET) & SPI_CR1_SPE) == 0)
+ {
+ /* Configure SPI1 pins: SCK, MISO, and MOSI */
+
+ stm32_configgpio(GPIO_SPI1_SCK);
+ stm32_configgpio(GPIO_SPI1_MISO);
+ stm32_configgpio(GPIO_SPI1_MOSI);
+
+ /* Set up default configuration: Master, 8-bit, etc. */
+
+ spi_bus_initialize(priv);
+ }
+ }
+ else
+#endif
+#ifdef CONFIG_STM32F7_SPI2
+ if (bus == 2)
+ {
+ /* Select SPI2 */
+
+ priv = &g_spi2dev;
+
+ /* Only configure if the bus is not already configured */
+
+ if ((spi_getreg(priv, STM32F7_SPI_CR1_OFFSET) & SPI_CR1_SPE) == 0)
+ {
+ /* Configure SPI2 pins: SCK, MISO, and MOSI */
+
+ stm32_configgpio(GPIO_SPI2_SCK);
+ stm32_configgpio(GPIO_SPI2_MISO);
+ stm32_configgpio(GPIO_SPI2_MOSI);
+
+ /* Set up default configuration: Master, 8-bit, etc. */
+
+ spi_bus_initialize(priv);
+ }
+ }
+ else
+#endif
+#ifdef CONFIG_STM32F7_SPI3
+ if (bus == 3)
+ {
+ /* Select SPI3 */
+
+ priv = &g_spi3dev;
+
+ /* Only configure if the bus is not already configured */
+
+ if ((spi_getreg(priv, STM32F7_SPI_CR1_OFFSET) & SPI_CR1_SPE) == 0)
+ {
+ /* Configure SPI3 pins: SCK, MISO, and MOSI */
+
+ stm32_configgpio(GPIO_SPI3_SCK);
+ stm32_configgpio(GPIO_SPI3_MISO);
+ stm32_configgpio(GPIO_SPI3_MOSI);
+
+ /* Set up default configuration: Master, 8-bit, etc. */
+
+ spi_bus_initialize(priv);
+ }
+ }
+ else
+#endif
+#ifdef CONFIG_STM32F7_SPI4
+ if (bus == 4)
+ {
+ /* Select SPI4 */
+
+ priv = &g_spi4dev;
+
+ /* Only configure if the bus is not already configured */
+
+ if ((spi_getreg(priv, STM32F7_SPI_CR1_OFFSET) & SPI_CR1_SPE) == 0)
+ {
+ /* Configure SPI4 pins: SCK, MISO, and MOSI */
+
+ stm32_configgpio(GPIO_SPI4_SCK);
+ stm32_configgpio(GPIO_SPI4_MISO);
+ stm32_configgpio(GPIO_SPI4_MOSI);
+
+ /* Set up default configuration: Master, 8-bit, etc. */
+
+ spi_bus_initialize(priv);
+ }
+ }
+ else
+#endif
+#ifdef CONFIG_STM32F7_SPI5
+ if (bus == 5)
+ {
+ /* Select SPI5 */
+
+ priv = &g_spi5dev;
+
+ /* Only configure if the bus is not already configured */
+
+ if ((spi_getreg(priv, STM32F7_SPI_CR1_OFFSET) & SPI_CR1_SPE) == 0)
+ {
+ /* Configure SPI5 pins: SCK, MISO, and MOSI */
+
+ stm32_configgpio(GPIO_SPI5_SCK);
+ stm32_configgpio(GPIO_SPI5_MISO);
+ stm32_configgpio(GPIO_SPI5_MOSI);
+
+ /* Set up default configuration: Master, 8-bit, etc. */
+
+ spi_bus_initialize(priv);
+ }
+ }
+ else
+#endif
+#ifdef CONFIG_STM32F7_SPI6
+ if (bus == 6)
+ {
+ /* Select SPI6 */
+
+ priv = &g_spi6dev;
+
+ /* Only configure if the bus is not already configured */
+
+ if ((spi_getreg(priv, STM32F7_SPI_CR1_OFFSET) & SPI_CR1_SPE) == 0)
+ {
+ /* Configure SPI6 pins: SCK, MISO, and MOSI */
+
+ stm32_configgpio(GPIO_SPI6_SCK);
+ stm32_configgpio(GPIO_SPI6_MISO);
+ stm32_configgpio(GPIO_SPI6_MOSI);
+
+ /* Set up default configuration: Master, 8-bit, etc. */
+
+ spi_bus_initialize(priv);
+ }
+ }
+ else
+#endif
+ {
+ spidbg("ERROR: Unsupbused SPI bus: %d\n", bus);
+ return NULL;
+ }
+
+ leave_critical_section(flags);
+ return (FAR struct spi_dev_s *)priv;
+}
+
+#endif /* CONFIG_STM32F7_SPI1 || CONFIG_STM32F7_SPI2 || CONFIG_STM32F7_SPI3 || CONFIG_STM32F7_SPI4 || CONFIG_STM32F7_SPI5 || CONFIG_STM32F7_SPI6 */
+
diff --git a/arch/arm/src/stm32f7/stm32_spi.h b/arch/arm/src/stm32f7/stm32_spi.h
index 2d606d2f45..676b6f3096 100644
--- a/arch/arm/src/stm32f7/stm32_spi.h
+++ b/arch/arm/src/stm32f7/stm32_spi.h
@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/stm32f7/stm32_spi.h
*
- * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_STC_STM32F7_STM32_SPI_H
-#define __ARCH_ARM_STC_STM32F7_STM32_SPI_H
+#ifndef __ARCH_ARM_SRC_STM32F7_STM32_SPI_H
+#define __ARCH_ARM_SRC_STM32F7_STM32_SPI_H
/************************************************************************************
* Included Files
@@ -42,13 +42,11 @@
#include
-#include
-
#include "chip.h"
-//#include "chip/stm32_spi.h"
+#include "chip/stm32_spi.h"
/************************************************************************************
- * Public Functions
+ * Pre-processor Definitions
************************************************************************************/
#ifndef __ASSEMBLY__
@@ -62,11 +60,19 @@ extern "C"
#define EXTERN extern
#endif
-struct spi_dev_s; /* Forward reference */
-enum spi_dev_e; /* Forward reference */
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+struct spi_dev_s;
+enum spi_dev_e;
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
/************************************************************************************
- * Name: stm32_spibus_initialize
+ * Name: stm32f7_spibus_initialize
*
* Description:
* Initialize the selected SPI bus
@@ -79,75 +85,75 @@ enum spi_dev_e; /* Forward reference */
*
************************************************************************************/
-FAR struct spi_dev_s *stm32_spibus_initialize(int bus);
+FAR struct spi_dev_s *stm32f7_spibus_initialize(int bus);
/************************************************************************************
- * Name: stm32_spi1/2/...select and stm32_spi1/2/...status
+ * Name: stm32f7_spi1/2/...select and stm32f7_spi1/2/...status
*
* Description:
- * The external functions, stm32_spi1/2/...select, stm32_spi1/2/...status, and
- * stm32_spi1/2/...cmddata must be provided by board-specific logic. These are
+ * The external functions, stm32f7_spi1/2/...select, stm32f7_spi1/2/...status, and
+ * stm32f7_spi1/2/...cmddata must be provided by board-specific logic. These are
* implementations of the select, status, and cmddata methods of the SPI interface
* defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods
- * (including stm32_spibus_initialize()) are provided by common STM32 logic. To use this
+ * (including stm32f7_spibus_initialize()) are provided by common STM32 logic. To use this
* common SPI logic on your board:
*
- * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select
+ * 1. Provide logic in stm32f7_boardinitialize() to configure SPI chip select
* pins.
- * 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() functions in your
+ * 2. Provide stm32f7_spi1/2/...select() and stm32f7_spi1/2/...status() functions in your
* board-specific logic. These functions will perform chip selection and
* status operations using GPIOs in the way your board is configured.
* 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, then
- * provide stm32_spi1/2/...cmddata() functions in your board-specific logic.
+ * provide stm32f7_spi1/2/...cmddata() functions in your board-specific logic.
* These functions will perform cmd/data selection operations using GPIOs in the
* way your board is configured.
- * 4. Add a calls to stm32_spibus_initialize() in your low level application
+ * 4. Add a calls to stm32f7_spibus_initialize() in your low level application
* initialization logic
- * 5. The handle returned by stm32_spibus_initialize() may then be used to bind the
+ * 5. The handle returned by stm32f7_spibus_initialize() may then be used to bind the
* SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
************************************************************************************/
-#ifdef CONFIG_STM32_SPI1
-void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
-uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
-int stm32_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
+#ifdef CONFIG_STM32F7_SPI1
+void stm32f7_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
+uint8_t stm32f7_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
+int stm32f7_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
-#ifdef CONFIG_STM32_SPI2
-void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
-uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
-int stm32_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
+#ifdef CONFIG_STM32F7_SPI2
+void stm32f7_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
+uint8_t stm32f7_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
+int stm32f7_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
-#ifdef CONFIG_STM32_SPI3
-void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
-uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
-int stm32_spi3cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
+#ifdef CONFIG_STM32F7_SPI3
+void stm32f7_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
+uint8_t stm32f7_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
+int stm32f7_spi3cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
-#ifdef CONFIG_STM32_SPI4
-void stm32_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
-uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
-int stm32_spi4cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
+#ifdef CONFIG_STM32F7_SPI4
+void stm32f7_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
+uint8_t stm32f7_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
+int stm32f7_spi4cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
-#ifdef CONFIG_STM32_SPI5
-void stm32_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
-uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
-int stm32_spi5cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
+#ifdef CONFIG_STM32F7_SPI5
+void stm32f7_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
+uint8_t stm32f7_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
+int stm32f7_spi5cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
-#ifdef CONFIG_STM32_SPI6
-void stm32_spi6select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
-uint8_t stm32_spi6status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
-int stm32_spi6cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
+#ifdef CONFIG_STM32F7_SPI6
+void stm32f7_spi6select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
+uint8_t stm32f7_spi6status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
+int stm32f7_spi6cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
/************************************************************************************
- * Name: stm32_spi1/2/...register
+ * Name: stm32f7_spi1/2/...register
*
* Description:
* If the board supports a card detect callback to inform the SPI-based MMC/SD
@@ -167,33 +173,33 @@ int stm32_spi6cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
****************************************************************************/
#ifdef CONFIG_SPI_CALLBACK
-#ifdef CONFIG_STM32_SPI1
-int stm32_spi1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
+#ifdef CONFIG_STM32F7_SPI1
+int stm32f7_spi1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
FAR void *arg);
#endif
-#ifdef CONFIG_STM32_SPI2
-int stm32_spi2register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
+#ifdef CONFIG_STM32F7_SPI2
+int stm32f7_spi2register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
FAR void *arg);
#endif
-#ifdef CONFIG_STM32_SPI3
-int stm32_spi3register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
+#ifdef CONFIG_STM32F7_SPI3
+int stm32f7_spi3register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
FAR void *arg);
#endif
-#ifdef CONFIG_STM32_SPI4
-int stm32_spi4register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
+#ifdef CONFIG_STM32F7_SPI4
+int stm32f7_spi4register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
FAR void *arg);
#endif
-#ifdef CONFIG_STM32_SPI5
-int stm32_spi5register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
+#ifdef CONFIG_STM32F7_SPI5
+int stm32f7_spi5register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
FAR void *arg);
#endif
-#ifdef CONFIG_STM32_SPI6
-int stm32_spi6register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
+#ifdef CONFIG_STM32F7_SPI6
+int stm32f7_spi6register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
FAR void *arg);
#endif
#endif
@@ -204,5 +210,5 @@ int stm32_spi6register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
#endif
#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_STC_STM32F7_STM32_SPI_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_STM32_SPI_H */
diff --git a/configs/stm32f746-ws/include/board.h b/configs/stm32f746-ws/include/board.h
index ab822ce9d2..9600448810 100644
--- a/configs/stm32f746-ws/include/board.h
+++ b/configs/stm32f746-ws/include/board.h
@@ -195,8 +195,13 @@
* -- ----- --------- -----
*/
- #define GPIO_USART6_RX GPIO_USART6_RX_1
- #define GPIO_USART6_TX GPIO_USART6_TX_1
+#define GPIO_USART6_RX GPIO_USART6_RX_1
+#define GPIO_USART6_TX GPIO_USART6_TX_1
+
+#define GPIO_SPI2_SCK GPIO_SPI2_SCK_5
+#define GPIO_SPI2_MISO GPIO_SPI2_MISO_2
+#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_2
+
/************************************************************************************
* Public Data
diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig
index 76656ac848..b13412af70 100644
--- a/configs/stm32f746-ws/nsh/defconfig
+++ b/configs/stm32f746-ws/nsh/defconfig
@@ -173,7 +173,7 @@ CONFIG_STM32F7_HAVE_LTDC=y
# CONFIG_STM32F7_DMA is not set
# CONFIG_STM32F7_I2C is not set
# CONFIG_STM32F7_SAI is not set
-# CONFIG_STM32F7_SPI is not set
+CONFIG_STM32F7_SPI=y
CONFIG_STM32F7_USART=y
# CONFIG_STM32F7_ADC1 is not set
# CONFIG_STM32F7_ADC2 is not set
@@ -206,7 +206,7 @@ CONFIG_STM32F7_USART=y
# CONFIG_STM32F7_SDMMC1 is not set
# CONFIG_STM32F7_SPDIFRX is not set
# CONFIG_STM32F7_SPI1 is not set
-# CONFIG_STM32F7_SPI2 is not set
+CONFIG_STM32F7_SPI2=y
# CONFIG_STM32F7_SPI3 is not set
# CONFIG_STM32F7_SPI4 is not set
# CONFIG_STM32F7_SPI5 is not set
diff --git a/configs/stm32f746-ws/src/stm32_spi.c b/configs/stm32f746-ws/src/stm32_spi.c
index 8544e7d138..afe9ce0f42 100644
--- a/configs/stm32f746-ws/src/stm32_spi.c
+++ b/configs/stm32f746-ws/src/stm32_spi.c
@@ -55,7 +55,7 @@
#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \
defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \
- defined(CONFIG_STM32F7_SPI5)
+ defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6)
/************************************************************************************
* Pre-processor Definitions
@@ -91,7 +91,7 @@ void weak_function stm32_spidev_initialize(void)
}
/****************************************************************************
- * Name: stm32_spi1/2/3/4/5select and stm32_spi1/2/3/4/5status
+ * Name: stm32_spi1-6 select and stm32_spi1-6 status
*
* Description:
* The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be
@@ -175,6 +175,18 @@ uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
}
#endif
+#ifdef CONFIG_STM32F7_SPI6
+void stm32_spi6select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+{
+ spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
+}
+
+uint8_t stm32_spi6status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+ return 0;
+}
+#endif
+
/****************************************************************************
* Name: stm32_spi1cmddata
*
@@ -234,5 +246,12 @@ int stm32_spi5cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
}
#endif
+#ifdef CONFIG_STM32F7_SPI6
+int stm32_spi6cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
+{
+ return -ENODEV;
+}
+#endif
+
#endif /* CONFIG_SPI_CMDDATA */
-#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI5 */
+#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI6 */
--
GitLab
From 7eb65246ee2995c19358b1468c72ac59c25ba089 Mon Sep 17 00:00:00 2001
From: Lok Tep
Date: Tue, 24 May 2016 23:24:22 +0200
Subject: [PATCH 005/400] eclipse
---
.gitignore | 63 ++++++++++++++++++++++++++++--------------------------
1 file changed, 33 insertions(+), 30 deletions(-)
diff --git a/.gitignore b/.gitignore
index 3ec700458d..409232b737 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,30 +1,33 @@
-.depend
-Make.dep
-*.o
-*.a
-*.d
-*.i
-*~
-.swp
-.*.swp
-core
-.gdbinit
-cscope.out
-/.config
-/.config.old
-/.version
-/Make.defs
-/setenv.sh
-/setenv.bat
-/nuttx
-/nuttx.*
-/nuttx-*
-/_SAVED_APPS_config
-/*.map
-/*.elf
-/*.srec
-/*.bin
-/*.ihx
-/*.hex
-/pcode
-/tags
+.depend
+Make.dep
+*.o
+*.a
+*.d
+*.i
+*~
+.swp
+.*.swp
+core
+.gdbinit
+cscope.out
+/.config
+/.config.old
+/.version
+/Make.defs
+/setenv.sh
+/setenv.bat
+/nuttx
+/nuttx.*
+/nuttx-*
+/_SAVED_APPS_config
+/*.map
+/*.elf
+/*.srec
+/*.bin
+/*.ihx
+/*.hex
+/pcode
+/tags
+/.settings/
+/.cproject
+/.project
--
GitLab
From 9ee3fe3f19126d7eb1d2b9fab1481f86e80fc8a8 Mon Sep 17 00:00:00 2001
From: pkolesnikov
Date: Wed, 25 May 2016 14:30:47 +0200
Subject: [PATCH 006/400] clocking for 54mhz
---
arch/arm/src/stm32f7/stm32_i2c.c | 51 +++++++++++++-------------------
1 file changed, 20 insertions(+), 31 deletions(-)
diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c
index e6402f16e8..3b9fc8270b 100644
--- a/arch/arm/src/stm32f7/stm32_i2c.c
+++ b/arch/arm/src/stm32f7/stm32_i2c.c
@@ -104,7 +104,7 @@
/* At least one I2C peripheral must be enabled */
#if defined(CONFIG_STM32F7_I2C1) || defined(CONFIG_STM32F7_I2C2) || defined(CONFIG_STM32F7_I2C3)
-/* This implementation is for the STM32 F1, F2, and F4 only */
+/* This implementation is for the STM32F7 only */
/************************************************************************************
@@ -1078,40 +1078,33 @@ static void stm32f7_i2c_setclock(FAR struct stm32f7_i2c_priv_s *priv, uint32_t f
/* Update timing and control registers */
- /* TODO: speed/timing calcs */
-#warning "check set filters before timing, see RM0316"
+ /* TODO: speed/timing calcs, at the moment 45Mhz = STM32_PCLK1_FREQUENCY, analog filter is on,
+ digital off from STM32F0-F3_AN4235_V1.0.1 */
- /* values from 100khz at 8mhz i2c clock */
-
- /* prescaler */
- /* t_presc= (presc+1)*t_i2cclk */
- /* RM0316 */
-
- if (frequency == 10000)
+ if (frequency == 100000)
{
- presc = 0x01;
- scl_l_period = 0xc7;
- scl_h_period = 0xc3;
- h_time = 0x02;
- s_time = 0x04;
+ presc = 0x06;
+ s_time = 0x02;
+ h_time = 0x00;
+ scl_h_period = 0x1e;
+ scl_l_period = 0x2b;
+
}
- else if (frequency == 100000)
+ else if (frequency == 400000)
{
- /* values from datasheet with clock 8mhz */
-
- presc = 0x01;
- scl_l_period = 0x13;
- scl_h_period = 0x0f;
- h_time = 0x02;
- s_time = 0x04;
+ presc = 0x00;
+ s_time = 0x0A;
+ h_time = 0x00;
+ scl_h_period = 0x1b;
+ scl_l_period = 0x5b;
}
else
{
presc = 0x00;
- scl_l_period = 0x09;
- scl_h_period = 0x03;
- h_time = 0x01;
- s_time = 0x03;
+ s_time = 0x08;
+ h_time = 0x00;
+ scl_h_period = 0x09;
+ scl_l_period = 0x1c;
}
uint32_t timingr =
@@ -1123,10 +1116,6 @@ static void stm32f7_i2c_setclock(FAR struct stm32f7_i2c_priv_s *priv, uint32_t f
stm32f7_i2c_putreg32(priv, STM32F7_I2C_TIMINGR_OFFSET, timingr);
- /* Bit 14 of OAR1 must be configured and kept at 1 */
-
- stm32f7_i2c_putreg(priv, STM32F7_I2C_OAR1_OFFSET, I2C_OAR1_OA1EN);
-
/* Re-enable the peripheral (or not) */
if (pe)
--
GitLab
From c00bb5d4a761a0119abc3c58febd689fadfeee3b Mon Sep 17 00:00:00 2001
From: Lok Tep
Date: Fri, 27 May 2016 00:16:55 +0200
Subject: [PATCH 007/400] i2c
---
arch/arm/src/stm32f7/stm32_i2c.c | 2222 +++++++++++------
configs/stm32f746-ws/nsh/defconfig | 6 +-
.../stm32f746-ws/src/stm32_appinitialize.c | 34 +-
3 files changed, 1473 insertions(+), 789 deletions(-)
diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c
index 3b9fc8270b..e5a9604294 100644
--- a/arch/arm/src/stm32f7/stm32_i2c.c
+++ b/arch/arm/src/stm32f7/stm32_i2c.c
@@ -1,22 +1,24 @@
/************************************************************************************
- * arch/arm/src/stm32f7/stm32f3xx_i2c.c
- * STM32F7 I2C driver - based on STM32L4 I2C Hardware Layer - Device Driver
+ * arch/arm/src/stm32/stm32f3xx_i2c.c
+ * STM32 F3 I2C Hardware Layer - Device Driver
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
* Author: Uros Platise
*
* With extensions and modifications for the F1, F2, and F4 by:
*
- * Copyright (C) 2011-2013, 2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved.
* Author: Gregroy Nutt
*
* And this version for the STM32 F3 by
*
* Author: John Wharington
*
- * Modified for STM32L4 by
+ * Major rewrite of ISR and supporting methods, including support
+ * for NACK and RELOAD by:
*
- * Author: Sebastien Lorquet
+ * Copyright (c) 2016 Doug Vetter. All rights reserved.
+ * Author: Doug Vetter
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -47,29 +49,162 @@
*
************************************************************************************/
-/* Supports:
- * - Master operation, 100 kHz (standard) and 400 kHz (full speed)
+/* ------------------------------------------------------------------------------
+ *
+ * STM32 F3 I2C Driver
+ *
+ * Supports:
+ * - STM32 F30xxx
+ * - Internal Oscillator (HSI) running at 8 Mhz
+ * - Master operation at up to 400Khz (Fast Mode)
* - Multiple instances (shared bus)
* - Interrupt based operation
+ * - RELOAD support
+ *
+ * Unsupported, possible future work:
+ * - More effective error reporting to higher layers
+ * - Fast mode plus (1Mhz)
+ * - Slave operation
+ * - Peripheral clock source selection (SYSCLK vs HSI)
+ * - Support of SYSCLK frequencies other than 8Mhz
+ * - Polled operation (code present but untested)
+ * - SMBus support
+ * - Multi-master support
+ * - IPMI
+ *
+ * Test Environment:
+ *
+ * - STM32F303VC on ST F3 Discovery Board (ST Part STM32F3DISCOVERY)
+ * 256K Flash, 40K SRAM available for all operations, 8K SRAM CCM
+ *
+ * Operational Status:
+ *
+ * All supported features have been tested and found to be operational.
+ *
+ * Although the RELOAD capability has been tested as it was required to
+ * implement the I2C_M_NORESTART flag on F3 hardware, the associated
+ * logic to support the transfer messages with more than 255 byte
+ * payloads has not been tested as the author lacked access to a real
+ * device supporting these types of transfers.
+ *
+ * Performance Benchmarks:
+ *
+ * Time to transfer two messages, each a byte in length, in addition to the
+ * START condition, in interrupt mode:
+ *
+ * DEBUG enabled (development): 80ms
+ * Excessive delay here is caused by printing to the console and
+ * is of no concern.
+ *
+ * DEBUG disabled (production): 120us
+ * Between Messages: 38us
+ * Between Bytes: 7us
+ *
+ * Implementation:
*
- * Structure naming:
* - Device: structure as defined by the nuttx/i2c/i2c.h
+ *
* - Instance: represents each individual access to the I2C driver, obtained by
* the i2c_init(); it extends the Device structure from the nuttx/i2c/i2c.h;
* Instance points to OPS, to common I2C Hardware private data and contains
- * its own private data, as frequency, address, mode of operation (in the future)
+ * its own private data including frequency, address and mode of operation.
+ *
* - Private: Private data of an I2C Hardware
*
- * TODO
- * - Check for all possible deadlocks (as BUSY='1' I2C needs to be reset in HW using the I2C_CR1_SWRST)
- * - SMBus support (hardware layer timings are already supported) and add SMBA gpio pin
- * - Slave support with multiple addresses (on multiple instances):
- * - 2 x 7-bit address or
- * - 1 x 10 bit adresses + 1 x 7 bit address (?)
- * - plus the broadcast address (general call)
- * - Multi-master support
- * - DMA (to get rid of too many CPU wake-ups and interventions)
- * - Be ready for IPMI
+ * High Level Functional Desecription
+ *
+ * This driver works with I2C "messages" (struct i2c_msg_s), which carry a buffer
+ * intended to transfer data to, or store data read from, the I2C bus.
+ *
+ * As the hardware can only transmit or receive one byte at a time the basic job
+ * of the driver (and the ISR specifically) is to process each message in the
+ * order they are stored in the message list, one byte at a time. When
+ * no messages are left the ISR exits and returns the result to the caller.
+ *
+ * The order of the list of I2C messages provided to the driver is important and
+ * dependent upon the hardware in use. A typical I2C transaction between the F3
+ * as an I2C Master and some other IC as a I2C Slave requires two messages that
+ * communicate the:
+ *
+ * 1) Subaddress (register offset on the slave device)
+ * 2) Data sent to or read from the device
+ *
+ * These messages will typically be one byte in length but may be up to 2^31
+ * bytes in length. Incidentally, the maximum length is limited only because
+ * i2c_msg_s.length is a signed int for some odd reason.
+ *
+ * Interrupt mode relies on the following interrupt events:
+ *
+ * TXIS - Transmit interrupt
+ * (data transmitted to bus and acknowedged)
+ * NACKF - Not Acknowledge Received
+ * (data transmitted to bus and NOT acknowledged)
+ * RXNE - Receive interrupt
+ * (data received from bus)
+ * TC - Transfer Complete
+ * (All bytes in message transferred)
+ * TCR - Transfer Complete (Reload)
+ * (Current batch of bytes in message transferred)
+ *
+ * The driver currently supports Single Master mode only. Slave mode is not
+ * supported. Additionally, the driver runs in Software End Mode (AUTOEND
+ * disabled) so the driver is responsible for telling the hardware what to
+ * do at the end of a transfer.
+ *
+ * ------------------------------------------------------------------------------
+ *
+ * Configuration:
+ *
+ * To use this driver, enable the following configuration variable:
+ *
+ * CONFIG_STM32F7_STM32F30XX
+ *
+ * and one or more interfaces:
+ *
+ * CONFIG_STM32F7_I2C1
+ * CONFIG_STM32F7_I2C2
+ * CONFIG_STM32F7_I2C3
+ *
+ * To configure the ISR timeout using fixed values (STM32_I2C_DYNTIMEO=n):
+ *
+ * CONFIG_STM32F7_I2CTIMEOMS (Timeout in milliseconds)
+ * CONFIG_STM32F7_I2CTIMEOSEC (Timeout in seconds)
+ * CONFIG_STM32F7_I2CTIMEOTICKS (Timeout in ticks)
+ *
+ * To configure the ISR timeout using dynamic values (STM32_I2C_DYNTIMEO=y):
+ *
+ * STM32_I2C_DYNTIMEO_USECPERBYTE (Timeout in microseconds per byte)
+ * STM32_I2C_DYNTIMEO_STARTSTOP (Timeout for start/stop in milliseconds)
+ *
+ * Debugging output enabled with:
+ *
+ * CONFIG_DEBUG and CONFIG_DEBUG_I2C
+ *
+ * ISR Debugging output may be enabled with:
+ *
+ * CONFIG_DEBUG_VERBOSE
+ *
+ * ------------------------------------------------------------------------------
+ *
+ * References:
+ *
+ * RM0316:
+ * ST STM32F303xB/C/D/E, etc. Reference Manual
+ * Document ID: DM00043574, Revision 6, August 2015.
+ *
+ * DATASHEET:
+ * ST STM32F303xB/STM32F303xC Datasheet
+ * Document ID: DM00058181, Revision 12, December 2015.
+ *
+ * 303ZYERRATA:
+ * STM32F303xB/C Rev Z and Y device limitations
+ * Document ID: DM00063985, Revision 7, September 2015.
+ *
+ * I2CSPEC:
+ * I2C Bus Specification and User Manual
+ * Document ID: UM10204, Revision 6, April 2014.
+ *
+ * ------------------------------------------------------------------------------
*/
/************************************************************************************
@@ -90,6 +225,7 @@
#include
#include
#include
+#include
#include
#include
@@ -104,13 +240,13 @@
/* At least one I2C peripheral must be enabled */
#if defined(CONFIG_STM32F7_I2C1) || defined(CONFIG_STM32F7_I2C2) || defined(CONFIG_STM32F7_I2C3)
-/* This implementation is for the STM32F7 only */
+/* This implementation is for the STM32 F1, F2, and F4 only */
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
-/* Configuration ********************************************************************/
+
/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. Instead,
* CPU-intensive polling will be used.
*/
@@ -147,18 +283,9 @@
#define I2C_CR1_TXRX \
(I2C_CR1_RXIE | I2C_CR1_TXIE)
#define I2C_CR1_ALLINTS \
- (I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ADDRIE | I2C_CR1_ERRIE)
+ (I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ERRIE)
-#define STATUS_NACK(status) (status & I2C_INT_NACK)
-#define STATUS_ADDR(status) (status & I2C_INT_ADDR)
-#define STATUS_ADDR_TX(status) (status & (I2C_INT_ADDR | I2C_ISR_TXIS))
-#define STATUS_ADD10(status) (0)
-#define STATUS_RXNE(status) (status & I2C_ISR_RXNE)
-#define STATUS_TC(status) (status & I2C_ISR_TC)
-#define STATUS_BUSY(status) (status & I2C_ISR_BUSY)
-
-/* Debug ****************************************************************************/
-/* CONFIG_DEBUG_I2C + CONFIG_DEBUG enables general I2C debug output. */
+/* I2C Debugging */
#ifdef CONFIG_DEBUG_I2C
# define i2cdbg dbg
@@ -168,16 +295,22 @@
# define i2cvdbg(x...)
#endif
-/* I2C event trace logic. NOTE: trace uses the internal, non-standard, low-level
- * debug interface syslog() but does not require that any other debug
- * is enabled.
+/* I2C event tracing
+ *
+ * To enable tracing statements which show the details of the state machine
+ * enable the following configuration variable:
+ *
+ * CONFIG_I2C_TRACE
+ *
+ * Note: This facility uses syslog, which sends output to the console by
+ * default. No other debug configuration variables are required.
*/
#ifndef CONFIG_I2C_TRACE
-# define stm32f7_i2c_tracereset(p)
-# define stm32f7_i2c_tracenew(p,s)
-# define stm32f7_i2c_traceevent(p,e,a)
-# define stm32f7_i2c_tracedump(p)
+# define stm32_i2c_tracereset(p)
+# define stm32_i2c_tracenew(p,s)
+# define stm32_i2c_traceevent(p,e,a)
+# define stm32_i2c_tracedump(p)
#endif
#ifndef CONFIG_I2C_NTRACE
@@ -187,9 +320,10 @@
/************************************************************************************
* Private Types
************************************************************************************/
+
/* Interrupt state */
-enum stm32f7_intstate_e
+enum stm32_intstate_e
{
INTSTATE_IDLE = 0, /* No I2C activity */
INTSTATE_WAITING, /* Waiting for completion of interrupt activity */
@@ -198,35 +332,46 @@ enum stm32f7_intstate_e
/* Trace events */
-enum stm32f7_trace_e
+enum stm32_trace_e
{
- I2CEVENT_NONE = 0, /* No events have occurred with this status */
- I2CEVENT_SENDADDR, /* Start/Master bit set and address sent, param = msgc */
- I2CEVENT_SENDBYTE, /* Send byte, param = dcnt */
- I2CEVENT_ITBUFEN, /* Enable buffer interrupts, param = 0 */
- I2CEVENT_RCVBYTE, /* Read more dta, param = dcnt */
- I2CEVENT_REITBUFEN, /* Re-enable buffer interrupts, param = 0 */
- I2CEVENT_DISITBUFEN, /* Disable buffer interrupts, param = 0 */
- I2CEVENT_BTFNOSTART, /* BTF on last byte with no restart, param = msgc */
- I2CEVENT_BTFRESTART, /* Last byte sent, re-starting, param = msgc */
- I2CEVENT_BTFSTOP, /* Last byte sten, send stop, param = 0 */
- I2CEVENT_ERROR /* Error occurred, param = 0 */
+ I2CEVENT_NONE = 0,
+ I2CEVENT_STATE_ERROR,
+ I2CEVENT_ISR_SHUTDOWN,
+ I2CEVENT_ISR_CALL,
+ I2CEVENT_ISR_EMPTY_CALL,
+ I2CEVENT_MSG_HANDLING,
+ I2CEVENT_POLL_NOT_READY,
+ I2CEVENT_EMPTY_MSG,
+ I2CEVENT_START,
+ I2CEVENT_ADDRESS_ACKED,
+ I2CEVENT_ADDRESS_NACKED,
+ I2CEVENT_NACK,
+ I2CEVENT_READ,
+ I2CEVENT_READ_ERROR,
+ I2CEVENT_WRITE_TO_DR,
+ I2CEVENT_WRITE_STOP,
+ I2CEVENT_WRITE_RESTART,
+ I2CEVENT_WRITE_NO_RESTART,
+ I2CEVENT_WRITE_ERROR,
+ I2CEVENT_WRITE_FLAG_ERROR,
+ I2CEVENT_TC_RESTART,
+ I2CEVENT_TC_NO_RESTART
};
/* Trace data */
-struct stm32f7_trace_s
+struct stm32_trace_s
{
uint32_t status; /* I2C 32-bit SR2|SR1 status */
uint32_t count; /* Interrupt count when status change */
- enum stm32f7_intstate_e event; /* Last event that occurred with this status */
+ enum stm32_intstate_e event; /* Last event that occurred with this status */
uint32_t parm; /* Parameter associated with the event */
- systime_t time; /* First of event or first status */
+ uint32_t time; /* First of event or first status */
};
/* I2C Device hardware configuration */
-struct stm32f7_i2c_config_s
+struct stm32_i2c_config_s
{
uint32_t base; /* I2C base address */
uint32_t clk_bit; /* Clock enable bit */
@@ -242,22 +387,20 @@ struct stm32f7_i2c_config_s
/* I2C Device Private Data */
-struct stm32f7_i2c_priv_s
+struct stm32_i2c_priv_s
{
- const struct i2c_ops_s *ops; /* Standard I2C operations */
- const struct stm32f7_i2c_config_s *config; /* Port configuration */
+ const struct stm32_i2c_config_s *config; /* Port configuration */
int refs; /* Referernce count */
sem_t sem_excl; /* Mutual exclusion semaphore */
#ifndef CONFIG_I2C_POLLED
sem_t sem_isr; /* Interrupt wait semaphore */
#endif
- volatile uint8_t intstate; /* Interrupt handshake (see enum stm32f7_intstate_e) */
+ volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */
uint8_t msgc; /* Message count */
struct i2c_msg_s *msgv; /* Message list */
uint8_t *ptr; /* Current message buffer */
- uint32_t frequency; /* Current I2C frequency */
- int dcnt; /* Current message length */
+ int dcnt; /* Current message bytes remaining to transfer */
uint16_t flags; /* Current message flags */
bool astart; /* START sent */
@@ -265,90 +408,89 @@ struct stm32f7_i2c_priv_s
#ifdef CONFIG_I2C_TRACE
int tndx; /* Trace array index */
- systime_t start_time; /* Time when the trace was started */
+ uint32_t start_time; /* Time when the trace was started */
/* The actual trace data */
- struct stm32f7_trace_s trace[CONFIG_I2C_NTRACE];
+ struct stm32_trace_s trace[CONFIG_I2C_NTRACE];
#endif
uint32_t status; /* End of transfer SR2|SR1 status */
};
+/* I2C Device, Instance */
+
+struct stm32_i2c_inst_s
+{
+ struct i2c_ops_s *ops; /* Standard I2C operations */
+ struct stm32_i2c_priv_s *priv; /* Common driver private data structure */
+
+ uint32_t frequency; /* Frequency used in this instantiation */
+ int address; /* Address used in this instantiation */
+ uint16_t flags; /* Flags used in this instantiation */
+};
+
/************************************************************************************
* Private Function Prototypes
************************************************************************************/
-static inline uint16_t stm32f7_i2c_getreg(FAR struct stm32f7_i2c_priv_s *priv,
+static inline uint16_t stm32_i2c_getreg(FAR struct stm32_i2c_priv_s *priv,
uint8_t offset);
-static inline void stm32f7_i2c_putreg(FAR struct stm32f7_i2c_priv_s *priv, uint8_t offset,
+static inline void stm32_i2c_putreg(FAR struct stm32_i2c_priv_s *priv, uint8_t offset,
uint16_t value);
-static inline void stm32f7_i2c_putreg32(FAR struct stm32f7_i2c_priv_s *priv, uint8_t offset,
+static inline void stm32_i2c_putreg32(FAR struct stm32_i2c_priv_s *priv, uint8_t offset,
uint32_t value);
-static inline void stm32f7_i2c_modifyreg(FAR struct stm32f7_i2c_priv_s *priv,
- uint8_t offset, uint16_t clearbits,
- uint16_t setbits);
-static inline void stm32f7_i2c_modifyreg32(FAR struct stm32f7_i2c_priv_s *priv,
+static inline void stm32_i2c_modifyreg32(FAR struct stm32_i2c_priv_s *priv,
uint8_t offset, uint32_t clearbits,
uint32_t setbits);
-static inline void stm32f7_i2c_sem_wait(FAR struct stm32f7_i2c_priv_s *priv);
+static inline void stm32_i2c_sem_wait(FAR struct i2c_master_s *dev);
#ifdef CONFIG_STM32F7_I2C_DYNTIMEO
-static useconds_t stm32f7_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs);
+static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs);
#endif /* CONFIG_STM32F7_I2C_DYNTIMEO */
-static inline int stm32f7_i2c_sem_waitdone(FAR struct stm32f7_i2c_priv_s *priv);
-static inline void stm32f7_i2c_sem_waitstop(FAR struct stm32f7_i2c_priv_s *priv);
-static inline void stm32f7_i2c_sem_post(FAR struct stm32f7_i2c_priv_s *priv);
-static inline void stm32f7_i2c_sem_init(FAR struct stm32f7_i2c_priv_s *priv);
-static inline void stm32f7_i2c_sem_destroy(FAR struct stm32f7_i2c_priv_s *priv);
+static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv);
+static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv);
+static inline void stm32_i2c_sem_post(FAR struct i2c_master_s *dev);
+static inline void stm32_i2c_sem_init(FAR struct i2c_master_s *dev);
+static inline void stm32_i2c_sem_destroy(FAR struct i2c_master_s *dev);
#ifdef CONFIG_I2C_TRACE
-static void stm32f7_i2c_tracereset(FAR struct stm32f7_i2c_priv_s *priv);
-static void stm32f7_i2c_tracenew(FAR struct stm32f7_i2c_priv_s *priv, uint32_t status);
-static void stm32f7_i2c_traceevent(FAR struct stm32f7_i2c_priv_s *priv,
- enum stm32f7_trace_e event, uint32_t parm);
-static void stm32f7_i2c_tracedump(FAR struct stm32f7_i2c_priv_s *priv);
+static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv);
+static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t status);
+static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv,
+ enum stm32_trace_e event, uint32_t parm);
+static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv);
#endif /* CONFIG_I2C_TRACE */
-static void stm32f7_i2c_setclock(FAR struct stm32f7_i2c_priv_s *priv,
+static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv,
uint32_t frequency);
-static inline void stm32f7_i2c_sendstart(FAR struct stm32f7_i2c_priv_s *priv);
-static inline void stm32f7_i2c_clrstart(FAR struct stm32f7_i2c_priv_s *priv);
-static inline void stm32f7_i2c_sendstop(FAR struct stm32f7_i2c_priv_s *priv);
-static inline uint32_t stm32f7_i2c_getstatus(FAR struct stm32f7_i2c_priv_s *priv);
-static int stm32f7_i2c_isr(struct stm32f7_i2c_priv_s * priv);
+static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv);
+static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv);
+static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv);
+static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv);
#ifndef CONFIG_I2C_POLLED
#ifdef CONFIG_STM32F7_I2C1
-static int stm32f7_i2c1_isr(int irq, void *context);
+static int stm32_i2c1_isr(int irq, void *context);
#endif
#ifdef CONFIG_STM32F7_I2C2
-static int stm32f7_i2c2_isr(int irq, void *context);
+static int stm32_i2c2_isr(int irq, void *context);
#endif
#ifdef CONFIG_STM32F7_I2C3
-static int stm32f7_i2c3_isr(int irq, void *context);
+static int stm32_i2c3_isr(int irq, void *context);
#endif
#endif
-static int stm32f7_i2c_init(FAR struct stm32f7_i2c_priv_s *priv);
-static int stm32f7_i2c_deinit(FAR struct stm32f7_i2c_priv_s *priv);
-static int stm32f7_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
+static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv);
+static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv);
+
+static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
+ int count);
+static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
int count);
-#ifdef CONFIG_I2C_RESET
-static int stm32f7_i2c_reset(FAR struct i2c_master_s *dev);
-#endif
+
/************************************************************************************
* Private Data
************************************************************************************/
-/* Device Structures, Instantiation */
-
-const struct i2c_ops_s stm32f7_i2c_ops =
-{
- .transfer = stm32f7_i2c_transfer
-#ifdef CONFIG_I2C_RESET
- , .reset = stm32f7_i2c_reset
-#endif
-};
-
#ifdef CONFIG_STM32F7_I2C1
-static const struct stm32f7_i2c_config_s stm32f7_i2c1_config =
+static const struct stm32_i2c_config_s stm32_i2c1_config =
{
.base = STM32_I2C1_BASE,
.clk_bit = RCC_APB1ENR_I2C1EN,
@@ -356,16 +498,15 @@ static const struct stm32f7_i2c_config_s stm32f7_i2c1_config =
.scl_pin = GPIO_I2C1_SCL,
.sda_pin = GPIO_I2C1_SDA,
#ifndef CONFIG_I2C_POLLED
- .isr = stm32f7_i2c1_isr,
+ .isr = stm32_i2c1_isr,
.ev_irq = STM32_IRQ_I2C1EV,
.er_irq = STM32_IRQ_I2C1ER
#endif
};
-struct stm32f7_i2c_priv_s stm32f7_i2c1_priv =
+struct stm32_i2c_priv_s stm32_i2c1_priv =
{
- .ops = &stm32f7_i2c_ops,
- .config = &stm32f7_i2c1_config,
+ .config = &stm32_i2c1_config,
.refs = 0,
.intstate = INTSTATE_IDLE,
.msgc = 0,
@@ -378,7 +519,7 @@ struct stm32f7_i2c_priv_s stm32f7_i2c1_priv =
#endif
#ifdef CONFIG_STM32F7_I2C2
-static const struct stm32f7_i2c_config_s stm32f7_i2c2_config =
+static const struct stm32_i2c_config_s stm32_i2c2_config =
{
.base = STM32_I2C2_BASE,
.clk_bit = RCC_APB1ENR_I2C2EN,
@@ -386,16 +527,15 @@ static const struct stm32f7_i2c_config_s stm32f7_i2c2_config =
.scl_pin = GPIO_I2C2_SCL,
.sda_pin = GPIO_I2C2_SDA,
#ifndef CONFIG_I2C_POLLED
- .isr = stm32f7_i2c2_isr,
+ .isr = stm32_i2c2_isr,
.ev_irq = STM32_IRQ_I2C2EV,
.er_irq = STM32_IRQ_I2C2ER
#endif
};
-struct stm32f7_i2c_priv_s stm32f7_i2c2_priv =
+struct stm32_i2c_priv_s stm32_i2c2_priv =
{
- .ops = &stm32f7_i2c_ops,
- .config = &stm32f7_i2c2_config,
+ .config = &stm32_i2c2_config,
.refs = 0,
.intstate = INTSTATE_IDLE,
.msgc = 0,
@@ -408,7 +548,7 @@ struct stm32f7_i2c_priv_s stm32f7_i2c2_priv =
#endif
#ifdef CONFIG_STM32F7_I2C3
-static const struct stm32f7_i2c_config_s stm32f7_i2c3_config =
+static const struct stm32_i2c_config_s stm32_i2c3_config =
{
.base = STM32_I2C3_BASE,
.clk_bit = RCC_APB1ENR_I2C3EN,
@@ -416,16 +556,15 @@ static const struct stm32f7_i2c_config_s stm32f7_i2c3_config =
.scl_pin = GPIO_I2C3_SCL,
.sda_pin = GPIO_I2C3_SDA,
#ifndef CONFIG_I2C_POLLED
- .isr = stm32f7_i2c3_isr,
+ .isr = stm32_i2c3_isr,
.ev_irq = STM32_IRQ_I2C3EV,
.er_irq = STM32_IRQ_I2C3ER
#endif
};
-struct stm32f7_i2c_priv_s stm32f7_i2c3_priv =
+struct stm32_i2c_priv_s stm32_i2c3_priv =
{
- .ops = &stm32f7_i2c_ops,
- .config = &stm32f7_i2c3_config,
+ .config = &stm32_i2c3_config,
.refs = 0,
.intstate = INTSTATE_IDLE,
.msgc = 0,
@@ -437,90 +576,86 @@ struct stm32f7_i2c_priv_s stm32f7_i2c3_priv =
};
#endif
+/* Device Structures, Instantiation */
+
+struct i2c_ops_s stm32_i2c_ops =
+{
+ .transfer = stm32_i2c_transfer
+#ifdef CONFIG_I2C_RESET
+ , .reset = stm32f7_i2c_reset
+#endif
+};
+
/************************************************************************************
* Private Functions
************************************************************************************/
/************************************************************************************
- * Name: stm32f7_i2c_getreg
+ * Name: stm32_i2c_getreg
*
* Description:
* Get a 16-bit register value by offset
*
************************************************************************************/
-static inline uint16_t stm32f7_i2c_getreg(FAR struct stm32f7_i2c_priv_s *priv,
+static inline uint16_t stm32_i2c_getreg(FAR struct stm32_i2c_priv_s *priv,
uint8_t offset)
{
return getreg16(priv->config->base + offset);
}
/************************************************************************************
- * Name: stm32f7_i2c_getreg32
+ * Name: stm32_i2c_getreg32
*
* Description:
* Get a 32-bit register value by offset
*
************************************************************************************/
-static inline uint32_t stm32f7_i2c_getreg32(FAR struct stm32f7_i2c_priv_s *priv,
+static inline uint32_t stm32_i2c_getreg32(FAR struct stm32_i2c_priv_s *priv,
uint8_t offset)
{
return getreg32(priv->config->base + offset);
}
/************************************************************************************
- * Name: stm32f7_i2c_putreg
+ * Name: stm32_i2c_putreg
*
* Description:
* Put a 16-bit register value by offset
*
************************************************************************************/
-static inline void stm32f7_i2c_putreg(FAR struct stm32f7_i2c_priv_s *priv, uint8_t offset,
+static inline void stm32_i2c_putreg(FAR struct stm32_i2c_priv_s *priv, uint8_t offset,
uint16_t value)
{
putreg16(value, priv->config->base + offset);
}
/************************************************************************************
- * Name: stm32f7_i2c_putreg32
+ * Name: stm32_i2c_putreg32
*
* Description:
* Put a 32-bit register value by offset
*
************************************************************************************/
-static inline void stm32f7_i2c_putreg32(FAR struct stm32f7_i2c_priv_s *priv,
+static inline void stm32_i2c_putreg32(FAR struct stm32_i2c_priv_s *priv,
uint8_t offset, uint32_t value)
{
putreg32(value, priv->config->base + offset);
}
-/************************************************************************************
- * Name: stm32f7_i2c_modifyreg
- *
- * Description:
- * Modify a 16-bit register value by offset
- *
- ************************************************************************************/
-
-static inline void stm32f7_i2c_modifyreg(FAR struct stm32f7_i2c_priv_s *priv,
- uint8_t offset, uint16_t clearbits,
- uint16_t setbits)
-{
- modifyreg16(priv->config->base + offset, clearbits, setbits);
-}
/************************************************************************************
- * Name: stm32f7_i2c_modifyreg32
+ * Name: stm32_i2c_modifyreg32
*
* Description:
* Modify a 32-bit register value by offset
*
************************************************************************************/
-static inline void stm32f7_i2c_modifyreg32(FAR struct stm32f7_i2c_priv_s *priv,
+static inline void stm32_i2c_modifyreg32(FAR struct stm32_i2c_priv_s *priv,
uint8_t offset, uint32_t clearbits,
uint32_t setbits)
{
@@ -528,23 +663,23 @@ static inline void stm32f7_i2c_modifyreg32(FAR struct stm32f7_i2c_priv_s *priv,
}
/************************************************************************************
- * Name: stm32f7_i2c_sem_wait
+ * Name: stm32_i2c_sem_wait
*
* Description:
* Take the exclusive access, waiting as necessary
*
************************************************************************************/
-static inline void stm32f7_i2c_sem_wait(FAR struct stm32f7_i2c_priv_s *priv)
+static inline void stm32_i2c_sem_wait(FAR struct i2c_master_s *dev)
{
- while (sem_wait(&priv->sem_excl) != 0)
+ while (sem_wait(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl) != 0)
{
ASSERT(errno == EINTR);
}
}
/************************************************************************************
- * Name: stm32f7_i2c_tousecs
+ * Name: stm32_i2c_tousecs
*
* Description:
* Return a micro-second delay based on the number of bytes left to be processed.
@@ -552,7 +687,7 @@ static inline void stm32f7_i2c_sem_wait(FAR struct stm32f7_i2c_priv_s *priv)
************************************************************************************/
#ifdef CONFIG_STM32F7_I2C_DYNTIMEO
-static useconds_t stm32f7_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs)
+static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs)
{
size_t bytecount = 0;
int i;
@@ -573,7 +708,7 @@ static useconds_t stm32f7_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs)
#endif
/************************************************************************************
- * Name: stm32f7_i2c_enableinterrupts
+ * Name: stm32_i2c_enableinterrupts
*
* Description:
* Enable I2C interrupts
@@ -581,37 +716,26 @@ static useconds_t stm32f7_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs)
************************************************************************************/
#ifndef CONFIG_I2C_POLLED
-static inline void stm32f7_i2c_enableinterrupts(struct stm32f7_i2c_priv_s *priv)
+static inline void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv)
{
- stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, I2C_CR1_TXRX);
+ stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE));
}
#endif
-/************************************************************************************
- * Name: stm32f7_i2c_disableinterrupts
- *
- * Description:
- * Enable I2C interrupts
- *
- ************************************************************************************/
-
-#ifndef CONFIG_I2C_POLLED
-static inline void stm32f7_i2c_disableinterrupts(struct stm32f7_i2c_priv_s *priv)
-{
- stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, I2C_CR1_TXRX, 0);
-}
-#endif
/************************************************************************************
- * Name: stm32f7_i2c_sem_waitdone
+ * Name: stm32_i2c_sem_waitdone
*
* Description:
* Wait for a transfer to complete
*
+ * There are two versions of this function. The first is included when using
+ * interrupts while the second is used if polling (CONFIG_I2C_POLLED=y).
+ *
************************************************************************************/
#ifndef CONFIG_I2C_POLLED
-static inline int stm32f7_i2c_sem_waitdone(FAR struct stm32f7_i2c_priv_s *priv)
+static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
{
struct timespec abstime;
irqstate_t flags;
@@ -621,13 +745,14 @@ static inline int stm32f7_i2c_sem_waitdone(FAR struct stm32f7_i2c_priv_s *priv)
/* Enable I2C interrupts */
- stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0,
+ /* The TXIE and RXIE interrupts are enabled initially in stm32_i2c_process.
+ * The remainder of the interrupts, including error-related, are enabled here.
+ */
+
+ stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0,
(I2C_CR1_ALLINTS & ~I2C_CR1_TXRX));
- /* Signal the interrupt handler that we are waiting. NOTE: Interrupts
- * are currently disabled but will be temporarily re-enabled below when
- * sem_timedwait() sleeps.
- */
+ /* Signal the interrupt handler that we are waiting */
priv->intstate = INTSTATE_WAITING;
do
@@ -645,7 +770,7 @@ static inline int stm32f7_i2c_sem_waitdone(FAR struct stm32f7_i2c_priv_s *priv)
/* Add a value proportional to the number of bytes in the transfer */
#ifdef CONFIG_STM32F7_I2C_DYNTIMEO
- abstime.tv_nsec += 1000 * stm32f7_i2c_tousecs(priv->msgc, priv->msgv);
+ abstime.tv_nsec += 1000 * stm32_i2c_tousecs(priv->msgc, priv->msgv);
if (abstime.tv_nsec >= 1000 * 1000 * 1000)
{
abstime.tv_sec++;
@@ -684,23 +809,23 @@ static inline int stm32f7_i2c_sem_waitdone(FAR struct stm32f7_i2c_priv_s *priv)
/* Disable I2C interrupts */
- stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0);
+ stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0);
leave_critical_section(flags);
return ret;
}
#else
-static inline int stm32f7_i2c_sem_waitdone(FAR struct stm32f7_i2c_priv_s *priv)
+static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
{
- systime_t timeout;
- systime_t start;
- systime_t elapsed;
+ uint32_t timeout;
+ uint32_t start;
+ uint32_t elapsed;
int ret;
/* Get the timeout value */
#ifdef CONFIG_STM32F7_I2C_DYNTIMEO
- timeout = USEC2TICK(stm32f7_i2c_tousecs(priv->msgc, priv->msgv));
+ timeout = USEC2TICK(stm32_i2c_tousecs(priv->msgc, priv->msgv));
#else
timeout = CONFIG_STM32F7_I2CTIMEOTICKS;
#endif
@@ -719,7 +844,7 @@ static inline int stm32f7_i2c_sem_waitdone(FAR struct stm32f7_i2c_priv_s *priv)
* reports that it is done.
*/
- stm32f7_i2c_isr(priv);
+ stm32_i2c_isr(priv);
/* Calculate the elapsed time */
@@ -730,8 +855,8 @@ static inline int stm32f7_i2c_sem_waitdone(FAR struct stm32f7_i2c_priv_s *priv)
while (priv->intstate != INTSTATE_DONE && elapsed < timeout);
- i2cvdbg("intstate: %d elapsed: %ld threshold: %ld status: %08x\n",
- priv->intstate, (long)elapsed, (long)timeout, priv->status);
+ i2cvdbg("intstate: %d elapsed: %d threshold: %d status: 0x%08x\n",
+ priv->intstate, elapsed, timeout, priv->status);
/* Set the interrupt state back to IDLE */
@@ -742,99 +867,100 @@ static inline int stm32f7_i2c_sem_waitdone(FAR struct stm32f7_i2c_priv_s *priv)
#endif
/************************************************************************************
- * Name: stm32f7_i2c_set_7bit_address
+ * Name: stm32_i2c_set_7bit_address
*
* Description:
*
************************************************************************************/
static inline void
-stm32f7_i2c_set_7bit_address(FAR struct stm32f7_i2c_priv_s *priv)
+stm32_i2c_set_7bit_address(FAR struct stm32_i2c_priv_s *priv)
{
- stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK,
+ stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK,
((priv->msgv->addr & 0x7F) << I2C_CR2_SADD7_SHIFT));
}
/************************************************************************************
- * Name: stm32f7_i2c_set_bytes_to_transfer
+ * Name: stm32_i2c_set_bytes_to_transfer
*
* Description:
*
************************************************************************************/
static inline void
-stm32f7_i2c_set_bytes_to_transfer(FAR struct stm32f7_i2c_priv_s *priv,
+stm32_i2c_set_bytes_to_transfer(FAR struct stm32_i2c_priv_s *priv,
uint8_t n_bytes)
{
- stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK,
+ stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK,
(n_bytes << I2C_CR2_NBYTES_SHIFT));
}
/************************************************************************************
- * Name: stm32f7_i2c_set_write_transfer_dir
+ * Name: stm32_i2c_set_write_transfer_dir
*
* Description:
*
************************************************************************************/
static inline void
-stm32f7_i2c_set_write_transfer_dir(FAR struct stm32f7_i2c_priv_s *priv)
+stm32_i2c_set_write_transfer_dir(FAR struct stm32_i2c_priv_s *priv)
{
- stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0);
+ stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0);
}
/************************************************************************************
- * Name: stm32f7_i2c_set_read_transfer_dir
+ * Name: stm32_i2c_set_read_transfer_dir
*
* Description:
*
************************************************************************************/
static inline void
-stm32f7_i2c_set_read_transfer_dir(FAR struct stm32f7_i2c_priv_s *priv)
+stm32_i2c_set_read_transfer_dir(FAR struct stm32_i2c_priv_s *priv)
{
- stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN);
+ stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN);
}
/************************************************************************************
- * Name: stm32f7_i2c_enable_autoend
+ * Name: stm32_i2c_enable_reload
*
* Description:
*
************************************************************************************/
static inline void
-stm32f7_i2c_enable_autoend(FAR struct stm32f7_i2c_priv_s *priv)
+stm32_i2c_enable_reload(FAR struct stm32_i2c_priv_s *priv)
{
- stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_AUTOEND);
+ stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD);
}
/************************************************************************************
- * Name: stm32f7_i2c_disable_autoend
+ * Name: stm32_i2c_disable_reload
*
* Description:
*
************************************************************************************/
static inline void
-stm32f7_i2c_disable_autoend(FAR struct stm32f7_i2c_priv_s *priv)
+stm32_i2c_disable_reload(FAR struct stm32_i2c_priv_s *priv)
{
- stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_AUTOEND, 0);
+ stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0);
}
+
/************************************************************************************
- * Name: stm32f7_i2c_sem_waitstop
+ * Name: stm32_i2c_sem_waitstop
*
* Description:
* Wait for a STOP to complete
*
************************************************************************************/
-static inline void stm32f7_i2c_sem_waitstop(FAR struct stm32f7_i2c_priv_s *priv)
+static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
{
- systime_t start;
- systime_t elapsed;
- systime_t timeout;
+ uint32_t start;
+ uint32_t elapsed;
+ uint32_t timeout;
uint32_t cr;
uint32_t sr;
@@ -846,18 +972,14 @@ static inline void stm32f7_i2c_sem_waitstop(FAR struct stm32f7_i2c_priv_s *priv)
timeout = CONFIG_STM32F7_I2CTIMEOTICKS;
#endif
- /* Wait as stop might still be in progress; but stop might also
- * be set because of a timeout error: "The [STOP] bit is set and
- * cleared by software, cleared by hardware when a Stop condition is
- * detected, set by hardware when a timeout error is detected."
- */
+ /* Wait as stop might still be in progress */
start = clock_systimer();
do
{
/* Check for STOP condition */
- cr = stm32f7_i2c_getreg32(priv, STM32F7_I2C_CR2_OFFSET);
+ cr = stm32_i2c_getreg32(priv, STM32F7_I2C_CR2_OFFSET);
if ((cr & I2C_CR2_STOP) == 0)
{
return;
@@ -865,7 +987,7 @@ static inline void stm32f7_i2c_sem_waitstop(FAR struct stm32f7_i2c_priv_s *priv)
/* Check for timeout error */
- sr = stm32f7_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET);
+ sr = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET);
if ((sr & I2C_INT_TIMEOUT) != 0)
{
return;
@@ -888,52 +1010,52 @@ static inline void stm32f7_i2c_sem_waitstop(FAR struct stm32f7_i2c_priv_s *priv)
}
/************************************************************************************
- * Name: stm32f7_i2c_sem_post
+ * Name: stm32_i2c_sem_post
*
* Description:
* Release the mutual exclusion semaphore
*
************************************************************************************/
-static inline void stm32f7_i2c_sem_post(FAR struct stm32f7_i2c_priv_s *priv)
+static inline void stm32_i2c_sem_post(FAR struct i2c_master_s *dev)
{
- sem_post(&priv->sem_excl);
+ sem_post(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl);
}
/************************************************************************************
- * Name: stm32f7_i2c_sem_init
+ * Name: stm32_i2c_sem_init
*
* Description:
* Initialize semaphores
*
************************************************************************************/
-static inline void stm32f7_i2c_sem_init(FAR struct stm32f7_i2c_priv_s *priv)
+static inline void stm32_i2c_sem_init(FAR struct i2c_master_s *dev)
{
- sem_init(&priv->sem_excl, 0, 1);
+ sem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl, 0, 1);
#ifndef CONFIG_I2C_POLLED
- sem_init(&priv->sem_isr, 0, 0);
+ sem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, 0, 0);
#endif
}
/************************************************************************************
- * Name: stm32f7_i2c_sem_destroy
+ * Name: stm32_i2c_sem_destroy
*
* Description:
* Destroy semaphores.
*
************************************************************************************/
-static inline void stm32f7_i2c_sem_destroy(FAR struct stm32f7_i2c_priv_s *priv)
+static inline void stm32_i2c_sem_destroy(FAR struct i2c_master_s *dev)
{
- sem_destroy(&priv->sem_excl);
+ sem_destroy(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl);
#ifndef CONFIG_I2C_POLLED
- sem_destroy(&priv->sem_isr);
+ sem_destroy(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr);
#endif
}
/************************************************************************************
- * Name: stm32f7_i2c_trace*
+ * Name: stm32_i2c_trace*
*
* Description:
* I2C trace instrumentation
@@ -941,30 +1063,30 @@ static inline void stm32f7_i2c_sem_destroy(FAR struct stm32f7_i2c_priv_s *priv)
************************************************************************************/
#ifdef CONFIG_I2C_TRACE
-static void stm32f7_i2c_traceclear(FAR struct stm32f7_i2c_priv_s *priv)
+static void stm32_i2c_traceclear(FAR struct stm32_i2c_priv_s *priv)
{
- struct stm32f7_trace_s *trace = &priv->trace[priv->tndx];
+ struct stm32_trace_s *trace = &priv->trace[priv->tndx];
- trace->status = 0; /* I2C 32-bit SR2|SR1 status */
+ trace->status = 0; /* I2C 32-bit status */
trace->count = 0; /* Interrupt count when status change */
trace->event = I2CEVENT_NONE; /* Last event that occurred with this status */
trace->parm = 0; /* Parameter associated with the event */
trace->time = 0; /* Time of first status or event */
}
-static void stm32f7_i2c_tracereset(FAR struct stm32f7_i2c_priv_s *priv)
+static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv)
{
/* Reset the trace info for a new data collection */
priv->tndx = 0;
priv->start_time = clock_systimer();
- stm32f7_i2c_traceclear(priv);
+ stm32_i2c_traceclear(priv);
}
-static void stm32f7_i2c_tracenew(FAR struct stm32f7_i2c_priv_s *priv,
+static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv,
uint32_t status)
{
- struct stm32f7_trace_s *trace = &priv->trace[priv->tndx];
+ struct stm32_trace_s *trace = &priv->trace[priv->tndx];
/* Is the current entry uninitialized? Has the status changed? */
@@ -988,7 +1110,7 @@ static void stm32f7_i2c_tracenew(FAR struct stm32f7_i2c_priv_s *priv,
/* Initialize the new trace entry */
- stm32f7_i2c_traceclear(priv);
+ stm32_i2c_traceclear(priv);
trace->status = status;
trace->count = 1;
trace->time = clock_systimer();
@@ -1001,10 +1123,10 @@ static void stm32f7_i2c_tracenew(FAR struct stm32f7_i2c_priv_s *priv,
}
}
-static void stm32f7_i2c_traceevent(FAR struct stm32f7_i2c_priv_s *priv,
- enum stm32f7_trace_e event, uint32_t parm)
+static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv,
+ enum stm32_trace_e event, uint32_t parm)
{
- struct stm32f7_trace_s *trace;
+ struct stm32_trace_s *trace;
if (event != I2CEVENT_NONE)
{
@@ -1024,17 +1146,17 @@ static void stm32f7_i2c_traceevent(FAR struct stm32f7_i2c_priv_s *priv,
}
priv->tndx++;
- stm32f7_i2c_traceclear(priv);
+ stm32_i2c_traceclear(priv);
}
}
-static void stm32f7_i2c_tracedump(FAR struct stm32f7_i2c_priv_s *priv)
+static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv)
{
- struct stm32f7_trace_s *trace;
+ struct stm32_trace_s *trace;
int i;
- syslog(LOG_DEBUG, "Elapsed time: %ld\n",
- (long)(clock_systimer() - priv->start_time));
+ syslog(LOG_DEBUG, "Elapsed time: %d\n",
+ clock_systimer() - priv->start_time);
for (i = 0; i <= priv->tndx; i++)
{
@@ -1048,437 +1170,919 @@ static void stm32f7_i2c_tracedump(FAR struct stm32f7_i2c_priv_s *priv)
#endif /* CONFIG_I2C_TRACE */
/************************************************************************************
- * Name: stm32f7_i2c_setclock
+ * Name: stm32_i2c_setclock
*
* Description:
- * Set the I2C clock
+ *
+ * Sets the I2C bus clock frequency by configuring the I2C_TIMINGR register.
+ *
+ * This function supports bus clock frequencies of:
+ *
+ * 500Khz
+ * 400Khz
+ * 100Khz
+ * 10Khz
+ *
+ * Attempts to set a different frequency will quietly provision the default
+ * of 10Khz.
+ *
+ * The only differences between the various modes of operation (std, fast,
+ * fast+) are the bus clock speed and setup/hold times. Setup/hold times are
+ * specified as a MINIMUM time for the given mode, and naturally std mode
+ * has the longest minimum times. As a result, by provisioning setup/hold
+ * times for std mode they are also compatible with fast/fast+, though some
+ * performance degradation occurs in fast/fast+ as a result of the times
+ * being somewhat longer than strictly required. The values remain as they
+ * are because reliability is favored over performance.
+ *
+ * Clock Selection:
+ *
+ * The I2C peripheral clock can be provided by either SYSCLK or the HSI.
+ *
+ * SYSCLK >------|\ I2CCLK
+ * | |--------->
+ * HSI >------|/
+ *
+ * HSI is the default and is always 8Mhz.
+ *
+ * SYSCLK can, in turn, be derived from the HSI, PLL or HSE.
+ *
+ * HSI >------|\
+ * | | SYSCLK
+ * PLL >------| |--------->
+ * | |
+ * HSE >------|/
+ *
+ * The ability to select the I2C peripheral clock source is not yet supported
+ * so all of this really only works at 8Mhz. The values provided are copied
+ * directly from the 8Mhz example table in RM0316 (See References).
+ *
+ * TODO:
+ *
+ * - Add support for peripheral clock source selection (SYSCLK vs HSI).
+ * - Calculate values for a given SYSCLK frequency.
+ * - Add support for Fast Mode Plus (up to 1Mhz)
+ *
+ * References:
+ *
+ * RM0316: Section: 28.4.9: I2C_TIMINGR register configuration examples
*
************************************************************************************/
-static void stm32f7_i2c_setclock(FAR struct stm32f7_i2c_priv_s *priv, uint32_t frequency)
+static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequency)
{
uint32_t pe;
uint8_t presc;
- uint8_t s_time;
- uint8_t h_time;
+ uint8_t scl_delay;
+ uint8_t sda_delay;
uint8_t scl_h_period;
uint8_t scl_l_period;
- /* Has the I2C bus frequency changed? */
+ /* I2C peripheral must be disabled to update clocking configuration */
- if (frequency != priv->frequency)
+ pe = (stm32_i2c_getreg32(priv, STM32F7_I2C_CR1_OFFSET) & I2C_CR1_PE);
+ if (pe)
{
- /* Disable the selected I2C peripheral to configure TRISE */
-
- pe = (stm32f7_i2c_getreg32(priv, STM32F7_I2C_CR1_OFFSET) & I2C_CR1_PE);
- if (pe)
- {
- stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
- }
-
- /* Update timing and control registers */
-
- /* TODO: speed/timing calcs, at the moment 45Mhz = STM32_PCLK1_FREQUENCY, analog filter is on,
- digital off from STM32F0-F3_AN4235_V1.0.1 */
-
- if (frequency == 100000)
- {
- presc = 0x06;
- s_time = 0x02;
- h_time = 0x00;
- scl_h_period = 0x1e;
- scl_l_period = 0x2b;
-
- }
- else if (frequency == 400000)
- {
- presc = 0x00;
- s_time = 0x0A;
- h_time = 0x00;
- scl_h_period = 0x1b;
- scl_l_period = 0x5b;
- }
- else
- {
- presc = 0x00;
- s_time = 0x08;
- h_time = 0x00;
- scl_h_period = 0x09;
- scl_l_period = 0x1c;
- }
-
- uint32_t timingr =
- (presc << I2C_TIMINGR_PRESC_SHIFT) |
- (s_time << I2C_TIMINGR_SCLDEL_SHIFT) |
- (h_time << I2C_TIMINGR_SDADEL_SHIFT) |
- (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) |
- (scl_l_period << I2C_TIMINGR_SCLL_SHIFT);
-
- stm32f7_i2c_putreg32(priv, STM32F7_I2C_TIMINGR_OFFSET, timingr);
-
- /* Re-enable the peripheral (or not) */
-
- if (pe)
- {
- stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
- }
-
- /* Save the new I2C frequency */
+ stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
+ }
- priv->frequency = frequency;
+ /* TODO: speed/timing calcs, at the moment 45Mhz = STM32_PCLK1_FREQUENCY, analog filter is on,
+ digital off from STM32F0-F3_AN4235_V1.0.1 */
+
+ if (frequency == 100000)
+ {
+ presc = 0x06;
+ scl_delay = 0x02;
+ sda_delay = 0x00;
+ scl_h_period = 0x1e;
+ scl_l_period = 0x2b;
+
+ }
+ else if (frequency == 400000)
+ {
+ presc = 0x00;
+ scl_delay = 0x0A;
+ sda_delay = 0x00;
+ scl_h_period = 0x1b;
+ scl_l_period = 0x5b;
+ }
+ else
+ {
+ presc = 0x00;
+ scl_delay = 0x08;
+ sda_delay = 0x00;
+ scl_h_period = 0x09;
+ scl_l_period = 0x1c;
+ }
+
+ uint32_t timingr =
+ (presc << I2C_TIMINGR_PRESC_SHIFT) |
+ (scl_delay << I2C_TIMINGR_SCLDEL_SHIFT) |
+ (sda_delay << I2C_TIMINGR_SDADEL_SHIFT) |
+ (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) |
+ (scl_l_period << I2C_TIMINGR_SCLL_SHIFT);
+
+ stm32_i2c_putreg32(priv, STM32F7_I2C_TIMINGR_OFFSET, timingr);
+
+ if (pe)
+ {
+ stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
}
}
/************************************************************************************
- * Name: stm32f7_i2c_sendstart
+ * Name: stm32_i2c_sendstart
*
* Description:
- * Send the START conditions/force Master mode
+ * Send the START condition / force Master mode
+ *
+ * A START condition in I2C consists of a single byte that contains both the
+ * 7 bit slave address and a read/write bit (0 = WRITE, 1 = READ). If the
+ * address is recognized by one of the slave devices that slave device will
+ * ACK the byte so that data transfers can begin.
+ *
+ * A RESTART (or repeated START per the I2CSPEC) is simply a START condition
+ * issued in the middle of a transfer (i.e. after the initial START and before
+ * a STOP). A RESTART sends a new address byte and R/W bit to the bus. A
+ * RESTART is optional in most cases but mandatory in the event the transfer
+ * direction is changed.
+ *
+ * Most of the time reading data from an I2C slave requires a WRITE of the
+ * subaddress followed by a READ (and hence a RESTART in between). Writing
+ * to an I2C slave typically requires only WRITE operations and hence no
+ * RESTARTs.
+ *
+ * This function is therefore called both at the beginning of a transfer
+ * (START) and at appropriate times during a transfer (RESTART).
*
************************************************************************************/
-static inline void stm32f7_i2c_sendstart(FAR struct stm32f7_i2c_priv_s *priv)
+static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv)
{
- /* Get run-time data */
+
+ /* Flag the first byte as an address byte */
priv->astart = true;
+
+ /* Set the private "current message" data used in protocol processing.
+ *
+ * ptr: A pointer to the start of the current message buffer. This is
+ * advanced after each byte in the current message is transferred.
+ *
+ * dcnt: A running counter of the bytes in the current message waiting to be
+ * transferred. This is decremented each time a byte is transferred.
+ * The hardware normally accepts a maximum of 255 bytes per transfer
+ * but can support more via the RELOAD mechanism. If dcnt initially
+ * exceeds 255, the RELOAD mechanism will be enabled automatically.
+ *
+ * flags: Used to characterize handling of the current message.
+ *
+ * The default flags value is 0 which specifies:
+ *
+ * - A transfer direction of WRITE (R/W bit = 0)
+ * - RESTARTs between all messages
+ *
+ * The following flags can be used to override this behavior as follows:
+ *
+ * - I2C_M_READ: Sets the transfer direction to READ (R/W bit = 1)
+ * - I2C_M_NORESTART: Prevents a RESTART from being issued prior to the
+ * transfer of the message (where allowed by the protocol).
+ *
+ */
+
priv->ptr = priv->msgv->buffer;
priv->dcnt = priv->msgv->length;
priv->flags = priv->msgv->flags;
- /* Disable ACK on receive by default and generate START */
+ /* Enabling RELOAD allows the transfer of:
+ *
+ * - individual messages with a payload exceeding 255 bytes
+ * - multiple messages back to back without a RESTART in between
+ *
+ * so we enable it if either of those conditions exist and disable
+ * it otherwise.
+ */
+
+ if ((priv->flags & I2C_M_NORESTART) || priv->dcnt > 255) {
+ i2cdbg("RELOAD enabled: dcnt = %i msgc = %i\n",
+ priv->dcnt, priv->msgc);
+ stm32_i2c_enable_reload(priv);
+ } else {
+ i2cdbg("RELOAD disable: dcnt = %i msgc = %i\n",
+ priv->dcnt, priv->msgc);
+ stm32_i2c_disable_reload(priv);
+ }
+
+ /* Set the number of bytes to transfer (I2C_CR2->NBYTES) to the number of
+ * bytes in the current message or 255, whichever is lower so as to not
+ * exceed the hardware maximum allowed.
+ */
- stm32f7_i2c_set_bytes_to_transfer(priv, priv->dcnt);
- stm32f7_i2c_set_7bit_address(priv);
- if (priv->flags & I2C_M_READ)
- {
- stm32f7_i2c_set_read_transfer_dir(priv);
- }
- else
- {
- stm32f7_i2c_set_write_transfer_dir(priv);
- }
+ if (priv->dcnt > 255) {
+ stm32_i2c_set_bytes_to_transfer(priv, 255);
+ } else {
+ stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
+ }
+
+ /* Set the (7 bit) address.
+ * 10 bit addressing is not yet supported.
+ */
+
+ stm32_i2c_set_7bit_address(priv);
- if (priv->msgc == 1)
+ /* The flag of the current message is used to determine the direction of
+ * transfer required for the current message.
+ */
+
+ if (priv->flags & I2C_M_READ)
{
- /* stm32f7_i2c_enable_autoend(priv); */
+ stm32_i2c_set_read_transfer_dir(priv);
}
else
{
- /* stm32f7_i2c_disable_autoend(priv); */
+ stm32_i2c_set_write_transfer_dir(priv);
}
- /* TODO check NACK */
- /* TODO handle NACKR? */
-
- stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_START);
-}
-
-/************************************************************************************
- * Name: stm32f7_i2c_clrstart
- *
- * Description:
- * Clear the STOP, START or PEC condition on certain error recovery steps.
- *
- ************************************************************************************/
-
-static inline void stm32f7_i2c_clrstart(FAR struct stm32f7_i2c_priv_s *priv)
-{
- /* "Note: When the STOP, START or PEC bit is set, the software must
- * not perform any write access to I2C_CR1 before this bit is
- * cleared by hardware. Otherwise there is a risk of setting a
- * second STOP, START or PEC request."
- *
- * "The [STOP] bit is set and cleared by software, cleared by hardware
- * when a Stop condition is detected, set by hardware when a timeout
- * error is detected.
- *
- * "This [START] bit is set and cleared by software and cleared by hardware
- * when start is sent or PE=0." The bit must be cleared by software if the
- * START is never sent.
- *
- * "This [PEC] bit is set and cleared by software, and cleared by hardware
- * when PEC is transferred or by a START or Stop condition or when PE=0."
+ /* Set the I2C_CR2->START bit to 1 to instruct the hardware to send the
+ * START condition using the address and transfer direction data entered.
*/
- /* TODO check PEC (32 bit separate reg) */
+ i2cdbg("Sending START: dcnt=%i msgc=%i flags=0x%04x\n",
+ priv->dcnt, priv->msgc, priv->flags);
- stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET,
- I2C_CR2_START | I2C_CR2_STOP, 0);
+ stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_START);
}
/************************************************************************************
- * Name: stm32f7_i2c_sendstop
+ * Name: stm32_i2c_sendstop
*
* Description:
* Send the STOP conditions
*
+ * A STOP condition can be requested by setting the STOP bit in the I2C_CR2
+ * register. Setting the STOP bit clears the TC flag and the STOP condition is
+ * sent on the bus.
+ *
************************************************************************************/
-static inline void stm32f7_i2c_sendstop(FAR struct stm32f7_i2c_priv_s *priv)
+static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv)
{
- /* TODO check NACK */
+ i2cdbg("Sending STOP\n");
+ stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0);
- stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_STOP);
+ stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_STOP);
}
/************************************************************************************
- * Name: stm32f7_i2c_getstatus
+ * Name: stm32_i2c_getstatus
*
* Description:
* Get 32-bit status (SR1 and SR2 combined)
*
************************************************************************************/
-static inline uint32_t stm32f7_i2c_getstatus(FAR struct stm32f7_i2c_priv_s *priv)
+static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv)
{
return getreg32(priv->config->base + STM32F7_I2C_ISR_OFFSET);
}
/************************************************************************************
- * Name: stm32f7_i2c_isr
+ * Name: stm32_i2c_clearinterrupts
*
* Description:
- * Common logic when a message is started. Just adds the even to the trace buffer
- * if enabled and adjusts the message pointer and count.
+ * Clear all interrupts
*
************************************************************************************/
-static inline void stm32f7_i2c_isr_startmessage(struct stm32f7_i2c_priv_s *priv)
+static inline void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv)
{
- stm32f7_i2c_traceevent(priv, I2CEVENT_SENDADDR, priv->msgc);
-
- /* Increment to next pointer and decrement message count */
-
- priv->msgv++;
- priv->msgc--;
+ stm32_i2c_modifyreg32(priv, STM32F7_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK);
}
/************************************************************************************
- * Name: stm32f7_i2c_clearinterrupts
+ * Name: stm32_i2c_isr
*
* Description:
- * Clear all interrupts
+ * Common interrupt service routine (ISR) that handles I2C protocol logic.
+ * This is instantiated for each configured I2C interface (I2C1, I2C2, I2C3).
*
- ************************************************************************************/
-
-static inline void stm32f7_i2c_clearinterrupts(struct stm32f7_i2c_priv_s *priv)
-{
-#warning "check this clears interrupts?"
- stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK);
-}
-
-/************************************************************************************
- * Name: stm32f7_i2c_isr
+ * This ISR is activated and deactivated by:
*
- * Description:
- * Common Interrupt Service Routine
+ * stm32_i2c_process
+ * and
+ * stm32_i2c_waitdone
+ *
+ * Input Parameters:
+ * priv - The private struct of the I2C driver.
*
************************************************************************************/
-static int stm32f7_i2c_isr(struct stm32f7_i2c_priv_s *priv)
+static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
{
- uint32_t status = stm32f7_i2c_getstatus(priv);
- /* Check for new trace setup */
+ uint32_t status;
- stm32f7_i2c_tracenew(priv, status);
+ /* Get state of the I2C controller */
-#warning "TODO: check clear interrupts after all actions"
+ status = stm32_i2c_getreg32(priv, STM32F7_I2C_ISR_OFFSET);
- if (STATUS_NACK(status))
- {
- /* wait, reset this? */
- }
- else if (priv->astart)
- {
- stm32f7_i2c_isr_startmessage(priv);
- priv->astart = false;
- }
+ i2cvdbg("ENTER: status = 0x%08x\n", status);
- /* Was address sent, continue with either sending or reading data */
+ /* Update private version of the state */
- if ((priv->flags & I2C_M_READ) == 0 && STATUS_ADDR_TX(status))
- {
-#warning "TODO: ADDRCF clear address interrupt flag"
- if (priv->dcnt > 0)
- {
- /* Send a byte */
+ priv->status = status;
- stm32f7_i2c_traceevent(priv, I2CEVENT_SENDBYTE, priv->dcnt);
- stm32f7_i2c_putreg(priv, STM32F7_I2C_TXDR_OFFSET, *priv->ptr++);
- priv->dcnt--;
- }
- }
+ /* If this is a new transmission set up the trace table accordingly */
- else if ((priv->flags & I2C_M_READ) != 0 && STATUS_ADDR(status))
- {
- /* Enable RxNE and TxE buffers in order to receive one or multiple bytes */
+ stm32_i2c_tracenew(priv, status);
+ stm32_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0);
-#warning "TODO: ADDRCF clear address interrupt flag"
+ /* --------------------- Start of I2C protocol handling -------------------- */
-#ifndef CONFIG_I2C_POLLED
- stm32f7_i2c_traceevent(priv, I2CEVENT_ITBUFEN, 0);
- stm32f7_i2c_enableinterrupts(priv);
-#endif
- }
+ /* I2C protocol logic follows. It's organized in an if else chain such that
+ * only one mode of operation is executed every time the ISR is called.
+ *
+ * If you need to add additional states to support new features be sure they
+ * continue the chain (i.e. begin with "else if") and are placed before the
+ * empty call / error states at the end of the chain.
+ */
+
+ /* NACK Handling
+ *
+ * This branch is only triggered when the NACK (Not Acknowledge Received)
+ * interrupt occurs. This interrupt will only fire when the I2C_CR1->NACKIE
+ * bit is 1.
+ *
+ * I2C_ISR->NACKF is set by hardware when a NACK is received after a byte
+ * is transmitted and the slave fails to acknowledge it. This is the
+ * opposite of, and mutually exclusive to, the I2C_ISR->TXIS event.
+ *
+ * In response to the NACK the hardware automatically triggers generation
+ * of a STOP condition, terminating the transfer. The only valid response
+ * to this state is to exit the ISR and report the failure.
+ *
+ * To differentiate an "address NACK" from a NACK that might occur during
+ * the transfer of other bytes the "priv->astart" parameter is
+ * used. This flag is set to TRUE in sendstart() and set to FALSE when
+ * the first TXIS event is received, which would be after the first byte
+ * (the address) is transmitted successfully (acknowledged).
+ */
- /* More bytes to read */
- else if (STATUS_RXNE(status))
+ if (status & I2C_INT_NACK)
{
- /* Read a byte, if dcnt goes < 0, then read dummy bytes to ack ISRs */
- if (priv->dcnt > 0)
+ if (priv->astart == true)
{
- stm32f7_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt);
- /* No interrupts or context switches may occur in the following
- * sequence. Otherwise, additional bytes may be sent by the
- * device.
- */
+ /* NACK received on first (address) byte: address is invalid */
-#ifdef CONFIG_I2C_POLLED
- irqstate_t flags = enter_critical_section();
-#endif
- /* Receive a byte */
+ i2cvdbg("NACK: Address invalid: dcnt=%i msgc=%i status=0x%08x\n",
+ priv->dcnt, priv->msgc, status);
+ stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr);
- *priv->ptr++ = stm32f7_i2c_getreg(priv, STM32F7_I2C_RXDR_OFFSET);
+ }
+ else
+ {
+ /* NACK received on regular byte */
- /* Disable acknowledge when last byte is to be received */
+ i2cvdbg("NACK: NACK received: dcnt=%i msgc=%i status=0x%08x\n",
+ priv->dcnt, priv->msgc, status);
+ stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr);
- priv->dcnt--;
- if (priv->dcnt == 1)
- {
- /* autoend? */
- }
+ }
+
+ /* Set flags to terminate message transmission:
+ *
+ * set message length to -1 to indicate last byte of message sent
+ * set message count to 0 to indicate no more messages to send
+ *
+ * As we fall through the logic in the ISR the message handling block
+ * will be triggered by these flags and signal the ISR to terminate.
+ */
+
+ priv->dcnt = -1;
+ priv->msgc = 0;
-#ifdef CONFIG_I2C_POLLED
- leave_critical_section(flags);
-#endif
- }
}
- /* Do we have more bytes to send, enable/disable buffer interrupts
- * (these ISRs could be replaced by DMAs)
+ /* Transmit Interrupt Status (TXIS) Handler
+ *
+ * This branch is only triggered when the TXIS interrupt occurs. This
+ * interrupt will only fire when the I2C_CR1->TXIE bit is 1.
+ *
+ * This indicates the transmit data register I2C_TXDR has been emptied
+ * following the successful transmission of a byte and slave acknowledgement.
+ * In this state the I2C_TXDR register is ready to accept another byte for
+ * transmission. The TXIS bit will be cleared automatically when the next
+ * byte is written to I2C_TXDR.
+ *
+ * The number of TXIS events during the transfer corresponds to NBYTES.
+ *
+ * The TXIS flag is not set when a NACK is received.
+ *
+ * When RELOAD is disabled (RELOAD=0) and NBYTES data have been transferred:
+ *
+ * - In Automatic End Mode (AUTOEND=1), a STOP is automatically sent.
+ *
+ * Note: Automatic End Mode is not currently supported.
+ *
+ * - In Software End Mode (AUTOEND=0), the TC event occurs and the SCL
+ * line is stretched low in order to allow software actions (STOP,
+ * RESTART).
+ *
+ * When RELOAD is enabled (RELOAD=1) and NBYTES bytes have been transferred
+ * a TCR event occurs instead and that handler simply updates NBYTES which
+ * causes TXIS events to continue. The process repeats until all bytes in
+ * the message have been transferred.
*/
-#ifndef CONFIG_I2C_POLLED
- if (priv->dcnt > 0)
- {
- stm32f7_i2c_traceevent(priv, I2CEVENT_REITBUFEN, 0);
- stm32f7_i2c_enableinterrupts(priv);
- }
- else if ((priv->dcnt == 0) && (priv->msgc == 0))
+ else if ((priv->flags & (I2C_M_READ)) == 0 && (status & (I2C_ISR_TXIS)) != 0)
{
- stm32f7_i2c_traceevent(priv, I2CEVENT_DISITBUFEN, 0);
- stm32f7_i2c_disableinterrupts(priv);
- }
-#endif
- /* Was last byte received or sent? Hmmm... the F2 and F4 seems to differ from
- * the F1 in that BTF is not set after data is received (only RXNE).
- */
+ /* TXIS interrupt occurred, address valid, ready to transmit */
- if (priv->dcnt <= 0 && STATUS_TC(status))
- {
- /* ??? */
+ stm32_i2c_traceevent(priv, I2CEVENT_WRITE, 0);
+ i2cvdbg("TXIS: ENTER dcnt = %i msgc = %i status 0x%08x\n",
+ priv->dcnt, priv->msgc, status);
- /* Do we need to terminate or restart after this byte?
- * If there are more messages to send, then we may:
- *
- * - continue with repeated start
- * - or just continue sending writeable part
- * - or we close down by sending the stop bit
+ /* The first event after the address byte is sent will be either TXIS
+ * or NACKF so it's safe to set the astart flag to false on
+ * the first TXIS event to indicate that it is no longer necessary to
+ * check for address validity.
*/
- if (priv->msgc > 0)
+ if (priv->astart == true)
{
- if (priv->msgv->flags & I2C_M_NORESTART)
- {
- stm32f7_i2c_traceevent(priv, I2CEVENT_BTFNOSTART, priv->msgc);
- priv->ptr = priv->msgv->buffer;
- priv->dcnt = priv->msgv->length;
- priv->flags = priv->msgv->flags;
- priv->msgv++;
- priv->msgc--;
+ i2cvdbg("TXIS: Address Valid\n");
+ stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, priv->msgv->addr);
+ priv->astart = false;
+ }
- /* Restart this ISR! */
+ /* If one or more bytes in the current message are ready to transmit */
+
+ if (priv->dcnt > 0)
+ {
+
+ /* Prepare to transmit the current byte */
+
+ stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt);
+ i2cvdbg("TXIS: Write Data 0x%02x\n", *priv->ptr);
+
+ /* Decrement byte counter */
+
+ priv->dcnt--;
+
+ /* If we are about to transmit the last byte in the current message */
+
+ if (priv->dcnt == 0) {
+
+ /* If this is also the last message to send, disable RELOAD so
+ * TC fires next and issues STOP condition. If we don't do this
+ * TCR will fire next, and since there are no bytes to send we
+ * can't write NBYTES to clear TCR so it will fire forever.
+ */
+
+ if ((priv->msgc - 1) == 0) {
+
+ stm32_i2c_disable_reload(priv);
+
+ }
+ }
+
+ /* Transmit current byte */
+
+ stm32_i2c_putreg(priv, STM32F7_I2C_TXDR_OFFSET, *priv->ptr);
+
+ /* Advance to next byte */
+
+ priv->ptr++;
-#ifndef CONFIG_I2C_POLLED
- stm32f7_i2c_enableinterrupts(priv);
-#endif
- }
- else
- {
- stm32f7_i2c_traceevent(priv, I2CEVENT_BTFRESTART, priv->msgc);
- /* ??? */
- stm32f7_i2c_sendstart(priv);
- }
}
- else if (priv->msgv)
+ else
{
- stm32f7_i2c_traceevent(priv, I2CEVENT_BTFSTOP, 0);
+ /* Unsupported state */
- stm32f7_i2c_sendstop(priv);
+ i2cdbg("TXIS: UNSUPPORTED STATE DETECTED, dcnt=%i, status 0x%08x\n",
+ priv->dcnt, status);
+ stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0);
- /* Is there a thread waiting for this event (there should be) */
+ }
-#ifndef CONFIG_I2C_POLLED
- if (priv->intstate == INTSTATE_WAITING)
- {
- /* Yes.. inform the thread that the transfer is complete
- * and wake it up.
- */
+ i2cvdbg("TXIS: EXIT dcnt = %i msgc = %i status 0x%08x\n",
+ priv->dcnt, priv->msgc, status);
- sem_post(&priv->sem_isr);
- priv->intstate = INTSTATE_DONE;
- }
-#else
- priv->intstate = INTSTATE_DONE;
+ }
+
+
+ /* Receive Buffer Not Empty (RXNE) State Handler
+ *
+ * This branch is only triggered when the RXNE interrupt occurs. This
+ * interrupt will only fire when the I2C_CR1->RXIE bit is 1.
+ *
+ * This indicates data has been received from the bus and is waiting to
+ * be read from the I2C_RXDR register. When I2C_RXDR is read this bit
+ * is automatically cleared and then an ACK or NACK is sent depending on
+ * whether we have more bytes to receive.
+ *
+ * When RELOAD is disabled and bytes remain to be transferred an acknowledge
+ * is automatically sent on the bus and the RXNE events continue until the
+ * last byte is received.
+ *
+ * When RELOAD is disabled (RELOAD=0) and BYTES have been transferred:
+ *
+ * - In Automatic End Mode (AUTOEND=1), a NACK and a STOP are automatically
+ * sent after the last received byte.
+ *
+ * Note: Automatic End Mode is not currently supported.
+ *
+ * - In Software End Mode (AUTOEND=0), a NACK is automatically sent after
+ * the last received byte, the TC event occurs and the SCL line is
+ * stretched low in order to allow software actions (STOP, RESTART).
+ *
+ * When RELOAD is enabled (RELOAD=1) and NBYTES bytes have been transferred
+ * a TCR event occurs and that handler simply updates NBYTES which causes
+ * RXNE events to continue until all bytes have been transferred.
+ */
+
+ else if ((priv->flags & (I2C_M_READ)) != 0 && (status & I2C_ISR_RXNE) != 0)
+ {
+ /* When read flag is set and the receive buffer is not empty
+ * (RXNE is set) then the driver can read from the data register.
+ */
+
+ stm32_i2c_traceevent(priv, I2CEVENT_READ, 0);
+ i2cvdbg("RXNE: ENTER dcnt = %i msgc = %i status 0x%08x\n",
+ priv->dcnt, priv->msgc, status);
+
+ /* If more bytes in the current message */
+
+ if (priv->dcnt > 0)
+ {
+
+ stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt);
+
+ /* No interrupts or context switches may occur in the following
+ * sequence. Otherwise, additional bytes may be received.
+ */
+
+#ifdef CONFIG_I2C_POLLED
+ irqstate_t state = enter_critical_section();
+#endif
+ /* Receive a byte */
+
+ *priv->ptr = stm32_i2c_getreg(priv, STM32F7_I2C_RXDR_OFFSET);
+
+ i2cvdbg("RXNE: Read Data 0x%02x\n", *priv->ptr);
+
+ /* Advance buffer to the next byte in the message */
+
+ priv->ptr++;
+
+ /* Signal byte received */
+
+ priv->dcnt--;
+
+#ifdef CONFIG_I2C_POLLED
+ leave_critical_section(state);
#endif
- /* Mark that we have stopped with this transaction */
+ }
+ else
+ {
+
+ /* Unsupported state */
+
+ stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0);
+ status = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET);
+ i2cdbg("RXNE: UNSUPPORTED STATE DETECTED, dcnt=%i, status 0x%08x\n",
+ priv->dcnt, status);
+
+ /* Set signals that will terminate ISR and wake waiting thread */
+
+ priv->dcnt = -1;
+ priv->msgc = 0;
- priv->msgv = NULL;
}
+
+ i2cvdbg("RXNE: EXIT dcnt = %i msgc = %i status 0x%08x\n",
+ priv->dcnt, priv->msgc, status);
}
- /* Check for errors, in which case, stop the transfer and return
- * Note that in master reception mode AF becomes set on last byte
- * since ACK is not returned. We should ignore this error.
+ /* Transfer Complete (TC) State Handler
+ *
+ * This branch is only triggered when the TC interrupt occurs. This
+ * interrupt will only fire when:
+ *
+ * I2C_CR1->TCIE = 1 (Transfer Complete Interrupts Enabled)
+ * I2C_CR2->RELOAD = 0 (Reload Mode Disabled)
+ * I2C_CR2->AUTOEND = 0 (Autoend Mode Disabled, i.e. Software End Mode)
+ *
+ * This event indicates that the number of bytes initially defined
+ * in NBYTES, meaning, the number of bytes in the current message (priv->dcnt)
+ * has been successfully transmitted or received.
+ *
+ * When the TC interrupt occurs we have two choices to clear it and move
+ * on, regardless of the transfer direction:
+ *
+ * - if more messages follow, perform a repeated START if required
+ * and then fall through to transmit or receive the next message.
+ *
+ * - if no messages follow, perform a STOP and set flags needed to
+ * exit the ISR.
+ *
+ * The fact that the hardware must either RESTART or STOP when a TC
+ * event occurs explains why, when messages must be sent back to back
+ * (i.e. without a restart by specifying the I2C_M_NORESTART flag),
+ * RELOAD mode must be enabled and TCR event(s) must be generated
+ * instead. See the TCR handler for more.
*/
- if ((status & I2C_ISR_ERRORMASK) != 0)
+ else if ((status & I2C_ISR_TC) != 0)
{
- stm32f7_i2c_traceevent(priv, I2CEVENT_ERROR, 0);
+ i2cvdbg("TC: ENTER dcnt = %i msgc = %i status 0x%08x\n",
+ priv->dcnt, priv->msgc, status);
- /* Clear interrupt flags */
+ /* Prior message has been sent successfully */
- stm32f7_i2c_clearinterrupts(priv);
+ priv->msgc--;
- /* Is there a thread waiting for this event (there should be) */
+ /* if additional messages remain to be transmitted / received */
+
+ if (priv->msgc > 0) {
+
+ i2cvdbg("TC: RESTART: dcnt=%i, msgc=%i\n",
+ priv->dcnt, priv->msgc);
+ stm32_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc);
+
+ /* Issue a START condition.
+ *
+ * Note that the first thing sendstart does is update the
+ * private structure "current message" data (ptr, dcnt, flags)
+ * so they all reflect the next message in the list so we
+ * update msgv before we get there.
+ */
+
+ /* Advance to the next message in the list */
+
+ priv->msgv++;
+
+ stm32_i2c_sendstart(priv);
+
+ } else {
+
+ /* Issue a STOP conditions.
+ *
+ * No additional messages to transmit / receive, so the
+ * transfer is indeed complete. Nothing else to do but
+ * issue a STOP and exit.
+ */
+
+ i2cvdbg("TC: STOP: dcnt=%i msgc=%i\n",
+ priv->dcnt, priv->msgc);
+ stm32_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt);
+
+ stm32_i2c_sendstop(priv);
+
+ /* Set signals that will terminate ISR and wake waiting thread */
+
+ priv->dcnt = -1;
+ priv->msgc = 0;
+
+ }
+
+ i2cvdbg("TC: EXIT dcnt = %i msgc = %i status 0x%08x\n",
+ priv->dcnt, priv->msgc, status);
+
+ }
+
+
+ /* Transfer Complete (Reload) State Handler
+ *
+ * This branch is only triggered when the TCR interrupt occurs. This
+ * interrupt will only fire when:
+ *
+ * I2C_CR1->TCIE = 1 (Transfer Complete Interrupts Enabled)
+ * I2C_CR2->RELOAD = 1 (Reload Mode Active)
+ * I2C_CR2->AUTOEND = 0 (Autoend Mode Disabled, i.e. Software End Mode)
+ *
+ * This is similar to the TC event except that TCR assumes that additional
+ * bytes are available to transfer. So despite what its name might imply
+ * the transfer really isn't complete.
+ *
+ * There are two reasons RELOAD would be enabled:
+ *
+ * 1) We're trying to send a message with a payload greater than 255 bytes.
+ * 2) We're trying to send messages back to back, regardless of their
+ * payload size, to avoid a RESTART (i.e. I2C_M_NORESTART flag is set).
+ *
+ * These conditions may be true simultaneously, as would be the case if
+ * we're sending multiple messages with payloads > 255 bytes. So we only
+ * advance to the next message if we arrive here and dcnt is 0, meaning,
+ * we're finished with the last message and ready to move to the next.
+ *
+ * This logic supports the transfer of bytes limited only by the size of
+ * the i2c_msg_s length variable. The SCL line will be stretched low
+ * until NBYTES is written with a non-zero value, allowing the transfer
+ * to continue.
+ *
+ * TODO: RESTARTs are required by the I2CSPEC if the next message transfer
+ * direction changes. Right now the NORESTART flag overrides this behavior.
+ * May have to introduce logic to issue sendstart, assuming it's legal
+ * with the hardware in the TCR state.
+ */
+
+ else if ((status & I2C_ISR_TCR) != 0)
+ {
+ i2cvdbg("TCR: ENTER dcnt = %i msgc = %i status 0x%08x\n",
+ priv->dcnt, priv->msgc, status);
+
+ /* If no more bytes in the current message to transfer */
+
+ if (priv->dcnt == 0) {
+
+ /* Prior message has been sent successfully */
+
+ priv->msgc--;
+
+ /* Advance to the next message in the list */
+
+ priv->msgv++;
+
+ /* Update current message data */
+
+ priv->ptr = priv->msgv->buffer;
+ priv->dcnt = priv->msgv->length;
+ priv->flags = priv->msgv->flags;
+
+ /* if this is the last message, disable reload so the
+ * TC event fires next time */
+
+ if (priv->msgc == 0) {
+ i2cvdbg("TCR: DISABLE RELOAD: dcnt = %i msgc = %i\n",
+ priv->dcnt, priv->msgc);
+
+ stm32_i2c_disable_reload(priv);
+ }
+
+ /* Update NBYTES with length of current message */
+
+ i2cvdbg("TCR: NEXT MSG dcnt = %i msgc = %i\n",
+ priv->dcnt, priv->msgc);
+
+ stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
+
+ } else {
+
+ /* More bytes in the current (greater than 255 byte payload
+ * length) message, so set NBYTES according to the bytes
+ * remaining in the message, up to a maximum each cycle of 255.
+ */
+
+ if (priv->dcnt > 255) {
+
+ i2cvdbg("TCR: ENABLE RELOAD: NBYTES = 255 dcnt = %i msgc = %i\n",
+ priv->dcnt, priv->msgc);
+
+ /* More than 255 bytes to transfer so the RELOAD bit is
+ * set in order to generate a TCR event rather than a TC
+ * event when 255 bytes are successfully transferred.
+ * This forces us to return here to update NBYTES and
+ * continue until NBYTES is set to less than 255 bytes,
+ * at which point RELOAD will be disabled and a TC
+ * event will (eventually) follow to officially terminate
+ * the transfer.
+ */
+
+ stm32_i2c_enable_reload(priv);
+
+ stm32_i2c_set_bytes_to_transfer(priv, 255);
+
+ } else {
+
+ /* Less than 255 bytes left to transfer, which means we'll
+ * complete the transfer of all bytes in the current message
+ * the next time around.
+ *
+ * This means we need to disable the RELOAD functionality so
+ * we receive a TC event next time which will allow us to
+ * either RESTART and continue sending the contents of the
+ * next message or send a STOP condition and exit the ISR.
+ */
+
+ i2cvdbg("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n",
+ priv->dcnt, priv->msgc);
+
+ stm32_i2c_disable_reload(priv);
+
+ stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
+
+ }
+
+ i2cvdbg("TCR: EXIT dcnt = %i msgc = %i status 0x%08x\n",
+ priv->dcnt, priv->msgc, status);
+ }
+ }
+
+ /* Empty call handler
+ *
+ * Case to handle an empty call to the ISR where it has nothing to
+ * do and should exit immediately.
+ */
+
+ else if (priv->dcnt == -1 && priv->msgc == 0)
+ {
+ status = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET);
+ i2cdbg("EMPTY CALL: Stopping ISR: status 0x%08x\n", status);
+ stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0);
+ }
+
+ /* Error handler
+ *
+ * We get to this branch only if we can't handle the current state.
+ *
+ * This should not happen in interrupt based operation.
+ *
+ * This will happen during polled operation when the device is not
+ * in one of the supported states when polled.
+ */
+
+ else
+ {
+#ifdef CONFIG_I2C_POLLED
+ stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0);
+#else
+ /* Read rest of the state */
+
+ status = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET);
+
+ i2cdbg("INVALID STATE DETECTED, status 0x%08x\n", status);
+
+ /* set condition to terminate ISR and wake waiting thread */
+
+ priv->dcnt = -1;
+ priv->msgc = 0;
+ stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0);
+#endif
+ }
+
+ /* --------------------- End of I2C protocol handling -------------------- */
+
+ /* Message Handling
+ *
+ * Transmission of the whole message chain has been completed. We have to
+ * terminate the ISR and wake up stm32_i2c_process() that is waiting for
+ * the ISR cycle to handle the sending/receiving of the messages.
+ */
+
+ if (priv->dcnt == -1 && priv->msgc == 0)
+ {
+ i2cvdbg("MSG: Shutting down I2C ISR\n");
+
+ stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0);
+
+ /* clear pointer to message content to reflect we are done
+ * with the current transaction */
+
+ priv->msgv = NULL;
+
+#ifdef CONFIG_I2C_POLLED
+ priv->intstate = INTSTATE_DONE;
+#else
+
+ status = stm32_i2c_getreg32(priv, STM32F7_I2C_ISR_OFFSET);
+
+ /* Update private state to capture NACK which is used in combination
+ * with the astart flag to report the type of NACK received (address
+ * vs data) to the upper layers once we exit the ISR.
+ *
+ * Note: We do this prior to clearing interrupts because the NACKF
+ * flag will naturally be cleared by that process. */
+
+ priv->status = status;
+
+ /* Clear all interrupts */
+
+ stm32_i2c_modifyreg32(priv, STM32F7_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK);
+
+ /* If a thread is waiting then inform it transfer is complete */
-#ifndef CONFIG_I2C_POLLED
if (priv->intstate == INTSTATE_WAITING)
{
- /* Yes.. inform the thread that the transfer is complete
- * and wake it up.
- */
-
sem_post(&priv->sem_isr);
priv->intstate = INTSTATE_DONE;
}
-#else
- priv->intstate = INTSTATE_DONE;
#endif
+
}
- priv->status = status;
+ status = stm32_i2c_getreg32(priv, STM32F7_I2C_ISR_OFFSET);
+ i2cvdbg("EXIT: status = 0x%08x\n", status);
+
return OK;
}
/************************************************************************************
- * Name: stm32f7_i2c1_isr
+ * Name: stm32_i2c1_isr
*
* Description:
* I2C1 interrupt service routine
@@ -1487,14 +2091,14 @@ static int stm32f7_i2c_isr(struct stm32f7_i2c_priv_s *priv)
#ifndef CONFIG_I2C_POLLED
#ifdef CONFIG_STM32F7_I2C1
-static int stm32f7_i2c1_isr(int irq, void *context)
+static int stm32_i2c1_isr(int irq, void *context)
{
- return stm32f7_i2c_isr(&stm32f7_i2c1_priv);
+ return stm32_i2c_isr(&stm32_i2c1_priv);
}
#endif
/************************************************************************************
- * Name: stm32f7_i2c2_isr
+ * Name: stm32_i2c2_isr
*
* Description:
* I2C2 interrupt service routine
@@ -1502,14 +2106,14 @@ static int stm32f7_i2c1_isr(int irq, void *context)
************************************************************************************/
#ifdef CONFIG_STM32F7_I2C2
-static int stm32f7_i2c2_isr(int irq, void *context)
+static int stm32_i2c2_isr(int irq, void *context)
{
- return stm32f7_i2c_isr(&stm32f7_i2c2_priv);
+ return stm32_i2c_isr(&stm32_i2c2_priv);
}
#endif
/************************************************************************************
- * Name: stm32f7_i2c3_isr
+ * Name: stm32_i2c3_isr
*
* Description:
* I2C2 interrupt service routine
@@ -1517,9 +2121,9 @@ static int stm32f7_i2c2_isr(int irq, void *context)
************************************************************************************/
#ifdef CONFIG_STM32F7_I2C3
-static int stm32f7_i2c3_isr(int irq, void *context)
+static int stm32_i2c3_isr(int irq, void *context)
{
- return stm32f7_i2c_isr(&stm32f7_i2c3_priv);
+ return stm32_i2c_isr(&stm32_i2c3_priv);
}
#endif
#endif
@@ -1529,14 +2133,14 @@ static int stm32f7_i2c3_isr(int irq, void *context)
************************************************************************************/
/************************************************************************************
- * Name: stm32f7_i2c_init
+ * Name: stm32_i2c_init
*
* Description:
* Setup the I2C hardware, ready for operation with defaults
*
************************************************************************************/
-static int stm32f7_i2c_init(FAR struct stm32f7_i2c_priv_s *priv)
+static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
{
/* Power-up and configure GPIOs */
@@ -1559,56 +2163,53 @@ static int stm32f7_i2c_init(FAR struct stm32f7_i2c_priv_s *priv)
return ERROR;
}
- /* Attach ISRs */
-
#ifndef CONFIG_I2C_POLLED
+
+ /* Attach error and event interrupts to the ISRs */
+
irq_attach(priv->config->ev_irq, priv->config->isr);
irq_attach(priv->config->er_irq, priv->config->isr);
up_enable_irq(priv->config->ev_irq);
up_enable_irq(priv->config->er_irq);
#endif
- /* Set peripheral frequency, where it must be at least 2 MHz for 100 kHz
- * or 4 MHz for 400 kHz. This also disables all I2C interrupts.
+ /* TODO:
+ * - Provide means to set peripheral clock source via RCC_CFGR3_I2CxSW
+ * - Set to HSI by default, make Kconfig option
*/
- /* Force a frequency update */
-
- priv->frequency = 0;
-
- /* TODO: f303 i2c clock source RCC_CFGR3 */
- /* RCC_CFGR3_I2C1SW (default is HSI clock) */
+ stm32_i2c_setclock(priv, 100000);
- stm32f7_i2c_setclock(priv, 100000);
+ /* Enable I2C peripheral */
- /* Enable I2C */
+ stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
- stm32f7_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
return OK;
}
/************************************************************************************
- * Name: stm32f7_i2c_deinit
+ * Name: stm32_i2c_deinit
*
* Description:
* Shutdown the I2C hardware
*
************************************************************************************/
-static int stm32f7_i2c_deinit(FAR struct stm32f7_i2c_priv_s *priv)
+static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv)
{
/* Disable I2C */
- stm32f7_i2c_putreg32(priv, STM32F7_I2C_CR1_OFFSET, 0);
+ stm32_i2c_putreg32(priv, STM32F7_I2C_CR1_OFFSET, 0);
/* Unconfigure GPIO pins */
stm32_unconfiggpio(priv->config->scl_pin);
stm32_unconfiggpio(priv->config->sda_pin);
+#ifndef CONFIG_I2C_POLLED
+
/* Disable and detach interrupts */
-#ifndef CONFIG_I2C_POLLED
up_disable_irq(priv->config->ev_irq);
up_disable_irq(priv->config->er_irq);
irq_detach(priv->config->ev_irq);
@@ -1618,50 +2219,41 @@ static int stm32f7_i2c_deinit(FAR struct stm32f7_i2c_priv_s *priv)
/* Disable clocking */
modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0);
+
return OK;
}
-/************************************************************************************
- * Device Driver Operations
- ************************************************************************************/
/************************************************************************************
- * Name: stm32f7_i2c_transfer
+ * Name: stm32_i2c_process
*
* Description:
- * Generic I2C transfer function
+ * Common I2C transfer logic
+ *
+ * Initiates a master mode transaction on the I2C bus to transfer the provided
+ * messages to and from the slave devices.
*
************************************************************************************/
-static int stm32f7_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
- int count)
+static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs, int count)
{
- FAR struct stm32f7_i2c_priv_s *priv = (struct stm32f7_i2c_priv_s *)dev;
- uint32_t status = 0;
- int ret = OK;
-
- DEBUGASSERT(dev != NULL && msgs != NULL && count > 0);
+ struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev;
+ FAR struct stm32_i2c_priv_s *priv = inst->priv;
+ uint32_t status = 0;
+ uint32_t cr1 = 0;
+ uint32_t cr2 = 0;
+ int errval = 0;
+ int waitrc = 0;
- /* Ensure that address or flags don't change meanwhile */
+ ASSERT(count);
- stm32f7_i2c_sem_wait(priv);
+ /* Wait for any STOP in progress */
- /* Wait for any STOP in progress. */
-
- stm32f7_i2c_sem_waitstop(priv);
+ stm32_i2c_sem_waitstop(priv);
/* Clear any pending error interrupts */
- stm32f7_i2c_clearinterrupts(priv);
-
- /* "Note: When the STOP, START or PEC bit is set, the software must
- * not perform any write access to I2C_CR1 before this bit is
- * cleared by hardware. Otherwise there is a risk of setting a
- * second STOP, START or PEC request." However, if the bits are
- * not cleared by hardware, then we will have to do that from hardware.
- */
-
- stm32f7_i2c_clrstart(priv);
+ stm32_i2c_clearinterrupts(priv);
/* Old transfers are done */
@@ -1670,184 +2262,354 @@ static int stm32f7_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg
/* Reset I2C trace logic */
- stm32f7_i2c_tracereset(priv);
+ stm32_i2c_tracereset(priv);
- /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !)
- * REVISIT: Note that the frequency is set only on the first message.
- * This could be extended to support different transfer frequencies for
- * each message segment.
- */
+ /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) */
- stm32f7_i2c_setclock(priv, msgs->frequency);
+ stm32_i2c_setclock(priv, msgs->frequency);
/* Trigger start condition, then the process moves into the ISR. I2C
- * interrupts will be enabled within stm32f7_i2c_waitdone().
+ * interrupts will be enabled within stm32_i2c_waitdone().
*/
priv->status = 0;
#ifndef CONFIG_I2C_POLLED
- stm32f7_i2c_enableinterrupts(priv);
+
+ /* Enable transmit and receive interrupts here so when we send the start
+ * condition below the ISR will fire if the data was sent and some
+ * response from the slave received. All other interrupts relevant to
+ * our needs are enabled in stm32_i2c_sem_waitdone() below.
+ */
+
+ stm32_i2c_enableinterrupts(priv);
#endif
- stm32f7_i2c_sendstart(priv);
+ /* Trigger START condition generation, which also sends the slave address
+ * with read/write flag and the data in the first message
+ */
+
+ stm32_i2c_sendstart(priv);
- /* Wait for an ISR, if there was a timeout, fetch latest status to get
- * the BUSY flag.
+ /* Wait for the ISR to tell us that the transfer is complete by attempting
+ * to grab the semaphore that is initially locked by the ISR. If the ISR
+ * does not release the lock so we can obtain it here prior to the end of
+ * the timeout period waitdone returns error and we report a timeout.
*/
- if (stm32f7_i2c_sem_waitdone(priv) < 0)
- {
- status = stm32f7_i2c_getstatus(priv);
- ret = -ETIMEDOUT;
+ waitrc = stm32_i2c_sem_waitdone(priv);
- i2cdbg("Timed out: CR1: %04x status: %08x\n",
- stm32f7_i2c_getreg(priv, STM32F7_I2C_CR1_OFFSET), status);
+ cr1 = stm32_i2c_getreg32(priv, STM32F7_I2C_CR1_OFFSET);
+ cr2 = stm32_i2c_getreg32(priv, STM32F7_I2C_CR2_OFFSET);
- /* "Note: When the STOP, START or PEC bit is set, the software must
- * not perform any write access to I2C_CR1 before this bit is
- * cleared by hardware. Otherwise there is a risk of setting a
- * second STOP, START or PEC request."
- */
+ /* Status after a normal / good exit is usually 0x00000001, meaning the TXE
+ * bit is set. That occurs as a result of the I2C_TXDR register being
+ * empty, and it naturally will be after the last byte is transmitted.
+ * This bit is cleared when we attempt communications again and re-enable
+ * the peripheral. The priv->status field can hold additional information
+ * like a NACK, so we reset the status field to include that information.
+ */
- stm32f7_i2c_clrstart(priv);
+ status = stm32_i2c_getstatus(priv);
- /* Clear busy flag in case of timeout */
+ /* The priv->status field can hold additional information like a NACK
+ * event so we include that information.
+ */
- status = priv->status & 0xffff;
- }
- else
+ status = priv->status & 0xffffffff;
+
+ if (waitrc < 0)
{
- /* clear SR2 (BUSY flag) as we've done successfully */
+ /* Connection timed out */
- status = priv->status & 0xffff;
+ errval = ETIMEDOUT;
+ i2cdbg("Waitdone timed out: CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n",
+ cr1, cr2,status);
}
-
- status &= ~I2C_ISR_BUSY;
-#if 0
- /* Refresh status */
- do
+ else
{
- status = stm32f7_i2c_getstatus(priv);
+ i2cdbg("Waitdone success: CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n",
+ cr1, cr2,status );
}
- while (STATUS_BUSY(status));
-#endif
+
+ i2cdbg("priv->status: 0x%08x\n", priv->status);
/* Check for error status conditions */
- if ((status & I2C_ISR_ERRORMASK) != 0)
+ if ((status & (I2C_INT_BERR |
+ I2C_INT_ARLO |
+ I2C_INT_OVR |
+ I2C_INT_PECERR |
+ I2C_INT_TIMEOUT |
+ I2C_INT_NACK)) != 0)
+
{
- /* I2C_SR1_ERRORMASK is the 'OR' of the following individual bits: */
+ /* one or more errors in the mask are present */
if (status & I2C_INT_BERR)
{
/* Bus Error */
- ret = -EIO;
+ i2cdbg("I2C: Bus Error\n");
+ errval = EIO;
}
else if (status & I2C_INT_ARLO)
{
/* Arbitration Lost (master mode) */
- ret = -EAGAIN;
+ i2cdbg("I2C: Arbitration Lost\n");
+ errval = EAGAIN;
}
- /* TODO Acknowledge failure */
-
else if (status & I2C_INT_OVR)
{
/* Overrun/Underrun */
- ret = -EIO;
+ i2cdbg("I2C: Overrun/Underrun\n");
+ errval = EIO;
}
else if (status & I2C_INT_PECERR)
{
- /* PEC Error in reception */
+ /* PEC Error in reception (SMBus Only) */
- ret = -EPROTO;
+ i2cdbg("I2C: PEC Error\n");
+ errval = EPROTO;
}
else if (status & I2C_INT_TIMEOUT)
{
- /* Timeout or Tlow Error */
+ /* Timeout or Tlow Error (SMBus Only) */
- ret = -ETIME;
+ i2cdbg("I2C: Timeout / Tlow Error\n");
+ errval = ETIME;
}
-
- /* This is not an error and should never happen since SMBus is not
- * enabled
- */
-
- else /* if (status & I2C_INT_ALERT) */
+ else if (status & I2C_INT_NACK)
+ {
+ /* NACK Received, flag as "communication error on send" */
+
+ if (priv->astart == TRUE)
+ {
+ i2cdbg("I2C: Address NACK\n");
+ errval = EADDRNOTAVAIL;
+ }
+ else
+ {
+ i2cdbg("I2C: Data NACK\n");
+ errval = ECOMM;
+ }
+ }
+ else
{
- /* SMBus alert is an optional signal with an interrupt line for devices
- * that want to trade their ability to master for a pin.
- */
+ /* Unrecognized error */
- ret = -EINTR;
+ i2cdbg("I2C: Unrecognized Error");
+ errval = EINTR;
}
}
- /* This is not an error, but should not happen. The BUSY signal can hang,
- * however, if there are unhealthy devices on the bus that need to be reset.
- * NOTE: We will only see this buy indication if stm32f7_i2c_sem_waitdone()
+ /* This is not an error, but should not happen. The BUSY signal can be
+ * present if devices on the bus are in an odd state and need to be reset.
+ * NOTE: We will only see this busy indication if stm32_i2c_sem_waitdone()
* fails above; Otherwise it is cleared.
*/
else if ((status & I2C_ISR_BUSY) != 0)
{
- /* I2C Bus is for some reason busy */
- ret = -EBUSY;
+ /* I2C Bus Busy
+ *
+ * This is a status condition rather than an error.
+ *
+ * We will only see this busy indication if stm32_i2c_sem_waitdone()
+ * fails above; Otherwise it is cleared by the hardware when the ISR
+ * wraps up the transfer with a STOP condition.
+ */
+ i2cdbg("I2C: Bus busy");
+ errval = EBUSY;
}
/* Dump the trace result */
- stm32f7_i2c_tracedump(priv);
- stm32f7_i2c_sem_post(priv);
- return ret;
+ stm32_i2c_tracedump(priv);
+ stm32_i2c_sem_post(dev);
+
+ return -errval;
}
/************************************************************************************
- * Name: stm32f7_i2c_reset
+ * Name: stm32_i2c_transfer
*
* Description:
- * Perform an I2C bus reset in an attempt to break loose stuck I2C devices.
+ * Generic I2C transfer function
*
- * Input Parameters:
- * dev - Device-specific state data
+ ************************************************************************************/
+
+static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
+ int count)
+{
+ stm32_i2c_sem_wait(dev); /* ensure that address or flags don't change meanwhile */
+ return stm32_i2c_process(dev, msgs, count);
+}
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: up_i2cinitialize
+ *
+ * Description:
+ * Initialize one I2C bus
+ *
+ ************************************************************************************/
+
+FAR struct i2c_master_s *stm32f7_i2cbus_initialize(int port)
+{
+ struct stm32_i2c_priv_s * priv = NULL; /* private data of device with multiple instances */
+ struct stm32_i2c_inst_s * inst = NULL; /* device, single instance */
+ int irqs;
+
+#if STM32_PCLK1_FREQUENCY < 4000000
+# warning STM32_I2C_INIT: Peripheral clock must be at least 4 MHz to support 400 kHz operation.
+#endif
+
+#if STM32_PCLK1_FREQUENCY < 2000000
+# warning STM32_I2C_INIT: Peripheral clock must be at least 2 MHz to support 100 kHz operation.
+ return NULL;
+#endif
+
+ /* Get I2C private structure */
+
+ switch (port)
+ {
+#ifdef CONFIG_STM32F7_I2C1
+ case 1:
+ priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv;
+ break;
+#endif
+#ifdef CONFIG_STM32F7_I2C2
+ case 2:
+ priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv;
+ break;
+#endif
+#ifdef CONFIG_STM32F7_I2C3
+ case 3:
+ priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv;
+ break;
+#endif
+ default:
+ return NULL;
+ }
+
+ /* Allocate instance */
+
+ if (!(inst = kmm_malloc(sizeof(struct stm32_i2c_inst_s))))
+ {
+ return NULL;
+ }
+
+ /* Initialize instance */
+
+ inst->ops = &stm32_i2c_ops;
+ inst->priv = priv;
+ inst->frequency = 0;
+ inst->address = 0;
+ inst->flags = 0;
+
+ /* Init private data for the first time, increment refs count,
+ * power-up hardware and configure GPIOs.
+ */
+
+ irqs = enter_critical_section();
+
+ if ((volatile int)priv->refs++ == 0)
+ {
+ stm32_i2c_sem_init((struct i2c_master_s *)inst);
+ stm32_i2c_init(priv);
+ }
+
+ leave_critical_section(irqs);
+ return (struct i2c_master_s *)inst;
+}
+
+/************************************************************************************
+ * Name: up_i2cuninitialize
+ *
+ * Description:
+ * Uninitialize an I2C bus
+ *
+ ************************************************************************************/
+
+int stm32f7_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
+{
+ int irqs;
+
+ ASSERT(dev);
+
+ /* Decrement refs and check for underflow */
+
+ if (((struct stm32_i2c_inst_s *)dev)->priv->refs == 0)
+ {
+ return ERROR;
+ }
+
+ irqs = enter_critical_section();
+
+ if (--((struct stm32_i2c_inst_s *)dev)->priv->refs)
+ {
+ leave_critical_section(irqs);
+ kmm_free(dev);
+ return OK;
+ }
+
+ leave_critical_section(irqs);
+
+ /* Disable power and other HW resource (GPIO's) */
+
+ stm32_i2c_deinit(((struct stm32_i2c_inst_s *)dev)->priv);
+
+ /* Release unused resources */
+
+ stm32_i2c_sem_destroy((struct i2c_master_s *)dev);
+
+ kmm_free(dev);
+ return OK;
+}
+
+/************************************************************************************
+ * Name: up_i2creset
*
- * Returned Value:
- * Zero (OK) on success; a negated errno value on failure.
+ * Description:
+ * Reset an I2C bus
*
************************************************************************************/
#ifdef CONFIG_I2C_RESET
-static int stm32f7_i2c_reset(FAR struct i2c_master_s * dev)
+int up_i2creset(FAR struct i2c_master_s * dev)
{
+ struct stm32_i2c_priv_s * priv;
unsigned int clock_count;
unsigned int stretch_count;
uint32_t scl_gpio;
uint32_t sda_gpio;
- uint32_t frequency;
int ret = ERROR;
ASSERT(dev);
+ /* Get I2C private structure */
+
+ priv = ((struct stm32_i2c_inst_s *)dev)->priv;
+
/* Our caller must own a ref */
ASSERT(priv->refs > 0);
/* Lock out other clients */
- stm32f7_i2c_sem_wait(priv);
-
- /* Save the current frequency */
-
- frequency = priv->frequency;
+ stm32_i2c_sem_wait(dev);
/* De-init the port */
- stm32f7_i2c_deinit(priv);
+ stm32_i2c_deinit(priv);
/* Use GPIO configuration to un-wedge the bus */
@@ -1856,12 +2618,12 @@ static int stm32f7_i2c_reset(FAR struct i2c_master_s * dev)
/* Let SDA go high */
- stm32f7_gpiowrite(sda_gpio, 1);
+ stm32_gpiowrite(sda_gpio, 1);
/* Clock the bus until any slaves currently driving it let it go. */
clock_count = 0;
- while (!stm32f7_gpioread(sda_gpio))
+ while (!stm32_gpioread(sda_gpio))
{
/* Give up if we have tried too hard */
@@ -1876,7 +2638,7 @@ static int stm32f7_i2c_reset(FAR struct i2c_master_s * dev)
*/
stretch_count = 0;
- while (!stm32f7_gpioread(scl_gpio))
+ while (!stm32_gpioread(scl_gpio))
{
/* Give up if we have tried too hard */
@@ -1890,12 +2652,12 @@ static int stm32f7_i2c_reset(FAR struct i2c_master_s * dev)
/* Drive SCL low */
- stm32f7_gpiowrite(scl_gpio, 0);
+ stm32_gpiowrite(scl_gpio, 0);
up_udelay(10);
/* Drive SCL high again */
- stm32f7_gpiowrite(scl_gpio, 1);
+ stm32_gpiowrite(scl_gpio, 1);
up_udelay(10);
}
@@ -1903,13 +2665,13 @@ static int stm32f7_i2c_reset(FAR struct i2c_master_s * dev)
* state machines.
*/
- stm32f7_gpiowrite(sda_gpio, 0);
+ stm32_gpiowrite(sda_gpio, 0);
up_udelay(10);
- stm32f7_gpiowrite(scl_gpio, 0);
+ stm32_gpiowrite(scl_gpio, 0);
up_udelay(10);
- stm32f7_gpiowrite(scl_gpio, 1);
+ stm32_gpiowrite(scl_gpio, 1);
up_udelay(10);
- stm32f7_gpiowrite(sda_gpio, 1);
+ stm32_gpiowrite(sda_gpio, 1);
up_udelay(10);
/* Revert the GPIO configuration. */
@@ -1919,129 +2681,17 @@ static int stm32f7_i2c_reset(FAR struct i2c_master_s * dev)
/* Re-init the port */
- stm32f7_i2c_init(priv);
-
- /* Restore the frequency */
-
- stm32f7_i2c_setclock(priv, frequency);
+ stm32_i2c_init(priv);
ret = OK;
out:
/* Release the port for re-use by other clients */
- stm32f7_i2c_sem_post(priv);
+ stm32_i2c_sem_post(dev);
return ret;
}
#endif /* CONFIG_I2C_RESET */
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-/************************************************************************************
- * Name: stm32f7_i2cbus_initialize
- *
- * Description:
- * Initialize one I2C bus
- *
- ************************************************************************************/
-
-FAR struct i2c_master_s *stm32f7_i2cbus_initialize(int port)
-{
- struct stm32f7_i2c_priv_s * priv = NULL; /* private data of device with multiple instances */
- irqstate_t flags;
-
-#if STM32_PCLK1_FREQUENCY < 4000000
-# warning STM32F7_I2C_INIT: Peripheral clock must be at least 4 MHz to support 400 kHz operation.
-#endif
-
-#if STM32_PCLK1_FREQUENCY < 2000000
-# warning STM32F7_I2C_INIT: Peripheral clock must be at least 2 MHz to support 100 kHz operation.
- return NULL;
-#endif
-
- /* Get I2C private structure */
-
- switch (port)
- {
-#ifdef CONFIG_STM32F7_I2C1
- case 1:
- priv = (struct stm32f7_i2c_priv_s *)&stm32f7_i2c1_priv;
- break;
-#endif
-#ifdef CONFIG_STM32F7_I2C2
- case 2:
- priv = (struct stm32f7_i2c_priv_s *)&stm32f7_i2c2_priv;
- break;
-#endif
-#ifdef CONFIG_STM32F7_I2C3
- case 3:
- priv = (struct stm32f7_i2c_priv_s *)&stm32f7_i2c3_priv;
- break;
-#endif
- default:
- return NULL;
- }
-
- /* Init private data for the first time, increment refs count,
- * power-up hardware and configure GPIOs.
- */
-
- flags = enter_critical_section();
-
- if ((volatile int)priv->refs++ == 0)
- {
- stm32f7_i2c_sem_init(priv);
- stm32f7_i2c_init(priv);
- }
-
- leave_critical_section(flags);
- return (struct i2c_master_s *)priv;
-}
-
-/************************************************************************************
- * Name: stm32f7_i2cbus_uninitialize
- *
- * Description:
- * Uninitialize an I2C bus
- *
- ************************************************************************************/
-
-int stm32f7_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
-{
- FAR struct stm32f7_i2c_priv_s *priv = (struct stm32f7_i2c_priv_s *)dev;
- irqstate_t flags;
-
- ASSERT(dev);
-
- /* Decrement refs and check for underflow */
-
- if (priv->refs == 0)
- {
- return ERROR;
- }
-
- flags = enter_critical_section();
-
- if (--priv->refs)
- {
- leave_critical_section(flags);
- return OK;
- }
-
- leave_critical_section(flags);
-
- /* Disable power and other HW resource (GPIO's) */
-
- stm32f7_i2c_deinit(priv);
-
- /* Release unused resources */
-
- stm32f7_i2c_sem_destroy(priv);
- return OK;
-}
-
#endif /* CONFIG_STM32F7_I2C1 || CONFIG_STM32F7_I2C2 || CONFIG_STM32F7_I2C3 */
-
diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig
index 1be6e1b081..73e832d3fd 100644
--- a/configs/stm32f746-ws/nsh/defconfig
+++ b/configs/stm32f746-ws/nsh/defconfig
@@ -318,7 +318,7 @@ CONFIG_NSH_MMCSDMINOR=0
#
# Board-Specific Options
#
-# CONFIG_LIB_BOARDCTL is not set
+CONFIG_LIB_BOARDCTL=y
#
# RTOS Features
@@ -907,8 +907,10 @@ CONFIG_READLINE_ECHO=y
# CONFIG_SYSTEM_UBLOXMODEM is not set
# CONFIG_SYSTEM_ZMODEM is not set
+CONFIG_I2C_DRIVER=y
+
CONFIG_SYSTEM_I2CTOOL=y
-CONFIG_I2CTOOL_MINBUS=0
+CONFIG_I2CTOOL_MINBUS=1
CONFIG_I2CTOOL_MAXBUS=1
CONFIG_I2CTOOL_MINADDR=0x03
CONFIG_I2CTOOL_MAXADDR=0x77
diff --git a/configs/stm32f746-ws/src/stm32_appinitialize.c b/configs/stm32f746-ws/src/stm32_appinitialize.c
index 610f4978e2..0df665374e 100644
--- a/configs/stm32f746-ws/src/stm32_appinitialize.c
+++ b/configs/stm32f746-ws/src/stm32_appinitialize.c
@@ -40,9 +40,38 @@
#include
#include
+#include
+#include
+#include
#include "stm32f746-ws.h"
-#include
+#include "stm32_i2c.h"
+
+static void stm32f7_i2c_register(int bus)
+{
+ FAR struct i2c_master_s *i2c;
+ int ret;
+
+ i2c = stm32f7_i2cbus_initialize(bus);
+ if (i2c == NULL)
+ {
+ dbg("ERROR: Failed to get I2C%d interface\n", bus);
+ }
+ else
+ {
+ ret = i2c_register(i2c, bus);
+ if (ret < 0)
+ {
+ dbg("ERROR: Failed to register I2C%d driver: %d\n", bus, ret);
+ stm32f7_i2cbus_uninitialize(i2c);
+ }
+ }
+}
+
+static void stm32f7_i2ctool(void)
+{
+ stm32f7_i2c_register(1);
+}
/****************************************************************************
* Public Functions
@@ -60,6 +89,9 @@
int board_app_initialize(void)
{
+ /* Register I2C drivers on behalf of the I2C tool */
+
+ stm32f7_i2ctool();
return OK;
}
--
GitLab
From f65616f872f2e3ea653ebb107db66951a13c27da Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Mon, 30 May 2016 09:16:08 -0600
Subject: [PATCH 008/400] Replace confusing references to uIP with just 'the
network'
---
TODO | 6 ++++++
arch/arm/src/c5471/c5471_ethernet.c | 24 ++++++++++++------------
arch/arm/src/imx6/Make.defs | 4 ++++
arch/arm/src/kinetis/kinetis_enet.c | 14 +++++++-------
arch/arm/src/lpc43xx/lpc43_ethernet.c | 16 ++++++++--------
arch/arm/src/sam34/sam_emac.c | 18 +++++++++---------
arch/arm/src/sama5/sam_emaca.c | 18 +++++++++---------
arch/arm/src/sama5/sam_emacb.c | 18 +++++++++---------
arch/arm/src/sama5/sam_gmac.c | 18 +++++++++---------
arch/arm/src/stm32/stm32_eth.c | 20 ++++++++++----------
arch/arm/src/stm32f7/stm32_ethernet.c | 20 ++++++++++----------
arch/arm/src/tiva/lm3s_ethernet.c | 18 +++++++++---------
arch/arm/src/tiva/tm4c_ethernet.c | 20 ++++++++++----------
13 files changed, 112 insertions(+), 102 deletions(-)
diff --git a/TODO b/TODO
index eeb3e6d29d..b131d0205e 100644
--- a/TODO
+++ b/TODO
@@ -599,6 +599,12 @@ o Kernel/Protected Build
For a truly secure system. Privileges need to be checked in
every interface that permits one thread to modify the
properties of another thread.
+
+ NOTE: It would be a simple matter to simply disable user
+ threads from modifying privileged threads. However, you
+ might also want to be able to modify privileged threads from
+ user tasks with certain permissions. Permissions is a much
+ more complex issue.
Status: Open
Priority: Low for most embedded systems but would be a critical need if
NuttX were used in a secure system.
diff --git a/arch/arm/src/c5471/c5471_ethernet.c b/arch/arm/src/c5471/c5471_ethernet.c
index 11c157f35f..5d1ddb6863 100644
--- a/arch/arm/src/c5471/c5471_ethernet.c
+++ b/arch/arm/src/c5471/c5471_ethernet.c
@@ -331,9 +331,9 @@ struct c5471_driver_s
uint32_t c_rxdropped; /* Packets dropped because of size */
#endif
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s c_dev; /* Interface understood by uIP */
+ struct net_driver_s c_dev; /* Interface understood by the network */
};
/****************************************************************************
@@ -960,7 +960,7 @@ static int c5471_transmit(struct c5471_driver_s *c5471)
* Function: c5471_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -1162,7 +1162,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
int j = 0;
/* Walk the newly received packet contained within the EIM and transfer
- * its contents to the uIP buffer. This frees up the memory contained within
+ * its contents to the network buffer. This frees up the memory contained within
* the EIM for additional packets that might be received later from the network.
*/
@@ -1185,7 +1185,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
framelen = (getreg32(c5471->c_txcpudesc) & EIM_TXDESC_BYTEMASK);
packetlen += framelen;
- /* Check if the received packet will fit within the uIP packet buffer */
+ /* Check if the received packet will fit within the network packet buffer */
if (packetlen < (CONFIG_NET_ETH_MTU + 4))
{
@@ -1234,7 +1234,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
c5471_inctxcpu(c5471);
}
- /* Adjust the packet length to remove the CRC bytes that uIP doesn't care about. */
+ /* Adjust the packet length to remove the CRC bytes that the network doesn't care about. */
packetlen -= 4;
@@ -1244,8 +1244,8 @@ static void c5471_receive(struct c5471_driver_s *c5471)
c5471->c_rxpackets++;
#endif
- /* If we successfully transferred the data into the uIP buffer, then pass it on
- * to uIP for processing.
+ /* If we successfully transferred the data into the network buffer, then pass it on
+ * to the network for processing.
*/
if (packetlen > 0 && packetlen < CONFIG_NET_ETH_MTU)
@@ -1496,7 +1496,7 @@ static void c5471_txdone(struct c5471_driver_s *c5471)
wd_cancel(c5471->c_txtimeout);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&c5471->c_dev, c5471_txpoll);
}
@@ -1615,7 +1615,7 @@ static void c5471_txtimeout(int argc, uint32_t arg, ...)
c5471_ifdown(&c5471->c_dev);
c5471_ifup(&c5471->c_dev);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&c5471->c_dev, c5471_txpoll);
}
@@ -1647,7 +1647,7 @@ static void c5471_polltimer(int argc, uint32_t arg, ...)
if ((EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) == 0)
{
- /* If so, update TCP timing states and poll uIP for new XMIT data */
+ /* If so, update TCP timing states and poll the network for new XMIT data */
(void)devif_timer(&c5471->c_dev, c5471_txpoll);
}
@@ -1811,7 +1811,7 @@ static int c5471_txavail(struct net_driver_s *dev)
if ((EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) == 0)
{
- /* If so, then poll uIP for new XMIT data */
+ /* If so, then poll the network for new XMIT data */
(void)devif_poll(&c5471->c_dev, c5471_txpoll);
}
diff --git a/arch/arm/src/imx6/Make.defs b/arch/arm/src/imx6/Make.defs
index 3f949158e3..47b36a5f1a 100644
--- a/arch/arm/src/imx6/Make.defs
+++ b/arch/arm/src/imx6/Make.defs
@@ -150,3 +150,7 @@ CHIP_CSRCS += imx_serial.c imx_lowputc.c
ifeq ($(CONFIG_SMP),y)
CHIP_CSRCS += imx_cpuboot.c
endif
+
+ifeq ($(CONFIG_IMX6_ECSPI),y)
+CHIP_CSRCS += imx_ecspi.c
+endif
diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c
index 95e511546f..0a05346055 100644
--- a/arch/arm/src/kinetis/kinetis_enet.c
+++ b/arch/arm/src/kinetis/kinetis_enet.c
@@ -165,9 +165,9 @@ struct kinetis_driver_s
struct enet_desc_s *txdesc; /* A pointer to the list of TX descriptor */
struct enet_desc_s *rxdesc; /* A pointer to the list of RX descriptors */
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
/* The DMA descriptors. A unaligned uint8_t is used to allocate the
* memory; 16 is added to assure that we can meet the descriptor alignment
@@ -435,7 +435,7 @@ static int kinetis_transmit(FAR struct kinetis_driver_s *priv)
* Function: kinetis_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -731,7 +731,7 @@ static void kinetis_txdone(FAR struct kinetis_driver_s *priv)
putreg32(regval, KINETIS_ENET_EIMR);
}
- /* There should be space for a new TX in any event. Poll uIP for new XMIT
+ /* There should be space for a new TX in any event. Poll the network for new XMIT
* data
*/
@@ -848,7 +848,7 @@ static void kinetis_txtimeout(int argc, uint32_t arg, ...)
(void)kinetis_ifdown(&priv->dev);
(void)kinetis_ifup(&priv->dev);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&priv->dev, kinetis_txpoll);
}
@@ -881,7 +881,7 @@ static void kinetis_polltimer(int argc, uint32_t arg, ...)
if (!kinetics_txringfull(priv))
{
- /* If so, update TCP timing states and poll uIP for new XMIT data. Hmmm..
+ /* If so, update TCP timing states and poll the network for new XMIT data. Hmmm..
* might be bug here. Does this mean if there is a transmit in progress,
* we will missing TCP time state updates?
*/
@@ -1112,7 +1112,7 @@ static int kinetis_txavail(struct net_driver_s *dev)
if (!kinetics_txringfull(priv))
{
- /* No, there is space for another transfer. Poll uIP for new
+ /* No, there is space for another transfer. Poll the network for new
* XMIT data.
*/
diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c
index 733a161c2b..cca1e89766 100644
--- a/arch/arm/src/lpc43xx/lpc43_ethernet.c
+++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c
@@ -522,9 +522,9 @@ struct lpc43_ethmac_s
struct work_s work; /* For deferring work to the work queue */
#endif
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
/* Used to track transmit and receive descriptors */
@@ -928,7 +928,7 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
struct eth_txdesc_s *txdesc;
struct eth_txdesc_s *txfirst;
- /* The internal (optimal) uIP buffer size may be configured to be larger
+ /* The internal (optimal) network buffer size may be configured to be larger
* than the Ethernet buffer size.
*/
@@ -1114,7 +1114,7 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
* Function: lpc43_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -1520,7 +1520,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
buffer = lpc43_allocbuffer(priv);
/* Take the buffer from the RX descriptor of the first free
- * segment, put it into the uIP device structure, then replace
+ * segment, put it into the network device structure, then replace
* the buffer in the RX descriptor with the newly allocated
* buffer.
*/
@@ -1602,7 +1602,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
pkt_input(&priv->dev);
#endif
- /* Check if the packet is a valid size for the uIP buffer configuration
+ /* Check if the packet is a valid size for the network buffer configuration
* (this should not happen)
*/
@@ -1888,7 +1888,7 @@ static void lpc43_txdone(FAR struct lpc43_ethmac_s *priv)
lpc43_disableint(priv, ETH_DMAINT_TI);
}
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
lpc43_dopoll(priv);
}
@@ -2120,7 +2120,7 @@ static inline void lpc43_txtimeout_process(FAR struct lpc43_ethmac_s *priv)
lpc43_ifdown(&priv->dev);
lpc43_ifup(&priv->dev);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
lpc43_dopoll(priv);
}
diff --git a/arch/arm/src/sam34/sam_emac.c b/arch/arm/src/sam34/sam_emac.c
index d33f1d8aab..c11332586a 100644
--- a/arch/arm/src/sam34/sam_emac.c
+++ b/arch/arm/src/sam34/sam_emac.c
@@ -278,9 +278,9 @@ struct sam_emac_s
struct work_s work; /* For deferring work to the work queue */
#endif
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
/* Used to track transmit and receive descriptors */
@@ -841,7 +841,7 @@ static int sam_transmit(struct sam_emac_s *priv)
* Function: sam_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -951,7 +951,7 @@ static void sam_dopoll(struct sam_emac_s *priv)
if (sam_txfree(priv) > 0)
{
- /* If we have the descriptor, then poll uIP for new XMIT data. */
+ /* If we have the descriptor, then poll the network for new XMIT data. */
(void)devif_poll(dev, sam_txpoll);
}
@@ -1201,7 +1201,7 @@ static void sam_receive(struct sam_emac_s *priv)
{
sam_dumppacket("Received packet", dev->d_buf, dev->d_len);
- /* Check if the packet is a valid size for the uIP buffer configuration
+ /* Check if the packet is a valid size for the network buffer configuration
* (this should not happen)
*/
@@ -1403,7 +1403,7 @@ static void sam_txdone(struct sam_emac_s *priv)
sam_putreg(priv, SAM_EMAC_IER, EMAC_INT_RCOMP);
}
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -1734,7 +1734,7 @@ static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv)
sam_ifdown(&priv->dev);
sam_ifup(&priv->dev);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -1844,7 +1844,7 @@ static inline void sam_poll_process(FAR struct sam_emac_s *priv)
if (sam_txfree(priv) > 0)
{
- /* Update TCP timing states and poll uIP for new XMIT data. */
+ /* Update TCP timing states and poll the network for new XMIT data. */
(void)devif_timer(dev, sam_txpoll);
}
@@ -2083,7 +2083,7 @@ static inline void sam_txavail_process(FAR struct sam_emac_s *priv)
if (priv->ifup)
{
- /* Poll uIP for new XMIT data */
+ /* Poll the network for new XMIT data */
sam_dopoll(priv);
}
diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c
index 5d3ad03e60..a4f895760d 100644
--- a/arch/arm/src/sama5/sam_emaca.c
+++ b/arch/arm/src/sama5/sam_emaca.c
@@ -267,9 +267,9 @@ struct sam_emac_s
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
/* Used to track transmit and receive descriptors */
@@ -817,7 +817,7 @@ static int sam_transmit(struct sam_emac_s *priv)
* Function: sam_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -926,7 +926,7 @@ static void sam_dopoll(struct sam_emac_s *priv)
if (sam_txfree(priv) > 0)
{
- /* If we have the descriptor, then poll uIP for new XMIT data. */
+ /* If we have the descriptor, then poll the network for new XMIT data. */
(void)devif_poll(dev, sam_txpoll);
}
@@ -1206,7 +1206,7 @@ static void sam_receive(struct sam_emac_s *priv)
{
sam_dumppacket("Received packet", dev->d_buf, dev->d_len);
- /* Check if the packet is a valid size for the uIP buffer configuration
+ /* Check if the packet is a valid size for the network buffer configuration
* (this should not happen)
*/
@@ -1410,7 +1410,7 @@ static void sam_txdone(struct sam_emac_s *priv)
sam_putreg(priv, SAM_EMAC_IER, EMAC_INT_RCOMP);
}
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -1633,7 +1633,7 @@ static void sam_txtimeout(int argc, uint32_t arg, ...)
sam_ifdown(&priv->dev);
sam_ifup(&priv->dev);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -1667,7 +1667,7 @@ static void sam_polltimer(int argc, uint32_t arg, ...)
if (sam_txfree(priv) > 0)
{
- /* Update TCP timing states and poll uIP for new XMIT data. */
+ /* Update TCP timing states and poll the network for new XMIT data. */
(void)devif_timer(dev, sam_txpoll);
}
@@ -1837,7 +1837,7 @@ static int sam_txavail(struct net_driver_s *dev)
if (priv->ifup)
{
- /* Poll uIP for new XMIT data */
+ /* Poll the network for new XMIT data */
sam_dopoll(priv);
}
diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c
index fccc2d51f0..270acd635b 100644
--- a/arch/arm/src/sama5/sam_emacb.c
+++ b/arch/arm/src/sama5/sam_emacb.c
@@ -421,9 +421,9 @@ struct sam_emac_s
struct work_s work; /* For deferring work to the work queue */
#endif
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
/* Constant and configured attributes of the EMAC */
@@ -1180,7 +1180,7 @@ static int sam_transmit(struct sam_emac_s *priv)
* Function: sam_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -1290,7 +1290,7 @@ static void sam_dopoll(struct sam_emac_s *priv)
if (sam_txfree(priv) > 0)
{
- /* If we have the descriptor, then poll uIP for new XMIT data. */
+ /* If we have the descriptor, then poll the network for new XMIT data. */
(void)devif_poll(dev, sam_txpoll);
}
@@ -1569,7 +1569,7 @@ static void sam_receive(struct sam_emac_s *priv)
{
sam_dumppacket("Received packet", dev->d_buf, dev->d_len);
- /* Check if the packet is a valid size for the uIP buffer configuration
+ /* Check if the packet is a valid size for the network buffer configuration
* (this should not happen)
*/
@@ -1797,7 +1797,7 @@ static void sam_txdone(struct sam_emac_s *priv)
sam_putreg(priv, SAM_EMAC_IER_OFFSET, EMAC_INT_RCOMP);
}
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -2154,7 +2154,7 @@ static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv)
sam_ifdown(&priv->dev);
sam_ifup(&priv->dev);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -2264,7 +2264,7 @@ static inline void sam_poll_process(FAR struct sam_emac_s *priv)
if (sam_txfree(priv) > 0)
{
- /* Update TCP timing states and poll uIP for new XMIT data. */
+ /* Update TCP timing states and poll the network for new XMIT data. */
(void)devif_timer(dev, sam_txpoll);
}
@@ -2511,7 +2511,7 @@ static inline void sam_txavail_process(FAR struct sam_emac_s *priv)
if (priv->ifup)
{
- /* Poll uIP for new XMIT data */
+ /* Poll the network for new XMIT data */
sam_dopoll(priv);
}
diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c
index 8426e7dcb3..7db62d10db 100644
--- a/arch/arm/src/sama5/sam_gmac.c
+++ b/arch/arm/src/sama5/sam_gmac.c
@@ -193,9 +193,9 @@ struct sam_gmac_s
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
/* Used to track transmit and receive descriptors */
@@ -749,7 +749,7 @@ static int sam_transmit(struct sam_gmac_s *priv)
* Function: sam_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -858,7 +858,7 @@ static void sam_dopoll(struct sam_gmac_s *priv)
if (sam_txfree(priv) > 0)
{
- /* If we have the descriptor, then poll uIP for new XMIT data. */
+ /* If we have the descriptor, then poll the network for new XMIT data. */
(void)devif_poll(dev, sam_txpoll);
}
@@ -1136,7 +1136,7 @@ static void sam_receive(struct sam_gmac_s *priv)
{
sam_dumppacket("Received packet", dev->d_buf, dev->d_len);
- /* Check if the packet is a valid size for the uIP buffer configuration
+ /* Check if the packet is a valid size for the network buffer configuration
* (this should not happen)
*/
@@ -1338,7 +1338,7 @@ static void sam_txdone(struct sam_gmac_s *priv)
sam_putreg(priv, SAM_GMAC_IER, GMAC_INT_RCOMP);
}
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -1585,7 +1585,7 @@ static void sam_txtimeout(int argc, uint32_t arg, ...)
sam_ifdown(&priv->dev);
sam_ifup(&priv->dev);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
sam_dopoll(priv);
}
@@ -1619,7 +1619,7 @@ static void sam_polltimer(int argc, uint32_t arg, ...)
if (sam_txfree(priv) > 0)
{
- /* Update TCP timing states and poll uIP for new XMIT data. */
+ /* Update TCP timing states and poll the network for new XMIT data. */
(void)devif_timer(dev, sam_txpoll);
}
@@ -1792,7 +1792,7 @@ static int sam_txavail(struct net_driver_s *dev)
if (priv->ifup)
{
- /* Poll uIP for new XMIT data */
+ /* Poll the network for new XMIT data */
sam_dopoll(priv);
}
diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c
index 7b06b9a368..c7a4abc044 100644
--- a/arch/arm/src/stm32/stm32_eth.c
+++ b/arch/arm/src/stm32/stm32_eth.c
@@ -585,9 +585,9 @@ struct stm32_ethmac_s
struct work_s work; /* For deferring work to the work queue */
#endif
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
/* Used to track transmit and receive descriptors */
@@ -993,7 +993,7 @@ static int stm32_transmit(FAR struct stm32_ethmac_s *priv)
struct eth_txdesc_s *txdesc;
struct eth_txdesc_s *txfirst;
- /* The internal (optimal) uIP buffer size may be configured to be larger
+ /* The internal (optimal) network buffer size may be configured to be larger
* than the Ethernet buffer size.
*/
@@ -1179,7 +1179,7 @@ static int stm32_transmit(FAR struct stm32_ethmac_s *priv)
* Function: stm32_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -1321,7 +1321,7 @@ static void stm32_dopoll(FAR struct stm32_ethmac_s *priv)
if ((priv->txhead->tdes0 & ETH_TDES0_OWN) == 0 &&
priv->txhead->tdes2 == 0)
{
- /* If we have the descriptor, then poll uIP for new XMIT data.
+ /* If we have the descriptor, then poll the network for new XMIT data.
* Allocate a buffer for the poll.
*/
@@ -1585,7 +1585,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
buffer = stm32_allocbuffer(priv);
/* Take the buffer from the RX descriptor of the first free
- * segment, put it into the uIP device structure, then replace
+ * segment, put it into the network device structure, then replace
* the buffer in the RX descriptor with the newly allocated
* buffer.
*/
@@ -1667,7 +1667,7 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
pkt_input(&priv->dev);
#endif
- /* Check if the packet is a valid size for the uIP buffer configuration
+ /* Check if the packet is a valid size for the network buffer configuration
* (this should not happen)
*/
@@ -1955,7 +1955,7 @@ static void stm32_txdone(FAR struct stm32_ethmac_s *priv)
stm32_disableint(priv, ETH_DMAINT_TI);
}
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
stm32_dopoll(priv);
}
@@ -2321,7 +2321,7 @@ static inline void stm32_poll_process(FAR struct stm32_ethmac_s *priv)
if (dev->d_buf)
{
- /* Update TCP timing states and poll uIP for new XMIT data.
+ /* Update TCP timing states and poll the network for new XMIT data.
*/
(void)devif_timer(dev, stm32_txpoll);
@@ -2551,7 +2551,7 @@ static inline void stm32_txavail_process(FAR struct stm32_ethmac_s *priv)
if (priv->ifup)
{
- /* Poll uIP for new XMIT data */
+ /* Poll the network for new XMIT data */
stm32_dopoll(priv);
}
diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c
index 4cf496a4eb..4e6664ade1 100644
--- a/arch/arm/src/stm32f7/stm32_ethernet.c
+++ b/arch/arm/src/stm32f7/stm32_ethernet.c
@@ -609,9 +609,9 @@ struct stm32_ethmac_s
struct work_s work; /* For deferring work to the work queue */
#endif
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
/* Used to track transmit and receive descriptors */
@@ -1041,7 +1041,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
struct eth_txdesc_s *txdesc;
struct eth_txdesc_s *txfirst;
- /* The internal (optimal) uIP buffer size may be configured to be larger
+ /* The internal (optimal) network buffer size may be configured to be larger
* than the Ethernet buffer size.
*/
@@ -1249,7 +1249,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
* Function: stm32_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -1391,7 +1391,7 @@ static void stm32_dopoll(struct stm32_ethmac_s *priv)
if ((priv->txhead->tdes0 & ETH_TDES0_OWN) == 0 &&
priv->txhead->tdes2 == 0)
{
- /* If we have the descriptor, then poll uIP for new XMIT data.
+ /* If we have the descriptor, then poll the network for new XMIT data.
* Allocate a buffer for the poll.
*/
@@ -1675,7 +1675,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
buffer = stm32_allocbuffer(priv);
/* Take the buffer from the RX descriptor of the first free
- * segment, put it into the uIP device structure, then replace
+ * segment, put it into the network device structure, then replace
* the buffer in the RX descriptor with the newly allocated
* buffer.
*/
@@ -1778,7 +1778,7 @@ static void stm32_receive(struct stm32_ethmac_s *priv)
pkt_input(&priv->dev);
#endif
- /* Check if the packet is a valid size for the uIP buffer configuration
+ /* Check if the packet is a valid size for the network buffer configuration
* (this should not happen)
*/
@@ -2072,7 +2072,7 @@ static void stm32_txdone(struct stm32_ethmac_s *priv)
stm32_disableint(priv, ETH_DMAINT_TI);
}
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
stm32_dopoll(priv);
}
@@ -2437,7 +2437,7 @@ static inline void stm32_poll_process(struct stm32_ethmac_s *priv)
if (dev->d_buf)
{
- /* Update TCP timing states and poll uIP for new XMIT data.
+ /* Update TCP timing states and poll the network for new XMIT data.
*/
(void)devif_timer(dev, stm32_txpoll);
@@ -2667,7 +2667,7 @@ static inline void stm32_txavail_process(struct stm32_ethmac_s *priv)
if (priv->ifup)
{
- /* Poll uIP for new XMIT data */
+ /* Poll the network for new XMIT data */
stm32_dopoll(priv);
}
diff --git a/arch/arm/src/tiva/lm3s_ethernet.c b/arch/arm/src/tiva/lm3s_ethernet.c
index 5544e25442..0acaeb3c07 100644
--- a/arch/arm/src/tiva/lm3s_ethernet.c
+++ b/arch/arm/src/tiva/lm3s_ethernet.c
@@ -187,9 +187,9 @@ struct tiva_driver_s
WDOG_ID ld_txpoll; /* TX poll timer */
WDOG_ID ld_txtimeout; /* TX timeout timer */
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s ld_dev; /* Interface understood by uIP */
+ struct net_driver_s ld_dev; /* Interface understood by the network */
};
/****************************************************************************
@@ -558,7 +558,7 @@ static int tiva_transmit(struct tiva_driver_s *priv)
* Function: tiva_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -677,7 +677,7 @@ static void tiva_receive(struct tiva_driver_s *priv)
/* Check if the pktlen is valid. It should be large enough to hold
* an Ethernet header and small enough to fit entirely in the I/O
* buffer. Six is subtracted to acount for the 2-byte length/type
- * and 4 byte FCS that are not copied into the uIP packet.
+ * and 4 byte FCS that are not copied into the network packet.
*/
if (pktlen > (CONFIG_NET_ETH_MTU + 6) || pktlen <= (ETH_HDRLEN + 6))
@@ -752,7 +752,7 @@ static void tiva_receive(struct tiva_driver_s *priv)
}
}
- /* Pass the packet length to uIP MINUS 2 bytes for the length and
+ /* Pass the packet length to the network MINUS 2 bytes for the length and
* 4 bytes for the FCS.
*/
@@ -905,7 +905,7 @@ static void tiva_txdone(struct tiva_driver_s *priv)
DEBUGASSERT((tiva_ethin(priv, TIVA_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&priv->ld_dev, tiva_txpoll);
}
@@ -1033,7 +1033,7 @@ static void tiva_txtimeout(int argc, uint32_t arg, ...)
tiva_ifdown(&priv->ld_dev);
tiva_ifup(&priv->ld_dev);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&priv->ld_dev, tiva_txpoll);
}
@@ -1069,7 +1069,7 @@ static void tiva_polltimer(int argc, uint32_t arg, ...)
if ((tiva_ethin(priv, TIVA_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
{
- /* If so, update TCP timing states and poll uIP for new XMIT data */
+ /* If so, update TCP timing states and poll the network for new XMIT data */
(void)devif_timer(&priv->ld_dev, tiva_txpoll);
@@ -1353,7 +1353,7 @@ static int tiva_txavail(struct net_driver_s *dev)
flags = enter_critical_section();
if (priv->ld_bifup && (tiva_ethin(priv, TIVA_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
{
- /* If the interface is up and we can use the Tx FIFO, then poll uIP
+ /* If the interface is up and we can use the Tx FIFO, then poll the network
* for new Tx data
*/
diff --git a/arch/arm/src/tiva/tm4c_ethernet.c b/arch/arm/src/tiva/tm4c_ethernet.c
index d8e73bec3a..eeb36a32ec 100644
--- a/arch/arm/src/tiva/tm4c_ethernet.c
+++ b/arch/arm/src/tiva/tm4c_ethernet.c
@@ -630,7 +630,7 @@ struct tiva_ethmac_s
xcpt_t handler; /* Attached PHY interrupt handler */
#endif
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
struct net_driver_s dev; /* Interface understood by network subsystem */
@@ -1032,7 +1032,7 @@ static int tiva_transmit(FAR struct tiva_ethmac_s *priv)
struct emac_txdesc_s *txdesc;
struct emac_txdesc_s *txfirst;
- /* The internal (optimal) uIP buffer size may be configured to be larger
+ /* The internal (optimal) network buffer size may be configured to be larger
* than the Ethernet buffer size.
*/
@@ -1218,7 +1218,7 @@ static int tiva_transmit(FAR struct tiva_ethmac_s *priv)
* Function: tiva_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -1360,7 +1360,7 @@ static void tiva_dopoll(FAR struct tiva_ethmac_s *priv)
if ((priv->txhead->tdes0 & EMAC_TDES0_OWN) == 0 &&
priv->txhead->tdes2 == 0)
{
- /* If we have the descriptor, then poll uIP for new XMIT data.
+ /* If we have the descriptor, then poll the network for new XMIT data.
* Allocate a buffer for the poll.
*/
@@ -1624,7 +1624,7 @@ static int tiva_recvframe(FAR struct tiva_ethmac_s *priv)
buffer = tiva_allocbuffer(priv);
/* Take the buffer from the RX descriptor of the first free
- * segment, put it into the uIP device structure, then replace
+ * segment, put it into the network device structure, then replace
* the buffer in the RX descriptor with the newly allocated
* buffer.
*/
@@ -1706,7 +1706,7 @@ static void tiva_receive(FAR struct tiva_ethmac_s *priv)
pkt_input(&priv->dev);
#endif
- /* Check if the packet is a valid size for the uIP buffer configuration
+ /* Check if the packet is a valid size for the network buffer configuration
* (this should not happen)
*/
@@ -1980,7 +1980,7 @@ static void tiva_txdone(FAR struct tiva_ethmac_s *priv)
tiva_disableint(priv, EMAC_DMAINT_TI);
}
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
tiva_dopoll(priv);
}
@@ -2228,7 +2228,7 @@ static inline void tiva_txtimeout_process(FAR struct tiva_ethmac_s *priv)
tiva_ifdown(&priv->dev);
tiva_ifup(&priv->dev);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
tiva_dopoll(priv);
}
@@ -2362,7 +2362,7 @@ static inline void tiva_poll_process(FAR struct tiva_ethmac_s *priv)
if (dev->d_buf)
{
- /* Update TCP timing states and poll uIP for new XMIT data.
+ /* Update TCP timing states and poll the network for new XMIT data.
*/
(void)devif_timer(dev, tiva_txpoll);
@@ -2592,7 +2592,7 @@ static inline void tiva_txavail_process(FAR struct tiva_ethmac_s *priv)
if (priv->ifup)
{
- /* Poll uIP for new XMIT data */
+ /* Poll the network for new XMIT data */
tiva_dopoll(priv);
}
--
GitLab
From 4f208600aa366d99fcea96609146c101d09c2f13 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Mon, 30 May 2016 09:31:44 -0600
Subject: [PATCH 009/400] Replace confusing references to uIP with just 'the
network'
---
net/Kconfig | 2 +-
net/arp/arp.h | 2 +-
net/arp/arp_table.c | 2 +-
net/devif/devif.h | 4 ++--
net/devif/devif_poll.c | 8 ++++----
net/pkt/Kconfig | 6 +++---
net/route/net_foreachroute.c | 4 ++--
net/socket/net_close.c | 14 +++++++-------
net/socket/net_sendfile.c | 2 +-
net/socket/recvfrom.c | 4 ++--
net/tcp/tcp_accept.c | 4 ++--
net/tcp/tcp_callback.c | 2 +-
net/tcp/tcp_conn.c | 2 +-
net/tcp/tcp_input.c | 2 +-
net/tcp/tcp_send_unbuffered.c | 2 +-
net/udp/udp.h | 2 +-
net/udp/udp_conn.c | 2 +-
17 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/net/Kconfig b/net/Kconfig
index 6d98fc77dc..3f454f4288 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -44,7 +44,7 @@ config NET_MULTIBUFFER
bool "Use multiple device-side I/O buffers"
default n
---help---
- Traditionally, the uIP stacl has used a single buffer for all
+ Traditionally, the uIP-based stack has used a single buffer for all
incoming and outgoing traffic. If this configuration is selected,
then the driver can manage multiple I/O buffers and can, for
example, be filling one input buffer while sending another output
diff --git a/net/arp/arp.h b/net/arp/arp.h
index b32490b411..ba62f7893b 100644
--- a/net/arp/arp.h
+++ b/net/arp/arp.h
@@ -382,7 +382,7 @@ void arp_notify(in_addr_t ipaddr);
*
* Assumptions
* Interrupts are disabled; Returned value will become unstable when
- * interrupts are re-enabled or if any other uIP APIs are called.
+ * interrupts are re-enabled or if any other network APIs are called.
*
****************************************************************************/
diff --git a/net/arp/arp_table.c b/net/arp/arp_table.c
index bdb27ad79d..928ed59019 100644
--- a/net/arp/arp_table.c
+++ b/net/arp/arp_table.c
@@ -260,7 +260,7 @@ void arp_hdr_update(FAR uint16_t *pipaddr, FAR uint8_t *ethaddr)
*
* Assumptions
* Interrupts are disabled; Returned value will become unstable when
- * interrupts are re-enabled or if any other uIP APIs are called.
+ * interrupts are re-enabled or if any other network APIs are called.
*
****************************************************************************/
diff --git a/net/devif/devif.h b/net/devif/devif.h
index 2251ffcad0..bca0987896 100644
--- a/net/devif/devif.h
+++ b/net/devif/devif.h
@@ -426,8 +426,8 @@ uint16_t devif_dev_event(FAR struct net_driver_s *dev, void *pvconn,
* processing can send data.
*
* The amount of data that actually is sent out after a call to this
- * function is determined by the maximum amount of data TCP allows. uIP
- * will automatically crop the data so that only the appropriate
+ * function is determined by the maximum amount of data TCP allows. The
+ * network will automatically crop the data so that only the appropriate
* amount of data is sent. The mss field of the TCP connection structure
* can be used to determine the amount of data that actually will be sent.
*
diff --git a/net/devif/devif_poll.c b/net/devif/devif_poll.c
index 3ec68be4f3..928b779fb3 100644
--- a/net/devif/devif_poll.c
+++ b/net/devif/devif_poll.c
@@ -296,7 +296,7 @@ static inline int devif_poll_tcp_timer(FAR struct net_driver_s *dev,
* Function: devif_poll
*
* Description:
- * This function will traverse each active uIP connection structure and
+ * This function will traverse each active network connection structure and
* will perform network polling operations. devif_poll() may be called
* asynchronously with the network driver can accept another outgoing
* packet.
@@ -307,7 +307,7 @@ static inline int devif_poll_tcp_timer(FAR struct net_driver_s *dev,
* should do only if it cannot accept further write data).
*
* When the callback function is called, there may be an outbound packet
- * waiting for service in the uIP packet buffer, and if so the d_len field
+ * waiting for service in the device packet buffer, and if so the d_len field
* is set to a value larger than zero. The device driver should then send
* out the packet.
*
@@ -400,7 +400,7 @@ int devif_poll(FAR struct net_driver_s *dev, devif_poll_callback_t callback)
* Function: devif_timer
*
* Description:
- * These function will traverse each active uIP connection structure and
+ * These function will traverse each active network connection structure and
* perform network timer operations. The Ethernet driver MUST implement
* logic to periodically call devif_timer().
*
@@ -410,7 +410,7 @@ int devif_poll(FAR struct net_driver_s *dev, devif_poll_callback_t callback)
* should do only if it cannot accept further write data).
*
* When the callback function is called, there may be an outbound packet
- * waiting for service in the uIP packet buffer, and if so the d_len field
+ * waiting for service in the device packet buffer, and if so the d_len field
* is set to a value larger than zero. The device driver should then send
* out the packet.
*
diff --git a/net/pkt/Kconfig b/net/pkt/Kconfig
index 2fc26442dd..ae9c7891f5 100644
--- a/net/pkt/Kconfig
+++ b/net/pkt/Kconfig
@@ -13,9 +13,9 @@ config NET_PKT
Packet sockets allow receiving and transmitting frames without
a transport protocol in between. Frames received are copied into
- a packet socket tap before they enter uIP. Data written into a
- packet socket will bypass uIP altogether and be placed in the
- transmission buffer of the network interface driver.
+ a packet socket tap before they enter the network. Data written into
+ a packet socket will bypass the network altogether and be placed in
+ the transmission buffer of the network interface driver.
if NET_PKT
diff --git a/net/route/net_foreachroute.c b/net/route/net_foreachroute.c
index 13c154f539..1c5789dd64 100644
--- a/net/route/net_foreachroute.c
+++ b/net/route/net_foreachroute.c
@@ -91,7 +91,7 @@ int net_foreachroute(route_handler_t handler, FAR void *arg)
ret = handler(route, arg);
}
- /* Unlock uIP */
+ /* Unlock the network */
net_unlock(save);
return ret;
@@ -122,7 +122,7 @@ int net_foreachroute_ipv6(route_handler_ipv6_t handler, FAR void *arg)
ret = handler(route, arg);
}
- /* Unlock uIP */
+ /* Unlock the network */
net_unlock(save);
return ret;
diff --git a/net/socket/net_close.c b/net/socket/net_close.c
index f439811b85..f03a9caeea 100644
--- a/net/socket/net_close.c
+++ b/net/socket/net_close.c
@@ -136,10 +136,10 @@ static inline int close_timeout(FAR struct tcp_close_s *pstate)
* Function: netclose_interrupt
*
* Description:
- * Handle uIP callback events.
+ * Handle network callback events.
*
* Parameters:
- * conn - uIP TCP connection structure
+ * conn - TCP connection structure
*
* Returned Value:
* None
@@ -320,7 +320,7 @@ static inline void netclose_txnotify(FAR struct socket *psock,
* Break any current TCP connection
*
* Parameters:
- * conn - uIP TCP connection structure
+ * conn - TCP connection structure
*
* Returned Value:
* None
@@ -428,7 +428,7 @@ static inline int netclose_disconnect(FAR struct socket *psock)
/* Free the connection */
conn->crefs = 0; /* No more references on the connection */
- tcp_free(conn); /* Free uIP resources */
+ tcp_free(conn); /* Free network resources */
/* Get the result of the close */
@@ -517,7 +517,7 @@ int psock_close(FAR struct socket *psock)
goto errout;
}
- /* We perform the uIP close operation only if this is the last count on
+ /* We perform the close operation only if this is the last count on
* the socket. (actually, I think the socket crefs only takes the values
* 0 and 1 right now).
*
@@ -527,7 +527,7 @@ int psock_close(FAR struct socket *psock)
if (psock->s_crefs <= 1 && psock->s_conn != NULL)
{
- /* Perform uIP side of the close depending on the protocol type */
+ /* Perform local side of the close depending on the protocol type */
switch (psock->s_type)
{
@@ -649,7 +649,7 @@ int psock_close(FAR struct socket *psock)
/* Yes... free the connection structure */
conn->crefs = 0; /* No more references on the connection */
- pkt_free(psock->s_conn); /* Free uIP resources */
+ pkt_free(psock->s_conn); /* Free network resources */
}
else
{
diff --git a/net/socket/net_sendfile.c b/net/socket/net_sendfile.c
index a8b7b9f162..d5fde26023 100644
--- a/net/socket/net_sendfile.c
+++ b/net/socket/net_sendfile.c
@@ -402,7 +402,7 @@ static uint16_t sendfile_interrupt(FAR struct net_driver_s *dev, FAR void *pvcon
dev->d_sndlen = sndlen;
- /* Set the sequence number for this packet. NOTE: uIP updates
+ /* Set the sequence number for this packet. NOTE: The network updates
* sndseq on recept of ACK *before* this function is called. In that
* case sndseq will point to the next unacknowledge byte (which might
* have already been sent). We will overwrite the value of sndseq
diff --git a/net/socket/recvfrom.c b/net/socket/recvfrom.c
index 0125975393..9bc234f541 100644
--- a/net/socket/recvfrom.c
+++ b/net/socket/recvfrom.c
@@ -1692,8 +1692,8 @@ static ssize_t tcp_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len,
}
}
- /* In general, this uIP-based implementation will not support non-blocking
- * socket operations... except in a few cases: Here for TCP receive with read-ahead
+ /* In general, this implementation will not support non-blocking socket
+ * operations... except in a few cases: Here for TCP receive with read-ahead
* enabled. If this socket is configured as non-blocking then return EAGAIN
* if no data was obtained from the read-ahead buffers.
*/
diff --git a/net/tcp/tcp_accept.c b/net/tcp/tcp_accept.c
index a37db211db..ced4f0d659 100644
--- a/net/tcp/tcp_accept.c
+++ b/net/tcp/tcp_accept.c
@@ -250,8 +250,8 @@ int psock_tcp_accept(FAR struct socket *psock, FAR struct sockaddr *addr,
accept_tcpsender(psock, state.acpt_newconn, addr, addrlen);
}
- /* In general, this uIP-based implementation will not support non-blocking
- * socket operations... except in a few cases: Here for TCP accept with
+ /* In general, this implementation will not support non-blocking socket
+ * operations... except in a few cases: Here for TCP accept with
* backlog enabled. If this socket is configured as non-blocking then
* return EAGAIN if there is no pending connection in the backlog.
*/
diff --git a/net/tcp/tcp_callback.c b/net/tcp/tcp_callback.c
index 73c6175fee..ac43091923 100644
--- a/net/tcp/tcp_callback.c
+++ b/net/tcp/tcp_callback.c
@@ -147,7 +147,7 @@ uint16_t tcp_callback(FAR struct net_driver_s *dev,
FAR struct tcp_conn_s *conn, uint16_t flags)
{
/* Preserve the TCP_ACKDATA, TCP_CLOSE, and TCP_ABORT in the response.
- * These is needed by uIP to handle responses and buffer state. The
+ * These is needed by the network to handle responses and buffer state. The
* TCP_NEWDATA indication will trigger the ACK response, but must be
* explicitly set in the callback.
*/
diff --git a/net/tcp/tcp_conn.c b/net/tcp/tcp_conn.c
index 6cc9950fc0..efc6527cc5 100644
--- a/net/tcp/tcp_conn.c
+++ b/net/tcp/tcp_conn.c
@@ -73,7 +73,7 @@
* Private Data
****************************************************************************/
-/* The array containing all uIP TCP connections. */
+/* The array containing all TCP connections. */
static struct tcp_conn_s g_tcp_connections[CONFIG_NET_TCP_CONNS];
diff --git a/net/tcp/tcp_input.c b/net/tcp/tcp_input.c
index 97bcb402fd..19c207f655 100644
--- a/net/tcp/tcp_input.c
+++ b/net/tcp/tcp_input.c
@@ -376,7 +376,7 @@ found:
ackseq = tcp_getsequence(tcp->ackno);
/* Check how many of the outstanding bytes have been acknowledged. For
- * a most uIP send operation, this should always be true. However,
+ * most send operations, this should always be true. However,
* the send() API sends data ahead when it can without waiting for
* the ACK. In this case, the 'ackseq' could be less than then the
* new sequence number.
diff --git a/net/tcp/tcp_send_unbuffered.c b/net/tcp/tcp_send_unbuffered.c
index 6d5c608ba3..53365e3f68 100644
--- a/net/tcp/tcp_send_unbuffered.c
+++ b/net/tcp/tcp_send_unbuffered.c
@@ -518,7 +518,7 @@ static uint16_t tcpsend_interrupt(FAR struct net_driver_s *dev,
if ((pstate->snd_sent - pstate->snd_acked + sndlen) < conn->winsize)
{
- /* Set the sequence number for this packet. NOTE: uIP updates
+ /* Set the sequence number for this packet. NOTE: The network updates
* sndseq on receipt of ACK *before* this function is called. In that
* case sndseq will point to the next unacknowledged byte (which might
* have already been sent). We will overwrite the value of sndseq
diff --git a/net/udp/udp.h b/net/udp/udp.h
index 91447d2596..f8584bff0b 100644
--- a/net/udp/udp.h
+++ b/net/udp/udp.h
@@ -74,7 +74,7 @@
* Public Type Definitions
****************************************************************************/
-/* Representation of a uIP UDP connection */
+/* Representation of a UDP connection */
struct devif_callback_s; /* Forward reference */
struct udp_hdr_s; /* Forward reference */
diff --git a/net/udp/udp_conn.c b/net/udp/udp_conn.c
index ddd599382e..1f5ecd095c 100644
--- a/net/udp/udp_conn.c
+++ b/net/udp/udp_conn.c
@@ -76,7 +76,7 @@
* Private Data
****************************************************************************/
-/* The array containing all uIP UDP connections. */
+/* The array containing all UDP connections. */
struct udp_conn_s g_udp_connections[CONFIG_NET_UDP_CONNS];
--
GitLab
From 44353f320c9dec87097e0aa677d239607b3b7264 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Mon, 30 May 2016 09:37:34 -0600
Subject: [PATCH 010/400] Replace confusing references to uIP with just 'the
network'
---
drivers/net/cs89x0.c | 12 +++++------
drivers/net/dm90x0.c | 16 +++++++--------
drivers/net/e1000.c | 10 ++++-----
drivers/net/enc28j60.c | 38 +++++++++++++++++-----------------
drivers/net/encx24j600.c | 44 ++++++++++++++++++++--------------------
drivers/net/ftmac100.c | 14 ++++++-------
drivers/net/loopback.c | 4 ++--
drivers/net/slip.c | 12 +++++------
drivers/net/tun.c | 12 +++++------
9 files changed, 81 insertions(+), 81 deletions(-)
diff --git a/drivers/net/cs89x0.c b/drivers/net/cs89x0.c
index dfaf2d6384..be6a890d1b 100644
--- a/drivers/net/cs89x0.c
+++ b/drivers/net/cs89x0.c
@@ -314,7 +314,7 @@ static int cs89x0_transmit(struct cs89x0_driver_s *cs89x0)
* Function: cs89x0_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -436,7 +436,7 @@ static void cs89x0_receive(FAR struct cs89x0_driver_s *cs89x0, uint16_t isq)
return;
}
- /* Check if the packet is a valid size for the uIP buffer configuration */
+ /* Check if the packet is a valid size for the network buffer configuration */
if (rxlength > ???)
{
@@ -618,7 +618,7 @@ static void cs89x0_txdone(struct cs89x0_driver_s *cs89x0, uint16_t isq)
wd_cancel(cs89x0->cs_txtimeout);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&cs89x0->cs_dev, cs89x0_txpoll);
}
@@ -759,7 +759,7 @@ static void cs89x0_txtimeout(int argc, uint32_t arg, ...)
/* Then reset the hardware */
#warning "Missing logic"
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&cs89x0->cs_dev, cs89x0_txpoll);
}
@@ -788,7 +788,7 @@ static void cs89x0_polltimer(int argc, uint32_t arg, ...)
/* Check if there is room in the send another TXr packet. */
#warning "Missing logic"
- /* If so, update TCP timing states and poll uIP for new XMIT data */
+ /* If so, update TCP timing states and poll the network for new XMIT data */
(void)devif_timer(&cs89x0->cs_dev, cs89x0_txpoll);
@@ -909,7 +909,7 @@ static int cs89x0_txavail(struct net_driver_s *dev)
/* Check if there is room in the hardware to hold another outgoing packet. */
#warning "Missing logic"
- /* If so, then poll uIP for new XMIT data */
+ /* If so, then poll the network for new XMIT data */
(void)devif_poll(&cs89x0->cs_dev, cs89x0_txpoll);
}
diff --git a/drivers/net/dm90x0.c b/drivers/net/dm90x0.c
index caaf0c1872..c1807b5303 100644
--- a/drivers/net/dm90x0.c
+++ b/drivers/net/dm90x0.c
@@ -309,7 +309,7 @@ struct dm9x_driver_s
void (*dm_write)(const uint8_t *ptr, int len);
void (*dm_discard)(int len);
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
struct net_driver_s dm_dev;
};
@@ -737,7 +737,7 @@ static int dm9x_transmit(struct dm9x_driver_s *dm9x)
* Function: dm9x_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -873,7 +873,7 @@ static void dm9x_receive(FAR struct dm9x_driver_s *dm9x)
dm9x->dm_discard(rx.desc.rx_len);
}
- /* Also check if the packet is a valid size for the uIP configuration */
+ /* Also check if the packet is a valid size for the network configuration */
else if (rx.desc.rx_len < ETH_HDRLEN || rx.desc.rx_len > (CONFIG_NET_ETH_MTU + 2))
{
@@ -886,7 +886,7 @@ static void dm9x_receive(FAR struct dm9x_driver_s *dm9x)
}
else
{
- /* Good packet... Copy the packet data out of SRAM and pass it one to uIP */
+ /* Good packet... Copy the packet data out of SRAM and pass it one to the network */
dm9x->dm_dev.d_len = rx.desc.rx_len;
dm9x->dm_read(dm9x->dm_dev.d_buf, rx.desc.rx_len);
@@ -1065,7 +1065,7 @@ static void dm9x_txdone(struct dm9x_driver_s *dm9x)
wd_cancel(dm9x->dm_txtimeout);
}
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&dm9x->dm_dev, dm9x_txpoll);
}
@@ -1222,7 +1222,7 @@ static void dm9x_txtimeout(int argc, uint32_t arg, ...)
dm9x_reset(dm9x);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&dm9x->dm_dev, dm9x_txpoll);
}
@@ -1264,7 +1264,7 @@ static void dm9x_polltimer(int argc, uint32_t arg, ...)
if (dm9x->dm_ntxpending < 1 || (dm9x->dm_b100M && dm9x->dm_ntxpending < 2))
{
- /* If so, update TCP timing states and poll uIP for new XMIT data */
+ /* If so, update TCP timing states and poll the network for new XMIT data */
(void)devif_timer(&dm9x->dm_dev, dm9x_txpoll);
}
@@ -1470,7 +1470,7 @@ static int dm9x_txavail(struct net_driver_s *dev)
if (dm9x->dm_ntxpending < 1 || (dm9x->dm_b100M && dm9x->dm_ntxpending < 2))
{
- /* If so, then poll uIP for new XMIT data */
+ /* If so, then poll the network for new XMIT data */
(void)devif_poll(&dm9x->dm_dev, dm9x_txpoll);
}
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 11a4452989..e7f3e2385c 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -127,7 +127,7 @@ struct e1000_dev
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
struct net_driver_s netdev; /* Interface understood by networking layer */
};
@@ -462,7 +462,7 @@ static int e1000_transmit(struct e1000_dev *e1000)
* Function: e1000_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -570,7 +570,7 @@ static void e1000_receive(struct e1000_dev *e1000)
goto next;
}
- /* Check if the packet is a valid size for the uIP buffer configuration */
+ /* Check if the packet is a valid size for the network buffer configuration */
/* get the number of actual data-bytes in this packet */
@@ -728,7 +728,7 @@ static void e1000_txtimeout(int argc, uint32_t arg, ...)
e1000_init(e1000);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&e1000->netdev, e1000_txpoll);
}
@@ -765,7 +765,7 @@ static void e1000_polltimer(int argc, uint32_t arg, ...)
return;
}
- /* If so, update TCP timing states and poll uIP for new XMIT data. Hmmm..
+ /* If so, update TCP timing states and poll the network for new XMIT data. Hmmm..
* might be bug here. Does this mean if there is a transmit in progress,
* we will missing TCP time state updates?
*/
diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c
index 2ae3a01ebd..df1fe7db47 100644
--- a/drivers/net/enc28j60.c
+++ b/drivers/net/enc28j60.c
@@ -252,9 +252,9 @@ struct enc_driver_s
FAR struct spi_dev_s *spi;
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
};
/****************************************************************************
@@ -1154,7 +1154,7 @@ static int enc_transmit(FAR struct enc_driver_s *priv)
* Function: enc_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
+ * The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -1168,7 +1168,7 @@ static int enc_transmit(FAR struct enc_driver_s *priv)
* OK on success; a negated errno on failure
*
* Assumptions:
- * Interrupts are enabled but the caller holds the uIP lock.
+ * Interrupts are enabled but the caller holds the network lock.
*
****************************************************************************/
@@ -1261,7 +1261,7 @@ static void enc_linkstatus(FAR struct enc_driver_s *priv)
* None
*
* Assumptions:
- * Interrupts are enabled but the caller holds the uIP lock.
+ * Interrupts are enabled but the caller holds the network lock.
*
****************************************************************************/
@@ -1288,7 +1288,7 @@ static void enc_txif(FAR struct enc_driver_s *priv)
(void)wd_start(priv->txpoll, ENC_WDDELAY, enc_polltimer, 1,
(wdparm_t)priv);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&priv->dev, enc_txpoll);
}
@@ -1362,7 +1362,7 @@ static void enc_rxerif(FAR struct enc_driver_s *priv)
* Function: enc_rxdispatch
*
* Description:
- * Give the newly received packet to uIP.
+ * Give the newly received packet to the network.
*
* Parameters:
* priv - Reference to the driver state structure
@@ -1371,7 +1371,7 @@ static void enc_rxerif(FAR struct enc_driver_s *priv)
* None
*
* Assumptions:
- * Interrupts are enabled but the caller holds the uIP lock.
+ * Interrupts are enabled but the caller holds the network lock.
*
****************************************************************************/
@@ -1502,7 +1502,7 @@ static void enc_rxdispatch(FAR struct enc_driver_s *priv)
* None
*
* Assumptions:
- * Interrupts are enabled but the caller holds the uIP lock.
+ * Interrupts are enabled but the caller holds the network lock.
*
****************************************************************************/
@@ -1578,7 +1578,7 @@ static void enc_pktif(FAR struct enc_driver_s *priv)
enc_rdbuffer(priv, priv->dev.d_buf, priv->dev.d_len);
enc_dumppacket("Received Packet", priv->dev.d_buf, priv->dev.d_len);
- /* Dispatch the packet to uIP */
+ /* Dispatch the packet to the network */
enc_rxdispatch(priv);
}
@@ -1620,7 +1620,7 @@ static void enc_irqworker(FAR void *arg)
DEBUGASSERT(priv);
- /* Get exclusive access to both uIP and the SPI bus. */
+ /* Get exclusive access to both the network and the SPI bus. */
lock = net_lock();
enc_lock(priv);
@@ -1810,7 +1810,7 @@ static void enc_irqworker(FAR void *arg)
enc_bfsgreg(priv, ENC_EIE, EIE_INTIE);
- /* Release lock on the SPI bus and uIP */
+ /* Release lock on the SPI bus and the network */
enc_unlock(priv);
net_unlock(lock);
@@ -1881,7 +1881,7 @@ static void enc_toworker(FAR void *arg)
nlldbg("Tx timeout\n");
DEBUGASSERT(priv);
- /* Get exclusive access to uIP */
+ /* Get exclusive access to the network */
lock = net_lock();
@@ -1899,11 +1899,11 @@ static void enc_toworker(FAR void *arg)
DEBUGASSERT(ret == OK);
UNUSED(ret);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&priv->dev, enc_txpoll);
- /* Release lock on uIP */
+ /* Release lock on the network */
net_unlock(lock);
}
@@ -1973,7 +1973,7 @@ static void enc_pollworker(FAR void *arg)
DEBUGASSERT(priv);
- /* Get exclusive access to both uIP and the SPI bus. */
+ /* Get exclusive access to both the network and the SPI bus. */
lock = net_lock();
enc_lock(priv);
@@ -1986,7 +1986,7 @@ static void enc_pollworker(FAR void *arg)
if ((enc_rdgreg(priv, ENC_ECON1) & ECON1_TXRTS) == 0)
{
- /* Yes.. update TCP timing states and poll uIP for new XMIT data. Hmmm..
+ /* Yes.. update TCP timing states and poll the network for new XMIT data. Hmmm..
* looks like a bug here to me. Does this mean if there is a transmit
* in progress, we will missing TCP time state updates?
*/
@@ -1994,7 +1994,7 @@ static void enc_pollworker(FAR void *arg)
(void)devif_timer(&priv->dev, enc_txpoll);
}
- /* Release lock on the SPI bus and uIP */
+ /* Release lock on the SPI bus and the network */
enc_unlock(priv);
net_unlock(lock);
@@ -2212,7 +2212,7 @@ static int enc_txavail(struct net_driver_s *dev)
if ((enc_rdgreg(priv, ENC_ECON1) & ECON1_TXRTS) == 0)
{
- /* The interface is up and TX is idle; poll uIP for new XMIT data */
+ /* The interface is up and TX is idle; poll the network for new XMIT data */
(void)devif_poll(&priv->dev, enc_txpoll);
}
diff --git a/drivers/net/encx24j600.c b/drivers/net/encx24j600.c
index aae63dcebb..c341c5486f 100644
--- a/drivers/net/encx24j600.c
+++ b/drivers/net/encx24j600.c
@@ -265,9 +265,9 @@ struct enc_driver_s
FAR struct spi_dev_s *spi;
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
};
/****************************************************************************
@@ -1081,7 +1081,7 @@ static int enc_transmit(FAR struct enc_driver_s *priv)
*
* Assumptions:
* A packet is available in d_buf.
- * Interrupts are enabled but the caller holds the uIP lock.
+ * Interrupts are enabled but the caller holds the network lock.
*
****************************************************************************/
@@ -1138,7 +1138,7 @@ static int enc_txenqueue(FAR struct enc_driver_s *priv)
* Function: enc_txpoll
*
* Description:
- * Enqueues uIP packets if available.
+ * Enqueues network packets if available.
* This is a callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
@@ -1152,7 +1152,7 @@ static int enc_txenqueue(FAR struct enc_driver_s *priv)
* OK on success; a negated errno on failure
*
* Assumptions:
- * Interrupts are enabled but the caller holds the uIP lock.
+ * Interrupts are enabled but the caller holds the network lock.
*
****************************************************************************/
@@ -1273,7 +1273,7 @@ static void enc_linkstatus(FAR struct enc_driver_s *priv)
* None
*
* Assumptions:
- * Interrupts are enabled but the caller holds the uIP lock.
+ * Interrupts are enabled but the caller holds the network lock.
*
****************************************************************************/
@@ -1322,7 +1322,7 @@ static void enc_txif(FAR struct enc_driver_s *priv)
* None
*
* Assumptions:
- * Interrupts are enabled but the caller holds the uIP lock.
+ * Interrupts are enabled but the caller holds the network lock.
*
****************************************************************************/
@@ -1362,7 +1362,7 @@ static void enc_rxldpkt(FAR struct enc_driver_s *priv,
* A free rx descriptor
*
* Assumptions:
- * Interrupts are enabled but the caller holds the uIP lock.
+ * Interrupts are enabled but the caller holds the network lock.
*
****************************************************************************/
@@ -1395,7 +1395,7 @@ static struct enc_descr_s *enc_rxgetdescr(FAR struct enc_driver_s *priv)
* None
*
* Assumptions:
- * Interrupts are enabled but the caller holds the uIP lock.
+ * Interrupts are enabled but the caller holds the network lock.
*
****************************************************************************/
@@ -1443,7 +1443,7 @@ static void enc_rxrmpkt(FAR struct enc_driver_s *priv, FAR struct enc_descr_s *d
* Function: enc_rxdispatch
*
* Description:
- * Give the newly received packet to uIP.
+ * Give the newly received packet to the network.
*
* Parameters:
* priv - Reference to the driver state structure
@@ -1452,7 +1452,7 @@ static void enc_rxrmpkt(FAR struct enc_driver_s *priv, FAR struct enc_descr_s *d
* None
*
* Assumptions:
- * Interrupts are enabled but the caller holds the uIP lock.
+ * Interrupts are enabled but the caller holds the network lock.
*
****************************************************************************/
@@ -1633,7 +1633,7 @@ static void enc_rxdispatch(FAR struct enc_driver_s *priv)
* None
*
* Assumptions:
- * Interrupts are enabled but the caller holds the uIP lock.
+ * Interrupts are enabled but the caller holds the network lock.
*
****************************************************************************/
@@ -1763,7 +1763,7 @@ static void enc_pktif(FAR struct enc_driver_s *priv)
* None
*
* Assumptions:
- * Interrupts are enabled but the caller holds the uIP lock.
+ * Interrupts are enabled but the caller holds the network lock.
*
****************************************************************************/
@@ -1832,7 +1832,7 @@ static void enc_irqworker(FAR void *arg)
DEBUGASSERT(priv);
- /* Get exclusive access to both uIP and the SPI bus. */
+ /* Get exclusive access to both the network and the SPI bus. */
lock = net_lock();
enc_lock(priv);
@@ -1975,7 +1975,7 @@ static void enc_irqworker(FAR void *arg)
enc_bfs(priv, ENC_EIE, EIE_INTIE);
- /* Release lock on the SPI bus and uIP */
+ /* Release lock on the SPI bus and the network */
enc_unlock(priv);
net_unlock(lock);
@@ -2046,7 +2046,7 @@ static void enc_toworker(FAR void *arg)
nlldbg("Tx timeout\n");
DEBUGASSERT(priv);
- /* Get exclusive access to uIP. */
+ /* Get exclusive access to the network. */
lock = net_lock();
@@ -2064,11 +2064,11 @@ static void enc_toworker(FAR void *arg)
DEBUGASSERT(ret == OK);
(void)ret;
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&priv->dev, enc_txpoll);
- /* Release uIP */
+ /* Release the network */
net_unlock(lock);
}
@@ -2138,7 +2138,7 @@ static void enc_pollworker(FAR void *arg)
DEBUGASSERT(priv);
- /* Get exclusive access to both uIP and the SPI bus. */
+ /* Get exclusive access to both the network and the SPI bus. */
lock = net_lock();
enc_lock(priv);
@@ -2151,7 +2151,7 @@ static void enc_pollworker(FAR void *arg)
if ((enc_rdreg(priv, ENC_ECON1) & ECON1_TXRTS) == 0)
{
- /* Yes.. update TCP timing states and poll uIP for new XMIT data. Hmmm..
+ /* Yes.. update TCP timing states and poll the network for new XMIT data. Hmmm..
* looks like a bug here to me. Does this mean if there is a transmit
* in progress, we will missing TCP time state updates?
*/
@@ -2159,7 +2159,7 @@ static void enc_pollworker(FAR void *arg)
(void)devif_timer(&priv->dev, enc_txpoll);
}
- /* Release lock on the SPI bus and uIP */
+ /* Release lock on the SPI bus and the network */
enc_unlock(priv);
net_unlock(lock);
@@ -2381,7 +2381,7 @@ static int enc_txavail(struct net_driver_s *dev)
if ((enc_rdreg(priv, ENC_ECON1) & ECON1_TXRTS) == 0)
{
- /* The interface is up and TX is idle; poll uIP for new XMIT data */
+ /* The interface is up and TX is idle; poll the network for new XMIT data */
(void)devif_poll(&priv->dev, enc_txpoll);
}
diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c
index fdf23a87e1..9cbdba7022 100644
--- a/drivers/net/ftmac100.c
+++ b/drivers/net/ftmac100.c
@@ -171,9 +171,9 @@ struct ftmac100_driver_s
struct work_s ft_work; /* For deferring work to the work queue */
#endif
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s ft_dev; /* Interface understood by uIP */
+ struct net_driver_s ft_dev; /* Interface understood by the network */
};
/****************************************************************************
@@ -331,7 +331,7 @@ static int ftmac100_transmit(FAR struct ftmac100_driver_s *priv)
* Function: ftmac100_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets
+ * The transmitter is available, check if the network has any outgoing packets
* ready to send. This is a callback from devif_poll(). devif_poll() may
* be called:
*
@@ -849,7 +849,7 @@ static void ftmac100_txdone(FAR struct ftmac100_driver_s *priv)
(void)wd_start(priv->ft_txpoll, FTMAC100_WDDELAY, ftmac100_poll_expiry, 1,
(wdparm_t)priv);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&priv->ft_dev, ftmac100_txpoll);
}
@@ -1089,7 +1089,7 @@ static inline void ftmac100_txtimeout_process(FAR struct ftmac100_driver_s *priv
nvdbg("TXTIMEOUT\n");
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&priv->ft_dev, ftmac100_txpoll);
}
@@ -1195,7 +1195,7 @@ static inline void ftmac100_poll_process(FAR struct ftmac100_driver_s *priv)
* the TX poll if he are unable to accept another packet for transmission.
*/
- /* If so, update TCP timing states and poll uIP for new XMIT data. Hmmm..
+ /* If so, update TCP timing states and poll the network for new XMIT data. Hmmm..
* might be bug here. Does this mean if there is a transmit in progress,
* we will missing TCP time state updates?
*/
@@ -1421,7 +1421,7 @@ static inline void ftmac100_txavail_process(FAR struct ftmac100_driver_s *priv)
{
/* Check if there is room in the hardware to hold another outgoing packet. */
- /* If so, then poll uIP for new XMIT data */
+ /* If so, then poll the network for new XMIT data */
(void)devif_poll(&priv->ft_dev, ftmac100_txpoll);
}
diff --git a/drivers/net/loopback.c b/drivers/net/loopback.c
index 3b750b8051..5b275474d0 100644
--- a/drivers/net/loopback.c
+++ b/drivers/net/loopback.c
@@ -99,9 +99,9 @@ struct lo_driver_s
WDOG_ID lo_polldog; /* TX poll timer */
struct work_s lo_work; /* For deferring work to the work queue */
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s lo_dev; /* Interface understood by uIP */
+ struct net_driver_s lo_dev; /* Interface understood by the network */
};
/****************************************************************************
diff --git a/drivers/net/slip.c b/drivers/net/slip.c
index c02ebb0e93..3691580341 100644
--- a/drivers/net/slip.c
+++ b/drivers/net/slip.c
@@ -146,11 +146,11 @@ struct slip_driver_s
uint16_t rxlen; /* The number of bytes in rxbuf */
pid_t rxpid; /* Receiver thread ID */
pid_t txpid; /* Transmitter thread ID */
- sem_t waitsem; /* Mutually exclusive access to uIP */
+ sem_t waitsem; /* Mutually exclusive access to the network */
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
uint8_t rxbuf[CONFIG_NET_SLIP_MTU + 2];
uint8_t txbuf[CONFIG_NET_SLIP_MTU + 2];
};
@@ -378,7 +378,7 @@ static int slip_transmit(FAR struct slip_driver_s *priv)
* Function: slip_txpoll
*
* Description:
- * Check if uIP has any outgoing packets ready to send. This is a
+ * Check if the network has any outgoing packets ready to send. This is a
* callback from devif_poll(). devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete, or
@@ -471,7 +471,7 @@ static void slip_txtask(int argc, FAR char *argv[])
if (priv->bifup)
{
- /* Get exclusive access to uIP (if it it is already being used
+ /* Get exclusive access to the network (if it it is already being used
* slip_rxtask, then we have to wait).
*/
@@ -725,7 +725,7 @@ static int slip_rxtask(int argc, FAR char *argv[])
{
NETDEV_RXIPV4(&priv->dev);
- /* Handle the IP input. Get exclusive access to uIP. */
+ /* Handle the IP input. Get exclusive access to the network. */
slip_semtake(priv);
priv->dev.d_buf = priv->rxbuf;
diff --git a/drivers/net/tun.c b/drivers/net/tun.c
index 1221b56ad8..9435f4a617 100644
--- a/drivers/net/tun.c
+++ b/drivers/net/tun.c
@@ -129,9 +129,9 @@ struct tun_device_s
sem_t waitsem;
sem_t read_wait_sem;
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
};
struct tun_driver_s
@@ -345,7 +345,7 @@ static int tun_transmit(FAR struct tun_device_s *priv)
* Function: tun_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets
+ * The transmitter is available, check if the network has any outgoing packets
* ready to send. This is a callback from devif_poll(). devif_poll() may
* be called:
*
@@ -498,7 +498,7 @@ static void tun_txdone(FAR struct tun_device_s *priv)
NETDEV_TXDONE(&priv->dev);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
priv->dev.d_buf = priv->read_buf;
(void)devif_poll(&priv->dev, tun_txpoll);
@@ -529,7 +529,7 @@ static void tun_poll_process(FAR struct tun_device_s *priv)
if (priv->read_d_len == 0)
{
- /* If so, poll uIP for new XMIT data. */
+ /* If so, poll the network for new XMIT data. */
priv->dev.d_buf = priv->read_buf;
(void)devif_timer(&priv->dev, tun_txpoll);
@@ -746,7 +746,7 @@ static int tun_txavail(struct net_driver_s *dev)
if (priv->bifup)
{
- /* Poll uIP for new XMIT data */
+ /* Poll the network for new XMIT data */
priv->dev.d_buf = priv->read_buf;
(void)devif_poll(&priv->dev, tun_txpoll);
--
GitLab
From 9b4cec922852511b4a0b41f4ced8b6841ac826ac Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Mon, 30 May 2016 09:51:15 -0600
Subject: [PATCH 011/400] Replace confusing references to uIP with just 'the
network'
---
include/netinet/arp.h | 6 +++---
include/nuttx/net/cs89x0.h | 4 ++--
include/nuttx/net/icmp.h | 2 +-
include/nuttx/net/icmpv6.h | 2 +-
include/nuttx/net/igmp.h | 2 +-
include/nuttx/net/ip.h | 2 +-
include/nuttx/net/net.h | 9 +++++----
include/nuttx/net/netconfig.h | 18 +++++++++---------
include/nuttx/net/netdev.h | 33 +++++++++++++++++----------------
include/nuttx/net/tcp.h | 8 ++++----
include/nuttx/net/udp.h | 8 ++++----
11 files changed, 48 insertions(+), 46 deletions(-)
diff --git a/include/netinet/arp.h b/include/netinet/arp.h
index caaa3e64b4..1ed14a6a67 100644
--- a/include/netinet/arp.h
+++ b/include/netinet/arp.h
@@ -102,9 +102,9 @@ extern "C"
****************************************************************************/
/* If CONFIG_NET_ARPIOCTLS is defined then the semi-standard ioctl commands
- * described above are supported. If not, you can call the uIP ARP interfaces
- * directly in a very non-standard way. See include/nuttx/net/arp.h for
- * prototypes.
+ * described above are supported. If not, you can call the network ARP
+ * interfaces directly in a very non-standard way. See
+ * include/nuttx/net/arp.h for prototypes.
*/
#undef EXTERN
diff --git a/include/nuttx/net/cs89x0.h b/include/nuttx/net/cs89x0.h
index 9d92a19311..5629a8f479 100644
--- a/include/nuttx/net/cs89x0.h
+++ b/include/nuttx/net/cs89x0.h
@@ -86,9 +86,9 @@ struct cs89x0_driver_s
uint32_t cs_txunderrun; /* Count of Tx underrun errors */
#endif
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s cs_dev; /* Interface understood by uIP */
+ struct net_driver_s cs_dev; /* Interface understood by the network */
};
/****************************************************************************
diff --git a/include/nuttx/net/icmp.h b/include/nuttx/net/icmp.h
index f64895afc4..875deaae42 100644
--- a/include/nuttx/net/icmp.h
+++ b/include/nuttx/net/icmp.h
@@ -1,6 +1,6 @@
/****************************************************************************
* include/nuttx/net/icmp.h
- * Header file for the uIP ICMP stack.
+ * Header file for the NuttX ICMP stack.
*
* Copyright (C) 2007-2009, 2012, 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/include/nuttx/net/icmpv6.h b/include/nuttx/net/icmpv6.h
index af17c4b95b..d303cfa848 100644
--- a/include/nuttx/net/icmpv6.h
+++ b/include/nuttx/net/icmpv6.h
@@ -1,6 +1,6 @@
/****************************************************************************
* include/nuttx/net/icmpv6.h
- * Header file for the uIP ICMPv6 stack.
+ * Header file for the NuttX ICMPv6 stack.
*
* Copyright (C) 2007-2009, 2012, 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/include/nuttx/net/igmp.h b/include/nuttx/net/igmp.h
index 68028daeea..d0620dbc7b 100644
--- a/include/nuttx/net/igmp.h
+++ b/include/nuttx/net/igmp.h
@@ -1,7 +1,7 @@
/****************************************************************************
* include/nuttx/net/igmp.h
* The definitions in this header file are intended only for internal use
- * by the NuttX port of the uIP stack.
+ * by the NuttX network stack.
*
* Copyright (C) 2010, 2012, 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/include/nuttx/net/ip.h b/include/nuttx/net/ip.h
index 6a494bd283..6a07edd585 100644
--- a/include/nuttx/net/ip.h
+++ b/include/nuttx/net/ip.h
@@ -1,7 +1,7 @@
/****************************************************************************
* include/nuttx/net/ip.h
*
- * The uIP header file contains IP-related definitions for a number of C
+ * This header file contains IP-related definitions for a number of C
* macros that are used by applications as well as internally by the
* OS networking logic.
*
diff --git a/include/nuttx/net/net.h b/include/nuttx/net/net.h
index e95c9e82a7..4fadfd2c8f 100644
--- a/include/nuttx/net/net.h
+++ b/include/nuttx/net/net.h
@@ -222,10 +222,11 @@ void net_initialize(void);
/****************************************************************************
* Critical section management. The NuttX configuration setting
- * CONFIG_NET_NOINTS indicates that uIP not called from the interrupt level.
- * If CONFIG_NET_NOINTS is defined, then these will map to semaphore
- * controls. Otherwise, it assumed that uIP will be called from interrupt
- * level handling and these will map to interrupt enable/disable controls.
+ * CONFIG_NET_NOINTS indicates that the network stack not called from the
+ * interrupt level. If CONFIG_NET_NOINTS is defined, then these will map
+ * to semaphore controls. Otherwise, it assumed that the stack will be
+ * called from interrupt level handling and these will map to interrupt
+ * enable/disable controls.
*
*
* If CONFIG_NET_NOINTS is defined, then semaphore based locking is used:
diff --git a/include/nuttx/net/netconfig.h b/include/nuttx/net/netconfig.h
index f65b1c478d..e00b75da91 100644
--- a/include/nuttx/net/netconfig.h
+++ b/include/nuttx/net/netconfig.h
@@ -1,10 +1,10 @@
/****************************************************************************
* include/nuttx/net/netconfig.h
- * Configuration options for NuttX uIP-based networking.
+ * Configuration options for NuttX networking.
*
- * This file is used for tweaking various configuration options for
- * uIP. This is most assuring the correct default values are provided and
- * that configured options are valid.
+ * This file is used for tweaking various configuration options for the
+ * network. This is most assuring the correct default values are provided
+ * and that configured options are valid.
*
* Note: Network configuration options the netconfig.h should not be changed,
* but rather the per-project defconfig file.
@@ -72,8 +72,8 @@
/* Layer 2 Configuration Options ********************************************/
-/* The default data link layer for uIP is Ethernet. If CONFIG_NET_SLIP is
- * defined in the NuttX header file, then SLIP will be supported. The basic
+/* The default data link laye is Ethernet. If CONFIG_NET_SLIP is defined in
+ * the NuttX header file, then SLIP will be supported. The basic
* differences between the SLIP and Ethernet configurations is that when SLIP
* is selected:
*
@@ -204,7 +204,7 @@
/* IP configuration options */
-/* The IP TTL (time to live) of IP packets sent by uIP.
+/* The IP TTL (time to live) of IP packets sent by the network stack.
*
* This should normally not be changed.
*/
@@ -494,7 +494,7 @@
#ifndef CONFIG_NET_ARPTAB_SIZE
/* The size of the ARP table.
*
- * This option should be set to a larger value if this uIP node will
+ * This option should be set to a larger value if this network node will
* have many connections from the local network.
*/
@@ -532,7 +532,7 @@
/* Statistics datatype
*
* This typedef defines the dataype used for keeping statistics in
- * uIP.
+ * the network.
*/
typedef uint16_t net_stats_t;
diff --git a/include/nuttx/net/netdev.h b/include/nuttx/net/netdev.h
index de6e997faf..7ef7cc62d7 100644
--- a/include/nuttx/net/netdev.h
+++ b/include/nuttx/net/netdev.h
@@ -1,6 +1,7 @@
/****************************************************************************
* include/nuttx/net/netdev.h
- * Defines architecture-specific device driver interfaces to the uIP network.
+ * Defines architecture-specific device driver interfaces to the NuttX
+ * network.
*
* Copyright (C) 2007, 2009, 2011-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -232,9 +233,9 @@ struct net_driver_s
* headers from this buffer. The size of the link level headers is
* configured by the NET_LL_HDRLEN(dev) define.
*
- * uIP will handle only a single buffer for both incoming and outgoing
- * packets. However, the drive design may be concurrently send and
- * filling separate, break-off buffers if CONFIG_NET_MULTIBUFFER is
+ * The network will handle only a single buffer for both incoming and
+ * outgoing packets. However, the driver design may be concurrently send
+ * and filling separate, break-off buffers if CONFIG_NET_MULTIBUFFER is
* defined. That buffer management must be controlled by the driver.
*/
@@ -266,7 +267,7 @@ struct net_driver_s
*
* Holds the length of the packet in the d_buf buffer.
*
- * When the network device driver calls the uIP input function,
+ * When the network device driver calls the network input function,
* d_len should be set to the length of the packet in the d_buf
* buffer.
*
@@ -353,10 +354,10 @@ typedef int (*devif_poll_callback_t)(FAR struct net_driver_s *dev);
****************************************************************************/
/****************************************************************************
- * uIP device driver functions
+ * Network device driver functions
*
* These functions are used by a network device driver for interacting
- * with uIP.
+ * with the NuttX network.
*
* Process an incoming IP packet.
*
@@ -383,9 +384,9 @@ typedef int (*devif_poll_callback_t)(FAR struct net_driver_s *dev);
* }
* }
*
- * Note: If you are writing a uIP device driver that needs ARP
- * (Address Resolution Protocol), e.g., when running uIP over
- * Ethernet, you will need to call the uIP ARP code before calling
+ * Note: If you are writing a network device driver that needs ARP
+ * (Address Resolution Protocol), e.g., when running the network over
+ * Ethernet, you will need to call the network ARP code before calling
* this function:
*
* #define BUF ((struct eth_hdr_s *)&dev->d_buf[0])
@@ -424,8 +425,8 @@ int ipv6_input(FAR struct net_driver_s *dev);
/****************************************************************************
* Polling of connections
*
- * These functions will traverse each active uIP connection structure and
- * perform appropriate operations: devif_timer() will perform TCP timer
+ * These functions will traverse each active network connection structure
+ * and perform appropriate operations: devif_timer() will perform TCP timer
* operations (and UDP polling operations); devif_poll() will perform TCP
* and UDP polling operations. The CAN driver MUST implement logic to
* periodically call devif_timer(); devif_poll() may be called asynchronously
@@ -437,7 +438,7 @@ int ipv6_input(FAR struct net_driver_s *dev);
* value (which it should do only if it cannot accept further write data).
*
* When the callback function is called, there may be an outbound packet
- * waiting for service in the uIP packet buffer, and if so the d_len field
+ * waiting for service in the device packet buffer, and if so the d_len field
* is set to a value larger than zero. The device driver should then send
* out the packet.
*
@@ -455,9 +456,9 @@ int ipv6_input(FAR struct net_driver_s *dev);
* ...
* devif_poll(dev, driver_callback);
*
- * Note: If you are writing a uIP device driver that needs ARP (Address
- * Resolution Protocol), e.g., when running uIP over Ethernet, you will
- * need to call the arp_out() function in the callback function
+ * Note: If you are writing a network device driver that needs ARP (Address
+ * Resolution Protocol), e.g., when running the networ over Ethernet, you
+ * will need to call the arp_out() function in the callback function
* before sending the packet:
*
* int driver_callback(FAR struct net_driver_s *dev)
diff --git a/include/nuttx/net/tcp.h b/include/nuttx/net/tcp.h
index 02dfa885cd..fd26d7ba5e 100644
--- a/include/nuttx/net/tcp.h
+++ b/include/nuttx/net/tcp.h
@@ -1,10 +1,10 @@
/****************************************************************************
* include/nuttx/net/tcp.h
- * Header file for the uIP TCP/IP stack.
+ * Header file for the NuttX TCP/IP stack.
*
- * The uIP TCP/IP stack header file contains definitions for a number
- * of C macros that are used by uIP programs as well as internal uIP
- * structures, TCP/IP header structures and function declarations.
+ * This TCP/IP stack header file contains definitions for a number of C
+ * macros that are used by internal network structures, TCP/IP header
+ * structures and function declarations.
*
* Copyright (C) 2007, 2009-2010, 2012-2014 Gregory Nutt. All rights
* reserved.
diff --git a/include/nuttx/net/udp.h b/include/nuttx/net/udp.h
index 24b47452f5..6d73cdae10 100644
--- a/include/nuttx/net/udp.h
+++ b/include/nuttx/net/udp.h
@@ -1,10 +1,10 @@
/****************************************************************************
* include/nuttx/net/udp.h
- * Header file for the uIP UDP stack.
+ * Header file for the NuttX UDP stack.
*
- * The uIP UDP stack header file contains definitions for a number
- * of C macros that are used by uIP programs as well as internal uIP
- * structures, UDP header structures and function declarations.
+ * The UDP stack header file contains definitions for a number of C macros
+ * that are used by the internal network structures, UDP header structures
+ * and function declarations.
*
* Copyright (C) 2007, 2009, 2012, 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
--
GitLab
From 50d640a102433d73b521f651c8b8057408a34653 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Mon, 30 May 2016 09:51:46 -0600
Subject: [PATCH 012/400] Typo fix
---
include/nuttx/net/arp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/nuttx/net/arp.h b/include/nuttx/net/arp.h
index 236053ce70..cf04895f76 100644
--- a/include/nuttx/net/arp.h
+++ b/include/nuttx/net/arp.h
@@ -5,7 +5,7 @@
* Copyright (C) 2007, 2009-2012, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
- * Derived from uIP with has a similar BSD-styple license:
+ * Derived from uIP with has a similar BSD-style license:
*
* Author: Adam Dunkels
* Copyright (c) 2001-2003, Adam Dunkels.
--
GitLab
From 5ef3e3e2158c8c65c1d76feaa5e62a60ad4dd8d3 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Mon, 30 May 2016 11:52:07 -0600
Subject: [PATCH 013/400] Replace confusing references to uIP with just 'the
network'
---
COPYING | 2 +-
Documentation/NuttxPortingGuide.html | 3 +-
Documentation/NuttxUserGuide.html | 5 +-
arch/README.txt | 211 ++++++------------
arch/hc/src/m9s12/m9s12_ethernet.c | 19 +-
arch/mips/src/pic32mx/pic32mx-ethernet.c | 25 ++-
arch/mips/src/pic32mz/pic32mz-ethernet.c | 25 ++-
arch/z80/src/ez80/ez80_emac.c | 19 +-
configs/dk-tm4c129x/src/tm4c_ethernet.c | 2 +-
configs/eagle100/src/lm_ethernet.c | 2 +-
configs/ekk-lm3s9b96/src/lm_ethernet.c | 2 +-
configs/lm3s6432-s2e/src/lm_ethernet.c | 2 +-
configs/lm3s6965-ek/src/lm_ethernet.c | 2 +-
configs/lm3s8962-ek/src/lm_ethernet.c | 2 +-
.../tm4c1294-launchpad/src/tm4c_ethernet.c | 2 +-
libc/netdb/lib_dnsquery.c | 4 +-
16 files changed, 127 insertions(+), 200 deletions(-)
diff --git a/COPYING b/COPYING
index 1c82d0ca20..a8113ab027 100644
--- a/COPYING
+++ b/COPYING
@@ -93,7 +93,7 @@ has a similar BSD style license:
IGMP
^^^^
-IGMP support, if enabled in uIP, adds additional logic by Steve Reynolds:
+IGMP support, if enabled, adds additional logic by Steve Reynolds:
Copyright (c) 2002 CITEL Technologies Ltd.
All rights reserved.
diff --git a/Documentation/NuttxPortingGuide.html b/Documentation/NuttxPortingGuide.html
index ff3990c9d9..9fc2e5e9e2 100644
--- a/Documentation/NuttxPortingGuide.html
+++ b/Documentation/NuttxPortingGuide.html
@@ -4901,8 +4901,7 @@ int kbd_decode(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *sta
include/nuttx/net/netdev.h
.
All structures and APIs needed to work with Ethernet drivers are provided in this header file.
- The structure struct net_driver_s
defines the interface and is passed to uIP via
- netdev_register()
.
+ The structure struct net_driver_s
defines the interface and is passed to the network via netdev_register()
.
diff --git a/Documentation/NuttxUserGuide.html b/Documentation/NuttxUserGuide.html
index a91959e198..3766eba646 100644
--- a/Documentation/NuttxUserGuide.html
+++ b/Documentation/NuttxUserGuide.html
@@ -8755,9 +8755,8 @@ FAR void *mmap(FAR void *start, size_t length, int prot, int flags, int fd, off_
- NuttX includes a simple interface layer based on uIP (see http://www.sics.se).
- NuttX supports subset of a standard socket interface to uIP.
- These network feature can be enabled by settings in the architecture configuration file.
+ NuttX supports a BSD-compatible socket interface layer.
+ These socket interface can be enabled by settings in the architecture configuration file.
Those socket APIs are discussed in the following paragraphs.
diff --git a/arch/README.txt b/arch/README.txt
index df34133df9..114f2f6f1e 100644
--- a/arch/README.txt
+++ b/arch/README.txt
@@ -134,6 +134,8 @@ src/Makefile
Supported Architectures
^^^^^^^^^^^^^^^^^^^^^^^
+NOTE: nuttx/Documentation/NuttX.html for current information about the
+state of these MCU ports.
arch/sim - Linux/Cygwin simulation
A user-mode port of NuttX to the x86 Linux platform is available.
@@ -145,135 +147,68 @@ arch/arm - ARM-based micro-controllers
This directory holds common ARM architectures. At present, this includes
the following subdirectories:
- arch/arm/include and arch/arm/src/common
- Common ARM/Cortex-M3 logic.
-
- arch/arm/src/arm and arch/arm/include/arm
- Common ARM-specific logic
-
- arch/arm/src/armv7-m and arch/arm/include/armv7-m
- Common ARMv7-M logic (Cortex-M3 and Cortex-M4)
-
- arch/arm/include/c5471 and arch/arm/src/c5471
- TI TMS320C5471 (also called TMS320DM180 or just C5471).
- NuttX operates on the ARM7 of this dual core processor. This port
- complete, verified, and included in the NuttX release 0.1.1.
-
- arch/arm/include/calypso and arch/arm/src/calypso
- TI "Calypso" MCU used in various cell phones (and, in particular,
- by the Osmocom-bb project). Like the c5471, NuttX operates on the
- ARM7 of this dual core processor. This port was contributed by
- Denis Carilki and includes the work of Denis, Alan Carvalho de Assis,
- and Stefan Richter. Calypso support first appeared in NuttX-6.17.
-
- arch/arm/include/dm320 and arch/arm/src/dm320
- TI TMS320DM320 (also called just DM320).
- NuttX operates on the ARM9EJS of this dual core processor. This port
- complete, verified, and included in the NuttX release 0.2.1.
-
- arch/arm/include/imx and arch/arm/src/imx
- Freescale MC9328MX1 or i.MX1. This port uses the Freescale MX1ADS
- development board with a GNU arm-elf toolchain* under either Linux or Cygwin.
- STATUS: This port has stalled because of development tool issues. Coding
- is complete on the basic port (timer, serial console, SPI).
-
- arch/arm/include/lm and arch/arm/src/lm
- These directories contain support for the Luminary LM3S/4F family. The
- initial, release of this port was included in NuttX version 0.4.6. The
- current port includes timer, serial console, Ethernet, SSI, and microSD
- support. There are working configurations the NuttX OS test, to run the
- NuttShell (NSH), the NuttX networking test, and the uIP web server.
-
- arch/arm/include/lpc214x and arch/arm/src/lpc214x
- These directories provide support for NXP LPC214x family of
- ARM7TDMI processors. This port boots and passes the OS test (examples/ostest).
- The port is complete and verifed. As of NuttX 0.3.17, the port includes:
- timer interrupts, serial console, USB driver, and SPI-based MMC/SD card
- support. A verifed NuttShell (NSH) configuration is also available.
-
- arch/arm/include/lpc2378 and arch/arm/src/lpc2378.
- NXP LPC2378. Support is provided for the NXP LPC2378 MCU. This port was
- contributed by Rommel Marcelo is was first released in NuttX-5.3.
- STATUS: This port boots and passes the OS test (examples/ostest) and
- includes a working implementation of the NuttShell (NSH). The port is
- complete and verified. As of NuttX 5.3, the port includes only basic
- timer interrupts and serial console support.
-
- arch/arm/include/lpc31xx and arch/arm/src/lpc31xx
- These directories provide support for NXP LPC31xx family of
- ARM926EJ-S processors. The port for the NXP LPC3131 was first
- released in NuttX-5.1 (but was not functional until NuttX-5.2).
- STATUS: The basic EA3131 port is complete and verified in NuttX-5.2
- This basic port includes basic boot-up, serial console, and timer
- interrupts. This port was extended in NuttX 5.3 with a USB high
- speed driver contributed by David Hewson. This port has been
- verified using the NuttX OS test, USB serial and mass storage tests
- and includes a working implementation of the NuttShell ((NSH)).
-
- This port was later extended to support additional members of the
- LPC31xx family including, specifically, the LPC3152.
-
- arch/arm/include/sam3u and arch/arm/src/sam3u
- Atmel AT91SAM3U. This port is for Atmel AT91SAM3U4E MCU.
- STATUS: The basic AT91SAM3U port was released in NuttX version 5.1.
- The basic port includes boot-up logic, interrupt driven serial
- console, and system timer interrupts. That release passes the
- NuttX OS test and is proven to have a valid OS implementation. A
- onfiguration to support the NuttShell is also included.
-
- arch/arm/include/stm32 and arch/arm/src/stm32
- These directories contain support for the STMicro STM32 F1, F2, and
- F4 families.
-
- STATUS: The basic STM32 F1 port was released in NuttX version 0.4.12.
- and has continued to develop consistently over time. It now includes
- support for the F2 and F4 families and a rich offering of peripheral
- drivers.
-
- arch/arm/include/str71x and arch/arm/src/str71x
- These directories provide support for the STMicro STR71x processors.
- Coding is complete on the basic port (boot logic, system time, serial console),
- but no testing has been performed due to some problems I am having with my
- JTAG wiggler and OpenOCD on Linux.
+ Architecture Support
+ arch/arm/include and arch/arm/src/common
+ arch/arm/src/arm and arch/arm/include/arm
+ arch/arm/src/armv7-a and arch/arm/include/armv7-a
+ arch/arm/src/armv7-m and arch/arm/include/armv7-m
+ arch/arm/src/armv7-r and arch/arm/include/armv7-4
+
+ MCU support
+ arch/arm/include/c5471 and arch/arm/src/c5471
+ arch/arm/include/calypso and arch/arm/src/calypso
+ arch/arm/include/dm320 and arch/arm/src/dm320
+ arch/arm/include/efm32 and arch/arm/src/efm32
+ arch/arm/include/imx1 and arch/arm/src/imx1
+ arch/arm/include/imx6 and arch/arm/src/imx6
+ arch/arm/include/kinetis and arch/arm/src/kinetis
+ arch/arm/include/kl and arch/arm/src/kl
+ arch/arm/include/lpc11xx and arch/arm/src/lpc11xx
+ arch/arm/include/lpc17xx and arch/arm/src/lpc17xx
+ arch/arm/include/lpc214x and arch/arm/src/lpc214x
+ arch/arm/include/lpc2378 and arch/arm/src/lpc2378.
+ arch/arm/include/lpc31xx and arch/arm/src/lpc31xx
+ arch/arm/include/lpc43xx and arch/arm/src/lpc43xx
+ arch/arm/include/moxart and arch/arm/src/moxart
+ arch/arm/include/nuc1xx and arch/arm/src/nuc1xx
+ arch/arm/include/sam34 and arch/arm/src/sam34
+ arch/arm/include/sama45 and arch/arm/src/sama5
+ arch/arm/include/samdl and arch/arm/src/samdl
+ arch/arm/include/samv7 and arch/arm/src/samv7
+ arch/arm/include/stm32 and arch/arm/src/stm32
+ arch/arm/include/stm32f7 and arch/arm/src/stm32f7
+ arch/arm/include/stm32l4 and arch/arm/src/stm32l4
+ arch/arm/include/str71x and arch/arm/src/str71x
+ arch/arm/include/tiva and arch/arm/src/tiva
+ arch/arm/include/tms570 and arch/arm/src/tms570
arch/avr
This directory is dedicated to ports to the Atmel AVR (8-bit) and AVR32 (32-bit)
MCU families. STATUS: Under development.
- arch/avr/include/avr and arch/avr/src/avr
- Common support for all 8-bit AVR MCUs
+ Architecture Support
+ arch/avr/include/avr and arch/avr/src/avr
+ arch/avr/include/avr32 and arch/avr/src/avr32
- arch/avr/include/atmega and arch/avr/src/atmega
- Support specifically for the AVR ATMega family (specifically only for
- the ATMega128 at the moment).
-
- arch/avr/include/at90usb and arch/avr/src/at90usb
- Support specifically for the AVR AT90USB646, 647, 1286, and 1287 family.
-
- arch/avr/include/avr32 and arch/avr/src/avr32
- Common support for all AVR32 MCUs
-
- arch/avr/include/at32uc3 and arch/avr/src/at32uc3
- Support specifically for the AT32UC3Bxxx family (specifically only for
- the AT32UC3B0256 at the moment).
+ MCU support
+ arch/avr/include/atmega and arch/avr/src/atmega
+ arch/avr/include/at90usb and arch/avr/src/at90usb
+ arch/avr/include/at32uc3 and arch/avr/src/at32uc3
arch/hc
This directory is dedicated to ports to the Freescale HC family.
arch/arm/include/m9s12 and arch/arm/src/m9s12
- These directories provide support for the Freescale mc9s12x family.
- STATUS: Fragments of this port were first released in nuttx-5.0 and
- the port was "code-complete" as nuttx-5.18. However, the final
- verification effort has been stalled because of higher priority tasks.
arch/mips
This directory is dedicated to ports to the MIPS family.
- arch/mips/include/mips32 and arch/mips/src/mips32
- Common support for all MIPS32 architectures
+ Architecture Support
+ arch/mips/include/mips32 and arch/mips/src/mips32
- arch/mips/include/pic32mx and arch/mips/src/pic32mx
- Support for all MicroChip PIC32MX architectures
+ MCU support
+ arch/mips/include/pic32mx and arch/mips/src/pic32mx
+ arch/mips/include/pic32mz and arch/mips/src/pic32mz
arch/rgmp
@@ -288,52 +223,42 @@ arch/rgmp
arch/sh - SuperH and related Hitachi/Renesas microcontrollers
- arch/sh/include and arch/sh/src/common
- Common SuperH logic.
+ Architecture Support
+ arch/sh/include and arch/sh/src/common
- arch/sh/include/shs and arch/sh/src/sh1
- Support for the SH-1 processor.
+ MCU support
+ arch/sh/include/m16c and arch/sh/src/m16c
+ arch/sh/include/sh1 and arch/sh/src/sh1
arch/x86 - Intel x86 architectures
This directory holds related, 32- and 64-bit architectures from Intel.
At present, this includes the following subdirectories:
- arch/x86/include and arch/x86/src/common
- Common x86 logic.
+ Architecture Support
+ arch/x86/include and arch/x86/src/common
- arch/x86/include/i486 and arch/x86/src/i486
- These directories hold definitions and logic appropriate for any
- instantiation of the 32-bit i486 architecture.
-
- arch/x86/include/qemu and arch/x86/src/qemu
- This is the implementation of NuttX on the QEMU x86 simulation.
+ MCU support
+ arch/x86/include/i486 and arch/x86/src/i486
+ arch/x86/include/qemu and arch/x86/src/qemu
arch/z16 - ZiLOG 16-bit processors
This directory holds related, 16-bit architectures from ZiLOG. At
present, this includes the following subdirectories:
- arch/z16/include and arch/z16/src/common
- Common microcontroller logic.
+ Architecture Support
+ arch/z16/include and arch/z16/src/common
- arch/z16/include/z16f and arch/z16/src/z16f
- ZiLOG z16f Microcontroller.
- STATUS: Released in nuttx-0.3.7. Fully functional other than issues
- addressed in ${TOPDIR}/TODO.
+ MCU support
+ arch/z16/include/z16f and arch/z16/src/z16f
arch/z80 - ZiLOG 8-bit microcontrollers
This directory holds related, 8-bit architectures from ZiLOG. At
present, this includes the following subdirectories:
- arch/z80/include and arch/z80/src/common
- Common microcontroller logic.
-
- arch/z80/include/z80 and arch/z80/src/z80
- Classic ZiLOG z80 Microcontroller.
- STATUS: Functional with no known defects. There are still several
- OS features that have not yet been tested (e.g., networking).
-
- arch/z80/include/z8 and arch/z80/src/z8
- ZiLOG Z8Encore! Microcontroller
+ Architecture Support
+ arch/z80/include and arch/z80/src/common
- arch/z80/include/ez80 and arch/z80/src/ez80
- ZiLOG ez80 Acclaim! Microcontroller
+ MCU support
+ arch/z80/include/z80 and arch/z80/src/z80
+ arch/z80/include/z8 and arch/z80/src/z8
+ arch/z80/include/ez80 and arch/z80/src/ez80
diff --git a/arch/hc/src/m9s12/m9s12_ethernet.c b/arch/hc/src/m9s12/m9s12_ethernet.c
index 0f02c88aed..ad3e1ef6b8 100644
--- a/arch/hc/src/m9s12/m9s12_ethernet.c
+++ b/arch/hc/src/m9s12/m9s12_ethernet.c
@@ -97,9 +97,9 @@ struct emac_driver_s
WDOG_ID d_txpoll; /* TX poll timer */
WDOG_ID d_txtimeout; /* TX timeout timer */
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s d_dev; /* Interface understood by uIP */
+ struct net_driver_s d_dev; /* Interface understood by the network */
};
/****************************************************************************
@@ -185,8 +185,9 @@ static int emac_transmit(FAR struct emac_driver_s *priv)
* Function: emac_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
- * to send. This is a callback from devif_poll(). devif_poll() may be called:
+ * The transmitter is available, check if the network has any outgoing
+ * packets ready to send. This is a callback from devif_poll().
+ * devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
* 2. When the preceding TX packet send timesout and the interface is reset
@@ -276,7 +277,7 @@ static void emac_receive(FAR struct emac_driver_s *priv)
{
/* Check for errors and update statistics */
- /* Check if the packet is a valid size for the uIP buffer configuration */
+ /* Check if the packet is a valid size for the network buffer configuration */
/* Copy the data data from the hardware to priv->d_dev.d_buf. Set
* amount of data in priv->d_dev.d_len
@@ -413,7 +414,7 @@ static void emac_txdone(FAR struct emac_driver_s *priv)
wd_cancel(priv->d_txtimeout);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&priv->d_dev, emac_txpoll);
}
@@ -484,7 +485,7 @@ static void emac_txtimeout(int argc, uint32_t arg, ...)
/* Then reset the hardware */
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&priv->d_dev, emac_txpoll);
}
@@ -515,7 +516,7 @@ static void emac_polltimer(int argc, uint32_t arg, ...)
* the TX poll if he are unable to accept another packet for transmission.
*/
- /* If so, update TCP timing states and poll uIP for new XMIT data. Hmmm..
+ /* If so, update TCP timing states and poll the network for new XMIT data. Hmmm..
* might be bug here. Does this mean if there is a transmit in progress,
* we will missing TCP time state updates?
*/
@@ -644,7 +645,7 @@ static int emac_txavail(struct net_driver_s *dev)
{
/* Check if there is room in the hardware to hold another outgoing packet. */
- /* If so, then poll uIP for new XMIT data */
+ /* If so, then poll the network for new XMIT data */
(void)devif_poll(&priv->d_dev, emac_txpoll);
}
diff --git a/arch/mips/src/pic32mx/pic32mx-ethernet.c b/arch/mips/src/pic32mx/pic32mx-ethernet.c
index eae7719bd4..4c11f5c660 100644
--- a/arch/mips/src/pic32mx/pic32mx-ethernet.c
+++ b/arch/mips/src/pic32mx/pic32mx-ethernet.c
@@ -319,9 +319,9 @@ struct pic32mx_driver_s
sq_queue_t pd_freebuffers; /* The free buffer list */
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s pd_dev; /* Interface understood by uIP */
+ struct net_driver_s pd_dev; /* Interface understood by the network */
/* Descriptors and packet buffers */
@@ -1024,7 +1024,7 @@ static int pic32mx_transmit(struct pic32mx_driver_s *priv)
/* Find the next available TX descriptor. We are guaranteed that is will
* not fail by upstream logic that assures that a TX packet is available
- * before polling uIP.
+ * before polling the network.
*/
txdesc = pic32mx_txdesc(priv);
@@ -1080,8 +1080,9 @@ static int pic32mx_transmit(struct pic32mx_driver_s *priv)
* Function: pic32mx_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
- * to send. This is a callback from devif_poll(). devif_poll() may be called:
+ * The transmitter is available, check if the network has any outgoing
+ * packets ready to send. This is a callback from devif_poll().
+ * devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
* 2. When the preceding TX packet send timesout and the interface is reset
@@ -1172,7 +1173,7 @@ static int pic32mx_txpoll(struct net_driver_s *dev)
* Function: pic32mx_poll
*
* Description:
- * Perform the uIP poll.
+ * Perform the network poll.
*
* Parameters:
* priv - Reference to the driver state structure
@@ -1220,7 +1221,7 @@ static void pic32mx_poll(struct pic32mx_driver_s *priv)
* Function: pic32mx_timerpoll
*
* Description:
- * Perform the uIP timer poll.
+ * Perform the network timer poll.
*
* Parameters:
* priv - Reference to the driver state structure
@@ -1634,11 +1635,11 @@ static void pic32mx_txdone(struct pic32mx_driver_s *priv)
pic32mx_putreg(priv->pd_inten, PIC32MX_ETH_IEN);
}
- /* Otherwise poll uIP for new XMIT data */
+ /* Otherwise poll the network for new XMIT data */
else
{
- /* Perform the uIP poll */
+ /* Perform the network poll */
pic32mx_poll(priv);
}
@@ -1848,7 +1849,7 @@ static void pic32mx_txtimeout(int argc, uint32_t arg, ...)
(void)pic32mx_ifup(&priv->pd_dev);
- /* Then poll uIP for new XMIT data (We are guaranteed to have a free
+ /* Then poll the network for new XMIT data (We are guaranteed to have a free
* buffer here).
*/
@@ -1884,7 +1885,7 @@ static void pic32mx_polltimer(int argc, uint32_t arg, ...)
if (pic32mx_txdesc(priv) != NULL)
{
- /* If so, update TCP timing states and poll uIP for new XMIT data. Hmmm..
+ /* If so, update TCP timing states and poll the network for new XMIT data. Hmmm..
* might be bug here. Does this mean if there is a transmit in progress,
* we will missing TCP time state updates?
*/
@@ -2281,7 +2282,7 @@ static int pic32mx_txavail(struct net_driver_s *dev)
if (pic32mx_txdesc(priv) != NULL)
{
- /* If so, then poll uIP for new XMIT data. First allocate a buffer
+ /* If so, then poll the network for new XMIT data. First allocate a buffer
* to perform the poll
*/
diff --git a/arch/mips/src/pic32mz/pic32mz-ethernet.c b/arch/mips/src/pic32mz/pic32mz-ethernet.c
index 6b45f1ea02..7d531efde9 100644
--- a/arch/mips/src/pic32mz/pic32mz-ethernet.c
+++ b/arch/mips/src/pic32mz/pic32mz-ethernet.c
@@ -337,9 +337,9 @@ struct pic32mz_driver_s
sq_queue_t pd_freebuffers; /* The free buffer list */
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s pd_dev; /* Interface understood by uIP */
+ struct net_driver_s pd_dev; /* Interface understood by the network */
/* Descriptors and packet buffers */
@@ -1042,7 +1042,7 @@ static int pic32mz_transmit(struct pic32mz_driver_s *priv)
/* Find the next available TX descriptor. We are guaranteed that is will
* not fail by upstream logic that assures that a TX packet is available
- * before polling uIP.
+ * before polling the network.
*/
txdesc = pic32mz_txdesc(priv);
@@ -1098,8 +1098,9 @@ static int pic32mz_transmit(struct pic32mz_driver_s *priv)
* Function: pic32mz_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
- * to send. This is a callback from devif_poll(). devif_poll() may be called:
+ * The transmitter is available, check if the network has any outgoing
+ * packets ready to send. This is a callback from devif_poll().
+ * devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
* 2. When the preceding TX packet send timesout and the interface is reset
@@ -1190,7 +1191,7 @@ static int pic32mz_txpoll(struct net_driver_s *dev)
* Function: pic32mz_poll
*
* Description:
- * Perform the uIP poll.
+ * Perform the network poll.
*
* Parameters:
* priv - Reference to the driver state structure
@@ -1238,7 +1239,7 @@ static void pic32mz_poll(struct pic32mz_driver_s *priv)
* Function: pic32mz_timerpoll
*
* Description:
- * Perform the uIP timer poll.
+ * Perform the network timer poll.
*
* Parameters:
* priv - Reference to the driver state structure
@@ -1651,11 +1652,11 @@ static void pic32mz_txdone(struct pic32mz_driver_s *priv)
pic32mz_putreg(priv->pd_inten, PIC32MZ_ETH_IEN);
}
- /* Otherwise poll uIP for new XMIT data */
+ /* Otherwise poll the network for new XMIT data */
else
{
- /* Perform the uIP poll */
+ /* Perform the network poll */
pic32mz_poll(priv);
}
@@ -1865,7 +1866,7 @@ static void pic32mz_txtimeout(int argc, uint32_t arg, ...)
(void)pic32mz_ifup(&priv->pd_dev);
- /* Then poll uIP for new XMIT data (We are guaranteed to have a free
+ /* Then poll the network for new XMIT data (We are guaranteed to have a free
* buffer here).
*/
@@ -1901,7 +1902,7 @@ static void pic32mz_polltimer(int argc, uint32_t arg, ...)
if (pic32mz_txdesc(priv) != NULL)
{
- /* If so, update TCP timing states and poll uIP for new XMIT data. Hmmm..
+ /* If so, update TCP timing states and poll the network for new XMIT data. Hmmm..
* might be bug here. Does this mean if there is a transmit in progress,
* we will missing TCP time state updates?
*/
@@ -2304,7 +2305,7 @@ static int pic32mz_txavail(struct net_driver_s *dev)
if (pic32mz_txdesc(priv) != NULL)
{
- /* If so, then poll uIP for new XMIT data. First allocate a buffer
+ /* If so, then poll the network for new XMIT data. First allocate a buffer
* to perform the poll
*/
diff --git a/arch/z80/src/ez80/ez80_emac.c b/arch/z80/src/ez80/ez80_emac.c
index 2b1b5834fe..0584aa0464 100644
--- a/arch/z80/src/ez80/ez80_emac.c
+++ b/arch/z80/src/ez80/ez80_emac.c
@@ -325,9 +325,9 @@ struct ez80emac_driver_s
struct ez80mac_statistics_s stat;
#endif
- /* This holds the information visible to uIP/NuttX */
+ /* This holds the information visible to the NuttX network */
- struct net_driver_s dev; /* Interface understood by uIP */
+ struct net_driver_s dev; /* Interface understood by the network */
};
/****************************************************************************
@@ -1055,8 +1055,9 @@ static int ez80emac_transmit(struct ez80emac_driver_s *priv)
* Function: ez80emac_txpoll
*
* Description:
- * The transmitter is available, check if uIP has any outgoing packets ready
- * to send. This is a callback from devif_poll(). devif_poll() may be called:
+ * The transmitter is available, check if the network has any outgoing
+ * packets ready to send. This is a callback from devif_poll().
+ * devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
* 2. When the preceding TX packet send timesout and the interface is reset
@@ -1228,7 +1229,7 @@ static int ez80emac_receive(struct ez80emac_driver_s *priv)
}
/* We have a good packet. Check if the packet is a valid size
- * for the uIP buffer configuration (I routinely see
+ * for the network buffer configuration (I routinely see
*/
if (rxdesc->pktsize > CONFIG_NET_ETH_MTU)
@@ -1669,7 +1670,7 @@ static void ez80emac_txtimeout(int argc, uint32_t arg, ...)
ez80emac_ifup(&priv->dev);
leave_critical_section(flags);
- /* Then poll uIP for new XMIT data */
+ /* Then poll the network for new XMIT data */
(void)devif_poll(&priv->dev, ez80emac_txpoll);
}
@@ -1695,7 +1696,7 @@ static void ez80emac_polltimer(int argc, uint32_t arg, ...)
{
struct ez80emac_driver_s *priv = (struct ez80emac_driver_s *)arg;
- /* Poll uIP for new XMIT data */
+ /* Poll the network for new XMIT data */
(void)devif_timer(&priv->dev, ez80emac_txpoll);
@@ -1882,7 +1883,7 @@ static int ez80emac_txavail(struct net_driver_s *dev)
/* Check if there is room in the hardware to hold another outgoing packet. */
- /* If so, then poll uIP for new XMIT data */
+ /* If so, then poll the network for new XMIT data */
(void)devif_poll(&priv->dev, ez80emac_txpoll);
}
@@ -2256,7 +2257,7 @@ errout:
* Add one MAC address to the multi-cast hash table
*
* Parameters:
- * dev - Reference to the uIP driver state structure
+ * dev - Reference to the network driver state structure
* mac - The MAC address to add
* enable - true: Enable filtering on this address; false: disable
*
diff --git a/configs/dk-tm4c129x/src/tm4c_ethernet.c b/configs/dk-tm4c129x/src/tm4c_ethernet.c
index 9394a4522b..8594d75559 100644
--- a/configs/dk-tm4c129x/src/tm4c_ethernet.c
+++ b/configs/dk-tm4c129x/src/tm4c_ethernet.c
@@ -87,7 +87,7 @@ void tiva_ethernetmac(struct ether_addr *ethaddr)
nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
- /* Re-format that MAC address the way that uIP expects to see it */
+ /* Re-format that MAC address the way that the network expects to see it */
ethaddr->ether_addr_octet[0] = ((user0 >> 0) & 0xff);
ethaddr->ether_addr_octet[1] = ((user0 >> 8) & 0xff);
diff --git a/configs/eagle100/src/lm_ethernet.c b/configs/eagle100/src/lm_ethernet.c
index 62f073697c..7a33e1af6c 100644
--- a/configs/eagle100/src/lm_ethernet.c
+++ b/configs/eagle100/src/lm_ethernet.c
@@ -86,7 +86,7 @@ void tiva_ethernetmac(struct ether_addr *ethaddr)
nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
- /* Re-format that MAC address the way that uIP expects to see it */
+ /* Re-format that MAC address the way that the network expects to see it */
ethaddr->ether_addr_octet[0] = ((user0 >> 0) & 0xff);
ethaddr->ether_addr_octet[1] = ((user0 >> 8) & 0xff);
diff --git a/configs/ekk-lm3s9b96/src/lm_ethernet.c b/configs/ekk-lm3s9b96/src/lm_ethernet.c
index 622a972b3e..c3627e4a16 100644
--- a/configs/ekk-lm3s9b96/src/lm_ethernet.c
+++ b/configs/ekk-lm3s9b96/src/lm_ethernet.c
@@ -87,7 +87,7 @@ void tiva_ethernetmac(struct ether_addr *ethaddr)
nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
- /* Re-format that MAC address the way that uIP expects to see it */
+ /* Re-format that MAC address the way that the network expects to see it */
ethaddr->ether_addr_octet[0] = ((user0 >> 0) & 0xff);
ethaddr->ether_addr_octet[1] = ((user0 >> 8) & 0xff);
diff --git a/configs/lm3s6432-s2e/src/lm_ethernet.c b/configs/lm3s6432-s2e/src/lm_ethernet.c
index 2d6bb5a088..c10d261adc 100644
--- a/configs/lm3s6432-s2e/src/lm_ethernet.c
+++ b/configs/lm3s6432-s2e/src/lm_ethernet.c
@@ -86,7 +86,7 @@ void tiva_ethernetmac(struct ether_addr *ethaddr)
nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
- /* Re-format that MAC address the way that uIP expects to see it */
+ /* Re-format that MAC address the way that the network expects to see it */
ethaddr->ether_addr_octet[0] = ((user0 >> 0) & 0xff);
ethaddr->ether_addr_octet[1] = ((user0 >> 8) & 0xff);
diff --git a/configs/lm3s6965-ek/src/lm_ethernet.c b/configs/lm3s6965-ek/src/lm_ethernet.c
index 6d4d62f5fa..4a467dd459 100644
--- a/configs/lm3s6965-ek/src/lm_ethernet.c
+++ b/configs/lm3s6965-ek/src/lm_ethernet.c
@@ -86,7 +86,7 @@ void tiva_ethernetmac(struct ether_addr *ethaddr)
nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
- /* Re-format that MAC address the way that uIP expects to see it */
+ /* Re-format that MAC address the way that the network expects to see it */
ethaddr->ether_addr_octet[0] = ((user0 >> 0) & 0xff);
ethaddr->ether_addr_octet[1] = ((user0 >> 8) & 0xff);
diff --git a/configs/lm3s8962-ek/src/lm_ethernet.c b/configs/lm3s8962-ek/src/lm_ethernet.c
index fb5db9e152..a6d4da70e9 100644
--- a/configs/lm3s8962-ek/src/lm_ethernet.c
+++ b/configs/lm3s8962-ek/src/lm_ethernet.c
@@ -86,7 +86,7 @@ void tiva_ethernetmac(struct ether_addr *ethaddr)
nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
- /* Re-format that MAC address the way that uIP expects to see it */
+ /* Re-format that MAC address the way that the network expects to see it */
ethaddr->ether_addr_octet[0] = ((user0 >> 0) & 0xff);
ethaddr->ether_addr_octet[1] = ((user0 >> 8) & 0xff);
diff --git a/configs/tm4c1294-launchpad/src/tm4c_ethernet.c b/configs/tm4c1294-launchpad/src/tm4c_ethernet.c
index f668660342..3b70b23853 100644
--- a/configs/tm4c1294-launchpad/src/tm4c_ethernet.c
+++ b/configs/tm4c1294-launchpad/src/tm4c_ethernet.c
@@ -87,7 +87,7 @@ void tiva_ethernetmac(struct ether_addr *ethaddr)
nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
- /* Re-format that MAC address the way that uIP expects to see it */
+ /* Re-format that MAC address the way that the network expects to see it */
ethaddr->ether_addr_octet[0] = ((user0 >> 0) & 0xff);
ethaddr->ether_addr_octet[1] = ((user0 >> 8) & 0xff);
diff --git a/libc/netdb/lib_dnsquery.c b/libc/netdb/lib_dnsquery.c
index 54a5046fab..c29437c7b2 100644
--- a/libc/netdb/lib_dnsquery.c
+++ b/libc/netdb/lib_dnsquery.c
@@ -2,8 +2,8 @@
* libc/netdb/lib_dnsquery.c
* DNS host name to IP address resolver.
*
- * The uIP DNS resolver functions are used to lookup a hostname and
- * map it to a numerical IP address.
+ * The DNS resolver functions are used to lookup a hostname and map it to a
+ * numerical IP address.
*
* Copyright (C) 2007, 2009, 2012, 2014-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
--
GitLab
From 39c1e3aba23b308e871501f4a105a1ccd7cb495d Mon Sep 17 00:00:00 2001
From: Pierre-noel Bouteville
Date: Mon, 30 May 2016 11:58:22 -0600
Subject: [PATCH 014/400] Allow to not use all channet in a lower part of PWM
---
arch/arm/src/stm32/stm32_pwm.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c
index 8779d18692..76783804ea 100644
--- a/arch/arm/src/stm32/stm32_pwm.c
+++ b/arch/arm/src/stm32/stm32_pwm.c
@@ -1314,6 +1314,15 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
duty = info->channels[i].duty;
channel = info->channels[i].channel;
+ /* A value of zero means to skip this channel */
+
+ if (channel == 0)
+ {
+ continue;
+ }
+
+ /* Find the channel */
+
for (j = 0; j < PWM_NCHANNELS; j++)
{
if (priv->channels[j].channel == channel)
--
GitLab
From 6940fe9655838a3d7b8f7e13248048e999c17913 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Mon, 30 May 2016 13:31:19 -0600
Subject: [PATCH 015/400] Update ChangeLog
---
ChangeLog | 56 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/ChangeLog b/ChangeLog
index dab311760b..7722d45c88 100755
--- a/ChangeLog
+++ b/ChangeLog
@@ -11813,3 +11813,59 @@
* fs/: Add logic to detach a file structure from a file descriptor.
This is for use only within the OS. It permits an open file or driver
to be used across multiple threads (2016-05-26).
+ * arch/arm/src/stm32l4: Get I2C working for STM32L4. From Dave
+ (ziggurat29) (2016-05-25).
+ * fs/ and include/nuttx/fs: Add logic to detach a file structure from a
+ file descriptor. This is for use only within the OS. It permits an
+ open file or driver to be used across multiple threads. (2016-05-26).
+ * drivers/analog/adc.c, include/nuttx/analog/adc.h, and all ADC lower
+ half drivers: No longer uses global adc_receive() call. Added a new
+ bind() method to the ADC interface. Now the ADC upper half driver
+ will register its receipt-of-data callback. This change allows the
+ ADC lower half driver to be used with a differ ADC upper half
+ (2016-05-26).
+ * drivers/analog/ads1255.c: Must not do SPI access from interrupt
+ handler. Use the worker thread instead. Must also lock the SPI bus
+ before using it. (2015-05-26).
+ * drivers/: Several SPI-based drivers modified. All drivers that use
+ SPI must call SPI_LOCK and SPI_UNLOCK. This is not optional
+ (2016-05-26).
+ * drivers/sensosrs: Fix a bug in crc computation for ms583730.
+ Implement POSIX read (2016-05-27).
+ * arch/arm/src/samv7: This is a fix to a problem in the handling of the
+ oneshot timer. Due to a wrong assumption concerning the behavior
+ directly after the start of the timer/counter the function
+ sam_oneshot_cancel(…) calculates the wrong remaining time. The code
+ assumes that the counter register is zero directly after the start of
+ the timer, but this is not true. To start the time/counter a software
+ trigger is invoked, this trigger starts the timer/count and sets the
+ counter register to zero, but the reset of the counter register is not
+ performed instantly. According to the datasheet: "The counter can be
+ reset by a trigger. In this case, the counter value passes to zero on
+ the next valid edge of the selected clock.” Thus the counter is set to
+ zero between 0 and USEC_PER_TICK microseconds after the clock was
+ started.
+ In my fix I use the freerun count value to determine if at least one
+ tick passed since the start of the timer and thus if the value of the
+ oneshot counter is correct. I also tried to use the function
+ up_timer_gettime(…) to achieve this but, at least if compiled with no
+ optimization the problem vanishes without using the value of the
+ function, the function call takes too long.
+ Another problem treated in the fix is that if the oneshot timer/counter
+ is canceled, we only know the remaining time with a precision of
+ USEC_PER_TICK microseconds. This means the calculated remaining time
+ is between 0 and USEC_PER_TICK microseconds too long. To fix this I
+ subtract one tick if the calculated remaining time is greater than one
+ tick and otherwise set the remaining time to zero. By doing so the
+ measured times are much more precise as without it. From Stefan Kolb
+ (2016-05-27).
+ * arch/arm/src/sama5: Stefan Kolb's change to the SAMV7 Oneshot Timer
+ should also be applied to the SAMA5 oneshot time since the drivers are
+ identical (2016-05-27).
+ * arch/arm/src/stm32l4: Add support for SPI 4 and 5 on stm32f411 chips.
+ From Konstantin Berezenko (2016-05-27).
+ * arch/arm/src/sam34: Stefan Kolb's change to the SAMV7 Oneshot Timer
+ should also be applied to the SAM3/4 oneshot time since the drivers
+ are identical (2016-05-29).
+ * arch/arm/src/stm32: Allow to not use all channel in a lower part of
+ PWM. From Pierre-noel Bouteville (2016-05-30).
--
GitLab
From f06a06952fa63dac3adf1c811b80b374c014a413 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Tue, 31 May 2016 06:22:10 -0600
Subject: [PATCH 016/400] LPC43xx: 1KB is 1024, not 1025. Noted by
phreakuencies.
---
arch/arm/include/lpc43xx/chip.h | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/lpc43xx/chip.h b/arch/arm/include/lpc43xx/chip.h
index a88559df21..4592117de1 100644
--- a/arch/arm/include/lpc43xx/chip.h
+++ b/arch/arm/include/lpc43xx/chip.h
@@ -322,8 +322,8 @@
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4337JBD144)
-# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
-# define LPC43_FLASH_BANKB_SIZE (512*1025)
+# define LPC43_FLASH_BANKA_SIZE (512*1024) /* 1024Kb FLASH */
+# define LPC43_FLASH_BANKB_SIZE (512*1024)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
@@ -426,8 +426,8 @@
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4353FBD208)
-# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
-# define LPC43_FLASH_BANKB_SIZE (256*1025)
+# define LPC43_FLASH_BANKA_SIZE (256*1024) /* 512Kb FLASH */
+# define LPC43_FLASH_BANKB_SIZE (256*1024)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
@@ -452,8 +452,8 @@
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4353FET180)
-# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
-# define LPC43_FLASH_BANKB_SIZE (256*1025)
+# define LPC43_FLASH_BANKA_SIZE (256*1024) /* 512Kb FLASH */
+# define LPC43_FLASH_BANKB_SIZE (256*1024)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
@@ -478,8 +478,8 @@
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4353FET256)
-# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
-# define LPC43_FLASH_BANKB_SIZE (256*1025)
+# define LPC43_FLASH_BANKA_SIZE (256*1024) /* 512Kb FLASH */
+# define LPC43_FLASH_BANKB_SIZE (256*1024)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
@@ -504,8 +504,8 @@
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4357FET180)
-# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
-# define LPC43_FLASH_BANKB_SIZE (512*1025)
+# define LPC43_FLASH_BANKA_SIZE (512*1024) /* 1024Kb FLASH */
+# define LPC43_FLASH_BANKB_SIZE (512*1024)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
@@ -530,8 +530,8 @@
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4357FBD208)
-# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
-# define LPC43_FLASH_BANKB_SIZE (512*1025)
+# define LPC43_FLASH_BANKA_SIZE (512*1024) /* 1024Kb FLASH */
+# define LPC43_FLASH_BANKB_SIZE (512*1024)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
@@ -556,8 +556,8 @@
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4357FET256)
-# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
-# define LPC43_FLASH_BANKB_SIZE (512*1025)
+# define LPC43_FLASH_BANKA_SIZE (512*1024) /* 1024Kb FLASH */
+# define LPC43_FLASH_BANKB_SIZE (512*1024)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
--
GitLab
From 4f81a60ef662886009f8a596485f6dafeb58d064 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Tue, 31 May 2016 06:31:04 -0600
Subject: [PATCH 017/400] Add a NAN test on 'x' in asin function of lib_asin.c.
Suggested by Pierre-noel Bouteville.
---
libc/math/lib_asin.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/libc/math/lib_asin.c b/libc/math/lib_asin.c
index 08a2dc9573..2f45a24a1d 100644
--- a/libc/math/lib_asin.c
+++ b/libc/math/lib_asin.c
@@ -3,7 +3,7 @@
*
* This file is a part of NuttX:
*
- * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2015-2016 Gregory Nutt. All rights reserved.
* Ported by: Darcy Gong
*
* It derives from the Rhombs OS math library by Nick Johnson which has
@@ -55,7 +55,7 @@ double asin(double x)
/* Verify that the input value is in the domain of the function */
- if (x < -1.0 || x > 1.0)
+ if (x < -1.0 || x > 1.0 || isnan(x))
{
return NAN;
}
--
GitLab
From 828c898a80972af48efb9f35aab32174aff3d545 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Tue, 31 May 2016 11:39:51 -0600
Subject: [PATCH 018/400] LP43: Add support for more than 63 interrupts (not
currently needed)
---
arch/arm/src/lpc43xx/lpc43_irq.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/src/lpc43xx/lpc43_irq.c b/arch/arm/src/lpc43xx/lpc43_irq.c
index 73ca6d3bc7..892b2c48a0 100644
--- a/arch/arm/src/lpc43xx/lpc43_irq.c
+++ b/arch/arm/src/lpc43xx/lpc43_irq.c
@@ -246,18 +246,45 @@ static int lpc43_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
if (irq >= LPC43_IRQ_EXTINT)
{
+ /* NOTE: We assume that there are at least 32 interrupts */
+
if (irq < (LPC43_IRQ_EXTINT + 32))
{
+ /* Interrupt in range {0-31} */
+
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << (irq - LPC43_IRQ_EXTINT);
}
+#if LPC43M4_IRQ_NIRQS > 95
+# error Extension to interrupt logic needed
+#elif LPC43M4_IRQ_NIRQS > 63
+ else if (irq < (LPC43_IRQ_EXTINT + 64))
+ {
+ /* Interrupt in range {32-63} */
+
+ *regaddr = (NVIC_IRQ32_63_ENABLE + offset);
+ *bit = 1 << (irq - LPC43_IRQ_EXTINT - 32);
+ }
else if (irq < LPC43M4_IRQ_NIRQS)
{
+ /* Interrupt in range {64-LPC43M4_IRQ_NIRQS}, LPC43M4_IRQ_NIRQS <= 95 */
+
+ *regaddr = (NVIC_IRQ64_95_ENABLE + offset);
+ *bit = 1 << (irq - LPC43_IRQ_EXTINT - 64);
+ }
+#else /* if LPC43M4_IRQ_NIRQS > 31 */
+ else if (irq < LPC43M4_IRQ_NIRQS)
+ {
+ /* Interrupt in range {32-LPC43M4_IRQ_NIRQS}, LPC43M4_IRQ_NIRQS <= 63 */
+
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (irq - LPC43_IRQ_EXTINT - 32);
}
+#endif
else
{
+ /* Interrupt >= LPC43M4_IRQ_NIRQS */
+
return ERROR; /* Invalid interrupt */
}
}
--
GitLab
From b5c37f02707e4abfe736efafdd88bd309ce2d83b Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Tue, 31 May 2016 11:42:21 -0600
Subject: [PATCH 019/400] LP43: Add support for more than 63 interrupts (not
currently needed)
---
arch/arm/src/lpc43xx/lpc43_irq.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/src/lpc43xx/lpc43_irq.c b/arch/arm/src/lpc43xx/lpc43_irq.c
index 892b2c48a0..be616ccb01 100644
--- a/arch/arm/src/lpc43xx/lpc43_irq.c
+++ b/arch/arm/src/lpc43xx/lpc43_irq.c
@@ -344,7 +344,12 @@ void up_irqinitialize(void)
/* Disable all interrupts */
putreg32(0, NVIC_IRQ0_31_ENABLE);
+#if LPC43M4_IRQ_NIRQS > 31
putreg32(0, NVIC_IRQ32_63_ENABLE);
+#if LPC43M4_IRQ_NIRQS > 63
+ putreg32(0, NVIC_IRQ64_95_ENABLE);
+#endif
+#endif
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
--
GitLab
From b80bf203746b3d20c90de6a83290bed3650644e9 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Tue, 31 May 2016 11:52:40 -0600
Subject: [PATCH 020/400] Fix another bungle in the last commit
---
arch/arm/src/lpc43xx/lpc43_irq.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/src/lpc43xx/lpc43_irq.c b/arch/arm/src/lpc43xx/lpc43_irq.c
index be616ccb01..a6e54b51f0 100644
--- a/arch/arm/src/lpc43xx/lpc43_irq.c
+++ b/arch/arm/src/lpc43xx/lpc43_irq.c
@@ -255,9 +255,9 @@ static int lpc43_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << (irq - LPC43_IRQ_EXTINT);
}
-#if LPC43M4_IRQ_NIRQS > 95
+#if LPC43M4_IRQ_NEXTINT > 95
# error Extension to interrupt logic needed
-#elif LPC43M4_IRQ_NIRQS > 63
+#elif LPC43M4_IRQ_NEXTINT > 63
else if (irq < (LPC43_IRQ_EXTINT + 64))
{
/* Interrupt in range {32-63} */
@@ -272,7 +272,7 @@ static int lpc43_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (irq - LPC43_IRQ_EXTINT - 64);
}
-#else /* if LPC43M4_IRQ_NIRQS > 31 */
+#else /* if LPC43M4_IRQ_NEXTINT > 31 */
else if (irq < LPC43M4_IRQ_NIRQS)
{
/* Interrupt in range {32-LPC43M4_IRQ_NIRQS}, LPC43M4_IRQ_NIRQS <= 63 */
@@ -344,9 +344,9 @@ void up_irqinitialize(void)
/* Disable all interrupts */
putreg32(0, NVIC_IRQ0_31_ENABLE);
-#if LPC43M4_IRQ_NIRQS > 31
+#if LPC43M4_IRQ_NEXTINT > 31
putreg32(0, NVIC_IRQ32_63_ENABLE);
-#if LPC43M4_IRQ_NIRQS > 63
+#if LPC43M4_IRQ_NEXTINT > 63
putreg32(0, NVIC_IRQ64_95_ENABLE);
#endif
#endif
--
GitLab
From 639410849ec5a059daa369e9cfb030093c56e8d9 Mon Sep 17 00:00:00 2001
From: neilh10
Date: Tue, 31 May 2016 14:17:52 -0700
Subject: [PATCH 021/400] alarm 10 now runs to completion
---
arch/arm/src/stm32/stm32_rtc_lowerhalf.c | 2 +-
arch/arm/src/stm32/stm32f40xxx_rtcc.c | 32 +++++++++++++++++-------
2 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_rtc_lowerhalf.c b/arch/arm/src/stm32/stm32_rtc_lowerhalf.c
index 20275ee921..feaa3f5395 100644
--- a/arch/arm/src/stm32/stm32_rtc_lowerhalf.c
+++ b/arch/arm/src/stm32/stm32_rtc_lowerhalf.c
@@ -178,7 +178,6 @@ static void stm32_alarm_callback(FAR void *arg, unsigned int alarmid)
rtc_alarm_callback_t cb;
FAR void *priv;
- DEBUGASSERT(priv != NULL);
DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB);
lower = (struct stm32_lowerhalf_s *)arg;
@@ -190,6 +189,7 @@ static void stm32_alarm_callback(FAR void *arg, unsigned int alarmid)
cb = (rtc_alarm_callback_t)cbinfo->cb;
priv = (FAR void *)cbinfo->priv;
+ DEBUGASSERT(priv != NULL);
cbinfo->cb = NULL;
cbinfo->priv = NULL;
diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
index ece81269c6..165c3c0247 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
@@ -219,7 +219,7 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg);
#ifdef CONFIG_DEBUG_RTC
static void rtc_dumpregs(FAR const char *msg)
{
- rtclldbg("%s:\n", msg);
+ rtclldbg("*** %s:\n", msg);
rtclldbg(" TR: %08x\n", getreg32(STM32_RTC_TR));
rtclldbg(" DR: %08x\n", getreg32(STM32_RTC_DR));
rtclldbg(" CR: %08x\n", getreg32(STM32_RTC_CR));
@@ -240,6 +240,12 @@ static void rtc_dumpregs(FAR const char *msg)
rtclldbg("ALRMASSR: %08x\n", getreg32(STM32_RTC_ALRMASSR));
rtclldbg("ALRMBSSR: %08x\n", getreg32(STM32_RTC_ALRMBSSR));
rtclldbg("MAGICREG: %08x\n", getreg32(RTC_MAGIC_REG));
+ int rtc_state =
+ ((getreg32(STM32_EXTI_RTSR) & EXTI_RTC_ALARM) ? 0x1000 : 0) |
+ ((getreg32(STM32_EXTI_FTSR) & EXTI_RTC_ALARM) ? 0x0100 : 0) |
+ ((getreg32(STM32_EXTI_IMR) & EXTI_RTC_ALARM) ? 0x0010 : 0) |
+ ((getreg32(STM32_EXTI_EMR) & EXTI_RTC_ALARM) ? 0x0001 : 0);
+ rtclldbg("EXTI (RTSR FTSR ISR EVT): %01x\n",rtc_state);
}
#else
# define rtc_dumpregs(msg)
@@ -600,9 +606,9 @@ static void rtc_resume(void)
regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF);
putreg32(regval, STM32_RTC_ISR);
- /* Clear the EXTI Line 17 Pending bit (Connected internally to RTC Alarm) */
+ /* Clear the RTC Alarm Pending bit */
- putreg32((1 << 17), STM32_EXTI_PR);
+ putreg32((1 << EXTI_RTC_ALARM ), STM32_EXTI_PR);
#endif
}
@@ -876,8 +882,6 @@ int up_rtc_initialize(void)
* maximum performance.
*/
- rtc_dumpregs("On reset");
-
/* Select the clock source */
/* Save the token before losing it when resetting */
@@ -902,16 +906,19 @@ int up_rtc_initialize(void)
#ifdef CONFIG_RTC_HSECLOCK
/* Use the HSE clock as the input to the RTC block */
+ rtc_dumpregs("On reset HSE");
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_HSE);
#elif defined(CONFIG_RTC_LSICLOCK)
/* Use the LSI clock as the input to the RTC block */
+ rtc_dumpregs("On reset LSI");
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSI);
#elif defined(CONFIG_RTC_LSECLOCK)
/* Use the LSE clock as the input to the RTC block */
+ rtc_dumpregs("On reset LSE");
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSE);
#endif
@@ -926,6 +933,8 @@ int up_rtc_initialize(void)
uint32_t clksrc = getreg32(STM32_RCC_XXX);
+ rtc_dumpregs("On reset warm");
+
#if defined(CONFIG_RTC_HSECLOCK)
if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_HSE)
#elif defined(CONFIG_RTC_LSICLOCK)
@@ -1060,10 +1069,13 @@ int up_rtc_initialize(void)
*/
stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler);
+ rtc_dumpregs("After InitExtiAlarm");
+#else
+ rtc_dumpregs("After Initialization");
#endif
g_rtc_enabled = true;
- rtc_dumpregs("After Initialization");
+
return OK;
}
@@ -1365,13 +1377,14 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
cbinfo->ac_cb = alminfo->as_cb;
cbinfo->ac_arg = alminfo->as_arg;
- ret = rtchw_set_alrmar(alarmreg | RTC_ALRMR_ENABLE);
+ ret = rtchw_set_alrmar(alarmreg | RTC_ALRMR_ENABLE | RTC_ALRMR_DIS_DATE_MASK);
if (ret < 0)
{
cbinfo->ac_cb = NULL;
cbinfo->ac_arg = NULL;
}
}
+ rtc_dumpregs("Set AlarmA");
break;
case RTC_ALARMB:
@@ -1380,13 +1393,14 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
cbinfo->ac_cb = alminfo->as_cb;
cbinfo->ac_arg = alminfo->as_arg;
- ret = rtchw_set_alrmbr(alarmreg | RTC_ALRMR_ENABLE);
+ ret = rtchw_set_alrmbr(alarmreg | RTC_ALRMR_ENABLE | RTC_ALRMR_DIS_DATE_MASK);
if (ret < 0)
{
cbinfo->ac_cb = NULL;
cbinfo->ac_arg = NULL;
}
}
+ rtc_dumpregs("Set AlarmB");
break;
default:
@@ -1486,7 +1500,7 @@ int stm32_rtc_cancelalarm(enum alm_id_e alarmid)
break;
default:
- rtcvdbg("ERROR: Invalid ALARM%d\n", alminfo->as_id);
+ rtcvdbg("ERROR: Invalid ALARM%d\n", alarmid);
break;
}
--
GitLab
From 8ca5daf2b3f5faef9a971e1884e1a67f887ecd43 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Tue, 31 May 2016 15:52:56 -0600
Subject: [PATCH 022/400] Changes from review of last PR
---
arch/arm/src/stm32/stm32f40xxx_rtcc.c | 32 +++++++++++++++++++--------
1 file changed, 23 insertions(+), 9 deletions(-)
diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
index 165c3c0247..448f54dea7 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
@@ -219,7 +219,9 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg);
#ifdef CONFIG_DEBUG_RTC
static void rtc_dumpregs(FAR const char *msg)
{
- rtclldbg("*** %s:\n", msg);
+ int rtc_state;
+
+ rtclldbg("%s:\n", msg);
rtclldbg(" TR: %08x\n", getreg32(STM32_RTC_TR));
rtclldbg(" DR: %08x\n", getreg32(STM32_RTC_DR));
rtclldbg(" CR: %08x\n", getreg32(STM32_RTC_CR));
@@ -240,11 +242,12 @@ static void rtc_dumpregs(FAR const char *msg)
rtclldbg("ALRMASSR: %08x\n", getreg32(STM32_RTC_ALRMASSR));
rtclldbg("ALRMBSSR: %08x\n", getreg32(STM32_RTC_ALRMBSSR));
rtclldbg("MAGICREG: %08x\n", getreg32(RTC_MAGIC_REG));
- int rtc_state =
- ((getreg32(STM32_EXTI_RTSR) & EXTI_RTC_ALARM) ? 0x1000 : 0) |
- ((getreg32(STM32_EXTI_FTSR) & EXTI_RTC_ALARM) ? 0x0100 : 0) |
- ((getreg32(STM32_EXTI_IMR) & EXTI_RTC_ALARM) ? 0x0010 : 0) |
- ((getreg32(STM32_EXTI_EMR) & EXTI_RTC_ALARM) ? 0x0001 : 0);
+
+ rtc_state =
+ ((getreg32(STM32_EXTI_RTSR) & EXTI_RTC_ALARM) ? 0x1000 : 0) |
+ ((getreg32(STM32_EXTI_FTSR) & EXTI_RTC_ALARM) ? 0x0100 : 0) |
+ ((getreg32(STM32_EXTI_IMR) & EXTI_RTC_ALARM) ? 0x0010 : 0) |
+ ((getreg32(STM32_EXTI_EMR) & EXTI_RTC_ALARM) ? 0x0001 : 0);
rtclldbg("EXTI (RTSR FTSR ISR EVT): %01x\n",rtc_state);
}
#else
@@ -1075,7 +1078,6 @@ int up_rtc_initialize(void)
#endif
g_rtc_enabled = true;
-
return OK;
}
@@ -1377,14 +1379,20 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
cbinfo->ac_cb = alminfo->as_cb;
cbinfo->ac_arg = alminfo->as_arg;
+ /* REVIST: Note that the alarm time is forced to lie within 24
+ * hours by using the flag RTC_ALRMR_DIS_DATE_MASK. If this mask
+ * is not et then the date tens:units need to be set up.
+ */
+
ret = rtchw_set_alrmar(alarmreg | RTC_ALRMR_ENABLE | RTC_ALRMR_DIS_DATE_MASK);
if (ret < 0)
{
cbinfo->ac_cb = NULL;
cbinfo->ac_arg = NULL;
}
+
+ rtc_dumpregs("Set AlarmA");
}
- rtc_dumpregs("Set AlarmA");
break;
case RTC_ALARMB:
@@ -1393,14 +1401,20 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
cbinfo->ac_cb = alminfo->as_cb;
cbinfo->ac_arg = alminfo->as_arg;
+ /* REVIST: Note that the alarm time is forced to lie within 24
+ * hours by using the flag RTC_ALRMR_DIS_DATE_MASK. If this mask
+ * is not et then the date tens:units need to be set up.
+ */
+
ret = rtchw_set_alrmbr(alarmreg | RTC_ALRMR_ENABLE | RTC_ALRMR_DIS_DATE_MASK);
if (ret < 0)
{
cbinfo->ac_cb = NULL;
cbinfo->ac_arg = NULL;
}
+
+ rtc_dumpregs("Set AlarmB");
}
- rtc_dumpregs("Set AlarmB");
break;
default:
--
GitLab
From 15810946b1bc0db4987b415c0232cf8ac1d59fcd Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Tue, 31 May 2016 17:28:02 -0600
Subject: [PATCH 023/400] Update some comments
---
arch/arm/src/stm32/stm32f40xxx_rtcc.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
index 448f54dea7..6623efa711 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
@@ -1365,7 +1365,11 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
rtc_dumptime(&alminfo->as_time, "New alarm time");
- /* Break out the values to the HW alarm register format */
+ /* Break out the values to the HW alarm register format.
+ * REVISIT: rtc_reg_alrmr_bin2bcd() sets only the hour, minute, seconds
+ * field. It does not set the month or year fields. This breaks the
+ * alarm for times > 24 hours. THIS NEEDS TO BE FIXED!!!
+ */
alarmreg = rtc_reg_alrmr_bin2bcd(&alminfo->as_time);
@@ -1381,7 +1385,8 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
/* REVIST: Note that the alarm time is forced to lie within 24
* hours by using the flag RTC_ALRMR_DIS_DATE_MASK. If this mask
- * is not et then the date tens:units need to be set up.
+ * is not set then the date tens:units need to be set up. See the
+ * rtc_reg_alrmr_bin2bcd() macro.
*/
ret = rtchw_set_alrmar(alarmreg | RTC_ALRMR_ENABLE | RTC_ALRMR_DIS_DATE_MASK);
@@ -1403,7 +1408,8 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
/* REVIST: Note that the alarm time is forced to lie within 24
* hours by using the flag RTC_ALRMR_DIS_DATE_MASK. If this mask
- * is not et then the date tens:units need to be set up.
+ * is not set then the date tens:units need to be set up. See the
+ * rtc_reg_alrmr_bin2bcd() macro.
*/
ret = rtchw_set_alrmbr(alarmreg | RTC_ALRMR_ENABLE | RTC_ALRMR_DIS_DATE_MASK);
--
GitLab
From 6eac8bf28dc20c1ec88f7d885272cd05395195ef Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Tue, 31 May 2016 17:31:15 -0600
Subject: [PATCH 024/400] Update some comments
---
arch/arm/src/stm32/stm32f40xxx_rtcc.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
index 6623efa711..483bf4df28 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
@@ -108,7 +108,11 @@
# define RCC_XXX_RTCSEL_LSI RCC_BDCR_RTCSEL_LSI
# define RCC_XXX_RTCSEL_HSE RCC_BDCR_RTCSEL_HSE
-/* BCD conversions */
+/* BCD conversions.
+ * FIXME: rtc_reg_alrmr_bin2bcd() sets only the hour, minute, seconds
+ * field. It does not set the month or year fields. This breaks the
+ * alarm for times > 24 hours. THIS NEEDS TO BE FIXED!!!
+ */
#define rtc_reg_tr_bin2bcd(tp) \
((rtc_bin2bcd((tp)->tm_sec) << RTC_TR_SU_SHIFT) | \
--
GitLab
From 70f2b47a0dffed0a880572f114ffba19a91a9e03 Mon Sep 17 00:00:00 2001
From: David Sidrane
Date: Tue, 31 May 2016 13:58:52 -1000
Subject: [PATCH 025/400] Fix the Value Line adc IRQ number selection
---
arch/arm/src/stm32/Kconfig | 1 -
arch/arm/src/stm32/stm32_adc.c | 53 +++++++++++++++++-----------------
2 files changed, 26 insertions(+), 28 deletions(-)
diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig
index 1da3821f82..fc5eb833b5 100644
--- a/arch/arm/src/stm32/Kconfig
+++ b/arch/arm/src/stm32/Kconfig
@@ -1182,7 +1182,6 @@ config STM32_VALUELINE
select STM32_HAVE_TIM15
select STM32_HAVE_TIM16
select STM32_HAVE_TIM17
- select STM32_HAVE_ADC2
select STM32_HAVE_SPI2 if STM32_HIGHDENSITY
select STM32_HAVE_SPI3 if STM32_HIGHDENSITY
diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c
index c24a98dbc7..5e34110fc9 100644
--- a/arch/arm/src/stm32/stm32_adc.c
+++ b/arch/arm/src/stm32/stm32_adc.c
@@ -344,22 +344,20 @@ static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset);
/* ADC Interrupt Handler */
static int adc_interrupt(FAR struct adc_dev_s *dev);
-#ifdef CONFIG_STM32_STM32L15XX
+#if defined(STM32_IRQ_ADC1) && defined(CONFIG_STM32_ADC1)
static int adc1_interrupt(int irq, FAR void *context);
#endif
-#if (defined(CONFIG_STM32_STM32F10XX) || \
- defined(CONFIG_STM32_STM32F30XX)) && \
- (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2))
+#if defined(STM32_IRQ_ADC12) && (defined(CONFIG_STM32_ADC1) || \
+ defined(CONFIG_STM32_ADC2))
static int adc12_interrupt(int irq, FAR void *context);
#endif
-#if (defined(CONFIG_STM32_STM32F10XX) || \
- defined(CONFIG_STM32_STM32F30XX)) && defined(CONFIG_STM32_ADC3)
+#if (defined(STM32_IRQ_ADC3) && defined(CONFIG_STM32_ADC3))
static int adc3_interrupt(int irq, FAR void *context);
#endif
-#if defined(CONFIG_STM32_STM32F30XX) && defined(CONFIG_STM32_ADC4)
+#if defined(STM32_IRQ_ADC4) && defined(CONFIG_STM32_ADC4)
static int adc4_interrupt(int irq, FAR void *context);
#endif
-#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+#if defined(STM32_IRQ_ADC)
static int adc123_interrupt(int irq, FAR void *context);
#endif
@@ -433,15 +431,17 @@ static const struct adc_ops_s g_adcops =
#ifdef CONFIG_STM32_ADC1
static struct stm32_dev_s g_adcpriv1 =
{
-#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
- .irq = STM32_IRQ_ADC12,
- .isr = adc12_interrupt,
-#elif defined(CONFIG_STM32_STM32L15XX)
+#if defined(STM32_IRQ_ADC1)
.irq = STM32_IRQ_ADC1,
.isr = adc1_interrupt,
-#else
+#elif defined(STM32_IRQ_ADC12)
+ .irq = STM32_IRQ_ADC12,
+ .isr = adc12_interrupt,
+#elif defined(STM32_IRQ_ADC)
.irq = STM32_IRQ_ADC,
.isr = adc123_interrupt,
+#else
+# error "No STM32_IRQ_ADC1 STM32_IRQ_ADC12 or STM32_IRQ_ADC defined for CONFIG_STM32_ADC1"
#endif
.intf = 1,
.base = STM32_ADC1_BASE,
@@ -470,12 +470,14 @@ static struct adc_dev_s g_adcdev1 =
#ifdef CONFIG_STM32_ADC2
static struct stm32_dev_s g_adcpriv2 =
{
-#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
+#if defined(STM32_IRQ_ADC12)
.irq = STM32_IRQ_ADC12,
.isr = adc12_interrupt,
-#else
+#elif defined(STM32_IRQ_ADC)
.irq = STM32_IRQ_ADC,
.isr = adc123_interrupt,
+#else
+# error "No STM32_IRQ_ADC12 or STM32_IRQ_ADC defined for CONFIG_STM32_ADC2"
#endif
.intf = 2,
.base = STM32_ADC2_BASE,
@@ -504,12 +506,14 @@ static struct adc_dev_s g_adcdev2 =
#ifdef CONFIG_STM32_ADC3
static struct stm32_dev_s g_adcpriv3 =
{
-#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
+#if defined(STM32_IRQ_ADC3)
.irq = STM32_IRQ_ADC3,
.isr = adc3_interrupt,
-#else
+#elif defined(STM32_IRQ_ADC)
.irq = STM32_IRQ_ADC,
.isr = adc123_interrupt,
+#else
+# error "No STM32_IRQ_ADC3 or STM32_IRQ_ADC defined for CONFIG_STM32_ADC3"
#endif
.intf = 3,
.base = STM32_ADC3_BASE,
@@ -2781,7 +2785,7 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
*
****************************************************************************/
-#ifdef CONFIG_STM32_STM32L15XX
+#if defined(STM32_IRQ_ADC1)
static int adc1_interrupt(int irq, FAR void *context)
{
adc_interrupt(&g_adcdev1);
@@ -2802,8 +2806,7 @@ static int adc1_interrupt(int irq, FAR void *context)
*
****************************************************************************/
-#if (defined(CONFIG_STM32_STM32F10XX) || \
- defined(CONFIG_STM32_STM32F30XX)) && \
+#if defined(STM32_IRQ_ADC12) && \
(defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2))
static int adc12_interrupt(int irq, FAR void *context)
{
@@ -2831,8 +2834,7 @@ static int adc12_interrupt(int irq, FAR void *context)
*
****************************************************************************/
-#if (defined(CONFIG_STM32_STM32F10XX) || \
- defined(CONFIG_STM32_STM32F30XX)) && defined(CONFIG_STM32_ADC3)
+#if defined(STM32_IRQ_ADC3) && defined(CONFIG_STM32_ADC3)
static int adc3_interrupt(int irq, FAR void *context)
{
adc_interrupt(&g_adcdev3);
@@ -2853,13 +2855,10 @@ static int adc3_interrupt(int irq, FAR void *context)
*
****************************************************************************/
-#if defined(CONFIG_STM32_STM32F30XX) && defined(CONFIG_STM32_ADC4)
+#if defined(STM32_IRQ_ADC4) && defined(CONFIG_STM32_ADC4)
static int adc4_interrupt(int irq, FAR void *context)
{
-#ifdef CONFIG_STM32_ADC4
adc_interrupt(&g_adcdev4);
-#endif
-
return OK;
}
#endif
@@ -2876,7 +2875,7 @@ static int adc4_interrupt(int irq, FAR void *context)
*
****************************************************************************/
-#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+#if defined(STM32_IRQ_ADC)
static int adc123_interrupt(int irq, FAR void *context)
{
#ifdef CONFIG_STM32_ADC1
--
GitLab
From 82dec4acab25a68bd0e42c10a56a4d80f3d77ccd Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Tue, 31 May 2016 19:13:21 -0600
Subject: [PATCH 026/400] STM32F4 RTC: Remove 24 hour limit; Fix calculation of
the alarm register (was not including day of the month). Fix a bad shift
value
---
arch/arm/src/stm32/stm32f40xxx_rtcc.c | 52 ++++++++-------------------
1 file changed, 14 insertions(+), 38 deletions(-)
diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
index 483bf4df28..a1f46513ef 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
@@ -108,22 +108,6 @@
# define RCC_XXX_RTCSEL_LSI RCC_BDCR_RTCSEL_LSI
# define RCC_XXX_RTCSEL_HSE RCC_BDCR_RTCSEL_HSE
-/* BCD conversions.
- * FIXME: rtc_reg_alrmr_bin2bcd() sets only the hour, minute, seconds
- * field. It does not set the month or year fields. This breaks the
- * alarm for times > 24 hours. THIS NEEDS TO BE FIXED!!!
- */
-
-#define rtc_reg_tr_bin2bcd(tp) \
- ((rtc_bin2bcd((tp)->tm_sec) << RTC_TR_SU_SHIFT) | \
- (rtc_bin2bcd((tp)->tm_min) << RTC_TR_MNU_SHIFT) | \
- (rtc_bin2bcd((tp)->tm_hour) << RTC_TR_HU_SHIFT))
-
-#define rtc_reg_alrmr_bin2bcd(tm) \
- ((rtc_bin2bcd((tm)->tm_sec) << RTC_ALRMR_SU_SHIFT) | \
- (rtc_bin2bcd((tm)->tm_min) << RTC_ALRMR_MNU_SHIFT) | \
- (rtc_bin2bcd((tm)->tm_hour) << RTC_ALRMR_HU_SHIFT))
-
/* Time conversions */
#define MINUTES_IN_HOUR 60
@@ -615,7 +599,7 @@ static void rtc_resume(void)
/* Clear the RTC Alarm Pending bit */
- putreg32((1 << EXTI_RTC_ALARM ), STM32_EXTI_PR);
+ putreg32(EXTI_RTC_ALARM, STM32_EXTI_PR);
#endif
}
@@ -1267,7 +1251,9 @@ int stm32_rtc_setdatetime(FAR const struct tm *tp)
* register.
*/
- tr = (rtc_reg_tr_bin2bcd(tp) & ~RTC_TR_RESERVED_BITS);
+ tr = (rtc_bin2bcd(tp->tm_sec) << RTC_TR_SU_SHIFT) |
+ (rtc_bin2bcd(tp->tm_min) << RTC_TR_MNU_SHIFT) |
+ (rtc_bin2bcd(tp->tm_hour) << RTC_TR_HU_SHIFT);
/* Now convert the fields in struct tm format to the RTC date register fields:
* Days: 1-31 match in both cases.
@@ -1369,14 +1355,16 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
rtc_dumptime(&alminfo->as_time, "New alarm time");
- /* Break out the values to the HW alarm register format.
- * REVISIT: rtc_reg_alrmr_bin2bcd() sets only the hour, minute, seconds
- * field. It does not set the month or year fields. This breaks the
- * alarm for times > 24 hours. THIS NEEDS TO BE FIXED!!!
+ /* Break out the values to the HW alarm register format. The values in
+ * all STM32 fields match the fields of struct tm in this case. Notice
+ * that the alarm is limited to one month.
*/
- alarmreg = rtc_reg_alrmr_bin2bcd(&alminfo->as_time);
-
+ alarmreg = (rtc_bin2bcd(alminfo->as_time.tm_sec) << RTC_ALRMR_SU_SHIFT) |
+ (rtc_bin2bcd(alminfo->as_time.tm_min) << RTC_ALRMR_MNU_SHIFT) |
+ (rtc_bin2bcd(alminfo->as_time.tm_hour) << RTC_ALRMR_HU_SHIFT) |
+ (rtc_bin2bcd(alminfo->as_time.tm_mday) << RTC_ALRMR_DU_SHIFT);
+
/* Set the alarm in hardware and enable interrupts */
switch (alminfo->as_id)
@@ -1387,13 +1375,7 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
cbinfo->ac_cb = alminfo->as_cb;
cbinfo->ac_arg = alminfo->as_arg;
- /* REVIST: Note that the alarm time is forced to lie within 24
- * hours by using the flag RTC_ALRMR_DIS_DATE_MASK. If this mask
- * is not set then the date tens:units need to be set up. See the
- * rtc_reg_alrmr_bin2bcd() macro.
- */
-
- ret = rtchw_set_alrmar(alarmreg | RTC_ALRMR_ENABLE | RTC_ALRMR_DIS_DATE_MASK);
+ ret = rtchw_set_alrmar(alarmreg | RTC_ALRMR_ENABLE);
if (ret < 0)
{
cbinfo->ac_cb = NULL;
@@ -1410,13 +1392,7 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
cbinfo->ac_cb = alminfo->as_cb;
cbinfo->ac_arg = alminfo->as_arg;
- /* REVIST: Note that the alarm time is forced to lie within 24
- * hours by using the flag RTC_ALRMR_DIS_DATE_MASK. If this mask
- * is not set then the date tens:units need to be set up. See the
- * rtc_reg_alrmr_bin2bcd() macro.
- */
-
- ret = rtchw_set_alrmbr(alarmreg | RTC_ALRMR_ENABLE | RTC_ALRMR_DIS_DATE_MASK);
+ ret = rtchw_set_alrmbr(alarmreg | RTC_ALRMR_ENABLE);
if (ret < 0)
{
cbinfo->ac_cb = NULL;
--
GitLab
From 90ccba1ad01cc7e3a15566c882b06210dc2237f1 Mon Sep 17 00:00:00 2001
From: Frank Benkert
Date: Wed, 1 Jun 2016 10:38:19 -0600
Subject: [PATCH 027/400] SAMV7: MCAN: fix missing unlock of device in
mcan_txempty
---
arch/arm/src/samv7/sam_mcan.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c
index f1f8f788a2..f7b9e31592 100644
--- a/arch/arm/src/samv7/sam_mcan.c
+++ b/arch/arm/src/samv7/sam_mcan.c
@@ -2905,6 +2905,7 @@ static bool mcan_txempty(FAR struct can_dev_s *dev)
regval = mcan_getreg(priv, SAM_MCAN_TXFQS_OFFSET);
if (((regval & MCAN_TXFQS_TFQF) != 0))
{
+ mcan_dev_unlock(priv);
return false;
}
--
GitLab
From 692ea396e3459cb42420509081be04ce27327217 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Wed, 1 Jun 2016 15:45:23 -0600
Subject: [PATCH 028/400] Prep for NuttX-7.16 release
---
ChangeLog | 24 ++-
Documentation/NuttX.html | 108 +++++++++---
ReleaseNotes | 362 +++++++++++++++++++++++++++++++++++++++
3 files changed, 460 insertions(+), 34 deletions(-)
diff --git a/ChangeLog b/ChangeLog
index 7722d45c88..ab23bf83e2 100755
--- a/ChangeLog
+++ b/ChangeLog
@@ -11586,7 +11586,7 @@
* configs/stm32l476vg-disco: Add support for the STM32L476VG Discovery
board. From Dave (2016-03-25).
-7.16 2016-xx-xx Gregory Nutt
+7.16 2016-06-01 Gregory Nutt
* PM: Add activity domain to all PM interfaces and driver callbacks. If
CONFIG_PM_NDOMAINS == 1, then the legacy behavior is preserved. If
@@ -11615,7 +11615,7 @@
* STM3220G-EVAL: Add support for both the IAR and uVision GCC IDEs
From Kha Vo (2016-04-08).
* STM32F429I Discovery: Add support for the uVision GCC IDE. From
- * Kha Vo (2016-04-08).
+ Kha Vo (2016-04-08).
* libc/signal and include/signal.h: Rename sigset() to signal().
sigset() is the System V function; signal() is the obsoleted POSIX
name. These seem to be equivalent. Neither are relevant in modern
@@ -11640,7 +11640,7 @@
is interpreted as a packed dual frame exchange. Sebastien Lorquet
(2016-04-13).
* net/sockets/listen.c and accept.c and include/nuttx/net: Separate
- out psock_listen() and psock_accepti() for internal OS usage
+ out psock_listen() and psock_accept() for internal OS usage
(2016-04-14).
* fs/inode/, fs/vfs/, and sched/task/: File and socket descriptors are
no longer allocated for kernel threads. They must use SYSLOG for
@@ -11753,7 +11753,7 @@
* arch/srm/src/stm32l4: Add CAN support for STM32L4. From Sebastien
Lorquet (2016-05-19).
* arch/arm/src/samv7: Adds a JTAG config and ERASE config to Kconfig to
- set the CCFG_SYSIO SYSIO Pins. From Davide Sidrane (2016-05-19).
+ set the CCFG_SYSIO SYSIO Pins. From David Sidrane (2016-05-19).
* arch/sim/src: Enhance networking support for the simulation under Linux.
Includes updated support for Linux TUN/TAP, and the addition of support
for Linux bridge devices. From Steve (2016-05-20).
@@ -11767,7 +11767,7 @@
configurations (2016-05-22).
* include/nuttx/crypto/aes.h: Modifications to the crypto API needed
for LPC43xx. From Alexander Vasiljev (2016-05-23).
- * arch/arm/src/lpc32xx: Add AES support. From Alexander Vasiljev
+ * arch/arm/src/lpc43xx: Add AES support. From Alexander Vasiljev
(2016-05-24).
* configs/*/src/tiva_timer.c: Tiva boards: Fix a naming collision,
rename board-specific function from tiva_timer_initialize() to
@@ -11830,7 +11830,7 @@
* drivers/: Several SPI-based drivers modified. All drivers that use
SPI must call SPI_LOCK and SPI_UNLOCK. This is not optional
(2016-05-26).
- * drivers/sensosrs: Fix a bug in crc computation for ms583730.
+ * drivers/sensors: Fix a bug in crc computation for ms583730.
Implement POSIX read (2016-05-27).
* arch/arm/src/samv7: This is a fix to a problem in the handling of the
oneshot timer. Due to a wrong assumption concerning the behavior
@@ -11842,7 +11842,7 @@
counter register to zero, but the reset of the counter register is not
performed instantly. According to the datasheet: "The counter can be
reset by a trigger. In this case, the counter value passes to zero on
- the next valid edge of the selected clock.” Thus the counter is set to
+ the next valid edge of the selected clock." Thus the counter is set to
zero between 0 and USEC_PER_TICK microseconds after the clock was
started.
In my fix I use the freerun count value to determine if at least one
@@ -11869,3 +11869,13 @@
are identical (2016-05-29).
* arch/arm/src/stm32: Allow to not use all channel in a lower part of
PWM. From Pierre-noel Bouteville (2016-05-30).
+ * libc/math: Add a NAN test on 'x' in asin function of lib_asin.c.
+ Suggested by Pierre-noel Bouteville (2016-05-31).
+ * arch/arm/src/stm32: Fix logic in F4 RTCC driver that prevent ALARM
+ interrupt. From Neil Hancock (2016-05-31).
+ * arch/arm/src/stm32: Fix STM32 ValueLine ADC IRQ number selection.
+ From David Sidrane (2016-05-31).
+ * arch/arm/src/samv7: Fix missing unlock of device in MCAN
+ mcan_txempty(). From Frank Benkert (2016-06-01).
+
+7.17 2016-xx-xx Gregory Nutt
diff --git a/Documentation/NuttX.html b/Documentation/NuttX.html
index 9910e4c275..83c42c61cf 100644
--- a/Documentation/NuttX.html
+++ b/Documentation/NuttX.html
@@ -8,7 +8,7 @@
NuttX RTOS
- Last Updated: April 12, 2016
+ Last Updated: June 1, 2016
|
@@ -1340,11 +1340,11 @@
Released Versions
In addition to the ever-changing GIT repository, there are frozen released versions of NuttX available.
- The current release is NuttX 7.15.
- NuttX 7.15 is the 115th release of NuttX.
- It was released on March 27, 2016, and is available for download from the
+ The current release is NuttX 7.16.
+ NuttX 7.16 is the 116th release of NuttX.
+ It was released on June 1, 2016, and is available for download from the
Bitbucket.org website.
- Note that the release consists of two tarballs: nuttx-7.15.tar.gz
and apps-7.15.tar.gz
.
+ Note that the release consists of two tarballs: nuttx-7.16.tar.gz
and apps-7.16.tar.gz
.
Both may be needed (see the top-level nuttx/README.txt
file for build information).
@@ -1353,7 +1353,7 @@
- nuttx.
- Release notes for NuttX 7.15 are available here.
+ Release notes for NuttX 7.16 are available here.
Release notes for all released versions on NuttX are available in the Bitbucket GIT.
The ChangeLog for all releases of NuttX is available in the ChangeLog file that can viewed in the Bitbucket GIT.
The ChangeLog for the current release is at the bottom of that file.
@@ -1361,7 +1361,7 @@
- apps.
- Atmel AVR
@@ -2257,7 +2257,7 @@
NXP/Freescale i.MX6.
- A port is underway for the following i.MX6 board
+ The basic port has been completed for the following i.MX6 board
-
@@ -2268,9 +2268,13 @@
STATUS:
- The basic, minimal port is code complete and introduced in NuttX-7.15, but has not yet been tested.
- I am still waiting for the reciept of the Sabre board.
- Expect to see the verified Sabre-6Quad support (with SMP!) in NuttX-7.16.
+ The basic, minimal port is code complete and introduced in NuttX-7.15, but had not yet been tested at that time due to the inavailability of hardware.
+ This basic port was verified in the NuttX-7.16 release, however.
+ The port is still mininal and more device drivers are needed to make the port usable.
+
+
+ Basic support of NuttX running in SMP mode on the i.MX6Q was also accomplished in NuttX-7.16.
+ However, there are still known issues with SMP support on this platform as described in the README file for the board.
@@ -2907,13 +2911,26 @@ nsh>
|
STMicro STM32F103C4/8 (STM32 F1 Low- and Medium-Density Family).
- This port is for "STM32 Tiny" development board.
- This board is available from several vendors on the net, and may be sold under different names.
- It is based on a STM32 F103C8T6 MCU, and is bundled with a nRF24L01 wireless communication module.
+ There are two ports available for this family:
-
- STATUS:
+ -
+
+ One port is for "STM32 Tiny" development board.
+ This board is available from several vendors on the net, and may be sold under different names.
+ It is based on a STM32 F103C8T6 MCU, and is bundled with a nRF24L01 wireless communication module.
+
+
+ -
+
+ The other port is for a generic minimual STM32F103CBT6 "blue" board contributed by Alan Carvalho de Assis.
+
+
+
+
+ STATUS:
+
+
The basic STM32F103C8 port was released in NuttX version 6.28.
This work was contributed by Laurent Latil.
Refer to the NuttX board README file for further information.
@@ -3160,11 +3177,17 @@ nsh>
- STATUS:
- The peripherals of the STM32 F2 family are compatible with the STM32 F4 family.
- See discussion of the STM3240G-EVAL board below for further information.
- Refer also to the NuttX board README file for further information.
-
+
+ STATUS:
+ The peripherals of the STM32 F2 family are compatible with the STM32 F4 family.
+ See discussion of the STM3240G-EVAL board below for further information.
+ Refer also to the NuttX board README file for further information.
+
+
+ Support for both the IAR and uVision GCC IDEs added for the STM3220G-EVAL board in NuttX 7.16.
+ From Kha Vo.
+
+
|
@@ -3779,6 +3802,10 @@ nsh>
In Nutt-7.7, Marco Krahl included support for a framebuffer based driver using the LTDC and DMA2D.
Marcos's implementation included extensions to support more advance LTDC functions through an auxiliary interface.
+ -
+ Support for the uVision GCC IDE added for theSTM32F429I-Discovery board in NuttX 7.16.
+ From Kha Vo.
+
Refer to the STM32F429I-Discovery board README file for further information.
@@ -3853,6 +3880,15 @@ nsh>
- UART, USART, Serial Console
- GPIO, DMA, I2C, RNG, SPI
+
+ NuttX-7.16.
+ Additional drivers were contributed:
+
+
+ - QSPI with DMA and memory mapped support. From Dave (ziggurat29).
+ - CAN contributed by Sebastien Lorquet.
+ - I2C made functional by Dave (ziggurat29).
+
@@ -3968,6 +4004,13 @@ nsh>
The NXP WaveShare LPC4337-WS port is was contributed by Lok Tep and first released in NuttX-7.14.
+
+ NuttX-7.16
+ Support for the LPC4337JET100 chip was contribed by Alexander Vasiljev.
+ Alexander also contributed an LPC43xx AES driver available in NuttX-7.16.
+
+
+
@@ -4407,13 +4450,24 @@ Mem: 29232 5920 23312 23312
STMicro STM32 F745/F746.
- This port uses the STMicro STM32F746G-DISCO development board featuring the STM32F746NGH6 MCU. The STM32F746NGH6 is a 216MHz Cortex-M7 operation with 1024Kb Flash.
- Refer to the STMicro web site for further information about this board.
+ Two boards are supported for this MCU:
- STATUS:
- The basic port is complete and there are two, verified configurations available.
+ STM32F746G Discovery.
+ One port uses the STMicro STM32F746G-DISCO development board featuring the STM32F746NGH6 MCU. The STM32F746NGH6 is a 216MHz Cortex-M7 operation with 1024Kb Flash.
+ Refer to the STMicro web site for further information about this board.
+
+
+ A basic port for the Nucleo-144 board with the STM32F746ZG MCU was contribued in NuttX-7.16 by Kconstantin Berezenko.
+
+
+
+ STATUS:
+
+
+
+ The basic STM32F746G-DISCO port is complete and there are two, verified configurations available.
Both configurations use the NuttShell (NSH) and a serial console; one includes Ethernet support.
DMA supports is available.
The STM32 F7 peripherals are very similar to some members of the STM32 F4 and additional drivers can easily be ported the F7 as discussed in this Wiki page: Porting Drivers to the STM32 F7
diff --git a/ReleaseNotes b/ReleaseNotes
index 89cf4119a4..71516d18af 100644
--- a/ReleaseNotes
+++ b/ReleaseNotes
@@ -10716,3 +10716,365 @@ detailed bugfix information):
- Moved C++ initialization logic out of the RTOS and into the
application space, specifically to apps/platform/board, where it
belongs.
+
+NuttX-7.16 Release Notes
+------------------------
+
+The 116th release of NuttX, Version 7.16, was made on June 1, 2016,
+and is available for download from the Bitbucket.org website. Note
+that release consists of two tarballs: nuttx-7.16.tar.gz and
+apps-7.16.tar.gz. These are available from:
+
+ https://bitbucket.org/nuttx/nuttx/downloads
+ https://bitbucket.org/nuttx/apps/downloads
+
+Both may be needed (see the top-level nuttx/README.txt file for build
+information).
+
+Additional new features and extended functionality:
+
+ * Core OS:
+
+ - Power Management: Add activity domain to all PM interfaces and
+ driver callbacks. If CONFIG_PM_NDOMAINS == 1, then the legacy
+ behavior is preserved. If CONFIG_PM_NDOMAINS > 1, then multiple
+ PM domains are supported. This will allow separate control for
+ certain power management groups. For example, a network can be
+ shut down without affect an ongoing UI (and vice versa).
+ - board_app_initialize(): board_app_initialize() now accepts an
+ argument that may be used to support initialization in different
+ configurations.
+
+ * File System and Block and MTD Drivers:
+
+ - N25Qxxx: Add MTD support for Micron N25Qxxx family of QSPI flash.
+ From Dave (ziggurat29).
+ - SST26F: Add an MTD driver for SST26F spi/qspi flash devices (SPI
+ mode only). From Sebastien Lorquet.
+ - File Descriptor Detach: Add logic to detach a file structure from a
+ file descriptor. This is for use only within the OS. It permits an
+ open file or driver to be used across multiple threads.
+
+ * Networking and Network Drivers:
+
+ - listen()/accept(): Separate out psock_listen() and psock_accepti()
+ for internal, thread independent OS usage (i.e., without a socket
+ descriptor).
+ - VNC Server: Add support for a VNC server. This logic is code
+ complete and functional, but not well tested.
+
+ * Graphics and Graphic Drivers:
+
+ - Framebuffer driver: Add a display number to each interface in order
+ to support multiple display devices.
+ - VNC Server: Add support for a VNC server. This logic is code
+ complete and functional, but not well tested.
+ - LCD Backpack: Add support for PCF8574 LCD Backpack driver. This
+ driver supports an interface board that is based on the PCF8574 I/O
+ expander and supports the HD44780-based (or compatible) LCD modules.
+ There are a myriad of different vendors of such, but they are
+ principally the same, save wiring and minor features like jumpers
+ for I2C addresses. This driver supports known and unknown variants.
+ From Dave (ziggurat29).
+
+ * Common Device Drivers:
+
+ - RTC: Simplify the RTC interface. The old interface was way too
+ complex and was not fully implemented anywhere.
+ - BH1750FVI: Add a character driver for Rohm Ambient Light Sensor
+ BH1750FVI. From Alan Carvalho de Assis.
+ - CAN: Improve CAN error reporting. From Frank Benkert.
+ - aes.h: Modifications to the crypto API needed for LPC43xx. From
+ Alexander Vasiljev.
+ - ADC: Interface no longer uses global adc_receive() call. Added a
+ new bind() method to the ADC interface. Now the ADC upper half
+ driver will register its receipt-of-data callback. This change
+ allows the ADC lower half driver to be used with a differ ADC upper
+ half.
+
+ * Simulation Platform:
+
+ - Linux Host Networking: Enhance networking support for the
+ simulation under Linux. Includes updated support for Linux TUN/TAP,
+ and the addition of support for Linux bridge devices. From Steve.
+
+ * ARMv7-A, ARMv7-R, and ARMv7-M:
+
+ - ARMv7-M: Convert more assembly language files for use with the IAR
+ toolchain. From Kha Vo.
+ - ARMv7-A: Complete re-design of SMP-related logic to initialize each
+ CPUn, n > 0, when CONFIG_SMP=y.
+
+ * Atmel SAMV7:
+
+ - Add a JTAG config and ERASE config to Kconfig to set the
+ CCFG_SYSIO SYSIO Pins. From David Sidrane.
+ - System Reset: Add the up_systemreset interface to the samv7 arch. The
+ approach is slightly different in that: 1) It enables ARCH_HAVE_RESET
+ and allows the user to set if, and for how long, to drive External
+ nRST signal. It also does not contain a default board_reset, as that
+ really should be done in the config's src if CONFIG_BOARDCTL_RESET
+ is defined. From David Sidrane.
+
+ * Atmel SAMV7 Boards:
+
+ - SAMV71-XULT: Add configuration(s) that were be used to verify VNC
+ graphics output as well as mouse and keyboard input.
+
+ * NXP Freescale i.MX6 Boards:
+
+ - Sabre-6Quad: The basic i.MX6 port is complete. This is a minimal
+ port at present and probably still has some as-of-yet-undiscovered
+ issues.
+ - Sabre-6Quad: Basic SMP NSH configuration is now working. But this
+ is probably only because the SMP test case does not stress the
+ logic. There are know outstanding SMP issues as noted in the
+ Sabre-6Quad README.txt file.
+
+ * NXP Freescale LPC43xx:
+
+ - LPC4337jet100: Add definitions for the LPC4337jet100 chip. From
+ Alexander Vasiljev.
+
+ * NXP Freescale LPC43xx Drivers:
+
+ - AES: Add AES support. From Alexander Vasiljev.
+
+ * STMicro STM32:
+
+ - STM32 L4: Add configuration options to allow SRAM2 to be used for
+ heap, or not at all, and to zero-initialize it on OS start, or not
+ at all. From Dave dev@ziggurat29.com.
+ - STM32 L4: Add support for HSE and MSI clocks, and auto trim of MSI
+ to LSE (needed for USB). From Dave (ziggurat29)
+ - STM32 L4: Add support for unique id function to arch; modified board
+ to support unique id boardctl. From Dave (ziggurat29)
+
+ * STMicro STM32 Drivers:
+
+ - STM32 F4 RTC: Add a custom RTC driver with support for alarms. From
+ Neil Hancock.
+ - STM32 L4 QSPI: Add a QSPI driver with DMA support and (optional
+ memory mapped mode support. From Dave ziggurat29).
+ - STM32, STM32 L4, and STM32 F7 Serial: Add support for compliant
+ SD-style breaks. From David Sidrane.
+ - STM32 L4 CAN: Add CAN support for STM32L4. From Sebastien Lorquet.
+ - STM32 1-Wire: Add support for a custom 1-wire driver. The serial
+ driver already supports a 1-wire interface, but this driver uses the
+ same serial logic to implement a lower half driver much like the
+ I2C lower half driver. From Aleksandr Vyhovanec.
+ - STM32 L4 SPI: Add support for SPI 4 and 5 on stm32f411 chips. From
+ Konstantin Berezenko.
+ - STM32 ADC: Allow omitting use of channels in a lower part of PWM.
+ From Pierre-noel Bouteville.
+ - STM32 L4 I2C: Get I2C working for STM32L4. From Dave (ziggurat29).
+
+ * STMicro STM32 Boards:
+
+ - STM3220G-EVAL: Add support for both the IAR and uVision GCC IDEs.
+ From Kha Vo.
+ - STM32F429I Discovery: Add support for the uVision GCC IDE. From
+ Kha Vo.
+ - STM32F4 Discovery: Integrate BH1750FVI driver in the STM32F4 Discovery
+ board. From Alan Carvalho de Assis.
+ - STM32L476VG Discovery: Add support for QSPI based N25Qxxx flash.
+ From Dave (ziggurat29)
+ - STM32L476VG Discovery: Add board ioctls for allowing user application
+ to cause QSPI memory mapped mode to be engaged and disengaged. Also
+ partitioned QSPI flash for file system and other (eventually xip).
+ From Dave (ziggurat29)
+ - Nucleo-144: Basic port for the Nucleo-144 board with the STM32F746ZG
+ MCU. From Kconstantin Berezenko.
+ - STM32F103 Minimum: Add support for this minimual STM32F103CBT6 "blue"
+ board. From Alan Carvalho de Assis.
+ - STM32F411E Discovery: Add basic configuration for stm32f411e-disco
+ board with STM32F411VE chip. From Konstantin Berezenko.
+
+ * Build/Configuration System:
+
+ - Moved NuttX repository to https://bitbucket.org/nuttx/nuttx.
+ Eliminated use of sub-modules.
+ - Add support for the IAR toolchain for the limited case of the ARMv7-M
+ architecture and the STM32 chip. From Aleksandr Vyhovanec.
+ - make export: Pass top-level make to the script to allow -j greater
+ than 1. From David Sidrane.
+ - fs/Kconfig: Allow CONFIG_FS_WRITABLE to be manually selectable. This
+ is needed when there are no writable file systems, but write support
+ is still needed in BCH or FTL.
+ - arch/*/Makefile: Add definitions that can be overrided to use GCC
+ instead of LD in the final link. From Paul Alexander Patience .
+
+ * Applications: apps/netutils:
+
+ - apps/netutils/esp8266: ESP8266 driver application. From Pierre-noel
+ Bouteville.
+
+ * Applications: apps/examples:
+
+ - apps/examples/alarm: Add a simple test of the ALARM iotcl calls of
+ the RTC driver.
+ - apps/examples/nximage: Add a configuration option to select
+ greyscale.
+
+ * Platforms: apps/platform:
+
+ - apps/platform/nucleo-144: Add platform files for NUCLEO-144
+ (NUCLEO-F746ZG). From Mark Olsson.
+ - apps/examples/media: You can now override the default device driver
+ path by providing an alternal path on the command line. From
+ Sbastien Lorquet.
+
+Works-In-Progress:
+
+ * IEEE802.14.5/6LowPAN. Hooks and framework for this effort were
+ introduced in NuttX-7.15. Work has continued on this effort on
+ forks from the main repositories, albeit with many interruptions.
+ The completion of this wireless feature will postponed until at
+ least NuttX-7.17.
+
+ * i.MX6 SMP. Partially functional, but there is more that still
+ needs to be done.
+
+Bugfixes. Only the most critical bugfixes are listed here (see the
+ChangeLog for the complete list of bugfixes and for additional, more
+detailed bugfix information):
+
+ * Core OS:
+
+ - Various places: Search for places where a stray semicolon following
+ an if condition cause the if body to be executed unconditionally.
+ Fixes in all SAM DMA logic, unionfs, OS signalling logic, and others.
+ - enter/leave_critical_section() may attempt to access task lists
+ before they have been initialized in the SMP configuration.
+
+ * File System/Block Drivers:
+
+ - SMART MTD: Return code of smart_scan not checked, can cause success
+ result in failure case, leading to 'dev' pointer being invalid. From
+ Dave (ziggurat29)
+ - mount: Fix a backward debug assertion. Noted by David Sidrane.
+
+ * Common Drivers:
+
+ - NRF24L01: Fix backward calculation of relative frequency. Noted by
+ Henry Zhang.
+ - PCA9555 I/O expander: Fix an error in the PCA9555 driver: Under
+ certain error conditions, interrupts were not being re-enabled.
+ Sebastien Lorquet.
+ - ADS1255: Must not do SPI access from interrupt handler. Use the
+ worker thread instead. Must also lock the SPI bus before using it.
+ - Several SPI-based drivers modified. All drivers that use SPI must
+ call SPI_LOCK and SPI_UNLOCK. This is not optional.
+ - MS583730: Fix a bug in crc computation for ms583730. Implement
+ POSIX read.
+
+ * Atmel SAMV7:
+
+ - Fix typo in MATRIX register definitions. From Stefan Kolb.
+ - SAMV7 Tickless Mode: This is a fix to a problem in the handling of
+ the oneshot timer. Due to a wrong assumption concerning the behavior
+ directly after the start of the timer/counter the function
+ sam_oneshot_cancel() calculates the wrong remaining time. The code
+ assumes that the counter register is zero directly after the start
+ of the timer, but this is not true. To start the time/counter a
+ software trigger is invoked, this trigger starts the timer/count and
+ sets the counter register to zero, but the reset of the counter
+ register is not performed instantly. According to the datasheet:
+ "The counter can be reset by a trigger. In this case, the counter
+ value passes to zero on the next valid edge of the selected clock."
+ Thus the counter is set to zero between 0 and USEC_PER_TICK
+ microseconds after the clock was started.
+ In my fix I use the freerun count value to determine if at least one
+ tick passed since the start of the timer and thus if the value of
+ the oneshot counter is correct. I also tried to use the function
+ up_timer_gettime() to achieve this but, at least if compiled with
+ no optimization the problem vanishes without using the value of the
+ function, the function call takes too long.
+ Another problem treated in the fix is that if the oneshot timer/counter
+ is canceled, we only know the remaining time with a precision of
+ USEC_PER_TICK microseconds. This means the calculated remaining time
+ is between 0 and USEC_PER_TICK microseconds too long. To fix this I
+ subtract one tick if the calculated remaining time is greater than
+ one tick and otherwise set the remaining time to zero. By doing so
+ the measured times are much more precise as without it. From Stefan
+ Kolb.
+
+ * Atmel SAMA5:
+
+ - SAMA5: Stefan Kolb's change to the SAMV7 Oneshot Timer should also
+ be applied to the SAMA5 oneshot time since the drivers are identical.
+
+ * Atmel SAM3/4:
+
+ - SAM3/4: Stefan Kolb's change to the SAMV7 Oneshot Timer should also
+ be applied to the SAM3/4 oneshot time since the drivers are identical.
+
+ * Atmel SAMV7 Drivers:
+
+ - SAMV7 TWIHS (as well as SAM3/4 and SAMA5: Ensure that the TWIHS
+ (i2c) hw get's its clock set when the sequence of
+ sam_i2cbus_initialize(), sam_i2cbus_uninitialize(), then
+ sam_i2cbus_initialize() or twi_reset() is called. I found this a
+ while back in the stm32 family, so there may be more arch-es with
+ this sort of bug. I suppose any driver that has the notion of "do
+ not set the freq if it is already set" could be suspect. From David
+ Sidrane.
+ - USBHS Device: Remove disabling of whole USB on suspend of USBHS.
+ This fix removes the disabling of the whole USB peripheral on
+ suspend interrupt. Its enough to freeze the clock instead. When
+ disabling the whole peripheral, the next wakeup-interrupt comes up
+ with an disabled clocking. The unfreeze clock has no effect, because
+ the master clock is disabled. This makes all registers, including
+ the IDR unwriteable and the IRQ falls in an endless loop blocking
+ the whole system. Furthermore the disabling of the peripheral clock
+ prevents hotplugging or reconnecting the USB. From Frank Benkert.
+ - MCAN: Fix missing unlock of device in MCAN mcan_txempty(). From
+ Frank Benkert.
+
+ * STMicro STM32:
+
+ - STM32 L4 Clocking: Problem with resetting backup domain clears
+ clocking options set up before in *rcc.c use INITS flag to avoid
+ magic reg value to detect power up reset state of RTC correct a
+ problem clearing interrupt flags (they weren't) which prevented an
+ alarm from ever being used more than once per reset cycle. From
+ Dave (ziggurat29)
+
+ * STMicro STM32 Drivers:
+
+ - STM32L4 SPI: That STM32Lr SPI driver is quite different. They now
+ handle frames of arbitrary size between 4 and 16 bits. It was broken
+ before a new bit has to be set (RX fifo threshold) to handle <= 8-bit
+ transactions. If not set, the default is 16-bit packed >=8-bit
+ frames and the RXNE bit is never set (it is set when 16-bits are
+ received). weird things as always. This also add 8-bit access
+ routines to the data register, because a 16-bit access to the data
+ register when the frame size is below 9 bits is interpreted as a
+ packed dual frame exchange. Sebastien Lorquet.
+ - STM32: Correct some bad commits that broke the LTDC display example.
+ From Marco Krahl.
+ - STM32 F4 RTC: Fix logic in F4 RTCC driver that prevent ALARM
+ interrupt. From Neil Hancock.
+ - STM32 F1 ADC: Fix STM32 ValueLine ADC IRQ number selection. From
+ David Sidrane.
+
+ * STMicro STM32 Boards:
+
+ - STM32F429I Discovery: Correct some bad commits that broke the LTDC
+ display example. From Marco Krahl.
+
+ * TI Tiva:
+
+ - GPIO Interrupts: Fix a bug of GPIO falling-edge interrupt for tiva.
+ From Young.
+
+ * C Library:
+
+ - math: Add a NAN test on 'x' in asin function of lib_asin.c. Suggested
+ by Pierre-noel Bouteville.
+
+ * Build/Configuration System:
+
+ - Several Makefiles: Add .PHONY definitions to prevent 'clean up to date'
+ message weirdness when 'make clean' is done with no .config or
+ Make.defs file.
--
GitLab
From beb6acc798de56e3f0203641afd5b813c6587b0f Mon Sep 17 00:00:00 2001
From: pkolesnikov
Date: Thu, 2 Jun 2016 12:09:42 +0200
Subject: [PATCH 029/400] timer copy
---
arch/arm/src/stm32f7/Make.defs | 2 +-
arch/arm/src/stm32f7/chip/stm32_tim.h | 1127 +++++++++++++++++++++++++
arch/arm/src/stm32f7/stm32_tim.c | 1099 ++++++++++++++++++++++++
arch/arm/src/stm32f7/stm32_tim.h | 215 +++++
configs/stm32f746-ws/nsh/defconfig | 2 +-
5 files changed, 2443 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/src/stm32f7/chip/stm32_tim.h
create mode 100644 arch/arm/src/stm32f7/stm32_tim.c
create mode 100644 arch/arm/src/stm32f7/stm32_tim.h
diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs
index 6cce8637eb..cf86c88c3e 100644
--- a/arch/arm/src/stm32f7/Make.defs
+++ b/arch/arm/src/stm32f7/Make.defs
@@ -114,7 +114,7 @@ endif
CHIP_ASRCS =
CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c
CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_serial.c
-CHIP_CSRCS += stm32_i2c.c stm32_spi.c stm32_start.c
+CHIP_CSRCS += stm32_i2c.c stm32_spi.c stm32_start.c stm32_tim.c
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += stm32_timerisr.c
diff --git a/arch/arm/src/stm32f7/chip/stm32_tim.h b/arch/arm/src/stm32f7/chip/stm32_tim.h
new file mode 100644
index 0000000000..4990022375
--- /dev/null
+++ b/arch/arm/src/stm32f7/chip/stm32_tim.h
@@ -0,0 +1,1127 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32_tim.h
+ *
+ * Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_TIM_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_TIM_H
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* Register Offsets *********************************************************************************/
+
+/* Basic Timers - TIM6 and TIM7 */
+
+#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
+#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */
+#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
+#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */
+#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
+#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */
+#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
+#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
+
+/* 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5
+ * 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
+ * For the STM32F10xx all timers are 16-bit.
+ * For the STM32F20xx and STM32F40xx, TIM2 and 5 are 32-bit
+ * The STM32 F1 Value Line and the STM32 F3 have variant general purpose registers
+ * that are not yet fully covered in this header file.
+ */
+
+#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
+#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit, TIM2-5 only) */
+#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5 only) */
+#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
+#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */
+#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
+#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit) */
+#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit, TIM2-5 only) */
+#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */
+#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit* or 32-bit STM3240 TIM2 and 5 only) */
+#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
+#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
+#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit STM3240 TIM2/5 only) */
+#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5 only or 32-bit STM32 F4 TIM2/5 or STM2 F3 TIM15 only) */
+#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit STM32 F4 TIM2/5 only) */
+#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit STM32 F4 TIM2/5 only) */
+#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit, TIM2-5 only) */
+#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit, TIM2-5 only) */
+
+/* The Option register is available on in the
+ *
+ * STM32 F1 value line, F2 and F4: TIM2, TIM5, and TIM11
+ * STM32 F3 (and possibly the F1 value line): TIM16
+ */
+
+#define STM32_GTIM_OR_OFFSET 0x0050 /* Timer 2/5/11/16 option register */
+
+/* TIM16, and 17 only.
+ * Only available in the STM32 F1 Value Line and the STM32 F3 family.
+ */
+
+#define STM32_GTIM_RCR_OFFSET 0x002c /* Repetition counter register (TIM16/TIM17) */
+#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */
+
+/* Advanced Timers - TIM1 and TIM8 */
+
+#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
+#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */
+#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */
+#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
+#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */
+#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
+#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */
+#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */
+#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */
+#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */
+#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
+#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
+#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */
+#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */
+#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */
+#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */
+#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */
+#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */
+#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */
+#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */
+
+/* Register Addresses *******************************************************************************/
+
+/* Advanced Timers - TIM1 and TIM8 */
+
+#if STM32F7_NATIM > 0
+# define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET)
+# define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET)
+# define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET)
+# define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET)
+# define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET)
+# define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET)
+# define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET)
+# define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET)
+# define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET)
+# define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET)
+# define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET)
+# define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET)
+# define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET)
+# define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET)
+# define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET)
+# define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET)
+# define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET)
+# define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET)
+# define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET)
+# define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET)
+#endif
+
+#if STM32F7_NATIM > 1
+# define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET)
+# define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET)
+# define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET)
+# define STM32_TIM8_DIER (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET)
+# define STM32_TIM8_SR (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET)
+# define STM32_TIM8_EGR (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET)
+# define STM32_TIM8_CCMR1 (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET)
+# define STM32_TIM8_CCMR2 (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET)
+# define STM32_TIM8_CCER (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET)
+# define STM32_TIM8_CNT (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET)
+# define STM32_TIM8_PSC (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET)
+# define STM32_TIM8_ARR (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET)
+# define STM32_TIM8_RCR (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET)
+# define STM32_TIM8_CCR1 (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET)
+# define STM32_TIM8_CCR2 (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET)
+# define STM32_TIM8_CCR3 (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET)
+# define STM32_TIM8_CCR4 (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET)
+# define STM32_TIM8_BDTR (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET)
+# define STM32_TIM8_DCR (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET)
+# define STM32_TIM8_DMAR (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET)
+#endif
+
+/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, and TIM5 with DMA.
+ * For the STM32F10xx all timers are 16-bit.
+ * For the STM32F2xx and STM32F40xx, TIM2 and 5 are 32-bit
+ */
+
+#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0
+# define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET)
+# define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET)
+# define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET)
+# define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET)
+# define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET)
+# define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET)
+# define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET)
+# define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET)
+# define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET)
+# define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET)
+# define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET)
+# define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET)
+# define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET)
+# define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET)
+# define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET)
+# define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET)
+# define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET)
+# define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET)
+#endif
+
+#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1
+# define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET)
+# define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET)
+# define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET)
+# define STM32_TIM3_DIER (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET)
+# define STM32_TIM3_SR (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET)
+# define STM32_TIM3_EGR (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET)
+# define STM32_TIM3_CCMR1 (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET)
+# define STM32_TIM3_CCMR2 (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET)
+# define STM32_TIM3_CCER (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET)
+# define STM32_TIM3_CNT (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET)
+# define STM32_TIM3_PSC (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET)
+# define STM32_TIM3_ARR (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET)
+# define STM32_TIM3_CCR1 (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET)
+# define STM32_TIM3_CCR2 (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET)
+# define STM32_TIM3_CCR3 (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET)
+# define STM32_TIM3_CCR4 (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET)
+# define STM32_TIM3_DCR (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET)
+# define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET)
+#endif
+
+#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2
+# define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET)
+# define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET)
+# define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET)
+# define STM32_TIM4_DIER (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET)
+# define STM32_TIM4_SR (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET)
+# define STM32_TIM4_EGR (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET)
+# define STM32_TIM4_CCMR1 (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET)
+# define STM32_TIM4_CCMR2 (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET)
+# define STM32_TIM4_CCER (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET)
+# define STM32_TIM4_CNT (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET)
+# define STM32_TIM4_PSC (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET)
+# define STM32_TIM4_ARR (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET)
+# define STM32_TIM4_CCR1 (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET)
+# define STM32_TIM4_CCR2 (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET)
+# define STM32_TIM4_CCR3 (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET)
+# define STM32_TIM4_CCR4 (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET)
+# define STM32_TIM4_DCR (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET)
+# define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET)
+#endif
+
+#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3
+# define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET)
+# define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET)
+# define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET)
+# define STM32_TIM5_DIER (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET)
+# define STM32_TIM5_SR (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET)
+# define STM32_TIM5_EGR (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET)
+# define STM32_TIM5_CCMR1 (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET)
+# define STM32_TIM5_CCMR2 (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET)
+# define STM32_TIM5_CCER (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET)
+# define STM32_TIM5_CNT (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET)
+# define STM32_TIM5_PSC (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET)
+# define STM32_TIM5_ARR (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET)
+# define STM32_TIM5_CCR1 (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET)
+# define STM32_TIM5_CCR2 (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET)
+# define STM32_TIM5_CCR3 (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET)
+# define STM32_TIM5_CCR4 (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET)
+# define STM32_TIM5_DCR (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET)
+# define STM32_TIM5_DMAR (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET)
+# define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET)
+#endif
+
+#define STM32_TIM15_CR1 (STM32_TIM15_BASE+STM32_GTIM_CR1_OFFSET)
+#define STM32_TIM15_CR2 (STM32_TIM15_BASE+STM32_GTIM_CR2_OFFSET)
+#define STM32_TIM15_SMCR (STM32_TIM15_BASE+STM32_GTIM_SMCR_OFFSET)
+#define STM32_TIM15_DIER (STM32_TIM15_BASE+STM32_GTIM_DIER_OFFSET)
+#define STM32_TIM15_SR (STM32_TIM15_BASE+STM32_GTIM_SR_OFFSET)
+#define STM32_TIM15_EGR (STM32_TIM15_BASE+STM32_GTIM_EGR_OFFSET)
+#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE+STM32_GTIM_CCMR1_OFFSET)
+#define STM32_TIM15_CCER (STM32_TIM15_BASE+STM32_GTIM_CCER_OFFSET)
+#define STM32_TIM15_CNT (STM32_TIM15_BASE+STM32_GTIM_CNT_OFFSET)
+#define STM32_TIM15_PSC (STM32_TIM15_BASE+STM32_GTIM_PSC_OFFSET)
+#define STM32_TIM15_ARR (STM32_TIM15_BASE+STM32_GTIM_ARR_OFFSET)
+#define STM32_TIM15_RCR (STM32_TIM15_BASE+STM32_GTIM_RCR_OFFSET)
+#define STM32_TIM15_CCR1 (STM32_TIM15_BASE+STM32_GTIM_CCR1_OFFSET)
+#define STM32_TIM15_CCR2 (STM32_TIM15_BASE+STM32_GTIM_CCR2_OFFSET)
+#define STM32_TIM15_BDTR (STM32_TIM15_BASE+STM32_GTIM_BDTR_OFFSET)
+#define STM32_TIM15_DCR (STM32_TIM15_BASE+STM32_GTIM_DCR_OFFSET)
+#define STM32_TIM15_DMAR (STM32_TIM15_BASE+STM32_GTIM_DMAR_OFFSET)
+
+#define STM32_TIM16_CR1 (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET)
+#define STM32_TIM16_CR2 (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET)
+#define STM32_TIM16_DIER (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET)
+#define STM32_TIM16_SR (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET)
+#define STM32_TIM16_EGR (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET)
+#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET)
+#define STM32_TIM16_CCMR2 (STM32_TIM16_BASE+STM32_GTIM_CCMR2_OFFSET)
+#define STM32_TIM16_CCER (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET)
+#define STM32_TIM16_CNT (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET)
+#define STM32_TIM16_PSC (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET)
+#define STM32_TIM16_ARR (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET)
+#define STM32_TIM16_RCR (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET)
+#define STM32_TIM16_CCR1 (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET)
+#define STM32_TIM16_BDTR (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET)
+#define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET)
+#define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET)
+#define STM32_TIM16_OR (STM32_TIM16_BASE+STM32_GTIM_OR_OFFSET)
+
+#define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET)
+#define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET)
+#define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET)
+#define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET)
+#define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET)
+#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET)
+#define STM32_TIM17_CCMR2 (STM32_TIM17_BASE+STM32_GTIM_CCMR2_OFFSET)
+#define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET)
+#define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET)
+#define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET)
+#define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET)
+#define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET)
+#define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET)
+#define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET)
+#define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET)
+#define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET)
+
+/* 16-bit General Timers - TIM9-14 without DMA. Note that (1) these timers
+ * support only a subset of the general timer registers are supported, and
+ * (2) TIM9 and TIM12 differ from the others.
+ */
+
+#if STM32F7_NGTIMNDMA > 0
+# define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET)
+# define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET)
+# define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET)
+# define STM32_TIM9_SR (STM32_TIM9_BASE+STM32_GTIM_SR_OFFSET)
+# define STM32_TIM9_EGR (STM32_TIM9_BASE+STM32_GTIM_EGR_OFFSET)
+# define STM32_TIM9_CCMR1 (STM32_TIM9_BASE+STM32_GTIM_CCMR1_OFFSET)
+# define STM32_TIM9_CCER (STM32_TIM9_BASE+STM32_GTIM_CCER_OFFSET)
+# define STM32_TIM9_CNT (STM32_TIM9_BASE+STM32_GTIM_CNT_OFFSET)
+# define STM32_TIM9_PSC (STM32_TIM9_BASE+STM32_GTIM_PSC_OFFSET)
+# define STM32_TIM9_ARR (STM32_TIM9_BASE+STM32_GTIM_ARR_OFFSET)
+# define STM32_TIM9_CCR1 (STM32_TIM9_BASE+STM32_GTIM_CCR1_OFFSET)
+# define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET)
+#endif
+
+#if STM32F7_NGTIMNDMA > 1
+# define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET)
+# define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET)
+# define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET)
+# define STM32_TIM10_EGR (STM32_TIM10_BASE+STM32_GTIM_EGR_OFFSET)
+# define STM32_TIM10_CCMR1 (STM32_TIM10_BASE+STM32_GTIM_CCMR1_OFFSET)
+# define STM32_TIM10_CCER (STM32_TIM10_BASE+STM32_GTIM_CCER_OFFSET)
+# define STM32_TIM10_CNT (STM32_TIM10_BASE+STM32_GTIM_CNT_OFFSET)
+# define STM32_TIM10_PSC (STM32_TIM10_BASE+STM32_GTIM_PSC_OFFSET)
+# define STM32_TIM10_ARR (STM32_TIM10_BASE+STM32_GTIM_ARR_OFFSET)
+# define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET)
+#endif
+
+#if STM32F7_NGTIMNDMA > 2
+# define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET)
+# define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET)
+# define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET)
+# define STM32_TIM11_EGR (STM32_TIM11_BASE+STM32_GTIM_EGR_OFFSET)
+# define STM32_TIM11_CCMR1 (STM32_TIM11_BASE+STM32_GTIM_CCMR1_OFFSET)
+# define STM32_TIM11_CCER (STM32_TIM11_BASE+STM32_GTIM_CCER_OFFSET)
+# define STM32_TIM11_CNT (STM32_TIM11_BASE+STM32_GTIM_CNT_OFFSET)
+# define STM32_TIM11_PSC (STM32_TIM11_BASE+STM32_GTIM_PSC_OFFSET)
+# define STM32_TIM11_ARR (STM32_TIM11_BASE+STM32_GTIM_ARR_OFFSET)
+# define STM32_TIM11_CCR1 (STM32_TIM11_BASE+STM32_GTIM_CCR1_OFFSET)
+# define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET)
+#endif
+
+#if STM32F7_NGTIMNDMA > 3
+# define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET)
+# define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET)
+# define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET)
+# define STM32_TIM12_SR (STM32_TIM12_BASE+STM32_GTIM_SR_OFFSET)
+# define STM32_TIM12_EGR (STM32_TIM12_BASE+STM32_GTIM_EGR_OFFSET)
+# define STM32_TIM12_CCMR1 (STM32_TIM12_BASE+STM32_GTIM_CCMR1_OFFSET)
+# define STM32_TIM12_CCER (STM32_TIM12_BASE+STM32_GTIM_CCER_OFFSET)
+# define STM32_TIM12_CNT (STM32_TIM12_BASE+STM32_GTIM_CNT_OFFSET)
+# define STM32_TIM12_PSC (STM32_TIM12_BASE+STM32_GTIM_PSC_OFFSET)
+# define STM32_TIM12_ARR (STM32_TIM12_BASE+STM32_GTIM_ARR_OFFSET)
+# define STM32_TIM12_CCR1 (STM32_TIM12_BASE+STM32_GTIM_CCR1_OFFSET)
+# define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET)
+#endif
+
+#if STM32F7_NGTIMNDMA > 4
+# define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET)
+# define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET)
+# define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET)
+# define STM32_TIM13_EGR (STM32_TIM13_BASE+STM32_GTIM_EGR_OFFSET)
+# define STM32_TIM13_CCMR1 (STM32_TIM13_BASE+STM32_GTIM_CCMR1_OFFSET)
+# define STM32_TIM13_CCER (STM32_TIM13_BASE+STM32_GTIM_CCER_OFFSET)
+# define STM32_TIM13_CNT (STM32_TIM13_BASE+STM32_GTIM_CNT_OFFSET)
+# define STM32_TIM13_PSC (STM32_TIM13_BASE+STM32_GTIM_PSC_OFFSET)
+# define STM32_TIM13_ARR (STM32_TIM13_BASE+STM32_GTIM_ARR_OFFSET)
+# define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET)
+#endif
+
+#if STM32F7_NGTIMNDMA > 5
+# define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET)
+# define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET)
+# define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET)
+# define STM32_TIM14_EGR (STM32_TIM14_BASE+STM32_GTIM_EGR_OFFSET)
+# define STM32_TIM14_CCMR1 (STM32_TIM14_BASE+STM32_GTIM_CCMR1_OFFSET)
+# define STM32_TIM14_CCER (STM32_TIM14_BASE+STM32_GTIM_CCER_OFFSET)
+# define STM32_TIM14_CNT (STM32_TIM14_BASE+STM32_GTIM_CNT_OFFSET)
+# define STM32_TIM14_PSC (STM32_TIM14_BASE+STM32_GTIM_PSC_OFFSET)
+# define STM32_TIM14_ARR (STM32_TIM14_BASE+STM32_GTIM_ARR_OFFSET)
+# define STM32_TIM14_CCR1 (STM32_TIM14_BASE+STM32_GTIM_CCR1_OFFSET)
+#endif
+
+/* Basic Timers - TIM6 and TIM7 */
+
+#if STM32F7_NBTIM > 0
+# define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET)
+# define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET)
+# define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET)
+# define STM32_TIM6_SR (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET)
+# define STM32_TIM6_EGR (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET)
+# define STM32_TIM6_CNT (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET)
+# define STM32_TIM6_PSC (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET)
+# define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET)
+#endif
+
+#if STM32F7_NBTIM > 1
+# define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET)
+# define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET)
+# define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET)
+# define STM32_TIM7_SR (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET)
+# define STM32_TIM7_EGR (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET)
+# define STM32_TIM7_CNT (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET)
+# define STM32_TIM7_PSC (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET)
+# define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ********************************************************************/
+
+/* Control register 1 */
+
+#define ATIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */
+#define ATIM_CR1_UDIS (1 << 1) /* Bit 1: Update disable */
+#define ATIM_CR1_URS (1 << 2) /* Bit 2: Update request source */
+#define ATIM_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */
+#define ATIM_CR1_DIR (1 << 4) /* Bit 4: Direction */
+#define ATIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned mode selection */
+#define ATIM_CR1_CMS_MASK (3 << ATIM_CR1_CMS_SHIFT)
+# define ATIM_CR1_EDGE (0 << ATIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */
+# define ATIM_CR1_CENTER1 (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */
+# define ATIM_CR1_CENTER2 (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */
+# define ATIM_CR1_CENTER3 (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */
+#define ATIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */
+#define ATIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock division */
+#define ATIM_CR1_CKD_MASK (3 << ATIM_CR1_CKD_SHIFT)
+# define ATIM_CR1_TCKINT (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */
+# define ATIM_CR1_2TCKINT (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */
+# define ATIM_CR1_4TCKINT (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */
+
+/* Control register 2 */
+
+#define ATIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare Preloaded Control */
+#define ATIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare Control Update Selection */
+#define ATIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */
+#define ATIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */
+#define ATIM_CR2_MMS_MASK (7 << ATIM_CR2_MMS_SHIFT)
+# define ATIM_CR2_MMS_RESET (0 << ATIM_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */
+# define ATIM_CR2_MMS_ENABLE (1 << ATIM_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */
+# define ATIM_CR2_MMS_UPDATE (2 << ATIM_CR2_MMS_SHIFT) /* 010: Update event is TRGO */
+# define ATIM_CR2_MMS_COMPP (3 << ATIM_CR2_MMS_SHIFT) /* 010: Compare Pulse - CC1IF flag */
+# define ATIM_CR2_MMS_OC1REF (4 << ATIM_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */
+# define ATIM_CR2_MMS_OC2REF (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */
+# define ATIM_CR2_MMS_OC3REF (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */
+# define ATIM_CR2_MMS_OC4REF (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */
+#define ATIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */
+#define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */
+#define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */
+#define ATIM_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */
+#define ATIM_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */
+#define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */
+#define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */
+#define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */
+
+/* Slave mode control register */
+
+#define ATIM_SMCR_SMS_SHIFT (0) /* Bits 0-2: Slave mode selection */
+#define ATIM_SMCR_SMS_MASK (7 << ATIM_SMCR_SMS_SHIFT)
+# define ATIM_SMCR_DISAB (0 << ATIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */
+# define ATIM_SMCR_ENCMD1 (1 << ATIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */
+# define ATIM_SMCR_ENCMD2 (2 << ATIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */
+# define ATIM_SMCR_ENCMD3 (3 << ATIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */
+# define ATIM_SMCR_RESET (4 << ATIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */
+# define ATIM_SMCR_GATED (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */
+# define ATIM_SMCR_TRIGGER (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */
+# define ATIM_SMCR_EXTCLK1 (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */
+#define ATIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */
+#define ATIM_SMCR_TS_MASK (7 << ATIM_SMCR_TS_SHIFT)
+# define ATIM_SMCR_ITR0 (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */
+# define ATIM_SMCR_ITR1 (1 << ATIM_SMCR_TS_SHIFT) /* 001: Internal trigger 1 (ITR1) */
+# define ATIM_SMCR_ITR2 (2 << ATIM_SMCR_TS_SHIFT) /* 010: Internal trigger 2 (ITR2) */
+# define ATIM_SMCR_ITR3 (3 << ATIM_SMCR_TS_SHIFT) /* 011: Internal trigger 3 (ITR3) */
+# define ATIM_SMCR_T1FED (4 << ATIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */
+# define ATIM_SMCR_TI1FP1 (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */
+# define ATIM_SMCR_T12FP2 (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */
+# define ATIM_SMCR_ETRF (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */
+#define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */
+#define ATIM_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */
+#define ATIM_SMCR_ETF_MASK (0x0f << ATIM_SMCR_ETF_SHIFT)
+# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */
+# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */
+# define ATIM_SMCR_FCKINT4 (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */
+# define ATIM_SMCR_FCKINT8 (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */
+# define ATIM_SMCR_FDTSd26 (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */
+# define ATIM_SMCR_FDTSd28 (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */
+# define ATIM_SMCR_FDTSd46 (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */
+# define ATIM_SMCR_FDTSd48 (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */
+# define ATIM_SMCR_FDTSd86 (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */
+# define ATIM_SMCR_FDTSd88 (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */
+# define ATIM_SMCR_FDTSd165 (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
+# define ATIM_SMCR_FDTSd166 (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
+# define ATIM_SMCR_FDTSd168 (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
+# define ATIM_SMCR_FDTSd325 (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
+# define ATIM_SMCR_FDTSd326 (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
+# define ATIM_SMCR_FDTSd328 (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
+#define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */
+#define ATIM_SMCR_ETPS_MASK (3 << ATIM_SMCR_ETPS_SHIFT)
+# define ATIM_SMCR_PSCOFF (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */
+# define ATIM_SMCR_ETRPd2 (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */
+# define ATIM_SMCR_ETRPd4 (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */
+# define ATIM_SMCR_ETRPd8 (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */
+#define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */
+#define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */
+
+/* DMA/Interrupt enable register */
+
+#define ATIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */
+#define ATIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */
+#define ATIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */
+#define ATIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */
+#define ATIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */
+
+#define ATIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */
+
+#define ATIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */
+#define ATIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */
+#define ATIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */
+#define ATIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */
+#define ATIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */
+
+#define ATIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */
+
+/* Status register */
+
+#define ATIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */
+#define ATIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */
+#define ATIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */
+#define ATIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */
+#define ATIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */
+#define ATIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */
+#define ATIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */
+
+#define ATIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */
+#define ATIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */
+#define ATIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */
+#define ATIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */
+
+/* Event generation register */
+
+#define ATIM_EGR_UG (1 << 0) /* Bit 0: Update Generation */
+#define ATIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */
+#define ATIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */
+#define ATIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */
+#define ATIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */
+
+#define ATIM_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */
+
+/* Capture/compare mode register 1 -- Output compare mode */
+
+#define ATIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */
+#define ATIM_CCMR1_CC1S_MASK (3 << ATIM_CCMR1_CC1S_SHIFT)
+ /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */
+#define ATIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */
+#define ATIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */
+#define ATIM_CCMR1_OC1M_MASK (7 << ATIM_CCMR1_OC1M_SHIFT)
+ /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */
+#define ATIM_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */
+#define ATIM_CCMR1_CC2S_MASK (3 << ATIM_CCMR1_CC2S_SHIFT)
+ /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */
+#define ATIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */
+#define ATIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */
+#define ATIM_CCMR1_OC2M_MASK (7 << ATIM_CCMR1_OC2M_SHIFT)
+ /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */
+
+/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */
+
+#define ATIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */
+#define ATIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */
+#define ATIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */
+#define ATIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */
+
+/* Common CCMR (unshifted) Compare Mode bit field definitions */
+
+#define ATIM_CCMR_MODE_FRZN (0) /* 000: Frozen */
+#define ATIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */
+#define ATIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */
+#define ATIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */
+#define ATIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */
+#define ATIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */
+#define ATIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */
+#define ATIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */
+#define ATIM_CCMR_MODE_COMBINED1 (12) /* 1100: Combined PWM mode 1 */
+#define ATIM_CCMR_MODE_COMBINED2 (13) /* 1101: Combined PWM mode 2 */
+#define ATIM_CCMR_MODE_ASYMMETRIC1 (14) /* 1110: Asymmetric PWM mode 1 */
+#define ATIM_CCMR_MODE_ASYMMETRIC2 (15) /* 1111: Asymmetric PWM mode 2 */
+
+/* Capture/compare mode register 1 -- Input capture mode */
+
+ /* Bits 1-0:(same as output compare mode) */
+#define ATIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */
+#define ATIM_CCMR1_IC1PSC_MASK (3 << ATIM_CCMR1_IC1PSC_SHIFT)
+ /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */
+#define ATIM_CCMR1_IC1F_MASK (0x0f << ATIM_CCMR1_IC1F_SHIFT)
+ /* (See common (unshifted) bit field definitions below) */
+ /* Bits 9:8 (same as output compare mode) */
+#define ATIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11:10: Input Capture 2 Prescaler */
+#define ATIM_CCMR1_IC2PSC_MASK (3 << ATIM_CCMR1_IC2PSC_SHIFT)
+ /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */
+#define ATIM_CCMR1_IC2F_MASK (0x0f << ATIM_CCMR1_IC2F_SHIFT)
+ /* (See common (unshifted) bit field definitions below) */
+
+/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */
+
+#define ATIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */
+#define ATIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */
+#define ATIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */
+#define ATIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */
+
+/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */
+
+#define ATIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */
+#define ATIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */
+#define ATIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */
+#define ATIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */
+#define ATIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */
+#define ATIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */
+#define ATIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */
+#define ATIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */
+#define ATIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */
+#define ATIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */
+#define ATIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */
+#define ATIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */
+#define ATIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */
+#define ATIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */
+#define ATIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */
+#define ATIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */
+
+/* Capture/compare mode register 2 - Output Compare mode */
+
+#define ATIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */
+#define ATIM_CCMR2_CC3S_MASK (3 << ATIM_CCMR2_CC3S_SHIFT)
+ /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */
+#define ATIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */
+#define ATIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */
+#define ATIM_CCMR2_OC3M_MASK (7 << ATIM_CCMR2_OC3M_SHIFT)
+ /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */
+#define ATIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */
+#define ATIM_CCMR2_CC4S_MASK (3 << ATIM_CCMR2_CC4S_SHIFT)
+ /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */
+#define ATIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */
+#define ATIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */
+#define ATIM_CCMR2_OC4M_MASK (7 << ATIM_CCMR2_OC4M_SHIFT)
+ /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */
+
+/* Capture/compare mode register 2 - Input Capture Mode */
+
+ /* Bits 1-0:(same as output compare mode) */
+#define ATIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */
+#define ATIM_CCMR1_IC3PSC_MASK (3 << ATIM_CCMR2_IC3PSC_SHIFT)
+ /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */
+#define ATIM_CCMR2_IC3F_MASK (0x0f << ATIM_CCMR2_IC3F_SHIFT)
+ /* (See common (unshifted) bit field definitions above) */
+ /* Bits 9:8 (same as output compare mode) */
+#define ATIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11:10: Input Capture 4 Prescaler */
+#define ATIM_CCMR2_IC4PSC_MASK (3 << ATIM_CCMR2_IC4PSC_SHIFT)
+ /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */
+#define ATIM_CCMR2_IC4F_MASK (0x0f << ATIM_CCMR2_IC4F_SHIFT)
+ /* (See common (unshifted) bit field definitions above) */
+
+/* Capture/compare enable register */
+
+#define ATIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */
+#define ATIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output Polarity */
+#define ATIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 Complementary output enable */
+#define ATIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 Complementary output polarity */
+#define ATIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */
+#define ATIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output Polarity */
+#define ATIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 Complementary output enable */
+#define ATIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 Complementary output polarity */
+#define ATIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */
+#define ATIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity */
+#define ATIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 Complementary output enable */
+#define ATIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 Complementary output polarity */
+#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */
+#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */
+#define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */
+
+
+/* 16-bit counter register */
+
+#define ATIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */
+#define ATIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT)
+
+/* Repetition counter register */
+
+#define ATIM_RCR_REP_SHIFT (0) /* Bits 0-7: Repetition Counter Value */
+#define ATIM_RCR_REP_MASK (0xff << ATIM_RCR_REP_SHIFT)
+
+#define ATIM_RCR_REP_MAX 128
+
+/* Capture/compare registers (CCR) */
+
+
+#define ATIM_CCR_MASK (0xffff)
+
+/* Break and dead-time register */
+
+#define ATIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */
+#define ATIM_BDTR_DTG_MASK (0xff << ATIM_BDTR_DTG_SHIFT)
+#define ATIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */
+#define ATIM_BDTR_LOCK_MASK (3 << ATIM_BDTR_LOCK_SHIFT)
+# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
+# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
+# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
+# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */
+#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
+#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */
+#define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */
+#define ATIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */
+#define ATIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */
+#define ATIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */
+
+/* DMA control register */
+
+#define ATIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */
+#define ATIM_DCR_DBA_MASK (0x1f << ATIM_DCR_DBA_SHIFT)
+#define ATIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */
+#define ATIM_DCR_DBL_MASK (0x1f << ATIM_DCR_DBL_SHIFT)
+# define ATIM_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */
+
+/* Control register 1 (TIM2-5 and TIM9-14) */
+
+#define GTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */
+#define GTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */
+#define GTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */
+#define GTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode (TIM2-5, 9, and 12 only) */
+#define GTIM_CR1_DIR (1 << 4) /* Bit 4: Direction (TIM2-5 only) */
+#define GTIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned Mode Selection (TIM2-5 only) */
+#define GTIM_CR1_CMS_MASK (3 << GTIM_CR1_CMS_SHIFT)
+# define GTIM_CR1_EDGE (0 << GTIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode. */
+# define GTIM_CR1_CENTER1 (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */
+# define GTIM_CR1_CENTER2 (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */
+# define GTIM_CR1_CENTER3 (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */
+#define GTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */
+#define GTIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock Division */
+#define GTIM_CR1_CKD_MASK (3 << GTIM_CR1_CKD_SHIFT)
+# define GTIM_CR1_TCKINT (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */
+# define GTIM_CR1_2TCKINT (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */
+# define GTIM_CR1_4TCKINT (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */
+
+/* Control register 2 (TIM2-5, TIM9-12, and TIM15-17 only) */
+
+#define GTIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/compare preloaded control (TIM15-17 only) */
+#define GTIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/compare control update selection (TIM15-17 only) */
+#define GTIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection (TIM2-5,1,&16 only) */
+#define GTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection (not TIM16) */
+#define GTIM_CR2_MMS_MASK (7 << GTIM_CR2_MMS_SHIFT)
+# define GTIM_CR2_MMS_RESET (0 << GTIM_CR2_MMS_SHIFT) /* 000: Reset */
+# define GTIM_CR2_MMS_ENABLE (1 << GTIM_CR2_MMS_SHIFT) /* 001: Enable */
+# define GTIM_CR2_MMS_UPDATE (2 << GTIM_CR2_MMS_SHIFT) /* 010: Update */
+# define GTIM_CR2_MMS_COMPP (3 << GTIM_CR2_MMS_SHIFT) /* 011: Compare Pulse */
+# define GTIM_CR2_MMS_OC1REF (4 << GTIM_CR2_MMS_SHIFT) /* 100: Compare - OC1REF signal is used as trigger output (TRGO) */
+# define GTIM_CR2_MMS_OC2REF (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */
+# define GTIM_CR2_MMS_OC3REF (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */
+# define GTIM_CR2_MMS_OC4REF (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */
+#define GTIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection (not TIM16) */
+#define GTIM_CR2_OIS1 (1 << 8) /* Bit 8: COutput Idle state 1 (OC1 output) (TIM15-17 only) */
+#define GTIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) (TIM15-17 only) */
+#define GTIM_CR2_OIS2 (1 << 10) /* Bit 10: Output idle state 2 (OC2 output) (TIM15 only) */
+
+/* Slave mode control register (TIM2-5 and TIM15 only) */
+
+#define GTIM_SMCR_SMS_SHIFT (0) /* Bits 2-0: Slave Mode Selection */
+#define GTIM_SMCR_SMS_MASK (7 << GTIM_SMCR_SMS_SHIFT)
+# define GTIM_SMCR_DISAB (0 << GTIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */
+# define GTIM_SMCR_ENCMD1 (1 << GTIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */
+# define GTIM_SMCR_ENCMD2 (2 << GTIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */
+# define GTIM_SMCR_ENCMD3 (3 << GTIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */
+# define GTIM_SMCR_RESET (4 << GTIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */
+# define GTIM_SMCR_GATED (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */
+# define GTIM_SMCR_TRIGGER (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */
+# define GTIM_SMCR_EXTCLK1 (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */
+#define GTIM_SMCR_TS_SHIFT (4) /* Bits 6-4: Trigger Selection */
+#define GTIM_SMCR_TS_MASK (7 << GTIM_SMCR_TS_SHIFT)
+# define GTIM_SMCR_ITR0 (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). TIM1 */
+# define GTIM_SMCR_ITR1 (1 << GTIM_SMCR_TS_SHIFT) /* 001: Internal Trigger 1 (ITR1). TIM2 */
+# define GTIM_SMCR_ITR2 (2 << GTIM_SMCR_TS_SHIFT) /* 010: Internal Trigger 2 (ITR2). TIM3 */
+# define GTIM_SMCR_ITR3 (3 << GTIM_SMCR_TS_SHIFT) /* 011: Internal Trigger 3 (ITR3). TIM4 */
+# define GTIM_SMCR_TI1FED (4 << GTIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */
+# define GTIM_SMCR_TI1FP1 (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */
+# define GTIM_SMCR_TI2FP2 (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */
+# define GTIM_SMCR_ETRF (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */
+#define GTIM_SMCR_MSM (1 << 7) /* Bit 7: Master/Slave mode */
+#define GTIM_SMCR_ETF_SHIFT (8) /* Bits 11-8: External Trigger Filter (not TIM15) */
+#define GTIM_SMCR_ETF_MASK (0x0f << GTIM_SMCR_ETF_SHIFT)
+# define GTIM_SMCR_NOFILT (0 << GTIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */
+# define GTIM_SMCR_FCKINT2 (1 << GTIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */
+# define GTIM_SMCR_FCKINT4 (2 << GTIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */
+# define GTIM_SMCR_FCKINT8 (3 << GTIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */
+# define GTIM_SMCR_FDTSd26 (4 << GTIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */
+# define GTIM_SMCR_FDTSd28 (5 << GTIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */
+# define GTIM_SMCR_FDTSd36 (6 << GTIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */
+# define GTIM_SMCR_FDTSd38 (7 << GTIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */
+# define GTIM_SMCR_FDTSd86 (8 << GTIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */
+# define GTIM_SMCR_FDTSd88 (9 << GTIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */
+# define GTIM_SMCR_FDTSd165 (10 << GTIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
+# define GTIM_SMCR_FDTSd166 (11 << GTIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
+# define GTIM_SMCR_FDTSd168 (12 << GTIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
+# define GTIM_SMCR_FDTSd325 (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
+# define GTIM_SMCR_FDTSd326 (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
+# define GTIM_SMCR_FDTSd328 (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
+#define GTIM_SMCR_ETPS_SHIFT (12) /* Bits 13-12: External Trigger Prescaler (not TIM15) */
+#define GTIM_SMCR_ETPS_MASK (3 << GTIM_SMCR_ETPS_SHIFT)
+# define GTIM_SMCR_PSCOFF (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */
+# define GTIM_SMCR_ETRPd2 (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */
+# define GTIM_SMCR_ETRPd4 (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */
+# define GTIM_SMCR_ETRPd8 (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */
+#define GTIM_SMCR_ECE (1 << 14) /* Bit 14: External Clock enable */
+#define GTIM_SMCR_ETP (1 << 15) /* Bit 15: External Trigger Polarity */
+
+/* DMA/Interrupt enable register (TIM2-5 and TIM9-14) */
+
+#define GTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */
+#define GTIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */
+#define GTIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable (TIM2-5,9,12,&15 only) */
+#define GTIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable (TIM2-5 only) */
+#define GTIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable (TIM2-5 only) */
+#define GTIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable (TIM15-17 only) */
+#define GTIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable (TIM2-5,9,&12 only) */
+#define GTIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable (TIM15-17 only) */
+#define GTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable (TIM2-5&15-17 only) */
+#define GTIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable (TIM2-5&15-17 only) */
+#define GTIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable (TIM2-5&15 only) */
+#define GTIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable (TIM2-5 only) */
+#define GTIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable (TIM2-5 only) */
+#define GTIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable (TIM15-17 only) */
+#define GTIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable (TIM2-5&15-17 only) */
+
+/* Status register */
+
+#define GTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */
+#define GTIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/compare 1 interrupt flag */
+#define GTIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt flag (TIM2-5,9,12,&15 only) */
+#define GTIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt flag (TIM2-5 only) */
+#define GTIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt flag (TIM2-5 only) */
+#define GTIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt flag (TIM15-17 only) */
+#define GTIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag (TIM2-5,9,12&15-17 only) */
+#define GTIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt flag (TIM15-17 only) */
+#define GTIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture flag */
+#define GTIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture flag (TIM2-5,9,12&15 only) */
+#define GTIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture flag (TIM2-5 only) */
+#define GTIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture flag (TIM2-5 only) */
+
+/* Event generation register (TIM2-5 and TIM9-14) */
+
+#define GTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */
+#define GTIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/compare 1 generation */
+#define GTIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/compare 2 generation (TIM2-5,9,12,&15 only) */
+#define GTIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/compare 3 generation (TIM2-5 only) */
+#define GTIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/compare 4 generation (TIM2-5 only) */
+#define GTIM_EGR_COMIG (1 << 5) /* Bit 5: Capture/Compare control update generation (TIM15-17 only) */
+#define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger generation (TIM2-5,9,12&16-17 only) */
+#define GTIM_EGR_BG (1 << 7) /* Bit 7: Break generation (TIM15-17 only) */
+
+/* Capture/compare mode register 1 - Output compare mode (TIM2-5 and TIM9-14) */
+
+#define GTIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */
+#define GTIM_CCMR1_CC1S_MASK (3 << GTIM_CCMR1_CC1S_SHIFT)
+ /* (See common CCMR Capture/Compare Selection definitions below) */
+#define GTIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */
+#define GTIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */
+#define GTIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */
+#define GTIM_CCMR1_OC1M_MASK (7 << GTIM_CCMR1_OC1M_SHIFT)
+ /* (See common CCMR Output Compare Mode definitions below) */
+#define GTIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */
+#define GTIM_CCMR1_CC2S_SHIFT (8) /* Bits 9-8: Capture/Compare 2 Selection */
+#define GTIM_CCMR1_CC2S_MASK (3 << GTIM_CCMR1_CC2S_SHIFT)
+ /* (See common CCMR Capture/Compare Selection definitions below) */
+#define GTIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */
+#define GTIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */
+#define GTIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */
+#define GTIM_CCMR1_OC2M_MASK (7 << GTIM_CCMR1_OC2M_SHIFT)
+ /* (See common CCMR Output Compare Mode definitions below) */
+#define GTIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */
+
+/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */
+
+#define GTIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */
+#define GTIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */
+#define GTIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */
+#define GTIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */
+
+/* Common CCMR (unshifted) Compare Mode bit field definitions */
+
+#define GTIM_CCMR_MODE_FRZN (0) /* 000: Frozen */
+#define GTIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */
+#define GTIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */
+#define GTIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */
+#define GTIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */
+#define GTIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */
+#define GTIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */
+#define GTIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */
+
+/* Capture/compare mode register 1 - Input capture mode (TIM2-5 and TIM9-14) */
+
+ /* Bits 1-0 (Same as Output Compare Mode) */
+#define GTIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */
+#define GTIM_CCMR1_IC1PSC_MASK (3 << GTIM_CCMR1_IC1PSC_SHIFT)
+ /* (See common CCMR Input Capture Prescaler definitions below) */
+#define GTIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */
+#define GTIM_CCMR1_IC1F_MASK (0x0f << GTIM_CCMR1_IC1F_SHIFT)
+ /* (See common CCMR Input Capture Filter definitions below) */
+ /* Bits 9-8: (Same as Output Compare Mode) */
+#define GTIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11-10: Input Capture 2 Prescaler */
+#define GTIM_CCMR1_IC2PSC_MASK (3 << GTIM_CCMR1_IC2PSC_SHIFT)
+ /* (See common CCMR Input Capture Prescaler definitions below) */
+#define GTIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */
+#define GTIM_CCMR1_IC2F_MASK (0x0f << GTIM_CCMR1_IC2F_SHIFT)
+ /* (See common CCMR Input Capture Filter definitions below) */
+
+/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */
+
+#define GTIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */
+#define GTIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */
+#define GTIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */
+#define GTIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */
+
+/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */
+
+#define GTIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */
+#define GTIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */
+#define GTIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */
+#define GTIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */
+#define GTIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */
+#define GTIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */
+#define GTIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */
+#define GTIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */
+#define GTIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */
+#define GTIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */
+#define GTIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */
+#define GTIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */
+#define GTIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */
+#define GTIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */
+#define GTIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */
+#define GTIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */
+
+/* Capture/compare mode register 2 - Output Compare mode (TIM2-5 only) */
+
+#define GTIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */
+#define GTIM_CCMR2_CC3S_MASK (3 << GTIM_CCMR2_CC3S_SHIFT)
+ /* (See common CCMR Capture/Compare Selection definitions above) */
+#define GTIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */
+#define GTIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */
+#define GTIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */
+#define GTIM_CCMR2_OC3M_MASK (7 << GTIM_CCMR2_OC3M_SHIFT)
+ /* (See common CCMR Output Compare Mode definitions above) */
+#define GTIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */
+#define GTIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */
+#define GTIM_CCMR2_CC4S_MASK (3 << GTIM_CCMR2_CC4S_SHIFT)
+ /* (See common CCMR Capture/Compare Selection definitions above) */
+#define GTIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */
+#define GTIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */
+#define GTIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */
+#define GTIM_CCMR2_OC4M_MASK (7 << GTIM_CCMR2_OC4M_SHIFT)
+ /* (See common CCMR Output Compare Mode definitions above) */
+#define GTIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */
+
+/* Capture/compare mode register 2 - Input capture mode (TIM2-5 only) */
+
+ /* Bits 1-0 (Same as Output Compare Mode) */
+#define GTIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */
+#define GTIM_CCMR2_IC3PSC_MASK (3 << GTIM_CCMR2_IC3PSC_SHIFT)
+ /* (See common CCMR Input Capture Prescaler definitions below) */
+#define GTIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */
+#define GTIM_CCMR2_IC3F_MASK (0x0f << GTIM_CCMR2_IC3F_SHIFT)
+ /* (See common CCMR Input Capture Filter definitions below) */
+ /* Bits 9-8: (Same as Output Compare Mode) */
+#define GTIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11-10: Input Capture 4 Prescaler */
+#define GTIM_CCMR2_IC4PSC_MASK (3 << GTIM_CCMR2_IC4PSC_SHIFT)
+ /* (See common CCMR Input Capture Prescaler definitions below) */
+#define GTIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */
+#define GTIM_CCMR2_IC4F_MASK (0x0f << GTIM_CCMR2_IC4F_SHIFT)
+ /* (See common CCMR Input Capture Filter definitions below) */
+
+/* Capture/compare enable register (TIM1 and TIM8, TIM2-5 and TIM9-14) */
+
+#define GTIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */
+#define GTIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */
+#define GTIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable (TIM1 and TIM8 only) */
+#define GTIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 output Polarity (F2,F3,F4 and TIM15-17) */
+#define GTIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable (TIM2-5,9&12 only) */
+#define GTIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output polarity (TIM2-5,9&12 only) */
+#define GTIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 complementary output enable (TIM1 and TIM8 only) */
+#define GTIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 output Polarity (F2,F3,F4 and TIM2-5,9,12&15 only) */
+#define GTIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable (TIM2-5 only) */
+#define GTIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity (TIM2-5 only) */
+#define GTIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 complementary output enable (TIM1 and TIM8 only) */
+#define GTIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 output Polarity (F2,F4 and TIM2-5 only) */
+#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */
+#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */
+#define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */
+
+/* 16-bit counter register */
+
+#define GTIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */
+#define GTIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT)
+
+/* Repitition counter (TIM15-17 only) */
+
+#define GTIM_RCR_REP_SHIFT (0) /* Bits 0-7: Repetition Counter Value */
+#define GTIM_RCR_REP_MASK (0xff << GTIM_RCR_REP_SHIFT)
+
+#define GTIM_RCR_REP_MAX 128
+
+/* Break and dead-time register (TIM15-17 only */
+
+#define GTIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */
+#define GTIM_BDTR_DTG_MASK (0xff << GTIM_BDTR_DTG_SHIFT)
+#define GTIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */
+#define GTIM_BDTR_LOCK_MASK (3 << GTIM_BDTR_LOCK_SHIFT)
+# define GTIM_BDTR_LOCKOFF (0 << GTIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
+# define GTIM_BDTR_LOCK1 (1 << GTIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
+# define GTIM_BDTR_LOCK2 (2 << GTIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
+# define GTIM_BDTR_LOCK3 (3 << GTIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */
+#define GTIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
+#define GTIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */
+#define GTIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */
+#define GTIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */
+#define GTIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */
+#define GTIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */
+#define GTIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */
+#define GTIM_BDTR_BKF_MASK (15 << GTIM_BDTR_BKF_SHIFT)
+# define GTIM_BDTR_BKF_NOFILT (0 << GTIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */
+# define GTIM_BDTR_BKF_FCKINT2 (1 << GTIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */
+# define GTIM_BDTR_BKF_FCKINT4 (2 << GTIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */
+# define GTIM_BDTR_BKF_FCKINT8 (3 << GTIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */
+# define GTIM_BDTR_BKF_FDTSd26 (4 << GTIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */
+# define GTIM_BDTR_BKF_FDTSd28 (5 << GTIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */
+# define GTIM_BDTR_BKF_FDTSd36 (6 << GTIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */
+# define GTIM_BDTR_BKF_FDTSd38 (7 << GTIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */
+# define GTIM_BDTR_BKF_FDTSd86 (8 << GTIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */
+# define GTIM_BDTR_BKF_FDTSd88 (9 << GTIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */
+# define GTIM_BDTR_BKF_FDTSd165 (10 << GTIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
+# define GTIM_BDTR_BKF_FDTSd166 (11 << GTIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
+# define GTIM_BDTR_BKF_FDTSd168 (12 << GTIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
+# define GTIM_BDTR_BKF_FDTSd325 (13 << GTIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
+# define GTIM_BDTR_BKF_FDTSd326 (14 << GTIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
+# define GTIM_BDTR_BKF_FDTSd328 (15 << GTIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
+
+/* DMA control register */
+
+#define GTIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */
+#define GTIM_DCR_DBA_MASK (0x1f << GTIM_DCR_DBA_SHIFT)
+#define GTIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */
+#define GTIM_DCR_DBL_MASK (0x1f << GTIM_DCR_DBL_SHIFT)
+
+/* Timer 2/5 option register */
+
+# define TIM2_OR_ITR1_RMP_SHIFT (10) /* Bits 10-11: Internal trigger 1 remap */
+# define TIM2_OR_ITR1_RMP_MASK (3 << TIM2_OR_ITR1_RMP_SHIFT)
+# define TIM2_OR_ITR1_TIM8_TRGOUT (0 << TIM2_OR_ITR1_RMP_SHIFT) /* 00: TIM2_ITR1 input connected to TIM8_TRGOUT */
+# define TIM2_OR_ITR1_PTP (1 << TIM2_OR_ITR1_RMP_SHIFT) /* 01: TIM2_ITR1 input connected to PTP trigger output */
+# define TIM2_OR_ITR1_OTGFSSOF (2 << TIM2_OR_ITR1_RMP_SHIFT) /* 10: TIM2_ITR1 input connected to OTG FS SOF */
+# define TIM2_OR_ITR1_OTGHSSOF (3 << TIM2_OR_ITR1_RMP_SHIFT) /* 11: TIM2_ITR1 input connected to OTG HS SOF */
+
+# define TIM5_OR_TI4_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */
+# define TIM5_OR_TI4_RMP_MASK (3 << TIM5_OR_TI4_RMP_SHIFT)
+# define TIM5_OR_TI4_GPIO (0 << TIM5_OR_TI4_RMP_SHIFT) /* 00: TIM5_CH4 input connected to GPIO */
+# define TIM5_OR_TI4_LSI (1 << TIM5_OR_TI4_RMP_SHIFT) /* 01: TIM5_CH4 input connected to LSI internal clock */
+# define TIM5_OR_TI4_LSE (2 << TIM5_OR_TI4_RMP_SHIFT) /* 10: TIM5_CH4 input connected to LSE internal clock */
+# define TIM5_OR_TI4_RTC (3 << TIM5_OR_TI4_RMP_SHIFT) /* 11: TIM5_CH4 input connected to RTC output event */
+
+# define TIM11_OR_TI1_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */
+# define TIM11_OR_TI1_RMP_MASK (3 << TIM11_OR_TI1_RMP_SHIFT)
+# define TIM11_OR_TI1_GPIO (0 << TIM11_OR_TI1_RMP_SHIFT) /* 00-11: TIM11_CH1 input connected to GPIO */
+# define TIM11_OR_TI1_HSERTC (3 << TIM11_OR_TI1_RMP_SHIFT) /* 11: TIM11_CH1 input connected to HSE_RTC clock */
+
+
+/* Control register 1 */
+
+#define BTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */
+#define BTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */
+#define BTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */
+#define BTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode */
+#define BTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */
+
+/* Control register 2 */
+
+#define BTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */
+#define BTIM_CR2_MMS_MASK (7 << BTIM_CR2_MMS_SHIFT)
+# define BTIM_CR2_RESET (0 << BTIM_CR2_MMS_SHIFT) /* 000: Reset */
+# define BTIM_CR2_ENAB (1 << BTIM_CR2_MMS_SHIFT) /* 001: Enable */
+# define BTIM_CR2_UPDT (2 << BTIM_CR2_MMS_SHIFT) /* 010: Update */
+
+/* DMA/Interrupt enable register */
+
+#define BTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */
+#define BTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */
+
+/* Status register */
+
+#define BTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */
+
+/* Event generation register */
+
+#define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */
+
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_TIM_H */
diff --git a/arch/arm/src/stm32f7/stm32_tim.c b/arch/arm/src/stm32f7/stm32_tim.c
new file mode 100644
index 0000000000..7605a14a7f
--- /dev/null
+++ b/arch/arm/src/stm32f7/stm32_tim.c
@@ -0,0 +1,1099 @@
+/************************************************************************************
+ * arm/arm/src/stm32f7/stm32_tim.c
+ *
+ * Copyright (C) 2011 Uros Platise. All rights reserved.
+ * Author: Uros Platise
+ *
+ * With modifications and updates by:
+ *
+ * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "chip.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "stm32_gpio.h"
+#include "stm32_tim.h"
+
+/************************************************************************************
+ * Private Types
+ ************************************************************************************/
+/* Configuration ********************************************************************/
+/* Timer devices may be used for different purposes. Such special purposes include:
+ *
+ * - To generate modulated outputs for such things as motor control. If CONFIG_STM32F7_TIMn
+ * is defined then the CONFIG_STM32F7_TIMn_PWM may also be defined to indicate that
+ * the timer is intended to be used for pulsed output modulation.
+ *
+ * - To control periodic ADC input sampling. If CONFIG_STM32F7_TIMn is defined then
+ * CONFIG_STM32F7_TIMn_ADC may also be defined to indicate that timer "n" is intended
+ * to be used for that purpose.
+ *
+ * - To control periodic DAC outputs. If CONFIG_STM32F7_TIMn is defined then
+ * CONFIG_STM32F7_TIMn_DAC may also be defined to indicate that timer "n" is intended
+ * to be used for that purpose.
+ *
+ * - To use a Quadrature Encoder. If CONFIG_STM32F7_TIMn is defined then
+ * CONFIG_STM32F7_TIMn_QE may also be defined to indicate that timer "n" is intended
+ * to be used for that purpose.
+ *
+ * In any of these cases, the timer will not be used by this timer module.
+ */
+
+#if defined(CONFIG_STM32F7_TIM1_PWM) || defined (CONFIG_STM32F7_TIM1_ADC) || \
+ defined(CONFIG_STM32F7_TIM1_DAC) || defined(CONFIG_STM32F7_TIM1_QE)
+# undef CONFIG_STM32F7_TIM1
+#endif
+#if defined(CONFIG_STM32F7_TIM2_PWM) || defined (CONFIG_STM32F7_TIM2_ADC) || \
+ defined(CONFIG_STM32F7_TIM2_DAC) || defined(CONFIG_STM32F7_TIM2_QE)
+# undef CONFIG_STM32F7_TIM2
+#endif
+#if defined(CONFIG_STM32F7_TIM3_PWM) || defined (CONFIG_STM32F7_TIM3_ADC) || \
+ defined(CONFIG_STM32F7_TIM3_DAC) || defined(CONFIG_STM32F7_TIM3_QE)
+# undef CONFIG_STM32F7_TIM3
+#endif
+#if defined(CONFIG_STM32F7_TIM4_PWM) || defined (CONFIG_STM32F7_TIM4_ADC) || \
+ defined(CONFIG_STM32F7_TIM4_DAC) || defined(CONFIG_STM32F7_TIM4_QE)
+# undef CONFIG_STM32F7_TIM4
+#endif
+#if defined(CONFIG_STM32F7_TIM5_PWM) || defined (CONFIG_STM32F7_TIM5_ADC) || \
+ defined(CONFIG_STM32F7_TIM5_DAC) || defined(CONFIG_STM32F7_TIM5_QE)
+# undef CONFIG_STM32F7_TIM5
+#endif
+#if defined(CONFIG_STM32F7_TIM6_PWM) || defined (CONFIG_STM32F7_TIM6_ADC) || \
+ defined(CONFIG_STM32F7_TIM6_DAC) || defined(CONFIG_STM32F7_TIM6_QE)
+# undef CONFIG_STM32F7_TIM6
+#endif
+#if defined(CONFIG_STM32F7_TIM7_PWM) || defined (CONFIG_STM32F7_TIM7_ADC) || \
+ defined(CONFIG_STM32F7_TIM7_DAC) || defined(CONFIG_STM32F7_TIM7_QE)
+# undef CONFIG_STM32F7_TIM7
+#endif
+#if defined(CONFIG_STM32F7_TIM8_PWM) || defined (CONFIG_STM32F7_TIM8_ADC) || \
+ defined(CONFIG_STM32F7_TIM8_DAC) || defined(CONFIG_STM32F7_TIM8_QE)
+# undef CONFIG_STM32F7_TIM8
+#endif
+#if defined(CONFIG_STM32F7_TIM9_PWM) || defined (CONFIG_STM32F7_TIM9_ADC) || \
+ defined(CONFIG_STM32F7_TIM9_DAC) || defined(CONFIG_STM32F7_TIM9_QE)
+# undef CONFIG_STM32F7_TIM9
+#endif
+#if defined(CONFIG_STM32F7_TIM10_PWM) || defined (CONFIG_STM32F7_TIM10_ADC) || \
+ defined(CONFIG_STM32F7_TIM10_DAC) || defined(CONFIG_STM32F7_TIM10_QE)
+# undef CONFIG_STM32F7_TIM10
+#endif
+#if defined(CONFIG_STM32F7_TIM11_PWM) || defined (CONFIG_STM32F7_TIM11_ADC) || \
+ defined(CONFIG_STM32F7_TIM11_DAC) || defined(CONFIG_STM32F7_TIM11_QE)
+# undef CONFIG_STM32F7_TIM11
+#endif
+#if defined(CONFIG_STM32F7_TIM12_PWM) || defined (CONFIG_STM32F7_TIM12_ADC) || \
+ defined(CONFIG_STM32F7_TIM12_DAC) || defined(CONFIG_STM32F7_TIM12_QE)
+# undef CONFIG_STM32F7_TIM12
+#endif
+#if defined(CONFIG_STM32F7_TIM13_PWM) || defined (CONFIG_STM32F7_TIM13_ADC) || \
+ defined(CONFIG_STM32F7_TIM13_DAC) || defined(CONFIG_STM32F7_TIM13_QE)
+# undef CONFIG_STM32F7_TIM13
+#endif
+#if defined(CONFIG_STM32F7_TIM14_PWM) || defined (CONFIG_STM32F7_TIM14_ADC) || \
+ defined(CONFIG_STM32F7_TIM14_DAC) || defined(CONFIG_STM32F7_TIM14_QE)
+# undef CONFIG_STM32F7_TIM14
+#endif
+
+#if defined(CONFIG_STM32F7_TIM1)
+# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\
+ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)
+# define HAVE_TIM1_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32F7_TIM2)
+# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\
+ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT)
+# define HAVE_TIM2_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32F7_TIM3)
+# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\
+ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT)
+# define HAVE_TIM3_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32F7_TIM4)
+# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\
+ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT)
+# define HAVE_TIM4_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32F7_TIM5)
+# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\
+ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT)
+# define HAVE_TIM5_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32F7_TIM8)
+# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\
+ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)
+# define HAVE_TIM8_GPIOCONFIG 1
+#endif
+#endif
+
+
+/* This module then only compiles if there are enabled timers that are not intended for
+ * some other purpose.
+ */
+
+#if defined(CONFIG_STM32F7_TIM1) || defined(CONFIG_STM32F7_TIM2) || defined(CONFIG_STM32F7_TIM3) || \
+ defined(CONFIG_STM32F7_TIM4) || defined(CONFIG_STM32F7_TIM5) || defined(CONFIG_STM32F7_TIM6) || \
+ defined(CONFIG_STM32F7_TIM7) || defined(CONFIG_STM32F7_TIM8)
+
+/************************************************************************************
+ * Private Types
+ ************************************************************************************/
+
+/* TIM Device Structure */
+
+struct stm32_tim_priv_s
+{
+ struct stm32_tim_ops_s *ops;
+ stm32_tim_mode_t mode;
+ uint32_t base; /* TIMn base address */
+};
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/* Get a 16-bit register value by offset */
+
+static inline uint16_t stm32_getreg16(FAR struct stm32_tim_dev_s *dev,
+ uint8_t offset)
+{
+ return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset);
+}
+
+/* Put a 16-bit register value by offset */
+
+static inline void stm32_putreg16(FAR struct stm32_tim_dev_s *dev, uint8_t offset,
+ uint16_t value)
+{
+ putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset);
+}
+
+/* Modify a 16-bit register value by offset */
+
+static inline void stm32_modifyreg16(FAR struct stm32_tim_dev_s *dev,
+ uint8_t offset, uint16_t clearbits,
+ uint16_t setbits)
+{
+ modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits);
+}
+
+/* Get a 32-bit register value by offset. This applies only for the STM32 F4
+ * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5.
+ */
+
+static inline uint32_t stm32_getreg32(FAR struct stm32_tim_dev_s *dev,
+ uint8_t offset)
+{
+ return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset);
+}
+
+/* Put a 32-bit register value by offset. This applies only for the STM32 F4
+ * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5.
+ */
+
+static inline void stm32_putreg32(FAR struct stm32_tim_dev_s *dev, uint8_t offset,
+ uint32_t value)
+{
+ putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset);
+}
+
+static void stm32_tim_reload_counter(FAR struct stm32_tim_dev_s *dev)
+{
+ uint16_t val = stm32_getreg16(dev, STM32_BTIM_EGR_OFFSET);
+ val |= ATIM_EGR_UG;
+ stm32_putreg16(dev, STM32_BTIM_EGR_OFFSET, val);
+}
+
+static void stm32_tim_enable(FAR struct stm32_tim_dev_s *dev)
+{
+ uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET);
+ val |= ATIM_CR1_CEN;
+ stm32_tim_reload_counter(dev);
+ stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val);
+}
+
+static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev)
+{
+ uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET);
+ val &= ~ATIM_CR1_CEN;
+ stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val);
+}
+
+/* Reset timer into system default state, but do not affect output/input pins */
+
+static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev)
+{
+ ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED;
+ stm32_tim_disable(dev);
+}
+
+#if defined(HAVE_TIM1_GPIOCONFIG)||defined(HAVE_TIM2_GPIOCONFIG)||\
+ defined(HAVE_TIM3_GPIOCONFIG)||defined(HAVE_TIM4_GPIOCONFIG)||\
+ defined(HAVE_TIM5_GPIOCONFIG)||defined(HAVE_TIM8_GPIOCONFIG)
+static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode)
+{
+ /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */
+
+ if (mode & STM32_TIM_CH_MODE_MASK)
+ {
+ stm32_configgpio(cfg);
+ }
+ else
+ {
+ stm32_unconfiggpio(cfg);
+ }
+}
+#endif
+
+/************************************************************************************
+ * Basic Functions
+ ************************************************************************************/
+
+static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
+{
+ int prescaler;
+
+ ASSERT(dev);
+
+ /* Disable Timer? */
+
+ if (freq == 0)
+ {
+ stm32_tim_disable(dev);
+ return 0;
+ }
+
+#if STM32F7_NATIM > 0
+ if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE ||
+ ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE)
+ {
+ prescaler = STM32_TIM18_FREQUENCY / freq;
+ }
+ else
+#endif
+ {
+ prescaler = STM32_TIM27_FREQUENCY / freq;
+ }
+
+ /* We need to decrement value for '1', but only, if we are allowed to
+ * not to cause underflow. Check for overflow.
+ */
+
+ if (prescaler > 0)
+ {
+ prescaler--;
+ }
+
+ if (prescaler > 0xffff)
+ {
+ prescaler = 0xffff;
+ }
+
+ stm32_putreg16(dev, STM32_BTIM_PSC_OFFSET, prescaler);
+ stm32_tim_enable(dev);
+
+ return prescaler;
+}
+
+static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev,
+ uint32_t period)
+{
+ ASSERT(dev);
+ stm32_putreg32(dev, STM32_BTIM_ARR_OFFSET, period);
+}
+
+static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
+ int (*handler)(int irq, void *context),
+ int source)
+{
+ int vectorno;
+
+ ASSERT(dev);
+ ASSERT(source == 0);
+
+ switch (((struct stm32_tim_priv_s *)dev)->base)
+ {
+#ifdef CONFIG_STM32F7_TIM2
+ case STM32_TIM2_BASE:
+ vectorno = STM32_IRQ_TIM2;
+ break;
+#endif
+#ifdef CONFIG_STM32F7_TIM3
+ case STM32_TIM3_BASE:
+ vectorno = STM32_IRQ_TIM3;
+ break;
+#endif
+#ifdef CONFIG_STM32F7_TIM4
+ case STM32_TIM4_BASE:
+ vectorno = STM32_IRQ_TIM4;
+ break;
+#endif
+#ifdef CONFIG_STM32F7_TIM5
+ case STM32_TIM5_BASE:
+ vectorno = STM32_IRQ_TIM5;
+ break;
+#endif
+#if STM32F7_NBTIM > 0
+#ifdef CONFIG_STM32F7_TIM6
+ case STM32_TIM6_BASE:
+ vectorno = STM32_IRQ_TIM6;
+ break;
+#endif
+#endif
+#if STM32F7_NBTIM > 1
+#ifdef CONFIG_STM32F7_TIM7
+ case STM32_TIM7_BASE:
+ vectorno = STM32_IRQ_TIM7;
+ break;
+#endif
+#endif
+#if STM32F7_NATIM > 0
+ /* TODO: add support for multiple sources and callbacks */
+
+#ifdef CONFIG_STM32F7_TIM1
+ case STM32_TIM1_BASE:
+ vectorno = STM32_IRQ_TIM1UP;
+ break;
+#endif
+#ifdef CONFIG_STM32F7_TIM8
+ case STM32_TIM8_BASE:
+ vectorno = STM32_IRQ_TIM8UP;
+ break;
+#endif
+#endif
+ default:
+ return ERROR;
+ }
+
+ /* Disable interrupt when callback is removed */
+
+ if (!handler)
+ {
+ up_disable_irq(vectorno);
+ irq_detach(vectorno);
+ return OK;
+ }
+
+ /* Otherwise set callback and enable interrupt */
+
+ irq_attach(vectorno, handler);
+ up_enable_irq(vectorno);
+
+#ifdef CONFIG_ARCH_IRQPRIO
+ /* Set the interrupt priority */
+
+ up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT);
+#endif
+
+ return OK;
+}
+
+static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source)
+{
+ ASSERT(dev);
+ stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, 0, ATIM_DIER_UIE);
+}
+
+static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source)
+{
+ ASSERT(dev);
+ stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0);
+}
+
+static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source)
+{
+ stm32_putreg16(dev, STM32_BTIM_SR_OFFSET, ~ATIM_SR_UIF);
+}
+
+/************************************************************************************
+ * General Functions
+ ************************************************************************************/
+
+static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode)
+{
+ uint16_t val = ATIM_CR1_CEN | ATIM_CR1_ARPE;
+
+ ASSERT(dev);
+
+ /* This function is not supported on basic timers. To enable or
+ * disable it, simply set its clock to valid frequency or zero.
+ */
+
+#if STM32F7_NBTIM > 0
+ if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE
+#endif
+#if STM32F7_NBTIM > 1
+ || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE
+#endif
+#if STM32F7_NBTIM > 0
+ )
+ {
+ return ERROR;
+ }
+#endif
+
+ /* Decode operational modes */
+
+ switch (mode & STM32_TIM_MODE_MASK)
+ {
+ case STM32_TIM_MODE_DISABLED:
+ val = 0;
+ break;
+
+ case STM32_TIM_MODE_DOWN:
+ val |= ATIM_CR1_DIR;
+
+ case STM32_TIM_MODE_UP:
+ break;
+
+ case STM32_TIM_MODE_UPDOWN:
+ val |= ATIM_CR1_CENTER1;
+ // Our default: Interrupts are generated on compare, when counting down
+ break;
+
+ case STM32_TIM_MODE_PULSE:
+ val |= ATIM_CR1_OPM;
+ break;
+
+ default:
+ return ERROR;
+ }
+
+ stm32_tim_reload_counter(dev);
+ stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val);
+
+#if STM32F7_NATIM > 0
+ /* Advanced registers require Main Output Enable */
+
+ if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE ||
+ ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE)
+ {
+ stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE);
+ }
+#endif
+
+ return OK;
+}
+
+static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
+ stm32_tim_channel_t mode)
+{
+ uint16_t ccmr_orig = 0;
+ uint16_t ccmr_val = 0;
+ uint16_t ccmr_mask = 0xff;
+ uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET);
+ uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET;
+
+ ASSERT(dev);
+
+ /* Further we use range as 0..3; if channel=0 it will also overflow here */
+
+ if (--channel > 4)
+ {
+ return ERROR;
+ }
+
+ /* Assume that channel is disabled and polarity is active high */
+
+ ccer_val &= ~(3 << (channel << 2));
+
+ /* This function is not supported on basic timers. To enable or
+ * disable it, simply set its clock to valid frequency or zero.
+ */
+
+#if STM32F7_NBTIM > 0
+ if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE
+#endif
+#if STM32F7_NBTIM > 1
+ || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE
+#endif
+#if STM32F7_NBTIM > 0
+ )
+ {
+ return ERROR;
+ }
+#endif
+
+ /* Decode configuration */
+
+ switch (mode & STM32_TIM_CH_MODE_MASK)
+ {
+ case STM32_TIM_CH_DISABLED:
+ break;
+
+ case STM32_TIM_CH_OUTPWM:
+ ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) + ATIM_CCMR1_OC1PE;
+ ccer_val |= ATIM_CCER_CC1E << (channel << 2);
+ break;
+
+ default:
+ return ERROR;
+ }
+
+ /* Set polarity */
+
+ if (mode & STM32_TIM_CH_POLARITY_NEG)
+ {
+ ccer_val |= ATIM_CCER_CC1P << (channel << 2);
+ }
+
+ /* Define its position (shift) and get register offset */
+
+ if (channel & 1)
+ {
+ ccmr_val <<= 8;
+ ccmr_mask <<= 8;
+ }
+
+ if (channel > 1)
+ {
+ ccmr_offset = STM32_GTIM_CCMR2_OFFSET;
+ }
+
+ ccmr_orig = stm32_getreg16(dev, ccmr_offset);
+ ccmr_orig &= ~ccmr_mask;
+ ccmr_orig |= ccmr_val;
+ stm32_putreg16(dev, ccmr_offset, ccmr_orig);
+ stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val);
+
+ /* set GPIO */
+
+ switch (((struct stm32_tim_priv_s *)dev)->base)
+ {
+#ifdef CONFIG_STM32F7_TIM2
+ case STM32_TIM2_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM2_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM2_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM2_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM2_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return ERROR;
+ }
+ break;
+#endif
+#ifdef CONFIG_STM32F7_TIM3
+ case STM32_TIM3_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM3_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM3_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM3_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM3_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return ERROR;
+ }
+ break;
+#endif
+#ifdef CONFIG_STM32F7_TIM4
+ case STM32_TIM4_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM4_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM4_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM4_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM4_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return ERROR;
+ }
+ break;
+#endif
+#ifdef CONFIG_STM32F7_TIM5
+ case STM32_TIM5_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM5_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM5_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM5_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM5_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return ERROR;
+ }
+ break;
+#endif
+
+#if STM32F7_NATIM > 0
+#ifdef CONFIG_STM32F7_TIM1
+ case STM32_TIM1_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM1_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break;
+#endif
+#if defined(GPIO_TIM1_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break;
+#endif
+#if defined(GPIO_TIM1_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break;
+#endif
+#if defined(GPIO_TIM1_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break;
+#endif
+ default:
+ return ERROR;
+ }
+ break;
+#endif
+#ifdef CONFIG_STM32F7_TIM8
+ case STM32_TIM8_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM8_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break;
+#endif
+#if defined(GPIO_TIM8_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break;
+#endif
+#if defined(GPIO_TIM8_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break;
+#endif
+#if defined(GPIO_TIM8_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break;
+#endif
+ default:
+ return ERROR;
+ }
+ break;
+#endif
+#endif
+ default:
+ return ERROR;
+ }
+
+ return OK;
+}
+
+static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
+ uint32_t compare)
+{
+ ASSERT(dev);
+
+ switch (channel)
+ {
+ case 1:
+ stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare);
+ break;
+ case 2:
+ stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare);
+ break;
+ case 3:
+ stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare);
+ break;
+ case 4:
+ stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare);
+ break;
+ default:
+ return ERROR;
+ }
+ return OK;
+}
+
+static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel)
+{
+ ASSERT(dev);
+
+ switch (channel)
+ {
+ case 1:
+ return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET);
+ case 2:
+ return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET);
+ case 3:
+ return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET);
+ case 4:
+ return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET);
+ }
+
+ return ERROR;
+}
+
+/************************************************************************************
+ * Advanced Functions
+ ************************************************************************************/
+
+/* TODO: Advanced functions for the STM32_ATIM */
+
+/************************************************************************************
+ * Device Structures, Instantiation
+ ************************************************************************************/
+
+struct stm32_tim_ops_s stm32_tim_ops =
+{
+ .setmode = &stm32_tim_setmode,
+ .setclock = &stm32_tim_setclock,
+ .setperiod = &stm32_tim_setperiod,
+ .setchannel = &stm32_tim_setchannel,
+ .setcompare = &stm32_tim_setcompare,
+ .getcapture = &stm32_tim_getcapture,
+ .setisr = &stm32_tim_setisr,
+ .enableint = &stm32_tim_enableint,
+ .disableint = &stm32_tim_disableint,
+ .ackint = &stm32_tim_ackint
+};
+
+#ifdef CONFIG_STM32F7_TIM2
+struct stm32_tim_priv_s stm32_tim2_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM2_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM3
+struct stm32_tim_priv_s stm32_tim3_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM3_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM4
+struct stm32_tim_priv_s stm32_tim4_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM4_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM5
+struct stm32_tim_priv_s stm32_tim5_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM5_BASE,
+};
+#endif
+
+#if STM32F7_NBTIM > 0
+#ifdef CONFIG_STM32F7_TIM6
+struct stm32_tim_priv_s stm32_tim6_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM6_BASE,
+};
+#endif
+#endif
+
+#if STM32F7_NBTIM > 1
+#ifdef CONFIG_STM32F7_TIM7
+struct stm32_tim_priv_s stm32_tim7_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM7_BASE,
+};
+#endif
+#endif
+
+#if STM32F7_NATIM > 0
+
+#ifdef CONFIG_STM32F7_TIM1
+struct stm32_tim_priv_s stm32_tim1_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM1_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM8
+struct stm32_tim_priv_s stm32_tim8_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM8_BASE,
+};
+#endif
+
+#endif
+
+/************************************************************************************
+ * Public Function - Initialization
+ ************************************************************************************/
+
+FAR struct stm32_tim_dev_s *stm32_tim_init(int timer)
+{
+ struct stm32_tim_dev_s *dev = NULL;
+
+ /* Get structure and enable power */
+
+ switch (timer)
+ {
+#ifdef CONFIG_STM32F7_TIM2
+ case 2:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv;
+ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN);
+ break;
+#endif
+#ifdef CONFIG_STM32F7_TIM3
+ case 3:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv;
+ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN);
+ break;
+#endif
+#ifdef CONFIG_STM32F7_TIM4
+ case 4:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv;
+ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN);
+ break;
+#endif
+#ifdef CONFIG_STM32F7_TIM5
+ case 5:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv;
+ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN);
+ break;
+#endif
+
+#if STM32F7_NBTIM > 0
+#ifdef CONFIG_STM32F7_TIM6
+ case 6:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv;
+ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN);
+ break;
+#endif
+#endif
+#if STM32F7_NBTIM > 1
+#ifdef CONFIG_STM32F7_TIM7
+ case 7:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv;
+ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN);
+ break;
+#endif
+#endif
+
+#if STM32F7_NATIM > 0
+#ifdef CONFIG_STM32F7_TIM1
+ case 1:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv;
+ modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
+ break;
+#endif
+#ifdef CONFIG_STM32F7_TIM8
+ case 8:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv;
+ modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
+ break;
+#endif
+#endif
+ default:
+ return NULL;
+ }
+
+ /* Is device already allocated */
+
+ if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED)
+ {
+ return NULL;
+ }
+
+ stm32_tim_reset(dev);
+
+ return dev;
+}
+
+/* TODO: Detach interrupts, and close down all TIM Channels */
+
+int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
+{
+ ASSERT(dev);
+
+ /* Disable power */
+
+ switch (((struct stm32_tim_priv_s *)dev)->base)
+ {
+#ifdef CONFIG_STM32F7_TIM2
+ case STM32_TIM2_BASE:
+ modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0);
+ break;
+#endif
+#ifdef CONFIG_STM32F7_TIM3
+ case STM32_TIM3_BASE:
+ modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0);
+ break;
+#endif
+#ifdef CONFIG_STM32F7_TIM4
+ case STM32_TIM4_BASE:
+ modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0);
+ break;
+#endif
+#ifdef CONFIG_STM32F7_TIM5
+ case STM32_TIM5_BASE:
+ modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0);
+ break;
+#endif
+#if STM32F7_NBTIM > 0
+#ifdef CONFIG_STM32F7_TIM6
+ case STM32_TIM6_BASE:
+ modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0);
+ break;
+#endif
+#endif
+#if STM32F7_NBTIM > 1
+#ifdef CONFIG_STM32F7_TIM7
+ case STM32_TIM7_BASE:
+ modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0);
+ break;
+#endif
+#endif
+
+#if STM32F7_NATIM > 0
+#ifdef CONFIG_STM32F7_TIM1
+ case STM32_TIM1_BASE:
+ modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
+ break;
+#endif
+#ifdef CONFIG_STM32F7_TIM8
+ case STM32_TIM8_BASE:
+ modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0);
+ break;
+#endif
+#endif
+ default:
+ return ERROR;
+ }
+
+ /* Mark it as free */
+
+ ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED;
+
+ return OK;
+}
+
+#endif /* defined(CONFIG_STM32F7_TIM1 || ... || TIM8) */
diff --git a/arch/arm/src/stm32f7/stm32_tim.h b/arch/arm/src/stm32f7/stm32_tim.h
new file mode 100644
index 0000000000..c4561288a9
--- /dev/null
+++ b/arch/arm/src/stm32f7/stm32_tim.h
@@ -0,0 +1,215 @@
+/************************************************************************************
+ * arch/arm/src/stm32f7/stm32_tim.h
+ *
+ * Copyright (C) 2011 Uros Platise. All rights reserved.
+ * Author: Uros Platise
+ *
+ * With modifications and updates by:
+ *
+ * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_STM32_TIM_H
+#define __ARCH_ARM_SRC_STM32F7_STM32_TIM_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include "chip.h"
+#include "chip/stm32_tim.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Helpers **************************************************************************/
+
+#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode))
+#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
+#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period))
+#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode))
+#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp))
+#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch))
+#define STM32_TIM_SETISR(d,hnd,s) ((d)->ops->setisr(d,hnd,s))
+#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s))
+#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s))
+#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s))
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* TIM Device Structure */
+
+struct stm32_tim_dev_s
+{
+ struct stm32_tim_ops_s *ops;
+};
+
+/* TIM Modes of Operation */
+
+typedef enum
+{
+ STM32_TIM_MODE_UNUSED = -1,
+
+ /* One of the following */
+
+ STM32_TIM_MODE_MASK = 0x0310,
+ STM32_TIM_MODE_DISABLED = 0x0000,
+ STM32_TIM_MODE_UP = 0x0100,
+ STM32_TIM_MODE_DOWN = 0x0110,
+ STM32_TIM_MODE_UPDOWN = 0x0200,
+ STM32_TIM_MODE_PULSE = 0x0300,
+
+ /* One of the following */
+
+ STM32_TIM_MODE_CK_INT = 0x0000,
+//STM32_TIM_MODE_CK_INT_TRIG = 0x0400,
+//STM32_TIM_MODE_CK_EXT = 0x0800,
+//STM32_TIM_MODE_CK_EXT_TRIG = 0x0C00,
+
+ /* Clock sources, OR'ed with CK_EXT */
+
+//STM32_TIM_MODE_CK_CHINVALID = 0x0000,
+//STM32_TIM_MODE_CK_CH1 = 0x0001,
+//STM32_TIM_MODE_CK_CH2 = 0x0002,
+//STM32_TIM_MODE_CK_CH3 = 0x0003,
+//STM32_TIM_MODE_CK_CH4 = 0x0004
+
+ /* Todo: external trigger block */
+
+} stm32_tim_mode_t;
+
+/* TIM Channel Modes */
+
+typedef enum
+{
+ STM32_TIM_CH_DISABLED = 0x00,
+
+ /* Common configuration */
+
+ STM32_TIM_CH_POLARITY_POS = 0x00,
+ STM32_TIM_CH_POLARITY_NEG = 0x01,
+
+ /* MODES: */
+
+ STM32_TIM_CH_MODE_MASK = 0x06,
+
+ /* Output Compare Modes */
+
+ STM32_TIM_CH_OUTPWM = 0x04, /** Enable standard PWM mode, active high when counter < compare */
+//STM32_TIM_CH_OUTCOMPARE = 0x06,
+
+ // TODO other modes ... as PWM capture, ENCODER and Hall Sensor
+//STM32_TIM_CH_INCAPTURE = 0x10,
+//STM32_TIM_CH_INPWM = 0x20
+//STM32_TIM_CH_DRIVE_OC -- open collector mode
+
+} stm32_tim_channel_t;
+
+/* TIM Operations */
+
+struct stm32_tim_ops_s
+{
+ /* Basic Timers */
+
+ int (*setmode)(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode);
+ int (*setclock)(FAR struct stm32_tim_dev_s *dev, uint32_t freq);
+ void (*setperiod)(FAR struct stm32_tim_dev_s *dev, uint32_t period);
+
+ /* General and Advanced Timers Adds */
+
+ int (*setchannel)(FAR struct stm32_tim_dev_s *dev, uint8_t channel, stm32_tim_channel_t mode);
+ int (*setcompare)(FAR struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare);
+ int (*getcapture)(FAR struct stm32_tim_dev_s *dev, uint8_t channel);
+
+ /* Timer interrupts */
+
+ int (*setisr)(FAR struct stm32_tim_dev_s *dev, int (*handler)(int irq, void *context), int source);
+ void (*enableint)(FAR struct stm32_tim_dev_s *dev, int source);
+ void (*disableint)(FAR struct stm32_tim_dev_s *dev, int source);
+ void (*ackint)(FAR struct stm32_tim_dev_s *dev, int source);
+};
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/* Power-up timer and get its structure */
+
+FAR struct stm32_tim_dev_s *stm32_tim_init(int timer);
+
+/* Power-down timer, mark it as unused */
+
+int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev);
+
+/****************************************************************************
+ * Name: stm32_timer_initialize
+ *
+ * Description:
+ * Bind the configuration timer to a timer lower half instance and
+ * register the timer drivers at 'devpath'
+ *
+ * Input Parameters:
+ * devpath - The full path to the timer device. This should be of the form /dev/timer0
+ * timer - the timer number.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_TIMER
+int stm32_timer_initialize(FAR const char *devpath, int timer);
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_STM32F7_STM32_TIM_H */
diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig
index 73e832d3fd..7648c14777 100644
--- a/configs/stm32f746-ws/nsh/defconfig
+++ b/configs/stm32f746-ws/nsh/defconfig
@@ -155,7 +155,7 @@ CONFIG_ARMV7M_HAVE_STACKCHECK=y
#
# STM32 F7 Configuration Options
#
-# CONFIG_ARCH_CHIP_STM32F745 is not set
+
CONFIG_ARCH_CHIP_STM32F746=y
# CONFIG_ARCH_CHIP_STM32F756 is not set
CONFIG_STM32F7_STM32F74XX=y
--
GitLab
From 82c73e206e058499090bcaaa6eb805f7fadc4dbb Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Thu, 2 Jun 2016 07:58:13 -0600
Subject: [PATCH 030/400] STM32 F4 RTC, trivial changes
---
arch/arm/src/stm32/stm32f40xxx_rtcc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
index a1f46513ef..22fd766f6c 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
@@ -38,6 +38,8 @@
* Included Files
************************************************************************************/
+#include
+
#include
#include
#include
@@ -216,9 +218,6 @@ static void rtc_dumpregs(FAR const char *msg)
rtclldbg(" ISR: %08x\n", getreg32(STM32_RTC_ISR));
rtclldbg(" PRER: %08x\n", getreg32(STM32_RTC_PRER));
rtclldbg(" WUTR: %08x\n", getreg32(STM32_RTC_WUTR));
-#ifndef CONFIG_STM32_STM32F30XX
- rtclldbg(" CALIBR: %08x\n", getreg32(STM32_RTC_CALIBR));
-#endif
rtclldbg(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR));
rtclldbg(" ALRMBR: %08x\n", getreg32(STM32_RTC_ALRMBR));
rtclldbg(" SHIFTR: %08x\n", getreg32(STM32_RTC_SHIFTR));
--
GitLab
From 3bb60966e7eee6f8190ce5e7d4f96f9b40dcabb6 Mon Sep 17 00:00:00 2001
From: Lok Tep
Date: Thu, 2 Jun 2016 16:17:58 +0200
Subject: [PATCH 031/400] adc copy
---
arch/arm/src/stm32f7/Make.defs | 4 +
arch/arm/src/stm32f7/chip/stm32_adc.h | 495 +++++++
arch/arm/src/stm32f7/stm32_adc.c | 1700 +++++++++++++++++++++++++
arch/arm/src/stm32f7/stm32_adc.h | 774 +++++++++++
4 files changed, 2973 insertions(+)
create mode 100644 arch/arm/src/stm32f7/chip/stm32_adc.h
create mode 100644 arch/arm/src/stm32f7/stm32_adc.c
create mode 100644 arch/arm/src/stm32f7/stm32_adc.h
diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs
index cf86c88c3e..39364a5f95 100644
--- a/arch/arm/src/stm32f7/Make.defs
+++ b/arch/arm/src/stm32f7/Make.defs
@@ -139,6 +139,10 @@ ifeq ($(CONFIG_STM32_PWR),y)
CHIP_CSRCS += stm32_exti_pwr.c
endif
+ifeq ($(CONFIG_ADC),y)
+CHIP_CSRCS += stm32_adc.c
+endif
+
ifeq ($(CONFIG_RTC),y)
ifeq ($(CONFIG_RTC_ALARM),y)
CHIP_CSRCS += stm32_exti_alarm.c
diff --git a/arch/arm/src/stm32f7/chip/stm32_adc.h b/arch/arm/src/stm32f7/chip/stm32_adc.h
new file mode 100644
index 0000000000..600d6c23b9
--- /dev/null
+++ b/arch/arm/src/stm32f7/chip/stm32_adc.h
@@ -0,0 +1,495 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32_adc.h
+ *
+ * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F_CHIP_STM32_ADC_H
+#define __ARCH_ARM_SRC_STM32F_CHIP_STM32_ADC_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* Register Offsets *********************************************************************************/
+
+#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */
+#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */
+#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */
+#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */
+#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */
+#define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 (32-bit) */
+#define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 (32-bit) */
+#define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 (32-bit) */
+#define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 (32-bit) */
+#define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register (32-bit) */
+#define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register (32-bit) */
+#define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 (32-bit) */
+#define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 (32-bit) */
+#define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 (32-bit) */
+#define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register (32-bit) */
+#define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 (32-bit) */
+#define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 1 (32-bit) */
+#define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 1 (32-bit) */
+#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */
+#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */
+
+
+#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */
+#define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */
+#define STM32_ADC_CDR_OFFSET 0x0008 /* Data register for dual and triple modes */
+
+/* Register Addresses *******************************************************************************/
+
+#if STM32F7_NADC > 0
+# define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET)
+# define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET)
+# define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET)
+# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET)
+# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET)
+# define STM32_ADC1_JOFR1 (STM32_ADC1_BASE+STM32_ADC_JOFR1_OFFSET)
+# define STM32_ADC1_JOFR2 (STM32_ADC1_BASE+STM32_ADC_JOFR2_OFFSET)
+# define STM32_ADC1_JOFR3 (STM32_ADC1_BASE+STM32_ADC_JOFR3_OFFSET)
+# define STM32_ADC1_JOFR4 (STM32_ADC1_BASE+STM32_ADC_JOFR4_OFFSET)
+# define STM32_ADC1_HTR (STM32_ADC1_BASE+STM32_ADC_HTR_OFFSET)
+# define STM32_ADC1_LTR (STM32_ADC1_BASE+STM32_ADC_LTR_OFFSET)
+# define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET)
+# define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET)
+# define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET)
+# define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET)
+# define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET)
+# define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET)
+# define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET)
+# define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET)
+# define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET)
+#endif
+
+#if STM32F7_NADC > 1
+# define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET)
+# define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET)
+# define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET)
+# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET)
+# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET)
+# define STM32_ADC2_JOFR1 (STM32_ADC2_BASE+STM32_ADC_JOFR1_OFFSET)
+# define STM32_ADC2_JOFR2 (STM32_ADC2_BASE+STM32_ADC_JOFR2_OFFSET)
+# define STM32_ADC2_JOFR3 (STM32_ADC2_BASE+STM32_ADC_JOFR3_OFFSET)
+# define STM32_ADC2_JOFR4 (STM32_ADC2_BASE+STM32_ADC_JOFR4_OFFSET)
+# define STM32_ADC2_HTR (STM32_ADC2_BASE+STM32_ADC_HTR_OFFSET)
+# define STM32_ADC2_LTR (STM32_ADC2_BASE+STM32_ADC_LTR_OFFSET)
+# define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET)
+# define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET)
+# define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET)
+# define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET)
+# define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET)
+# define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET)
+# define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET)
+# define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET)
+# define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET)
+#endif
+
+#if STM32F7_NADC > 2
+# define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET)
+# define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET)
+# define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET)
+# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET)
+# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET)
+# define STM32_ADC3_JOFR1 (STM32_ADC3_BASE+STM32_ADC_JOFR1_OFFSET)
+# define STM32_ADC3_JOFR2 (STM32_ADC3_BASE+STM32_ADC_JOFR2_OFFSET)
+# define STM32_ADC3_JOFR3 (STM32_ADC3_BASE+STM32_ADC_JOFR3_OFFSET)
+# define STM32_ADC3_JOFR4 (STM32_ADC3_BASE+STM32_ADC_JOFR4_OFFSET)
+# define STM32_ADC3_HTR (STM32_ADC3_BASE+STM32_ADC_HTR_OFFSET)
+# define STM32_ADC3_LTR (STM32_ADC3_BASE+STM32_ADC_LTR_OFFSET)
+# define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET)
+# define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET)
+# define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET)
+# define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET)
+# define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET)
+# define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET)
+# define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET)
+# define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET)
+# define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET)
+#endif
+
+#define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET)
+#define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET)
+#define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET)
+
+/* Register Bitfield Definitions ********************************************************************/
+
+/* ADC status register */
+
+#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */
+#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */
+#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */
+#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */
+#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */
+#define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */
+
+/* ADC control register 1 */
+
+#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */
+#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT)
+
+#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */
+#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */
+#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */
+#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */
+#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */
+
+#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */
+#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT)
+
+
+#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */
+
+#define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */
+#define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT)
+#define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK cycles. For STM32L15XX: 12 ADCCLK cycles */
+#define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK cycles. For STM32L15XX: 11 ADCCLK cycles */
+#define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles. For STM32L15XX: 9 ADCCLK cycles */
+#define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles. For STM32L15XX: 7 ADCCLK cycles */
+#define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */
+
+/* ADC control register 2 */
+
+#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */
+#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */
+
+#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */
+
+#define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */
+#define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */
+
+#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */
+
+ /* Bits 12-15: Reserved */
+#define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */
+#define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT)
+#define ADC_CR2_JEXTSEL_T1TRGO (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 TRGO event */
+#define ADC_CR2_JEXTSEL_T1CC4 (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 CC4 event */
+#define ADC_CR2_JEXTSEL_T2TRGO (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event */
+#define ADC_CR2_JEXTSEL_T2CC1 (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */
+#define ADC_CR2_JEXTSEL_T3CC4 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */
+#define ADC_CR2_JEXTSEL_T4TRGO (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */
+ /* 0110: NA */
+#define ADC_CR2_JEXTSEL_T8CC4 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 8 CC4 event */
+#define ADC_CR2_JEXTSEL_T1TRGO2 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 1 TRGO2 event */
+#define ADC_CR2_JEXTSEL_T8TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 8 TRGO event */
+#define ADC_CR2_JEXTSEL_T8TRGO2 (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 8 TRGO2 event */
+#define ADC_CR2_JEXTSEL_T3CC3 (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 3 CC3 event */
+#define ADC_CR2_JEXTSEL_T5TRGO (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 5 TRGO event */
+#define ADC_CR2_JEXTSEL_T3CC1 (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 3 CC1 event */
+#define ADC_CR2_JEXTSEL_T6TRGO (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 6 TRGO event */
+ /* 1111: NA */
+#define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */
+#define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT)
+#define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
+#define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
+#define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
+#define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
+
+#define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */
+ /* Bit 23: Reserved, must be kept at reset value. */
+#define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */
+#define ADC_CR2_EXTSEL_MASK (0x0F << ADC_CR2_EXTSEL_SHIFT)
+#define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */
+#define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */
+#define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */
+#define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */
+#define ADC_CR2_EXTSEL_T5TRGO (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 5 TRGO event */
+#define ADC_CR2_EXTSEL_T4CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */
+#define ADC_CR2_EXTSEL_T3CC4 (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 3 CC4 event */
+#define ADC_CR2_EXTSEL_T8TRGO (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 8 TRGO event */
+#define ADC_CR2_EXTSEL_T8TRGO2 (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 8 TRGO2 event */
+#define ADC_CR2_EXTSEL_T1TRGO (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 1 TRGO event */
+#define ADC_CR2_EXTSEL_T1TRGO2 (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 1 TRGO2 event */
+#define ADC_CR2_EXTSEL_T2TRGO (0x0B << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 2 TRGO event */
+#define ADC_CR2_EXTSEL_T4TRGO (0x0C << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 4 TRGO event */
+#define ADC_CR2_EXTSEL_T6TRGO (0x0D << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 6 TRGO event */
+ /* 1110: NA */
+#define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */
+
+#define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */
+#define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT)
+#define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */
+#define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
+#define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
+#define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
+
+# define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */
+
+/* ADC sample time register 1 */
+
+#define ADC_SMPR_3 0 /* 000: 3 cycles */
+#define ADC_SMPR_15 1 /* 001: 15 cycles */
+#define ADC_SMPR_28 2 /* 010: 28 cycles */
+#define ADC_SMPR_56 3 /* 011: 56 cycles */
+#define ADC_SMPR_84 4 /* 100: 84 cycles */
+#define ADC_SMPR_112 5 /* 101: 112 cycles */
+#define ADC_SMPR_144 6 /* 110: 144 cycles */
+#define ADC_SMPR_480 7 /* 111: 480 cycles */
+
+#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */
+#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT)
+#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */
+#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT)
+#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */
+#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT)
+#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */
+#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT)
+#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */
+#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT)
+#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */
+#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT)
+#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */
+#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT)
+#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
+#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
+#define ADC_SMPR1_SMP18_SHIFT (21) /* Bits 24-26: Channel 18 Sample time selection */
+#define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
+
+
+/* ADC sample time register 2 */
+
+#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */
+#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT)
+#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */
+#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT)
+#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */
+#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT)
+#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */
+#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT)
+#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */
+#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT)
+#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */
+#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT)
+#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */
+#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT)
+#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */
+#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT)
+#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */
+#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT)
+#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */
+#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT)
+
+
+/* ADC injected channel data offset register 1-4 */
+
+#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */
+#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT)
+
+/* ADC watchdog high threshold register */
+
+#define ADC_HTR_SHIFT (0) /* Bits 11-0: Analog watchdog high threshold */
+#define ADC_HTR_MASK (0x0fff << ADC_HTR_SHIFT)
+
+/* ADC watchdog low threshold register */
+
+#define ADC_LTR_SHIFT (0) /* Bits 11-0: Analog watchdog low threshold */
+#define ADC_LTR_MASK (0x0fff << ADC_LTR_SHIFT)
+
+/* ADC regular sequence register 1 */
+
+#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */
+#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT)
+#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */
+#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT)
+#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */
+#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT)
+#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */
+#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT)
+#define ADC_SQR1_L_SHIFT (20) /* Bits 23-20: Regular channel sequence length */
+#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT)
+#define ADC_SQR1_RESERVED (0xff000000)
+#define ADC_SQR1_FIRST (13)
+#define ADC_SQR1_LAST (16)
+#define ADC_SQR1_SQ_OFFSET (0)
+
+/* ADC regular sequence register 2 */
+
+#define ADC_SQR2_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */
+#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT)
+#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */
+#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT)
+#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */
+#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT)
+#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */
+#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT)
+#define ADC_SQR2_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */
+#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT )
+#define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */
+#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT)
+#define ADC_SQR2_RESERVED (0xc0000000)
+#define ADC_SQR2_FIRST (7)
+#define ADC_SQR2_LAST (12)
+#define ADC_SQR2_SQ_OFFSET (0)
+
+/* ADC regular sequence register 3 */
+
+#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */
+#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT)
+#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */
+#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT)
+#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */
+#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT)
+#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */
+#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT)
+#define ADC_SQR3_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */
+#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT )
+#define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */
+#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT)
+#define ADC_SQR3_RESERVED (0xc0000000)
+#define ADC_SQR3_FIRST (1)
+#define ADC_SQR3_LAST (6)
+#define ADC_SQR3_SQ_OFFSET (0)
+
+/* Offset between SQ bits */
+
+#define ADC_SQ_OFFSET (5)
+
+/* ADC injected sequence register */
+
+#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */
+#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT)
+#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in injected sequence */
+#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT)
+#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in injected sequence */
+#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT)
+#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19-15: 4th conversion in injected sequence */
+#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT)
+#define ADC_JSQR_JL_SHIFT (20) /* Bits 21-20: Injected Sequence length */
+#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT)
+
+/* ADC injected data register 1-4 */
+
+#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */
+#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT)
+
+/* ADC regular data register */
+
+#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */
+#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT)
+
+/* Common status register */
+
+#define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */
+#define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */
+#define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */
+#define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */
+#define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */
+#define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */
+
+#define ADC_CSR_AWD2 (1 << 8) /* Bit 8: Analog watchdog flag of ADC2 (copy of AWD in ADC2_SR) */
+#define ADC_CSR_EOC2 (1 << 9) /* Bit 9: End of conversion of ADC2 (copy of EOC in ADC2_SR) */
+#define ADC_CSR_JEOC2 (1 << 10) /* Bit 10: Injected channel end of conversion of ADC2 (copy of JEOC in ADC2_SR) */
+#define ADC_CSR_JSTRT2 (1 << 11) /* Bit 11: Injected channel Start flag of ADC2 (copy of JSTRT in ADC2_SR) */
+#define ADC_CSR_STRT2 (1 << 12) /* Bit 12: Regular channel Start flag of ADC2 (copy of STRT in ADC2_SR) */
+#define ADC_CSR_OVR2 (1 << 13) /* Bit 13: Overrun flag of ADC2 (copy of OVR in ADC2_SR) */
+# /* Bits 14-15: Reserved, must be kept at reset value. */
+#define ADC_CSR_AWD3 (1 << 16) /* Bit 16: ADC3 Analog watchdog flag (copy of AWD in ADC3_SR) */
+#define ADC_CSR_EOC3 (1 << 17) /* Bit 17: ADC3 End of conversion (copy of EOC in ADC3_SR) */
+#define ADC_CSR_JEOC3 (1 << 18) /* Bit 18: ADC3 Injected channel end of conversion (copy of JEOC in ADC3_SR) */
+#define ADC_CSR_JSTRT3 (1 << 19) /* Bit 19: ADC3 Injected channel Start flag (copy of JSTRT in ADC3_SR) */
+#define ADC_CSR_STRT3 (1 << 20) /* Bit 20: ADC3 Regular channel Start flag (copy of STRT in ADC3_SR). */
+#define ADC_CSR_OVR3 (1 << 21) /* Bit 21: ADC3 overrun flag (copy of OVR in ADC3_SR). */
+
+/* Common control register */
+
+# define ADC_CCR_MULTI_SHIFT (0) /* Bits 0-4: Multi ADC mode selection */
+# define ADC_CCR_MULTI_MASK (31 << ADC_CCR_MULTI_SHIFT)
+# define ADC_CCR_MULTI_NONE (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */
+ /* 00001 to 01001: Dual mode (ADC1 and ADC2), ADC3 independent */
+# define ADC_CCR_MULTI_RSISM2 (1 << ADC_CCR_MULTI_SHIFT) /* 00001: Combined regular simultaneous + injected simultaneous mode */
+# define ADC_CCR_MULTI_RSATM2 (2 << ADC_CCR_MULTI_SHIFT) /* 00010: Combined regular simultaneous + alternate trigger mode */
+# define ADC_CCR_MULTI_ISM2 (5 << ADC_CCR_MULTI_SHIFT) /* 00101: Injected simultaneous mode only */
+# define ADC_CCR_MULTI_RSM2 (6 << ADC_CCR_MULTI_SHIFT) /* 00110: Regular simultaneous mode only */
+# define ADC_CCR_MULTI_IM2 (7 << ADC_CCR_MULTI_SHIFT) /* 00111: interleaved mode only */
+# define ADC_CCR_MULTI_ATM2 (9 << ADC_CCR_MULTI_SHIFT) /* 01001: Alternate trigger mode only */
+ /* 10001 to 11001: Triple mode (ADC1, 2 and 3) */
+# define ADC_CCR_MULTI_RSISM3 (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */
+# define ADC_CCR_MULTI_RSATM3 (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */
+# define ADC_CCR_MULTI_ISM3 (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */
+# define ADC_CCR_MULTI_RSM3 (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */
+# define ADC_CCR_MULTI_IM3 (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */
+# define ADC_CCR_MULTI_ATM3 (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */
+ /* Bits 5-7: Reserved, must be kept at reset value. */
+# define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */
+# define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT)
+# define ADC_CCR_DELAY(n) (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */
+ /* Bit 12 Reserved, must be kept at reset value. */
+# define ADC_CCR_DDS (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */
+
+# define ADC_CCR_DMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for multi ADC mode */
+# define ADC_CCR_DMA_MASK (3 << ADC_CCR_DMA_SHIFT)
+# define ADC_CCR_DMA_DISABLED (0 << ADC_CCR_DMA_SHIFT) /* 00: DMA mode disabled */
+# define ADC_CCR_DMA_MODE1 (1 << ADC_CCR_DMA_SHIFT) /* 01: DMA mode 1 enabled */
+# define ADC_CCR_DMA_MODE2 (2 << ADC_CCR_DMA_SHIFT) /* 10: DMA mode 2 enabled */
+# define ADC_CCR_DMA_MODE3 (3 << ADC_CCR_DMA_SHIFT) /* 11: DMA mode 3 enabled */
+
+# define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-17: ADC prescaler */
+# define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT)
+# define ADC_CCR_ADCPRE_DIV2 (0 << ADC_CCR_ADCPRE_SHIFT) /* 00: PCLK2 divided by 2 */
+# define ADC_CCR_ADCPRE_DIV4 (1 << ADC_CCR_ADCPRE_SHIFT) /* 01: PCLK2 divided by 4 */
+# define ADC_CCR_ADCPRE_DIV6 (2 << ADC_CCR_ADCPRE_SHIFT) /* 10: PCLK2 divided by 6 */
+# define ADC_CCR_ADCPRE_DIV8 (3 << ADC_CCR_ADCPRE_SHIFT) /* 11: PCLK2 divided by 8 */
+ /* Bits 18-21: Reserved, must be kept at reset value. */
+# define ADC_CCR_VBATE (1 << 22) /* Bit 22: VBAT enable */
+# define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */
+ /* Bits 24-31 Reserved, must be kept at reset value. */
+
+/* Data register for dual and triple modes (32-bit data with no named fields) */
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32F_CHIP_STM32_ADC_H */
diff --git a/arch/arm/src/stm32f7/stm32_adc.c b/arch/arm/src/stm32f7/stm32_adc.c
new file mode 100644
index 0000000000..99d48238c5
--- /dev/null
+++ b/arch/arm/src/stm32f7/stm32_adc.c
@@ -0,0 +1,1700 @@
+/****************************************************************************
+ * arch/arm/src/stm32f7/stm32_adc.c
+ *
+ * Copyright (C) 2011, 2013, 2015-2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved.
+ * Authors: Gregory Nutt
+ * Diego Sanchez
+ * Paul Alexander Patience
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "stm32_dma.h"
+#include "stm32_adc.h"
+
+/* ADC "upper half" support must be enabled */
+
+#ifdef CONFIG_ADC
+
+/* Some ADC peripheral must be enabled */
+
+#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || \
+ defined(CONFIG_STM32F7_ADC3)
+
+/* This implementation is for the STM32 F7 only */
+
+#if defined(CONFIG_STM32F7_STM32F74XX)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* RCC reset ****************************************************************/
+
+#define STM32_RCC_RSTR STM32_RCC_APB2RSTR
+#define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADCRST
+#define RCC_RSTR_ADC2RST RCC_APB2RSTR_ADCRST
+#define RCC_RSTR_ADC3RST RCC_APB2RSTR_ADCRST
+
+/* ADC interrupts ***********************************************************/
+
+#define STM32_ADC_DMAREG_OFFSET STM32_ADC_CR2_OFFSET
+#define ADC_DMAREG_DMA ADC_CR2_DMA
+#define STM32_ADC_EXTREG_OFFSET STM32_ADC_CR2_OFFSET
+#define ADC_EXTREG_EXTSEL_MASK ADC_CR2_EXTSEL_MASK
+#define STM32_ADC_ISR_OFFSET STM32_ADC_SR_OFFSET
+#define STM32_ADC_IER_OFFSET STM32_ADC_CR1_OFFSET
+#define ADC_ISR_EOC ADC_SR_EOC
+#define ADC_IER_EOC ADC_CR1_EOCIE
+#define ADC_ISR_AWD ADC_SR_AWD
+#define ADC_IER_AWD ADC_CR1_AWDIE
+#define ADC_ISR_JEOC ADC_SR_JEOC
+#define ADC_IER_JEOC ADC_CR1_JEOCIE
+#define ADC_EXTREG_EXTEN_MASK ADC_CR2_EXTEN_MASK
+#define ADC_EXTREG_EXTEN_NONE ADC_CR2_EXTEN_NONE
+#define ADC_EXTREG_EXTEN_DEFAULT ADC_CR2_EXTEN_RISING
+#define ADC_ISR_OVR ADC_SR_OVR
+#define ADC_IER_OVR ADC_CR1_OVRIE
+
+#define ADC_ISR_ALLINTS (ADC_ISR_EOC | ADC_ISR_AWD | ADC_ISR_JEOC | \
+ ADC_ISR_OVR)
+#define ADC_IER_ALLINTS (ADC_IER_EOC | ADC_IER_AWD | ADC_IER_JEOC | \
+ ADC_IER_OVR)
+
+/* ADC Channels/DMA ********************************************************/
+/* The maximum number of channels that can be sampled. If DMA support is
+ * not enabled, then only a single channel can be sampled. Otherwise,
+ * data overruns would occur.
+ */
+
+#define ADC_MAX_CHANNELS_DMA 16
+#define ADC_MAX_CHANNELS_NODMA 1
+
+#ifdef ADC_HAVE_DMA
+# define ADC_MAX_SAMPLES ADC_MAX_CHANNELS_DMA
+#else
+# define ADC_MAX_SAMPLES ADC_MAX_CHANNELS_NODMA
+#endif
+
+#define ADC_DMA_CONTROL_WORD (DMA_SCR_MSIZE_16BITS | \
+ DMA_SCR_PSIZE_16BITS | \
+ DMA_SCR_MINC | \
+ DMA_SCR_CIRC | \
+ DMA_SCR_DIR_P2M)
+
+/* DMA channels and interface values */
+
+#define ADC_SMPR_DEFAULT ADC_SMPR_112
+#define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP10_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP11_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP12_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP13_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP14_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP15_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP16_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP17_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP18_SHIFT))
+#define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP0_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP1_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP2_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP3_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP4_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP5_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP6_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP7_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT))
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure describes the state of one ADC block */
+
+struct stm32_dev_s
+{
+ uint8_t irq; /* Interrupt generated by this ADC block */
+ uint8_t nchannels; /* Number of channels */
+ uint8_t cchannels; /* Number of configured channels */
+ uint8_t intf; /* ADC interface number */
+ uint8_t current; /* Current ADC channel being converted */
+#ifdef ADC_HAVE_DMA
+ uint8_t dmachan; /* DMA channel needed by this ADC */
+ bool hasdma; /* True: This channel supports DMA */
+#endif
+#ifdef ADC_HAVE_TIMER
+ uint8_t trigger; /* Timer trigger channel: 0=CC1, 1=CC2, 2=CC3,
+ * 3=CC4, 4=TRGO */
+#endif
+ xcpt_t isr; /* Interrupt handler for this ADC block */
+ uint32_t base; /* Base address of registers unique to this ADC
+ * block */
+#ifdef ADC_HAVE_TIMER
+ uint32_t tbase; /* Base address of timer used by this ADC block */
+ uint32_t extsel; /* EXTSEL value used by this ADC block */
+ uint32_t pclck; /* The PCLK frequency that drives this timer */
+ uint32_t freq; /* The desired frequency of conversions */
+#endif
+#ifdef ADC_HAVE_DMA
+ DMA_HANDLE dma; /* Allocated DMA channel */
+
+ /* DMA transfer buffer */
+
+ uint16_t dmabuffer[ADC_MAX_SAMPLES];
+#endif
+
+ /* List of selected ADC channels to sample */
+
+ uint8_t chanlist[ADC_MAX_SAMPLES];
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* ADC Register access */
+
+static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
+ uint32_t setbits);
+static uint32_t adc_getreg(FAR struct stm32_dev_s *priv, int offset);
+static void adc_putreg(FAR struct stm32_dev_s *priv, int offset,
+ uint32_t value);
+static void adc_modifyreg(FAR struct stm32_dev_s *priv, int offset,
+ uint32_t clrbits, uint32_t setbits);
+#ifdef ADC_HAVE_TIMER
+static uint16_t tim_getreg(FAR struct stm32_dev_s *priv, int offset);
+static void tim_putreg(FAR struct stm32_dev_s *priv, int offset,
+ uint16_t value);
+static void tim_modifyreg(FAR struct stm32_dev_s *priv, int offset,
+ uint16_t clrbits, uint16_t setbits);
+static void tim_dumpregs(FAR struct stm32_dev_s *priv,
+ FAR const char *msg);
+#endif
+
+static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset);
+
+/* ADC Interrupt Handler */
+static int adc_interrupt(FAR struct adc_dev_s *dev);
+static int adc123_interrupt(int irq, FAR void *context);
+
+/* ADC Driver Methods */
+
+static void adc_reset(FAR struct adc_dev_s *dev);
+static int adc_setup(FAR struct adc_dev_s *dev);
+static void adc_shutdown(FAR struct adc_dev_s *dev);
+static void adc_rxint(FAR struct adc_dev_s *dev, bool enable);
+static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg);
+static void adc_enable(FAR struct stm32_dev_s *priv, bool enable);
+
+static uint32_t adc_sqrbits(FAR struct stm32_dev_s *priv, int first, int last,
+ int offset);
+static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch);
+
+#ifdef ADC_HAVE_TIMER
+static void adc_timstart(FAR struct stm32_dev_s *priv, bool enable);
+static int adc_timinit(FAR struct stm32_dev_s *priv);
+#endif
+
+#ifdef ADC_HAVE_DMA
+static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr,
+ FAR void *arg);
+#endif
+
+static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* ADC interface operations */
+
+static const struct adc_ops_s g_adcops =
+{
+ .ao_reset = adc_reset,
+ .ao_setup = adc_setup,
+ .ao_shutdown = adc_shutdown,
+ .ao_rxint = adc_rxint,
+ .ao_ioctl = adc_ioctl,
+};
+
+/* ADC1 state */
+
+#ifdef CONFIG_STM32F7_ADC1
+static struct stm32_dev_s g_adcpriv1 =
+{
+ .irq = STM32_IRQ_ADC,
+ .isr = adc123_interrupt,
+ .intf = 1,
+ .base = STM32_ADC1_BASE,
+#ifdef ADC1_HAVE_TIMER
+ .trigger = CONFIG_STM32F7_ADC1_TIMTRIG,
+ .tbase = ADC1_TIMER_BASE,
+ .extsel = ADC1_EXTSEL_VALUE,
+ .pclck = ADC1_TIMER_PCLK_FREQUENCY,
+ .freq = CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY,
+#endif
+#ifdef ADC1_HAVE_DMA
+ .dmachan = ADC1_DMA_CHAN,
+ .hasdma = true,
+#endif
+};
+
+static struct adc_dev_s g_adcdev1 =
+{
+ .ad_ops = &g_adcops,
+ .ad_priv = &g_adcpriv1,
+};
+#endif
+
+/* ADC2 state */
+
+#ifdef CONFIG_STM32F7_ADC2
+static struct stm32_dev_s g_adcpriv2 =
+{
+ .irq = STM32_IRQ_ADC,
+ .isr = adc123_interrupt,
+ .intf = 2,
+ .base = STM32_ADC2_BASE,
+#ifdef ADC2_HAVE_TIMER
+ .trigger = CONFIG_STM32F7_ADC2_TIMTRIG,
+ .tbase = ADC2_TIMER_BASE,
+ .extsel = ADC2_EXTSEL_VALUE,
+ .pclck = ADC2_TIMER_PCLK_FREQUENCY,
+ .freq = CONFIG_STM32F7_ADC2_SAMPLE_FREQUENCY,
+#endif
+#ifdef ADC2_HAVE_DMA
+ .dmachan = ADC2_DMA_CHAN,
+ .hasdma = true,
+#endif
+};
+
+static struct adc_dev_s g_adcdev2 =
+{
+ .ad_ops = &g_adcops,
+ .ad_priv = &g_adcpriv2,
+};
+#endif
+
+/* ADC3 state */
+
+#ifdef CONFIG_STM32F7_ADC3
+static struct stm32_dev_s g_adcpriv3 =
+{
+ .irq = STM32_IRQ_ADC,
+ .isr = adc123_interrupt,
+ .intf = 3,
+ .base = STM32_ADC3_BASE,
+#ifdef ADC3_HAVE_TIMER
+ .trigger = CONFIG_STM32F7_ADC3_TIMTRIG,
+ .tbase = ADC3_TIMER_BASE,
+ .extsel = ADC3_EXTSEL_VALUE,
+ .pclck = ADC3_TIMER_PCLK_FREQUENCY,
+ .freq = CONFIG_STM32F7_ADC3_SAMPLE_FREQUENCY,
+#endif
+#ifdef ADC3_HAVE_DMA
+ .dmachan = ADC3_DMA_CHAN,
+ .hasdma = true,
+#endif
+};
+
+static struct adc_dev_s g_adcdev3 =
+{
+ .ad_ops = &g_adcops,
+ .ad_priv = &g_adcpriv3,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_modifyreg32
+ *
+ * Description:
+ * Modify the value of a 32-bit register (not atomic).
+ *
+ * Input Parameters:
+ * addr - The address of the register
+ * clrbits - The bits to clear
+ * setbits - The bits to set
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
+ uint32_t setbits)
+{
+ putreg32((getreg32(addr) & ~clrbits) | setbits, addr);
+}
+
+/****************************************************************************
+ * Name: adc_getreg
+ *
+ * Description:
+ * Read the value of an ADC register.
+ *
+ * Input Parameters:
+ * priv - A reference to the ADC block status
+ * offset - The offset to the register to read
+ *
+ * Returned Value:
+ * The current contents of the specified register
+ *
+ ****************************************************************************/
+
+static uint32_t adc_getreg(FAR struct stm32_dev_s *priv, int offset)
+{
+ return getreg32(priv->base + offset);
+}
+
+/****************************************************************************
+ * Name: adc_putreg
+ *
+ * Description:
+ * Write a value to an ADC register.
+ *
+ * Input Parameters:
+ * priv - A reference to the ADC block status
+ * offset - The offset to the register to write to
+ * value - The value to write to the register
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void adc_putreg(FAR struct stm32_dev_s *priv, int offset,
+ uint32_t value)
+{
+ putreg32(value, priv->base + offset);
+}
+
+/****************************************************************************
+ * Name: adc_modifyreg
+ *
+ * Description:
+ * Modify the value of an ADC register (not atomic).
+ *
+ * Input Parameters:
+ * priv - A reference to the ADC block status
+ * offset - The offset to the register to modify
+ * clrbits - The bits to clear
+ * setbits - The bits to set
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void adc_modifyreg(FAR struct stm32_dev_s *priv, int offset,
+ uint32_t clrbits, uint32_t setbits)
+{
+ adc_putreg(priv, offset, (adc_getreg(priv, offset) & ~clrbits) | setbits);
+}
+
+/****************************************************************************
+ * Name: tim_getreg
+ *
+ * Description:
+ * Read the value of an ADC timer register.
+ *
+ * Input Parameters:
+ * priv - A reference to the ADC block status
+ * offset - The offset to the register to read
+ *
+ * Returned Value:
+ * The current contents of the specified register
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static uint16_t tim_getreg(FAR struct stm32_dev_s *priv, int offset)
+{
+ return getreg16(priv->tbase + offset);
+}
+#endif
+
+/****************************************************************************
+ * Name: tim_putreg
+ *
+ * Description:
+ * Write a value to an ADC timer register.
+ *
+ * Input Parameters:
+ * priv - A reference to the ADC block status
+ * offset - The offset to the register to write to
+ * value - The value to write to the register
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static void tim_putreg(FAR struct stm32_dev_s *priv, int offset,
+ uint16_t value)
+{
+ putreg16(value, priv->tbase + offset);
+}
+#endif
+
+/****************************************************************************
+ * Name: tim_modifyreg
+ *
+ * Description:
+ * Modify the value of an ADC timer register (not atomic).
+ *
+ * Input Parameters:
+ * priv - A reference to the ADC block status
+ * offset - The offset to the register to modify
+ * clrbits - The bits to clear
+ * setbits - The bits to set
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static void tim_modifyreg(FAR struct stm32_dev_s *priv, int offset,
+ uint16_t clrbits, uint16_t setbits)
+{
+ tim_putreg(priv, offset, (tim_getreg(priv, offset) & ~clrbits) | setbits);
+}
+#endif
+
+/****************************************************************************
+ * Name: tim_dumpregs
+ *
+ * Description:
+ * Dump all timer registers.
+ *
+ * Input parameters:
+ * priv - A reference to the ADC block status
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static void tim_dumpregs(FAR struct stm32_dev_s *priv, FAR const char *msg)
+{
+ avdbg("%s:\n", msg);
+ avdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
+ tim_getreg(priv, STM32_GTIM_CR1_OFFSET),
+ tim_getreg(priv, STM32_GTIM_CR2_OFFSET),
+ tim_getreg(priv, STM32_GTIM_SMCR_OFFSET),
+ tim_getreg(priv, STM32_GTIM_DIER_OFFSET));
+ avdbg(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n",
+ tim_getreg(priv, STM32_GTIM_SR_OFFSET),
+ tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET),
+ tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET));
+ avdbg(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
+ tim_getreg(priv, STM32_GTIM_CCER_OFFSET),
+ tim_getreg(priv, STM32_GTIM_CNT_OFFSET),
+ tim_getreg(priv, STM32_GTIM_PSC_OFFSET),
+ tim_getreg(priv, STM32_GTIM_ARR_OFFSET));
+ avdbg(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
+ tim_getreg(priv, STM32_GTIM_CCR1_OFFSET),
+ tim_getreg(priv, STM32_GTIM_CCR2_OFFSET),
+ tim_getreg(priv, STM32_GTIM_CCR3_OFFSET),
+ tim_getreg(priv, STM32_GTIM_CCR4_OFFSET));
+ if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
+ {
+ avdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
+ tim_getreg(priv, STM32_ATIM_RCR_OFFSET),
+ tim_getreg(priv, STM32_ATIM_BDTR_OFFSET),
+ tim_getreg(priv, STM32_ATIM_DCR_OFFSET),
+ tim_getreg(priv, STM32_ATIM_DMAR_OFFSET));
+ }
+ else
+ {
+ avdbg(" DCR: %04x DMAR: %04x\n",
+ tim_getreg(priv, STM32_GTIM_DCR_OFFSET),
+ tim_getreg(priv, STM32_GTIM_DMAR_OFFSET));
+ }
+}
+#endif
+
+/****************************************************************************
+ * Name: adc_timstart
+ *
+ * Description:
+ * Start (or stop) the timer counter
+ *
+ * Input Parameters:
+ * priv - A reference to the ADC block status
+ * enable - True: Start conversion
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static void adc_timstart(FAR struct stm32_dev_s *priv, bool enable)
+{
+ avdbg("enable: %d\n", enable ? 1 : 0);
+
+ if (enable)
+ {
+ /* Start the counter */
+
+ tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN);
+ }
+ else
+ {
+ /* Disable the counter */
+
+ tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0);
+ }
+}
+#endif
+
+/****************************************************************************
+ * Name: adc_timinit
+ *
+ * Description:
+ * Initialize the timer that drivers the ADC sampling for this channel
+ * using the pre-calculated timer divider definitions.
+ *
+ * Input Parameters:
+ * priv - A reference to the ADC block status
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static int adc_timinit(FAR struct stm32_dev_s *priv)
+{
+ uint32_t prescaler;
+ uint32_t reload;
+ uint32_t timclk;
+
+ uint16_t clrbits = 0;
+ uint16_t setbits = 0;
+ uint16_t cr2;
+ uint16_t ccmr1;
+ uint16_t ccmr2;
+ uint16_t ocmode1;
+ uint16_t ocmode2;
+ uint16_t ccenable;
+ uint16_t ccer;
+ uint16_t egr;
+
+ /* If the timer base address is zero, then this ADC was not configured to
+ * use a timer.
+ */
+
+ if (priv->tbase == 0)
+ {
+ return ERROR;
+ }
+
+ /* EXTSEL selection: These bits select the external event used to trigger
+ * the start of conversion of a regular group. NOTE:
+ *
+ * - The position with of the EXTSEL field varies from one STM32 MCU
+ * to another.
+ * - The width of the EXTSEL field varies from one STM32 MCU to another.
+ * - The value in priv->extsel is already shifted into the correct bit
+ * position.
+ */
+
+ avdbg("Initializing timers extsel = 0x%08x\n", priv->extsel);
+
+ adc_modifyreg(priv, STM32_ADC_EXTREG_OFFSET,
+ ADC_EXTREG_EXTEN_MASK | ADC_EXTREG_EXTSEL_MASK,
+ ADC_EXTREG_EXTEN_DEFAULT | priv->extsel);
+
+ /* Configure the timer channel to drive the ADC */
+
+ /* Caculate optimal values for the timer prescaler and for the timer
+ * reload register. If freq is the desired frequency, then
+ *
+ * reload = timclk / freq
+ * reload = (pclck / prescaler) / freq
+ *
+ * There are many solutions to do this, but the best solution will be the
+ * one that has the largest reload value and the smallest prescaler value.
+ * That is the solution that should give us the most accuracy in the timer
+ * control. Subject to:
+ *
+ * 0 <= prescaler <= 65536
+ * 1 <= reload <= 65535
+ *
+ * So ( prescaler = pclck / 65535 / freq ) would be optimal.
+ */
+
+ prescaler = (priv->pclck / priv->freq + 65534) / 65535;
+
+ /* We need to decrement the prescaler value by one, but only, the value
+ * does not underflow.
+ */
+
+ if (prescaler < 1)
+ {
+ adbg("WARNING: Prescaler underflowed.\n");
+ prescaler = 1;
+ }
+
+ /* Check for overflow */
+
+ else if (prescaler > 65536)
+ {
+ adbg("WARNING: Prescaler overflowed.\n");
+ prescaler = 65536;
+ }
+
+ timclk = priv->pclck / prescaler;
+
+ reload = timclk / priv->freq;
+ if (reload < 1)
+ {
+ adbg("WARNING: Reload value underflowed.\n");
+ reload = 1;
+ }
+ else if (reload > 65535)
+ {
+ adbg("WARNING: Reload value overflowed.\n");
+ reload = 65535;
+ }
+
+ /* Disable the timer until we get it configured */
+
+ adc_timstart(priv, false);
+
+ /* Set up the timer CR1 register.
+ *
+ * Select the Counter Mode == count up:
+ *
+ * ATIM_CR1_EDGE: The counter counts up or down depending on the
+ * direction bit(DIR).
+ * ATIM_CR1_DIR: 0: count up, 1: count down
+ *
+ * Set the clock division to zero for all
+ */
+
+ clrbits = GTIM_CR1_DIR | GTIM_CR1_CMS_MASK | GTIM_CR1_CKD_MASK;
+ setbits = GTIM_CR1_EDGE;
+ tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, clrbits, setbits);
+
+ /* Set the reload and prescaler values */
+
+ tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler-1);
+ tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload);
+
+ /* Clear the advanced timers repetition counter in TIM1 */
+
+ if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
+ {
+ tim_putreg(priv, STM32_ATIM_RCR_OFFSET, 0);
+ tim_putreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */
+ }
+
+ /* TIMx event generation: Bit 0 UG: Update generation */
+
+ tim_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG);
+
+ /* Handle channel specific setup */
+
+ ocmode1 = 0;
+ ocmode2 = 0;
+
+ switch (priv->trigger)
+ {
+ case 0: /* TimerX CC1 event */
+ {
+ ccenable = ATIM_CCER_CC1E;
+ ocmode1 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) |
+ (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) |
+ ATIM_CCMR1_OC1PE;
+
+ /* Set the event CC1 */
+
+ egr = ATIM_EGR_CC1G;
+
+ /* Set the duty cycle by writing to the CCR register for this
+ * channel
+ */
+
+ tim_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)(reload >> 1));
+ }
+ break;
+
+ case 1: /* TimerX CC2 event */
+ {
+ ccenable = ATIM_CCER_CC2E;
+ ocmode1 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT) |
+ (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) |
+ ATIM_CCMR1_OC2PE;
+
+ /* Set the event CC2 */
+
+ egr = ATIM_EGR_CC2G;
+
+ /* Set the duty cycle by writing to the CCR register for this
+ * channel
+ */
+
+ tim_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)(reload >> 1));
+ }
+ break;
+
+ case 2: /* TimerX CC3 event */
+ {
+ ccenable = ATIM_CCER_CC3E;
+ ocmode2 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) |
+ (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) |
+ ATIM_CCMR2_OC3PE;
+
+ /* Set the event CC3 */
+
+ egr = ATIM_EGR_CC3G;
+
+ /* Set the duty cycle by writing to the CCR register for this
+ * channel
+ */
+
+ tim_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)(reload >> 1));
+ }
+ break;
+
+ case 3: /* TimerX CC4 event */
+ {
+ ccenable = ATIM_CCER_CC4E;
+ ocmode2 = (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT) |
+ (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC4M_SHIFT) |
+ ATIM_CCMR2_OC4PE;
+
+ /* Set the event CC4 */
+
+ egr = ATIM_EGR_CC4G;
+
+ /* Set the duty cycle by writing to the CCR register for this
+ * channel
+ */
+
+ tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1));
+ }
+ break;
+
+ case 4: /* TimerX TRGO event */
+ {
+ /* TODO: TRGO support not yet implemented */
+ /* Set the event TRGO */
+
+ ccenable = 0;
+ egr = GTIM_EGR_TG;
+
+ /* Set the duty cycle by writing to the CCR register for this
+ * channel
+ */
+
+ tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1));
+ }
+ break;
+
+ default:
+ adbg("No such trigger: %d\n", priv->trigger);
+ return -EINVAL;
+ }
+
+ /* Disable the Channel by resetting the CCxE Bit in the CCER register */
+
+ ccer = tim_getreg(priv, STM32_GTIM_CCER_OFFSET);
+ ccer &= ~ccenable;
+ tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer);
+
+ /* Fetch the CR2, CCMR1, and CCMR2 register (already have ccer) */
+
+ cr2 = tim_getreg(priv, STM32_GTIM_CR2_OFFSET);
+ ccmr1 = tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET);
+ ccmr2 = tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET);
+
+ /* Reset the Output Compare Mode Bits and set the select output compare
+ * mode
+ */
+
+ ccmr1 &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | ATIM_CCMR1_OC1PE |
+ ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | ATIM_CCMR1_OC2PE);
+ ccmr2 &= ~(ATIM_CCMR2_CC3S_MASK | ATIM_CCMR2_OC3M_MASK | ATIM_CCMR2_OC3PE |
+ ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | ATIM_CCMR2_OC4PE);
+ ccmr1 |= ocmode1;
+ ccmr2 |= ocmode2;
+
+ /* Reset the output polarity level of all channels (selects high
+ * polarity)
+ */
+
+ ccer &= ~(ATIM_CCER_CC1P | ATIM_CCER_CC2P |
+ ATIM_CCER_CC3P | ATIM_CCER_CC4P);
+
+ /* Enable the output state of the selected channel (only) */
+
+ ccer &= ~(ATIM_CCER_CC1E | ATIM_CCER_CC2E |
+ ATIM_CCER_CC3E | ATIM_CCER_CC4E);
+ ccer |= ccenable;
+
+ if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
+ {
+ /* Reset output N polarity level, output N state, output compare state,
+ * output compare N idle state.
+ */
+
+ ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP |
+ ATIM_CCER_CC2NE | ATIM_CCER_CC2NP |
+ ATIM_CCER_CC3NE | ATIM_CCER_CC3NP |
+ ATIM_CCER_CC4NP);
+
+ /* Reset the output compare and output compare N IDLE State */
+
+ cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N |
+ ATIM_CR2_OIS2 | ATIM_CR2_OIS2N |
+ ATIM_CR2_OIS3 | ATIM_CR2_OIS3N |
+ ATIM_CR2_OIS4);
+ }
+ else
+ {
+ ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP);
+ }
+
+ /* Save the modified register values */
+
+ tim_putreg(priv, STM32_GTIM_CR2_OFFSET, cr2);
+ tim_putreg(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1);
+ tim_putreg(priv, STM32_GTIM_CCMR2_OFFSET, ccmr2);
+ tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer);
+ tim_putreg(priv, STM32_GTIM_EGR_OFFSET, egr);
+
+ /* Set the ARR Preload Bit */
+
+ tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE);
+
+ /* Enable the timer counter */
+
+ adc_timstart(priv, true);
+
+ tim_dumpregs(priv, "After starting timers");
+
+ return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: adc_startconv
+ *
+ * Description:
+ * Start (or stop) the ADC conversion process
+ *
+ * Input Parameters:
+ * priv - A reference to the ADC block status
+ * enable - True: Start conversion
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable)
+{
+ avdbg("enable: %d\n", enable ? 1 : 0);
+
+ if (enable)
+ {
+ /* Start the conversion of regular channels */
+
+ adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_SWSTART);
+ }
+ else
+ {
+ /* Stop the conversion */
+
+ adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_SWSTART, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: adc_rccreset
+ *
+ * Description:
+ * Deinitializes the ADCx peripheral registers to their default
+ * reset values. It could set all the ADCs configured.
+ *
+ * Input Parameters:
+ * regaddr - The register to read
+ * reset - Condition, set or reset
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset)
+{
+ uint32_t adcbit;
+
+ /* Pick the appropriate bit in the APB2 reset register.
+ * For the STM32 F1, there is an individual bit to reset each ADC,
+ * but for the STM32 F2/F4, there is one common reset for all ADCs.
+ * THIS will probably cause some problems!
+ */
+
+ switch (priv->intf)
+ {
+#ifdef CONFIG_STM32F7_ADC1
+ case 1:
+ adcbit = RCC_RSTR_ADC1RST;
+ break;
+#endif
+#ifdef CONFIG_STM32F7_ADC2
+ case 2:
+ adcbit = RCC_RSTR_ADC2RST;
+ break;
+#endif
+#ifdef CONFIG_STM32F7_ADC3
+ case 3:
+ adcbit = RCC_RSTR_ADC3RST;
+ break;
+#endif
+ default:
+ return;
+ }
+
+ /* Set or clear the selected bit in the APB2 reset register.
+ * modifyreg32() disables interrupts. Disabling interrupts is necessary
+ * because the APB2RTSR register is used by several different drivers.
+ */
+
+ if (reset)
+ {
+ /* Enable ADC reset state */
+
+ modifyreg32(STM32_RCC_RSTR, 0, adcbit);
+ }
+ else
+ {
+ /* Release ADC from reset state */
+
+ modifyreg32(STM32_RCC_RSTR, adcbit, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: adc_enable
+ *
+ * Description : Enables or disables the specified ADC peripheral.
+ * Also, starts a conversion when the ADC is not
+ * triggered by timers
+ *
+ * Input Parameters:
+ *
+ * enable - true: enable ADC conversion
+ * false: disable ADC conversion
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static void adc_enable(FAR struct stm32_dev_s *priv, bool enable)
+{
+#ifdef ADC_SR_ADONS
+ bool enabled = (adc_getreg(priv, STM32_ADC_SR_OFFSET) & ADC_SR_ADONS) != 0;
+#else
+ bool enabled = false;
+#endif
+
+ avdbg("enable: %d\n", enable ? 1 : 0);
+
+ if (!enabled && enable)
+ {
+ adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_ADON);
+ }
+ else if (enabled && !enable)
+ {
+ adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_ADON, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: adc_dmacovcallback
+ *
+ * Description:
+ * Callback for DMA. Called from the DMA transfer complete interrupt after
+ * all channels have been converted and transferred with DMA.
+ *
+ * Input Parameters:
+ *
+ * handle - handle to DMA
+ * isr -
+ * arg - adc device
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_DMA
+static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg)
+{
+ FAR struct adc_dev_s *dev = (FAR struct adc_dev_s *)arg;
+ FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+ int i;
+
+ for (i = 0; i < priv->nchannels; i++)
+ {
+ adc_receive(dev, priv->current, priv->dmabuffer[priv->current]);
+ priv->current++;
+ if (priv->current >= priv->nchannels)
+ {
+ /* Restart the conversion sequence from the beginning */
+
+ priv->current = 0;
+ }
+ }
+
+ /* Restart DMA for the next conversion series */
+
+ adc_modifyreg(priv, STM32_ADC_DMAREG_OFFSET, ADC_DMAREG_DMA, 0);
+ adc_modifyreg(priv, STM32_ADC_DMAREG_OFFSET, 0, ADC_DMAREG_DMA);
+}
+#endif
+
+/****************************************************************************
+ * Name: adc_reset
+ *
+ * Description:
+ * Reset the ADC device. Called early to initialize the hardware. This
+ * is called, before adc_setup() and on error conditions.
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static void adc_reset(FAR struct adc_dev_s *dev)
+{
+ FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+ irqstate_t flags;
+ uint32_t clrbits;
+ uint32_t setbits;
+#ifdef ADC_HAVE_TIMER
+ int ret;
+#endif
+
+ allvdbg("intf: %d\n", priv->intf);
+ flags = enter_critical_section();
+
+ /* Enable ADC reset state */
+
+ adc_rccreset(priv, true);
+
+ /* Release ADC from reset state */
+
+ adc_rccreset(priv, false);
+
+ /* Initialize the watchdog high threshold register */
+
+ adc_putreg(priv, STM32_ADC_HTR_OFFSET, 0x00000fff);
+
+ /* Initialize the watchdog low threshold register */
+
+ adc_putreg(priv, STM32_ADC_LTR_OFFSET, 0x00000000);
+
+ /* Initialize the same sample time for each ADC.
+ * During sample cycles channel selection bits must remain unchanged.
+ */
+
+ adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, ADC_SMPR1_DEFAULT);
+ adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT);
+
+ /* Enable the analog watchdog */
+
+ clrbits = ADC_CR1_AWDCH_MASK;
+ setbits = ADC_CR1_AWDEN | (priv->chanlist[0] << ADC_CR1_AWDCH_SHIFT);
+
+ /* Set the resolution of the conversion */
+
+ clrbits |= ADC_CR1_RES_MASK;
+ setbits |= ADC_CR1_RES_12BIT;
+
+#ifdef ADC_HAVE_DMA
+ if (priv->hasdma)
+ {
+ setbits |= ADC_CR1_SCAN;
+ }
+#endif
+
+ /* Enable interrupt flags, but disable overrun interrupt */
+
+ clrbits |= ADC_IER_OVR;
+ setbits |= ADC_IER_ALLINTS & ~ADC_IER_OVR;
+
+ /* Set CR1 configuration */
+
+ adc_modifyreg(priv, STM32_ADC_CR1_OFFSET, clrbits, setbits);
+
+ /* Disable continuous mode and set align to right */
+
+ clrbits = ADC_CR2_CONT | ADC_CR2_ALIGN;
+ setbits = 0;
+
+ /* Disable external trigger for regular channels */
+
+ clrbits |= ADC_EXTREG_EXTEN_MASK;
+ setbits |= ADC_EXTREG_EXTEN_NONE;
+
+#ifdef ADC_HAVE_DMA
+ if (priv->hasdma)
+ {
+ setbits |= ADC_CR2_DMA;
+ }
+#endif
+
+ /* Set CR2 configuration */
+
+ adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, clrbits, setbits);
+
+ /* Configuration of the channel conversions */
+
+ adc_set_ch(dev, 0);
+
+ /* ADC CCR configuration */
+
+ clrbits = ADC_CCR_ADCPRE_MASK | ADC_CCR_TSVREFE;
+ setbits = ADC_CCR_ADCPRE_DIV2;
+
+ clrbits |= ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS |
+ ADC_CCR_DMA_MASK | ADC_CCR_VBATE;
+ setbits |= ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED;
+
+ stm32_modifyreg32(STM32_ADC_CCR, clrbits, setbits);
+
+#ifdef ADC_HAVE_DMA
+
+ /* Enable DMA */
+
+ if (priv->hasdma)
+ {
+ /* Stop and free DMA if it was started before */
+
+ if (priv->dma != NULL)
+ {
+ stm32_dmastop(priv->dma);
+ stm32_dmafree(priv->dma);
+ }
+
+ priv->dma = stm32_dmachannel(priv->dmachan);
+
+ stm32_dmasetup(priv->dma,
+ priv->base + STM32_ADC_DR_OFFSET,
+ (uint32_t)priv->dmabuffer,
+ priv->nchannels,
+ ADC_DMA_CONTROL_WORD);
+
+ stm32_dmastart(priv->dma, adc_dmaconvcallback, dev, false);
+ }
+
+#endif
+
+ /* Set ADON to wake up the ADC from the power down state */
+
+ adc_enable(priv, true);
+
+#ifdef ADC_HAVE_TIMER
+ if (priv->tbase != 0)
+ {
+ ret = adc_timinit(priv);
+ if (ret < 0)
+ {
+ adbg("adc_timinit failed: %d\n", ret);
+ }
+ }
+#ifndef CONFIG_ADC_NO_STARTUP_CONV
+ else
+#endif
+#endif
+#ifndef CONFIG_ADC_NO_STARTUP_CONV
+ {
+ adc_startconv(priv, true);
+ }
+#endif
+
+ leave_critical_section(flags);
+
+ avdbg("SR: 0x%08x CR1: 0x%08x CR2: 0x%08x\n",
+ adc_getreg(priv, STM32_ADC_SR_OFFSET),
+ adc_getreg(priv, STM32_ADC_CR1_OFFSET),
+ adc_getreg(priv, STM32_ADC_CR2_OFFSET));
+
+ avdbg("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n",
+ adc_getreg(priv, STM32_ADC_SQR1_OFFSET),
+ adc_getreg(priv, STM32_ADC_SQR2_OFFSET),
+ adc_getreg(priv, STM32_ADC_SQR3_OFFSET));
+
+ avdbg("CCR: 0x%08x\n", getreg32(STM32_ADC_CCR));
+
+}
+
+/****************************************************************************
+ * Name: adc_setup
+ *
+ * Description:
+ * Configure the ADC. This method is called the first time that the ADC
+ * device is opened. This will occur when the port is first opened.
+ * This setup includes configuring and attaching ADC interrupts.
+ * Interrupts are all disabled upon return.
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static int adc_setup(FAR struct adc_dev_s *dev)
+{
+ FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+ int ret;
+
+ /* Attach the ADC interrupt */
+
+ ret = irq_attach(priv->irq, priv->isr);
+ if (ret < 0)
+ {
+ avdbg("irq_attach failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Make sure that the ADC device is in the powered up, reset state */
+
+ adc_reset(dev);
+
+ /* Enable the ADC interrupt */
+
+ avdbg("Enable the ADC interrupt: irq=%d\n", priv->irq);
+ up_enable_irq(priv->irq);
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: adc_shutdown
+ *
+ * Description:
+ * Disable the ADC. This method is called when the ADC device is closed.
+ * This method reverses the operation the setup method.
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static void adc_shutdown(FAR struct adc_dev_s *dev)
+{
+ FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+
+ adc_enable(priv, false);
+
+ /* Disable ADC interrupts and detach the ADC interrupt handler */
+
+ up_disable_irq(priv->irq);
+ irq_detach(priv->irq);
+
+ /* Disable and reset the ADC module */
+
+ adc_rccreset(priv, true);
+}
+
+/****************************************************************************
+ * Name: adc_rxint
+ *
+ * Description:
+ * Call to enable or disable RX interrupts.
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
+{
+ FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+
+ avdbg("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0);
+
+ if (enable)
+ {
+ /* Enable the end-of-conversion ADC and analog watchdog interrupts */
+
+ adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_ALLINTS);
+ }
+ else
+ {
+ /* Disable all ADC interrupts */
+
+ adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_ALLINTS, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: adc_sqrbits
+ ****************************************************************************/
+
+static uint32_t adc_sqrbits(FAR struct stm32_dev_s *priv, int first, int last,
+ int offset)
+{
+ uint32_t bits = 0;
+ int i;
+
+ for (i = first - 1;
+ i < priv->nchannels && i < last;
+ i++, offset += ADC_SQ_OFFSET)
+ {
+ bits |= (uint32_t)priv->chanlist[i] << offset;
+ }
+
+ return bits;
+}
+
+/****************************************************************************
+ * Name: adc_set_ch
+ *
+ * Description:
+ * Sets the ADC channel.
+ *
+ * Input Parameters:
+ * dev - pointer to device structure used by the driver
+ * ch - ADC channel number + 1. 0 reserved for all configured channels
+ *
+ * Returned Value:
+ * int - errno
+ *
+ ****************************************************************************/
+
+static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch)
+{
+ FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+ uint32_t bits;
+ int i;
+
+ if (ch == 0)
+ {
+ priv->current = 0;
+ priv->nchannels = priv->cchannels;
+ }
+ else
+ {
+ for (i = 0; i < priv->cchannels && priv->chanlist[i] != ch - 1; i++);
+
+ if (i >= priv->cchannels)
+ {
+ return -ENODEV;
+ }
+
+ priv->current = i;
+ priv->nchannels = 1;
+ }
+
+#ifdef STM32_ADC_SQR5_OFFSET
+ bits = adc_sqrbits(priv, ADC_SQR5_FIRST, ADC_SQR5_LAST, ADC_SQR5_SQ_OFFSET);
+ adc_modifyreg(priv, STM32_ADC_SQR5_OFFSET, ~ADC_SQR5_RESERVED, bits);
+#endif
+
+#ifdef STM32_ADC_SQR4_OFFSET
+ bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, ADC_SQR4_SQ_OFFSET);
+ adc_modifyreg(priv, STM32_ADC_SQR4_OFFSET, ~ADC_SQR4_RESERVED, bits);
+#endif
+
+ bits = adc_sqrbits(priv, ADC_SQR3_FIRST, ADC_SQR3_LAST, ADC_SQR3_SQ_OFFSET);
+ adc_modifyreg(priv, STM32_ADC_SQR3_OFFSET, ~ADC_SQR3_RESERVED, bits);
+
+ bits = adc_sqrbits(priv, ADC_SQR2_FIRST, ADC_SQR2_LAST, ADC_SQR2_SQ_OFFSET);
+ adc_modifyreg(priv, STM32_ADC_SQR2_OFFSET, ~ADC_SQR2_RESERVED, bits);
+
+ bits = ((uint32_t)priv->nchannels - 1) << ADC_SQR1_L_SHIFT |
+ adc_sqrbits(priv, ADC_SQR1_FIRST, ADC_SQR1_LAST, ADC_SQR1_SQ_OFFSET);
+ adc_modifyreg(priv, STM32_ADC_SQR1_OFFSET, ~ADC_SQR1_RESERVED, bits);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: adc_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method.
+ *
+ * Input Parameters:
+ * dev - pointer to device structure used by the driver
+ * cmd - command
+ * arg - arguments passed with command
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
+{
+ FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+ int ret = OK;
+
+ switch (cmd)
+ {
+ case ANIOC_TRIGGER:
+ adc_startconv(priv, true);
+ break;
+
+ default:
+ adbg("ERROR: Unknown cmd: %d\n", cmd);
+ ret = -ENOTTY;
+ break;
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: adc_interrupt
+ *
+ * Description:
+ * Common ADC interrupt handler.
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static int adc_interrupt(FAR struct adc_dev_s *dev)
+{
+ FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+ uint32_t regval;
+ uint32_t pending;
+ int32_t data;
+
+ regval = adc_getreg(priv, STM32_ADC_ISR_OFFSET);
+ pending = regval & ADC_ISR_ALLINTS;
+ if (pending == 0)
+ {
+ return OK;
+ }
+
+ /* Identifies the interruption AWD, OVR or EOC */
+
+ if ((regval & ADC_ISR_AWD) != 0)
+ {
+ alldbg("WARNING: Analog Watchdog, Value converted out of range!\n");
+ }
+
+ if ((regval & ADC_ISR_OVR) != 0)
+ {
+ alldbg("WARNING: Overrun has occurred!\n");
+ }
+
+ /* EOC: End of conversion */
+
+ if ((regval & ADC_ISR_EOC) != 0)
+ {
+ /* Read the converted value and clear EOC bit
+ * (It is cleared by reading the ADC_DR)
+ */
+
+ data = adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_RDATA_MASK;
+
+ /* Give the ADC data to the ADC driver. adc_receive() accepts 3
+ * parameters:
+ *
+ * 1) The first is the ADC device instance for this ADC block.
+ * 2) The second is the channel number for the data, and
+ * 3) The third is the converted data for the channel.
+ */
+
+ adc_receive(dev, priv->chanlist[priv->current], data);
+
+ /* Set the channel number of the next channel that will complete
+ * conversion.
+ */
+
+ priv->current++;
+
+ if (priv->current >= priv->nchannels)
+ {
+ /* Restart the conversion sequence from the beginning */
+
+ priv->current = 0;
+ }
+ }
+
+ regval &= ~pending;
+ adc_putreg(priv, STM32_ADC_ISR_OFFSET, regval);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: adc123_interrupt
+ *
+ * Description:
+ * ADC1/2/3 interrupt handler
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static int adc123_interrupt(int irq, FAR void *context)
+{
+#ifdef CONFIG_STM32F7_ADC1
+ adc_interrupt(&g_adcdev1);
+#endif
+
+#ifdef CONFIG_STM32F7_ADC2
+ adc_interrupt(&g_adcdev2);
+#endif
+
+#ifdef CONFIG_STM32F7_ADC3
+ adc_interrupt(&g_adcdev3);
+#endif
+
+ return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_adcinitialize
+ *
+ * Description:
+ * Initialize the ADC.
+ *
+ * The logic is, save nchannels : # of channels (conversions) in ADC_SQR1_L
+ * Then, take the chanlist array and store it in the SQR Regs,
+ * chanlist[0] -> ADC_SQR3_SQ1
+ * chanlist[1] -> ADC_SQR3_SQ2
+ * ...
+ * chanlist[15]-> ADC_SQR1_SQ16
+ *
+ * up to
+ * chanlist[nchannels]
+ *
+ * Input Parameters:
+ * intf - Could be {1,2,3} for ADC1, ADC2, or ADC3
+ * chanlist - The list of channels
+ * cchannels - Number of channels
+ *
+ * Returned Value:
+ * Valid ADC device structure reference on succcess; a NULL on failure
+ *
+ ****************************************************************************/
+
+struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
+ int cchannels)
+{
+ FAR struct adc_dev_s *dev;
+ FAR struct stm32_dev_s *priv;
+
+ avdbg("intf: %d cchannels: %d\n", intf, cchannels);
+
+ switch (intf)
+ {
+#ifdef CONFIG_STM32F7_ADC1
+ case 1:
+ avdbg("ADC1 selected\n");
+ dev = &g_adcdev1;
+ break;
+#endif
+#ifdef CONFIG_STM32F7_ADC2
+ case 2:
+ avdbg("ADC2 selected\n");
+ dev = &g_adcdev2;
+ break;
+#endif
+#ifdef CONFIG_STM32F7_ADC3
+ case 3:
+ avdbg("ADC3 selected\n");
+ dev = &g_adcdev3;
+ break;
+#endif
+ default:
+ adbg("No ADC interface defined\n");
+ return NULL;
+ }
+
+ /* Configure the selected ADC */
+
+ priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+
+ DEBUGASSERT(cchannels <= ADC_MAX_SAMPLES);
+
+ priv->cchannels = cchannels;
+
+ memcpy(priv->chanlist, chanlist, cchannels);
+
+ return dev;
+}
+
+#endif /* CONFIG_STM32F7_STM32F74XX */
+#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 ||
+ * CONFIG_STM32F7_ADC3
+ */
+#endif /* CONFIG_ADC */
diff --git a/arch/arm/src/stm32f7/stm32_adc.h b/arch/arm/src/stm32f7/stm32_adc.h
new file mode 100644
index 0000000000..b4383c74fb
--- /dev/null
+++ b/arch/arm/src/stm32f7/stm32_adc.h
@@ -0,0 +1,774 @@
+/************************************************************************************
+ * arch/arm/src/stm32f7/stm32_adc.h
+ *
+ * Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved.
+ * Authors: Gregory Nutt
+ * Paul Alexander Patience
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_STM32_ADC_H
+#define __ARCH_ARM_SRC_STM32F7_STM32_ADC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+#include
+#include "chip.h"
+#include "chip/stm32_adc.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Configuration ********************************************************************/
+
+/* Timer devices may be used for different purposes. One special purpose is to
+ * control periodic ADC sampling. If CONFIG_STM32F7_TIMn is defined then
+ * CONFIG_STM32F7_TIMn_ADC must also be defined to indicate that timer "n" is intended
+ * to be used for that purpose. Timers 1-6 and 8 may be used.
+ */
+
+#ifndef CONFIG_STM32F7_TIM1
+# undef CONFIG_STM32F7_TIM1_ADC
+# undef CONFIG_STM32F7_TIM1_ADC1
+# undef CONFIG_STM32F7_TIM1_ADC2
+# undef CONFIG_STM32F7_TIM1_ADC3
+#endif
+#ifndef CONFIG_STM32F7_TIM2
+# undef CONFIG_STM32F7_TIM2_ADC
+# undef CONFIG_STM32F7_TIM2_ADC1
+# undef CONFIG_STM32F7_TIM2_ADC2
+# undef CONFIG_STM32F7_TIM2_ADC3
+#endif
+#ifndef CONFIG_STM32F7_TIM3
+# undef CONFIG_STM32F7_TIM3_ADC
+# undef CONFIG_STM32F7_TIM3_ADC1
+# undef CONFIG_STM32F7_TIM3_ADC2
+# undef CONFIG_STM32F7_TIM3_ADC3
+#endif
+#ifndef CONFIG_STM32F7_TIM4
+# undef CONFIG_STM32F7_TIM4_ADC
+# undef CONFIG_STM32F7_TIM4_ADC1
+# undef CONFIG_STM32F7_TIM4_ADC2
+# undef CONFIG_STM32F7_TIM4_ADC3
+#endif
+#ifndef CONFIG_STM32F7_TIM5
+# undef CONFIG_STM32F7_TIM5_ADC
+# undef CONFIG_STM32F7_TIM5_ADC1
+# undef CONFIG_STM32F7_TIM5_ADC2
+# undef CONFIG_STM32F7_TIM5_ADC3
+#endif
+#ifndef CONFIG_STM32F7_TIM6
+# undef CONFIG_STM32F7_TIM6_ADC
+# undef CONFIG_STM32F7_TIM6_ADC1
+# undef CONFIG_STM32F7_TIM6_ADC2
+# undef CONFIG_STM32F7_TIM6_ADC3
+#endif
+#ifndef CONFIG_STM32F7_TIM8
+# undef CONFIG_STM32F7_TIM8_ADC
+# undef CONFIG_STM32F7_TIM8_ADC1
+# undef CONFIG_STM32F7_TIM8_ADC2
+# undef CONFIG_STM32F7_TIM8_ADC3
+#endif
+
+/* Up to 3 ADC interfaces are supported */
+
+#if STM32_NADC < 4
+# undef CONFIG_STM32F7_ADC4
+#endif
+
+#if STM32_NADC < 3
+# undef CONFIG_STM32F7_ADC3
+#endif
+
+#if STM32_NADC < 2
+# undef CONFIG_STM32F7_ADC2
+#endif
+
+#if STM32_NADC < 1
+# undef CONFIG_STM32F7_ADC1
+#endif
+
+#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || \
+ defined(CONFIG_STM32F7_ADC3)
+
+/* DMA support */
+
+#undef ADC_HAVE_DMA
+#if defined(CONFIG_STM32F7_ADC1_DMA) || defined(CONFIG_STM32F7_ADC2_DMA) || \
+ defined(CONFIG_STM32F7_ADC3_DMA)
+# define ADC_HAVE_DMA 1
+#endif
+
+#ifdef CONFIG_STM32F7_ADC1_DMA
+# define ADC1_HAVE_DMA 1
+#else
+# undef ADC1_HAVE_DMA
+#endif
+
+#ifdef CONFIG_STM32F7_ADC2_DMA
+# define ADC2_HAVE_DMA 1
+#else
+# undef ADC2_HAVE_DMA
+#endif
+
+#ifdef CONFIG_STM32F7_ADC3_DMA
+# define ADC3_HAVE_DMA 1
+#else
+# undef ADC3_HAVE_DMA
+#endif
+
+/* Timer configuration: If a timer trigger is specified, then get
+ * information about the timer.
+ */
+
+#if defined(CONFIG_STM32F7_TIM1_ADC1)
+# define ADC1_HAVE_TIMER 1
+# define ADC1_TIMER_BASE STM32_TIM1_BASE
+# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
+#elif defined(CONFIG_STM32F7_TIM2_ADC1)
+# define ADC1_HAVE_TIMER 1
+# define ADC1_TIMER_BASE STM32_TIM2_BASE
+# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
+#elif defined(CONFIG_STM32F7_TIM3_ADC1)
+# define ADC1_HAVE_TIMER 1
+# define ADC1_TIMER_BASE STM32_TIM3_BASE
+# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
+#elif defined(CONFIG_STM32F7_TIM4_ADC1)
+# define ADC1_HAVE_TIMER 1
+# define ADC1_TIMER_BASE STM32_TIM4_BASE
+# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
+#elif defined(CONFIG_STM32F7_TIM5_ADC1)
+# define ADC1_HAVE_TIMER 1
+# define ADC1_TIMER_BASE STM32_TIM5_BASE
+# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN
+#elif defined(CONFIG_STM32F7_TIM6_ADC1)
+# define ADC1_HAVE_TIMER 1
+# define ADC1_TIMER_BASE STM32_TIM6_BASE
+# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN
+#elif defined(CONFIG_STM32F7_TIM8_ADC1)
+# define ADC1_HAVE_TIMER 1
+# define ADC1_TIMER_BASE STM32_TIM8_BASE
+# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
+#else
+# undef ADC1_HAVE_TIMER
+#endif
+
+#ifdef ADC1_HAVE_TIMER
+# ifndef CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY
+# error "CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY not defined"
+# endif
+# ifndef CONFIG_STM32F7_ADC1_TIMTRIG
+# error "CONFIG_STM32F7_ADC1_TIMTRIG not defined"
+# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO"
+# endif
+#endif
+
+#if defined(CONFIG_STM32F7_TIM1_ADC2)
+# define ADC2_HAVE_TIMER 1
+# define ADC2_TIMER_BASE STM32_TIM1_BASE
+# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
+#elif defined(CONFIG_STM32F7_TIM2_ADC2)
+# define ADC2_HAVE_TIMER 1
+# define ADC2_TIMER_BASE STM32_TIM2_BASE
+# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
+#elif defined(CONFIG_STM32F7_TIM3_ADC2)
+# define ADC2_HAVE_TIMER 1
+# define ADC2_TIMER_BASE STM32_TIM3_BASE
+# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
+#elif defined(CONFIG_STM32F7_TIM4_ADC2)
+# define ADC2_HAVE_TIMER 1
+# define ADC2_TIMER_BASE STM32_TIM4_BASE
+# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
+#elif defined(CONFIG_STM32F7_TIM5_ADC2)
+# define ADC2_HAVE_TIMER 1
+# define ADC2_TIMER_BASE STM32_TIM5_BASE
+# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN
+#elif defined(CONFIG_STM32F7_TIM6_ADC2)
+# define ADC2_HAVE_TIMER 1
+# define ADC2_TIMER_BASE STM32_TIM6_BASE
+# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN
+#elif defined(CONFIG_STM32F7_TIM8_ADC2)
+# define ADC2_HAVE_TIMER 1
+# define ADC2_TIMER_BASE STM32_TIM8_BASE
+# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
+#else
+# undef ADC2_HAVE_TIMER
+#endif
+
+#ifdef ADC2_HAVE_TIMER
+# ifndef CONFIG_STM32F7_ADC2_SAMPLE_FREQUENCY
+# error "CONFIG_STM32F7_ADC2_SAMPLE_FREQUENCY not defined"
+# endif
+# ifndef CONFIG_STM32F7_ADC2_TIMTRIG
+# error "CONFIG_STM32F7_ADC2_TIMTRIG not defined"
+# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO"
+# endif
+#endif
+
+#if defined(CONFIG_STM32F7_TIM1_ADC3)
+# define ADC3_HAVE_TIMER 1
+# define ADC3_TIMER_BASE STM32_TIM1_BASE
+# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
+#elif defined(CONFIG_STM32F7_TIM2_ADC3)
+# define ADC3_HAVE_TIMER 1
+# define ADC3_TIMER_BASE STM32_TIM2_BASE
+# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
+#elif defined(CONFIG_STM32F7_TIM3_ADC3)
+# define ADC3_HAVE_TIMER 1
+# define ADC3_TIMER_BASE STM32_TIM3_BASE
+# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
+#elif defined(CONFIG_STM32F7_TIM4_ADC3)
+# define ADC3_HAVE_TIMER 1
+# define ADC3_TIMER_BASE STM32_TIM4_BASE
+# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
+#elif defined(CONFIG_STM32F7_TIM5_ADC3)
+# define ADC3_HAVE_TIMER 1
+# define ADC3_TIMER_BASE STM32_TIM5_BASE
+# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN
+#elif defined(CONFIG_STM32F7_TIM6_ADC3)
+# define ADC3_HAVE_TIMER 1
+# define ADC3_TIMER_BASE STM32_TIM6_BASE
+# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN
+#elif defined(CONFIG_STM32F7_TIM8_ADC3)
+# define ADC3_HAVE_TIMER 1
+# define ADC3_TIMER_BASE STM32_TIM8_BASE
+# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
+#else
+# undef ADC3_HAVE_TIMER
+#endif
+
+#ifdef ADC3_HAVE_TIMER
+# ifndef CONFIG_STM32F7_ADC3_SAMPLE_FREQUENCY
+# error "CONFIG_STM32F7_ADC3_SAMPLE_FREQUENCY not defined"
+# endif
+# ifndef CONFIG_STM32F7_ADC3_TIMTRIG
+# error "CONFIG_STM32F7_ADC3_TIMTRIG not defined"
+# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO"
+# endif
+#endif
+
+#if defined(ADC1_HAVE_TIMER) || defined(ADC2_HAVE_TIMER) || \
+ defined(ADC3_HAVE_TIMER)
+# define ADC_HAVE_TIMER 1
+#else
+# undef ADC_HAVE_TIMER
+#endif
+
+/* NOTE: The following assumes that all possible combinations of timers and
+ * values are support EXTSEL. That is not so and it varies from one STM32
+ * to another. But this (wrong) assumptions keeps the logic as simple as
+ * possible. If unsupported combination is used, an error will show up
+ * later during compilation although it may be difficult to track it back
+ * to this simplification.
+ *
+ */
+
+# define ADC1_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1
+# define ADC1_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2
+# define ADC1_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3
+# define ADC1_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4
+# define ADC1_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO
+# define ADC1_EXTSEL_T1TRGO2 ADC_CR2_EXTSEL_T1TRGO2
+# define ADC2_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1
+# define ADC2_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2
+# define ADC2_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3
+# define ADC2_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4
+# define ADC2_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO
+# define ADC2_EXTSEL_T1TRGO2 ADC_CR2_EXTSEL_T1TRGO2
+# define ADC3_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1
+# define ADC3_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2
+# define ADC3_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3
+# define ADC3_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4
+# define ADC3_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO
+# define ADC3_EXTSEL_T1TRGO2 ADC_CR2_EXTSEL_T1TRGO2
+
+# define ADC1_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1
+# define ADC1_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2
+# define ADC1_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3
+# define ADC1_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4
+# define ADC1_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO
+# define ADC2_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1
+# define ADC2_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2
+# define ADC2_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3
+# define ADC2_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4
+# define ADC2_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO
+# define ADC3_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1
+# define ADC3_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2
+# define ADC3_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3
+# define ADC3_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4
+# define ADC3_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO
+
+# define ADC1_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1
+# define ADC1_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2
+# define ADC1_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3
+# define ADC1_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4
+# define ADC1_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO
+# define ADC2_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1
+# define ADC2_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2
+# define ADC2_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3
+# define ADC2_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4
+# define ADC2_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO
+# define ADC3_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1
+# define ADC3_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2
+# define ADC3_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3
+# define ADC3_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4
+# define ADC3_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO
+
+# define ADC1_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1
+# define ADC1_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2
+# define ADC1_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3
+# define ADC1_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4
+# define ADC1_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO
+# define ADC2_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1
+# define ADC2_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2
+# define ADC2_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3
+# define ADC2_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4
+# define ADC2_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO
+# define ADC3_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1
+# define ADC3_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2
+# define ADC3_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3
+# define ADC3_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4
+# define ADC3_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO
+
+# define ADC1_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1
+# define ADC1_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2
+# define ADC1_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3
+# define ADC1_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4
+# define ADC1_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO
+# define ADC2_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1
+# define ADC2_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2
+# define ADC2_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3
+# define ADC2_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4
+# define ADC2_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO
+# define ADC3_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1
+# define ADC3_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2
+# define ADC3_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3
+# define ADC3_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4
+# define ADC3_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO
+
+# define ADC1_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1
+# define ADC1_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2
+# define ADC1_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3
+# define ADC1_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4
+# define ADC1_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO
+# define ADC2_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1
+# define ADC2_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2
+# define ADC2_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3
+# define ADC2_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4
+# define ADC2_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO
+# define ADC3_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1
+# define ADC3_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2
+# define ADC3_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3
+# define ADC3_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4
+# define ADC3_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO
+
+# define ADC1_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1
+# define ADC1_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2
+# define ADC1_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3
+# define ADC1_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4
+# define ADC1_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO
+# define ADC1_EXTSEL_T8TRGO2 ADC_CR2_EXTSEL_T8TRGO2
+# define ADC2_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1
+# define ADC2_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2
+# define ADC2_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3
+# define ADC2_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4
+# define ADC2_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO
+# define ADC2_EXTSEL_T8TRGO2 ADC_CR2_EXTSEL_T8TRGO2
+# define ADC3_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1
+# define ADC3_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2
+# define ADC3_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3
+# define ADC3_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4
+# define ADC3_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO
+# define ADC3_EXTSEL_T8TRGO2 ADC_CR2_EXTSEL_T8TRGO2
+
+
+#if defined(CONFIG_STM32F7_TIM1_ADC1)
+# if CONFIG_STM32F7_ADC1_TIMTRIG == 0
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC2
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC3
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 5
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2
+# else
+# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range"
+# endif
+#elif defined(CONFIG_STM32F7_TIM2_ADC1)
+# if CONFIG_STM32F7_ADC1_TIMTRIG == 0
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC1
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC2
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC3
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO
+# else
+# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range"
+# endif
+#elif defined(CONFIG_STM32F7_TIM3_ADC1)
+# if CONFIG_STM32F7_ADC1_TIMTRIG == 0
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC1
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC2
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC3
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC4
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO
+# else
+# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range"
+# endif
+#elif defined(CONFIG_STM32F7_TIM4_ADC1)
+# if CONFIG_STM32F7_ADC1_TIMTRIG == 0
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC1
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC2
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC3
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC4
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4TRGO
+# else
+# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range"
+# endif
+#elif defined(CONFIG_STM32F7_TIM5_ADC1)
+# if CONFIG_STM32F7_ADC1_TIMTRIG == 0
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC1
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC2
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC3
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC4
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5TRGO
+# else
+# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range"
+# endif
+#elif defined(CONFIG_STM32F7_TIM6_ADC1)
+# if CONFIG_STM32F7_ADC1_TIMTRIG == 0
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC1
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC2
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC3
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC4
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6TRGO
+# else
+# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range"
+# endif
+#elif defined(CONFIG_STM32F7_TIM8_ADC1)
+# if CONFIG_STM32F7_ADC1_TIMTRIG == 0
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC1
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC2
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC3
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC4
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO
+# elif CONFIG_STM32F7_ADC1_TIMTRIG == 5
+# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO2
+# else
+# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range"
+# endif
+#endif
+
+#if defined(CONFIG_STM32F7_TIM1_ADC2)
+# if CONFIG_STM32F7_ADC2_TIMTRIG == 0
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC1
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC2
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC3
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC4
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 5
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO2
+# else
+# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range"
+# endif
+#elif defined(CONFIG_STM32F7_TIM2_ADC2)
+# if CONFIG_STM32F7_ADC2_TIMTRIG == 0
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC1
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC2
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC3
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC4
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2TRGO
+# else
+# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range"
+# endif
+#elif defined(CONFIG_STM32F7_TIM3_ADC2)
+# if CONFIG_STM32F7_ADC2_TIMTRIG == 0
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC1
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC2
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC3
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC4
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3TRGO
+# else
+# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range"
+# endif
+#elif defined(CONFIG_STM32F7_TIM4_ADC2)
+# if CONFIG_STM32F7_ADC2_TIMTRIG == 0
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC1
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC2
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC3
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC4
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4TRGO
+# else
+# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range"
+# endif
+#elif defined(CONFIG_STM32F7_TIM5_ADC2)
+# if CONFIG_STM32F7_ADC2_TIMTRIG == 0
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC1
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC2
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC3
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC4
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5TRGO
+# else
+# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range"
+# endif
+#elif defined(CONFIG_STM32F7_TIM6_ADC2)
+# if CONFIG_STM32F7_ADC2_TIMTRIG == 0
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC1
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC2
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC3
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC4
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6TRGO
+# else
+# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range"
+# endif
+#elif defined(CONFIG_STM32F7_TIM8_ADC2)
+# if CONFIG_STM32F7_ADC2_TIMTRIG == 0
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC1
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC2
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC3
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC4
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO
+# elif CONFIG_STM32F7_ADC2_TIMTRIG == 5
+# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO2
+# else
+# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range"
+# endif
+#endif
+
+#if defined(CONFIG_STM32F7_TIM1_ADC3)
+# if CONFIG_STM32F7_ADC3_TIMTRIG == 0
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC1
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC2
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC3
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC4
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 5
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO2
+# else
+# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range"
+# endif
+#elif defined(CONFIG_STM32F7_TIM2_ADC3)
+# if CONFIG_STM32F7_ADC3_TIMTRIG == 0
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC1
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC2
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC3
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC4
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2TRGO
+# else
+# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range"
+# endif
+#elif defined(CONFIG_STM32F7_TIM3_ADC3)
+# if CONFIG_STM32F7_ADC3_TIMTRIG == 0
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC1
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC2
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC3
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC4
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3TRGO
+# else
+# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range"
+# endif
+#elif defined(CONFIG_STM32F7_TIM4_ADC3)
+# if CONFIG_STM32F7_ADC3_TIMTRIG == 0
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC1
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC2
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC3
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC4
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4TRGO
+# else
+# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range"
+# endif
+#elif defined(CONFIG_STM32F7_TIM5_ADC3)
+# if CONFIG_STM32F7_ADC3_TIMTRIG == 0
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC1
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC2
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC3
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC4
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5TRGO
+# else
+# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range"
+# endif
+#elif defined(CONFIG_STM32F7_TIM6_ADC3)
+# if CONFIG_STM32F7_ADC3_TIMTRIG == 0
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC1
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC2
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC3
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC4
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6TRGO
+# else
+# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range"
+# endif
+#elif defined(CONFIG_STM32F7_TIM8_ADC3)
+# if CONFIG_STM32F7_ADC3_TIMTRIG == 0
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC1
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC2
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC3
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC4
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO
+# elif CONFIG_STM32F7_ADC3_TIMTRIG == 5
+# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO2
+# else
+# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range"
+# endif
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: stm32_adcinitialize
+ *
+ * Description:
+ * Initialize the ADC.
+ *
+ * Input Parameters:
+ * intf - Could be {1,2,3} for ADC1, ADC2, or ADC3
+ * chanlist - The list of channels
+ * nchannels - Number of channels
+ *
+ * Returned Value:
+ * Valid can device structure reference on succcess; a NULL on failure
+ *
+ ****************************************************************************/
+
+struct adc_dev_s;
+struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
+ int nchannels);
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif /* __ASSEMBLY__ */
+
+#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 ||
+ * CONFIG_STM32F7_ADC3
+ */
+#endif /* __ARCH_ARM_SRC_STM32F7_STM32_ADC_H */
--
GitLab
From 2b47473778d287cec35e5c1874c25e227e2fbba7 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Thu, 2 Jun 2016 10:19:02 -0600
Subject: [PATCH 032/400] Remove all references to CONFIG_SYSTEM_FLASH_ERASEALL
---
configs/mikroe-stm32f4/fulldemo/defconfig | 1 -
configs/mikroe-stm32f4/nsh/defconfig | 1 -
configs/mikroe-stm32f4/usbnsh/defconfig | 1 -
configs/olimex-stm32-p107/nsh/defconfig | 1 -
configs/pic32mx-starterkit/nsh/defconfig | 1 -
configs/pic32mx-starterkit/nsh2/defconfig | 1 -
configs/pic32mx7mmb/nsh/defconfig | 1 -
configs/pic32mz-starterkit/nsh/defconfig | 1 -
configs/sam4e-ek/nsh/defconfig | 1 -
configs/sam4e-ek/nxwm/defconfig | 1 -
configs/sam4e-ek/usbnsh/defconfig | 1 -
configs/sama5d3x-ek/demo/defconfig | 1 -
configs/same70-xplained/netnsh/defconfig | 1 -
configs/same70-xplained/nsh/defconfig | 1 -
configs/samv71-xult/mxtxplnd/defconfig | 1 -
configs/samv71-xult/netnsh/defconfig | 1 -
configs/samv71-xult/nsh/defconfig | 1 -
configs/samv71-xult/nxwm/defconfig | 1 -
configs/samv71-xult/vnc/defconfig | 1 -
configs/samv71-xult/vnxwm/defconfig | 1 -
configs/shenzhou/thttpd/defconfig | 1 -
configs/spark/composite/defconfig | 1 -
configs/spark/nsh/defconfig | 1 -
configs/spark/usbmsc/defconfig | 1 -
configs/spark/usbnsh/defconfig | 1 -
configs/stm3210e-eval/nsh2/defconfig | 1 -
configs/stm3220g-eval/nsh/defconfig | 1 -
configs/stm3220g-eval/nsh2/defconfig | 1 -
configs/stm3240g-eval/nsh2/defconfig | 1 -
configs/stm32f429i-disco/extflash/defconfig | 1 -
configs/stm32l476vg-disco/nsh/defconfig | 1 -
31 files changed, 31 deletions(-)
diff --git a/configs/mikroe-stm32f4/fulldemo/defconfig b/configs/mikroe-stm32f4/fulldemo/defconfig
index 65b3ac8069..5d2ec9b165 100644
--- a/configs/mikroe-stm32f4/fulldemo/defconfig
+++ b/configs/mikroe-stm32f4/fulldemo/defconfig
@@ -1722,7 +1722,6 @@ CONFIG_MIKROE_STM32F4_CONFIGDATA_PART=y
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-CONFIG_SYSTEM_FLASH_ERASEALL=y
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
CONFIG_SYSTEM_NXPLAYER=y
diff --git a/configs/mikroe-stm32f4/nsh/defconfig b/configs/mikroe-stm32f4/nsh/defconfig
index ed18e9a0b9..9ef8a7e8e3 100644
--- a/configs/mikroe-stm32f4/nsh/defconfig
+++ b/configs/mikroe-stm32f4/nsh/defconfig
@@ -1218,7 +1218,6 @@ CONFIG_NSH_ARCHINIT=y
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-CONFIG_SYSTEM_FLASH_ERASEALL=y
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
# CONFIG_SYSTEM_RAMTEST is not set
diff --git a/configs/mikroe-stm32f4/usbnsh/defconfig b/configs/mikroe-stm32f4/usbnsh/defconfig
index ae0211b6ad..2ba9677ab6 100644
--- a/configs/mikroe-stm32f4/usbnsh/defconfig
+++ b/configs/mikroe-stm32f4/usbnsh/defconfig
@@ -1268,7 +1268,6 @@ CONFIG_NSH_ARCHINIT=y
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-CONFIG_SYSTEM_FLASH_ERASEALL=y
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
# CONFIG_SYSTEM_RAMTEST is not set
diff --git a/configs/olimex-stm32-p107/nsh/defconfig b/configs/olimex-stm32-p107/nsh/defconfig
index 6f02ee2d93..0dd0067302 100644
--- a/configs/olimex-stm32-p107/nsh/defconfig
+++ b/configs/olimex-stm32-p107/nsh/defconfig
@@ -1341,7 +1341,6 @@ CONFIG_NSH_MAX_ROUNDTRIP=20
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
# CONFIG_SYSTEM_NETDB is not set
diff --git a/configs/pic32mx-starterkit/nsh/defconfig b/configs/pic32mx-starterkit/nsh/defconfig
index 34d57a29fd..f337701d2e 100644
--- a/configs/pic32mx-starterkit/nsh/defconfig
+++ b/configs/pic32mx-starterkit/nsh/defconfig
@@ -889,7 +889,6 @@ CONFIG_NSH_ARCHINIT=y
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_FSUTILS_INIFILE is not set
# CONFIG_SYSTEM_RAMTEST is not set
diff --git a/configs/pic32mx-starterkit/nsh2/defconfig b/configs/pic32mx-starterkit/nsh2/defconfig
index 60935ce1ac..7163dda511 100644
--- a/configs/pic32mx-starterkit/nsh2/defconfig
+++ b/configs/pic32mx-starterkit/nsh2/defconfig
@@ -1119,7 +1119,6 @@ CONFIG_NSH_IOBUFFER_SIZE=512
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_FSUTILS_INIFILE is not set
# CONFIG_SYSTEM_HEXED is not set
diff --git a/configs/pic32mx7mmb/nsh/defconfig b/configs/pic32mx7mmb/nsh/defconfig
index 492a3f054e..6433c6d3e8 100644
--- a/configs/pic32mx7mmb/nsh/defconfig
+++ b/configs/pic32mx7mmb/nsh/defconfig
@@ -1179,7 +1179,6 @@ CONFIG_NSH_IOBUFFER_SIZE=512
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_FSUTILS_INIFILE is not set
# CONFIG_SYSTEM_HEXED is not set
diff --git a/configs/pic32mz-starterkit/nsh/defconfig b/configs/pic32mz-starterkit/nsh/defconfig
index a6299b98a9..4948a286e6 100644
--- a/configs/pic32mz-starterkit/nsh/defconfig
+++ b/configs/pic32mz-starterkit/nsh/defconfig
@@ -816,7 +816,6 @@ CONFIG_NSH_ARCHINIT=y
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_FSUTILS_INIFILE is not set
# CONFIG_SYSTEM_RAMTEST is not set
diff --git a/configs/sam4e-ek/nsh/defconfig b/configs/sam4e-ek/nsh/defconfig
index 869702660d..5fd87f6c13 100644
--- a/configs/sam4e-ek/nsh/defconfig
+++ b/configs/sam4e-ek/nsh/defconfig
@@ -1216,7 +1216,6 @@ CONFIG_NSH_IOBUFFER_SIZE=512
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
# CONFIG_SYSTEM_NETDB is not set
diff --git a/configs/sam4e-ek/nxwm/defconfig b/configs/sam4e-ek/nxwm/defconfig
index 5e2ebc17c0..d0ff053f15 100644
--- a/configs/sam4e-ek/nxwm/defconfig
+++ b/configs/sam4e-ek/nxwm/defconfig
@@ -1572,7 +1572,6 @@ CONFIG_NXWM_HEXCALCULATOR_FONTID=5
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
# CONFIG_SYSTEM_NETDB is not set
diff --git a/configs/sam4e-ek/usbnsh/defconfig b/configs/sam4e-ek/usbnsh/defconfig
index 58b643af0c..0252440008 100644
--- a/configs/sam4e-ek/usbnsh/defconfig
+++ b/configs/sam4e-ek/usbnsh/defconfig
@@ -1256,7 +1256,6 @@ CONFIG_NSH_IOBUFFER_SIZE=512
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
# CONFIG_SYSTEM_NETDB is not set
diff --git a/configs/sama5d3x-ek/demo/defconfig b/configs/sama5d3x-ek/demo/defconfig
index fc3d188f89..6805bd04ab 100644
--- a/configs/sama5d3x-ek/demo/defconfig
+++ b/configs/sama5d3x-ek/demo/defconfig
@@ -1131,7 +1131,6 @@ CONFIG_NSH_ARCHINIT=y
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
# CONFIG_SYSTEM_RAMTEST is not set
diff --git a/configs/same70-xplained/netnsh/defconfig b/configs/same70-xplained/netnsh/defconfig
index 17951d79a8..8e6d047dd6 100644
--- a/configs/same70-xplained/netnsh/defconfig
+++ b/configs/same70-xplained/netnsh/defconfig
@@ -1265,7 +1265,6 @@ CONFIG_NSH_IOBUFFER_SIZE=512
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
CONFIG_SYSTEM_I2CTOOL=y
CONFIG_I2CTOOL_MINBUS=0
diff --git a/configs/same70-xplained/nsh/defconfig b/configs/same70-xplained/nsh/defconfig
index 7a425dcb80..07e012f98e 100644
--- a/configs/same70-xplained/nsh/defconfig
+++ b/configs/same70-xplained/nsh/defconfig
@@ -1031,7 +1031,6 @@ CONFIG_NSH_ARCHINIT=y
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
CONFIG_SYSTEM_I2CTOOL=y
CONFIG_I2CTOOL_MINBUS=0
diff --git a/configs/samv71-xult/mxtxplnd/defconfig b/configs/samv71-xult/mxtxplnd/defconfig
index 93136214de..2186d42ddf 100644
--- a/configs/samv71-xult/mxtxplnd/defconfig
+++ b/configs/samv71-xult/mxtxplnd/defconfig
@@ -1176,7 +1176,6 @@ CONFIG_NSH_ARCHINIT=y
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
CONFIG_SYSTEM_I2CTOOL=y
CONFIG_I2CTOOL_MINBUS=0
diff --git a/configs/samv71-xult/netnsh/defconfig b/configs/samv71-xult/netnsh/defconfig
index ccc9adb0d8..f029c9e9a9 100644
--- a/configs/samv71-xult/netnsh/defconfig
+++ b/configs/samv71-xult/netnsh/defconfig
@@ -1277,7 +1277,6 @@ CONFIG_NSH_IOBUFFER_SIZE=512
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
CONFIG_SYSTEM_I2CTOOL=y
CONFIG_I2CTOOL_MINBUS=0
diff --git a/configs/samv71-xult/nsh/defconfig b/configs/samv71-xult/nsh/defconfig
index 8734da8581..235b9afd19 100644
--- a/configs/samv71-xult/nsh/defconfig
+++ b/configs/samv71-xult/nsh/defconfig
@@ -1041,7 +1041,6 @@ CONFIG_NSH_ARCHINIT=y
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
CONFIG_SYSTEM_I2CTOOL=y
CONFIG_I2CTOOL_MINBUS=0
diff --git a/configs/samv71-xult/nxwm/defconfig b/configs/samv71-xult/nxwm/defconfig
index 7bba67ff6e..f0734a4218 100644
--- a/configs/samv71-xult/nxwm/defconfig
+++ b/configs/samv71-xult/nxwm/defconfig
@@ -1363,7 +1363,6 @@ CONFIG_NXWM_HEXCALCULATOR_FONTID=5
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
CONFIG_SYSTEM_I2CTOOL=y
CONFIG_I2CTOOL_MINBUS=0
diff --git a/configs/samv71-xult/vnc/defconfig b/configs/samv71-xult/vnc/defconfig
index 8aad6db72b..e3088f3870 100644
--- a/configs/samv71-xult/vnc/defconfig
+++ b/configs/samv71-xult/vnc/defconfig
@@ -1358,7 +1358,6 @@ CONFIG_NSH_IOBUFFER_SIZE=512
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_I2CTOOL is not set
# CONFIG_SYSTEM_HEXED is not set
diff --git a/configs/samv71-xult/vnxwm/defconfig b/configs/samv71-xult/vnxwm/defconfig
index 6e9f662f49..27fcae5122 100644
--- a/configs/samv71-xult/vnxwm/defconfig
+++ b/configs/samv71-xult/vnxwm/defconfig
@@ -1549,7 +1549,6 @@ CONFIG_NXWM_HEXCALCULATOR_FONTID=5
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_I2CTOOL is not set
# CONFIG_SYSTEM_HEXED is not set
diff --git a/configs/shenzhou/thttpd/defconfig b/configs/shenzhou/thttpd/defconfig
index 89c3735931..29c1266ee6 100644
--- a/configs/shenzhou/thttpd/defconfig
+++ b/configs/shenzhou/thttpd/defconfig
@@ -1472,7 +1472,6 @@ CONFIG_NSH_IOBUFFER_SIZE=512
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
# CONFIG_SYSTEM_NETDB is not set
diff --git a/configs/spark/composite/defconfig b/configs/spark/composite/defconfig
index 0db4b8554e..bb01a161b5 100644
--- a/configs/spark/composite/defconfig
+++ b/configs/spark/composite/defconfig
@@ -1252,7 +1252,6 @@ CONFIG_NSH_ARCHINIT=y
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
# CONFIG_SYSTEM_RAMTEST is not set
diff --git a/configs/spark/nsh/defconfig b/configs/spark/nsh/defconfig
index a5f8963ab4..6f2a5f631a 100644
--- a/configs/spark/nsh/defconfig
+++ b/configs/spark/nsh/defconfig
@@ -1254,7 +1254,6 @@ CONFIG_NSH_ARCHINIT=y
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
# CONFIG_SYSTEM_RAMTEST is not set
diff --git a/configs/spark/usbmsc/defconfig b/configs/spark/usbmsc/defconfig
index ae97bcd86c..cb4040ef82 100644
--- a/configs/spark/usbmsc/defconfig
+++ b/configs/spark/usbmsc/defconfig
@@ -1217,7 +1217,6 @@ CONFIG_NSH_ARCHINIT=y
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
# CONFIG_SYSTEM_RAMTEST is not set
diff --git a/configs/spark/usbnsh/defconfig b/configs/spark/usbnsh/defconfig
index 5c7f49052d..4d3c51a5ff 100644
--- a/configs/spark/usbnsh/defconfig
+++ b/configs/spark/usbnsh/defconfig
@@ -1200,7 +1200,6 @@ CONFIG_USBDEV_MINOR=0
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
# CONFIG_SYSTEM_RAMTEST is not set
diff --git a/configs/stm3210e-eval/nsh2/defconfig b/configs/stm3210e-eval/nsh2/defconfig
index c222587561..f2a22b3f38 100644
--- a/configs/stm3210e-eval/nsh2/defconfig
+++ b/configs/stm3210e-eval/nsh2/defconfig
@@ -1402,7 +1402,6 @@ CONFIG_NSH_ARCHINIT=y
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
CONFIG_SYSTEM_I2CTOOL=y
CONFIG_I2CTOOL_MINBUS=1
diff --git a/configs/stm3220g-eval/nsh/defconfig b/configs/stm3220g-eval/nsh/defconfig
index aca94bb076..84f2214df4 100644
--- a/configs/stm3220g-eval/nsh/defconfig
+++ b/configs/stm3220g-eval/nsh/defconfig
@@ -1398,7 +1398,6 @@ CONFIG_NSH_MAX_ROUNDTRIP=20
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_I2CTOOL is not set
# CONFIG_SYSTEM_HEXED is not set
diff --git a/configs/stm3220g-eval/nsh2/defconfig b/configs/stm3220g-eval/nsh2/defconfig
index b689019b01..625447e2f3 100644
--- a/configs/stm3220g-eval/nsh2/defconfig
+++ b/configs/stm3220g-eval/nsh2/defconfig
@@ -1423,7 +1423,6 @@ CONFIG_NSH_IOBUFFER_SIZE=512
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
CONFIG_SYSTEM_I2CTOOL=y
CONFIG_I2CTOOL_MINBUS=1
diff --git a/configs/stm3240g-eval/nsh2/defconfig b/configs/stm3240g-eval/nsh2/defconfig
index 1752213148..360d7b9e4d 100644
--- a/configs/stm3240g-eval/nsh2/defconfig
+++ b/configs/stm3240g-eval/nsh2/defconfig
@@ -1427,7 +1427,6 @@ CONFIG_NSH_IOBUFFER_SIZE=512
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
CONFIG_SYSTEM_I2CTOOL=y
CONFIG_I2CTOOL_MINBUS=1
diff --git a/configs/stm32f429i-disco/extflash/defconfig b/configs/stm32f429i-disco/extflash/defconfig
index f1601ff527..3fab3e076b 100644
--- a/configs/stm32f429i-disco/extflash/defconfig
+++ b/configs/stm32f429i-disco/extflash/defconfig
@@ -1232,7 +1232,6 @@ CONFIG_PLATFORM_CONFIGDATA=y
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-CONFIG_SYSTEM_FLASH_ERASEALL=y
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
# CONFIG_SYSTEM_RAMTEST is not set
diff --git a/configs/stm32l476vg-disco/nsh/defconfig b/configs/stm32l476vg-disco/nsh/defconfig
index 1b79946f71..9d68963f5d 100644
--- a/configs/stm32l476vg-disco/nsh/defconfig
+++ b/configs/stm32l476vg-disco/nsh/defconfig
@@ -1073,7 +1073,6 @@ CONFIG_NSH_ARCHINIT=y
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
# CONFIG_SYSTEM_RAMTEST is not set
--
GitLab
From a18dbfda6e4acf1d77d13cec1ea35fc628cd0e6d Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Thu, 2 Jun 2016 10:44:13 -0600
Subject: [PATCH 033/400] Remove drivers/mtd/flash_eraseall.c. It is not used
in the OS and is just a dumb wrapper around the MDIOC_BULKERASE IOCTL call.
---
ChangeLog | 8 ++
ReleaseNotes | 3 +-
.../stm3220g-eval/ide/nsh/iar/libdrivers.ewp | 3 -
.../ide/nsh/uvision/libdrivers.uvproj | 5 -
drivers/mtd/Make.defs | 2 +-
drivers/mtd/flash_eraseall.c | 117 ------------------
fs/nxffs/Kconfig | 4 +-
include/nuttx/mtd/mtd.h | 11 --
8 files changed, 13 insertions(+), 140 deletions(-)
delete mode 100644 drivers/mtd/flash_eraseall.c
diff --git a/ChangeLog b/ChangeLog
index ab23bf83e2..0df50e18fc 100755
--- a/ChangeLog
+++ b/ChangeLog
@@ -11879,3 +11879,11 @@
mcan_txempty(). From Frank Benkert (2016-06-01).
7.17 2016-xx-xx Gregory Nutt
+
+ * drivers/mtd/flash_eraseall.c: Removed. This is no longer used
+ in the OS and is simply a wrapper around the MDIOC_BULKERASE
+ IOCTL command. It used to be called (only) from
+ apps/system/flash_eraseall, but that has been removed because it
+ violated the OS/applicatin interface -- by calling flash_eraseall().
+ The old code can be found in the Obsoleted' repository (2016-06-03).
+
diff --git a/ReleaseNotes b/ReleaseNotes
index 71516d18af..c760fca737 100644
--- a/ReleaseNotes
+++ b/ReleaseNotes
@@ -5303,7 +5303,8 @@ Additional new features and extended functionality:
can be re-enabled if needed via configuration option.
- NXFFS: Make the start up scan of the media a configuration option.
It just takes to long and is not really necessary! Those rare cases
- where the scan was helpful can be fixed using flash_eraseall().
+ where the scan was helpful can be fixed using MDIOC_BULKERASE IOCTL
+ command.
* General Drivers:
diff --git a/configs/stm3220g-eval/ide/nsh/iar/libdrivers.ewp b/configs/stm3220g-eval/ide/nsh/iar/libdrivers.ewp
index b009ac58d0..0f2f399a3e 100644
--- a/configs/stm3220g-eval/ide/nsh/iar/libdrivers.ewp
+++ b/configs/stm3220g-eval/ide/nsh/iar/libdrivers.ewp
@@ -1991,9 +1991,6 @@
$PROJ_DIR$/../../../../../drivers/mtd/at45db.c
-
- $PROJ_DIR$/../../../../../drivers/mtd/flash_eraseall.c
-
$PROJ_DIR$/../../../../../drivers/mtd/ftl.c
diff --git a/configs/stm3220g-eval/ide/nsh/uvision/libdrivers.uvproj b/configs/stm3220g-eval/ide/nsh/uvision/libdrivers.uvproj
index f1343317b7..f31ea50bf8 100644
--- a/configs/stm3220g-eval/ide/nsh/uvision/libdrivers.uvproj
+++ b/configs/stm3220g-eval/ide/nsh/uvision/libdrivers.uvproj
@@ -383,11 +383,6 @@
1
../../../../../drivers/mtd/at45db.c
-
- flash_eraseall.c
- 1
- ../../../../../drivers/mtd/flash_eraseall.c
-
ftl.c
1
diff --git a/drivers/mtd/Make.defs b/drivers/mtd/Make.defs
index 1d1ba6d26b..dfc2781e95 100644
--- a/drivers/mtd/Make.defs
+++ b/drivers/mtd/Make.defs
@@ -39,7 +39,7 @@
ifeq ($(CONFIG_MTD),y)
-CSRCS += at45db.c flash_eraseall.c ftl.c m25px.c ramtron.c mtd_config.c
+CSRCS += at45db.c ftl.c m25px.c ramtron.c mtd_config.c
ifeq ($(CONFIG_MTD_PARTITION),y)
CSRCS += mtd_partition.c
diff --git a/drivers/mtd/flash_eraseall.c b/drivers/mtd/flash_eraseall.c
deleted file mode 100644
index 185da7695c..0000000000
--- a/drivers/mtd/flash_eraseall.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/****************************************************************************
- * drivers/mtd/flash_eraseall.c
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include
-
-#include
-#include
-
-#include
-#include
-#include
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: flash_eraseall
- *
- * Description:
- * Call a block driver with the MDIOC_BULKERASE ioctl command. This will
- * cause the MTD driver to erase all of the flash.
- *
- ****************************************************************************/
-
-int flash_eraseall(FAR const char *driver)
-{
- FAR struct inode *inode;
- FAR const struct block_operations *ops;
- int ret;
-
- /* Open the block driver */
-
- ret = open_blockdriver(driver, 0, &inode);
- if (ret < 0)
- {
- fdbg("ERROR: Failed to open '%s': %d\n", driver, ret);
- return ret;
- }
-
- /* Get the block operations */
-
- ops = inode->u.i_bops;
-
- /* Invoke the block driver ioctl method */
-
- ret = -EPERM;
- if (ops->ioctl)
- {
- ret = ops->ioctl(inode, MTDIOC_BULKERASE, 0);
- if (ret < 0)
- {
- fdbg("ERROR: MTD ioctl(%04x) failed: %d\n", MTDIOC_BULKERASE, ret);
- }
- }
-
- /* Close the block driver */
-
- close_blockdriver(inode);
- return ret;
-}
diff --git a/fs/nxffs/Kconfig b/fs/nxffs/Kconfig
index 3618b2cf64..f3dd6e1166 100644
--- a/fs/nxffs/Kconfig
+++ b/fs/nxffs/Kconfig
@@ -31,8 +31,8 @@ config NXFFS_SCAN_VOLUME
The down side is that scanning the volume can adversely affect
your start-up time. An option is to just erase the FLASH and
- reboot in these cases. That can be done with
- apps/system/flash_eraseall.
+ reboot in these cases. That can be done with MDIOC_BULKERASE
+ IOCTL command.
config NXFFS_NAND
bool "Enable NAND support"
diff --git a/include/nuttx/mtd/mtd.h b/include/nuttx/mtd/mtd.h
index 8d1ee6db70..9ccefb1384 100644
--- a/include/nuttx/mtd/mtd.h
+++ b/include/nuttx/mtd/mtd.h
@@ -298,17 +298,6 @@ FAR struct mtd_dev_s *mtd_rwb_initialize(FAR struct mtd_dev_s *mtd);
int ftl_initialize(int minor, FAR struct mtd_dev_s *mtd);
-/****************************************************************************
- * Name: flash_eraseall
- *
- * Description:
- * Call a block driver with the MTDIOC_BULKERASE ioctl command. This will
- * cause the MTD driver to erase all of the flash.
- *
- ****************************************************************************/
-
-int flash_eraseall(FAR const char *driver);
-
/****************************************************************************
* Name: smart_initialize
*
--
GitLab
From fcdc17056b4e6135bc447296341d4666c76e4531 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Thu, 2 Jun 2016 15:04:23 -0600
Subject: [PATCH 034/400] STM32 F4 RTC: I believe that the F405/407 has only a
single alarm. Not sure.
---
arch/arm/src/stm32/stm32f40xxx_rtcc.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
index 22fd766f6c..d89134fd46 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
@@ -183,10 +183,12 @@ volatile bool g_rtc_enabled = false;
#ifdef CONFIG_RTC_ALARM
static int rtchw_check_alrawf(void);
-static int rtchw_check_alrbwf(void);
static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg);
+#if CONFIG_RTC_NALARMS > 1
+static int rtchw_check_alrbwf(void);
static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg);
#endif
+#endif
/************************************************************************************
* Private Functions
@@ -655,6 +657,7 @@ static int stm32_rtc_alarm_handler(int irq, void *context)
}
}
+#if CONFIG_RTC_NALARMS > 1
if ((isr & RTC_ISR_ALRBF) != 0)
{
cr = getreg32(STM32_RTC_CR);
@@ -678,6 +681,7 @@ static int stm32_rtc_alarm_handler(int irq, void *context)
putreg32(isr, STM32_RTC_CR);
}
}
+#endif
return ret;
}
@@ -723,7 +727,7 @@ static int rtchw_check_alrawf(void)
}
#endif
-#ifdef CONFIG_RTC_ALARM
+#if defined(CONFIG_RTC_ALARM) && CONFIG_RTC_NALARMS > 1
static int rtchw_check_alrbwf(void)
{
volatile uint32_t timeout;
@@ -801,7 +805,7 @@ errout_with_wprunlock:
}
#endif
-#ifdef CONFIG_RTC_ALARM
+#if defined(CONFIG_RTC_ALARM) && CONFIG_RTC_NALARMS > 1
static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg)
{
int ret = -EBUSY;
@@ -1385,6 +1389,7 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
}
break;
+#if CONFIG_RTC_NALARMS > 1
case RTC_ALARMB:
{
cbinfo = &g_alarmcb[RTC_ALARMB];
@@ -1401,6 +1406,7 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
rtc_dumpregs("Set AlarmB");
}
break;
+#endif
default:
rtcvdbg("ERROR: Invalid ALARM%d\n", alminfo->as_id);
@@ -1467,6 +1473,7 @@ int stm32_rtc_cancelalarm(enum alm_id_e alarmid)
}
break;
+#if CONFIG_RTC_NALARMS > 1
case RTC_ALARMB:
{
/* Cancel the global callback function */
@@ -1497,6 +1504,7 @@ int stm32_rtc_cancelalarm(enum alm_id_e alarmid)
ret = OK;
}
break;
+#endif
default:
rtcvdbg("ERROR: Invalid ALARM%d\n", alarmid);
--
GitLab
From 94a14de19096be1e12be3d847629b1e1863163f2 Mon Sep 17 00:00:00 2001
From: Pierre-noel Bouteville
Date: Fri, 3 Jun 2016 08:38:11 -0600
Subject: [PATCH 035/400] Fix EFM32 FLASH conditional compilation
---
arch/arm/src/efm32/efm32_flash.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/src/efm32/efm32_flash.c b/arch/arm/src/efm32/efm32_flash.c
index a35422b73d..1353bbbdb1 100644
--- a/arch/arm/src/efm32/efm32_flash.c
+++ b/arch/arm/src/efm32/efm32_flash.c
@@ -845,7 +845,7 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size)
bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WREN_SHIFT, 0);
-#if (defined(CONFIG_EFM32_EFM32GG) || defined(CONFIG_EFM32_EFM32WG)) && (2==WORDS_PER_DATA_PHASE)
+#if (defined(CONFIG_EFM32_EFM32GG) || defined(CONFIG_EFM32_EFM32WG))
/* Turn off double word write cycle support. */
--
GitLab
From 6a2a0bf11f28324a8a3117dd50738daa40638def Mon Sep 17 00:00:00 2001
From: Pierre-noel Bouteville
Date: Fri, 3 Jun 2016 08:39:17 -0600
Subject: [PATCH 036/400] Note reserved bits in STM32 ADC
---
arch/arm/src/stm32/chip/stm32_adc.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/src/stm32/chip/stm32_adc.h b/arch/arm/src/stm32/chip/stm32_adc.h
index 3a59ba25a8..b0990a37be 100644
--- a/arch/arm/src/stm32/chip/stm32_adc.h
+++ b/arch/arm/src/stm32/chip/stm32_adc.h
@@ -1,7 +1,7 @@
/****************************************************************************************************
* arch/arm/src/stm32/chip/stm32_adc.h
*
- * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009, 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -261,6 +261,7 @@
# define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles. For STM32L15XX: 9 ADCCLK cycles */
# define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles. For STM32L15XX: 7 ADCCLK cycles */
# define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */
+# define ADC_CR1_RESERVED (0xfb3f0000)
#endif
/* ADC control register 2 */
@@ -391,7 +392,7 @@
# define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
# define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */
-
+# define ADC_CR2_RESERVED (0x8080f0fc)
#else
# define ADC_CR2_JEXTSEL_SHIFT (12) /* Bits 12-14: External event select for injected group */
# define ADC_CR2_JEXTSEL_MASK (7 << ADC_CR2_JEXTSEL_SHIFT)
--
GitLab
From 426e425a551a1b8ab659ca9cf409f0a917afeea8 Mon Sep 17 00:00:00 2001
From: Pierre-noel Bouteville
Date: Fri, 3 Jun 2016 08:41:53 -0600
Subject: [PATCH 037/400] Correct conditional compilation in STM32 timer
cpature logic
---
arch/arm/src/stm32/stm32_capture.c | 76 +++++++++++++++---------------
1 file changed, 38 insertions(+), 38 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_capture.c b/arch/arm/src/stm32/stm32_capture.c
index 55864281a9..e5fefa74cf 100644
--- a/arch/arm/src/stm32/stm32_capture.c
+++ b/arch/arm/src/stm32/stm32_capture.c
@@ -185,7 +185,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
{
switch(priv->base)
{
-#ifdef CONFIG_STM32_TIM1
+#ifdef CONFIG_STM32_TIM1_CAP
case STM32_TIM1_BASE:
switch (channel)
{
@@ -212,7 +212,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
}
break;
#endif
-#ifdef CONFIG_STM32_TIM2
+#ifdef CONFIG_STM32_TIM2_CAP
case STM32_TIM2_BASE:
switch (channel)
{
@@ -239,7 +239,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
}
break;
#endif
-#ifdef CONFIG_STM32_TIM3
+#ifdef CONFIG_STM32_TIM3_CAP
case STM32_TIM3_BASE:
switch (channel)
{
@@ -266,7 +266,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
}
break;
#endif
-#ifdef CONFIG_STM32_TIM4
+#ifdef CONFIG_STM32_TIM4_CAP
case STM32_TIM4_BASE:
switch (channel)
{
@@ -293,7 +293,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
}
break;
#endif
-#ifdef CONFIG_STM32_TIM5
+#ifdef CONFIG_STM32_TIM5_CAP
case STM32_TIM5_BASE:
switch (channel)
{
@@ -323,7 +323,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
/* TIM6 and TIM7 cannot be used in capture */
-#ifdef CONFIG_STM32_TIM8
+#ifdef CONFIG_STM32_TIM8_CAP
case STM32_TIM8_BASE:
switch (channel)
{
@@ -351,7 +351,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
break;
#endif
-#ifdef CONFIG_STM32_TIM9
+#ifdef CONFIG_STM32_TIM9_CAP
case STM32_TIM9_BASE:
switch (channel)
{
@@ -379,7 +379,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
break;
#endif
-#ifdef CONFIG_STM32_TIM10
+#ifdef CONFIG_STM32_TIM10_CAP
case STM32_TIM10_BASE:
switch (channel)
{
@@ -407,7 +407,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
break;
#endif
-#ifdef CONFIG_STM32_TIM11
+#ifdef CONFIG_STM32_TIM11_CAP
case STM32_TIM11_BASE:
switch (channel)
{
@@ -435,7 +435,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
break;
#endif
-#ifdef CONFIG_STM32_TIM12
+#ifdef CONFIG_STM32_TIM12_CAP
case STM32_TIM12_BASE:
switch (channel)
{
@@ -463,7 +463,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
break;
#endif
-#ifdef CONFIG_STM32_TIM13
+#ifdef CONFIG_STM32_TIM13_CAP
case STM32_TIM13_BASE:
switch (channel)
{
@@ -491,7 +491,7 @@ static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv,
break;
#endif
-#ifdef CONFIG_STM32_TIM14
+#ifdef CONFIG_STM32_TIM14_CAP
case STM32_TIM14_BASE:
switch (channel)
{
@@ -531,31 +531,31 @@ static inline int stm32_cap_set_rcc(FAR const struct stm32_cap_priv_s *priv,
switch (priv->base)
{
#ifdef CONFIG_STM32_TIM1_CAP
- case 1:
+ case STM32_TIM1_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM1EN;
break;
#endif
#ifdef CONFIG_STM32_TIM2_CAP
- case 2:
+ case STM32_TIM2_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM2EN;
break;
#endif
#ifdef CONFIG_STM32_TIM3_CAP
- case 3:
+ case STM32_TIM3_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM3EN;
break;
#endif
#ifdef CONFIG_STM32_TIM4_CAP
- case 4:
+ case STM32_TIM4_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM4EN;
break;
#endif
#ifdef CONFIG_STM32_TIM5_CAP
- case 5:
+ case STM32_TIM5_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM5EN;
break;
@@ -564,43 +564,43 @@ static inline int stm32_cap_set_rcc(FAR const struct stm32_cap_priv_s *priv,
/* TIM6 and TIM7 cannot be used in capture */
#ifdef CONFIG_STM32_TIM8_CAP
- case 8:
+ case STM32_TIM8_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM8EN;
break;
#endif
#ifdef CONFIG_STM32_TIM9_CAP
- case 9:
+ case STM32_TIM9_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM9EN;
break;
#endif
#ifdef CONFIG_STM32_TIM10_CAP
- case 10:
+ case STM32_TIM10_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM10EN;
break;
#endif
#ifdef CONFIG_STM32_TIM11_CAP
- case 11:
+ case STM32_TIM11_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM11EN;
break;
#endif
#ifdef CONFIG_STM32_TIM12_CAP
- case 12:
+ case STM32_TIM12_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB2ENR_TIM12EN;
break;
#endif
#ifdef CONFIG_STM32_TIM13_CAP
- case 13:
+ case STM32_TIM13_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB2ENR_TIM13EN;
break;
#endif
#ifdef CONFIG_STM32_TIM14_CAP
- case 14:
+ case STM32_TIM14_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB2ENR_TIM14EN;
break;
@@ -1097,9 +1097,9 @@ const struct stm32_cap_priv_s stm32_tim1_priv =
{
.ops = &stm32_cap_ops,
.base = STM32_TIM1_BASE,
- .irq = STM32_IRQ_TIM1,
+ .irq = STM32_IRQ_TIM1CC,
#ifdef USE_ADVENCED_TIM
- .irg_of = STM32_IRQ_TIM1UP,
+ .irq_of = STM32_IRQ_TIM1UP,
#endif
};
#endif
@@ -1111,7 +1111,7 @@ const struct stm32_cap_priv_s stm32_tim2_priv =
.base = STM32_TIM2_BASE,
.irq = STM32_IRQ_TIM2,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
@@ -1123,7 +1123,7 @@ const struct stm32_cap_priv_s stm32_tim3_priv =
.base = STM32_TIM3_BASE,
.irq = STM32_IRQ_TIM3,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
@@ -1135,7 +1135,7 @@ const struct stm32_cap_priv_s stm32_tim4_priv =
.base = STM32_TIM4_BASE,
.irq = STM32_IRQ_TIM4,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
@@ -1147,7 +1147,7 @@ const struct stm32_cap_priv_s stm32_tim5_priv =
.base = STM32_TIM5_BASE,
.irq = STM32_IRQ_TIM5,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
@@ -1159,9 +1159,9 @@ const struct stm32_cap_priv_s stm32_tim8_priv =
{
.ops = &stm32_cap_ops,
.base = STM32_TIM8_BASE,
- .irq = STM32_IRQ_TIM8,
+ .irq = STM32_IRQ_TIM8CC,
#ifdef USE_ADVENCED_TIM
- .irg_of = STM32_IRQ_TIM8UP,
+ .irq_of = STM32_IRQ_TIM8UP,
#endif
};
#endif
@@ -1173,7 +1173,7 @@ const struct stm32_cap_priv_s stm32_tim9_priv =
.base = STM32_TIM9_BASE,
.irq = STM32_IRQ_TIM9,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
@@ -1185,7 +1185,7 @@ const struct stm32_cap_priv_s stm32_tim10_priv =
.base = STM32_TIM10_BASE,
.irq = STM32_IRQ_TIM10,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
@@ -1197,7 +1197,7 @@ const struct stm32_cap_priv_s stm32_tim11_priv =
.base = STM32_TIM11_BASE,
.irq = STM32_IRQ_TIM11,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
@@ -1209,7 +1209,7 @@ const struct stm32_cap_priv_s stm32_tim12_priv =
.base = STM32_TIM12_BASE,
.irq = STM32_IRQ_TIM12,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
@@ -1221,7 +1221,7 @@ const struct stm32_cap_priv_s stm32_tim13_priv =
.base = STM32_TIM13_BASE,
.irq = STM32_IRQ_TIM13,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
@@ -1233,7 +1233,7 @@ const struct stm32_cap_priv_s stm32_tim14_priv =
.base = STM32_TIM14_BASE,
.irq = STM32_IRQ_TIM14,
#ifdef USE_ADVENCED_TIM
- .irg_of = 0,
+ .irq_of = 0,
#endif
};
#endif
--
GitLab
From 7e2aed942a3a87bebf8d613ac2114c1c351f0ec5 Mon Sep 17 00:00:00 2001
From: Pierre-noel Bouteville
Date: Fri, 3 Jun 2016 08:42:32 -0600
Subject: [PATCH 038/400] Correct conditioinal compilation in ST7565 driver
---
drivers/lcd/st7565.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/lcd/st7565.c b/drivers/lcd/st7565.c
index 6b4a1c0288..323fda4c73 100644
--- a/drivers/lcd/st7565.c
+++ b/drivers/lcd/st7565.c
@@ -1017,7 +1017,7 @@ FAR struct lcd_dev_s *st7565_initialize(FAR struct st7565_lcd_s *lcd,
/* Follow NHD-C12864KGZ DISPLAY INITIALIZATION... */
-#ifdef CONFIG_NHD_C12864KGZ
+#if defined(CONFIG_NHD_C12864KGZ)
(void)st7565_send_one_data(priv, ST7565_BIAS_1_9);
@@ -1027,7 +1027,7 @@ FAR struct lcd_dev_s *st7565_initialize(FAR struct st7565_lcd_s *lcd,
(void)st7565_send_one_data(priv, ST7565_POWERCTRL_INT);
(void)st7565_send_one_data(priv, ST7565_SETSTARTLINE);
-#elif CONFIG_ERC_12864_3
+#elif defined(CONFIG_ERC_12864_3)
(void)st7565_send_one_data(priv, ST7565_ADCNORMAL);
(void)st7565_send_one_data(priv, ST7565_SETCOMREVERSE);
--
GitLab
From 082d32226b582033daf565c9bddca3e600b31769 Mon Sep 17 00:00:00 2001
From: Pierre-noel Bouteville
Date: Fri, 3 Jun 2016 08:45:22 -0600
Subject: [PATCH 039/400] STM32 Timer Driver: Change calculation of per-timer
pre-scaler value
---
arch/arm/src/stm32/stm32_tim.c | 94 ++++++++++++++++++++++++++++++----
1 file changed, 84 insertions(+), 10 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c
index 14359625f8..26749a05b0 100644
--- a/arch/arm/src/stm32/stm32_tim.c
+++ b/arch/arm/src/stm32/stm32_tim.c
@@ -324,17 +324,91 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
return 0;
}
-#if STM32_NATIM > 0
- if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE ||
- ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE)
- {
- prescaler = STM32_TIM18_FREQUENCY / freq;
- }
- else
+ switch (((struct stm32_tim_priv_s *)dev)->base)
+ {
+#ifdef STM32_APB2_TIM1_CLKIN
+ case STM32_TIM1_BASE:
+ prescaler = STM32_APB2_TIM1_CLKIN / freq;
+ break;
#endif
- {
- prescaler = STM32_TIM27_FREQUENCY / freq;
- }
+#ifdef STM32_APB2_TIM2_CLKIN
+ case STM32_TIM2_BASE:
+ prescaler = STM32_APB2_TIM2_CLKIN / freq;
+ break;
+#endif
+#ifdef STM32_APB2_TIM3_CLKIN
+ case STM32_TIM3_BASE:
+ prescaler = STM32_APB2_TIM3_CLKIN / freq;
+ break;
+#endif
+#ifdef STM32_APB2_TIM4_CLKIN
+ case STM32_TIM4_BASE:
+ prescaler = STM32_APB2_TIM4_CLKIN / freq;
+ break;
+#endif
+#ifdef STM32_APB2_TIM5_CLKIN
+ case STM32_TIM5_BASE:
+ prescaler = STM32_APB2_TIM5_CLKIN / freq;
+ break;
+#endif
+#ifdef STM32_APB2_TIM6_CLKIN
+ case STM32_TIM6_BASE:
+ prescaler = STM32_APB2_TIM6_CLKIN / freq;
+ break;
+#endif
+#ifdef STM32_APB2_TIM7_CLKIN
+ case STM32_TIM7_BASE:
+ prescaler = STM32_APB2_TIM7_CLKIN / freq;
+ break;
+#endif
+#ifdef STM32_APB2_TIM8_CLKIN
+ case STM32_TIM8_BASE:
+ prescaler = STM32_APB2_TIM8_CLKIN / freq;
+ break;
+#endif
+#ifdef STM32_APB2_TIM9_CLKIN
+ case STM32_TIM9_BASE:
+ prescaler = STM32_APB2_TIM9_CLKIN / freq;
+ break;
+#endif
+#ifdef STM32_APB2_TIM10_CLKIN
+ case STM32_TIM10_BASE:
+ prescaler = STM32_APB2_TIM10_CLKIN / freq;
+ break;
+#endif
+#ifdef STM32_APB2_TIM11_CLKIN
+ case STM32_TIM11_BASE:
+ prescaler = STM32_APB2_TIM11_CLKIN / freq;
+ break;
+#endif
+#ifdef STM32_APB2_TIM12_CLKIN
+ case STM32_TIM12_BASE:
+ prescaler = STM32_APB2_TIM12_CLKIN / freq;
+ break;
+#endif
+#ifdef STM32_APB2_TIM13_CLKIN
+ case STM32_TIM13_BASE:
+ prescaler = STM32_APB2_TIM13_CLKIN / freq;
+ break;
+#endif
+#ifdef STM32_APB2_TIM14_CLKIN
+ case STM32_TIM14_BASE:
+ prescaler = STM32_APB2_TIM14_CLKIN / freq;
+ break;
+#endif
+#ifdef STM32_APB2_TIM15_CLKIN
+ case STM32_TIM15_BASE:
+ prescaler = STM32_APB2_TIM15_CLKIN / freq;
+ break;
+#endif
+#ifdef STM32_APB2_TIM16_CLKIN
+ case STM32_TIM16_BASE:
+ prescaler = STM32_APB2_TIM16_CLKIN / freq;
+ break;
+#endif
+ default:
+ return ERROR;
+ }
/* We need to decrement value for '1', but only, if we are allowed to
* not to cause underflow. Check for overflow.
--
GitLab
From d76d889efdc2cc375c24dfd66ac2bf9740a3ce71 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Fri, 3 Jun 2016 09:10:21 -0600
Subject: [PATCH 040/400] Restore FLASH_ERASALL in configurations where it was
previously selected
---
configs/mikroe-stm32f4/fulldemo/defconfig | 22 +++++++++++++++------
configs/mikroe-stm32f4/nsh/defconfig | 15 ++++++++++++++
configs/mikroe-stm32f4/usbnsh/defconfig | 15 ++++++++++++++
configs/stm32f429i-disco/extflash/defconfig | 15 ++++++++++++++
drivers/lcd/Kconfig | 2 +-
5 files changed, 62 insertions(+), 7 deletions(-)
diff --git a/configs/mikroe-stm32f4/fulldemo/defconfig b/configs/mikroe-stm32f4/fulldemo/defconfig
index 5d2ec9b165..60e6ec4584 100644
--- a/configs/mikroe-stm32f4/fulldemo/defconfig
+++ b/configs/mikroe-stm32f4/fulldemo/defconfig
@@ -454,10 +454,18 @@ CONFIG_STM32_SERIALDRIVER=y
#
# U[S]ART Configuration
#
+
+#
+# U[S]ART Device Configuration
+#
CONFIG_STM32_USART2_SERIALDRIVER=y
# CONFIG_STM32_USART2_1WIREDRIVER is not set
# CONFIG_USART2_RS485 is not set
# CONFIG_USART2_RXDMA is not set
+
+#
+# Serial Driver Configuration
+#
# CONFIG_SERIAL_DISABLE_REORDERING is not set
# CONFIG_STM32_FLOWCONTROL_BROKEN is not set
# CONFIG_STM32_USART_BREAKS is not set
@@ -753,10 +761,14 @@ CONFIG_INPUT=y
# CONFIG_DJOYSTICK is not set
# CONFIG_AJOYSTICK is not set
# CONFIG_IOEXPANDER is not set
+
+#
+# LCD Driver Support
+#
CONFIG_LCD=y
#
-# Common LCD Settings
+# Common Graphipc LCD Settings
#
# CONFIG_LCD_CONSOLE is not set
# CONFIG_LCD_NOGETRUN is not set
@@ -785,11 +797,7 @@ CONFIG_LCD_LANDSCAPE=y
# CONFIG_LCD_RLANDSCAPE is not set
# CONFIG_LCD_ILI9341 is not set
# CONFIG_LCD_RA8875 is not set
-
-#
-# Alphanumeric/Segment LCD Devices
-#
-# CONFIG_LCD_LCD1602 is not set
+# CONFIG_SLCD is not set
#
# LED Support
@@ -1353,6 +1361,7 @@ CONFIG_EXAMPLES_TOUCHSCREEN_ARCHINIT=y
#
# File System Utilities
#
+CONFIG_FSUTILS_FLASH_ERASEALL=y
# CONFIG_FSUTILS_INIFILE is not set
CONFIG_FSUTILS_MKSMARTFS=y
# CONFIG_FSUTILS_PASSWD is not set
@@ -1721,6 +1730,7 @@ CONFIG_MIKROE_STM32F4_CONFIGDATA_PART=y
# CONFIG_SYSTEM_FREE is not set
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
+CONFIG_SYSTEM_FLASH_ERASEALL=y
# CONFIG_SYSTEM_INSTALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
diff --git a/configs/mikroe-stm32f4/nsh/defconfig b/configs/mikroe-stm32f4/nsh/defconfig
index 9ef8a7e8e3..ddff8824cb 100644
--- a/configs/mikroe-stm32f4/nsh/defconfig
+++ b/configs/mikroe-stm32f4/nsh/defconfig
@@ -446,9 +446,17 @@ CONFIG_STM32_SERIALDRIVER=y
#
# U[S]ART Configuration
#
+
+#
+# U[S]ART Device Configuration
+#
CONFIG_STM32_USART2_SERIALDRIVER=y
# CONFIG_STM32_USART2_1WIREDRIVER is not set
# CONFIG_USART2_RS485 is not set
+
+#
+# Serial Driver Configuration
+#
# CONFIG_SERIAL_DISABLE_REORDERING is not set
# CONFIG_STM32_FLOWCONTROL_BROKEN is not set
# CONFIG_STM32_USART_BREAKS is not set
@@ -709,7 +717,12 @@ CONFIG_SPI_EXCHANGE=y
# CONFIG_BCH is not set
# CONFIG_INPUT is not set
# CONFIG_IOEXPANDER is not set
+
+#
+# LCD Driver Support
+#
# CONFIG_LCD is not set
+# CONFIG_SLCD is not set
#
# LED Support
@@ -1065,6 +1078,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
#
# File System Utilities
#
+CONFIG_FSUTILS_FLASH_ERASEALL=y
# CONFIG_FSUTILS_INIFILE is not set
CONFIG_FSUTILS_MKSMARTFS=y
# CONFIG_FSUTILS_PASSWD is not set
@@ -1217,6 +1231,7 @@ CONFIG_NSH_ARCHINIT=y
# CONFIG_SYSTEM_FREE is not set
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
+CONFIG_SYSTEM_FLASH_ERASEALL=y
# CONFIG_SYSTEM_INSTALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
diff --git a/configs/mikroe-stm32f4/usbnsh/defconfig b/configs/mikroe-stm32f4/usbnsh/defconfig
index 2ba9677ab6..aff176b9df 100644
--- a/configs/mikroe-stm32f4/usbnsh/defconfig
+++ b/configs/mikroe-stm32f4/usbnsh/defconfig
@@ -446,9 +446,17 @@ CONFIG_STM32_SERIALDRIVER=y
#
# U[S]ART Configuration
#
+
+#
+# U[S]ART Device Configuration
+#
CONFIG_STM32_USART2_SERIALDRIVER=y
# CONFIG_STM32_USART2_1WIREDRIVER is not set
# CONFIG_USART2_RS485 is not set
+
+#
+# Serial Driver Configuration
+#
# CONFIG_SERIAL_DISABLE_REORDERING is not set
# CONFIG_STM32_FLOWCONTROL_BROKEN is not set
# CONFIG_STM32_USART_BREAKS is not set
@@ -717,7 +725,12 @@ CONFIG_SPI_EXCHANGE=y
# CONFIG_BCH is not set
# CONFIG_INPUT is not set
# CONFIG_IOEXPANDER is not set
+
+#
+# LCD Driver Support
+#
# CONFIG_LCD is not set
+# CONFIG_SLCD is not set
#
# LED Support
@@ -1114,6 +1127,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
#
# File System Utilities
#
+CONFIG_FSUTILS_FLASH_ERASEALL=y
# CONFIG_FSUTILS_INIFILE is not set
CONFIG_FSUTILS_MKSMARTFS=y
# CONFIG_FSUTILS_PASSWD is not set
@@ -1267,6 +1281,7 @@ CONFIG_NSH_ARCHINIT=y
# CONFIG_SYSTEM_FREE is not set
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
+CONFIG_SYSTEM_FLASH_ERASEALL=y
# CONFIG_SYSTEM_INSTALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
diff --git a/configs/stm32f429i-disco/extflash/defconfig b/configs/stm32f429i-disco/extflash/defconfig
index 3fab3e076b..e277a69d2a 100644
--- a/configs/stm32f429i-disco/extflash/defconfig
+++ b/configs/stm32f429i-disco/extflash/defconfig
@@ -451,9 +451,17 @@ CONFIG_STM32_SERIALDRIVER=y
#
# U[S]ART Configuration
#
+
+#
+# U[S]ART Device Configuration
+#
CONFIG_STM32_USART1_SERIALDRIVER=y
# CONFIG_STM32_USART1_1WIREDRIVER is not set
# CONFIG_USART1_RS485 is not set
+
+#
+# Serial Driver Configuration
+#
# CONFIG_SERIAL_DISABLE_REORDERING is not set
# CONFIG_STM32_FLOWCONTROL_BROKEN is not set
# CONFIG_STM32_USART_BREAKS is not set
@@ -728,7 +736,12 @@ CONFIG_SPI_EXCHANGE=y
# CONFIG_BCH is not set
# CONFIG_INPUT is not set
# CONFIG_IOEXPANDER is not set
+
+#
+# LCD Driver Support
+#
# CONFIG_LCD is not set
+# CONFIG_SLCD is not set
#
# LED Support
@@ -1081,6 +1094,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
#
# File System Utilities
#
+CONFIG_FSUTILS_FLASH_ERASEALL=y
# CONFIG_FSUTILS_INIFILE is not set
CONFIG_FSUTILS_MKSMARTFS=y
# CONFIG_FSUTILS_PASSWD is not set
@@ -1231,6 +1245,7 @@ CONFIG_PLATFORM_CONFIGDATA=y
# CONFIG_SYSTEM_FREE is not set
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
+CONFIG_SYSTEM_FLASH_ERASEALL=y
# CONFIG_SYSTEM_INSTALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
diff --git a/drivers/lcd/Kconfig b/drivers/lcd/Kconfig
index 441e6fba26..97618eba04 100644
--- a/drivers/lcd/Kconfig
+++ b/drivers/lcd/Kconfig
@@ -19,7 +19,7 @@ menuconfig LCD
if LCD
-comment "Common Graphipc LCD Settings"
+comment "Common Graphic LCD Settings"
config LCD_CONSOLE
bool "LCD console output"
--
GitLab
From 82cd44dbc50f016af81e483c41bd1f011b0f5ae1 Mon Sep 17 00:00:00 2001
From: Lok Tep
Date: Fri, 3 Jun 2016 17:19:22 +0200
Subject: [PATCH 041/400] adc i2c_reset
---
.../stm32f7/chip/stm32f74xx75xx_memorymap.h | 4 ++++
arch/arm/src/stm32f7/stm32_i2c.c | 20 +++++++++++--------
configs/stm32f746-ws/include/board.h | 8 ++++++++
configs/stm32f746-ws/nsh/defconfig | 4 +++-
4 files changed, 27 insertions(+), 9 deletions(-)
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h
index 82a5d2242b..5949c83c3b 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h
+++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h
@@ -142,6 +142,10 @@
#define STM32_USART1_BASE 0x40011000 /* 0x40011000-0x400113ff: USART1 */
#define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff: USART6 */
#define STM32_ADC_BASE 0x40012000 /* 0x40012000-0x400123ff: ADC1 - ADC2 - ADC3 */
+# define STM32_ADC1_BASE 0x40012000 /* ADC1 */
+# define STM32_ADC2_BASE 0x40012100 /* ADC2 */
+# define STM32_ADC3_BASE 0x40012200 /* ADC3 */
+# define STM32_ADCCMN_BASE 0x40012300 /* Common */
#define STM32_SDMMC1_BASE 0x40012c00 /* 0x40012c00-0x40012fff: SDMMC1 */
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff: SPI1 */
#define STM32_SPI4_BASE 0x40013400 /* 0x40013400-0x400137ff: SPI4 */
diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c
index e5a9604294..4a769b08fa 100644
--- a/arch/arm/src/stm32f7/stm32_i2c.c
+++ b/arch/arm/src/stm32f7/stm32_i2c.c
@@ -273,10 +273,12 @@
# define CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32F7_I2CTIMEOTICKS)
#endif
-#define I2C_OUTPUT \
- (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | GPIO_MODE_50MHz)
-#define MKI2C_OUTPUT(p) \
- (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT)
+/* Macros to convert a I2C pin to a GPIO output */
+
+#define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\
+ GPIO_SPEED_50MHz | GPIO_OUTPUT_SET)
+
+#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT)
/* Register setting unique to the STM32F30xx */
@@ -483,7 +485,9 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
int count);
static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
int count);
-
+#ifdef CONFIG_I2C_RESET
+int stm32_i2c_reset(FAR struct i2c_master_s * dev);
+#endif
/************************************************************************************
* Private Data
@@ -582,7 +586,7 @@ struct i2c_ops_s stm32_i2c_ops =
{
.transfer = stm32_i2c_transfer
#ifdef CONFIG_I2C_RESET
- , .reset = stm32f7_i2c_reset
+ , .reset = stm32_i2c_reset
#endif
};
@@ -2576,7 +2580,7 @@ int stm32f7_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
}
/************************************************************************************
- * Name: up_i2creset
+ * Name: stm32_i2c_reset
*
* Description:
* Reset an I2C bus
@@ -2584,7 +2588,7 @@ int stm32f7_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
************************************************************************************/
#ifdef CONFIG_I2C_RESET
-int up_i2creset(FAR struct i2c_master_s * dev)
+int stm32_i2c_reset(FAR struct i2c_master_s * dev)
{
struct stm32_i2c_priv_s * priv;
unsigned int clock_count;
diff --git a/configs/stm32f746-ws/include/board.h b/configs/stm32f746-ws/include/board.h
index ca1b9ea2c7..1f5e3f030c 100644
--- a/configs/stm32f746-ws/include/board.h
+++ b/configs/stm32f746-ws/include/board.h
@@ -165,6 +165,14 @@
#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
+/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
+ * otherwise frequency is 2xAPBx.
+ * Note: TIM1,8 are on APB2, others on APB1
+ */
+
+#define STM32_TIM18_FREQUENCY (2*STM32_PCLK2_FREQUENCY)
+#define STM32_TIM27_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
+
/* FLASH wait states
*
* --------- ---------- -----------
diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig
index 7648c14777..4e3899a234 100644
--- a/configs/stm32f746-ws/nsh/defconfig
+++ b/configs/stm32f746-ws/nsh/defconfig
@@ -175,7 +175,7 @@ CONFIG_STM32F7_I2C=y
# CONFIG_STM32F7_SAI is not set
CONFIG_STM32F7_SPI=y
CONFIG_STM32F7_USART=y
-# CONFIG_STM32F7_ADC1 is not set
+CONFIG_STM32F7_ADC1=y
# CONFIG_STM32F7_ADC2 is not set
# CONFIG_STM32F7_ADC3 is not set
# CONFIG_STM32F7_BKPSRAM is not set
@@ -442,6 +442,7 @@ CONFIG_DEV_NULL=y
# CONFIG_PWM is not set
CONFIG_ARCH_HAVE_I2CRESET=y
CONFIG_I2C=y
+CONFIG_I2C_RESET=y
CONFIG_SPI=y
# CONFIG_SPI_SLAVE is not set
CONFIG_SPI_EXCHANGE=y
@@ -451,6 +452,7 @@ CONFIG_SPI_EXCHANGE=y
# CONFIG_SPI_HWFEATURES is not set
# CONFIG_SPI_CRCGENERATION is not set
# CONFIG_I2S is not set
+CONFIG_ADC=y
#
# Timer Driver Support
--
GitLab
From 88a41862b51d922e444c92b03c776cdd527ffe88 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Fri, 3 Jun 2016 09:41:17 -0600
Subject: [PATCH 042/400] Revert "STM32 Timer Driver: Change calculation of
per-timer pre-scaler value"
This reverts commit 082d32226b582033daf565c9bddca3e600b31769.
---
arch/arm/src/stm32/stm32_tim.c | 94 ++++------------------------------
1 file changed, 10 insertions(+), 84 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c
index 26749a05b0..14359625f8 100644
--- a/arch/arm/src/stm32/stm32_tim.c
+++ b/arch/arm/src/stm32/stm32_tim.c
@@ -324,91 +324,17 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
return 0;
}
- switch (((struct stm32_tim_priv_s *)dev)->base)
- {
-#ifdef STM32_APB2_TIM1_CLKIN
- case STM32_TIM1_BASE:
- prescaler = STM32_APB2_TIM1_CLKIN / freq;
- break;
-#endif
-#ifdef STM32_APB2_TIM2_CLKIN
- case STM32_TIM2_BASE:
- prescaler = STM32_APB2_TIM2_CLKIN / freq;
- break;
-#endif
-#ifdef STM32_APB2_TIM3_CLKIN
- case STM32_TIM3_BASE:
- prescaler = STM32_APB2_TIM3_CLKIN / freq;
- break;
-#endif
-#ifdef STM32_APB2_TIM4_CLKIN
- case STM32_TIM4_BASE:
- prescaler = STM32_APB2_TIM4_CLKIN / freq;
- break;
-#endif
-#ifdef STM32_APB2_TIM5_CLKIN
- case STM32_TIM5_BASE:
- prescaler = STM32_APB2_TIM5_CLKIN / freq;
- break;
-#endif
-#ifdef STM32_APB2_TIM6_CLKIN
- case STM32_TIM6_BASE:
- prescaler = STM32_APB2_TIM6_CLKIN / freq;
- break;
-#endif
-#ifdef STM32_APB2_TIM7_CLKIN
- case STM32_TIM7_BASE:
- prescaler = STM32_APB2_TIM7_CLKIN / freq;
- break;
-#endif
-#ifdef STM32_APB2_TIM8_CLKIN
- case STM32_TIM8_BASE:
- prescaler = STM32_APB2_TIM8_CLKIN / freq;
- break;
-#endif
-#ifdef STM32_APB2_TIM9_CLKIN
- case STM32_TIM9_BASE:
- prescaler = STM32_APB2_TIM9_CLKIN / freq;
- break;
-#endif
-#ifdef STM32_APB2_TIM10_CLKIN
- case STM32_TIM10_BASE:
- prescaler = STM32_APB2_TIM10_CLKIN / freq;
- break;
-#endif
-#ifdef STM32_APB2_TIM11_CLKIN
- case STM32_TIM11_BASE:
- prescaler = STM32_APB2_TIM11_CLKIN / freq;
- break;
-#endif
-#ifdef STM32_APB2_TIM12_CLKIN
- case STM32_TIM12_BASE:
- prescaler = STM32_APB2_TIM12_CLKIN / freq;
- break;
-#endif
-#ifdef STM32_APB2_TIM13_CLKIN
- case STM32_TIM13_BASE:
- prescaler = STM32_APB2_TIM13_CLKIN / freq;
- break;
-#endif
-#ifdef STM32_APB2_TIM14_CLKIN
- case STM32_TIM14_BASE:
- prescaler = STM32_APB2_TIM14_CLKIN / freq;
- break;
-#endif
-#ifdef STM32_APB2_TIM15_CLKIN
- case STM32_TIM15_BASE:
- prescaler = STM32_APB2_TIM15_CLKIN / freq;
- break;
-#endif
-#ifdef STM32_APB2_TIM16_CLKIN
- case STM32_TIM16_BASE:
- prescaler = STM32_APB2_TIM16_CLKIN / freq;
- break;
+#if STM32_NATIM > 0
+ if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE ||
+ ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE)
+ {
+ prescaler = STM32_TIM18_FREQUENCY / freq;
+ }
+ else
#endif
- default:
- return ERROR;
- }
+ {
+ prescaler = STM32_TIM27_FREQUENCY / freq;
+ }
/* We need to decrement value for '1', but only, if we are allowed to
* not to cause underflow. Check for overflow.
--
GitLab
From 910bac65fadff4841de7f5e583c119d7b76d592b Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Fri, 3 Jun 2016 11:38:59 -0600
Subject: [PATCH 043/400] STM32 Timer: Generalize and extend calculation of
per-timer pre-scaler value. Inspired by original proposal from Pierre-noel
Bouteville.
---
arch/arm/src/stm32/stm32_dac.c | 2 +-
arch/arm/src/stm32/stm32_tim.c | 125 ++++++++++++++++--
configs/fire-stm32v2/include/board.h | 12 +-
configs/hymini-stm32v/include/board.h | 13 +-
configs/maple/include/board.h | 12 +-
configs/mikroe-stm32f4/include/board.h | 12 +-
configs/nucleo-f303re/include/board.h | 12 +-
configs/nucleo-f4x1re/include/board.h | 2 +-
configs/nucleo-f4x1re/include/nucleo-f401re.h | 12 +-
configs/nucleo-f4x1re/include/nucleo-f411re.h | 12 +-
configs/olimex-stm32-h405/include/board.h | 12 +-
configs/olimex-stm32-h407/include/board.h | 10 +-
configs/olimex-stm32-p207/include/board.h | 12 +-
configs/olimexino-stm32/include/board.h | 12 +-
configs/spark/include/board.h | 12 +-
configs/stm3210e-eval/include/board.h | 13 +-
configs/stm3220g-eval/include/board.h | 13 +-
configs/stm3240g-eval/include/board.h | 12 +-
configs/stm32_tiny/include/board.h | 13 +-
configs/stm32f103-minimum/include/board.h | 10 +-
configs/stm32f3discovery/include/board.h | 13 +-
configs/stm32f411e-disco/include/board.h | 10 +-
configs/stm32f429i-disco/include/board.h | 12 +-
configs/stm32f4discovery/include/board.h | 10 +-
configs/stm32vldiscovery/include/board.h | 12 +-
.../include/board-stm32f103vct6.h | 12 +-
configs/viewtool-stm32f107/include/board.h | 2 +-
27 files changed, 322 insertions(+), 82 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_dac.c b/arch/arm/src/stm32/stm32_dac.c
index 77213af264..4c1a985c32 100644
--- a/arch/arm/src/stm32/stm32_dac.c
+++ b/arch/arm/src/stm32/stm32_dac.c
@@ -848,7 +848,7 @@ static int dac_timinit(FAR struct stm32_chan_s *chan)
case 8:
regaddr = STM32_RCC_APB2ENR;
setbits = RCC_APB2ENR_TIM8EN;
- pclk = STM32_TIM18_FREQUENCY;
+ pclk = BOARD_TIM8_FREQUENCY;
break;
#endif
default:
diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c
index 14359625f8..b7015c39ce 100644
--- a/arch/arm/src/stm32/stm32_tim.c
+++ b/arch/arm/src/stm32/stm32_tim.c
@@ -312,6 +312,7 @@ static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode)
static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
{
+ uint32_t freqin;
int prescaler;
ASSERT(dev);
@@ -324,20 +325,122 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
return 0;
}
-#if STM32_NATIM > 0
- if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE ||
- ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE)
+ /* Get the input clock frequency for this timer. These vary with
+ * different timer clock sources, MCU-specific timer configuration, and
+ * board-specific clock configuration. The correct input clock frequency
+ * must be defined in the board.h header file.
+ */
+
+ switch (((struct stm32_tim_priv_s *)dev)->base)
{
- prescaler = STM32_TIM18_FREQUENCY / freq;
- }
- else
+#if defined(CONFIG_STM32_TIM1) && defined(BOARD_TIM1_FREQUENCY)
+ case STM32_TIM1_BASE:
+ freqin = BOARD_TIM1_FREQUENCY;
+ break;
#endif
- {
- prescaler = STM32_TIM27_FREQUENCY / freq;
+
+#if defined(CONFIG_STM32_TIM2) && defined(BOARD_TIM2_FREQUENCY)
+ case STM32_TIM2_BASE:
+ freqin = BOARD_TIM2_FREQUENCY;
+ break;
+#endif
+
+#if defined(CONFIG_STM32_TIM3) && defined(BOARD_TIM3_FREQUENCY)
+ case STM32_TIM3_BASE:
+ freqin = BOARD_TIM3_FREQUENCY;
+ break;
+#endif
+
+#if defined(CONFIG_STM32_TIM4) && defined(BOARD_TIM4_FREQUENCY)
+ case STM32_TIM4_BASE:
+ freqin = BOARD_TIM4_FREQUENCY;
+ break;
+#endif
+
+#if defined(CONFIG_STM32_TIM5) && defined(BOARD_TIM5_FREQUENCY)
+ case STM32_TIM5_BASE:
+ freqin = BOARD_TIM5_FREQUENCY;
+ break;
+#endif
+
+#if defined(CONFIG_STM32_TIM6) && defined(BOARD_TIM6_FREQUENCY)
+ case STM32_TIM6_BASE:
+ freqin = BOARD_TIM6_FREQUENCY;
+ break;
+#endif
+
+#if defined(CONFIG_STM32_TIM7) && defined(BOARD_TIM7_FREQUENCY)
+ case STM32_TIM7_BASE:
+ freqin = BOARD_TIM7_FREQUENCY;
+ break;
+#endif
+
+#if defined(CONFIG_STM32_TIM8) && defined(BOARD_TIM8_FREQUENCY)
+ case STM32_TIM8_BASE:
+ freqin = BOARD_TIM8_FREQUENCY;
+ break;
+#endif
+
+#if defined(CONFIG_STM32_TIM9) && defined(BOARD_TIM9_FREQUENCY)
+ case STM32_TIM9_BASE:
+ freqin = BOARD_TIM9_FREQUENCY;
+ break;
+#endif
+
+#if defined(CONFIG_STM32_TIM10) && defined(BOARD_TIM10_FREQUENCY)
+ case STM32_TIM10_BASE:
+ freqin = BOARD_TIM10_FREQUENCY;
+ break;
+#endif
+
+#if defined(CONFIG_STM32_TIM11) && defined(BOARD_TIM11_FREQUENCY)
+ case STM32_TIM11_BASE:
+ freqin = BOARD_TIM11_FREQUENCY;
+ break;
+#endif
+
+#if defined(CONFIG_STM32_TIM12) && defined(BOARD_TIM12_FREQUENCY)
+ case STM32_TIM12_BASE:
+ freqin = BOARD_TIM12_FREQUENCY;
+ break;
+#endif
+
+#if defined(CONFIG_STM32_TIM13) && defined(BOARD_TIM13_FREQUENCY)
+ case STM32_TIM13_BASE:
+ freqin = BOARD_TIM13_FREQUENCY;
+ break;
+#endif
+
+#if defined(CONFIG_STM32_TIM14) && defined(BOARD_TIM14_FREQUENCY)
+ case STM32_TIM14_BASE:
+ freqin = BOARD_TIM14_FREQUENCY;
+ break;
+#endif
+
+#if defined(CONFIG_STM32_TIM15) && defined(BOARD_TIM15_FREQUENCY)
+ case STM32_TIM15_BASE:
+ freqin = BOARD_TIM15_FREQUENCY;
+ break;
+#endif
+
+#if defined(CONFIG_STM32_TIM16) && defined(BOARD_TIM16_FREQUENCY)
+ case STM32_TIM16_BASE:
+ freqin = BOARD_TIM8_FREQUENCY;
+ break;
+#endif
+
+ default:
+ return -EINVAL;
}
- /* We need to decrement value for '1', but only, if we are allowed to
- * not to cause underflow. Check for overflow.
+ /* Select a pre-scaler value for this timer using the input clock
+ * frequency.
+ */
+
+ prescaler = freqin / freq;
+
+ /* We need to decrement value for '1', but only, if that will not to
+ * cause underflow.
*/
if (prescaler > 0)
@@ -345,6 +448,8 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
prescaler--;
}
+ /* Check for overflow as well. */
+
if (prescaler > 0xffff)
{
prescaler = 0xffff;
diff --git a/configs/fire-stm32v2/include/board.h b/configs/fire-stm32v2/include/board.h
index 880ea6d6c7..013833d1b5 100644
--- a/configs/fire-stm32v2/include/board.h
+++ b/configs/fire-stm32v2/include/board.h
@@ -2,7 +2,7 @@
* configs/fire-stm32v2/include/board.h
* include/arch/board/board.h
*
- * Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -120,8 +120,14 @@
* otherwise frequency is 2xAPBx.
* Note: TIM1,8 are on APB2, others on APB1 */
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
diff --git a/configs/hymini-stm32v/include/board.h b/configs/hymini-stm32v/include/board.h
index ba55bdecdf..1625b0d5e0 100644
--- a/configs/hymini-stm32v/include/board.h
+++ b/configs/hymini-stm32v/include/board.h
@@ -1,9 +1,10 @@
/************************************************************************************
* configs/hymini-stm32v/include/board.h
- * include/arch/board/board.h
*
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2011 Laurent Latil. All rights reserved.
* Author: Laurent Latil
+ * Gregory Nutt
*
* Derives, in part, from configs/stm3210e-eval/include/board.h
*
@@ -115,8 +116,14 @@
* otherwise frequency is 2xAPBx.
* Note: TIM1,8 are on APB2, others on APB1 */
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
diff --git a/configs/maple/include/board.h b/configs/maple/include/board.h
index 8b4da7dd35..ab347f9c7e 100644
--- a/configs/maple/include/board.h
+++ b/configs/maple/include/board.h
@@ -2,7 +2,7 @@
* configs/maple/include/board.h
* include/arch/board/board.h
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt
* Librae
*
@@ -111,8 +111,14 @@
* otherwise frequency is 2xAPBx.
* Note: TIM1,8 are on APB2, others on APB1 */
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
diff --git a/configs/mikroe-stm32f4/include/board.h b/configs/mikroe-stm32f4/include/board.h
index 796b6a62b4..a985f31e50 100644
--- a/configs/mikroe-stm32f4/include/board.h
+++ b/configs/mikroe-stm32f4/include/board.h
@@ -2,7 +2,7 @@
* configs/mikroe-stm32f4/include/board.h
* include/arch/board/board.h
*
- * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012-2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -154,8 +154,14 @@
* Note: TIM1,8 are on APB2, others on APB1
*/
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY (STM32_HCLK_FREQUENCY/2)
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* LED definitions ******************************************************************/
/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any
diff --git a/configs/nucleo-f303re/include/board.h b/configs/nucleo-f303re/include/board.h
index c645b46b80..bc35c80338 100644
--- a/configs/nucleo-f303re/include/board.h
+++ b/configs/nucleo-f303re/include/board.h
@@ -2,7 +2,7 @@
* configs/nucleo-f303re/include/board.h
* include/arch/board/board.h
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved.
* Authors: Gregory Nutt
* Paul Alexander Patience
@@ -154,8 +154,14 @@
* Note: TIM1,8 are on APB2, others on APB1
*/
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY (STM32_HCLK_FREQUENCY/2)
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* LED definitions **********************************************************/
/* The Nucleo F303RE board has three LEDs. Two of these are controlled by
diff --git a/configs/nucleo-f4x1re/include/board.h b/configs/nucleo-f4x1re/include/board.h
index cd6db041bd..8580b8045a 100644
--- a/configs/nucleo-f4x1re/include/board.h
+++ b/configs/nucleo-f4x1re/include/board.h
@@ -1,7 +1,7 @@
/************************************************************************************
* configs/nucleo-f4x1re/include/board.h
*
- * Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
diff --git a/configs/nucleo-f4x1re/include/nucleo-f401re.h b/configs/nucleo-f4x1re/include/nucleo-f401re.h
index 581c154e70..1460f5c3cc 100644
--- a/configs/nucleo-f4x1re/include/nucleo-f401re.h
+++ b/configs/nucleo-f4x1re/include/nucleo-f401re.h
@@ -1,7 +1,7 @@
/************************************************************************************
* configs/nucleo-f4x1re/include/nucleo-f401re.h
*
- * Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -168,8 +168,14 @@
*/
/* REVISIT */
-#define STM32_TIM18_FREQUENCY (2*STM32_PCLK2_FREQUENCY)
-#define STM32_TIM27_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY)
+#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY)
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
diff --git a/configs/nucleo-f4x1re/include/nucleo-f411re.h b/configs/nucleo-f4x1re/include/nucleo-f411re.h
index 84018f7d4b..1d6908bae5 100644
--- a/configs/nucleo-f4x1re/include/nucleo-f411re.h
+++ b/configs/nucleo-f4x1re/include/nucleo-f411re.h
@@ -1,7 +1,7 @@
/************************************************************************************
* configs/nucleo-f4x1re/include/nucleo-f411re.h
*
- * Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -164,8 +164,14 @@
*/
/* REVISIT */
-#define STM32_TIM18_FREQUENCY (2*STM32_PCLK2_FREQUENCY)
-#define STM32_TIM27_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY)
+#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY)
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
diff --git a/configs/olimex-stm32-h405/include/board.h b/configs/olimex-stm32-h405/include/board.h
index 462d34751d..86d98da3fa 100644
--- a/configs/olimex-stm32-h405/include/board.h
+++ b/configs/olimex-stm32-h405/include/board.h
@@ -1,7 +1,7 @@
/************************************************************************************
* configs/olimex-stm32-h405/include/board.h
*
- * Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -129,8 +129,14 @@
* Note: TIM1,8 are on APB2, others on APB1
*/
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* LED definitions ******************************************************************/
/* If CONFIG_ARCH_LEDS is not defined, then the user can control the status LED in any
diff --git a/configs/olimex-stm32-h407/include/board.h b/configs/olimex-stm32-h407/include/board.h
index a116f5bb65..9418619164 100644
--- a/configs/olimex-stm32-h407/include/board.h
+++ b/configs/olimex-stm32-h407/include/board.h
@@ -164,8 +164,14 @@
* Note: TIM1,8 are on APB2, others on APB1
*/
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
diff --git a/configs/olimex-stm32-p207/include/board.h b/configs/olimex-stm32-p207/include/board.h
index c000536905..62cb143755 100644
--- a/configs/olimex-stm32-p207/include/board.h
+++ b/configs/olimex-stm32-p207/include/board.h
@@ -1,7 +1,7 @@
/************************************************************************************
* configs/olimex-stm32-p207/include/board.h
*
- * Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009, 2012, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -129,8 +129,14 @@
* Note: TIM1,8 are on APB2, others on APB1
*/
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* LED definitions ******************************************************************/
/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any
diff --git a/configs/olimexino-stm32/include/board.h b/configs/olimexino-stm32/include/board.h
index ac695f9710..3455c3d8ab 100644
--- a/configs/olimexino-stm32/include/board.h
+++ b/configs/olimexino-stm32/include/board.h
@@ -1,7 +1,7 @@
/************************************************************************************
* configs/olimexino-stm32/include/board.h
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
* David Sidrane
*
@@ -119,8 +119,14 @@
* otherwise frequency is 2xAPBx.
* Note: TIM1,8 are on APB2, others on APB1 */
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* Buttons *************************************************************************/
diff --git a/configs/spark/include/board.h b/configs/spark/include/board.h
index 197f53ebb8..4464e8ad5c 100644
--- a/configs/spark/include/board.h
+++ b/configs/spark/include/board.h
@@ -2,7 +2,7 @@
* configs/spark/include/board.h
* include/arch/board/board.h
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt
* Librae
*
@@ -115,8 +115,14 @@
* otherwise frequency is 2xAPBx.
* Note: TIM1,8 are on APB2, others on APB1 */
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
diff --git a/configs/stm3210e-eval/include/board.h b/configs/stm3210e-eval/include/board.h
index 462d07ca53..fcefa160fa 100644
--- a/configs/stm3210e-eval/include/board.h
+++ b/configs/stm3210e-eval/include/board.h
@@ -1,8 +1,7 @@
/************************************************************************************
* configs/stm3210e-eval/include/board.h
- * include/arch/board/board.h
*
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -111,8 +110,14 @@
* otherwise frequency is 2xAPBx.
* Note: TIM1,8 are on APB2, others on APB1 */
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
diff --git a/configs/stm3220g-eval/include/board.h b/configs/stm3220g-eval/include/board.h
index d8dad32f74..74d2b5bea7 100644
--- a/configs/stm3220g-eval/include/board.h
+++ b/configs/stm3220g-eval/include/board.h
@@ -1,8 +1,7 @@
/************************************************************************************
* configs/stm3220g-eval/include/board.h
- * include/arch/board/board.h
*
- * Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -162,8 +161,14 @@
* Note: TIM1,8 are on APB2, others on APB1
*/
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
diff --git a/configs/stm3240g-eval/include/board.h b/configs/stm3240g-eval/include/board.h
index d693bdacf6..674d58000e 100644
--- a/configs/stm3240g-eval/include/board.h
+++ b/configs/stm3240g-eval/include/board.h
@@ -2,7 +2,7 @@
* configs/stm3240g-eval/include/board.h
* include/arch/board/board.h
*
- * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -161,8 +161,14 @@
* Note: TIM1,8 are on APB2, others on APB1
*/
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
diff --git a/configs/stm32_tiny/include/board.h b/configs/stm32_tiny/include/board.h
index d393437c50..b4e3e6c8aa 100644
--- a/configs/stm32_tiny/include/board.h
+++ b/configs/stm32_tiny/include/board.h
@@ -1,8 +1,7 @@
/************************************************************************************
* configs/stm32_tiny/include/board.h
- * include/arch/board/board.h
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt
* Laurent Latil
*
@@ -111,8 +110,14 @@
* otherwise frequency is 2xAPBx.
* Note: TIM1,8 are on APB2, others on APB1 */
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
diff --git a/configs/stm32f103-minimum/include/board.h b/configs/stm32f103-minimum/include/board.h
index 8c5385e45b..27e958abb1 100644
--- a/configs/stm32f103-minimum/include/board.h
+++ b/configs/stm32f103-minimum/include/board.h
@@ -110,8 +110,14 @@
* otherwise frequency is 2xAPBx.
* Note: TIM1,8 are on APB2, others on APB1 */
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
diff --git a/configs/stm32f3discovery/include/board.h b/configs/stm32f3discovery/include/board.h
index e1fd1ed2a3..0f57dad336 100644
--- a/configs/stm32f3discovery/include/board.h
+++ b/configs/stm32f3discovery/include/board.h
@@ -1,8 +1,7 @@
/************************************************************************************
* configs/stm32f3discovery/include/board.h
- * include/arch/board/board.h
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -150,8 +149,14 @@
* Note: TIM1,8 are on APB2, others on APB1
*/
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY (STM32_HCLK_FREQUENCY/2)
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* LED definitions ******************************************************************/
/* The STM32F3Discovery board has ten LEDs. Two of these are controlled by logic on
diff --git a/configs/stm32f411e-disco/include/board.h b/configs/stm32f411e-disco/include/board.h
index 46d2df971e..a50e2d3a53 100644
--- a/configs/stm32f411e-disco/include/board.h
+++ b/configs/stm32f411e-disco/include/board.h
@@ -163,8 +163,14 @@
*/
/* REVISIT */
-#define STM32_TIM18_FREQUENCY (2*STM32_PCLK2_FREQUENCY)
-#define STM32_TIM27_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM1_FREQUENCY (2 * STM32_PCLK2_FREQUENCY)
+#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY)
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
diff --git a/configs/stm32f429i-disco/include/board.h b/configs/stm32f429i-disco/include/board.h
index adcd72adde..723b398492 100644
--- a/configs/stm32f429i-disco/include/board.h
+++ b/configs/stm32f429i-disco/include/board.h
@@ -2,7 +2,7 @@
* configs/stm32f429i-disco/include/board.h
* include/arch/board/board.h
*
- * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -154,8 +154,14 @@
* Note: TIM1,8 are on APB2, others on APB1
*/
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY (STM32_HCLK_FREQUENCY/2)
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
+#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY/2)
+#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY/2)
+#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY/2)
+#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY/2)
+#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY/2)
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* LED definitions ******************************************************************/
/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any
diff --git a/configs/stm32f4discovery/include/board.h b/configs/stm32f4discovery/include/board.h
index 2ab3c99132..10cc583ab0 100644
--- a/configs/stm32f4discovery/include/board.h
+++ b/configs/stm32f4discovery/include/board.h
@@ -156,8 +156,14 @@
* Note: TIM1,8 are on APB2, others on APB1
*/
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY (STM32_HCLK_FREQUENCY/2)
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
diff --git a/configs/stm32vldiscovery/include/board.h b/configs/stm32vldiscovery/include/board.h
index efbb3f3e8c..19e167309d 100644
--- a/configs/stm32vldiscovery/include/board.h
+++ b/configs/stm32vldiscovery/include/board.h
@@ -1,7 +1,7 @@
/************************************************************************************
* configs/stm32vldiscovery/include/board.h
*
- * Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
* Freddie Chopin
*
@@ -110,8 +110,14 @@
* otherwise frequency is 2xAPBx.
* Note: TIM1,15-17 are on APB2, others on APB1 */
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* LED definitions ******************************************************************/
diff --git a/configs/viewtool-stm32f107/include/board-stm32f103vct6.h b/configs/viewtool-stm32f107/include/board-stm32f103vct6.h
index 54731ecf72..39cc30a49f 100644
--- a/configs/viewtool-stm32f107/include/board-stm32f103vct6.h
+++ b/configs/viewtool-stm32f107/include/board-stm32f103vct6.h
@@ -1,7 +1,7 @@
/************************************************************************************
* configs/viewtool-stm32f107/include/board-stm32f103vct6.h
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -113,8 +113,14 @@
* otherwise frequency is 2xAPBx.
* Note: TIM1,8 are on APB2, others on APB1 */
-#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
-#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
+#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/************************************************************************************
* Public Data
diff --git a/configs/viewtool-stm32f107/include/board.h b/configs/viewtool-stm32f107/include/board.h
index 242feeb67a..2fea6a29da 100644
--- a/configs/viewtool-stm32f107/include/board.h
+++ b/configs/viewtool-stm32f107/include/board.h
@@ -1,7 +1,7 @@
/************************************************************************************
* configs/viewtool-stm32f107/include/board.h
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
--
GitLab
From c11e923ad4fb9a5d391e5180fc9b04952d21eb9b Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Fri, 3 Jun 2016 12:11:55 -0600
Subject: [PATCH 044/400] Fix a cut'n'paste error left from last commit.
---
arch/arm/src/stm32/stm32_tim.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c
index b7015c39ce..39175a4e64 100644
--- a/arch/arm/src/stm32/stm32_tim.c
+++ b/arch/arm/src/stm32/stm32_tim.c
@@ -425,7 +425,7 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
#if defined(CONFIG_STM32_TIM16) && defined(BOARD_TIM16_FREQUENCY)
case STM32_TIM16_BASE:
- freqin = BOARD_TIM8_FREQUENCY;
+ freqin = BOARD_TIM16_FREQUENCY;
break;
#endif
--
GitLab
From 282edefab3deb43fad630d45e47f77bd2f91cd8a Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Fri, 3 Jun 2016 13:51:43 -0600
Subject: [PATCH 045/400] STM32 TIM: Add hooks for all previously unsupported
timers. Also fix some PWM warnings.
---
arch/arm/src/stm32/stm32_pwm.c | 4 +
arch/arm/src/stm32/stm32_tim.c | 642 ++++++++++++++++++++++++++++-----
2 files changed, 558 insertions(+), 88 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c
index 76783804ea..06d6b2b080 100644
--- a/arch/arm/src/stm32/stm32_pwm.c
+++ b/arch/arm/src/stm32/stm32_pwm.c
@@ -1903,6 +1903,8 @@ static void pwm_set_apb_clock(FAR struct stm32_pwmtimer_s *priv, bool on)
en_bit = RCC_APB2ENR_TIM17EN;
break;
#endif
+ default:
+ return;
}
/* Enable/disable APB 1/2 clock for timer */
@@ -2219,6 +2221,8 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
resetbit = RCC_APB2RSTR_TIM17RST;
break;
#endif
+ default:
+ return -EINVAL;
}
/* Reset the timer - stopping the output and putting the timer back
diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c
index 39175a4e64..f427267c52 100644
--- a/arch/arm/src/stm32/stm32_tim.c
+++ b/arch/arm/src/stm32/stm32_tim.c
@@ -144,6 +144,14 @@
defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE)
# undef CONFIG_STM32_TIM14
#endif
+#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \
+ defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE)
+# undef CONFIG_STM32_TIM15
+#endif
+#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \
+ defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE)
+# undef CONFIG_STM32_TIM16
+#endif
#if defined(CONFIG_STM32_TIM1)
# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\
@@ -187,14 +195,74 @@
#endif
#endif
+#if defined(CONFIG_STM32_TIM9)
+# if defined(GPIO_TIM9_CH1OUT) ||defined(GPIO_TIM9_CH2OUT)||\
+ defined(GPIO_TIM9_CH3OUT) ||defined(GPIO_TIM9_CH4OUT)
+# define HAVE_TIM9_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32_TIM10)
+# if defined(GPIO_TIM10_CH1OUT) ||defined(GPIO_TIM10_CH2OUT)||\
+ defined(GPIO_TIM10_CH3OUT) ||defined(GPIO_TIM10_CH4OUT)
+# define HAVE_TIM10_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32_TIM11)
+# if defined(GPIO_TIM11_CH1OUT) ||defined(GPIO_TIM11_CH2OUT)||\
+ defined(GPIO_TIM11_CH3OUT) ||defined(GPIO_TIM11_CH4OUT)
+# define HAVE_TIM11_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32_TIM12)
+# if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT)||\
+ defined(GPIO_TIM12_CH3OUT) ||defined(GPIO_TIM12_CH4OUT)
+# define HAVE_TIM12_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32_TIM13)
+# if defined(GPIO_TIM13_CH1OUT) ||defined(GPIO_TIM13_CH2OUT)||\
+ defined(GPIO_TIM13_CH3OUT) ||defined(GPIO_TIM13_CH4OUT)
+# define HAVE_TIM13_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32_TIM14)
+# if defined(GPIO_TIM14_CH1OUT) ||defined(GPIO_TIM14_CH2OUT)||\
+ defined(GPIO_TIM14_CH3OUT) ||defined(GPIO_TIM14_CH4OUT)
+# define HAVE_TIM14_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32_TIM15)
+# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\
+ defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT)
+# define HAVE_TIM15_GPIOCONFIG 1
+#endif
+#endif
+
+#if defined(CONFIG_STM32_TIM16)
+# if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\
+ defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT)
+# define HAVE_TIM16_GPIOCONFIG 1
+#endif
+#endif
/* This module then only compiles if there are enabled timers that are not intended for
* some other purpose.
*/
-#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM3) || \
- defined(CONFIG_STM32_TIM4) || defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
- defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8)
+#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \
+ defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \
+ defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
+ defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \
+ defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \
+ defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \
+ defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14) || \
+ defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16)
/************************************************************************************
* Private Types
@@ -479,6 +547,11 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
switch (((struct stm32_tim_priv_s *)dev)->base)
{
+#ifdef CONFIG_STM32_TIM1
+ case STM32_TIM1_BASE:
+ vectorno = STM32_IRQ_TIM1UP;
+ break;
+#endif
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
vectorno = STM32_IRQ_TIM2;
@@ -499,36 +572,64 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
vectorno = STM32_IRQ_TIM5;
break;
#endif
-#if STM32_NBTIM > 0
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
vectorno = STM32_IRQ_TIM6;
break;
#endif
-#endif
-#if STM32_NBTIM > 1
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
vectorno = STM32_IRQ_TIM7;
break;
#endif
-#endif
-#if STM32_NATIM > 0
- /* TODO: add support for multiple sources and callbacks */
-
-#ifdef CONFIG_STM32_TIM1
- case STM32_TIM1_BASE:
- vectorno = STM32_IRQ_TIM1UP;
- break;
-#endif
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
vectorno = STM32_IRQ_TIM8UP;
break;
#endif
+#ifdef CONFIG_STM32_TIM9
+ case STM32_TIM9_BASE:
+ vectorno = STM32_IRQ_TIM9;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM10
+ case STM32_TIM10_BASE:
+ vectorno = STM32_IRQ_TIM10;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM11
+ case STM32_TIM11_BASE:
+ vectorno = STM32_IRQ_TIM11;
+ break;
#endif
+#ifdef CONFIG_STM32_TIM12
+ case STM32_TIM12_BASE:
+ vectorno = STM32_IRQ_TIM12;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM13
+ case STM32_TIM13_BASE:
+ vectorno = STM32_IRQ_TIM13;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM14
+ case STM32_TIM14_BASE:
+ vectorno = STM32_IRQ_TIM14;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM15
+ case STM32_TIM15_BASE:
+ vectorno = STM32_IRQ_TIM15;
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM16
+ case STM32_TIM16_BASE:
+ vectorno = STM32_IRQ_TIM16;
+ break;
+#endif
+
default:
- return ERROR;
+ return -EINVAL;
}
/* Disable interrupt when callback is removed */
@@ -594,7 +695,7 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m
#if STM32_NBTIM > 0
)
{
- return ERROR;
+ return -EINVAL;
}
#endif
@@ -622,7 +723,7 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m
break;
default:
- return ERROR;
+ return -EINVAL;
}
stm32_tim_reload_counter(dev);
@@ -656,7 +757,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
if (--channel > 4)
{
- return ERROR;
+ return -EINVAL;
}
/* Assume that channel is disabled and polarity is active high */
@@ -676,7 +777,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
#if STM32_NBTIM > 0
)
{
- return ERROR;
+ return -EINVAL;
}
#endif
@@ -693,7 +794,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
break;
default:
- return ERROR;
+ return -EINVAL;
}
/* Set polarity */
@@ -726,6 +827,31 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
switch (((struct stm32_tim_priv_s *)dev)->base)
{
+#ifdef CONFIG_STM32_TIM1
+ case STM32_TIM1_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM1_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break;
+#endif
+#if defined(GPIO_TIM1_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break;
+#endif
+#if defined(GPIO_TIM1_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break;
+#endif
+#if defined(GPIO_TIM1_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break;
+#endif
+ default:
+ return -EINVAL;
+ }
+ break;
+#endif
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
switch (channel)
@@ -751,7 +877,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
break;
#endif
default:
- return ERROR;
+ return -EINVAL;
}
break;
#endif
@@ -780,7 +906,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
break;
#endif
default:
- return ERROR;
+ return -EINVAL;
}
break;
#endif
@@ -809,7 +935,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
break;
#endif
default:
- return ERROR;
+ return -EINVAL;
}
break;
#endif
@@ -838,65 +964,269 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
break;
#endif
default:
- return ERROR;
+ return -EINVAL;
}
break;
#endif
-
-#if STM32_NATIM > 0
-#ifdef CONFIG_STM32_TIM1
- case STM32_TIM1_BASE:
+#ifdef CONFIG_STM32_TIM8
+ case STM32_TIM8_BASE:
switch (channel)
{
-#if defined(GPIO_TIM1_CH1OUT)
+#if defined(GPIO_TIM8_CH1OUT)
case 0:
- stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break;
+ stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break;
#endif
-#if defined(GPIO_TIM1_CH2OUT)
+#if defined(GPIO_TIM8_CH2OUT)
case 1:
- stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break;
+ stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break;
#endif
-#if defined(GPIO_TIM1_CH3OUT)
+#if defined(GPIO_TIM8_CH3OUT)
case 2:
- stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break;
+ stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break;
#endif
-#if defined(GPIO_TIM1_CH4OUT)
+#if defined(GPIO_TIM8_CH4OUT)
case 3:
- stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break;
+ stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break;
#endif
default:
- return ERROR;
+ return -EINVAL;
}
break;
#endif
-#ifdef CONFIG_STM32_TIM8
- case STM32_TIM8_BASE:
+#ifdef CONFIG_STM32_TIM9
+ case STM32_TIM9_BASE:
switch (channel)
{
-#if defined(GPIO_TIM8_CH1OUT)
+#if defined(GPIO_TIM9_CH1OUT)
case 0:
- stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break;
+ stm32_tim_gpioconfig(GPIO_TIM9_CH1OUT, mode);
+ break;
#endif
-#if defined(GPIO_TIM8_CH2OUT)
+#if defined(GPIO_TIM9_CH2OUT)
case 1:
- stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break;
+ stm32_tim_gpioconfig(GPIO_TIM9_CH2OUT, mode);
+ break;
#endif
-#if defined(GPIO_TIM8_CH3OUT)
+#if defined(GPIO_TIM9_CH3OUT)
case 2:
- stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break;
+ stm32_tim_gpioconfig(GPIO_TIM9_CH3OUT, mode);
+ break;
#endif
-#if defined(GPIO_TIM8_CH4OUT)
+#if defined(GPIO_TIM9_CH4OUT)
case 3:
- stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break;
+ stm32_tim_gpioconfig(GPIO_TIM9_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM10
+ case STM32_TIM10_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM10_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM10_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM10_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM10_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM10_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM10_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM10_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM10_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM11
+ case STM32_TIM11_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM11_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM11_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM11_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM11_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM11_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM11_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM11_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM11_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM12
+ case STM32_TIM12_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM12_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM12_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM12_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM12_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM12_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM12_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM12_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM12_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM13
+ case STM32_TIM13_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM13_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM13_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM13_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM13_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM13_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM13_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM13_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM13_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM14
+ case STM32_TIM14_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM14_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM14_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM14_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM14_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM14_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM14_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM14_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM14_CH4OUT, mode);
+ break;
#endif
default:
- return ERROR;
+ return -EINVAL;
}
break;
#endif
+#ifdef CONFIG_STM32_TIM15
+ case STM32_TIM15_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM15_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM15_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM15_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM15_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM16
+ case STM32_TIM16_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM16_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM16_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM16_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM16_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+ break;
#endif
default:
- return ERROR;
+ return -EINVAL;
}
return OK;
@@ -922,7 +1252,7 @@ static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel
stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare);
break;
default:
- return ERROR;
+ return -EINVAL;
}
return OK;
}
@@ -943,7 +1273,7 @@ static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel
return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET);
}
- return ERROR;
+ return -EINVAL;
}
/************************************************************************************
@@ -970,6 +1300,14 @@ struct stm32_tim_ops_s stm32_tim_ops =
.ackint = &stm32_tim_ackint
};
+#ifdef CONFIG_STM32_TIM1
+struct stm32_tim_priv_s stm32_tim1_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM1_BASE,
+};
+#endif
#ifdef CONFIG_STM32_TIM2
struct stm32_tim_priv_s stm32_tim2_priv =
{
@@ -1006,7 +1344,6 @@ struct stm32_tim_priv_s stm32_tim5_priv =
};
#endif
-#if STM32_NBTIM > 0
#ifdef CONFIG_STM32_TIM6
struct stm32_tim_priv_s stm32_tim6_priv =
{
@@ -1015,9 +1352,7 @@ struct stm32_tim_priv_s stm32_tim6_priv =
.base = STM32_TIM6_BASE,
};
#endif
-#endif
-#if STM32_NBTIM > 1
#ifdef CONFIG_STM32_TIM7
struct stm32_tim_priv_s stm32_tim7_priv =
{
@@ -1026,28 +1361,86 @@ struct stm32_tim_priv_s stm32_tim7_priv =
.base = STM32_TIM7_BASE,
};
#endif
+
+#ifdef CONFIG_STM32_TIM8
+struct stm32_tim_priv_s stm32_tim8_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM8_BASE,
+};
#endif
-#if STM32_NATIM > 0
+#ifdef CONFIG_STM32_TIM9
+struct stm32_tim_priv_s stm32_tim9_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM9_BASE,
+};
+#endif
-#ifdef CONFIG_STM32_TIM1
-struct stm32_tim_priv_s stm32_tim1_priv =
+#ifdef CONFIG_STM32_TIM10
+struct stm32_tim_priv_s stm32_tim10_priv =
{
.ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED,
- .base = STM32_TIM1_BASE,
+ .base = STM32_TIM10_BASE,
};
#endif
-#ifdef CONFIG_STM32_TIM8
-struct stm32_tim_priv_s stm32_tim8_priv =
+#ifdef CONFIG_STM32_TIM11
+struct stm32_tim_priv_s stm32_tim11_priv =
{
.ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED,
- .base = STM32_TIM8_BASE,
+ .base = STM32_TIM11_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32_TIM12
+struct stm32_tim_priv_s stm32_tim12_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM12_BASE,
};
#endif
+#ifdef CONFIG_STM32_TIM13
+struct stm32_tim_priv_s stm32_tim13_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM13_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32_TIM14
+struct stm32_tim_priv_s stm32_tim14_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM14_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32_TIM15
+struct stm32_tim_priv_s stm32_tim15_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM15_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32_TIM16
+struct stm32_tim_priv_s stm32_tim16_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM16_BASE,
+};
#endif
/************************************************************************************
@@ -1062,6 +1455,12 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer)
switch (timer)
{
+#ifdef CONFIG_STM32_TIM1
+ case 1:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv;
+ modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
+ break;
+#endif
#ifdef CONFIG_STM32_TIM2
case 2:
dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv;
@@ -1086,37 +1485,71 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer)
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN);
break;
#endif
-
-#if STM32_NBTIM > 0
#ifdef CONFIG_STM32_TIM6
case 6:
dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN);
break;
#endif
-#endif
-#if STM32_NBTIM > 1
#ifdef CONFIG_STM32_TIM7
case 7:
dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN);
break;
#endif
-#endif
-
-#if STM32_NATIM > 0
-#ifdef CONFIG_STM32_TIM1
- case 1:
- dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv;
- modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
- break;
-#endif
#ifdef CONFIG_STM32_TIM8
case 8:
dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
break;
#endif
+#ifdef CONFIG_STM32_TIM9
+ case 9:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim9_priv;
+ modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM9EN);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM10
+ case 10:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim10_priv;
+ modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM10EN);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM11
+ case 11:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim11_priv;
+ modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM11EN);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM12
+ case 12:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv;
+ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM13
+ case 13:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv;
+ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM14
+ case 14:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv;
+ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM14EN);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM15
+ case 15:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv;
+ modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM16
+ case 16:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv;
+ modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN);
+ break;
#endif
default:
return NULL;
@@ -1144,6 +1577,11 @@ int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
switch (((struct stm32_tim_priv_s *)dev)->base)
{
+#ifdef CONFIG_STM32_TIM1
+ case STM32_TIM1_BASE:
+ modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
+ break;
+#endif
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0);
@@ -1164,35 +1602,63 @@ int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0);
break;
#endif
-#if STM32_NBTIM > 0
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0);
break;
#endif
-#endif
-#if STM32_NBTIM > 1
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0);
break;
#endif
-#endif
-
-#if STM32_NATIM > 0
-#ifdef CONFIG_STM32_TIM1
- case STM32_TIM1_BASE:
- modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
- break;
-#endif
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0);
break;
#endif
+#ifdef CONFIG_STM32_TIM9
+ case STM32_TIM9_BASE:
+ modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM9EN, 0);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM10
+ case STM32_TIM10_BASE:
+ modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM10EN, 0);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM11
+ case STM32_TIM11_BASE:
+ modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM11EN, 0);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM12
+ case STM32_TIM12_BASE:
+ modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM13
+ case STM32_TIM13_BASE:
+ modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM14
+ case STM32_TIM14_BASE:
+ modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM14EN, 0);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM15
+ case STM32_TIM15_BASE:
+ modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0);
+ break;
+#endif
+#ifdef CONFIG_STM32_TIM16
+ case STM32_TIM16_BASE:
+ modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0);
+ break;
#endif
default:
- return ERROR;
+ return -EINVAL;
}
/* Mark it as free */
@@ -1202,4 +1668,4 @@ int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
return OK;
}
-#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM8) */
+#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM16) */
--
GitLab
From 3ec2386be8511333711ff3f0ba2912e61fb723df Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Fri, 3 Jun 2016 14:08:28 -0600
Subject: [PATCH 046/400] STM32 TIM: There is a TIM17 on some parts too
---
arch/arm/src/stm32/stm32_tim.c | 104 ++++++++++++++++++++++++++++-----
1 file changed, 88 insertions(+), 16 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c
index f427267c52..99b43144fe 100644
--- a/arch/arm/src/stm32/stm32_tim.c
+++ b/arch/arm/src/stm32/stm32_tim.c
@@ -152,105 +152,116 @@
defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE)
# undef CONFIG_STM32_TIM16
#endif
+#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \
+ defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE)
+# undef CONFIG_STM32_TIM17
+#endif
-#if defined(CONFIG_STM32_TIM1)
+#if defined(CONFIG_STM32_TIM1)
# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\
defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)
# define HAVE_TIM1_GPIOCONFIG 1
#endif
#endif
-#if defined(CONFIG_STM32_TIM2)
+#if defined(CONFIG_STM32_TIM2)
# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\
defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT)
# define HAVE_TIM2_GPIOCONFIG 1
#endif
#endif
-#if defined(CONFIG_STM32_TIM3)
+#if defined(CONFIG_STM32_TIM3)
# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\
defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT)
# define HAVE_TIM3_GPIOCONFIG 1
#endif
#endif
-#if defined(CONFIG_STM32_TIM4)
+#if defined(CONFIG_STM32_TIM4)
# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\
defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT)
# define HAVE_TIM4_GPIOCONFIG 1
#endif
#endif
-#if defined(CONFIG_STM32_TIM5)
+#if defined(CONFIG_STM32_TIM5)
# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\
defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT)
# define HAVE_TIM5_GPIOCONFIG 1
#endif
#endif
-#if defined(CONFIG_STM32_TIM8)
+#if defined(CONFIG_STM32_TIM8)
# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\
defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)
# define HAVE_TIM8_GPIOCONFIG 1
#endif
#endif
-#if defined(CONFIG_STM32_TIM9)
+#if defined(CONFIG_STM32_TIM9)
# if defined(GPIO_TIM9_CH1OUT) ||defined(GPIO_TIM9_CH2OUT)||\
defined(GPIO_TIM9_CH3OUT) ||defined(GPIO_TIM9_CH4OUT)
# define HAVE_TIM9_GPIOCONFIG 1
#endif
#endif
-#if defined(CONFIG_STM32_TIM10)
+#if defined(CONFIG_STM32_TIM10)
# if defined(GPIO_TIM10_CH1OUT) ||defined(GPIO_TIM10_CH2OUT)||\
defined(GPIO_TIM10_CH3OUT) ||defined(GPIO_TIM10_CH4OUT)
# define HAVE_TIM10_GPIOCONFIG 1
#endif
#endif
-#if defined(CONFIG_STM32_TIM11)
+#if defined(CONFIG_STM32_TIM11)
# if defined(GPIO_TIM11_CH1OUT) ||defined(GPIO_TIM11_CH2OUT)||\
defined(GPIO_TIM11_CH3OUT) ||defined(GPIO_TIM11_CH4OUT)
# define HAVE_TIM11_GPIOCONFIG 1
#endif
#endif
-#if defined(CONFIG_STM32_TIM12)
+#if defined(CONFIG_STM32_TIM12)
# if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT)||\
defined(GPIO_TIM12_CH3OUT) ||defined(GPIO_TIM12_CH4OUT)
# define HAVE_TIM12_GPIOCONFIG 1
#endif
#endif
-#if defined(CONFIG_STM32_TIM13)
+#if defined(CONFIG_STM32_TIM13)
# if defined(GPIO_TIM13_CH1OUT) ||defined(GPIO_TIM13_CH2OUT)||\
defined(GPIO_TIM13_CH3OUT) ||defined(GPIO_TIM13_CH4OUT)
# define HAVE_TIM13_GPIOCONFIG 1
#endif
#endif
-#if defined(CONFIG_STM32_TIM14)
+#if defined(CONFIG_STM32_TIM14)
# if defined(GPIO_TIM14_CH1OUT) ||defined(GPIO_TIM14_CH2OUT)||\
defined(GPIO_TIM14_CH3OUT) ||defined(GPIO_TIM14_CH4OUT)
# define HAVE_TIM14_GPIOCONFIG 1
#endif
#endif
-#if defined(CONFIG_STM32_TIM15)
+#if defined(CONFIG_STM32_TIM15)
# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\
defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT)
# define HAVE_TIM15_GPIOCONFIG 1
#endif
#endif
-#if defined(CONFIG_STM32_TIM16)
+#if defined(CONFIG_STM32_TIM16)
# if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\
defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT)
# define HAVE_TIM16_GPIOCONFIG 1
#endif
#endif
+#if defined(CONFIG_STM32_TIM17)
+# if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\
+ defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT)
+# define HAVE_TIM17_GPIOCONFIG 1
+#endif
+#endif
+
/* This module then only compiles if there are enabled timers that are not intended for
* some other purpose.
*/
@@ -262,7 +273,8 @@
defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \
defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \
defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14) || \
- defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16)
+ defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \
+ defined(CONFIG_STM32_TIM17)
/************************************************************************************
* Private Types
@@ -497,6 +509,12 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
break;
#endif
+#if defined(CONFIG_STM32_TIM17) && defined(BOARD_TIM17_FREQUENCY)
+ case STM32_TIM17_BASE:
+ freqin = BOARD_TIM17_FREQUENCY;
+ break;
+#endif
+
default:
return -EINVAL;
}
@@ -627,6 +645,11 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
vectorno = STM32_IRQ_TIM16;
break;
#endif
+#ifdef CONFIG_STM32_TIM17
+ case STM32_TIM17_BASE:
+ vectorno = STM32_IRQ_TIM17;
+ break;
+#endif
default:
return -EINVAL;
@@ -1224,6 +1247,35 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
return -EINVAL;
}
break;
+#endif
+#ifdef CONFIG_STM32_TIM17
+ case STM32_TIM17_BASE:
+ switch (channel)
+ {
+#if defined(GPIO_TIM17_CH1OUT)
+ case 0:
+ stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM17_CH2OUT)
+ case 1:
+ stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM17_CH3OUT)
+ case 2:
+ stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode);
+ break;
+#endif
+#if defined(GPIO_TIM17_CH4OUT)
+ case 3:
+ stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode);
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+ break;
#endif
default:
return -EINVAL;
@@ -1443,6 +1495,15 @@ struct stm32_tim_priv_s stm32_tim16_priv =
};
#endif
+#ifdef CONFIG_STM32_TIM17
+struct stm32_tim_priv_s stm32_tim17_priv =
+{
+ .ops = &stm32_tim_ops,
+ .mode = STM32_TIM_MODE_UNUSED,
+ .base = STM32_TIM17_BASE,
+};
+#endif
+
/************************************************************************************
* Public Function - Initialization
************************************************************************************/
@@ -1550,6 +1611,12 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer)
dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN);
break;
+#endif
+#ifdef CONFIG_STM32_TIM17
+ case 17:
+ dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv;
+ modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN);
+ break;
#endif
default:
return NULL;
@@ -1656,6 +1723,11 @@ int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
case STM32_TIM16_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0);
break;
+#endif
+#ifdef CONFIG_STM32_TIM17
+ case STM32_TIM17_BASE:
+ modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0);
+ break;
#endif
default:
return -EINVAL;
@@ -1668,4 +1740,4 @@ int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
return OK;
}
-#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM16) */
+#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */
--
GitLab
From 704fadb0e6d2c961f1658a7157aac11763a17fa9 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Fri, 3 Jun 2016 14:17:18 -0600
Subject: [PATCH 047/400] STM32 TIM: Assure that a compilation error will occur
if the old timer input clock frequency definitions are used
---
arch/arm/src/stm32/stm32_tim.c | 50 ++++++++++++----------------------
1 file changed, 17 insertions(+), 33 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c
index 99b43144fe..f4c7d57210 100644
--- a/arch/arm/src/stm32/stm32_tim.c
+++ b/arch/arm/src/stm32/stm32_tim.c
@@ -413,103 +413,87 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
switch (((struct stm32_tim_priv_s *)dev)->base)
{
-#if defined(CONFIG_STM32_TIM1) && defined(BOARD_TIM1_FREQUENCY)
+#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
freqin = BOARD_TIM1_FREQUENCY;
break;
#endif
-
-#if defined(CONFIG_STM32_TIM2) && defined(BOARD_TIM2_FREQUENCY)
+#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
freqin = BOARD_TIM2_FREQUENCY;
break;
#endif
-
-#if defined(CONFIG_STM32_TIM3) && defined(BOARD_TIM3_FREQUENCY)
+#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
freqin = BOARD_TIM3_FREQUENCY;
break;
#endif
-
-#if defined(CONFIG_STM32_TIM4) && defined(BOARD_TIM4_FREQUENCY)
+#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
freqin = BOARD_TIM4_FREQUENCY;
break;
#endif
-
-#if defined(CONFIG_STM32_TIM5) && defined(BOARD_TIM5_FREQUENCY)
+#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
freqin = BOARD_TIM5_FREQUENCY;
break;
#endif
-
-#if defined(CONFIG_STM32_TIM6) && defined(BOARD_TIM6_FREQUENCY)
+#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
freqin = BOARD_TIM6_FREQUENCY;
break;
#endif
-
-#if defined(CONFIG_STM32_TIM7) && defined(BOARD_TIM7_FREQUENCY)
+#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
freqin = BOARD_TIM7_FREQUENCY;
break;
#endif
-
-#if defined(CONFIG_STM32_TIM8) && defined(BOARD_TIM8_FREQUENCY)
+#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
freqin = BOARD_TIM8_FREQUENCY;
break;
#endif
-
-#if defined(CONFIG_STM32_TIM9) && defined(BOARD_TIM9_FREQUENCY)
+#ifdef CONFIG_STM32_TIM9
case STM32_TIM9_BASE:
freqin = BOARD_TIM9_FREQUENCY;
break;
#endif
-
-#if defined(CONFIG_STM32_TIM10) && defined(BOARD_TIM10_FREQUENCY)
+#ifdef CONFIG_STM32_TIM10
case STM32_TIM10_BASE:
freqin = BOARD_TIM10_FREQUENCY;
break;
#endif
-
-#if defined(CONFIG_STM32_TIM11) && defined(BOARD_TIM11_FREQUENCY)
+#ifdef CONFIG_STM32_TIM11
case STM32_TIM11_BASE:
freqin = BOARD_TIM11_FREQUENCY;
break;
#endif
-
-#if defined(CONFIG_STM32_TIM12) && defined(BOARD_TIM12_FREQUENCY)
+#ifdef CONFIG_STM32_TIM12
case STM32_TIM12_BASE:
freqin = BOARD_TIM12_FREQUENCY;
break;
#endif
-
-#if defined(CONFIG_STM32_TIM13) && defined(BOARD_TIM13_FREQUENCY)
+#ifdef CONFIG_STM32_TIM13
case STM32_TIM13_BASE:
freqin = BOARD_TIM13_FREQUENCY;
break;
#endif
-
-#if defined(CONFIG_STM32_TIM14) && defined(BOARD_TIM14_FREQUENCY)
+#ifdef CONFIG_STM32_TIM14
case STM32_TIM14_BASE:
freqin = BOARD_TIM14_FREQUENCY;
break;
#endif
-
-#if defined(CONFIG_STM32_TIM15) && defined(BOARD_TIM15_FREQUENCY)
+#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
freqin = BOARD_TIM15_FREQUENCY;
break;
#endif
-
-#if defined(CONFIG_STM32_TIM16) && defined(BOARD_TIM16_FREQUENCY)
+#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
freqin = BOARD_TIM16_FREQUENCY;
break;
#endif
-
-#if defined(CONFIG_STM32_TIM17) && defined(BOARD_TIM17_FREQUENCY)
+#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
freqin = BOARD_TIM17_FREQUENCY;
break;
--
GitLab
From 34df98d97e9f7b7c5faf5139a41b134e0797f320 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Fri, 3 Jun 2016 14:49:05 -0600
Subject: [PATCH 048/400] Use DEBUG assertions to save space
---
arch/arm/src/stm32/stm32_tim.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c
index f4c7d57210..62e2783e3a 100644
--- a/arch/arm/src/stm32/stm32_tim.c
+++ b/arch/arm/src/stm32/stm32_tim.c
@@ -395,7 +395,7 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
uint32_t freqin;
int prescaler;
- ASSERT(dev);
+ DEBUGASSERT(dev != NULL);
/* Disable Timer? */
@@ -534,7 +534,7 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev,
uint32_t period)
{
- ASSERT(dev);
+ DEBUGASSERT(dev != NULL);
stm32_putreg32(dev, STM32_BTIM_ARR_OFFSET, period);
}
@@ -544,8 +544,8 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
{
int vectorno;
- ASSERT(dev);
- ASSERT(source == 0);
+ DEBUGASSERT(dev != NULL);
+ DEBUGASSERT(source == 0);
switch (((struct stm32_tim_priv_s *)dev)->base)
{
@@ -664,13 +664,13 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source)
{
- ASSERT(dev);
+ DEBUGASSERT(dev != NULL);
stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, 0, ATIM_DIER_UIE);
}
static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source)
{
- ASSERT(dev);
+ DEBUGASSERT(dev != NULL);
stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0);
}
@@ -687,7 +687,7 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m
{
uint16_t val = ATIM_CR1_CEN | ATIM_CR1_ARPE;
- ASSERT(dev);
+ DEBUGASSERT(dev != NULL);
/* This function is not supported on basic timers. To enable or
* disable it, simply set its clock to valid frequency or zero.
@@ -758,7 +758,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET);
uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET;
- ASSERT(dev);
+ DEBUGASSERT(dev != NULL);
/* Further we use range as 0..3; if channel=0 it will also overflow here */
@@ -1271,7 +1271,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
uint32_t compare)
{
- ASSERT(dev);
+ DEBUGASSERT(dev != NULL);
switch (channel)
{
@@ -1295,7 +1295,7 @@ static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel
static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel)
{
- ASSERT(dev);
+ DEBUGASSERT(dev != NULL);
switch (channel)
{
@@ -1622,7 +1622,7 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer)
int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
{
- ASSERT(dev);
+ DEBUGASSERT(dev != NULL);
/* Disable power */
--
GitLab
From 774e7f9865397633f0f80c2936cdde52fadac32b Mon Sep 17 00:00:00 2001
From: v01d
Date: Sat, 4 Jun 2016 00:28:53 -0300
Subject: [PATCH 049/400] lpc43 GPIO Interrupts enabled and fixed (not all
cases tested)
---
arch/arm/src/lpc43xx/Kconfig | 7 +++++++
arch/arm/src/lpc43xx/lpc43_gpio.c | 4 ++++
arch/arm/src/lpc43xx/lpc43_gpio.h | 12 ++++++------
arch/arm/src/lpc43xx/lpc43_gpioint.c | 29 +++++++++++++++++++++++++++-
arch/arm/src/lpc43xx/lpc43_gpioint.h | 16 +++++++++++++++
5 files changed, 61 insertions(+), 7 deletions(-)
diff --git a/arch/arm/src/lpc43xx/Kconfig b/arch/arm/src/lpc43xx/Kconfig
index 5b7d730151..c6df85ae35 100644
--- a/arch/arm/src/lpc43xx/Kconfig
+++ b/arch/arm/src/lpc43xx/Kconfig
@@ -150,6 +150,13 @@ endchoice # LPC43XX Boot Configuration
menu "LPC43xx Peripheral Support"
+
+config GPIO_IRQ
+ bool "GPIO interrupt support"
+ default n
+ ---help---
+ Enable support for GPIO interrupts
+
config LPC43_ADC0
bool "ADC0"
default n
diff --git a/arch/arm/src/lpc43xx/lpc43_gpio.c b/arch/arm/src/lpc43xx/lpc43_gpio.c
index 3d5db11b7e..49b7f9b27f 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpio.c
+++ b/arch/arm/src/lpc43xx/lpc43_gpio.c
@@ -49,6 +49,10 @@
#include "up_arch.h"
#include "lpc43_gpio.h"
+#ifdef CONFIG_GPIO_IRQ
+#include "lpc43_gpioint.h"
+#endif
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
diff --git a/arch/arm/src/lpc43xx/lpc43_gpio.h b/arch/arm/src/lpc43xx/lpc43_gpio.h
index 1ee14fac63..4f16c841de 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpio.h
+++ b/arch/arm/src/lpc43xx/lpc43_gpio.h
@@ -143,7 +143,7 @@
* ..CC C... .... ....
*/
-#define GPIO_PININT_SHIFT (10) /* Bits 11-13: Pin interrupt number */
+#define GPIO_PININT_SHIFT (11) /* Bits 11-13: Pin interrupt number */
#define GPIO_PININT_MASK (7 << GPIO_PININT_SHIFT)
# define GPIO_PININT0 (0 << GPIO_PININT_SHIFT)
# define GPIO_PININT1 (1 << GPIO_PININT_SHIFT)
@@ -162,9 +162,9 @@
* .... .III .... ....
*/
-#define _GPIO_INT_LEVEL (1 << 10) /* Bit 10: 1=Level (vs edge) */
-#define _GPIO_INT_HIGH (1 << 9) /* Bit 9: 1=High level or rising edge */
-#define _GPIO_INT_LOW (1 << 8) /* Bit 8: 1=Low level or falling edge */
+#define _GPIO_INT_EDGE (1 << 10) /* Bit 10: 1=Edge (vs level) */
+#define _GPIO_INT_LOW (1 << 9) /* Bit 9: 1=Low level or falling edge */
+#define _GPIO_INT_HIGH (1 << 8) /* Bit 8: 1=High level or rising edge */
#define GPIO_INT_SHIFT (8) /* Bits 8-10: Interrupt mode */
#define GPIO_INT_MASK (7 << GPIO_INT_SHIFT)
@@ -176,8 +176,8 @@
#define GPIO_IS_ACTIVE_HI(p) (((p) & _GPIO_INT_HIGH) != 0)
#define GPIO_IS_ACTIVE_LOW(p) (((p) & _GPIO_INT_LOW) != 0)
-#define GPIO_IS_EDGE(p) (((p) & _GPIO_INT_LEVEL) == 0)
-#define GPIO_IS_LEVEL(p) (((p) & _GPIO_INT_LEVEL) != 0)
+#define GPIO_IS_LEVEL(p) (((p) & _GPIO_INT_EDGE) == 0)
+#define GPIO_IS_EDGE(p) (((p) & _GPIO_INT_EDGE) != 0)
/* GPIO Port Number:
*
diff --git a/arch/arm/src/lpc43xx/lpc43_gpioint.c b/arch/arm/src/lpc43xx/lpc43_gpioint.c
index 51e010ba33..029e2aec20 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpioint.c
+++ b/arch/arm/src/lpc43xx/lpc43_gpioint.c
@@ -57,6 +57,7 @@
#include
#include
+#include
#include
@@ -176,7 +177,7 @@ int lpc43_gpioint_grpinitialize(int group, bool anded, bool level)
int lpc43_gpioint_pinconfig(uint16_t gpiocfg)
{
unsigned int port = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
- unsigned int pin = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
+ unsigned int pin = ((gpiocfg & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
unsigned int pinint = ((gpiocfg & GPIO_PININT_MASK) >> GPIO_PININT_SHIFT);
uint32_t bitmask = (1 << pinint);
uint32_t regval;
@@ -227,6 +228,8 @@ int lpc43_gpioint_pinconfig(uint16_t gpiocfg)
/* Configure the active high level or rising edge */
+ /* TODO: this works for edge sensitive, but not level sensitive, active level is only controlled in IENF */
+
regval = getreg32(LPC43_GPIOINT_IENR);
if (GPIO_IS_ACTIVE_HI(gpiocfg))
{
@@ -321,4 +324,28 @@ int lpc43_gpioint_grpconfig(uint16_t gpiocfg)
return OK;
}
+/****************************************************************************
+ * Name: lpc43_gpioint_ack
+ *
+ * Description:
+ * Acknowledge the interrupt for a given pint interrupt number. Call this
+ * inside the interrupt handler. For edge sensitive interrupts, the interrupt
+ * status is cleared. For level sensitive interrupts, the active-high/-low
+ * sensitivity is inverted.
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int lpc43_gpioint_ack(uint8_t intnumber)
+{
+ uint32_t regval;
+
+ regval = getreg32(LPC43_GPIOINT_IST);
+ regval |= (1 << intnumber);
+ putreg32(regval, LPC43_GPIOINT_IST);
+ return OK;
+}
+
#endif /* CONFIG_GPIO_IRQ */
diff --git a/arch/arm/src/lpc43xx/lpc43_gpioint.h b/arch/arm/src/lpc43xx/lpc43_gpioint.h
index 35b22f7c7f..ec34649455 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpioint.h
+++ b/arch/arm/src/lpc43xx/lpc43_gpioint.h
@@ -136,5 +136,21 @@ int lpc43_gpioint_pinconfig(uint16_t gpiocfg);
int lpc43_gpioint_grpconfig(uint16_t gpiocfg);
+/****************************************************************************
+ * Name: lpc43_gpioint_ack
+ *
+ * Description:
+ * Acknowledge the interrupt for a given pint interrupt number. Call this
+ * inside the interrupt handler. For edge sensitive interrupts, the interrupt
+ * status is cleared. For level sensitive interrupts, the active-high/-low
+ * sensitivity is inverted.
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int lpc43_gpioint_ack(uint8_t intnumber);
+
#endif /* CONFIG_GPIO_IRQ */
#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_GPIOINT_H */
--
GitLab
From 37e8536a88639aa6e2bd854a7d66da83990331ee Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Sat, 4 Jun 2016 07:11:05 -0600
Subject: [PATCH 050/400] STM32: Put timer selections in a separate menu
---
arch/arm/src/stm32/Kconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig
index fc5eb833b5..c871fdf30c 100644
--- a/arch/arm/src/stm32/Kconfig
+++ b/arch/arm/src/stm32/Kconfig
@@ -2532,6 +2532,8 @@ config STM32_FSMC_SRAM
---help---
In addition to internal SRAM, SRAM may also be available through the FSMC.
+menu "Timer Configuration"
+
config STM32_TIM1_PWM
bool "TIM1 PWM"
default n
@@ -5299,6 +5301,8 @@ config STM32_TIM14_CAP
Timer devices may be used for different purposes. One special purpose is
to capture input.
+endmenu # Timer Configuration
+
menu "ADC Configuration"
depends on STM32_ADC
--
GitLab
From 86cfcfd58ab0edd044fa967c11484bc4251ecd25 Mon Sep 17 00:00:00 2001
From: Alan Carvalho de Assis
Date: Sat, 4 Jun 2016 07:22:45 -0600
Subject: [PATCH 051/400] Add the up_getc() function to STM32 in order to
support the minnsh configuration.
---
arch/arm/src/stm32/Make.defs | 8 +-
arch/arm/src/stm32/stm32.h | 1 +
arch/arm/src/stm32/stm32_lowgetc.c | 117 +++++++++++++++++++++++++++++
arch/arm/src/stm32/stm32_lowgetc.h | 47 ++++++++++++
4 files changed, 169 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/src/stm32/stm32_lowgetc.c
create mode 100644 arch/arm/src/stm32/stm32_lowgetc.h
diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs
index 98c1bad646..2cc901fb2c 100644
--- a/arch/arm/src/stm32/Make.defs
+++ b/arch/arm/src/stm32/Make.defs
@@ -109,10 +109,10 @@ endif
CHIP_ASRCS =
CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c
-CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c stm32_irq.c
-CHIP_CSRCS += stm32_dma.c stm32_lowputc.c stm32_serial.c stm32_spi.c
-CHIP_CSRCS += stm32_sdio.c stm32_tim.c stm32_waste.c stm32_ccm.c stm32_uid.c
-CHIP_CSRCS += stm32_capture.c
+CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c
+CHIP_CSRCS += stm32_irq.c stm32_dma.c stm32_lowputc.c stm32_lowgetc.c
+CHIP_CSRCS += stm32_serial.c stm32_spi.c stm32_sdio.c stm32_tim.c
+CHIP_CSRCS += stm32_waste.c stm32_ccm.c stm32_uid.c stm32_capture.c
ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += stm32_tim_lowerhalf.c
diff --git a/arch/arm/src/stm32/stm32.h b/arch/arm/src/stm32/stm32.h
index ee5a6497f8..8e75e4e9d7 100644
--- a/arch/arm/src/stm32/stm32.h
+++ b/arch/arm/src/stm32/stm32.h
@@ -92,6 +92,7 @@
#include "stm32_usbdev.h"
#include "stm32_wdg.h"
#include "stm32_lowputc.h"
+#include "stm32_lowgetc.h"
#include "stm32_eth.h"
#endif /* __ARCH_ARM_SRC_STM32_STM32_H */
diff --git a/arch/arm/src/stm32/stm32_lowgetc.c b/arch/arm/src/stm32/stm32_lowgetc.c
new file mode 100644
index 0000000000..4e080b828a
--- /dev/null
+++ b/arch/arm/src/stm32/stm32_lowgetc.c
@@ -0,0 +1,117 @@
+/****************************************************************************
+ * arch/arm/src/stm32/stm32_lowgetc.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+
+#include
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+
+#include "stm32.h"
+#include "stm32_rcc.h"
+#include "stm32_gpio.h"
+#include "stm32_uart.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Select U[S]ART console base address */
+
+#ifdef HAVE_CONSOLE
+# if defined(CONFIG_USART1_SERIAL_CONSOLE)
+# define STM32_CONSOLE_BASE STM32_USART1_BASE
+# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
+# define STM32_CONSOLE_BASE STM32_USART2_BASE
+# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
+# define STM32_CONSOLE_BASE STM32_USART3_BASE
+# elif defined(CONFIG_UART4_SERIAL_CONSOLE)
+# define STM32_CONSOLE_BASE STM32_UART4_BASE
+# elif defined(CONFIG_UART5_SERIAL_CONSOLE)
+# define STM32_CONSOLE_BASE STM32_UART5_BASE
+# elif defined(CONFIG_USART6_SERIAL_CONSOLE)
+# define STM32_CONSOLE_BASE STM32_USART6_BASE
+# elif defined(CONFIG_UART7_SERIAL_CONSOLE)
+# define STM32_CONSOLE_BASE STM32_UART7_BASE
+# elif defined(CONFIG_UART8_SERIAL_CONSOLE)
+# define STM32_CONSOLE_BASE STM32_UART8_BASE
+# endif
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_getc
+ *
+ * Description:
+ * Read one byte from the serial console
+ *
+ ****************************************************************************/
+
+int up_getc(void)
+{
+ uint32_t ch = 0;
+
+#ifdef HAVE_CONSOLE
+ /* While there is any error, read and discard bytes to clear the errors */
+
+ while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) &
+ (USART_SR_ORE | USART_SR_NE | USART_SR_FE | USART_SR_PE)) != 0)
+ {
+ (void)getreg32(STM32_CONSOLE_BASE + STM32_USART_RDR_OFFSET);
+ }
+
+ /* Wait until the RX data register has a character to be read */
+
+ while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & USART_SR_RXNE) == 0);
+
+ /* Then read the character */
+
+ ch = getreg32(STM32_CONSOLE_BASE + STM32_USART_RDR_OFFSET);
+#endif /* HAVE_CONSOLE */
+
+ return (int)ch;
+}
diff --git a/arch/arm/src/stm32/stm32_lowgetc.h b/arch/arm/src/stm32/stm32_lowgetc.h
new file mode 100644
index 0000000000..624e6272f4
--- /dev/null
+++ b/arch/arm/src/stm32/stm32_lowgetc.h
@@ -0,0 +1,47 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_lowgetc.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_LOWGETC_H
+#define __ARCH_ARM_SRC_STM32_STM32_LOWGETC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_LOWGETC_H */
--
GitLab
From 76a899f9eb41f475c4e665c81f572d268fcb3708 Mon Sep 17 00:00:00 2001
From: Alan Carvalho de Assis
Date: Sat, 4 Jun 2016 07:36:04 -0600
Subject: [PATCH 052/400] STM32F103 Minimum: Add minnsh configuration
---
configs/stm32f103-minimum/README.txt | 25 +
configs/stm32f103-minimum/minnsh/Make.defs | 113 +++
configs/stm32f103-minimum/minnsh/defconfig | 1052 ++++++++++++++++++++
configs/stm32f103-minimum/minnsh/setenv.sh | 100 ++
4 files changed, 1290 insertions(+)
create mode 100644 configs/stm32f103-minimum/minnsh/Make.defs
create mode 100644 configs/stm32f103-minimum/minnsh/defconfig
create mode 100644 configs/stm32f103-minimum/minnsh/setenv.sh
diff --git a/configs/stm32f103-minimum/README.txt b/configs/stm32f103-minimum/README.txt
index 59bef3ef6a..96e7be7a79 100644
--- a/configs/stm32f103-minimum/README.txt
+++ b/configs/stm32f103-minimum/README.txt
@@ -421,6 +421,31 @@ instead of configure.sh:
Where is one of the following:
+ minnsh:
+ ------
+
+ This is a experiment to see just how small we can get a usable NSH
+ configuration. This configuration has far fewer features than the nsh
+ configuration but is also a fraction of the size.
+
+ STATUS:
+ 2016-06-03: Using that config I got this:
+
+ $ ls -l nuttx.bin
+ -rwxr-xr-x 1 alan alan 12543 Jun 3 17:58 nuttx.bin
+
+ $ arm-none-eabi-size nuttx
+ text data bss dec hex filename
+ 12542 1 816 13359 342f nuttx
+
+ And this is free command from NuttX shell:
+
+ NuttShell (NSH)
+ nsh> free
+ total used free largest
+ Mem: 18624 2328 16296 16296
+ nsh>
+
nsh:
---
Configures the NuttShell (nsh) located at apps/examples/nsh. This
diff --git a/configs/stm32f103-minimum/minnsh/Make.defs b/configs/stm32f103-minimum/minnsh/Make.defs
new file mode 100644
index 0000000000..b77741df25
--- /dev/null
+++ b/configs/stm32f103-minimum/minnsh/Make.defs
@@ -0,0 +1,113 @@
+############################################################################
+# configs/stm32f103-minimum/nsh/Make.defs
+#
+# Copyright (C) 2016 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
+
+LDSCRIPT = ld.script
+
+ifeq ($(WINTOOL),y)
+ # Windows-native toolchains
+ DIRLINK = $(TOPDIR)/tools/copydir.sh
+ DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+ MKDEP = $(TOPDIR)/tools/mkwindeps.sh
+ ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+ ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+ ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
+else
+ # Linux/Cygwin-native toolchain
+ MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
+ ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+ ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+ ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
+endif
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+AR = $(CROSSDEV)ar rcs
+NM = $(CROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ ARCHOPTIMIZATION = -g
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+ ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
+ARCHWARNINGSXX = -Wall -Wshadow -Wundef
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+ASMEXT = .S
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-nuttx-elf-)
+ LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ LDFLAGS += -g
+endif
+
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
+HOSTLDFLAGS =
+
diff --git a/configs/stm32f103-minimum/minnsh/defconfig b/configs/stm32f103-minimum/minnsh/defconfig
new file mode 100644
index 0000000000..16568484f0
--- /dev/null
+++ b/configs/stm32f103-minimum/minnsh/defconfig
@@ -0,0 +1,1052 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Nuttx/ Configuration
+#
+
+#
+# Build Setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_DEFAULT_SMALL=y
+CONFIG_HOST_LINUX=y
+# CONFIG_HOST_OSX is not set
+# CONFIG_HOST_WINDOWS is not set
+# CONFIG_HOST_OTHER is not set
+
+#
+# Build Configuration
+#
+# CONFIG_APPS_DIR="../apps"
+CONFIG_BUILD_FLAT=y
+# CONFIG_BUILD_2PASS is not set
+
+#
+# Binary Output Formats
+#
+# CONFIG_RRLOAD_BINARY is not set
+# CONFIG_INTELHEX_BINARY is not set
+# CONFIG_MOTOROLA_SREC is not set
+CONFIG_RAW_BINARY=y
+# CONFIG_UBOOT_UIMAGE is not set
+
+#
+# Customize Header Files
+#
+# CONFIG_ARCH_STDINT_H is not set
+# CONFIG_ARCH_STDBOOL_H is not set
+# CONFIG_ARCH_MATH_H is not set
+# CONFIG_ARCH_FLOAT_H is not set
+# CONFIG_ARCH_STDARG_H is not set
+# CONFIG_ARCH_DEBUG_H is not set
+
+#
+# Debug Options
+#
+# CONFIG_DEBUG is not set
+CONFIG_ARCH_HAVE_HEAPCHECK=y
+CONFIG_ARCH_HAVE_STACKCHECK=y
+# CONFIG_STACK_COLORATION is not set
+# CONFIG_DEBUG_SYMBOLS is not set
+CONFIG_ARCH_HAVE_CUSTOMOPT=y
+# CONFIG_DEBUG_NOOPT is not set
+# CONFIG_DEBUG_CUSTOMOPT is not set
+CONFIG_DEBUG_FULLOPT=y
+
+#
+# System Type
+#
+CONFIG_ARCH_ARM=y
+# CONFIG_ARCH_AVR is not set
+# CONFIG_ARCH_HC is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_RGMP is not set
+# CONFIG_ARCH_SH is not set
+# CONFIG_ARCH_SIM is not set
+# CONFIG_ARCH_X86 is not set
+# CONFIG_ARCH_Z16 is not set
+# CONFIG_ARCH_Z80 is not set
+CONFIG_ARCH="arm"
+
+#
+# ARM Options
+#
+# CONFIG_ARCH_CHIP_A1X is not set
+# CONFIG_ARCH_CHIP_C5471 is not set
+# CONFIG_ARCH_CHIP_CALYPSO is not set
+# CONFIG_ARCH_CHIP_DM320 is not set
+# CONFIG_ARCH_CHIP_EFM32 is not set
+# CONFIG_ARCH_CHIP_IMX1 is not set
+# CONFIG_ARCH_CHIP_IMX6 is not set
+# CONFIG_ARCH_CHIP_KINETIS is not set
+# CONFIG_ARCH_CHIP_KL is not set
+# CONFIG_ARCH_CHIP_LM is not set
+# CONFIG_ARCH_CHIP_TIVA is not set
+# CONFIG_ARCH_CHIP_LPC11XX is not set
+# CONFIG_ARCH_CHIP_LPC17XX is not set
+# CONFIG_ARCH_CHIP_LPC214X is not set
+# CONFIG_ARCH_CHIP_LPC2378 is not set
+# CONFIG_ARCH_CHIP_LPC31XX is not set
+# CONFIG_ARCH_CHIP_LPC43XX is not set
+# CONFIG_ARCH_CHIP_NUC1XX is not set
+# CONFIG_ARCH_CHIP_SAMA5 is not set
+# CONFIG_ARCH_CHIP_SAMD is not set
+# CONFIG_ARCH_CHIP_SAML is not set
+# CONFIG_ARCH_CHIP_SAM34 is not set
+# CONFIG_ARCH_CHIP_SAMV7 is not set
+CONFIG_ARCH_CHIP_STM32=y
+# CONFIG_ARCH_CHIP_STM32F7 is not set
+# CONFIG_ARCH_CHIP_STM32L4 is not set
+# CONFIG_ARCH_CHIP_STR71X is not set
+# CONFIG_ARCH_CHIP_TMS570 is not set
+# CONFIG_ARCH_CHIP_MOXART is not set
+# CONFIG_ARCH_ARM7TDMI is not set
+# CONFIG_ARCH_ARM926EJS is not set
+# CONFIG_ARCH_ARM920T is not set
+# CONFIG_ARCH_CORTEXM0 is not set
+CONFIG_ARCH_CORTEXM3=y
+# CONFIG_ARCH_CORTEXM4 is not set
+# CONFIG_ARCH_CORTEXM7 is not set
+# CONFIG_ARCH_CORTEXA5 is not set
+# CONFIG_ARCH_CORTEXA8 is not set
+# CONFIG_ARCH_CORTEXA9 is not set
+# CONFIG_ARCH_CORTEXR4 is not set
+# CONFIG_ARCH_CORTEXR4F is not set
+# CONFIG_ARCH_CORTEXR5 is not set
+# CONFIG_ARCH_CORTEX5F is not set
+# CONFIG_ARCH_CORTEXR7 is not set
+# CONFIG_ARCH_CORTEXR7F is not set
+CONFIG_ARCH_FAMILY="armv7-m"
+CONFIG_ARCH_CHIP="stm32"
+# CONFIG_ARM_TOOLCHAIN_IAR is not set
+CONFIG_ARM_TOOLCHAIN_GNU=y
+# CONFIG_ARMV7M_USEBASEPRI is not set
+CONFIG_ARCH_HAVE_CMNVECTOR=y
+# CONFIG_ARMV7M_CMNVECTOR is not set
+# CONFIG_ARMV7M_LAZYFPU is not set
+# CONFIG_ARCH_HAVE_FPU is not set
+# CONFIG_ARCH_HAVE_DPFPU is not set
+# CONFIG_ARCH_HAVE_TRUSTZONE is not set
+CONFIG_ARM_HAVE_MPU_UNIFIED=y
+# CONFIG_ARM_MPU is not set
+
+#
+# ARMV7M Configuration Options
+#
+# CONFIG_ARMV7M_HAVE_ICACHE is not set
+# CONFIG_ARMV7M_HAVE_DCACHE is not set
+# CONFIG_ARMV7M_HAVE_ITCM is not set
+# CONFIG_ARMV7M_HAVE_DTCM is not set
+# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set
+# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
+# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
+# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
+CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y
+CONFIG_ARMV7M_HAVE_STACKCHECK=y
+# CONFIG_ARMV7M_STACKCHECK is not set
+# CONFIG_ARMV7M_ITMSYSLOG is not set
+# CONFIG_SERIAL_TERMIOS is not set
+
+#
+# STM32 Configuration Options
+#
+# CONFIG_ARCH_CHIP_STM32L151C6 is not set
+# CONFIG_ARCH_CHIP_STM32L151C8 is not set
+# CONFIG_ARCH_CHIP_STM32L151CB is not set
+# CONFIG_ARCH_CHIP_STM32L151R6 is not set
+# CONFIG_ARCH_CHIP_STM32L151R8 is not set
+# CONFIG_ARCH_CHIP_STM32L151RB is not set
+# CONFIG_ARCH_CHIP_STM32L151V6 is not set
+# CONFIG_ARCH_CHIP_STM32L151V8 is not set
+# CONFIG_ARCH_CHIP_STM32L151VB is not set
+# CONFIG_ARCH_CHIP_STM32L152C6 is not set
+# CONFIG_ARCH_CHIP_STM32L152C8 is not set
+# CONFIG_ARCH_CHIP_STM32L152CB is not set
+# CONFIG_ARCH_CHIP_STM32L152R6 is not set
+# CONFIG_ARCH_CHIP_STM32L152R8 is not set
+# CONFIG_ARCH_CHIP_STM32L152RB is not set
+# CONFIG_ARCH_CHIP_STM32L152V6 is not set
+# CONFIG_ARCH_CHIP_STM32L152V8 is not set
+# CONFIG_ARCH_CHIP_STM32L152VB is not set
+# CONFIG_ARCH_CHIP_STM32L162ZD is not set
+# CONFIG_ARCH_CHIP_STM32L162VE is not set
+# CONFIG_ARCH_CHIP_STM32F100C8 is not set
+# CONFIG_ARCH_CHIP_STM32F100CB is not set
+# CONFIG_ARCH_CHIP_STM32F100R8 is not set
+# CONFIG_ARCH_CHIP_STM32F100RB is not set
+# CONFIG_ARCH_CHIP_STM32F100RC is not set
+# CONFIG_ARCH_CHIP_STM32F100RD is not set
+# CONFIG_ARCH_CHIP_STM32F100RE is not set
+# CONFIG_ARCH_CHIP_STM32F100V8 is not set
+# CONFIG_ARCH_CHIP_STM32F100VB is not set
+# CONFIG_ARCH_CHIP_STM32F100VC is not set
+# CONFIG_ARCH_CHIP_STM32F100VD is not set
+# CONFIG_ARCH_CHIP_STM32F100VE is not set
+# CONFIG_ARCH_CHIP_STM32F102CB is not set
+# CONFIG_ARCH_CHIP_STM32F103T8 is not set
+# CONFIG_ARCH_CHIP_STM32F103TB is not set
+# CONFIG_ARCH_CHIP_STM32F103C4 is not set
+CONFIG_ARCH_CHIP_STM32F103C8=y
+# CONFIG_ARCH_CHIP_STM32F103CB is not set
+# CONFIG_ARCH_CHIP_STM32F103R8 is not set
+# CONFIG_ARCH_CHIP_STM32F103RB is not set
+# CONFIG_ARCH_CHIP_STM32F103RC is not set
+# CONFIG_ARCH_CHIP_STM32F103RD is not set
+# CONFIG_ARCH_CHIP_STM32F103RE is not set
+# CONFIG_ARCH_CHIP_STM32F103RG is not set
+# CONFIG_ARCH_CHIP_STM32F103V8 is not set
+# CONFIG_ARCH_CHIP_STM32F103VB is not set
+# CONFIG_ARCH_CHIP_STM32F103VC is not set
+# CONFIG_ARCH_CHIP_STM32F103VE is not set
+# CONFIG_ARCH_CHIP_STM32F103ZE is not set
+# CONFIG_ARCH_CHIP_STM32F105VB is not set
+# CONFIG_ARCH_CHIP_STM32F107VC is not set
+# CONFIG_ARCH_CHIP_STM32F205RG is not set
+# CONFIG_ARCH_CHIP_STM32F207IG is not set
+# CONFIG_ARCH_CHIP_STM32F207ZE is not set
+# CONFIG_ARCH_CHIP_STM32F302K6 is not set
+# CONFIG_ARCH_CHIP_STM32F302K8 is not set
+# CONFIG_ARCH_CHIP_STM32F302CB is not set
+# CONFIG_ARCH_CHIP_STM32F302CC is not set
+# CONFIG_ARCH_CHIP_STM32F302RB is not set
+# CONFIG_ARCH_CHIP_STM32F302RC is not set
+# CONFIG_ARCH_CHIP_STM32F302VB is not set
+# CONFIG_ARCH_CHIP_STM32F302VC is not set
+# CONFIG_ARCH_CHIP_STM32F303K6 is not set
+# CONFIG_ARCH_CHIP_STM32F303K8 is not set
+# CONFIG_ARCH_CHIP_STM32F303C6 is not set
+# CONFIG_ARCH_CHIP_STM32F303C8 is not set
+# CONFIG_ARCH_CHIP_STM32F303CB is not set
+# CONFIG_ARCH_CHIP_STM32F303CC is not set
+# CONFIG_ARCH_CHIP_STM32F303RB is not set
+# CONFIG_ARCH_CHIP_STM32F303RC is not set
+# CONFIG_ARCH_CHIP_STM32F303RD is not set
+# CONFIG_ARCH_CHIP_STM32F303RE is not set
+# CONFIG_ARCH_CHIP_STM32F303VB is not set
+# CONFIG_ARCH_CHIP_STM32F303VC is not set
+# CONFIG_ARCH_CHIP_STM32F372C8 is not set
+# CONFIG_ARCH_CHIP_STM32F372R8 is not set
+# CONFIG_ARCH_CHIP_STM32F372V8 is not set
+# CONFIG_ARCH_CHIP_STM32F372CB is not set
+# CONFIG_ARCH_CHIP_STM32F372RB is not set
+# CONFIG_ARCH_CHIP_STM32F372VB is not set
+# CONFIG_ARCH_CHIP_STM32F372CC is not set
+# CONFIG_ARCH_CHIP_STM32F372RC is not set
+# CONFIG_ARCH_CHIP_STM32F372VC is not set
+# CONFIG_ARCH_CHIP_STM32F373C8 is not set
+# CONFIG_ARCH_CHIP_STM32F373R8 is not set
+# CONFIG_ARCH_CHIP_STM32F373V8 is not set
+# CONFIG_ARCH_CHIP_STM32F373CB is not set
+# CONFIG_ARCH_CHIP_STM32F373RB is not set
+# CONFIG_ARCH_CHIP_STM32F373VB is not set
+# CONFIG_ARCH_CHIP_STM32F373CC is not set
+# CONFIG_ARCH_CHIP_STM32F373RC is not set
+# CONFIG_ARCH_CHIP_STM32F373VC is not set
+# CONFIG_ARCH_CHIP_STM32F401RE is not set
+# CONFIG_ARCH_CHIP_STM32F411RE is not set
+# CONFIG_ARCH_CHIP_STM32F411VE is not set
+# CONFIG_ARCH_CHIP_STM32F405RG is not set
+# CONFIG_ARCH_CHIP_STM32F405VG is not set
+# CONFIG_ARCH_CHIP_STM32F405ZG is not set
+# CONFIG_ARCH_CHIP_STM32F407VE is not set
+# CONFIG_ARCH_CHIP_STM32F407VG is not set
+# CONFIG_ARCH_CHIP_STM32F407ZE is not set
+# CONFIG_ARCH_CHIP_STM32F407ZG is not set
+# CONFIG_ARCH_CHIP_STM32F407IE is not set
+# CONFIG_ARCH_CHIP_STM32F407IG is not set
+# CONFIG_ARCH_CHIP_STM32F427V is not set
+# CONFIG_ARCH_CHIP_STM32F427Z is not set
+# CONFIG_ARCH_CHIP_STM32F427I is not set
+# CONFIG_ARCH_CHIP_STM32F429V is not set
+# CONFIG_ARCH_CHIP_STM32F429Z is not set
+# CONFIG_ARCH_CHIP_STM32F429I is not set
+# CONFIG_ARCH_CHIP_STM32F429B is not set
+# CONFIG_ARCH_CHIP_STM32F429N is not set
+# CONFIG_ARCH_CHIP_STM32F446M is not set
+# CONFIG_ARCH_CHIP_STM32F446R is not set
+# CONFIG_ARCH_CHIP_STM32F446V is not set
+# CONFIG_ARCH_CHIP_STM32F446Z is not set
+# CONFIG_ARCH_CHIP_STM32F469A is not set
+# CONFIG_ARCH_CHIP_STM32F469I is not set
+# CONFIG_ARCH_CHIP_STM32F469B is not set
+# CONFIG_ARCH_CHIP_STM32F469N is not set
+CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
+# CONFIG_STM32_FLASH_CONFIG_4 is not set
+# CONFIG_STM32_FLASH_CONFIG_6 is not set
+# CONFIG_STM32_FLASH_CONFIG_8 is not set
+# CONFIG_STM32_FLASH_CONFIG_B is not set
+# CONFIG_STM32_FLASH_CONFIG_C is not set
+# CONFIG_STM32_FLASH_CONFIG_D is not set
+# CONFIG_STM32_FLASH_CONFIG_E is not set
+# CONFIG_STM32_FLASH_CONFIG_F is not set
+# CONFIG_STM32_FLASH_CONFIG_G is not set
+# CONFIG_STM32_FLASH_CONFIG_I is not set
+# CONFIG_STM32_STM32L15XX is not set
+# CONFIG_STM32_ENERGYLITE is not set
+CONFIG_STM32_STM32F10XX=y
+# CONFIG_STM32_VALUELINE is not set
+# CONFIG_STM32_CONNECTIVITYLINE is not set
+CONFIG_STM32_PERFORMANCELINE=y
+# CONFIG_STM32_USBACCESSLINE is not set
+# CONFIG_STM32_HIGHDENSITY is not set
+CONFIG_STM32_MEDIUMDENSITY=y
+# CONFIG_STM32_LOWDENSITY is not set
+# CONFIG_STM32_STM32F20XX is not set
+# CONFIG_STM32_STM32F205 is not set
+# CONFIG_STM32_STM32F207 is not set
+# CONFIG_STM32_STM32F30XX is not set
+# CONFIG_STM32_STM32F302 is not set
+# CONFIG_STM32_STM32F303 is not set
+# CONFIG_STM32_STM32F37XX is not set
+# CONFIG_STM32_STM32F40XX is not set
+# CONFIG_STM32_STM32F401 is not set
+# CONFIG_STM32_STM32F411 is not set
+# CONFIG_STM32_STM32F405 is not set
+# CONFIG_STM32_STM32F407 is not set
+# CONFIG_STM32_STM32F427 is not set
+# CONFIG_STM32_STM32F429 is not set
+# CONFIG_STM32_STM32F446 is not set
+# CONFIG_STM32_STM32F469 is not set
+# CONFIG_STM32_DFU is not set
+
+#
+# STM32 Peripheral Support
+#
+# CONFIG_STM32_HAVE_CCM is not set
+CONFIG_STM32_HAVE_USBDEV=y
+# CONFIG_STM32_HAVE_OTGFS is not set
+# CONFIG_STM32_HAVE_FSMC is not set
+# CONFIG_STM32_HAVE_LTDC is not set
+CONFIG_STM32_HAVE_USART3=y
+CONFIG_STM32_HAVE_UART4=y
+CONFIG_STM32_HAVE_UART5=y
+# CONFIG_STM32_HAVE_USART6 is not set
+# CONFIG_STM32_HAVE_UART7 is not set
+# CONFIG_STM32_HAVE_UART8 is not set
+CONFIG_STM32_HAVE_TIM1=y
+# CONFIG_STM32_HAVE_TIM2 is not set
+CONFIG_STM32_HAVE_TIM3=y
+CONFIG_STM32_HAVE_TIM4=y
+CONFIG_STM32_HAVE_TIM5=y
+CONFIG_STM32_HAVE_TIM6=y
+CONFIG_STM32_HAVE_TIM7=y
+CONFIG_STM32_HAVE_TIM8=y
+# CONFIG_STM32_HAVE_TIM9 is not set
+# CONFIG_STM32_HAVE_TIM10 is not set
+# CONFIG_STM32_HAVE_TIM11 is not set
+# CONFIG_STM32_HAVE_TIM12 is not set
+# CONFIG_STM32_HAVE_TIM13 is not set
+# CONFIG_STM32_HAVE_TIM14 is not set
+# CONFIG_STM32_HAVE_TIM15 is not set
+# CONFIG_STM32_HAVE_TIM16 is not set
+# CONFIG_STM32_HAVE_TIM17 is not set
+CONFIG_STM32_HAVE_ADC2=y
+CONFIG_STM32_HAVE_ADC3=y
+# CONFIG_STM32_HAVE_ADC4 is not set
+# CONFIG_STM32_HAVE_ADC1_DMA is not set
+# CONFIG_STM32_HAVE_ADC2_DMA is not set
+# CONFIG_STM32_HAVE_ADC3_DMA is not set
+# CONFIG_STM32_HAVE_ADC4_DMA is not set
+CONFIG_STM32_HAVE_CAN1=y
+# CONFIG_STM32_HAVE_CAN2 is not set
+# CONFIG_STM32_HAVE_DAC1 is not set
+# CONFIG_STM32_HAVE_DAC2 is not set
+# CONFIG_STM32_HAVE_RNG is not set
+# CONFIG_STM32_HAVE_ETHMAC is not set
+CONFIG_STM32_HAVE_I2C2=y
+# CONFIG_STM32_HAVE_I2C3 is not set
+CONFIG_STM32_HAVE_SPI2=y
+CONFIG_STM32_HAVE_SPI3=y
+# CONFIG_STM32_HAVE_SPI4 is not set
+# CONFIG_STM32_HAVE_SPI5 is not set
+# CONFIG_STM32_HAVE_SPI6 is not set
+# CONFIG_STM32_HAVE_SAIPLL is not set
+# CONFIG_STM32_HAVE_I2SPLL is not set
+# CONFIG_STM32_ADC1 is not set
+# CONFIG_STM32_ADC2 is not set
+# CONFIG_STM32_ADC3 is not set
+# CONFIG_STM32_BKP is not set
+# CONFIG_STM32_CAN1 is not set
+# CONFIG_STM32_CRC is not set
+# CONFIG_STM32_DMA1 is not set
+# CONFIG_STM32_DMA2 is not set
+# CONFIG_STM32_I2C1 is not set
+# CONFIG_STM32_I2C2 is not set
+# CONFIG_STM32_PWR is not set
+# CONFIG_STM32_SDIO is not set
+# CONFIG_STM32_SPI1 is not set
+# CONFIG_STM32_SPI2 is not set
+# CONFIG_STM32_SPI3 is not set
+# CONFIG_STM32_TIM1 is not set
+# CONFIG_STM32_TIM2 is not set
+# CONFIG_STM32_TIM3 is not set
+# CONFIG_STM32_TIM4 is not set
+# CONFIG_STM32_TIM5 is not set
+# CONFIG_STM32_TIM6 is not set
+# CONFIG_STM32_TIM7 is not set
+# CONFIG_STM32_TIM8 is not set
+CONFIG_STM32_USART1=y
+# CONFIG_STM32_USART2 is not set
+# CONFIG_STM32_USART3 is not set
+# CONFIG_STM32_UART4 is not set
+# CONFIG_STM32_UART5 is not set
+# CONFIG_STM32_USB is not set
+# CONFIG_STM32_IWDG is not set
+# CONFIG_STM32_WWDG is not set
+# CONFIG_STM32_NOEXT_VECTORS is not set
+
+#
+# Alternate Pin Mapping
+#
+# CONFIG_STM32_USART1_REMAP is not set
+# CONFIG_STM32_JTAG_DISABLE is not set
+CONFIG_STM32_JTAG_FULL_ENABLE=y
+# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set
+# CONFIG_STM32_JTAG_SW_ENABLE is not set
+CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
+# CONFIG_STM32_FORCEPOWER is not set
+# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set
+# CONFIG_STM32_TIM1_CAP is not set
+# CONFIG_STM32_TIM3_CAP is not set
+# CONFIG_STM32_TIM4_CAP is not set
+# CONFIG_STM32_TIM5_CAP is not set
+# CONFIG_STM32_TIM8_CAP is not set
+CONFIG_STM32_USART=y
+CONFIG_STM32_SERIALDRIVER=y
+
+#
+# U[S]ART Configuration
+#
+
+#
+# U[S]ART Device Configuration
+#
+CONFIG_STM32_USART1_SERIALDRIVER=y
+# CONFIG_STM32_USART1_1WIREDRIVER is not set
+# CONFIG_USART1_RS485 is not set
+
+#
+# Serial Driver Configuration
+#
+# CONFIG_SERIAL_DISABLE_REORDERING is not set
+# CONFIG_STM32_FLOWCONTROL_BROKEN is not set
+# CONFIG_STM32_USART_BREAKS is not set
+# CONFIG_STM32_USART_SINGLEWIRE is not set
+CONFIG_STM32_HAVE_RTC_COUNTER=y
+# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set
+
+#
+# USB FS Host Configuration
+#
+
+#
+# USB HS Host Configuration
+#
+
+#
+# USB Host Debug Configuration
+#
+
+#
+# USB Device Configuration
+#
+
+#
+# Architecture Options
+#
+# CONFIG_ARCH_NOINTC is not set
+# CONFIG_ARCH_VECNOTIRQ is not set
+# CONFIG_ARCH_DMA is not set
+CONFIG_ARCH_HAVE_IRQPRIO=y
+# CONFIG_ARCH_L2CACHE is not set
+# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set
+# CONFIG_ARCH_HAVE_ADDRENV is not set
+# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set
+# CONFIG_ARCH_HAVE_MULTICPU is not set
+CONFIG_ARCH_HAVE_VFORK=y
+# CONFIG_ARCH_HAVE_MMU is not set
+CONFIG_ARCH_HAVE_MPU=y
+# CONFIG_ARCH_NAND_HWECC is not set
+# CONFIG_ARCH_HAVE_EXTCLK is not set
+# CONFIG_ARCH_HAVE_POWEROFF is not set
+CONFIG_ARCH_HAVE_RESET=y
+# CONFIG_ARCH_USE_MPU is not set
+# CONFIG_ARCH_IRQPRIO is not set
+# CONFIG_ARCH_STACKDUMP is not set
+# CONFIG_ENDIAN_BIG is not set
+# CONFIG_ARCH_IDLE_CUSTOM is not set
+# CONFIG_ARCH_HAVE_RAMFUNCS is not set
+CONFIG_ARCH_HAVE_RAMVECTORS=y
+# CONFIG_ARCH_RAMVECTORS is not set
+
+#
+# Board Settings
+#
+CONFIG_BOARD_LOOPSPERMSEC=5483
+# CONFIG_ARCH_CALIBRATION is not set
+
+#
+# Interrupt options
+#
+CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
+CONFIG_ARCH_INTERRUPTSTACK=0
+CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y
+# CONFIG_ARCH_HIPRI_INTERRUPT is not set
+
+#
+# Boot options
+#
+# CONFIG_BOOT_RUNFROMEXTSRAM is not set
+CONFIG_BOOT_RUNFROMFLASH=y
+# CONFIG_BOOT_RUNFROMISRAM is not set
+# CONFIG_BOOT_RUNFROMSDRAM is not set
+# CONFIG_BOOT_COPYTORAM is not set
+
+#
+# Boot Memory Configuration
+#
+CONFIG_RAM_START=0x20000000
+CONFIG_RAM_SIZE=20480
+# CONFIG_ARCH_HAVE_SDRAM is not set
+
+#
+# Board Selection
+#
+# CONFIG_ARCH_BOARD_STM32_TINY is not set
+CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y
+# CONFIG_ARCH_BOARD_CUSTOM is not set
+CONFIG_ARCH_BOARD="stm32f103-minimum"
+
+#
+# Common Board Options
+#
+CONFIG_ARCH_HAVE_LEDS=y
+CONFIG_ARCH_LEDS=y
+CONFIG_NSH_MMCSDMINOR=0
+
+#
+# Board-Specific Options
+#
+# CONFIG_LIB_BOARDCTL is not set
+
+#
+# RTOS Features
+#
+CONFIG_DISABLE_OS_API=y
+CONFIG_DISABLE_POSIX_TIMERS=y
+CONFIG_DISABLE_PTHREAD=y
+CONFIG_DISABLE_SIGNALS=y
+CONFIG_DISABLE_MQUEUE=y
+CONFIG_DISABLE_ENVIRON=y
+
+#
+# Clocks and Timers
+#
+CONFIG_USEC_PER_TICK=10000
+# CONFIG_SYSTEM_TIME64 is not set
+# CONFIG_CLOCK_MONOTONIC is not set
+# CONFIG_JULIAN_TIME is not set
+CONFIG_START_YEAR=2013
+CONFIG_START_MONTH=2
+CONFIG_START_DAY=26
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_PREALLOC_WDOGS=4
+CONFIG_WDOG_INTRESERVE=0
+CONFIG_PREALLOC_TIMERS=0
+
+#
+# Tasks and Scheduling
+#
+# CONFIG_INIT_NONE is not set
+CONFIG_INIT_ENTRYPOINT=y
+# CONFIG_INIT_FILEPATH is not set
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_RR_INTERVAL=0
+# CONFIG_SCHED_SPORADIC is not set
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_MAX_TASKS=4
+# CONFIG_SCHED_HAVE_PARENT is not set
+# CONFIG_SCHED_WAITPID is not set
+
+#
+# Performance Monitoring
+#
+# CONFIG_SCHED_CPULOAD is not set
+# CONFIG_SCHED_INSTRUMENTATION is not set
+
+#
+# Files and I/O
+#
+# CONFIG_DEV_CONSOLE is not set
+CONFIG_FDCLONE_DISABLE=y
+# CONFIG_FDCLONE_STDIO is not set
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_NFILE_DESCRIPTORS=0
+CONFIG_NFILE_STREAMS=0
+CONFIG_NAME_MAX=32
+# CONFIG_PRIORITY_INHERITANCE is not set
+
+#
+# RTOS hooks
+#
+# CONFIG_BOARD_INITIALIZE is not set
+# CONFIG_SCHED_STARTHOOK is not set
+# CONFIG_SCHED_ATEXIT is not set
+# CONFIG_SCHED_ONEXIT is not set
+# CONFIG_MODULE is not set
+
+#
+# Work queue support
+#
+
+#
+# Stack and heap information
+#
+CONFIG_IDLETHREAD_STACKSIZE=1024
+CONFIG_USERMAIN_STACKSIZE=2048
+CONFIG_PTHREAD_STACK_MIN=256
+CONFIG_PTHREAD_STACK_DEFAULT=2048
+# CONFIG_LIB_SYSCALL is not set
+
+#
+# Device Drivers
+#
+CONFIG_DISABLE_POLL=y
+# CONFIG_DEV_NULL is not set
+# CONFIG_DEV_ZERO is not set
+# CONFIG_DEV_LOOP is not set
+
+#
+# Buffering
+#
+# CONFIG_DRVR_WRITEBUFFER is not set
+# CONFIG_DRVR_READAHEAD is not set
+# CONFIG_RAMDISK is not set
+# CONFIG_CAN is not set
+# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set
+# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set
+# CONFIG_PWM is not set
+CONFIG_ARCH_HAVE_I2CRESET=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_I2S is not set
+
+#
+# Timer Driver Support
+#
+# CONFIG_TIMER is not set
+# CONFIG_RTC is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_ANALOG is not set
+# CONFIG_AUDIO_DEVICES is not set
+# CONFIG_VIDEO_DEVICES is not set
+# CONFIG_BCH is not set
+# CONFIG_INPUT is not set
+# CONFIG_IOEXPANDER is not set
+
+#
+# LCD Driver Support
+#
+# CONFIG_LCD is not set
+# CONFIG_SLCD is not set
+
+#
+# LED Support
+#
+# CONFIG_USERLED is not set
+# CONFIG_RGBLED is not set
+# CONFIG_PCA9635PW is not set
+# CONFIG_MMCSD is not set
+# CONFIG_MODEM is not set
+# CONFIG_MTD is not set
+# CONFIG_EEPROM is not set
+# CONFIG_PIPES is not set
+# CONFIG_PM is not set
+# CONFIG_POWER is not set
+# CONFIG_SENSORS is not set
+# CONFIG_SERCOMM_CONSOLE is not set
+CONFIG_SERIAL=y
+# CONFIG_16550_UART is not set
+# CONFIG_UART_SERIALDRIVER is not set
+# CONFIG_UART0_SERIALDRIVER is not set
+# CONFIG_UART1_SERIALDRIVER is not set
+# CONFIG_UART2_SERIALDRIVER is not set
+# CONFIG_UART3_SERIALDRIVER is not set
+# CONFIG_UART4_SERIALDRIVER is not set
+# CONFIG_UART5_SERIALDRIVER is not set
+# CONFIG_UART6_SERIALDRIVER is not set
+# CONFIG_UART7_SERIALDRIVER is not set
+# CONFIG_UART8_SERIALDRIVER is not set
+# CONFIG_SCI0_SERIALDRIVER is not set
+# CONFIG_SCI1_SERIALDRIVER is not set
+# CONFIG_USART0_SERIALDRIVER is not set
+CONFIG_USART1_SERIALDRIVER=y
+# CONFIG_USART2_SERIALDRIVER is not set
+# CONFIG_USART3_SERIALDRIVER is not set
+# CONFIG_USART4_SERIALDRIVER is not set
+# CONFIG_USART5_SERIALDRIVER is not set
+# CONFIG_USART6_SERIALDRIVER is not set
+# CONFIG_USART7_SERIALDRIVER is not set
+# CONFIG_USART8_SERIALDRIVER is not set
+# CONFIG_OTHER_UART_SERIALDRIVER is not set
+CONFIG_MCU_SERIAL=y
+# CONFIG_STANDARD_SERIAL is not set
+# CONFIG_SERIAL_IFLOWCONTROL is not set
+# CONFIG_SERIAL_OFLOWCONTROL is not set
+# CONFIG_SERIAL_DMA is not set
+CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y
+CONFIG_USART1_SERIAL_CONSOLE=y
+# CONFIG_OTHER_SERIAL_CONSOLE is not set
+# CONFIG_NO_SERIAL_CONSOLE is not set
+
+#
+# USART1 Configuration
+#
+CONFIG_USART1_RXBUFSIZE=64
+CONFIG_USART1_TXBUFSIZE=64
+CONFIG_USART1_BAUD=115200
+CONFIG_USART1_BITS=8
+CONFIG_USART1_PARITY=0
+CONFIG_USART1_2STOP=0
+# CONFIG_USART1_IFLOWCONTROL is not set
+# CONFIG_USART1_OFLOWCONTROL is not set
+# CONFIG_USART1_DMA is not set
+# CONFIG_USBDEV is not set
+# CONFIG_USBHOST is not set
+# CONFIG_DRIVERS_WIRELESS is not set
+
+#
+# System Logging Device Options
+#
+
+#
+# System Logging
+#
+# CONFIG_RAMLOG is not set
+
+#
+# Networking Support
+#
+# CONFIG_ARCH_HAVE_NET is not set
+# CONFIG_ARCH_HAVE_PHY is not set
+# CONFIG_NET is not set
+
+#
+# Crypto API
+#
+# CONFIG_CRYPTO is not set
+
+#
+# File Systems
+#
+
+#
+# File system configuration
+#
+CONFIG_DISABLE_MOUNTPOINT=y
+CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
+# CONFIG_FS_READABLE is not set
+# CONFIG_FS_WRITABLE is not set
+# CONFIG_FS_NAMED_SEMAPHORES is not set
+# CONFIG_FS_RAMMAP is not set
+# CONFIG_FS_PROCFS is not set
+# CONFIG_FS_UNIONFS is not set
+
+#
+# System Logging
+#
+# CONFIG_SYSLOG is not set
+# CONFIG_SYSLOG_TIMESTAMP is not set
+
+#
+# Graphics Support
+#
+# CONFIG_NX is not set
+
+#
+# Memory Management
+#
+CONFIG_MM_SMALL=y
+CONFIG_MM_REGIONS=1
+# CONFIG_ARCH_HAVE_HEAP2 is not set
+# CONFIG_GRAN is not set
+
+#
+# Audio Support
+#
+# CONFIG_AUDIO is not set
+
+#
+# Wireless Support
+#
+
+#
+# Binary Loader
+#
+# CONFIG_BINFMT_DISABLE is not set
+# CONFIG_NXFLAT is not set
+# CONFIG_ELF is not set
+# CONFIG_BUILTIN is not set
+# CONFIG_PIC is not set
+# CONFIG_SYMTAB_ORDEREDBYNAME is not set
+
+#
+# Library Routines
+#
+
+#
+# Standard C Library Options
+#
+CONFIG_STDIO_BUFFER_SIZE=0
+CONFIG_STDIO_LINEBUFFER=y
+CONFIG_NUNGET_CHARS=0
+# CONFIG_LIBM is not set
+CONFIG_NOPRINTF_FIELDWIDTH=y
+# CONFIG_LIBC_FLOATINGPOINT is not set
+# CONFIG_LIBC_LONG_LONG is not set
+# CONFIG_LIBC_IOCTL_VARIADIC is not set
+CONFIG_LIB_RAND_ORDER=1
+# CONFIG_EOL_IS_CR is not set
+# CONFIG_EOL_IS_LF is not set
+# CONFIG_EOL_IS_BOTH_CRLF is not set
+CONFIG_EOL_IS_EITHER_CRLF=y
+# CONFIG_LIBC_EXECFUNCS is not set
+CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024
+CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048
+# CONFIG_LIBC_STRERROR is not set
+# CONFIG_LIBC_PERROR_STDOUT is not set
+CONFIG_ARCH_LOWPUTC=y
+# CONFIG_TIME_EXTENDED is not set
+CONFIG_LIB_SENDFILE_BUFSIZE=512
+# CONFIG_ARCH_ROMGETC is not set
+# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
+CONFIG_ARCH_HAVE_TLS=y
+# CONFIG_TLS is not set
+# CONFIG_LIBC_NETDB is not set
+
+#
+# Non-standard Library Support
+#
+# CONFIG_LIB_KBDCODEC is not set
+# CONFIG_LIB_SLCDCODEC is not set
+
+#
+# Basic CXX Support
+#
+# CONFIG_C99_BOOL8 is not set
+# CONFIG_HAVE_CXX is not set
+
+#
+# Application Configuration
+#
+
+#
+# CAN Utilities
+#
+
+#
+# Examples
+#
+# CONFIG_EXAMPLES_CHAT is not set
+# CONFIG_EXAMPLES_CONFIGDATA is not set
+# CONFIG_EXAMPLES_CPUHOG is not set
+# CONFIG_EXAMPLES_DHCPD is not set
+# CONFIG_EXAMPLES_ELF is not set
+# CONFIG_EXAMPLES_FTPC is not set
+# CONFIG_EXAMPLES_FTPD is not set
+# CONFIG_EXAMPLES_HELLO is not set
+# CONFIG_EXAMPLES_JSON is not set
+# CONFIG_EXAMPLES_HIDKBD is not set
+# CONFIG_EXAMPLES_KEYPADTEST is not set
+# CONFIG_EXAMPLES_IGMP is not set
+# CONFIG_EXAMPLES_MEDIA is not set
+# CONFIG_EXAMPLES_MM is not set
+# CONFIG_EXAMPLES_MODBUS is not set
+# CONFIG_EXAMPLES_MOUNT is not set
+# CONFIG_EXAMPLES_NRF24L01TERM is not set
+CONFIG_EXAMPLES_NSH=y
+# CONFIG_EXAMPLES_NULL is not set
+# CONFIG_EXAMPLES_NX is not set
+# CONFIG_EXAMPLES_NXTERM is not set
+# CONFIG_EXAMPLES_NXFFS is not set
+# CONFIG_EXAMPLES_NXHELLO is not set
+# CONFIG_EXAMPLES_NXIMAGE is not set
+# CONFIG_EXAMPLES_NXLINES is not set
+# CONFIG_EXAMPLES_NXTEXT is not set
+# CONFIG_EXAMPLES_OSTEST is not set
+# CONFIG_EXAMPLES_PCA9635 is not set
+# CONFIG_EXAMPLES_PIPE is not set
+# CONFIG_EXAMPLES_POLL is not set
+# CONFIG_EXAMPLES_PPPD is not set
+# CONFIG_EXAMPLES_POSIXSPAWN is not set
+# CONFIG_EXAMPLES_RGBLED is not set
+# CONFIG_EXAMPLES_RGMP is not set
+# CONFIG_EXAMPLES_SENDMAIL is not set
+# CONFIG_EXAMPLES_SERIALBLASTER is not set
+# CONFIG_EXAMPLES_SERIALRX is not set
+# CONFIG_EXAMPLES_SERLOOP is not set
+# CONFIG_EXAMPLES_SLCD is not set
+# CONFIG_EXAMPLES_SMART is not set
+# CONFIG_EXAMPLES_SMP is not set
+# CONFIG_EXAMPLES_TCPECHO is not set
+# CONFIG_EXAMPLES_TELNETD is not set
+# CONFIG_EXAMPLES_TIFF is not set
+# CONFIG_EXAMPLES_TOUCHSCREEN is not set
+# CONFIG_EXAMPLES_WEBSERVER is not set
+# CONFIG_EXAMPLES_USBTERM is not set
+# CONFIG_EXAMPLES_WATCHDOG is not set
+
+#
+# File System Utilities
+#
+# CONFIG_FSUTILS_INIFILE is not set
+
+#
+# GPS Utilities
+#
+# CONFIG_GPSUTILS_MINMEA_LIB is not set
+
+#
+# Graphics Support
+#
+# CONFIG_TIFF is not set
+# CONFIG_GRAPHICS_TRAVELER is not set
+
+#
+# Interpreters
+#
+# CONFIG_INTERPRETERS_FICL is not set
+# CONFIG_INTERPRETERS_PCODE is not set
+# CONFIG_INTERPRETERS_MICROPYTHON is not set
+
+#
+# FreeModBus
+#
+# CONFIG_MODBUS is not set
+
+#
+# Network Utilities
+#
+# CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_FTPC is not set
+# CONFIG_NETUTILS_JSON is not set
+# CONFIG_NETUTILS_SMTP is not set
+
+#
+# NSH Library
+#
+CONFIG_NSH_LIBRARY=y
+# CONFIG_NSH_MOTD is not set
+
+#
+# Command Line Configuration
+#
+CONFIG_NSH_READLINE=y
+# CONFIG_NSH_CLE is not set
+CONFIG_NSH_LINELEN=80
+CONFIG_NSH_DISABLE_SEMICOLON=y
+CONFIG_NSH_MAXARGUMENTS=6
+# CONFIG_NSH_ARGCAT is not set
+CONFIG_NSH_NESTDEPTH=3
+# CONFIG_NSH_DISABLEBG is not set
+
+#
+# Disable Individual commands
+#
+CONFIG_NSH_DISABLE_ADDROUTE=y
+CONFIG_NSH_DISABLE_BASENAME=y
+# CONFIG_NSH_DISABLE_CAT is not set
+CONFIG_NSH_DISABLE_CD=y
+CONFIG_NSH_DISABLE_CP=y
+# CONFIG_NSH_DISABLE_CMP is not set
+CONFIG_NSH_DISABLE_DATE=y
+CONFIG_NSH_DISABLE_DD=y
+CONFIG_NSH_DISABLE_DF=y
+CONFIG_NSH_DISABLE_DELROUTE=y
+CONFIG_NSH_DISABLE_DIRNAME=y
+# CONFIG_NSH_DISABLE_ECHO is not set
+# CONFIG_NSH_DISABLE_EXEC is not set
+# CONFIG_NSH_DISABLE_EXIT is not set
+# CONFIG_NSH_DISABLE_FREE is not set
+CONFIG_NSH_DISABLE_GET=y
+# CONFIG_NSH_DISABLE_HELP is not set
+# CONFIG_NSH_DISABLE_HEXDUMP is not set
+CONFIG_NSH_DISABLE_IFCONFIG=y
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+# CONFIG_NSH_DISABLE_KILL is not set
+CONFIG_NSH_DISABLE_LOSETUP=y
+CONFIG_NSH_DISABLE_LOSMART=y
+# CONFIG_NSH_DISABLE_LS is not set
+# CONFIG_NSH_DISABLE_MB is not set
+CONFIG_NSH_DISABLE_MKDIR=y
+# CONFIG_NSH_DISABLE_MKFIFO is not set
+CONFIG_NSH_DISABLE_MKRD=y
+# CONFIG_NSH_DISABLE_MH is not set
+CONFIG_NSH_DISABLE_MOUNT=y
+CONFIG_NSH_DISABLE_MV=y
+# CONFIG_NSH_DISABLE_MW is not set
+# CONFIG_NSH_DISABLE_PS is not set
+CONFIG_NSH_DISABLE_PUT=y
+# CONFIG_NSH_DISABLE_PWD is not set
+CONFIG_NSH_DISABLE_RM=y
+CONFIG_NSH_DISABLE_RMDIR=y
+# CONFIG_NSH_DISABLE_SET is not set
+# CONFIG_NSH_DISABLE_SH is not set
+# CONFIG_NSH_DISABLE_SLEEP is not set
+CONFIG_NSH_DISABLE_TIME=y
+# CONFIG_NSH_DISABLE_TEST is not set
+CONFIG_NSH_DISABLE_UMOUNT=y
+CONFIG_NSH_DISABLE_UNAME=y
+# CONFIG_NSH_DISABLE_UNSET is not set
+# CONFIG_NSH_DISABLE_USLEEP is not set
+CONFIG_NSH_DISABLE_WGET=y
+# CONFIG_NSH_DISABLE_XD is not set
+
+#
+# Configure Command Options
+#
+CONFIG_NSH_CODECS_BUFSIZE=128
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+CONFIG_NSH_FILEIOSIZE=64
+
+#
+# Scripting Support
+#
+CONFIG_NSH_DISABLESCRIPT=y
+
+#
+# Console Configuration
+#
+CONFIG_NSH_CONSOLE=y
+# CONFIG_NSH_ALTCONDEV is not set
+# CONFIG_NSH_ARCHINIT is not set
+# CONFIG_NSH_LOGIN is not set
+# CONFIG_NSH_CONSOLE_LOGIN is not set
+
+#
+# NxWidgets/NxWM
+#
+
+#
+# Platform-specific Support
+#
+# CONFIG_PLATFORM_CONFIGDATA is not set
+
+#
+# System Libraries and NSH Add-Ons
+#
+# CONFIG_SYSTEM_FREE is not set
+# CONFIG_SYSTEM_CLE is not set
+# CONFIG_SYSTEM_CUTERM is not set
+# CONFIG_SYSTEM_INSTALL is not set
+# CONFIG_SYSTEM_HEX2BIN is not set
+# CONFIG_SYSTEM_HEXED is not set
+# CONFIG_SYSTEM_RAMTEST is not set
+CONFIG_READLINE_HAVE_EXTMATCH=y
+CONFIG_SYSTEM_READLINE=y
+CONFIG_READLINE_ECHO=y
+# CONFIG_READLINE_TABCOMPLETION is not set
+# CONFIG_READLINE_CMD_HISTORY is not set
+# CONFIG_SYSTEM_SUDOKU is not set
+# CONFIG_SYSTEM_VI is not set
+# CONFIG_SYSTEM_UBLOXMODEM is not set
+# CONFIG_SYSTEM_ZMODEM is not set
diff --git a/configs/stm32f103-minimum/minnsh/setenv.sh b/configs/stm32f103-minimum/minnsh/setenv.sh
new file mode 100644
index 0000000000..73dfab5a4d
--- /dev/null
+++ b/configs/stm32f103-minimum/minnsh/setenv.sh
@@ -0,0 +1,100 @@
+#!/bin/bash
+# configs//stm32f103-minimum/nsh/setenv.sh
+#
+# Copyright (C) 2016 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+if [ "$_" = "$0" ] ; then
+ echo "You must source this script, not run it!" 1>&2
+ exit 1
+fi
+
+WD=`pwd`
+if [ ! -x "setenv.sh" ]; then
+ echo "This script must be executed from the top-level NuttX build directory"
+ exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then
+ export PATH_ORIG="${PATH}"
+fi
+
+# This is the Cygwin path to the location where I installed the CodeSourcery
+# toolchain under windows. You will also have to edit this if you install
+# the CodeSourcery toolchain in any other location
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
+# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
+
+# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors"
+# You can this free toolchain here https://launchpad.net/gcc-arm-embedded
+export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin"
+
+# This is the path to the location where I installed the devkitARM toolchain
+# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin"
+
+# This is the Cygwin path to the location where I build the buildroot
+# toolchain.
+# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin"
+
+# Add the path to the toolchain to the PATH varialble
+export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
+
+echo "PATH : ${PATH}"
--
GitLab
From ed1535f18846ebcd1744121b85de40dde5d25e3d Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Sat, 4 Jun 2016 07:52:56 -0600
Subject: [PATCH 053/400] Changes from review of last PR
---
arch/arm/src/lpc43xx/Kconfig | 2 +-
arch/arm/src/lpc43xx/Make.defs | 2 +-
arch/arm/src/lpc43xx/lpc43_gpio.c | 6 ++---
arch/arm/src/lpc43xx/lpc43_gpioint.c | 15 ++++++++-----
arch/arm/src/lpc43xx/lpc43_gpioint.h | 33 ++++++++++------------------
5 files changed, 25 insertions(+), 33 deletions(-)
diff --git a/arch/arm/src/lpc43xx/Kconfig b/arch/arm/src/lpc43xx/Kconfig
index c6df85ae35..d29fe32781 100644
--- a/arch/arm/src/lpc43xx/Kconfig
+++ b/arch/arm/src/lpc43xx/Kconfig
@@ -151,7 +151,7 @@ endchoice # LPC43XX Boot Configuration
menu "LPC43xx Peripheral Support"
-config GPIO_IRQ
+config LPC43_GPIO_IRQ
bool "GPIO interrupt support"
default n
---help---
diff --git a/arch/arm/src/lpc43xx/Make.defs b/arch/arm/src/lpc43xx/Make.defs
index 018b929d4d..60e0ad3ed0 100644
--- a/arch/arm/src/lpc43xx/Make.defs
+++ b/arch/arm/src/lpc43xx/Make.defs
@@ -118,7 +118,7 @@ ifeq ($(CONFIG_LPC43_GPDMA),y)
CHIP_CSRCS += lpc43_gpdma.c
endif
-ifeq ($(CONFIG_GPIO_IRQ),y)
+ifeq ($(CONFIG_LPC43_GPIO_IRQ),y)
CHIP_CSRCS += lpc43_gpioint.c
endif
diff --git a/arch/arm/src/lpc43xx/lpc43_gpio.c b/arch/arm/src/lpc43xx/lpc43_gpio.c
index 49b7f9b27f..cda1757cd3 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpio.c
+++ b/arch/arm/src/lpc43xx/lpc43_gpio.c
@@ -49,7 +49,7 @@
#include "up_arch.h"
#include "lpc43_gpio.h"
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC43_GPIO_IRQ
#include "lpc43_gpioint.h"
#endif
@@ -185,14 +185,14 @@ int lpc43_gpio_config(uint16_t gpiocfg)
case GPIO_MODE_PININTR: /* GPIO pin interrupt */
lpc43_configinput(gpiocfg, port, pin);
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC43_GPIO_IRQ
ret = lpc43_gpioint_pinconfig(gpiocfg);
#endif
break;
case GPIO_MODE_GRPINTR: /* GPIO group interrupt */
lpc43_configinput(gpiocfg, port, pin);
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC43_GPIO_IRQ
ret = lpc43_gpioint_grpconfig(gpiocfg);
#endif
break;
diff --git a/arch/arm/src/lpc43xx/lpc43_gpioint.c b/arch/arm/src/lpc43xx/lpc43_gpioint.c
index 029e2aec20..39d664aabe 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpioint.c
+++ b/arch/arm/src/lpc43xx/lpc43_gpioint.c
@@ -71,7 +71,7 @@
#include "lpc43_gpio.h"
#include "lpc43_gpioint.h"
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC43_GPIO_IRQ
/****************************************************************************
* Pre-processor Definitions
@@ -226,9 +226,11 @@ int lpc43_gpioint_pinconfig(uint16_t gpiocfg)
putreg32(regval, LPC43_GPIOINT_ISEL);
- /* Configure the active high level or rising edge */
-
- /* TODO: this works for edge sensitive, but not level sensitive, active level is only controlled in IENF */
+ /* Configure the active high level or rising edge
+ *
+ * TODO: this works for edge sensitive, but not level sensitive, active
+ * level is only controlled in IENF.
+ */
regval = getreg32(LPC43_GPIOINT_IENR);
if (GPIO_IS_ACTIVE_HI(gpiocfg))
@@ -342,10 +344,11 @@ int lpc43_gpioint_ack(uint8_t intnumber)
{
uint32_t regval;
- regval = getreg32(LPC43_GPIOINT_IST);
+ regval = getreg32(LPC43_GPIOINT_IST);
regval |= (1 << intnumber);
putreg32(regval, LPC43_GPIOINT_IST);
+
return OK;
}
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_LPC43_GPIO_IRQ */
diff --git a/arch/arm/src/lpc43xx/lpc43_gpioint.h b/arch/arm/src/lpc43xx/lpc43_gpioint.h
index ec34649455..ae479f83c6 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpioint.h
+++ b/arch/arm/src/lpc43xx/lpc43_gpioint.h
@@ -1,7 +1,7 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/lpc43xx/lpc43_gpioint.h
*
- * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -31,7 +31,8 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
+
/* GPIO pin interrupts
*
* From all available GPIO pins, up to eight pins can be selected in the system
@@ -52,31 +53,19 @@
#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_GPIOINT_H
#define __ARCH_ARM_SRC_LPC43XX_LPC43_GPIOINT_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include
#include "chip.h"
#include "chip/lpc43_gpio.h"
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC43_GPIO_IRQ
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
/****************************************************************************
* Name: lpc43_gpioint_grpinitialize
@@ -152,5 +141,5 @@ int lpc43_gpioint_grpconfig(uint16_t gpiocfg);
int lpc43_gpioint_ack(uint8_t intnumber);
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_LPC43_GPIO_IRQ */
#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_GPIOINT_H */
--
GitLab
From 184ca294e8ae1065d8cec59baff32f53e21d2c83 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Sat, 4 Jun 2016 07:59:02 -0600
Subject: [PATCH 054/400] Rename all references to up_lowgetc
---
arch/arm/src/kl/kl_lowgetc.c | 22 +---------------------
arch/arm/src/kl/kl_lowgetc.h | 10 +---------
arch/arm/src/lpc11xx/lpc11_lowgetc.c | 22 +---------------------
arch/arm/src/lpc11xx/lpc11_lowgetc.h | 10 +---------
arch/z16/src/common/up_internal.h | 2 +-
arch/z16/src/z16f/z16f_lowuart.S | 20 ++++++++++----------
6 files changed, 15 insertions(+), 71 deletions(-)
diff --git a/arch/arm/src/kl/kl_lowgetc.c b/arch/arm/src/kl/kl_lowgetc.c
index f1c02981d2..8033ee732f 100644
--- a/arch/arm/src/kl/kl_lowgetc.c
+++ b/arch/arm/src/kl/kl_lowgetc.c
@@ -77,32 +77,12 @@
# define CONSOLE_PARITY CONFIG_UART2_PARITY
#endif
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: up_lowgetc
+ * Name: kl_lowgetc
*
* Description:
* Input one byte from the serial console
diff --git a/arch/arm/src/kl/kl_lowgetc.h b/arch/arm/src/kl/kl_lowgetc.h
index 4ed52365a2..625f534964 100644
--- a/arch/arm/src/kl/kl_lowgetc.h
+++ b/arch/arm/src/kl/kl_lowgetc.h
@@ -43,14 +43,6 @@
#include
#include "kl_config.h"
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
/************************************************************************************
* Public Data
************************************************************************************/
@@ -67,7 +59,7 @@ extern "C"
#endif
/************************************************************************************
- * Public Functions
+ * Public Function Prototypes
************************************************************************************/
#ifdef HAVE_SERIAL_CONSOLE
diff --git a/arch/arm/src/lpc11xx/lpc11_lowgetc.c b/arch/arm/src/lpc11xx/lpc11_lowgetc.c
index a0a12b6108..a4c0f81c54 100644
--- a/arch/arm/src/lpc11xx/lpc11_lowgetc.c
+++ b/arch/arm/src/lpc11xx/lpc11_lowgetc.c
@@ -79,32 +79,12 @@
# define CONSOLE_PARITY CONFIG_UART2_PARITY
#endif
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: up_lowgetc
+ * Name: lpc11_lowgetc
*
* Description:
* Input one byte from the serial console
diff --git a/arch/arm/src/lpc11xx/lpc11_lowgetc.h b/arch/arm/src/lpc11xx/lpc11_lowgetc.h
index 4c94f39b78..932898f395 100644
--- a/arch/arm/src/lpc11xx/lpc11_lowgetc.h
+++ b/arch/arm/src/lpc11xx/lpc11_lowgetc.h
@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/lpc11/lpc11_lowgetc.h
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -43,14 +43,6 @@
#include
#include "lpc11_serial.h"
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
/************************************************************************************
* Public Data
************************************************************************************/
diff --git a/arch/z16/src/common/up_internal.h b/arch/z16/src/common/up_internal.h
index bd6f36ca9f..64a5302a42 100644
--- a/arch/z16/src/common/up_internal.h
+++ b/arch/z16/src/common/up_internal.h
@@ -58,7 +58,7 @@
#undef CONFIG_SUPPRESS_UART_CONFIG /* Do not reconfig UART */
#undef CONFIG_DUMP_ON_EXIT /* Dump task state on exit */
#undef CONFIG_Z16_LOWPUTC /* Support up_lowputc for debug */
-#undef CONFIG_Z16_LOWGETC /* support up_lowgetc for debug */
+#undef CONFIG_Z16_LOWGETC /* support z16_lowgetc for debug */
/* Determine which (if any) console driver to use. If a console is enabled
* and no other console device is specified, then a serial console is
diff --git a/arch/z16/src/z16f/z16f_lowuart.S b/arch/z16/src/z16f/z16f_lowuart.S
index 161d5ac924..ef7c31a6ca 100644
--- a/arch/z16/src/z16f/z16f_lowuart.S
+++ b/arch/z16/src/z16f/z16f_lowuart.S
@@ -70,7 +70,7 @@
xdef _up_lowputc
#endif
#ifdef CONFIG_Z16_LOWGETC
- xdef _up_lowgetc
+ xdef _z16_lowgetc
#endif
/*************************************************************************
@@ -222,7 +222,7 @@ _z16f_xmitc1:
#endif /* CONFIG_Z16_LOWPUTC */
/*************************************************************************
- * Name: _up_lowgetc
+ * Name: _z16_lowgetc
*
* Description:
* Get a character from the serial port
@@ -236,34 +236,34 @@ _z16f_xmitc1:
*************************************************************************/
#ifdef CONFIG_Z16_LOWGETC
-_up_lowgetc:
-_up_lowgetc1:
+_z16_lowgetc:
+_z16_lowgetc1:
#ifdef HAVE_Z16F_SERIAL_CONSOLE
ld r0, #Z16F_UARTSTAT0_RDA /* RDA=Receive data available */
#ifdef CONFIG_UART1_SERIAL_CONSOLE
tm.b Z16F_UART1_STAT0, r0
- jp eq, _up_lowgetc1 /* While (!Z16F_UART1_STAT0 & RDA)) */
+ jp eq, _z16_lowgetc1 /* While (!Z16F_UART1_STAT0 & RDA)) */
ld.ub r0, Z16F_UART1_RXD /* r0 = Z16F_UART1_RXD */
#else
tm.b Z16F_UART0_STAT0,r0 /* While (!Z16F_UART0_STAT0 & RDA) */
- jp eq, _up_lowgetc1
+ jp eq, _z16_lowgetc1
ld.ub r0, Z16F_UART0_RXD /* r0 = Z16F_UART0_RXD */
#endif
cp r0, #%0d /* Test for '\r' */
- jp eq, _up_lowgetc2
+ jp eq, _z16_lowgetc2
cp r0, #%0d /* Test \r + high bit */
- jp ne, _up_lowgetc3
+ jp ne, _z16_lowgetc3
-_up_lowgetc2:
+_z16_lowgetc2:
ld r0, #%0a /* Convert '\r' to '\n' */
-_up_lowgetc3: /* Return value in r0 */
+_z16_lowgetc3: /* Return value in r0 */
#endif /* HAVE_Z16F_SERIAL_CONSOLE */
ret /* Return */
--
GitLab
From 4965d0dc9967847e76795ef625de9a0e49228a80 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Sat, 4 Jun 2016 11:29:27 -0600
Subject: [PATCH 055/400] KL and LPC11: Perform similar name change as for
STM32: xyz_lowputc -> up_putc
---
arch/arm/src/kl/Make.defs | 2 +-
arch/arm/src/kl/{kl_lowgetc.c => kl_getc.c} | 33 ++++-----------
arch/arm/src/kl/{kl_lowgetc.h => kl_getc.h} | 40 ++++---------------
arch/arm/src/kl/kl_serial.c | 19 +--------
arch/arm/src/lpc11xx/Make.defs | 2 +-
.../lpc11xx/{lpc11_lowgetc.c => lpc11_getc.c} | 30 +++-----------
.../lpc11xx/{lpc11_lowgetc.h => lpc11_getc.h} | 37 +++--------------
arch/arm/src/lpc11xx/lpc11_serial.c | 16 --------
arch/arm/src/stm32/Make.defs | 2 +-
arch/arm/src/stm32/stm32.h | 2 +-
.../stm32/{stm32_lowgetc.c => stm32_getc.c} | 2 +-
.../stm32/{stm32_lowgetc.h => stm32_getc.h} | 8 ++--
12 files changed, 36 insertions(+), 157 deletions(-)
rename arch/arm/src/kl/{kl_lowgetc.c => kl_getc.c} (77%)
rename arch/arm/src/kl/{kl_lowgetc.h => kl_getc.h} (69%)
rename arch/arm/src/lpc11xx/{lpc11_lowgetc.c => lpc11_getc.c} (79%)
rename arch/arm/src/lpc11xx/{lpc11_lowgetc.h => lpc11_getc.h} (70%)
rename arch/arm/src/stm32/{stm32_lowgetc.c => stm32_getc.c} (99%)
rename arch/arm/src/stm32/{stm32_lowgetc.h => stm32_getc.h} (91%)
diff --git a/arch/arm/src/kl/Make.defs b/arch/arm/src/kl/Make.defs
index 68c58af802..39308b6948 100644
--- a/arch/arm/src/kl/Make.defs
+++ b/arch/arm/src/kl/Make.defs
@@ -70,7 +70,7 @@ CMN_CSRCS += up_dumpnvic.c
endif
CHIP_ASRCS =
-CHIP_CSRCS = kl_clockconfig.c kl_gpio.c kl_idle.c kl_irq.c kl_lowgetc.c
+CHIP_CSRCS = kl_clockconfig.c kl_gpio.c kl_idle.c kl_irq.c kl_getc.c
CHIP_CSRCS += kl_lowputc.c kl_serial.c kl_start.c kl_cfmconfig.c
ifneq ($(CONFIG_SCHED_TICKLESS),y)
diff --git a/arch/arm/src/kl/kl_lowgetc.c b/arch/arm/src/kl/kl_getc.c
similarity index 77%
rename from arch/arm/src/kl/kl_lowgetc.c
rename to arch/arm/src/kl/kl_getc.c
index 8033ee732f..cee3195dd0 100644
--- a/arch/arm/src/kl/kl_lowgetc.c
+++ b/arch/arm/src/kl/kl_getc.c
@@ -1,7 +1,7 @@
/****************************************************************************
- * arch/arm/src/kl/kl_lowgetc.c
+ * arch/arm/src/kl/kl_getc.c
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -41,40 +41,23 @@
#include
-#include
-#include
-
-#include "up_internal.h"
#include "up_arch.h"
#include "kl_config.h"
-#include "kl_lowgetc.h"
-
-#include "chip/kl_uart.h"
+#include "kl_getc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* Select UART parameters for the selected console */
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
# define CONSOLE_BASE KL_UART0_BASE
-# define CONSOLE_FREQ BOARD_CORECLK_FREQ
-# define CONSOLE_BAUD CONFIG_UART0_BAUD
-# define CONSOLE_BITS CONFIG_UART0_BITS
-# define CONSOLE_PARITY CONFIG_UART0_PARITY
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
# define CONSOLE_BASE KL_UART1_BASE
-# define CONSOLE_FREQ BOARD_BUSCLK_FREQ
-# define CONSOLE_BAUD CONFIG_UART1_BAUD
-# define CONSOLE_BITS CONFIG_UART1_BITS
-# define CONSOLE_PARITY CONFIG_UART1_PARITY
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
# define CONSOLE_BASE KL_UART2_BASE
-# define CONSOLE_FREQ BOARD_BUSCLK_FREQ
-# define CONSOLE_BAUD CONFIG_UART2_BAUD
-# define CONSOLE_BITS CONFIG_UART2_BITS
-# define CONSOLE_PARITY CONFIG_UART2_PARITY
#endif
/****************************************************************************
@@ -82,14 +65,14 @@
****************************************************************************/
/****************************************************************************
- * Name: kl_lowgetc
+ * Name: up_getc
*
* Description:
* Input one byte from the serial console
*
****************************************************************************/
-int kl_lowgetc(void)
+int up_getc(void)
{
uint8_t ch = 0;
@@ -98,11 +81,11 @@ int kl_lowgetc(void)
* we have data in the buffer to read.
*/
- while ((getreg8(CONSOLE_BASE+KL_UART_S1_OFFSET) & UART_S1_RDRF) == 0);
+ while ((getreg8(CONSOLE_BASE + KL_UART_S1_OFFSET) & UART_S1_RDRF) == 0);
/* Then read a character from the UART data register */
- ch = getreg8(CONSOLE_BASE+KL_UART_D_OFFSET);
+ ch = getreg8(CONSOLE_BASE + KL_UART_D_OFFSET);
#endif
return (int)ch;
diff --git a/arch/arm/src/kl/kl_lowgetc.h b/arch/arm/src/kl/kl_getc.h
similarity index 69%
rename from arch/arm/src/kl/kl_lowgetc.h
rename to arch/arm/src/kl/kl_getc.h
index 625f534964..aff6b2a0b3 100644
--- a/arch/arm/src/kl/kl_lowgetc.h
+++ b/arch/arm/src/kl/kl_getc.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kl/kl_lowgetc.h
+ * arch/arm/src/kl/kl_getc.h
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,42 +33,16 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KL_KINETIS_LOWGETC_H
-#define __ARCH_ARM_SRC_KL_KINETIS_LOWGETC_H
+#ifndef __ARCH_ARM_SRC_KL_KINETIS_GETC_H
+#define __ARCH_ARM_SRC_KL_KINETIS_GETC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include
-#include "kl_config.h"
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-#undef EXTERN
-#if defined(__cplusplus)
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#ifdef HAVE_SERIAL_CONSOLE
-int kl_lowgetc(void);
-#endif
+#include "kl_config.h"
+#include "chip/kl_uart.h"
-#undef EXTERN
-#if defined(__cplusplus)
-}
-#endif
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_KL_KINETIS_LOWGETC_H */
+#endif /* __ARCH_ARM_SRC_KL_KINETIS_GETC_H */
diff --git a/arch/arm/src/kl/kl_serial.c b/arch/arm/src/kl/kl_serial.c
index fb135ca795..fab56a34d5 100644
--- a/arch/arm/src/kl/kl_serial.c
+++ b/arch/arm/src/kl/kl_serial.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/kl/kl_serial.c
*
- * Copyright (C) 2013-2012 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013-2012, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -59,15 +59,14 @@
#include "kl_config.h"
#include "kl_lowputc.h"
-#include "kl_lowgetc.h"
#include "chip.h"
#include "kl_gpio.h"
#include "chip/kl_uart.h"
-
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* Some sanity checks *******************************************************/
/* Is there at least one UART enabled and configured as a RS-232 device? */
@@ -958,18 +957,4 @@ int up_putc(int ch)
return ch;
}
-/****************************************************************************
- * Name: up_getc
- *
- * Description:
- * Provide priority, low-level access to support OS debug writes
- *
- ****************************************************************************/
-
-int up_getc(void)
-{
- /* Check for LF */
-
- return kl_lowgetc();
-}
#endif /* USE_SERIALDRIVER */
diff --git a/arch/arm/src/lpc11xx/Make.defs b/arch/arm/src/lpc11xx/Make.defs
index a40c143545..fd0e046964 100644
--- a/arch/arm/src/lpc11xx/Make.defs
+++ b/arch/arm/src/lpc11xx/Make.defs
@@ -71,7 +71,7 @@ endif
CHIP_ASRCS =
CHIP_CSRCS = lpc11_clockconfig.c lpc11_gpio.c lpc11_i2c.c lpc11_idle.c
-CHIP_CSRCS += lpc11_irq.c lpc11_lowputc.c lpc11_lowgetc.c lpc11_serial.c
+CHIP_CSRCS += lpc11_irq.c lpc11_lowputc.c lpc11_getc.c lpc11_serial.c
CHIP_CSRCS += lpc11_spi.c lpc11_ssp.c lpc11_start.c
# Configuration-dependent LPC11xx files
diff --git a/arch/arm/src/lpc11xx/lpc11_lowgetc.c b/arch/arm/src/lpc11xx/lpc11_getc.c
similarity index 79%
rename from arch/arm/src/lpc11xx/lpc11_lowgetc.c
rename to arch/arm/src/lpc11xx/lpc11_getc.c
index a4c0f81c54..9d733b2e3e 100644
--- a/arch/arm/src/lpc11xx/lpc11_lowgetc.c
+++ b/arch/arm/src/lpc11xx/lpc11_getc.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/lpc11/lpc11_lowgetc.c
+ * arch/arm/src/lpc11/lpc11_getc.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -41,42 +41,22 @@
#include
-#include
-#include
-
-#include "up_internal.h"
#include "up_arch.h"
-#include "chip/lpc11_syscon.h"
-#include "chip/lpc11_uart.h"
-
-#include "lpc11_gpio.h"
-#include "lpc11_lowgetc.h"
-#include "lpc11_serial.h"
+#include "lpc11_getc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* Select UART parameters for the selected console */
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
# define CONSOLE_BASE LPC11_UART0_BASE
-# define CONSOLE_FREQ BOARD_CORECLK_FREQ
-# define CONSOLE_BAUD CONFIG_UART0_BAUD
-# define CONSOLE_BITS CONFIG_UART0_BITS
-# define CONSOLE_PARITY CONFIG_UART0_PARITY
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
# define CONSOLE_BASE LPC11_UART1_BASE
-# define CONSOLE_FREQ BOARD_BUSCLK_FREQ
-# define CONSOLE_BAUD CONFIG_UART1_BAUD
-# define CONSOLE_BITS CONFIG_UART1_BITS
-# define CONSOLE_PARITY CONFIG_UART1_PARITY
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
# define CONSOLE_BASE LPC11_UART2_BASE
-# define CONSOLE_FREQ BOARD_BUSCLK_FREQ
-# define CONSOLE_BAUD CONFIG_UART2_BAUD
-# define CONSOLE_BITS CONFIG_UART2_BITS
-# define CONSOLE_PARITY CONFIG_UART2_PARITY
#endif
/****************************************************************************
@@ -84,14 +64,14 @@
****************************************************************************/
/****************************************************************************
- * Name: lpc11_lowgetc
+ * Name: up_getc
*
* Description:
* Input one byte from the serial console
*
****************************************************************************/
-int lpc11_lowgetc(void)
+int up_getc(void)
{
uint8_t ch = 0;
diff --git a/arch/arm/src/lpc11xx/lpc11_lowgetc.h b/arch/arm/src/lpc11xx/lpc11_getc.h
similarity index 70%
rename from arch/arm/src/lpc11xx/lpc11_lowgetc.h
rename to arch/arm/src/lpc11xx/lpc11_getc.h
index 932898f395..e00864bfc4 100644
--- a/arch/arm/src/lpc11xx/lpc11_lowgetc.h
+++ b/arch/arm/src/lpc11xx/lpc11_getc.h
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/arm/src/lpc11/lpc11_lowgetc.h
+ * arch/arm/src/lpc11/lpc11_getc.h
*
* Copyright (C) 2015, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_LOWGETC_H
-#define __ARCH_ARM_SRC_LPC11XX_LPC11_LOWGETC_H
+#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_GETC_H
+#define __ARCH_ARM_SRC_LPC11XX_LPC11_GETC_H
/************************************************************************************
* Included Files
@@ -42,33 +42,6 @@
#include
#include "lpc11_serial.h"
+#include "chip/lpc11_uart.h"
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-#undef EXTERN
-#if defined(__cplusplus)
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#ifdef HAVE_SERIAL_CONSOLE
-int lpc11_lowgetc(void);
-#endif
-
-#undef EXTERN
-#if defined(__cplusplus)
-}
-#endif
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_LOWGETC_H */
+#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_GETC_H */
diff --git a/arch/arm/src/lpc11xx/lpc11_serial.c b/arch/arm/src/lpc11xx/lpc11_serial.c
index 6bbd488a3e..86e3feb11c 100644
--- a/arch/arm/src/lpc11xx/lpc11_serial.c
+++ b/arch/arm/src/lpc11xx/lpc11_serial.c
@@ -64,7 +64,6 @@
#include "chip.h"
#include "chip/lpc11_uart.h"
#include "lpc11_gpio.h"
-#include "lpc11_lowgetc.h"
#include "lpc11_serial.h"
/****************************************************************************
@@ -1041,19 +1040,4 @@ int up_putc(int ch)
return ch;
}
-/****************************************************************************
- * Name: up_getc
- *
- * Description:
- * Provide priority, low-level access to support OS debug writes
- *
- ****************************************************************************/
-
-int up_getc(void)
-{
- /* Check for LF */
-
- return lpc11_lowgetc();
-}
-
#endif /* USE_SERIALDRIVER */
diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs
index 2cc901fb2c..0b691c270d 100644
--- a/arch/arm/src/stm32/Make.defs
+++ b/arch/arm/src/stm32/Make.defs
@@ -110,7 +110,7 @@ CHIP_ASRCS =
CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c
CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c
-CHIP_CSRCS += stm32_irq.c stm32_dma.c stm32_lowputc.c stm32_lowgetc.c
+CHIP_CSRCS += stm32_irq.c stm32_dma.c stm32_lowputc.c stm32_getc.c
CHIP_CSRCS += stm32_serial.c stm32_spi.c stm32_sdio.c stm32_tim.c
CHIP_CSRCS += stm32_waste.c stm32_ccm.c stm32_uid.c stm32_capture.c
diff --git a/arch/arm/src/stm32/stm32.h b/arch/arm/src/stm32/stm32.h
index 8e75e4e9d7..7ae058ee05 100644
--- a/arch/arm/src/stm32/stm32.h
+++ b/arch/arm/src/stm32/stm32.h
@@ -92,7 +92,7 @@
#include "stm32_usbdev.h"
#include "stm32_wdg.h"
#include "stm32_lowputc.h"
-#include "stm32_lowgetc.h"
+#include "stm32_getc.h"
#include "stm32_eth.h"
#endif /* __ARCH_ARM_SRC_STM32_STM32_H */
diff --git a/arch/arm/src/stm32/stm32_lowgetc.c b/arch/arm/src/stm32/stm32_getc.c
similarity index 99%
rename from arch/arm/src/stm32/stm32_lowgetc.c
rename to arch/arm/src/stm32/stm32_getc.c
index 4e080b828a..e5fbb0fa3d 100644
--- a/arch/arm/src/stm32/stm32_lowgetc.c
+++ b/arch/arm/src/stm32/stm32_getc.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/stm32/stm32_lowgetc.c
+ * arch/arm/src/stm32/stm32_getc.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/arm/src/stm32/stm32_lowgetc.h b/arch/arm/src/stm32/stm32_getc.h
similarity index 91%
rename from arch/arm/src/stm32/stm32_lowgetc.h
rename to arch/arm/src/stm32/stm32_getc.h
index 624e6272f4..651165fba5 100644
--- a/arch/arm/src/stm32/stm32_lowgetc.h
+++ b/arch/arm/src/stm32/stm32_getc.h
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/arm/src/stm32/stm32_lowgetc.h
+ * arch/arm/src/stm32/stm32_getc.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_STM32_STM32_LOWGETC_H
-#define __ARCH_ARM_SRC_STM32_STM32_LOWGETC_H
+#ifndef __ARCH_ARM_SRC_STM32_STM32_GETC_H
+#define __ARCH_ARM_SRC_STM32_STM32_GETC_H
/************************************************************************************
* Included Files
@@ -44,4 +44,4 @@
#include "chip.h"
-#endif /* __ARCH_ARM_SRC_STM32_STM32_LOWGETC_H */
+#endif /* __ARCH_ARM_SRC_STM32_STM32_GETC_H */
--
GitLab
From 6b84637a5ba6a61058e68c7148322e7d7a6f3b35 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Sat, 4 Jun 2016 13:04:13 -0600
Subject: [PATCH 056/400] Update some comments
---
arch/arm/src/kl/kl_getc.c | 4 ++++
arch/arm/src/lpc11xx/lpc11_getc.c | 6 +++++-
arch/arm/src/stm32/stm32_getc.c | 4 ++++
3 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm/src/kl/kl_getc.c b/arch/arm/src/kl/kl_getc.c
index cee3195dd0..8b63ec217d 100644
--- a/arch/arm/src/kl/kl_getc.c
+++ b/arch/arm/src/kl/kl_getc.c
@@ -70,6 +70,10 @@
* Description:
* Input one byte from the serial console
*
+ * REVIST: If used with the serial driver enabled, then this could
+ * interfere with the serial driver operations. Serial interrupts should
+ * be disabled when this function executes in that case.
+ *
****************************************************************************/
int up_getc(void)
diff --git a/arch/arm/src/lpc11xx/lpc11_getc.c b/arch/arm/src/lpc11xx/lpc11_getc.c
index 9d733b2e3e..f809e9d343 100644
--- a/arch/arm/src/lpc11xx/lpc11_getc.c
+++ b/arch/arm/src/lpc11xx/lpc11_getc.c
@@ -67,7 +67,11 @@
* Name: up_getc
*
* Description:
- * Input one byte from the serial console
+ * Input one byte from the serial console.
+ *
+ * REVIST: If used with the serial driver enabled, then this could
+ * interfere with the serial driver operations. Serial interrupts should
+ * be disabled when this function executes in that case.
*
****************************************************************************/
diff --git a/arch/arm/src/stm32/stm32_getc.c b/arch/arm/src/stm32/stm32_getc.c
index e5fbb0fa3d..de9020bab4 100644
--- a/arch/arm/src/stm32/stm32_getc.c
+++ b/arch/arm/src/stm32/stm32_getc.c
@@ -89,6 +89,10 @@
* Description:
* Read one byte from the serial console
*
+ * REVIST: If used with the serial driver enabled, then this could
+ * interfere with the serial driver operations. Serial interrupts should
+ * be disabled when this function executes in that case.
+ *
****************************************************************************/
int up_getc(void)
--
GitLab
From 1c4d0686c8d6a881c8ae2c3574b80e5faea79b79 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Sat, 4 Jun 2016 16:05:36 -0600
Subject: [PATCH 057/400] LPC43xx: Fill out some missing GPIO interrupt logic
---
arch/arm/src/lpc43xx/Kconfig | 13 +++---
arch/arm/src/lpc43xx/lpc43_gpioint.c | 68 ++++++++++++++++++----------
2 files changed, 50 insertions(+), 31 deletions(-)
diff --git a/arch/arm/src/lpc43xx/Kconfig b/arch/arm/src/lpc43xx/Kconfig
index d29fe32781..9a2bcad916 100644
--- a/arch/arm/src/lpc43xx/Kconfig
+++ b/arch/arm/src/lpc43xx/Kconfig
@@ -150,13 +150,6 @@ endchoice # LPC43XX Boot Configuration
menu "LPC43xx Peripheral Support"
-
-config LPC43_GPIO_IRQ
- bool "GPIO interrupt support"
- default n
- ---help---
- Enable support for GPIO interrupts
-
config LPC43_ADC0
bool "ADC0"
default n
@@ -321,6 +314,12 @@ config LPC43_WWDT
endmenu # LPC43xx Peripheral Support
+config LPC43_GPIO_IRQ
+ bool "GPIO interrupt support"
+ default n
+ ---help---
+ Enable support for GPIO interrupts
+
if LPC43_ETHERNET
menu "Ethernet MAC configuration"
diff --git a/arch/arm/src/lpc43xx/lpc43_gpioint.c b/arch/arm/src/lpc43xx/lpc43_gpioint.c
index 39d664aabe..328a62c85c 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpioint.c
+++ b/arch/arm/src/lpc43xx/lpc43_gpioint.c
@@ -181,6 +181,9 @@ int lpc43_gpioint_pinconfig(uint16_t gpiocfg)
unsigned int pinint = ((gpiocfg & GPIO_PININT_MASK) >> GPIO_PININT_SHIFT);
uint32_t bitmask = (1 << pinint);
uint32_t regval;
+ uint32_t isel;
+ uint32_t einr;
+ uint32_t einf;
DEBUGASSERT(port < NUM_GPIO_PORTS && pin < NUM_GPIO_PINS && GPIO_IS_PININT(gpiocfg));
@@ -226,37 +229,54 @@ int lpc43_gpioint_pinconfig(uint16_t gpiocfg)
putreg32(regval, LPC43_GPIOINT_ISEL);
- /* Configure the active high level or rising edge
+ /* Configure the active level or rising/falling edge
*
- * TODO: this works for edge sensitive, but not level sensitive, active
- * level is only controlled in IENF.
+ * ISEL
+ * 0 = Edge sensitive
+ * 1 = Level sensitive
+ * EINR 0-7:
+ * 0 = Disable rising edge or level interrupt.
+ * 1 = Enable rising edge or level interrupt.
+ * EINF 0-7:
+ * 0 = Disable falling edge interrupt or set active interrupt level
+ * LOW.
+ * 1 = Enable falling edge interrupt enabled or set active interrupt
+ * level HIGH
*/
- regval = getreg32(LPC43_GPIOINT_IENR);
- if (GPIO_IS_ACTIVE_HI(gpiocfg))
- {
- regval |= bitmask;
- }
- else
- {
- regval &= ~bitmask;
- }
-
- putreg32(regval, LPC43_GPIOINT_IENR);
+ isel = getreg32(LPC43_GPIOINT_ISEL) & ~bitmask;
+ einr = getreg32(LPC43_GPIOINT_IENR) & ~bitmask;
+ einf = getreg32(LPC43_GPIOINT_IENF) & ~bitmask;
- /* Configure the active high low or falling edge */
-
- regval = getreg32(LPC43_GPIOINT_IENF);
- if (GPIO_IS_ACTIVE_LOW(gpiocfg))
+ switch (gpiocfg & GPIO_INT_MASK)
{
- regval |= bitmask;
- }
- else
- {
- regval &= ~bitmask;
+ case GPIO_INT_LEVEL_HI:
+ einf |= bitmask; /* Enable active level HI */
+ case GPIO_INT_LEVEL_LOW:
+ isel |= bitmask; /* Level sensitive */
+ einr |= bitmask; /* Enable level interrupt */
+ break;
+
+ case GPIO_INT_EDGE_RISING:
+ einr |= bitmask; /* Enable rising edge interrupt */
+ break;
+
+ case GPIO_INT_EDGE_BOTH:
+ einr |= bitmask; /* Enable rising edge interrupt */
+ case GPIO_INT_EDGE_FALLING:
+ einf |= bitmask; /* Enable falling edge interrupt */
+ break;
+
+ /* Default is edge sensitive but with both edges disabled. */
+
+ default:
+ break;
}
- putreg32(regval, LPC43_GPIOINT_IENF);
+ putreg32(isel, LPC43_GPIOINT_ISEL);
+ putreg32(einr, LPC43_GPIOINT_IENR);
+ putreg32(einf, LPC43_GPIOINT_IENF);
+
return OK;
}
--
GitLab
From 7671087abcc59a52ac604c2549328f9ddeca4826 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Sat, 4 Jun 2016 16:36:27 -0600
Subject: [PATCH 058/400] LPC32xx GPIO interrupts: Remove some old logic that
should not be there.
---
arch/arm/src/lpc43xx/lpc43_gpioint.c | 32 ++++++++--------------------
1 file changed, 9 insertions(+), 23 deletions(-)
diff --git a/arch/arm/src/lpc43xx/lpc43_gpioint.c b/arch/arm/src/lpc43xx/lpc43_gpioint.c
index 328a62c85c..bfe660070e 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpioint.c
+++ b/arch/arm/src/lpc43xx/lpc43_gpioint.c
@@ -180,7 +180,7 @@ int lpc43_gpioint_pinconfig(uint16_t gpiocfg)
unsigned int pin = ((gpiocfg & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
unsigned int pinint = ((gpiocfg & GPIO_PININT_MASK) >> GPIO_PININT_SHIFT);
uint32_t bitmask = (1 << pinint);
- uint32_t regval;
+ uint32_t pinsel;
uint32_t isel;
uint32_t einr;
uint32_t einf;
@@ -200,34 +200,20 @@ int lpc43_gpioint_pinconfig(uint16_t gpiocfg)
if (pinint < 4)
{
- regval = getreg32(LPC43_SCU_PINTSEL0);
- regval &= ~SCU_PINTSEL0_MASK(pinint);
- regval |= ((pin << SCU_PINTSEL0_INTPIN_SHIFT(pinint)) |
+ pinsel = getreg32(LPC43_SCU_PINTSEL0);
+ pinsel &= ~SCU_PINTSEL0_MASK(pinint);
+ pinsel |= ((pin << SCU_PINTSEL0_INTPIN_SHIFT(pinint)) |
(port << SCU_PINTSEL0_PORTSEL_SHIFT(pinint)));
- putreg32(regval, LPC43_SCU_PINTSEL0);
+ putreg32(pinsel, LPC43_SCU_PINTSEL0);
}
else
{
- regval = getreg32(LPC43_SCU_PINTSEL1);
- regval &= ~SCU_PINTSEL1_MASK(pinint);
- regval |= ((pin << SCU_PINTSEL1_INTPIN_SHIFT(pinint)) |
+ pinsel = getreg32(LPC43_SCU_PINTSEL1);
+ pinsel &= ~SCU_PINTSEL1_MASK(pinint);
+ pinsel |= ((pin << SCU_PINTSEL1_INTPIN_SHIFT(pinint)) |
(port << SCU_PINTSEL1_PORTSEL_SHIFT(pinint)));
- putreg32(regval, LPC43_SCU_PINTSEL1);
- }
-
- /* Set level or edge sensitive */
-
- regval = getreg32(LPC43_GPIOINT_ISEL);
- if (GPIO_IS_LEVEL(gpiocfg))
- {
- regval |= bitmask;
+ putreg32(pinsel, LPC43_SCU_PINTSEL1);
}
- else
- {
- regval &= ~bitmask;
- }
-
- putreg32(regval, LPC43_GPIOINT_ISEL);
/* Configure the active level or rising/falling edge
*
--
GitLab
From 88b51683bbcc9b6c3d5bcc246ffb9917cf03fd68 Mon Sep 17 00:00:00 2001
From: Lok Tep
Date: Sun, 5 Jun 2016 11:43:06 +0200
Subject: [PATCH 059/400] bus busy timeout, errata
---
arch/arm/src/stm32f7/stm32_i2c.c | 162 ++++++++++++++++-------------
configs/stm32f746-ws/nsh/defconfig | 2 +-
2 files changed, 90 insertions(+), 74 deletions(-)
diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c
index 4a769b08fa..b2409f253b 100644
--- a/arch/arm/src/stm32f7/stm32_i2c.c
+++ b/arch/arm/src/stm32f7/stm32_i2c.c
@@ -402,6 +402,7 @@ struct stm32_i2c_priv_s
uint8_t msgc; /* Message count */
struct i2c_msg_s *msgv; /* Message list */
uint8_t *ptr; /* Current message buffer */
+ uint32_t frequency; /* Current I2C frequency */
int dcnt; /* Current message bytes remaining to transfer */
uint16_t flags; /* Current message flags */
bool astart; /* START sent */
@@ -426,10 +427,6 @@ struct stm32_i2c_inst_s
{
struct i2c_ops_s *ops; /* Standard I2C operations */
struct stm32_i2c_priv_s *priv; /* Common driver private data structure */
-
- uint32_t frequency; /* Frequency used in this instantiation */
- int address; /* Address used in this instantiation */
- uint16_t flags; /* Flags used in this instantiation */
};
/************************************************************************************
@@ -516,6 +513,7 @@ struct stm32_i2c_priv_s stm32_i2c1_priv =
.msgc = 0,
.msgv = NULL,
.ptr = NULL,
+ .frequency = 0,
.dcnt = 0,
.flags = 0,
.status = 0
@@ -545,6 +543,7 @@ struct stm32_i2c_priv_s stm32_i2c2_priv =
.msgc = 0,
.msgv = NULL,
.ptr = NULL,
+ .frequency = 0,
.dcnt = 0,
.flags = 0,
.status = 0
@@ -574,6 +573,7 @@ struct stm32_i2c_priv_s stm32_i2c3_priv =
.msgc = 0,
.msgv = NULL,
.ptr = NULL,
+ .frequency = 0,
.dcnt = 0,
.flags = 0,
.status = 0
@@ -1242,55 +1242,59 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ
uint8_t scl_h_period;
uint8_t scl_l_period;
- /* I2C peripheral must be disabled to update clocking configuration */
-
- pe = (stm32_i2c_getreg32(priv, STM32F7_I2C_CR1_OFFSET) & I2C_CR1_PE);
- if (pe)
- {
- stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
- }
-
- /* TODO: speed/timing calcs, at the moment 45Mhz = STM32_PCLK1_FREQUENCY, analog filter is on,
- digital off from STM32F0-F3_AN4235_V1.0.1 */
-
- if (frequency == 100000)
- {
- presc = 0x06;
- scl_delay = 0x02;
- sda_delay = 0x00;
- scl_h_period = 0x1e;
- scl_l_period = 0x2b;
-
- }
- else if (frequency == 400000)
- {
- presc = 0x00;
- scl_delay = 0x0A;
- sda_delay = 0x00;
- scl_h_period = 0x1b;
- scl_l_period = 0x5b;
- }
- else
- {
- presc = 0x00;
- scl_delay = 0x08;
- sda_delay = 0x00;
- scl_h_period = 0x09;
- scl_l_period = 0x1c;
- }
-
- uint32_t timingr =
- (presc << I2C_TIMINGR_PRESC_SHIFT) |
- (scl_delay << I2C_TIMINGR_SCLDEL_SHIFT) |
- (sda_delay << I2C_TIMINGR_SDADEL_SHIFT) |
- (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) |
- (scl_l_period << I2C_TIMINGR_SCLL_SHIFT);
-
- stm32_i2c_putreg32(priv, STM32F7_I2C_TIMINGR_OFFSET, timingr);
-
- if (pe)
+ if (frequency != priv->frequency)
{
- stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
+ /* I2C peripheral must be disabled to update clocking configuration */
+
+ pe = (stm32_i2c_getreg32(priv, STM32F7_I2C_CR1_OFFSET) & I2C_CR1_PE);
+ if (pe)
+ {
+ stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
+ }
+
+ /* TODO: speed/timing calcs, at the moment 45Mhz = STM32_PCLK1_FREQUENCY, analog filter is on,
+ digital off from STM32F0-F3_AN4235_V1.0.1 */
+
+ if (frequency == 100000)
+ {
+ presc = 0x06;
+ scl_delay = 0x02;
+ sda_delay = 0x00;
+ scl_h_period = 0x1e;
+ scl_l_period = 0x2b;
+
+ }
+ else if (frequency == 400000)
+ {
+ presc = 0x00;
+ scl_delay = 0x0A;
+ sda_delay = 0x00;
+ scl_h_period = 0x1b;
+ scl_l_period = 0x5b;
+ }
+ else
+ {
+ presc = 0x00;
+ scl_delay = 0x08;
+ sda_delay = 0x00;
+ scl_h_period = 0x09;
+ scl_l_period = 0x1c;
+ }
+
+ uint32_t timingr =
+ (presc << I2C_TIMINGR_PRESC_SHIFT) |
+ (scl_delay << I2C_TIMINGR_SCLDEL_SHIFT) |
+ (sda_delay << I2C_TIMINGR_SDADEL_SHIFT) |
+ (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) |
+ (scl_l_period << I2C_TIMINGR_SCLL_SHIFT);
+
+ stm32_i2c_putreg32(priv, STM32F7_I2C_TIMINGR_OFFSET, timingr);
+
+ if (pe)
+ {
+ stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
+ }
+ priv->frequency = frequency;
}
}
@@ -2352,16 +2356,17 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
if (status & I2C_INT_BERR)
{
- /* Bus Error */
+ /* Bus Error, ignore it because of errata (revision A,Z) */
- i2cdbg("I2C: Bus Error\n");
- errval = EIO;
+ i2cdbg("I2C: Bus Error\n");
+
+ /* errval = EIO; */
}
else if (status & I2C_INT_ARLO)
{
/* Arbitration Lost (master mode) */
- i2cdbg("I2C: Arbitration Lost\n");
+ i2cdbg("I2C: Arbitration Lost\n");
errval = EAGAIN;
}
@@ -2369,21 +2374,21 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
{
/* Overrun/Underrun */
- i2cdbg("I2C: Overrun/Underrun\n");
+ i2cdbg("I2C: Overrun/Underrun\n");
errval = EIO;
}
else if (status & I2C_INT_PECERR)
{
/* PEC Error in reception (SMBus Only) */
- i2cdbg("I2C: PEC Error\n");
+ i2cdbg("I2C: PEC Error\n");
errval = EPROTO;
}
else if (status & I2C_INT_TIMEOUT)
{
/* Timeout or Tlow Error (SMBus Only) */
- i2cdbg("I2C: Timeout / Tlow Error\n");
+ i2cdbg("I2C: Timeout / Tlow Error\n");
errval = ETIME;
}
else if (status & I2C_INT_NACK)
@@ -2391,21 +2396,21 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
/* NACK Received, flag as "communication error on send" */
if (priv->astart == TRUE)
- {
+ {
i2cdbg("I2C: Address NACK\n");
errval = EADDRNOTAVAIL;
- }
- else
- {
- i2cdbg("I2C: Data NACK\n");
- errval = ECOMM;
- }
+ }
+ else
+ {
+ i2cdbg("I2C: Data NACK\n");
+ errval = ECOMM;
+ }
}
else
{
- /* Unrecognized error */
+ /* Unrecognized error */
- i2cdbg("I2C: Unrecognized Error");
+ i2cdbg("I2C: Unrecognized Error");
errval = EINTR;
}
}
@@ -2427,8 +2432,22 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
* fails above; Otherwise it is cleared by the hardware when the ISR
* wraps up the transfer with a STOP condition.
*/
- i2cdbg("I2C: Bus busy");
- errval = EBUSY;
+
+ uint32_t start = clock_systimer();
+ uint32_t timeout = USEC2TICK(USEC_PER_SEC/priv->frequency) + 1;
+
+ status = stm32_i2c_getstatus(priv);
+
+ while(status & I2C_ISR_BUSY)
+ {
+ if((clock_systimer() - start) > timeout)
+ {
+ i2cdbg("I2C: Bus busy");
+ errval = EBUSY;
+ break;
+ }
+ status = stm32_i2c_getstatus(priv);
+ }
}
/* Dump the trace result */
@@ -2515,9 +2534,6 @@ FAR struct i2c_master_s *stm32f7_i2cbus_initialize(int port)
inst->ops = &stm32_i2c_ops;
inst->priv = priv;
- inst->frequency = 0;
- inst->address = 0;
- inst->flags = 0;
/* Init private data for the first time, increment refs count,
* power-up hardware and configure GPIOs.
diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig
index 4e3899a234..ff3a5c5973 100644
--- a/configs/stm32f746-ws/nsh/defconfig
+++ b/configs/stm32f746-ws/nsh/defconfig
@@ -333,7 +333,7 @@ CONFIG_DISABLE_OS_API=y
#
# Clocks and Timers
#
-CONFIG_USEC_PER_TICK=10000
+CONFIG_USEC_PER_TICK=1000
# CONFIG_SYSTEM_TIME64 is not set
# CONFIG_CLOCK_MONOTONIC is not set
# CONFIG_JULIAN_TIME is not set
--
GitLab
From f2c65a4c47e41f86410eabac517ce81b3f2e1399 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Sun, 5 Jun 2016 12:13:11 -0600
Subject: [PATCH 060/400] Refresh configurations
---
configs/sam3u-ek/nxwm/defconfig | 27 +++++++++++++++---------
configs/sama5d3x-ek/nxwm/defconfig | 23 +++++++++++++++-----
configs/samv71-xult/nxwm/defconfig | 30 ++++++++++++++++++---------
configs/shenzhou/nxwm/defconfig | 24 +++++++++++++++------
configs/stm3220g-eval/nxwm/defconfig | 25 +++++++++++++++-------
configs/stm3240g-eval/knxwm/defconfig | 25 +++++++++++++++-------
configs/stm3240g-eval/nxwm/defconfig | 25 +++++++++++++++-------
7 files changed, 127 insertions(+), 52 deletions(-)
diff --git a/configs/sam3u-ek/nxwm/defconfig b/configs/sam3u-ek/nxwm/defconfig
index fb8be1e62e..35a17fe3f1 100644
--- a/configs/sam3u-ek/nxwm/defconfig
+++ b/configs/sam3u-ek/nxwm/defconfig
@@ -76,6 +76,7 @@ CONFIG_ARCH="arm"
# CONFIG_ARCH_CHIP_DM320 is not set
# CONFIG_ARCH_CHIP_EFM32 is not set
# CONFIG_ARCH_CHIP_IMX1 is not set
+# CONFIG_ARCH_CHIP_IMX6 is not set
# CONFIG_ARCH_CHIP_KINETIS is not set
# CONFIG_ARCH_CHIP_KL is not set
# CONFIG_ARCH_CHIP_LM is not set
@@ -94,6 +95,7 @@ CONFIG_ARCH_CHIP_SAM34=y
# CONFIG_ARCH_CHIP_SAMV7 is not set
# CONFIG_ARCH_CHIP_STM32 is not set
# CONFIG_ARCH_CHIP_STM32F7 is not set
+# CONFIG_ARCH_CHIP_STM32L4 is not set
# CONFIG_ARCH_CHIP_STR71X is not set
# CONFIG_ARCH_CHIP_TMS570 is not set
# CONFIG_ARCH_CHIP_MOXART is not set
@@ -115,12 +117,15 @@ CONFIG_ARCH_CORTEXM3=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARCH_CHIP="sam34"
+# CONFIG_ARM_TOOLCHAIN_IAR is not set
+CONFIG_ARM_TOOLCHAIN_GNU=y
# CONFIG_ARMV7M_USEBASEPRI is not set
CONFIG_ARCH_HAVE_CMNVECTOR=y
# CONFIG_ARMV7M_CMNVECTOR is not set
# CONFIG_ARMV7M_LAZYFPU is not set
# CONFIG_ARCH_HAVE_FPU is not set
# CONFIG_ARCH_HAVE_DPFPU is not set
+# CONFIG_ARCH_HAVE_TRUSTZONE is not set
CONFIG_ARM_HAVE_MPU_UNIFIED=y
# CONFIG_ARM_MPU is not set
@@ -131,6 +136,7 @@ CONFIG_ARM_HAVE_MPU_UNIFIED=y
# CONFIG_ARMV7M_HAVE_DCACHE is not set
# CONFIG_ARMV7M_HAVE_ITCM is not set
# CONFIG_ARMV7M_HAVE_DTCM is not set
+# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set
CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
@@ -508,10 +514,14 @@ CONFIG_ADS7843E_THRESHY=39
# CONFIG_DJOYSTICK is not set
# CONFIG_AJOYSTICK is not set
# CONFIG_IOEXPANDER is not set
+
+#
+# LCD Driver Support
+#
CONFIG_LCD=y
#
-# Common LCD Settings
+# Common Graphic LCD Settings
#
# CONFIG_LCD_CONSOLE is not set
# CONFIG_LCD_NOGETRUN is not set
@@ -540,11 +550,7 @@ CONFIG_LCD_LANDSCAPE=y
# CONFIG_LCD_RLANDSCAPE is not set
# CONFIG_LCD_ILI9341 is not set
# CONFIG_LCD_RA8875 is not set
-
-#
-# Alphanumeric/Segment LCD Devices
-#
-# CONFIG_LCD_LCD1602 is not set
+# CONFIG_SLCD is not set
#
# LED Support
@@ -586,10 +592,6 @@ CONFIG_UART0_SERIALDRIVER=y
# CONFIG_USART7_SERIALDRIVER is not set
# CONFIG_USART8_SERIALDRIVER is not set
# CONFIG_OTHER_UART_SERIALDRIVER is not set
-
-#
-# USART Configuration
-#
CONFIG_MCU_SERIAL=y
CONFIG_STANDARD_SERIAL=y
# CONFIG_SERIAL_IFLOWCONTROL is not set
@@ -675,6 +677,7 @@ CONFIG_NX_LCDDRIVER=y
CONFIG_NX_NPLANES=1
CONFIG_NX_BGCOLOR=0x0
CONFIG_NX_WRITEONLY=y
+# CONFIG_NX_UPDATE is not set
#
# Supported Pixel Depths
@@ -838,6 +841,8 @@ CONFIG_ARCH_LOWPUTC=y
CONFIG_LIB_SENDFILE_BUFSIZE=512
# CONFIG_ARCH_ROMGETC is not set
# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
+CONFIG_ARCH_HAVE_TLS=y
+# CONFIG_TLS is not set
# CONFIG_LIBC_NETDB is not set
#
@@ -956,6 +961,7 @@ CONFIG_CXX_NEWLONG=y
# Network Utilities
#
# CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_ESP8266 is not set
# CONFIG_NETUTILS_FTPC is not set
# CONFIG_NETUTILS_JSON is not set
# CONFIG_NETUTILS_SMTP is not set
@@ -1078,6 +1084,7 @@ CONFIG_NXWIDGETS_LISTENERSTACK=1596
# NXWidget Configuration
#
CONFIG_NXWIDGETS_BPP=16
+# CONFIG_NXWIDGETS_GREYSCALE is not set
CONFIG_NXWIDGETS_SIZEOFCHAR=1
#
diff --git a/configs/sama5d3x-ek/nxwm/defconfig b/configs/sama5d3x-ek/nxwm/defconfig
index 5e533abf0d..682488ad76 100644
--- a/configs/sama5d3x-ek/nxwm/defconfig
+++ b/configs/sama5d3x-ek/nxwm/defconfig
@@ -80,6 +80,7 @@ CONFIG_ARCH="arm"
# CONFIG_ARCH_CHIP_DM320 is not set
# CONFIG_ARCH_CHIP_EFM32 is not set
# CONFIG_ARCH_CHIP_IMX1 is not set
+# CONFIG_ARCH_CHIP_IMX6 is not set
# CONFIG_ARCH_CHIP_KINETIS is not set
# CONFIG_ARCH_CHIP_KL is not set
# CONFIG_ARCH_CHIP_LM is not set
@@ -98,6 +99,7 @@ CONFIG_ARCH_CHIP_SAMA5=y
# CONFIG_ARCH_CHIP_SAMV7 is not set
# CONFIG_ARCH_CHIP_STM32 is not set
# CONFIG_ARCH_CHIP_STM32F7 is not set
+# CONFIG_ARCH_CHIP_STM32L4 is not set
# CONFIG_ARCH_CHIP_STR71X is not set
# CONFIG_ARCH_CHIP_TMS570 is not set
# CONFIG_ARCH_CHIP_MOXART is not set
@@ -119,9 +121,12 @@ CONFIG_ARCH_CORTEXA5=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-a"
CONFIG_ARCH_CHIP="sama5"
+# CONFIG_ARM_TOOLCHAIN_IAR is not set
+# CONFIG_ARM_TOOLCHAIN_GNU is not set
CONFIG_ARCH_HAVE_FPU=y
# CONFIG_ARCH_HAVE_DPFPU is not set
CONFIG_ARCH_FPU=y
+# CONFIG_ARCH_HAVE_TRUSTZONE is not set
# CONFIG_ARM_HAVE_MPU_UNIFIED is not set
CONFIG_ARCH_HAVE_LOWVECTORS=y
CONFIG_ARCH_LOWVECTORS=y
@@ -131,6 +136,8 @@ CONFIG_ARCH_LOWVECTORS=y
# ARMv7-A Configuration Options
#
# CONFIG_ARMV7A_HAVE_GICv2 is not set
+# CONFIG_ARMV7A_HAVE_GTM is not set
+# CONFIG_ARMV7A_HAVE_PTM is not set
# CONFIG_ARMV7A_HAVE_L2CC is not set
# CONFIG_ARMV7A_HAVE_L2CC_PL310 is not set
# CONFIG_ARMV7A_TOOLCHAIN_BUILDROOT is not set
@@ -182,7 +189,6 @@ CONFIG_SAMA5_HAVE_PIOE=y
# CONFIG_SAMA5_HAVE_TC is not set
# CONFIG_SAMA5_HAVE_TC1 is not set
# CONFIG_SAMA5_HAVE_TC2 is not set
-# CONFIG_ARCH_HAVE_TRUSTZONE is not set
# CONFIG_SAMA5_HAVE_TWI3 is not set
# CONFIG_SAMA5_HAVE_VDEC is not set
# CONFIG_SAMA5_FLEXCOM is not set
@@ -603,7 +609,12 @@ CONFIG_INPUT=y
# CONFIG_DJOYSTICK is not set
# CONFIG_AJOYSTICK is not set
# CONFIG_IOEXPANDER is not set
+
+#
+# LCD Driver Support
+#
# CONFIG_LCD is not set
+# CONFIG_SLCD is not set
#
# LED Support
@@ -645,10 +656,6 @@ CONFIG_USART1_SERIALDRIVER=y
# CONFIG_USART7_SERIALDRIVER is not set
# CONFIG_USART8_SERIALDRIVER is not set
# CONFIG_OTHER_UART_SERIALDRIVER is not set
-
-#
-# USART Configuration
-#
CONFIG_MCU_SERIAL=y
CONFIG_STANDARD_SERIAL=y
# CONFIG_SERIAL_IFLOWCONTROL is not set
@@ -743,6 +750,7 @@ CONFIG_NX_NPLANES=1
CONFIG_NX_BGCOLOR=0x95fa
# CONFIG_NX_ANTIALIASING is not set
# CONFIG_NX_WRITEONLY is not set
+# CONFIG_NX_UPDATE is not set
#
# Supported Pixel Depths
@@ -907,6 +915,8 @@ CONFIG_ARCH_LOWPUTC=y
CONFIG_LIB_SENDFILE_BUFSIZE=512
# CONFIG_ARCH_ROMGETC is not set
# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
+CONFIG_ARCH_HAVE_TLS=y
+# CONFIG_TLS is not set
# CONFIG_LIBC_NETDB is not set
# CONFIG_NETDB_HOSTFILE is not set
@@ -945,6 +955,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
#
# Examples
#
+# CONFIG_EXAMPLES_ADC is not set
# CONFIG_EXAMPLES_CHAT is not set
# CONFIG_EXAMPLES_CONFIGDATA is not set
# CONFIG_EXAMPLES_CPUHOG is not set
@@ -1031,6 +1042,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
# Network Utilities
#
# CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_ESP8266 is not set
# CONFIG_NETUTILS_FTPC is not set
# CONFIG_NETUTILS_JSON is not set
# CONFIG_NETUTILS_SMTP is not set
@@ -1155,6 +1167,7 @@ CONFIG_NXWIDGETS_LISTENERSTACK=1596
# NXWidget Configuration
#
CONFIG_NXWIDGETS_BPP=16
+# CONFIG_NXWIDGETS_GREYSCALE is not set
CONFIG_NXWIDGETS_SIZEOFCHAR=1
#
diff --git a/configs/samv71-xult/nxwm/defconfig b/configs/samv71-xult/nxwm/defconfig
index f0734a4218..cae079b2d7 100644
--- a/configs/samv71-xult/nxwm/defconfig
+++ b/configs/samv71-xult/nxwm/defconfig
@@ -264,6 +264,13 @@ CONFIG_SAMV7_USART0=y
# CONFIG_SAMV7_USART2 is not set
# CONFIG_SAMV7_WDT is not set
# CONFIG_SAMV7_RSWDT is not set
+# CONFIG_SAMV7_JTAG_DISABLE is not set
+CONFIG_SAMV7_JTAG_FULL_ENABLE=y
+# CONFIG_SAMV7_JTAG_FULL_SW_ENABLE is not set
+# CONFIG_SAMV7_JTAG_SW_ENABLE is not set
+# CONFIG_SAMV7_ERASE_DISABLE is not set
+CONFIG_SAMV7_ERASE_ENABLE=y
+# CONFIG_SAMV7_SYSTEMRESET is not set
CONFIG_SAMV7_GPIO_IRQ=y
CONFIG_SAMV7_GPIOA_IRQ=y
CONFIG_SAMV7_GPIOB_IRQ=y
@@ -549,10 +556,14 @@ CONFIG_MXT_THRESHY=8
# CONFIG_DJOYSTICK is not set
# CONFIG_AJOYSTICK is not set
# CONFIG_IOEXPANDER is not set
+
+#
+# LCD Driver Support
+#
CONFIG_LCD=y
#
-# Common LCD Settings
+# Common Graphic LCD Settings
#
# CONFIG_LCD_CONSOLE is not set
CONFIG_LCD_NOGETRUN=y
@@ -581,11 +592,7 @@ CONFIG_LCD_LANDSCAPE=y
# CONFIG_LCD_RLANDSCAPE is not set
# CONFIG_LCD_ILI9341 is not set
# CONFIG_LCD_RA8875 is not set
-
-#
-# Alphanumeric/Segment LCD Devices
-#
-# CONFIG_LCD_LCD1602 is not set
+# CONFIG_SLCD is not set
#
# LED Support
@@ -639,10 +646,12 @@ CONFIG_AT25_SPIFREQUENCY=20000000
# CONFIG_MTD_AT45DB is not set
# CONFIG_MTD_M25P is not set
# CONFIG_MTD_S25FL1 is not set
+# CONFIG_MTD_N25QXXX is not set
# CONFIG_MTD_SMART is not set
# CONFIG_MTD_RAMTRON is not set
# CONFIG_MTD_SST25 is not set
# CONFIG_MTD_SST25XX is not set
+# CONFIG_MTD_SST26 is not set
# CONFIG_MTD_SST39FV is not set
# CONFIG_MTD_W25 is not set
# CONFIG_EEPROM is not set
@@ -676,10 +685,6 @@ CONFIG_USART0_SERIALDRIVER=y
# CONFIG_USART7_SERIALDRIVER is not set
# CONFIG_USART8_SERIALDRIVER is not set
# CONFIG_OTHER_UART_SERIALDRIVER is not set
-
-#
-# USART Configuration
-#
CONFIG_MCU_SERIAL=y
CONFIG_STANDARD_SERIAL=y
# CONFIG_SERIAL_IFLOWCONTROL is not set
@@ -773,6 +778,7 @@ CONFIG_NX_LCDDRIVER=y
CONFIG_NX_NPLANES=1
CONFIG_NX_BGCOLOR=0x95fa
CONFIG_NX_WRITEONLY=y
+# CONFIG_NX_UPDATE is not set
#
# Supported Pixel Depths
@@ -1036,6 +1042,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
#
# File System Utilities
#
+# CONFIG_FSUTILS_FLASH_ERASEALL is not set
# CONFIG_FSUTILS_INIFILE is not set
# CONFIG_FSUTILS_PASSWD is not set
@@ -1067,6 +1074,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
# Network Utilities
#
# CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_ESP8266 is not set
# CONFIG_NETUTILS_FTPC is not set
# CONFIG_NETUTILS_JSON is not set
# CONFIG_NETUTILS_SMTP is not set
@@ -1191,6 +1199,7 @@ CONFIG_NXWIDGETS_LISTENERSTACK=2048
# NXWidget Configuration
#
CONFIG_NXWIDGETS_BPP=16
+# CONFIG_NXWIDGETS_GREYSCALE is not set
CONFIG_NXWIDGETS_SIZEOFCHAR=1
#
@@ -1362,6 +1371,7 @@ CONFIG_NXWM_HEXCALCULATOR_FONTID=5
# CONFIG_SYSTEM_FREE is not set
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
+# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_INSTALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
CONFIG_SYSTEM_I2CTOOL=y
diff --git a/configs/shenzhou/nxwm/defconfig b/configs/shenzhou/nxwm/defconfig
index a59049abed..78e803db84 100644
--- a/configs/shenzhou/nxwm/defconfig
+++ b/configs/shenzhou/nxwm/defconfig
@@ -417,6 +417,10 @@ CONFIG_STM32_JTAG_FULL_ENABLE=y
# CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG is not set
# CONFIG_STM32_FORCEPOWER is not set
# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set
+
+#
+# Timer Configuration
+#
# CONFIG_STM32_TIM1_CAP is not set
# CONFIG_STM32_TIM3_CAP is not set
# CONFIG_STM32_TIM4_CAP is not set
@@ -428,9 +432,17 @@ CONFIG_STM32_SERIALDRIVER=y
#
# U[S]ART Configuration
#
+
+#
+# U[S]ART Device Configuration
+#
CONFIG_STM32_USART2_SERIALDRIVER=y
# CONFIG_STM32_USART2_1WIREDRIVER is not set
# CONFIG_USART2_RS485 is not set
+
+#
+# Serial Driver Configuration
+#
# CONFIG_SERIAL_DISABLE_REORDERING is not set
# CONFIG_STM32_FLOWCONTROL_BROKEN is not set
# CONFIG_STM32_USART_BREAKS is not set
@@ -752,10 +764,14 @@ CONFIG_ADS7843E_THRESHY=51
# CONFIG_DJOYSTICK is not set
# CONFIG_AJOYSTICK is not set
# CONFIG_IOEXPANDER is not set
+
+#
+# LCD Driver Support
+#
CONFIG_LCD=y
#
-# Common LCD Settings
+# Common Graphic LCD Settings
#
# CONFIG_LCD_CONSOLE is not set
CONFIG_LCD_NOGETRUN=y
@@ -787,11 +803,7 @@ CONFIG_LCD_LANDSCAPE=y
# CONFIG_LCD_RLANDSCAPE is not set
# CONFIG_LCD_ILI9341 is not set
# CONFIG_LCD_RA8875 is not set
-
-#
-# Alphanumeric/Segment LCD Devices
-#
-# CONFIG_LCD_LCD1602 is not set
+# CONFIG_SLCD is not set
#
# LED Support
diff --git a/configs/stm3220g-eval/nxwm/defconfig b/configs/stm3220g-eval/nxwm/defconfig
index fadce2d0ab..3c430c4fd6 100644
--- a/configs/stm3220g-eval/nxwm/defconfig
+++ b/configs/stm3220g-eval/nxwm/defconfig
@@ -434,6 +434,10 @@ CONFIG_STM32_JTAG_FULL_ENABLE=y
# CONFIG_STM32_FORCEPOWER is not set
# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set
# CONFIG_STM32_FSMC_SRAM is not set
+
+#
+# Timer Configuration
+#
# CONFIG_STM32_TIM1_CAP is not set
# CONFIG_STM32_TIM3_CAP is not set
# CONFIG_STM32_TIM4_CAP is not set
@@ -451,9 +455,17 @@ CONFIG_STM32_SERIALDRIVER=y
#
# U[S]ART Configuration
#
+
+#
+# U[S]ART Device Configuration
+#
CONFIG_STM32_USART3_SERIALDRIVER=y
# CONFIG_STM32_USART3_1WIREDRIVER is not set
# CONFIG_USART3_RS485 is not set
+
+#
+# Serial Driver Configuration
+#
# CONFIG_SERIAL_DISABLE_REORDERING is not set
# CONFIG_STM32_FLOWCONTROL_BROKEN is not set
# CONFIG_STM32_USART_BREAKS is not set
@@ -766,10 +778,14 @@ CONFIG_STMPE811_TEMP_DISABLE=y
# CONFIG_DJOYSTICK is not set
# CONFIG_AJOYSTICK is not set
# CONFIG_IOEXPANDER is not set
+
+#
+# LCD Driver Support
+#
CONFIG_LCD=y
#
-# Common LCD Settings
+# Common Graphic LCD Settings
#
# CONFIG_LCD_CONSOLE is not set
CONFIG_LCD_NOGETRUN=y
@@ -797,12 +813,7 @@ CONFIG_LCD_LANDSCAPE=y
# CONFIG_LCD_RLANDSCAPE is not set
# CONFIG_LCD_ILI9341 is not set
# CONFIG_LCD_RA8875 is not set
-
-#
-# Alphanumeric/Segment LCD Devices
-#
-# CONFIG_LCD_LCD1602 is not set
-# CONFIG_LCD_BACKPACK is not set
+# CONFIG_SLCD is not set
#
# LED Support
diff --git a/configs/stm3240g-eval/knxwm/defconfig b/configs/stm3240g-eval/knxwm/defconfig
index fe098b72e1..851b298219 100644
--- a/configs/stm3240g-eval/knxwm/defconfig
+++ b/configs/stm3240g-eval/knxwm/defconfig
@@ -444,6 +444,10 @@ CONFIG_STM32_JTAG_FULL_ENABLE=y
# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set
# CONFIG_STM32_CCMEXCLUDE is not set
# CONFIG_STM32_FSMC_SRAM is not set
+
+#
+# Timer Configuration
+#
# CONFIG_STM32_TIM1_CAP is not set
# CONFIG_STM32_TIM2_CAP is not set
# CONFIG_STM32_TIM3_CAP is not set
@@ -462,9 +466,17 @@ CONFIG_STM32_SERIALDRIVER=y
#
# U[S]ART Configuration
#
+
+#
+# U[S]ART Device Configuration
+#
CONFIG_STM32_USART3_SERIALDRIVER=y
# CONFIG_STM32_USART3_1WIREDRIVER is not set
# CONFIG_USART3_RS485 is not set
+
+#
+# Serial Driver Configuration
+#
# CONFIG_SERIAL_DISABLE_REORDERING is not set
# CONFIG_STM32_FLOWCONTROL_BROKEN is not set
# CONFIG_STM32_USART_BREAKS is not set
@@ -761,10 +773,14 @@ CONFIG_STMPE811_TEMP_DISABLE=y
# CONFIG_DJOYSTICK is not set
# CONFIG_AJOYSTICK is not set
# CONFIG_IOEXPANDER is not set
+
+#
+# LCD Driver Support
+#
CONFIG_LCD=y
#
-# Common LCD Settings
+# Common Graphic LCD Settings
#
# CONFIG_LCD_CONSOLE is not set
CONFIG_LCD_NOGETRUN=y
@@ -792,12 +808,7 @@ CONFIG_LCD_LANDSCAPE=y
# CONFIG_LCD_RLANDSCAPE is not set
# CONFIG_LCD_ILI9341 is not set
# CONFIG_LCD_RA8875 is not set
-
-#
-# Alphanumeric/Segment LCD Devices
-#
-# CONFIG_LCD_LCD1602 is not set
-# CONFIG_LCD_BACKPACK is not set
+# CONFIG_SLCD is not set
#
# LED Support
diff --git a/configs/stm3240g-eval/nxwm/defconfig b/configs/stm3240g-eval/nxwm/defconfig
index e3e15ad43e..d2bfa0fa65 100644
--- a/configs/stm3240g-eval/nxwm/defconfig
+++ b/configs/stm3240g-eval/nxwm/defconfig
@@ -437,6 +437,10 @@ CONFIG_STM32_JTAG_FULL_ENABLE=y
# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set
# CONFIG_STM32_CCMEXCLUDE is not set
# CONFIG_STM32_FSMC_SRAM is not set
+
+#
+# Timer Configuration
+#
# CONFIG_STM32_TIM1_CAP is not set
# CONFIG_STM32_TIM2_CAP is not set
# CONFIG_STM32_TIM3_CAP is not set
@@ -455,9 +459,17 @@ CONFIG_STM32_SERIALDRIVER=y
#
# U[S]ART Configuration
#
+
+#
+# U[S]ART Device Configuration
+#
CONFIG_STM32_USART3_SERIALDRIVER=y
# CONFIG_STM32_USART3_1WIREDRIVER is not set
# CONFIG_USART3_RS485 is not set
+
+#
+# Serial Driver Configuration
+#
# CONFIG_SERIAL_DISABLE_REORDERING is not set
# CONFIG_STM32_FLOWCONTROL_BROKEN is not set
# CONFIG_STM32_USART_BREAKS is not set
@@ -769,10 +781,14 @@ CONFIG_STMPE811_TEMP_DISABLE=y
# CONFIG_DJOYSTICK is not set
# CONFIG_AJOYSTICK is not set
# CONFIG_IOEXPANDER is not set
+
+#
+# LCD Driver Support
+#
CONFIG_LCD=y
#
-# Common LCD Settings
+# Common Graphic LCD Settings
#
# CONFIG_LCD_CONSOLE is not set
CONFIG_LCD_NOGETRUN=y
@@ -800,12 +816,7 @@ CONFIG_LCD_LANDSCAPE=y
# CONFIG_LCD_RLANDSCAPE is not set
# CONFIG_LCD_ILI9341 is not set
# CONFIG_LCD_RA8875 is not set
-
-#
-# Alphanumeric/Segment LCD Devices
-#
-# CONFIG_LCD_LCD1602 is not set
-# CONFIG_LCD_BACKPACK is not set
+# CONFIG_SLCD is not set
#
# LED Support
--
GitLab
From 37dd4e52a1d62a27c66aa54a73e5e03161808c6a Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Sun, 5 Jun 2016 12:13:56 -0600
Subject: [PATCH 061/400] boardctl.h needs to be include-able from C++ files
---
include/sys/boardctl.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/include/sys/boardctl.h b/include/sys/boardctl.h
index 5177dd8074..b1ebe45e8f 100644
--- a/include/sys/boardctl.h
+++ b/include/sys/boardctl.h
@@ -265,6 +265,19 @@ struct boardioc_usbdev_ctrl_s
};
#endif /* CONFIG_BOARDCTL_USBDEVCTRL */
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
@@ -299,5 +312,10 @@ struct boardioc_usbdev_ctrl_s
int boardctl(unsigned int cmd, uintptr_t arg);
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
#endif /* CONFIG_LIB_BOARDCTL */
#endif /* __INCLUDE_SYS_BOARDCTL_H */
--
GitLab
From f36e342f3889bc0761bfb09bf90ea8487c80d761 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Sun, 5 Jun 2016 12:14:18 -0600
Subject: [PATCH 062/400] tools/tesbuild.sh will now build NxWM configurations
---
tools/testbuild.sh | 66 ++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 64 insertions(+), 2 deletions(-)
diff --git a/tools/testbuild.sh b/tools/testbuild.sh
index 9546c92144..c9f30a178b 100755
--- a/tools/testbuild.sh
+++ b/tools/testbuild.sh
@@ -34,22 +34,27 @@
WD=$PWD
nuttx=$WD/../nuttx
+UNLINK=./unlink.sh
progname=$0
host=linux
wenv=cygwin
sizet=uint
+APPSDIR=../apps
+NXWDIR=../NxWidgets
unset testfile
function showusage {
echo ""
- echo "USAGE: $progname [-w|l] [-c|n] [-s] "
+ echo "USAGE: $progname [-w|l] [-c|n] [-s] [-a ] [-n ] "
echo " $progname -h"
echo ""
echo "Where:"
echo " -w|l selects Windows (w) or Linux (l). Default: Linux"
echo " -c|n selects Windows native (n) or Cygwin (c). Default Cygwin"
echo " -s Use C++ unsigned long size_t in new operator. Default unsigned int"
+ echo " -a provides the relative path to the apps/ directory. Default ../apps"
+ echo " -n provides the relative path to the NxWidgets/ directory. Default ../NxWidgets"
echo " -h will show this help test and terminate"
echo " selects the list of configurations to test. No default"
echo ""
@@ -78,6 +83,14 @@ while [ ! -z "$1" ]; do
-s )
sizet=long
;;
+ -a )
+ shift
+ APPSDIR="$1"
+ ;;
+ -n )
+ shift
+ NXWDIR="$1"
+ ;;
-h )
showusage
;;
@@ -122,6 +135,15 @@ function distclean {
fi
}
+# Check if build is NxWM and clean
+
+function nxcheck {
+ unset nxconfig
+ if [ -d $NXWDIR ]; then
+ nxconfig=`grep CONFIG_NXWM=y $nuttx/.config`
+ fi
+}
+
# Configure for the next build
function configure {
@@ -196,6 +218,33 @@ function configure {
make olddefconfig 1>/dev/null 2>&1
}
+# Build the NxWidgets libraries
+
+function nxbuild {
+ if [ -e $APPSDIR/internal ]; then
+ $UNLINK $APPSDIR/internal
+ fi
+
+ if [ ! -z "$nxconfig" ]; then
+ echo " Building NxWidgets..."
+ echo "------------------------------------------------------------------------------------"
+
+ cd $nuttx/$NXTOOLS || { echo "Failed to CD to $NXTOOLS"; exit 1; }
+ ./install.sh $nuttx/$APPSDIR nxwm 1>/dev/null
+
+ cd $nuttx || { echo "Failed to CD to $nuttx"; exit 1; }
+ make -i context 1>/dev/null
+
+ cd $nuttx/$NXWIDGETSDIR || { echo "Failed to CD to $NXWIDGETSDIR"; exit 1; }
+ make -i TOPDIR=$nuttx clean 1>/dev/null
+ make -i TOPDIR=$nuttx 1>/dev/null
+
+ cd $nuttx/$NXWMDIR || { echo "Failed to CD to $NXWMDIR"; exit 1; }
+ make -i TOPDIR=$nuttx clean 1>/dev/null
+ make -i TOPDIR=$nuttx 1>/dev/null
+ fi
+}
+
# Perform the next build
function build {
@@ -209,14 +258,27 @@ function build {
function dotest {
echo "------------------------------------------------------------------------------------"
+ nxcheck
distclean
configure
+ nxbuild
build
}
# Perform the build test for each entry in the test list file
-export APPSDIR=../apps
+if [ ! -d $APPSDIR ]; then
+ export "ERROR: No directory found at $APPSDIR"
+ exit 1
+fi
+
+export APPSDIR
+
+if [ -d $NXWDIR ]; then
+ NXWIDGETSDIR=$NXWDIR/libnxwidgets
+ NXWMDIR=$NXWDIR/nxwm
+ NXTOOLS=$NXWDIR/tools
+fi
# Shouldn't have to do this
--
GitLab
From ba0040fe1f948dae8f33f7819bce27f9ceff3440 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Sun, 5 Jun 2016 13:18:43 -0600
Subject: [PATCH 063/400] NxWM configurations need boardctl() with touchscreen
support
---
configs/sam3u-ek/nxwm/defconfig | 2 +-
configs/sama5d3x-ek/nxwm/defconfig | 2 +-
configs/shenzhou/nxwm/defconfig | 2 +-
configs/stm3220g-eval/nxwm/defconfig | 11 ++++++++++-
configs/stm3240g-eval/knxwm/defconfig | 11 ++++++++++-
configs/stm3240g-eval/nxwm/defconfig | 11 ++++++++++-
6 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/configs/sam3u-ek/nxwm/defconfig b/configs/sam3u-ek/nxwm/defconfig
index 35a17fe3f1..407a4e34d5 100644
--- a/configs/sam3u-ek/nxwm/defconfig
+++ b/configs/sam3u-ek/nxwm/defconfig
@@ -341,7 +341,7 @@ CONFIG_NSH_MMCSDMINOR=0
CONFIG_LIB_BOARDCTL=y
# CONFIG_BOARDCTL_RESET is not set
# CONFIG_BOARDCTL_UNIQUEID is not set
-# CONFIG_BOARDCTL_TSCTEST is not set
+CONFIG_BOARDCTL_TSCTEST=y
# CONFIG_BOARDCTL_ADCTEST is not set
# CONFIG_BOARDCTL_PWMTEST is not set
# CONFIG_BOARDCTL_GRAPHICS is not set
diff --git a/configs/sama5d3x-ek/nxwm/defconfig b/configs/sama5d3x-ek/nxwm/defconfig
index 682488ad76..bc5e3694ac 100644
--- a/configs/sama5d3x-ek/nxwm/defconfig
+++ b/configs/sama5d3x-ek/nxwm/defconfig
@@ -443,7 +443,7 @@ CONFIG_SAMA5D3xEK_TSD_DEVMINOR=0
# CONFIG_SAMA5D3xEK_SLOWCLOCK is not set
CONFIG_LIB_BOARDCTL=y
# CONFIG_BOARDCTL_UNIQUEID is not set
-# CONFIG_BOARDCTL_TSCTEST is not set
+CONFIG_BOARDCTL_TSCTEST=y
# CONFIG_BOARDCTL_ADCTEST is not set
# CONFIG_BOARDCTL_PWMTEST is not set
# CONFIG_BOARDCTL_GRAPHICS is not set
diff --git a/configs/shenzhou/nxwm/defconfig b/configs/shenzhou/nxwm/defconfig
index 78e803db84..22489a72ce 100644
--- a/configs/shenzhou/nxwm/defconfig
+++ b/configs/shenzhou/nxwm/defconfig
@@ -591,7 +591,7 @@ CONFIG_NSH_MMCSDMINOR=0
CONFIG_LIB_BOARDCTL=y
# CONFIG_BOARDCTL_RESET is not set
# CONFIG_BOARDCTL_UNIQUEID is not set
-# CONFIG_BOARDCTL_TSCTEST is not set
+CONFIG_BOARDCTL_TSCTEST=y
# CONFIG_BOARDCTL_ADCTEST is not set
# CONFIG_BOARDCTL_PWMTEST is not set
# CONFIG_BOARDCTL_GRAPHICS is not set
diff --git a/configs/stm3220g-eval/nxwm/defconfig b/configs/stm3220g-eval/nxwm/defconfig
index 3c430c4fd6..5ee92bfc04 100644
--- a/configs/stm3220g-eval/nxwm/defconfig
+++ b/configs/stm3220g-eval/nxwm/defconfig
@@ -605,7 +605,14 @@ CONFIG_NSH_MMCSDSLOTNO=0
# CONFIG_STM32_ILI9325_DISABLE is not set
CONFIG_STM3220G_LCD=y
CONFIG_LCD_RDSHIFT=5
-# CONFIG_LIB_BOARDCTL is not set
+CONFIG_LIB_BOARDCTL=y
+# CONFIG_BOARDCTL_RESET is not set
+# CONFIG_BOARDCTL_UNIQUEID is not set
+CONFIG_BOARDCTL_TSCTEST=y
+# CONFIG_BOARDCTL_ADCTEST is not set
+# CONFIG_BOARDCTL_PWMTEST is not set
+# CONFIG_BOARDCTL_GRAPHICS is not set
+# CONFIG_BOARDCTL_IOCTL is not set
#
# RTOS Features
@@ -1364,6 +1371,7 @@ CONFIG_HAVE_CXXINITIALIZE=y
# CONFIG_EXAMPLES_UDPBLASTER is not set
# CONFIG_EXAMPLES_DISCOVER is not set
# CONFIG_EXAMPLES_WEBSERVER is not set
+# CONFIG_EXAMPLES_USBSERIAL is not set
# CONFIG_EXAMPLES_USBTERM is not set
# CONFIG_EXAMPLES_WATCHDOG is not set
# CONFIG_EXAMPLES_WGET is not set
@@ -1557,6 +1565,7 @@ CONFIG_NXWIDGETS=y
# NX Server/Device Configuration
#
CONFIG_NXWIDGETS_FLICKERFREE=y
+# CONFIG_NXWIDGETS_EXTERNINIT is not set
CONFIG_NXWIDGETS_DEVNO=0
CONFIG_NXWIDGET_SERVERINIT=y
CONFIG_NXWIDGETS_SERVERPRIO=110
diff --git a/configs/stm3240g-eval/knxwm/defconfig b/configs/stm3240g-eval/knxwm/defconfig
index 851b298219..9d2baf17c6 100644
--- a/configs/stm3240g-eval/knxwm/defconfig
+++ b/configs/stm3240g-eval/knxwm/defconfig
@@ -598,7 +598,14 @@ CONFIG_STM3240G_LCD_RDSHIFT=5
# CONFIG_STM3240G_ILI9325_DISABLE is not set
CONFIG_STM3240G_BOARDINIT_PRIO=196
CONFIG_STM3240G_BOARDINIT_STACK=2048
-# CONFIG_LIB_BOARDCTL is not set
+CONFIG_LIB_BOARDCTL=y
+# CONFIG_BOARDCTL_RESET is not set
+# CONFIG_BOARDCTL_UNIQUEID is not set
+CONFIG_BOARDCTL_TSCTEST=y
+# CONFIG_BOARDCTL_ADCTEST is not set
+# CONFIG_BOARDCTL_PWMTEST is not set
+# CONFIG_BOARDCTL_GRAPHICS is not set
+# CONFIG_BOARDCTL_IOCTL is not set
#
# RTOS Features
@@ -1187,6 +1194,7 @@ CONFIG_CXX_NEWLONG=y
# CONFIG_EXAMPLES_TIFF is not set
# CONFIG_EXAMPLES_TOUCHSCREEN is not set
# CONFIG_EXAMPLES_WEBSERVER is not set
+# CONFIG_EXAMPLES_USBSERIAL is not set
# CONFIG_EXAMPLES_USBTERM is not set
# CONFIG_EXAMPLES_WATCHDOG is not set
@@ -1243,6 +1251,7 @@ CONFIG_NXWIDGETS=y
# NX Server/Device Configuration
#
CONFIG_NXWIDGETS_FLICKERFREE=y
+# CONFIG_NXWIDGETS_EXTERNINIT is not set
CONFIG_NXWIDGETS_DEVNO=0
CONFIG_NXWIDGETS_CLIENTPRIO=100
CONFIG_NXWIDGETS_LISTENERPRIO=100
diff --git a/configs/stm3240g-eval/nxwm/defconfig b/configs/stm3240g-eval/nxwm/defconfig
index d2bfa0fa65..677e3d58ff 100644
--- a/configs/stm3240g-eval/nxwm/defconfig
+++ b/configs/stm3240g-eval/nxwm/defconfig
@@ -608,7 +608,14 @@ CONFIG_STM3240G_LCD=y
CONFIG_STM3240G_LCD_RDSHIFT=5
# CONFIG_STM3240G_ILI9320_DISABLE is not set
# CONFIG_STM3240G_ILI9325_DISABLE is not set
-# CONFIG_LIB_BOARDCTL is not set
+CONFIG_LIB_BOARDCTL=y
+# CONFIG_BOARDCTL_RESET is not set
+# CONFIG_BOARDCTL_UNIQUEID is not set
+CONFIG_BOARDCTL_TSCTEST=y
+# CONFIG_BOARDCTL_ADCTEST is not set
+# CONFIG_BOARDCTL_PWMTEST is not set
+# CONFIG_BOARDCTL_GRAPHICS is not set
+# CONFIG_BOARDCTL_IOCTL is not set
#
# RTOS Features
@@ -1367,6 +1374,7 @@ CONFIG_HAVE_CXXINITIALIZE=y
# CONFIG_EXAMPLES_UDPBLASTER is not set
# CONFIG_EXAMPLES_DISCOVER is not set
# CONFIG_EXAMPLES_WEBSERVER is not set
+# CONFIG_EXAMPLES_USBSERIAL is not set
# CONFIG_EXAMPLES_USBTERM is not set
# CONFIG_EXAMPLES_WATCHDOG is not set
# CONFIG_EXAMPLES_WGET is not set
@@ -1562,6 +1570,7 @@ CONFIG_NXWIDGETS=y
# NX Server/Device Configuration
#
CONFIG_NXWIDGETS_FLICKERFREE=y
+# CONFIG_NXWIDGETS_EXTERNINIT is not set
CONFIG_NXWIDGETS_DEVNO=0
CONFIG_NXWIDGET_SERVERINIT=y
CONFIG_NXWIDGETS_SERVERPRIO=110
--
GitLab
From 7fa31493c958e5e5028679643d285aefdea630bd Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Sun, 5 Jun 2016 13:19:41 -0600
Subject: [PATCH 064/400] Update tools/tesbuild.sh
---
tools/testbuild.sh | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/tools/testbuild.sh b/tools/testbuild.sh
index c9f30a178b..0a6ecb0bdf 100755
--- a/tools/testbuild.sh
+++ b/tools/testbuild.sh
@@ -34,7 +34,8 @@
WD=$PWD
nuttx=$WD/../nuttx
-UNLINK=./unlink.sh
+TOOLSDIR=$nuttx/tools
+UNLINK=$TOOLSDIR/unlink.sh
progname=$0
host=linux
@@ -53,7 +54,7 @@ function showusage {
echo " -w|l selects Windows (w) or Linux (l). Default: Linux"
echo " -c|n selects Windows native (n) or Cygwin (c). Default Cygwin"
echo " -s Use C++ unsigned long size_t in new operator. Default unsigned int"
- echo " -a provides the relative path to the apps/ directory. Default ../apps"
+ echo " -a provides the relative path to the apps/ directory. Default ../apps"
echo " -n provides the relative path to the NxWidgets/ directory. Default ../NxWidgets"
echo " -h will show this help test and terminate"
echo " selects the list of configurations to test. No default"
@@ -221,8 +222,8 @@ function configure {
# Build the NxWidgets libraries
function nxbuild {
- if [ -e $APPSDIR/internal ]; then
- $UNLINK $APPSDIR/internal
+ if [ -e $APPSDIR/external ]; then
+ $UNLINK $APPSDIR/external
fi
if [ ! -z "$nxconfig" ]; then
@@ -232,6 +233,8 @@ function nxbuild {
cd $nuttx/$NXTOOLS || { echo "Failed to CD to $NXTOOLS"; exit 1; }
./install.sh $nuttx/$APPSDIR nxwm 1>/dev/null
+ make -C $nuttx/$APPSDIR/external TOPDIR=$nuttx APPDIR=$nuttx/$APPSDIR TOPDIR=$nuttx clean 1>/dev/null
+
cd $nuttx || { echo "Failed to CD to $nuttx"; exit 1; }
make -i context 1>/dev/null
@@ -249,7 +252,7 @@ function nxbuild {
function build {
cd $nuttx || { echo "ERROR: failed to CD to $nuttx"; exit 1; }
- echo " Building..."
+ echo " Building NuttX..."
echo "------------------------------------------------------------------------------------"
make -i 1>/dev/null
}
--
GitLab
From af43ce4f467a56774cadc49bac169b248a50912b Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Sun, 5 Jun 2016 15:01:16 -0600
Subject: [PATCH 065/400] Update ChangeLog
---
ChangeLog | 23 ++++++++++++++++++++---
arch/arm/src/lpc43xx/lpc43_gpioint.c | 4 ++--
2 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/ChangeLog b/ChangeLog
index 0df50e18fc..36041eb279 100755
--- a/ChangeLog
+++ b/ChangeLog
@@ -11884,6 +11884,23 @@
in the OS and is simply a wrapper around the MDIOC_BULKERASE
IOCTL command. It used to be called (only) from
apps/system/flash_eraseall, but that has been removed because it
- violated the OS/applicatin interface -- by calling flash_eraseall().
- The old code can be found in the Obsoleted' repository (2016-06-03).
-
+ violated the OS/application interface -- by calling flash_eraseall().
+ The old code can be found in the Obsoleted' repository (and a revised
+ version can be found at apps/fsutils/flash_eraseall) (2016-06-03).
+ * arch/arm/src/lpc43xx: Fix errors in GPIO interrupt logic. From v01d
+ (phreakuencies) (2016-06-04)
+ * arch/arm/src/kl and lpc11xx: rename xyz_lowputc to up_putc. Remove
+ all references to up_lowputc, everywhere (2016-06-04).
+ * configs/stm32f103-minimum: Add minnsh configuration. From Alan
+ Carvalho de Assis (2016-06-04).
+ * arch/arm/src/stm32: Add the up_getc() function to STM32 in order to
+ support the minnsh configuration. From Alan Carvalho de Assis
+ (2016-06-04).
+ * arch/arm/src/stm32: STM32 Timer Driver: Change calculation of per-
+ timer pre-scaler value. Add support for all timers (2016-6-03)
+ * drivers/lcd: Correct conditional compilation in ST7565 driver. From
+ Pierre-noel Bouteville (2016-6-03)
+ * arch/arm/src/stm32: Correct conditional compilation in STM32 timer
+ capture logic. From Pierre-noel Bouteville (2016-6-03)
+ * arch/arm/src/efm32: Fix EFM32 FLASH conditional compilation. From
+ Pierre-noel Bouteville (2016-6-03)
diff --git a/arch/arm/src/lpc43xx/lpc43_gpioint.c b/arch/arm/src/lpc43xx/lpc43_gpioint.c
index bfe660070e..e8726420c1 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpioint.c
+++ b/arch/arm/src/lpc43xx/lpc43_gpioint.c
@@ -200,7 +200,7 @@ int lpc43_gpioint_pinconfig(uint16_t gpiocfg)
if (pinint < 4)
{
- pinsel = getreg32(LPC43_SCU_PINTSEL0);
+ pinsel = getreg32(LPC43_SCU_PINTSEL0);
pinsel &= ~SCU_PINTSEL0_MASK(pinint);
pinsel |= ((pin << SCU_PINTSEL0_INTPIN_SHIFT(pinint)) |
(port << SCU_PINTSEL0_PORTSEL_SHIFT(pinint)));
@@ -208,7 +208,7 @@ int lpc43_gpioint_pinconfig(uint16_t gpiocfg)
}
else
{
- pinsel = getreg32(LPC43_SCU_PINTSEL1);
+ pinsel = getreg32(LPC43_SCU_PINTSEL1);
pinsel &= ~SCU_PINTSEL1_MASK(pinint);
pinsel |= ((pin << SCU_PINTSEL1_INTPIN_SHIFT(pinint)) |
(port << SCU_PINTSEL1_PORTSEL_SHIFT(pinint)));
--
GitLab
From 0bd444ae47a143d4a4d8148b2b55749d60e64037 Mon Sep 17 00:00:00 2001
From: Pierre-noel Bouteville
Date: Sun, 5 Jun 2016 15:35:43 -0600
Subject: [PATCH 066/400] Just update duty if frequency is not changed and PSM
started. This removeis glitch or blinking when only duty is frequently
changed.
---
arch/arm/src/stm32/stm32_pwm.c | 152 ++++++++++++++++++++++++++++++---
1 file changed, 138 insertions(+), 14 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c
index 06d6b2b080..d0ede86450 100644
--- a/arch/arm/src/stm32/stm32_pwm.c
+++ b/arch/arm/src/stm32/stm32_pwm.c
@@ -166,8 +166,8 @@ enum stm32_chanmode_e
struct stm32_pwmchan_s
{
- uint8_t channel; /* Timer output channel: {1,..4} */
- uint32_t pincfg; /* Output pin configuration */
+ uint8_t channel; /* Timer output channel: {1,..4} */
+ uint32_t pincfg; /* Output pin configuration */
enum stm32_chanmode_e mode;
};
@@ -176,21 +176,23 @@ struct stm32_pwmchan_s
struct stm32_pwmtimer_s
{
FAR const struct pwm_ops_s *ops; /* PWM operations */
- uint8_t timid; /* Timer ID {1,...,17} */
- struct stm32_pwmchan_s channels[PWM_NCHANNELS];
- uint8_t timtype; /* See the TIMTYPE_* definitions */
- enum stm32_timmode_e mode;
+ uint8_t timid; /* Timer ID {1,...,17} */
+ struct stm32_pwmchan_s channels[PWM_NCHANNELS];
+ uint8_t timtype; /* See the TIMTYPE_* definitions */
+ enum stm32_timmode_e mode;
#ifdef CONFIG_PWM_PULSECOUNT
- uint8_t irq; /* Timer update IRQ */
- uint8_t prev; /* The previous value of the RCR (pre-loaded) */
- uint8_t curr; /* The current value of the RCR (pre-loaded) */
- uint32_t count; /* Remaining pluse count */
+ uint8_t irq; /* Timer update IRQ */
+ uint8_t prev; /* The previous value of the RCR (pre-loaded) */
+ uint8_t curr; /* The current value of the RCR (pre-loaded) */
+ uint32_t count; /* Remaining pluse count */
+#else
+ int frequency; /* Current frequency setting */
#endif
- uint32_t base; /* The base address of the timer */
- uint32_t pclk; /* The frequency of the peripheral clock
+ uint32_t base; /* The base address of the timer */
+ uint32_t pclk; /* The frequency of the peripheral clock
* that drives the timer module. */
#ifdef CONFIG_PWM_PULSECOUNT
- FAR void *handle; /* Handle used for upper-half callback */
+ FAR void *handle; /* Handle used for upper-half callback */
#endif
};
@@ -1634,6 +1636,89 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
return OK;
}
+#ifndef CONFIG_PWM_PULSECOUNT
+/****************************************************************************
+ * Name: pwm_update_duty
+ *
+ * Description:
+ * Try to change only channel duty.
+ *
+ * Input parameters:
+ * priv - A reference to the lower half PWM driver state structure
+ * channel - Channel to by updated
+ * duty - New duty.
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_update_duty(FAR struct stm32_pwmtimer_s *priv, uint8_t channel,
+ ub16_t duty)
+{
+ /* Register offset */
+
+ int ccr_offset;
+
+ /* Calculated values */
+
+ uint32_t reload;
+ uint32_t ccr;
+
+ DEBUGASSERT(priv != NULL);
+
+ pwmvdbg("TIM%d channel: %d duty: %08x\n",
+ priv->timid, channel, duty);
+
+#ifndef CONFIG_PWM_MULTICHAN
+ DEBUGASSERT(channel == priv->channels[0].channel);
+ DEBUGASSERT(chan->duty >= 0 && chan->duty < uitoub16(100));
+#endif
+
+ /* Get the reload values */
+
+ reload = pwm_getreg(priv, STM32_GTIM_ARR_OFFSET);
+
+ /* Duty cycle:
+ *
+ * duty cycle = ccr / reload (fractional value)
+ */
+
+ ccr = b16toi(duty * reload + b16HALF);
+
+ pwmvdbg("ccr: %d\n", ccr);
+
+ switch (channel)
+ {
+ case 1: /* Register offset for Channel 1 */
+ ccr_offset = STM32_GTIM_CCR1_OFFSET;
+ break;
+
+ case 2: /* Register offset for Channel 2 */
+ ccr_offset = STM32_GTIM_CCR2_OFFSET;
+ break;
+
+ case 3: /* Register offset for Channel 3 */
+ ccr_offset = STM32_GTIM_CCR3_OFFSET;
+ break;
+
+ case 4: /* Register offset for Channel 4 */
+ ccr_offset = STM32_GTIM_CCR4_OFFSET;
+ break;
+
+ default:
+ pwmdbg("No such channel: %d\n", channel);
+ return -EINVAL;
+ }
+
+ /* Set the duty cycle by writing to the CCR register for this channel */
+
+ pwm_putreg(priv, ccr_offset, (uint16_t)ccr);
+
+ return OK;
+}
+#endif
+
/****************************************************************************
* Name: pwm_interrupt
*
@@ -2082,8 +2167,43 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
FAR const struct pwm_info_s *info)
{
+ int ret = OK;
FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
- return pwm_timer(priv, info);
+
+#ifndef CONFIG_PWM_PULSECOUNT
+ /* if frequency has not changed we just update duty */
+
+ if ( info->frequency == priv->frequency )
+ {
+#ifdef CONFIG_PWM_MULTICHAN
+ int i;
+
+ for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++)
+ {
+ ret = pwm_update_duty(priv,info->channels[i].channel,
+ info->channels[i].duty);
+ }
+#else
+ ret = pwm_update_duty(priv,priv->channels[0].channel,info->duty);
+#endif
+ }
+ else
+#endif
+ {
+ ret = pwm_timer(priv, info);
+
+#ifndef CONFIG_PWM_PULSECOUNT
+
+ /* Save current frequency */
+
+ if ( ret == OK )
+ {
+ priv->frequency = info->frequency;
+ }
+#endif
+ }
+
+ return ret;
}
#endif
@@ -2122,6 +2242,10 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
flags = enter_critical_section();
+ /* Stopped so frequency is zero */
+
+ priv->frequency = 0;
+
/* Disable further interrupts and stop the timer */
pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0);
--
GitLab
From 053ac343fd7dbb39061de356068d9a6f7ce1d218 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Sun, 5 Jun 2016 16:01:29 -0600
Subject: [PATCH 067/400] STM32 PWM: More review changes from last commit;
improve handling of unsigned types
---
arch/arm/src/stm32/stm32_pwm.c | 47 +++++++++++++++++-----------------
1 file changed, 23 insertions(+), 24 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c
index d0ede86450..8d43ddd551 100644
--- a/arch/arm/src/stm32/stm32_pwm.c
+++ b/arch/arm/src/stm32/stm32_pwm.c
@@ -186,7 +186,7 @@ struct stm32_pwmtimer_s
uint8_t curr; /* The current value of the RCR (pre-loaded) */
uint32_t count; /* Remaining pluse count */
#else
- int frequency; /* Current frequency setting */
+ uint32_t frequency; /* Current frequency setting */
#endif
uint32_t base; /* The base address of the timer */
uint32_t pclk; /* The frequency of the peripheral clock
@@ -760,7 +760,7 @@ static struct stm32_pwmtimer_s g_pwm13dev =
.irq = STM32_IRQ_TIM13,
#endif
.base = STM32_TIM13_BASE,
- .pclk = STM32_APB1_TIM13_CLKIN,
+ .pclk = STM32_APB1_TIM13_CLKIN,
};
#endif
@@ -1068,14 +1068,14 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
DEBUGASSERT(priv != NULL && info != NULL);
#if defined(CONFIG_PWM_MULTICHAN)
- pwmvdbg("TIM%d frequency: %d\n",
+ pwmvdbg("TIM%u frequency: %u\n",
priv->timid, info->frequency);
#elif defined(CONFIG_PWM_PULSECOUNT)
- pwmvdbg("TIM%d channel: %d frequency: %d duty: %08x count: %d\n",
+ pwmvdbg("TIM%u channel: %u frequency: %u duty: %08x count: %u\n",
priv->timid, priv->channel, info->frequency,
info->duty, info->count);
#else
- pwmvdbg("TIM%d channel: %d frequency: %d duty: %08x\n",
+ pwmvdbg("TIM%u channel: %u frequency: %u duty: %08x\n",
priv->timid, priv->channel, info->frequency, info->duty);
#endif
@@ -1146,7 +1146,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
reload = 65535;
}
- pwmvdbg("TIM%d PCLK: %d frequency: %d TIMCLK: %d prescaler: %d reload: %d\n",
+ pwmvdbg("TIM%u PCLK: %u frequency: %u TIMCLK: %u prescaler: %u reload: %u\n",
priv->timid, priv->pclk, info->frequency, timclk, prescaler, reload);
/* Set up the timer CR1 register:
@@ -1209,7 +1209,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
break;
default:
- pwmdbg("No such timer mode: %d\n", (int)priv->mode);
+ pwmdbg("No such timer mode: %u\n", (unsigned int)priv->mode);
return -EINVAL;
}
}
@@ -1336,7 +1336,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
if (j >= PWM_NCHANNELS)
{
- pwmdbg("No such channel: %d\n", channel);
+ pwmdbg("No such channel: %u\n", channel);
return -EINVAL;
}
#else
@@ -1352,7 +1352,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
ccr = b16toi(duty * reload + b16HALF);
- pwmvdbg("ccr: %d\n", ccr);
+ pwmvdbg("ccr: %u\n", ccr);
switch (mode)
{
@@ -1387,7 +1387,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
#endif
default:
- pwmdbg("No such mode: %d\n", (int)mode);
+ pwmdbg("No such mode: %u\n", (unsigned int)mode);
return -EINVAL;
}
@@ -1494,7 +1494,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
break;
default:
- pwmdbg("No such channel: %d\n", channel);
+ pwmdbg("No such channel: %u\n", channel);
return -EINVAL;
}
}
@@ -1667,7 +1667,7 @@ static int pwm_update_duty(FAR struct stm32_pwmtimer_s *priv, uint8_t channel,
DEBUGASSERT(priv != NULL);
- pwmvdbg("TIM%d channel: %d duty: %08x\n",
+ pwmvdbg("TIM%u channel: %u duty: %08x\n",
priv->timid, channel, duty);
#ifndef CONFIG_PWM_MULTICHAN
@@ -1686,7 +1686,7 @@ static int pwm_update_duty(FAR struct stm32_pwmtimer_s *priv, uint8_t channel,
ccr = b16toi(duty * reload + b16HALF);
- pwmvdbg("ccr: %d\n", ccr);
+ pwmvdbg("ccr: %u\n", ccr);
switch (channel)
{
@@ -1707,7 +1707,7 @@ static int pwm_update_duty(FAR struct stm32_pwmtimer_s *priv, uint8_t channel,
break;
default:
- pwmdbg("No such channel: %d\n", channel);
+ pwmdbg("No such channel: %u\n", channel);
return -EINVAL;
}
@@ -1795,7 +1795,7 @@ static int pwm_interrupt(struct stm32_pwmtimer_s *priv)
/* Now all of the time critical stuff is done so we can do some debug output */
- pwmllvdbg("Update interrupt SR: %04x prev: %d curr: %d count: %d\n",
+ pwmllvdbg("Update interrupt SR: %04x prev: %u curr: %u count: %u\n",
regval, priv->prev, priv->curr, priv->count);
return OK;
@@ -2030,7 +2030,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
uint32_t pincfg;
int i;
- pwmvdbg("TIM%d\n", priv->timid);
+ pwmvdbg("TIM%u\n", priv->timid);
pwm_dumpregs(priv, "Initially");
/* Enable APB1/2 clocking for timer. */
@@ -2078,7 +2078,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
uint32_t pincfg;
int i;
- pwmvdbg("TIM%d\n", priv->timid);
+ pwmvdbg("TIM%u\n", priv->timid);
/* Make sure that the output has been stopped */
@@ -2149,7 +2149,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
if (priv->timtype != TIMTYPE_ADVANCED)
{
- pwmdbg("ERROR: TIM%d cannot support pulse count: %d\n",
+ pwmdbg("ERROR: TIM%u cannot support pulse count: %u\n",
priv->timid, info->count);
return -EPERM;
}
@@ -2173,7 +2173,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
#ifndef CONFIG_PWM_PULSECOUNT
/* if frequency has not changed we just update duty */
- if ( info->frequency == priv->frequency )
+ if (info->frequency == priv->frequency)
{
#ifdef CONFIG_PWM_MULTICHAN
int i;
@@ -2193,10 +2193,9 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
ret = pwm_timer(priv, info);
#ifndef CONFIG_PWM_PULSECOUNT
-
/* Save current frequency */
- if ( ret == OK )
+ if (ret == OK)
{
priv->frequency = info->frequency;
}
@@ -2234,7 +2233,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
uint32_t regval;
irqstate_t flags;
- pwmvdbg("TIM%d\n", priv->timid);
+ pwmvdbg("TIM%u\n", priv->timid);
/* Disable interrupts momentary to stop any ongoing timer processing and
* to prevent any concurrent access to the reset register.
@@ -2389,7 +2388,7 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg
/* There are no platform-specific ioctl commands */
- pwmvdbg("TIM%d\n", priv->timid);
+ pwmvdbg("TIM%u\n", priv->timid);
#endif
return -ENOTTY;
}
@@ -2419,7 +2418,7 @@ FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer)
{
FAR struct stm32_pwmtimer_s *lower;
- pwmvdbg("TIM%d\n", timer);
+ pwmvdbg("TIM%u\n", timer);
switch (timer)
{
--
GitLab
From dbca089c96bd609d74bf37a834712438a791a353 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Mon, 6 Jun 2016 06:48:32 -0600
Subject: [PATCH 068/400] Update TODO list
---
TODO | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/TODO b/TODO
index b131d0205e..0ce0c457ef 100644
--- a/TODO
+++ b/TODO
@@ -1,4 +1,4 @@
-NuttX TODO List (Last updated May 28, 2016)
+NuttX TODO List (Last updated June 6, 2016)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -23,7 +23,7 @@ nuttx/:
(11) Libraries (libc/, libm/)
(11) File system/Generic drivers (fs/, drivers/)
(8) Graphics subsystem (graphics/)
- (1) Build system / Toolchains
+ (2) Build system / Toolchains
(3) Linux/Cywgin simulation (arch/sim)
(4) ARM (arch/arm/)
@@ -1601,6 +1601,14 @@ o Build system
Status: Open
Priority: Low.
+ Title: NATIVE WINDOWS BUILD BROKEN
+ Description: The way that apps/ no generates Kmenu files depends on changes added
+ to apps/tools/mkkconfig.sh. Similar changes need to be made to
+ apps/tools/mkkconfig.bat to restore the Windows Native build.
+ Status: Open
+ Priority: Low, since I am not aware of anyone using the Windows Native build.
+ But, of course, very high if you want to use it.
+
o Other drivers (drivers/)
^^^^^^^^^^^^^^^^^^^^^^^^
--
GitLab
From 85c6263a303f90ba9c702815abc2488b36981b7e Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Sun, 5 Jun 2016 14:21:02 -0600
Subject: [PATCH 069/400] tools/testbuild.sh was testing .config before
configured.
---
tools/testbuild.sh | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/tools/testbuild.sh b/tools/testbuild.sh
index 0a6ecb0bdf..31b0f9b4ea 100755
--- a/tools/testbuild.sh
+++ b/tools/testbuild.sh
@@ -136,15 +136,6 @@ function distclean {
fi
}
-# Check if build is NxWM and clean
-
-function nxcheck {
- unset nxconfig
- if [ -d $NXWDIR ]; then
- nxconfig=`grep CONFIG_NXWM=y $nuttx/.config`
- fi
-}
-
# Configure for the next build
function configure {
@@ -226,6 +217,11 @@ function nxbuild {
$UNLINK $APPSDIR/external
fi
+ unset nxconfig
+ if [ -d $NXWDIR ]; then
+ nxconfig=`grep CONFIG_NXWM=y $nuttx/.config`
+ fi
+
if [ ! -z "$nxconfig" ]; then
echo " Building NxWidgets..."
echo "------------------------------------------------------------------------------------"
@@ -261,7 +257,6 @@ function build {
function dotest {
echo "------------------------------------------------------------------------------------"
- nxcheck
distclean
configure
nxbuild
--
GitLab
From 3f7840f009b94bbac225103e0d08ed433acfc123 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Sun, 5 Jun 2016 14:21:24 -0600
Subject: [PATCH 070/400] Fix some NxWM configuration errors
---
configs/shenzhou/nxwm/defconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/configs/shenzhou/nxwm/defconfig b/configs/shenzhou/nxwm/defconfig
index 22489a72ce..37411bc91f 100644
--- a/configs/shenzhou/nxwm/defconfig
+++ b/configs/shenzhou/nxwm/defconfig
@@ -751,7 +751,7 @@ CONFIG_INPUT=y
# CONFIG_INPUT_TSC2007 is not set
CONFIG_INPUT_ADS7843E=y
# CONFIG_ADS7843E_MULTIPLE is not set
-CONFIG_ADS7843E_SPIDEV=0
+CONFIG_ADS7843E_SPIDEV=3
CONFIG_ADS7843E_DEVMINOR=0
CONFIG_ADS7843E_SPIMODE=0
CONFIG_ADS7843E_FREQUENCY=100000
@@ -1661,7 +1661,7 @@ CONFIG_NXWM_TOUCHSCREEN_DEVINIT=y
CONFIG_NXWM_TOUCHSCREEN_DEVNO=0
CONFIG_NXWM_TOUCHSCREEN_DEVPATH="/dev/input0"
CONFIG_NXWM_TOUCHSCREEN_SIGNO=5
-CONFIG_NXWM_TOUCHSCREEN_LISTENERPRIO=100
+CONFIG_NXWM_TOUCHSCREEN_LISTENERPRIO=101
CONFIG_NXWM_TOUCHSCREEN_LISTENERSTACK=1596
#
--
GitLab
From 56b018d5dbec89e9200eb15256367dc9c928346e Mon Sep 17 00:00:00 2001
From: "Paul A. Patience"
Date: Mon, 6 Jun 2016 12:01:13 -0400
Subject: [PATCH 071/400] STM32: Fix typo
---
arch/arm/include/stm32/chip.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h
index 98d0073c50..0a920ccee0 100644
--- a/arch/arm/include/stm32/chip.h
+++ b/arch/arm/include/stm32/chip.h
@@ -2430,7 +2430,7 @@
# if defined(CONFIG_ARCH_CHIP_STM32F469A)
# define STM32_NETHERNET 0 /* No Ethernet MAC */
# elif defined(CONFIG_ARCH_CHIP_STM32F469I) || \
-# defined(CONFIG_ARCH_CHIP_STM32F469B) || \
+ defined(CONFIG_ARCH_CHIP_STM32F469B) || \
defined(CONFIG_ARCH_CHIP_STM32F469N)
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# endif
--
GitLab
From e7bb9f714e420b38c9da95853c9693316d3d2a6f Mon Sep 17 00:00:00 2001
From: kfazz
Date: Mon, 6 Jun 2016 13:50:58 -0400
Subject: [PATCH 072/400] include so OK is defined.
---
configs/teensy-3.x/src/k20_appinit.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/teensy-3.x/src/k20_appinit.c b/configs/teensy-3.x/src/k20_appinit.c
index fd1b2bd5c8..a66f7a38b0 100644
--- a/configs/teensy-3.x/src/k20_appinit.c
+++ b/configs/teensy-3.x/src/k20_appinit.c
@@ -38,7 +38,7 @@
****************************************************************************/
#include
-
+#include
#include
#include "teensy-3x.h"
--
GitLab
From 0a4c58e573f9de6461250e3785c76f7c43afca45 Mon Sep 17 00:00:00 2001
From: kfazz
Date: Mon, 6 Jun 2016 13:58:07 -0400
Subject: [PATCH 073/400] First attempt at a usb device controller driver for
kinetis. derived from pic32mx usb driver, which uses the same usb controller.
---
arch/arm/src/kinetis/kinetis_usbdev.c | 4688 +++++++++++++++++++++++++
arch/arm/src/kinetis/kinetis_usbotg.h | 55 +-
2 files changed, 4741 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/src/kinetis/kinetis_usbdev.c
diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c
new file mode 100644
index 0000000000..75fcdb2cc7
--- /dev/null
+++ b/arch/arm/src/kinetis/kinetis_usbdev.c
@@ -0,0 +1,4688 @@
+/****************************************************************************
+ * arch/arm/src/kinetis/kinetis_usbdev.c
+ *
+ * Copyright (C) 2011-2014 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * References:
+ * This file derives from the STM32 USB device driver with modifications
+ * based on additional information from:
+ *
+ * - "USB On-The-Go (OTG)", DS61126E, Microchip Technology Inc., 2009
+ * - Sample code provided with the Sure Electronics PIC32 board
+ * (which seems to have derived from Microchip PICDEM PIC18 code).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "up_arch.h"
+//#include "pic32mx.h"
+//#include "pic32mx-usbotg.h"
+#include "kinetis.h"
+#include "kinetis_usbotg.h"
+#include "kinetis_sim.h"
+#include "kinetis_fmc.h"
+
+#if defined(CONFIG_USBDEV) && defined(CONFIG_KINETIS_USBOTG)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* Configuration ************************************************************/
+
+//#define CONFIG_USBOTG
+
+#ifndef CONFIG_USBDEV_EP0_MAXSIZE
+# define CONFIG_USBDEV_EP0_MAXSIZE 64
+#endif
+
+/* Extremely detailed register/BDT debug that you would normally never want
+ * enabled.
+ */
+
+#ifndef CONFIG_DEBUG
+# undef CONFIG_KHCI_USBDEV_REGDEBUG
+# undef CONFIG_KHCI_USBDEV_BDTDEBUG
+#endif
+
+//#define CONFIG_KHCI_USBDEV_REGDEBUG
+//#define CONFIG_KHCI_USBDEV_BDTDEBUG
+
+/* Disable this logic because it is buggy. It works most of the time but
+ * has some lurking issues that keep this higher performance solution from
+ * being usable.
+ */
+
+#undef CONFIG_USBDEV_NOREADAHEAD /* Makes no difference */
+
+#undef CONFIG_USBDEV_NOWRITEAHEAD
+#define CONFIG_USBDEV_NOWRITEAHEAD 1 /* Fixes some problems with IN transfers */
+
+/* Interrupts ***************************************************************/
+/* Initial interrupt sets */
+
+//#define CONFIG_USB_SOFINTS
+
+#ifdef CONFIG_USB_SOFINTS
+# define USB_SOF_INTERRUPT USB_INT_SOFTOK
+#else
+# define USB_SOF_INTERRUPT 0
+#endif
+
+#define ERROR_INTERRUPTS (USB_ERRSTAT_PIDERR | USB_ERRSTAT_CRC5EOF | \
+ USB_ERRSTAT_CRC16 | USB_ERRSTAT_DFN8 | USB_ERRSTAT_BTOERR | \
+ USB_ERRSTAT_BTSERR)
+
+#define NORMAL_INTERRUPTS (USB_INT_USBRST | USB_INT_ERROR | USB_SOF_INTERRUPT | \
+ USB_INT_TOKDNE | USB_INT_SLEEP | USB_INT_STALL)
+
+/* Endpoints ****************************************************************/
+
+#define USB_STAT_ENDPT(n) ((n) << USB_STAT_ENDP_SHIFT) /* Endpoint n, n=0..15 */
+
+#define USB_STAT_ODD_ODD USB_STAT_ODD /* The last transaction was to the ODD BD bank */
+#define USB_STAT_ODD_EVEN 0 /* The last transaction was to the EVEN BD bank */
+
+#define USB_STAT_TX_IN USB_STAT_TX /* Last transaction was a transmit transfer (TX) */
+#define USB_STAT_TX_OUT 0 /* Last transaction was a receive transfer (RX) */
+
+#define KHCI_NENDPOINTS (16)
+#define EP0 (0)
+
+#define KHCI_ENDP_BIT(ep) (1 << (ep))
+#define KHCI_ENDP_ALLSET 0xffff
+
+/* BDT Table Indexing. The BDT is addressed in the hardware as follows:
+ *
+ * Bits 9-31: These come the BDT address bits written into the BDTP3,
+ * BDTP2, and BDTP1 registers
+ * Bits 5-8: The endpoint number
+ * Bit 4: Direction:
+ * 1 = Transmit: SETUP/OUT for host, IN for function
+ * 0 = Receive: IN for host, SETUP/OUT for function
+ * Bit 3: PPBI, the ping point buffer index bit (0=EVEN, 1=ODD)
+ * Bits 0-2: Supports 8-byte BDT entries
+ */
+
+#define EP0_OUT_EVEN (0)
+#define EP0_OUT_ODD (1)
+#define EP0_IN_EVEN (2)
+#define EP0_IN_ODD (3)
+#define EP_OUT_EVEN(ep) ((int)(ep) << 2)
+#define EP_OUT_ODD(ep) (((int)(ep) << 2) + 1)
+#define EP_IN_EVEN(ep) (((int)(ep) << 2) + 2)
+#define EP_IN_ODD(ep) (((int)(ep) << 2) + 3)
+
+#define EP(ep,dir,pp) (((int)(ep) << 2) + ((int)(dir) << 1) + (int)(pp))
+#define EP_DIR_OUT 0
+#define EP_DIR_IN 1
+#define EP_PP_EVEN 0
+#define EP_PP_ODD 1
+
+/* Packet sizes. We use a fixed 64 max packet size for all endpoint types */
+
+#define KHCI_MAXPACKET_SHIFT (6)
+#define KHCI_MAXPACKET_SIZE (1 << (KHCI_MAXPACKET_SHIFT))
+
+#define KHCI_EP0MAXPACKET KHCI_MAXPACKET_SIZE
+
+/* Endpoint register initialization parameters */
+
+#define KHCI_EP_CONTROL (USB_ENDPT_EPHSHK|USB_ENDPT_EPTXEN|USB_ENDPT_EPRXEN)
+#define KHCI_EP_BULKIN (USB_ENDPT_EPTXEN|USB_ENDPT_EPCTLDIS|USB_ENDPT_EPHSHK)
+#define KHCI_EP_BULKOUT (USB_ENDPT_EPRXEN|USB_ENDPT_EPCTLDIS|USB_ENDPT_EPHSHK)
+#define KHCI_EP_INTIN (USB_ENDPT_EPTXEN|USB_ENDPT_EPCTLDIS|USB_ENDPT_EPHSHK)
+#define KHCI_EP_INTOUT (USB_ENDPT_EPRXEN|USB_ENDPT_EPCTLDIS|USB_ENDPT_EPHSHK)
+#define KHCI_EP_ISOCIN (USB_ENDPT_EPTXEN|USB_ENDPT_EPCTLDIS)
+#define KHCI_EP_ISOCOUT (USB_ENDPT_EPRXEN|USB_ENDPT_EPCTLDIS)
+
+/* USB-related masks */
+
+#define REQRECIPIENT_MASK (USB_REQ_TYPE_MASK | USB_REQ_RECIPIENT_MASK)
+
+/* Request queue operations *************************************************/
+
+#define khci_rqempty(q) ((q)->head == NULL)
+#define khci_rqhead(q) ((q)->head)
+#define khci_rqtail(q) ((q)->tail)
+
+#define RESTART_DELAY (150 * CLOCKS_PER_SEC / 1000)
+
+/* USB trace ****************************************************************/
+/* Trace error codes */
+
+#define KHCI_TRACEERR_ALLOCFAIL 0x0001
+#define KHCI_TRACEERR_BADCLEARFEATURE 0x0002
+#define KHCI_TRACEERR_BADDEVGETSTATUS 0x0003
+#define KHCI_TRACEERR_BADEPGETSTATUS 0x0004
+#define KHCI_TRACEERR_BADEPNO 0x0005
+#define KHCI_TRACEERR_BADEPTYPE 0x0006
+#define KHCI_TRACEERR_BADGETCONFIG 0x0007
+#define KHCI_TRACEERR_BADGETSETDESC 0x0008
+#define KHCI_TRACEERR_BADGETSTATUS 0x0009
+#define KHCI_TRACEERR_BADSETADDRESS 0x000a
+#define KHCI_TRACEERR_BADSETCONFIG 0x000b
+#define KHCI_TRACEERR_BADSETFEATURE 0x000c
+#define KHCI_TRACEERR_BINDFAILED 0x000d
+#define KHCI_TRACEERR_DISPATCHSTALL 0x000e
+#define KHCI_TRACEERR_DRIVER 0x000f
+#define KHCI_TRACEERR_DRIVERREGISTERED 0x0010
+#define KHCI_TRACEERR_EP0SETUPSTALLED 0x0011
+#define KHCI_TRACEERR_EPDISABLED 0x0012
+#define KHCI_TRACEERR_EPOUTNULLPACKET 0x0013
+#define KHCI_TRACEERR_EPRESERVE 0x0014
+#define KHCI_TRACEERR_INVALIDCTRLREQ 0x0015
+#define KHCI_TRACEERR_INVALIDPARMS 0x0016
+#define KHCI_TRACEERR_IRQREGISTRATION 0x0017
+#define KHCI_TRACEERR_NOTCONFIGURED 0x0018
+#define KHCI_TRACEERR_REQABORTED 0x0019
+#define KHCI_TRACEERR_INVALIDSTATE 0x001a
+
+/* Trace interrupt codes */
+
+#define KHCI_TRACEINTID_CLEARFEATURE 0x0001
+#define KHCI_TRACEINTID_DEVGETSTATUS 0x0002
+#define KHCI_TRACEINTID_DISPATCH 0x0003
+#define KHCI_TRACEINTID_EP0IN 0x0004
+#define KHCI_TRACEINTID_EP0INDONE 0x0005
+#define KHCI_TRACEINTID_EP0OUTDONE 0x0006
+#define KHCI_TRACEINTID_EP0SETUPDONE 0x0007
+#define KHCI_TRACEINTID_EP0SETUPSETADDRESS 0x0008
+#define KHCI_TRACEINTID_EP0ADDRESSSET 0x0009
+#define KHCI_TRACEINTID_EPGETSTATUS 0x000a
+#define KHCI_TRACEINTID_EPINDONE 0x000b
+#define KHCI_TRACEINTID_EPINQEMPTY 0x000c
+#define KHCI_TRACEINTID_EPOUTDONE 0x000d
+#define KHCI_TRACEINTID_EPOUTQEMPTY 0x000e
+#define KHCI_TRACEINTID_SOF 0x000f
+#define KHCI_TRACEINTID_GETCONFIG 0x0010
+#define KHCI_TRACEINTID_GETSETDESC 0x0011
+#define KHCI_TRACEINTID_GETSETIF 0x0012
+#define KHCI_TRACEINTID_GETSTATUS 0x0013
+#define KHCI_TRACEINTID_IFGETSTATUS 0x0014
+#define KHCI_TRACEINTID_TRNC 0x0015
+#define KHCI_TRACEINTID_TRNCS 0x0016
+#define KHCI_TRACEINTID_INTERRUPT 0x0017
+#define KHCI_TRACEINTID_NOSTDREQ 0x0018
+#define KHCI_TRACEINTID_RESET 0x0019
+#define KHCI_TRACEINTID_SETCONFIG 0x001a
+#define KHCI_TRACEINTID_SETFEATURE 0x001b
+#define KHCI_TRACEINTID_IDLE 0x001c
+#define KHCI_TRACEINTID_SYNCHFRAME 0x001d
+#define KHCI_TRACEINTID_WKUP 0x001e
+#define KHCI_TRACEINTID_T1MSEC 0x001f
+#define KHCI_TRACEINTID_OTGID 0x0020
+#define KHCI_TRACEINTID_STALL 0x0021
+#define KHCI_TRACEINTID_UERR 0x0022
+#define KHCI_TRACEINTID_SUSPENDED 0x0023
+#define KHCI_TRACEINTID_WAITRESET 0x0024
+
+
+
+#ifdef CONFIG_USBDEV_TRACE_STRINGS
+const struct trace_msg_t g_usb_trace_strings_intdecode[] =
+{
+ TRACE_STR(KHCI_TRACEINTID_CLEARFEATURE ), //0001
+ TRACE_STR(KHCI_TRACEINTID_DEVGETSTATUS ), //0002
+ TRACE_STR(KHCI_TRACEINTID_DISPATCH ), //0003
+ TRACE_STR(KHCI_TRACEINTID_EP0IN ), //0004
+ TRACE_STR(KHCI_TRACEINTID_EP0INDONE ), //0005
+ TRACE_STR(KHCI_TRACEINTID_EP0OUTDONE ), //0006
+ TRACE_STR(KHCI_TRACEINTID_EP0SETUPDONE ), //0007
+ TRACE_STR(KHCI_TRACEINTID_EP0SETUPSETADDRESS ), //0008
+ TRACE_STR(KHCI_TRACEINTID_EP0ADDRESSSET ), //0009
+ TRACE_STR(KHCI_TRACEINTID_EPGETSTATUS ), //000a
+ TRACE_STR(KHCI_TRACEINTID_EPINDONE ), //000b
+ TRACE_STR(KHCI_TRACEINTID_EPINQEMPTY ), //000c
+ TRACE_STR(KHCI_TRACEINTID_EPOUTDONE ), //000d
+ TRACE_STR(KHCI_TRACEINTID_EPOUTQEMPTY ), //000e
+ TRACE_STR(KHCI_TRACEINTID_SOF ), //000f
+ TRACE_STR(KHCI_TRACEINTID_GETCONFIG ), //0010
+ TRACE_STR(KHCI_TRACEINTID_GETSETDESC ), //0011
+ TRACE_STR(KHCI_TRACEINTID_GETSETIF ), //0012
+ TRACE_STR(KHCI_TRACEINTID_GETSTATUS ), //0013
+ TRACE_STR(KHCI_TRACEINTID_IFGETSTATUS ), //0014
+ TRACE_STR(KHCI_TRACEINTID_TRNC ), //0015
+ TRACE_STR(KHCI_TRACEINTID_TRNCS ), //0016
+ TRACE_STR(KHCI_TRACEINTID_INTERRUPT ), //0017
+ TRACE_STR(KHCI_TRACEINTID_NOSTDREQ ), //0018
+ TRACE_STR(KHCI_TRACEINTID_RESET ), //0019
+ TRACE_STR(KHCI_TRACEINTID_SETCONFIG ), //001a
+ TRACE_STR(KHCI_TRACEINTID_SETFEATURE ), //001b
+ TRACE_STR(KHCI_TRACEINTID_IDLE ), //001c
+ TRACE_STR(KHCI_TRACEINTID_SYNCHFRAME ), //001d
+ TRACE_STR(KHCI_TRACEINTID_WKUP ), //001e
+ TRACE_STR(KHCI_TRACEINTID_T1MSEC ), //001f
+ TRACE_STR(KHCI_TRACEINTID_OTGID ), //0020
+ TRACE_STR(KHCI_TRACEINTID_STALL ), //0021
+ TRACE_STR(KHCI_TRACEINTID_UERR ), //0022
+ TRACE_STR(KHCI_TRACEINTID_SUSPENDED ), //0023
+ TRACE_STR(KHCI_TRACEINTID_WAITRESET ), //0024
+ TRACE_STR_END
+};
+#endif
+
+#ifdef CONFIG_USBDEV_TRACE_STRINGS
+const struct trace_msg_t g_usb_trace_strings_deverror[] =
+{
+ TRACE_STR(KHCI_TRACEERR_ALLOCFAIL ), //0001
+ TRACE_STR(KHCI_TRACEERR_BADCLEARFEATURE ), //0002
+ TRACE_STR(KHCI_TRACEERR_BADDEVGETSTATUS ), //0003
+ TRACE_STR(KHCI_TRACEERR_BADEPGETSTATUS ), //0004
+ TRACE_STR(KHCI_TRACEERR_BADEPNO ), //0005
+ TRACE_STR(KHCI_TRACEERR_BADEPTYPE ), //0006
+ TRACE_STR(KHCI_TRACEERR_BADGETCONFIG ), //0007
+ TRACE_STR(KHCI_TRACEERR_BADGETSETDESC ), //0008
+ TRACE_STR(KHCI_TRACEERR_BADGETSTATUS ), //0009
+ TRACE_STR(KHCI_TRACEERR_BADSETADDRESS ), //000a
+ TRACE_STR(KHCI_TRACEERR_BADSETCONFIG ), //000b
+ TRACE_STR(KHCI_TRACEERR_BADSETFEATURE ), //000c
+ TRACE_STR(KHCI_TRACEERR_BINDFAILED ), //000d
+ TRACE_STR(KHCI_TRACEERR_DISPATCHSTALL ), //000e
+ TRACE_STR(KHCI_TRACEERR_DRIVER ), //000f
+ TRACE_STR(KHCI_TRACEERR_DRIVERREGISTERED ), //0010
+ TRACE_STR(KHCI_TRACEERR_EP0SETUPSTALLED ), //0011
+ TRACE_STR(KHCI_TRACEERR_EPDISABLED ), //0012
+ TRACE_STR(KHCI_TRACEERR_EPOUTNULLPACKET ), //0013
+ TRACE_STR(KHCI_TRACEERR_EPRESERVE ), //0014
+ TRACE_STR(KHCI_TRACEERR_INVALIDCTRLREQ ), //0015
+ TRACE_STR(KHCI_TRACEERR_INVALIDPARMS ), //0016
+ TRACE_STR(KHCI_TRACEERR_IRQREGISTRATION ), //0017
+ TRACE_STR(KHCI_TRACEERR_NOTCONFIGURED ), //0018
+ TRACE_STR(KHCI_TRACEERR_REQABORTED ), //0019
+ TRACE_STR(KHCI_TRACEERR_INVALIDSTATE ), //001a
+ TRACE_STR_END
+};
+#endif
+
+/* Misc Helper Macros *******************************************************/
+
+/* Ever-present MIN and MAX macros */
+
+#ifndef MIN
+# define MIN(a,b) (a < b ? a : b)
+#endif
+
+#ifndef MAX
+# define MAX(a,b) (a > b ? a : b)
+#endif
+
+/* Byte ordering in host-based values */
+
+#ifdef CONFIG_ENDIAN_BIG
+# define LSB 1
+# define MSB 0
+#else
+# define LSB 0
+# define MSB 1
+#endif
+
+/* Debug ********************************************************************/
+/* CONFIG_KHCI_USBDEV_REGDEBUG enables dumping of all low-level register
+ * access and BDT accesses. Normally, this generates so much debug output
+ * that USB may not even be functional.
+ */
+
+#ifdef CONFIG_KHCI_USBDEV_REGDEBUG
+
+# undef CONFIG_KHCI_USBDEV_BDTDEBUG
+# define CONFIG_KHCI_USBDEV_BDTDEBUG 1
+
+# define regdbg lldbg
+# ifdef CONFIG_DEBUG_VERBOSE
+# define regvdbg lldbg
+# else
+# define regvdbg(x...)
+# endif
+
+#else
+
+# define khci_getreg(addr) getreg8(addr)
+# define khci_putreg(val,addr) putreg8(val,addr)
+# define regdbg(x...)
+# define regvdbg(x...)
+
+#endif
+
+/* CONFIG_KHCI_USBDEV_BDTDEBUG dumps most BDT settings */
+
+#ifdef CONFIG_KHCI_USBDEV_BDTDEBUG
+
+# define bdtdbg lldbg
+# ifdef CONFIG_DEBUG_VERBOSE
+# define bdtvdbg lldbg
+# else
+# define bdtvdbg(x...)
+# endif
+
+#else
+
+# define bdtdbg(x...)
+# define bdtvdbg(x...)
+
+#endif
+
+/****************************************************************************
+ * Private Type Definitions
+ ****************************************************************************/
+
+/* Overvall device state */
+
+enum khci_devstate_e
+{
+ DEVSTATE_DETACHED = 0, /* Not connected to a host */
+ DEVSTATE_ATTACHED, /* Connected to a host */
+ DEVSTATE_POWERED, /* Powered */
+ DEVSTATE_DEFAULT, /* Default state */
+ DEVSTATE_ADDRPENDING, /* Waiting for an address */
+ DEVSTATE_ADDRESS, /* Address received */
+ DEVSTATE_CONFIGURED, /* Configuration received */
+};
+
+/* The various states of the control pipe */
+
+enum khci_ctrlstate_e
+{
+ CTRLSTATE_WAITSETUP = 0, /* No request in progress, waiting for setup */
+ CTRLSTATE_RDREQUEST, /* Read request (OUT) in progress */
+ CTRLSTATE_WRREQUEST, /* Write request (IN) in progress */
+ CTRLSTATE_STALL, /* EP0 stall requested */
+ CTRLSTATE_STALLED /* EP0 is stalled */
+};
+
+union wb_u
+{
+ uint16_t w;
+ uint8_t b[2];
+};
+
+/* A container for a request so that the request make be retained in a
+ * singly-linked list.
+ */
+
+struct khci_req_s
+{
+ struct usbdev_req_s req; /* Standard USB request */
+#ifdef CONFIG_USBDEV_NOWRITEAHEAD
+ uint16_t inflight[1]; /* The number of bytes "in-flight" */
+#else
+ uint16_t inflight[2]; /* The number of bytes "in-flight" */
+#endif
+ struct khci_req_s *flink; /* Supports a singly linked list */
+};
+
+/* This structure represents the 'head' of a singly linked list of requests */
+
+struct khci_queue_s
+{
+ struct khci_req_s *head; /* Head of the request queue */
+ struct khci_req_s *tail; /* Tail of the request queue */
+};
+
+/* This is the internal representation of an endpoint */
+
+struct khci_ep_s
+{
+ /* Common endpoint fields. This must be the first thing defined in the
+ * structure so that it is possible to simply cast from struct usbdev_ep_s
+ * to struct khci_ep_s.
+ */
+
+ struct usbdev_ep_s ep; /* Standard endpoint structure */
+
+ /* KHCI-specific fields */
+
+ struct khci_usbdev_s *dev; /* Reference to private driver data */
+ struct khci_queue_s pend; /* List of pending (inactive) requests for this endpoint */
+ struct khci_queue_s active; /* List of active requests for this endpoint */
+ uint8_t stalled:1; /* true: Endpoint is stalled */
+ uint8_t halted:1; /* true: Endpoint feature halted */
+ uint8_t txnullpkt:1; /* Null packet needed at end of TX transfer */
+ uint8_t txdata1:1; /* Data0/1 of next TX transfer */
+ uint8_t rxdata1:1; /* Data0/1 of next RX transfer */
+ volatile struct usbotg_bdtentry_s *bdtin; /* BDT entry for the IN transaction */
+ volatile struct usbotg_bdtentry_s *bdtout; /* BDT entry for the OUT transaction */
+};
+
+struct khci_usbdev_s
+{
+ /* Common device fields. This must be the first thing defined in the
+ * structure so that it is possible to simply cast from struct usbdev_s
+ * to structkhci_usbdev_s.
+ */
+
+ struct usbdev_s usbdev;
+
+ /* The bound device class driver */
+
+ struct usbdevclass_driver_s *driver;
+
+ /* KHCI-specific fields */
+
+ struct usb_ctrlreq_s ctrl; /* Last EP0 request */
+ uint8_t devstate; /* Driver state (see enum khci_devstate_e) */
+ uint8_t ctrlstate; /* Control EP state (see enum khci_ctrlstate_e) */
+ uint8_t selfpowered:1; /* 1: Device is self powered */
+ uint8_t rwakeup:1; /* 1: Device supports remote wakeup */
+ uint8_t attached:1; /* Device is attached to the host */
+ uint8_t ep0done:1; /* EP0 OUT already prepared */
+ uint8_t rxbusy:1; /* EP0 OUT data transfer in progress */
+ uint16_t epavail; /* Bitset of available endpoints */
+ uint16_t epstalled; /* Bitset of stalled endpoints */
+ WDOG_ID wdog; /* Supports the restart delay */
+
+ /* The endpoint list */
+
+ struct khci_ep_s eplist[KHCI_NENDPOINTS];
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Register operations ******************************************************/
+
+#ifdef CONFIG_KHCI_USBDEV_REGDEBUG
+static uint16_t khci_getreg(uint32_t addr);
+static void khci_putreg(uint32_t val, uint32_t addr);
+#endif
+
+/* Suspend/Resume Helpers ***************************************************/
+
+static void khci_suspend(struct khci_usbdev_s *priv);
+static void khci_resume(struct khci_usbdev_s *priv);
+
+/* Request Queue Management *************************************************/
+
+static struct khci_req_s *khci_remfirst(struct khci_queue_s *queue);
+static struct khci_req_s *khci_remlast(struct khci_queue_s *queue);
+static void khci_addlast(struct khci_queue_s *queue,
+ struct khci_req_s *req);
+static void khci_addfirst(struct khci_queue_s *queue,
+ struct khci_req_s *req);
+
+/* Request Helpers **********************************************************/
+
+static void khci_reqreturn(struct khci_ep_s *privep,
+ struct khci_req_s *privreq, int16_t result);
+static void khci_reqcomplete(struct khci_ep_s *privep,
+ int16_t result);
+static void khci_epwrite(struct khci_ep_s *privep,
+ volatile struct usbotg_bdtentry_s *bdt,
+ const uint8_t *src, uint32_t nbytes);
+static void khci_wrcomplete(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep);
+static void khci_rqrestart(int argc, uint32_t arg1, ...);
+static void khci_delayedrestart(struct khci_usbdev_s *priv,
+ uint8_t epno);
+static void khci_rqstop(struct khci_ep_s *privep);
+static int khci_wrstart(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep);
+static int khci_wrrequest(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep);
+static int khci_rdcomplete(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep);
+static int khci_ep0rdsetup(struct khci_usbdev_s *priv,
+ uint8_t *dest, int readlen);
+static int khci_rdsetup(struct khci_ep_s *privep, uint8_t *dest,
+ int readlen);
+static int khci_rdrequest(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep);
+static void khci_cancelrequests(struct khci_ep_s *privep,
+ int16_t result);
+
+/* Interrupt level processing ***********************************************/
+
+static void khci_dispatchrequest(struct khci_usbdev_s *priv);
+static void khci_ep0stall(struct khci_usbdev_s *priv);
+static void khci_eptransfer(struct khci_usbdev_s *priv, uint8_t epno,
+ uint16_t ustat);
+static void khci_ep0nextsetup(struct khci_usbdev_s *priv);
+static void khci_ep0rdcomplete(struct khci_usbdev_s *priv);
+static void khci_ep0setup(struct khci_usbdev_s *priv);
+static void khci_ep0outcomplete(struct khci_usbdev_s *priv);
+static void khci_ep0incomplete(struct khci_usbdev_s *priv);
+static void khci_ep0transfer(struct khci_usbdev_s *priv,
+ uint16_t ustat);
+static int khci_interrupt(int irq, void *context);
+
+/* Endpoint helpers *********************************************************/
+
+static inline struct khci_ep_s *
+ khci_epreserve(struct khci_usbdev_s *priv, uint8_t epset);
+static inline void
+ khci_epunreserve(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep);
+static inline bool
+ khci_epreserved(struct khci_usbdev_s *priv, int epno);
+static void khci_ep0configure(struct khci_usbdev_s *priv);
+
+/* Endpoint operations ******************************************************/
+
+static int khci_epconfigure(struct usbdev_ep_s *ep,
+ const struct usb_epdesc_s *desc, bool last);
+static int khci_epdisable(struct usbdev_ep_s *ep);
+static struct usbdev_req_s *
+ khci_epallocreq(struct usbdev_ep_s *ep);
+static void khci_epfreereq(struct usbdev_ep_s *ep,
+ struct usbdev_req_s *);
+static int khci_epsubmit(struct usbdev_ep_s *ep,
+ struct usbdev_req_s *req);
+static int khci_epcancel(struct usbdev_ep_s *ep,
+ struct usbdev_req_s *req);
+static int khci_epbdtstall(struct usbdev_ep_s *ep, bool resume,
+ bool epin);
+static int khci_epstall(struct usbdev_ep_s *ep, bool resume);
+
+/* USB device controller operations *****************************************/
+
+static struct usbdev_ep_s *
+ khci_allocep(struct usbdev_s *dev, uint8_t epno, bool in,
+ uint8_t eptype);
+static void khci_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep);
+static int khci_getframe(struct usbdev_s *dev);
+static int khci_wakeup(struct usbdev_s *dev);
+static int khci_selfpowered(struct usbdev_s *dev, bool selfpowered);
+
+/* Initialization/Reset *****************************************************/
+
+static void khci_reset(struct khci_usbdev_s *priv);
+static void khci_attach(struct khci_usbdev_s *priv);
+static void khci_detach(struct khci_usbdev_s *priv);
+static void khci_swreset(struct khci_usbdev_s *priv);
+static void khci_hwreset(struct khci_usbdev_s *priv);
+static void khci_stateinit(struct khci_usbdev_s *priv);
+static void khci_hwshutdown(struct khci_usbdev_s *priv);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Since there is only a single USB interface, all status information can be
+ * be simply retained in a single global instance.
+ */
+
+static struct khci_usbdev_s g_usbdev;
+
+static const struct usbdev_epops_s g_epops =
+{
+ .configure = khci_epconfigure,
+ .disable = khci_epdisable,
+ .allocreq = khci_epallocreq,
+ .freereq = khci_epfreereq,
+ .submit = khci_epsubmit,
+ .cancel = khci_epcancel,
+ .stall = khci_epstall,
+};
+
+static const struct usbdev_ops_s g_devops =
+{
+ .allocep = khci_allocep,
+ .freeep = khci_freeep,
+ .getframe = khci_getframe,
+ .wakeup = khci_wakeup,
+ .selfpowered = khci_selfpowered,
+ .pullup = kinetis_usbpullup,
+};
+
+/* Buffer Descriptor Table. Four BDT entries per endpoint
+ *
+ * The BDT is addressed in the hardware as follows:
+ *
+ * Bits 9-31: These come the BDT address bits written into the BDTP3, BDTP2
+ * and BDTP1 registers
+ * Bits 5-8: The endpoint number
+ * Bit 4: Direction (0=IN/Tx, 1 = OUT/Rx)
+ * Bit 3: PPBI, the ping point buffer index bit.
+ * Bits 0-2: Supports 8-byte BDT entries
+ */
+
+static volatile struct usbotg_bdtentry_s g_bdt[4*KHCI_NENDPOINTS]
+ __attribute__ ((aligned(512)));
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Register Operations
+ ****************************************************************************/
+/****************************************************************************
+ * Name: khci_getreg
+ ****************************************************************************/
+
+#ifdef CONFIG_KHCI_USBDEV_REGDEBUG
+static uint16_t khci_getreg(uint32_t addr)
+{
+ static uint32_t prevaddr = 0;
+ static uint32_t preval = 0;
+ static uint32_t count = 0;
+
+ /* Read the value from the register */
+
+ uint16_t val = getreg8(addr);
+
+ /* Is this the same value that we read from the same register last time?
+ * Are we polling the register? If so, suppress some of the output.
+ */
+
+ if (addr == prevaddr && val == preval)
+ {
+ if (count == 0xffffffff || ++count > 3)
+ {
+ if (count == 4)
+ {
+ lldbg("...\n");
+ }
+ return val;
+ }
+ }
+
+ /* No this is a new address or value */
+
+ else
+ {
+ /* Did we print "..." for the previous value? */
+
+ if (count > 3)
+ {
+ /* Yes.. then show how many times the value repeated */
+
+ lldbg("[repeats %d more times]\n", count-3);
+ }
+
+ /* Save the new address, value, and count */
+
+ prevaddr = addr;
+ preval = val;
+ count = 1;
+ }
+
+ /* Show the register value read */
+
+ lldbg("%08x->%04x\n", addr, val);
+ return val;
+}
+#endif
+
+/****************************************************************************
+ * Name: khci_putreg
+ ****************************************************************************/
+
+#ifdef CONFIG_KHCI_USBDEV_REGDEBUG
+static void khci_putreg(uint32_t val, uint32_t addr)
+{
+ /* Show the register value being written */
+
+ lldbg("%08x<-%04x\n", addr, val);
+
+ /* Write the value */
+
+ putreg8(val, addr);
+}
+#endif
+
+/****************************************************************************
+ * Request Helpers
+ ****************************************************************************/
+/****************************************************************************
+ * Name: khci_remfirst
+ ****************************************************************************/
+
+static struct khci_req_s *khci_remfirst(struct khci_queue_s *queue)
+{
+ struct khci_req_s *ret = queue->head;
+
+ if (ret)
+ {
+ queue->head = ret->flink;
+ if (!queue->head)
+ {
+ queue->tail = NULL;
+ }
+
+ ret->flink = NULL;
+ }
+
+ return ret;
+}
+
+
+/****************************************************************************
+ * Name: khci_remlast
+ ****************************************************************************/
+
+static struct khci_req_s *khci_remlast(struct khci_queue_s *queue)
+{
+ struct khci_req_s *prev;
+ struct khci_req_s *ret = queue->tail;
+
+ ret = queue->tail;
+ if (ret)
+ {
+ if (queue->head == queue->tail)
+ {
+ queue->head = NULL;
+ queue->tail = NULL;
+ }
+ else
+ {
+ for (prev = queue->head;
+ prev && prev->flink != ret;
+ prev = prev->flink);
+
+ if (prev)
+ {
+ prev->flink = NULL;
+ queue->tail = prev;
+ }
+ }
+
+ ret->flink = NULL;
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: khci_addlast
+ ****************************************************************************/
+
+static void khci_addlast(struct khci_queue_s *queue, struct khci_req_s *req)
+{
+ req->flink = NULL;
+ if (!queue->head)
+ {
+ queue->head = req;
+ queue->tail = req;
+ }
+ else
+ {
+ queue->tail->flink = req;
+ queue->tail = req;
+ }
+}
+
+/****************************************************************************
+ * Name: khci_addfirst
+ ****************************************************************************/
+
+static void khci_addfirst(struct khci_queue_s *queue, struct khci_req_s *req)
+{
+ req->flink = queue->head;
+ if (!queue->head)
+ {
+ queue->tail = req;
+ }
+ queue->head = req;
+}
+
+/****************************************************************************
+ * Name: khci_reqreturn
+ ****************************************************************************/
+
+static void khci_reqreturn(struct khci_ep_s *privep,
+ struct khci_req_s *privreq, int16_t result)
+{
+ /* If endpoint 0, temporarily reflect the state of protocol stalled
+ * in the callback.
+ */
+
+ bool stalled = privep->stalled;
+ if (USB_EPNO(privep->ep.eplog) == EP0)
+ {
+ privep->stalled = (privep->dev->ctrlstate == CTRLSTATE_STALLED);
+ }
+
+ /* Save the result in the request structure */
+
+ privreq->req.result = result;
+
+ /* Callback to the request completion handler */
+
+ privreq->flink = NULL;
+ privreq->req.callback(&privep->ep, &privreq->req);
+
+ /* Restore the stalled indication */
+
+ privep->stalled = stalled;
+}
+
+/****************************************************************************
+ * Name: khci_reqcomplete
+ ****************************************************************************/
+
+static void khci_reqcomplete(struct khci_ep_s *privep, int16_t result)
+{
+ struct khci_req_s *privreq;
+ irqstate_t flags;
+
+ /* Remove the completed request at the head of the endpoint's active
+ * request list.
+ */
+
+ flags = enter_critical_section();
+ privreq = khci_remfirst(&privep->active);
+ leave_critical_section(flags);
+
+ if (privreq)
+ {
+ /* Return the request to the class driver */
+
+ khci_reqreturn(privep, privreq, result);
+ }
+}
+
+/****************************************************************************
+ * Name: khci_epwrite
+ ****************************************************************************/
+
+static void khci_epwrite(struct khci_ep_s *privep,
+ volatile struct usbotg_bdtentry_s *bdt,
+ const uint8_t *src, uint32_t nbytes)
+{
+ uint32_t status;
+
+ usbtrace(TRACE_WRITE(USB_EPNO(privep->ep.eplog)), nbytes);
+
+ /* Clear all bits in the status (assuring that we own the BDT) */
+
+ bdt->status = 0;
+
+ /* Get the correct data toggle (as well as other BDT bits) */
+
+ if (privep->txdata1)
+ {
+ status = (USB_BDT_UOWN | USB_BDT_DATA1 | USB_BDT_DTS);
+ privep->txdata1 = 0;
+ }
+ else
+ {
+ status = (USB_BDT_UOWN | USB_BDT_DATA0 | USB_BDT_DTS);
+ privep->txdata1 = 1;
+ }
+
+ /* Set the data pointer and data length */
+
+ bdt->addr = (uint8_t *)src;
+ status |= (nbytes << USB_BDT_BYTECOUNT_SHIFT) | USB_BDT_DTS;
+
+ /* And, finally, give the BDT to the USB */
+
+ bdtdbg("EP%d BDT IN [%p] {%08x, %08x}\n",
+ USB_EPNO(privep->ep.eplog), bdt, status, bdt->addr);
+
+ bdt->status = status;
+}
+
+/****************************************************************************
+ * Name: khci_wrcomplete
+ ****************************************************************************/
+
+static void khci_wrcomplete(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep)
+{
+ volatile struct usbotg_bdtentry_s *bdtin;
+ struct khci_req_s *privreq;
+ int bytesleft;
+ int epno;
+
+ /* Check the request at the head of the endpoint's active request queue.
+ * Since we got here from a write completion event, the active request queue
+ * should not be empty.
+ */
+
+ privreq = khci_rqhead(&privep->active);
+ DEBUGASSERT(privreq != NULL);
+
+ /* An outgoing IN packet has completed. bdtin should point to the BDT
+ * that just completed.
+ */
+
+ bdtin = privep->bdtin;
+ epno = USB_EPNO(privep->ep.eplog);
+
+#ifdef CONFIG_USBDEV_NOWRITEAHEAD
+ ullvdbg("EP%d: len=%d xfrd=%d inflight=%d\n",
+ epno, privreq->req.len, privreq->req.xfrd, privreq->inflight[0]);
+#else
+ ullvdbg("EP%d: len=%d xfrd=%d inflight={%d, %d}\n",
+ epno, privreq->req.len, privreq->req.xfrd,
+ privreq->inflight[0], privreq->inflight[1]);
+#endif
+ bdtdbg("EP%d BDT IN [%p] {%08x, %08x}\n",
+ epno, bdtin, bdtin->status, bdtin->addr);
+
+ /* We should own the BDT that just completed. But NULLify the entire BDT IN.
+ * Why? So that we can tell later that the BDT available. No, it is not
+ * sufficient to look at the UOWN bit. If UOWN==0, then the transfer has
+ * been completed BUT it may not yet have been processed. But a completely
+ * NULLified BDT is a sure indication
+ */
+
+ DEBUGASSERT((bdtin->status & USB_BDT_UOWN) == USB_BDT_COWN);
+ bdtin->status = 0;
+ bdtin->addr = 0;
+
+ /* Toggle bdtin to the other BDT. Is the current bdtin the EVEN bdt? */
+
+ privep->bdtin = &g_bdt[EP_IN_EVEN(epno)];
+ if (bdtin == privep->bdtin)
+ {
+ /* Yes.. Then the other BDT is the ODD BDT */
+
+ privep->bdtin++;
+ }
+
+ /* Update the number of bytes transferred. */
+
+ privreq->req.xfrd += privreq->inflight[0];
+#ifdef CONFIG_USBDEV_NOWRITEAHEAD
+ privreq->inflight[0] = 0;
+#else
+ privreq->inflight[0] = privreq->inflight[1];
+ privreq->inflight[1] = 0;
+#endif
+ bytesleft = privreq->req.len - privreq->req.xfrd;
+
+ /* If all of the bytes were sent (bytesleft == 0) and no NULL packet is
+ * needed (!txnullpkt), then we are finished with the transfer
+ */
+
+ if (bytesleft == 0 && !privep->txnullpkt)
+ {
+ /* The transfer is complete. Give the completed request back to
+ * the class driver.
+ */
+
+ usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd);
+ khci_reqcomplete(privep, OK);
+
+ /* Special case writes to endpoint zero. If there is no transfer in
+ * progress, then we need to configure to received the next SETUP packet.
+ */
+
+ if (USB_EPNO(privep->ep.eplog) == 0)
+ {
+ priv->ctrlstate = CTRLSTATE_WAITSETUP;
+ }
+ }
+}
+
+/****************************************************************************
+ * Name: khci_rqrestart
+ ****************************************************************************/
+
+static void khci_rqrestart(int argc, uint32_t arg1, ...)
+{
+ struct khci_usbdev_s *priv;
+ struct khci_ep_s *privep;
+ struct khci_req_s *privreq;
+ uint16_t epstalled;
+ uint16_t mask;
+ int epno;
+
+ /* Recover the pointer to the driver structure */
+
+ priv = (struct khci_usbdev_s *)((uintptr_t)arg1);
+ DEBUGASSERT(priv != NULL);
+
+ /* Sample and clear the set of endpoints that have recovered from a stall */
+
+ epstalled = priv->epstalled;
+ priv->epstalled = 0;
+
+ /* Loop, checking each bit in the epstalled bit set */
+
+ for (epno = 0; epstalled && epno < KHCI_NENDPOINTS; epno++)
+ {
+ /* Has this encpoint recovered from a stall? */
+
+ mask = (1 << epno);
+ if ((epstalled & mask) != 0)
+ {
+ /* Yes, this endpoint needs to be restarteed */
+
+ epstalled &= ~mask;
+ privep = &priv->eplist[epno];
+
+ /* Reset some endpoint state variables */
+
+ privep->stalled = false;
+ privep->txnullpkt = false;
+
+ /* Check the request at the head of the endpoint's pending request queue */
+
+ privreq = khci_rqhead(&privep->pend);
+ if (privreq)
+ {
+ /* Restart transmission after we have recovered from a stall */
+
+ privreq->req.xfrd = 0;
+ privreq->inflight[0] = 0;
+#ifndef CONFIG_USBDEV_NOWRITEAHEAD
+ privreq->inflight[1] = 0;
+#endif
+ (void)khci_wrrequest(priv, privep);
+ }
+ }
+ }
+}
+
+/****************************************************************************
+ * Name: khci_delayedrestart
+ ****************************************************************************/
+
+static void khci_delayedrestart(struct khci_usbdev_s *priv, uint8_t epno)
+{
+ /* Add endpoint to the set of endpoints that need to be restarted */
+
+ priv->epstalled |= (1 << epno);
+
+ /* And start (or re-start) the watchdog timer */
+
+ wd_start(priv->wdog, RESTART_DELAY, khci_rqrestart, 1, (uint32_t)priv);
+}
+
+/****************************************************************************
+ * Name: khci_rqstop
+ ****************************************************************************/
+
+static void khci_rqstop(struct khci_ep_s *privep)
+{
+ struct khci_req_s *privreq;
+
+ /* Move all of the active requests back to the pending request queue */
+
+ while ((privreq = khci_remlast(&privep->active)))
+ {
+ /* Move the request back to the head of the pending list */
+
+ khci_addfirst(&privep->pend, privreq);
+ }
+}
+
+/****************************************************************************
+ * Name: khci_wrstart
+ ****************************************************************************/
+
+static int khci_wrstart(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep)
+{
+ volatile struct usbotg_bdtentry_s *bdt;
+ struct khci_req_s *privreq;
+ uint8_t *buf;
+ uint8_t epno;
+ int nbytes;
+ int bytesleft;
+ int xfrd;
+ int index;
+
+ /* We get here when either (1) an IN endpoint completion interrupt occurs,
+ * or (2) a new write request is reqeived from the class.
+ */
+
+ /* Get the endpoint number that we are servicing */
+
+ epno = USB_EPNO(privep->ep.eplog);
+
+ /* Decide which BDT to use. bdtin points to the "current" BDT. That is,
+ * the one that either (1) available for next transfer, or (2) the one
+ * that is currently busy with the current transfer. If the current
+ * BDT is busy, we have the option of setting up the other BDT in advance
+ * in order to improve data transfer performance.
+ */
+
+ bdt = privep->bdtin;
+ index = 0;
+
+ if (bdt->status || bdt->addr)
+ {
+#ifdef CONFIG_USBDEV_NOWRITEAHEAD
+ /* The current BDT is not available and write ahead is disabled. There
+ * is nothing we can do now. Return -EBUSY to indicate this condition.
+ */
+
+ return -EBUSY;
+#else
+ /* The current BDT is not available, check the other BDT */
+
+ volatile struct usbotg_bdtentry_s *otherbdt;
+ otherbdt = &g_bdt[EP(epno, EP_DIR_IN, EP_PP_EVEN)];
+ if (otherbdt == bdt)
+ {
+ otherbdt++;
+ }
+
+ /* Is it available? */
+
+ if (otherbdt->status || otherbdt->addr)
+ {
+ /* No, neither are available. We cannot perform the transfer now.
+ * Return -EBUSY to indicate this condition.
+ */
+
+ return -EBUSY;
+ }
+
+ /* Yes... use the other BDT */
+
+ bdt = otherbdt;
+ index = 1;
+#endif
+ }
+
+ /* A BDT is available. Which request should we be operating on? The last
+ * incomplete, active request would be at the tail of the active list.
+ */
+
+ privreq = khci_rqtail(&privep->active);
+
+ /* This request would be NULL if there is no incomplete, active request. */
+
+ if (privreq)
+ {
+ /* Get the number of bytes left to be transferred in the request */
+
+ xfrd = privreq->req.xfrd;
+ bytesleft = privreq->req.len - xfrd;
+
+ /* Even if the request is incomplete, transfer of all the requested
+ * bytes may already been started. NOTE: inflight[1] should be zero
+ * because we know that there is a BDT available.
+ */
+
+#ifndef CONFIG_USBDEV_NOWRITEAHEAD
+ DEBUGASSERT(privreq->inflight[1] == 0);
+#endif
+ /* Has the transfer been initiated for all of the bytes? */
+
+ if (bytesleft > privreq->inflight[0])
+ {
+ /* No.. we have more work to do with this request */
+
+ xfrd += privreq->inflight[0];
+ bytesleft -= privreq->inflight[0];
+ }
+
+ /* Do we need to send a null packet after this packet? */
+
+ else if (privep->txnullpkt)
+ {
+ /* Yes... set up for the NULL packet transfer */
+
+ xfrd = privreq->req.len;
+ bytesleft = 0;
+ }
+ else
+ {
+ /* No.. We are finished with this request. We need to get the
+ * next request from the head of the pending request list.
+ */
+
+ privreq = NULL;
+ }
+ }
+
+ /* If privreq is NULL here then either (1) there is no active request, or
+ * (2) the (only) active request is fully queued. In either case, we need
+ * to get the next request from the head of the pending request list.
+ */
+
+ if (!privreq)
+ {
+ /* Remove the next request from the head of the pending request list */
+
+ privreq = khci_remfirst(&privep->pend);
+ if (!privreq)
+ {
+ /* The pending request list is empty. There are no queued TX
+ * requests to be sent.
+ */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPINQEMPTY), epno);
+
+ /* Return -ENODATA to indicate that there are no further requests
+ * to be processed.
+ */
+
+ return -ENODATA;
+ }
+
+ /* Add this request to the tail of the active request list */
+
+ khci_addlast(&privep->active, privreq);
+
+ /* Set up the first transfer for this request */
+
+ xfrd = 0;
+ bytesleft = privreq->req.len;
+ }
+
+ ullvdbg("epno=%d req=%p: len=%d xfrd=%d index=%d nullpkt=%d\n",
+ epno, privreq, privreq->req.len, xfrd, index, privep->txnullpkt);
+
+ /* Get the number of bytes left to be sent in the packet */
+
+ nbytes = bytesleft;
+ if (nbytes > 0 || privep->txnullpkt)
+ {
+ /* Either send the maxpacketsize or all of the remaining data in
+ * the request.
+ */
+
+ privep->txnullpkt = 0;
+ if (nbytes >= privep->ep.maxpacket)
+ {
+ nbytes = privep->ep.maxpacket;
+
+ /* Handle the case where this packet is exactly the
+ * maxpacketsize. Do we need to send a zero-length packet
+ * in this case?
+ */
+
+ if (bytesleft == privep->ep.maxpacket &&
+ (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0)
+ {
+ privep->txnullpkt = 1;
+ }
+ }
+ }
+
+ /* Send the packet (might be a null packet with nbytes == 0) */
+
+ buf = privreq->req.buf + xfrd;
+
+ /* Setup the writes to the endpoints */
+
+ khci_epwrite(privep, bdt, buf, nbytes);
+
+ /* Special case endpoint 0 state information. The write request is in
+ * progress.
+ */
+
+ if (epno == 0)
+ {
+ priv->ctrlstate = CTRLSTATE_WRREQUEST;
+ }
+
+ /* Update for the next data IN interrupt */
+
+ privreq->inflight[index] = nbytes;
+ return OK;
+}
+
+/****************************************************************************
+ * Name: khci_wrrequest
+ ****************************************************************************/
+
+static int khci_wrrequest(struct khci_usbdev_s *priv, struct khci_ep_s *privep)
+{
+ int ret;
+
+ /* Always try to start two transfers in order to take advantage of the
+ * KHCI's ping pong buffering.
+ */
+
+ ret = khci_wrstart(priv, privep);
+#ifndef CONFIG_USBDEV_NOWRITEAHEAD
+ if (ret == OK)
+ {
+ /* Note: We need to return the error condition only if nothing was
+ * queued
+ */
+
+ (void)khci_wrstart(priv, privep);
+ }
+#else
+ UNUSED(ret);
+#endif
+
+ /* We return OK to indicate that a write request is still in progress */
+
+ return khci_rqhead(&privep->active) == NULL ? -ENODATA : OK;
+}
+
+/****************************************************************************
+ * Name: khci_rdcomplete
+ ****************************************************************************/
+
+static int khci_rdcomplete(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep)
+{
+ volatile struct usbotg_bdtentry_s *bdtout;
+ struct khci_req_s *privreq;
+ int epno;
+
+ /* Check the request at the head of the endpoint's active request queue */
+
+ privreq = khci_rqhead(&privep->active);
+ if (!privreq)
+ {
+ /* There is no active packet waiting to receive any data. Then why are
+ * we here?
+ */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPOUTQEMPTY),
+ USB_EPNO(privep->ep.eplog));
+ return -EINVAL;
+ }
+
+ /* bdtout should point to the BDT that just completed */
+
+ bdtout = privep->bdtout;
+ epno = USB_EPNO(privep->ep.eplog);
+
+ ullvdbg("EP%d: len=%d xfrd=%d\n",
+ epno, privreq->req.len, privreq->req.xfrd);
+ bdtdbg("EP%d BDT OUT [%p] {%08x, %08x}\n",
+ epno, bdtout, bdtout->status, bdtout->addr);
+
+ /* We should own the BDT that just completed */
+
+ DEBUGASSERT((bdtout->status & USB_BDT_UOWN) == USB_BDT_COWN);
+
+ /* Get the length of the data received from the BDT. */
+
+ privreq->req.xfrd = (bdtout->status & USB_BDT_BYTECOUNT_MASK) >> USB_BDT_BYTECOUNT_SHIFT;
+
+ /* Complete the transfer and return the request to the class driver. */
+
+ usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd);
+ khci_reqcomplete(privep, OK);
+
+ /* Nullify the BDT entry that just completed. Why? So that we can tell later
+ * that the BDT has been processed. No, it is not sufficient to look at the
+ * UOWN bit. If UOWN==0, then the transfer has been completed BUT it may not
+ * yet have been processed.
+ */
+
+ bdtout->status = 0;
+ bdtout->addr = 0;
+
+ /* Toggle bdtout to the other BDT. Is the current bdtout the EVEN bdt? */
+
+ privep->bdtout = &g_bdt[EP_OUT_EVEN(epno)];
+ if (bdtout == privep->bdtout)
+ {
+ /* Yes.. Then the other BDT is the ODD BDT */
+
+ privep->bdtout++;
+ }
+
+ /* Set up the next read operation */
+
+ return khci_rdrequest(priv, privep);
+}
+
+/****************************************************************************
+ * Name: khci_ep0rdsetup
+ ****************************************************************************/
+
+static int khci_ep0rdsetup(struct khci_usbdev_s *priv, uint8_t *dest,
+ int readlen)
+{
+ volatile struct usbotg_bdtentry_s *bdtout;
+ volatile struct usbotg_bdtentry_s *otherbdt;
+ struct khci_ep_s *privep;
+ uint32_t status;
+
+ /* bdtout refers to the next ping-pong BDT to use. */
+
+ privep = &priv->eplist[EP0];
+ bdtout = privep->bdtout;
+
+ /* Get the other BDT. Check if the current BDT the EVEN BDT? */
+
+ otherbdt = &g_bdt[EP_OUT_EVEN(EP0)];
+ if (bdtout == otherbdt)
+ {
+ /* Yes.. then the other BDT is the ODD BDT. */
+
+ otherbdt++;
+ }
+
+ /* If there is no RX transfer in progress, then the other BDT is setup
+ * to receive the next setup packet. There is a race condition here!
+ * Stop any setup packet.
+ */
+
+ if (!priv->rxbusy)
+ {
+ /* Nullify all BDT OUT entries. Why? So that we can tell later
+ * that the BDT available. No, it is not sufficient to look at the
+ * UOWN bit. If UOWN==0, then the transfer has been completed BUT
+ * it may not yet have been processed. But a completely NULLified
+ * BDT is a sure indication
+ */
+
+ bdtout->status = 0;
+ bdtout->addr = 0;
+ otherbdt->status = 0;
+ otherbdt->addr = 0;
+
+ /* Reset the other BDT to zero... this will cause any attempted use
+ * of the other BDT to be NAKed. Set the first DATA0/1 value to 1.
+ */
+
+ privep->rxdata1 = 1;
+ }
+
+ /* Otherwise, there are RX transfers in progress. bdtout may be
+ * unavailable now. In that case, we are free to setup the other BDT
+ * in order to improve performance. NOTE: That we check if the
+ * entire BDT has been NULLified. That is the only sure indication
+ * that the BDT is available (see above).
+ */
+
+ if (bdtout->status || bdtout->addr)
+ {
+#ifdef CONFIG_USBDEV_NOREADAHEAD
+ /* We will not try to read ahead */
+
+ return -EBUSY;
+#else
+ /* bdtout is not available. Is the other BDT available? */
+
+ if (otherbdt->status || otherbdt->addr)
+ {
+ /* Neither are available... we cannot accept the request now */
+
+ return -EBUSY;
+ }
+
+ /* Use the other BDT */
+
+ bdtout = otherbdt;
+#endif
+ }
+
+ usbtrace(TRACE_READ(EP0), readlen);
+
+ /* Get the correct data toggle (as well as other BDT bits) */
+
+ if (privep->rxdata1)
+ {
+ status = (USB_BDT_UOWN | USB_BDT_DATA1 | USB_BDT_DTS);
+ privep->rxdata1 = 0;
+ }
+ else
+ {
+ status = (USB_BDT_UOWN | USB_BDT_DATA0 | USB_BDT_DTS);
+ privep->rxdata1 = 1;
+ }
+
+ /* Set the data pointer, data length, and enable the endpoint */
+
+ bdtout->addr = (uint8_t *)dest;
+ status |= ((uint32_t)readlen << USB_BDT_BYTECOUNT_SHIFT);
+
+ /* Then give the BDT to the USB */
+
+ bdtdbg("EP0 BDT OUT [%p] {%08x, %08x}\n", bdtout, status, bdtout->addr);
+ bdtout->status = status;
+
+ priv->ctrlstate = CTRLSTATE_RDREQUEST;
+ priv->rxbusy = 1;
+ return OK;
+}
+
+/****************************************************************************
+ * Name: khci_rdsetup
+ ****************************************************************************/
+
+static int khci_rdsetup(struct khci_ep_s *privep, uint8_t *dest, int readlen)
+{
+ volatile struct usbotg_bdtentry_s *bdtout;
+ uint32_t status;
+ int epno;
+
+ /* Select a BDT. Check both the even and the ODD BDT and use the first one
+ * that we own.
+ */
+
+ epno = USB_EPNO(privep->ep.eplog);
+
+ /* bdtout refers to the next ping-pong BDT to use. However, bdtout may be
+ * unavailable now. But, in that case, we are free to setup the other BDT
+ * in order to improve performance.
+ *
+ * Note that we NULLify the BDT OUT entries. This is so that we can tell
+ * that the BDT readlly available. No, it is not sufficient to look at the
+ * UOWN bit. If UOWN==0, then the transfer has been completed BUT it may
+ * not yet have been processed. But a completely NULLified BDT is a sure
+ * indication
+ */
+
+ bdtout = privep->bdtout;
+ if (bdtout->status || bdtout->addr)
+ {
+#ifdef CONFIG_USBDEV_NOREADAHEAD
+ /* We will not try to read-ahead */
+
+ return -EBUSY;
+#else
+ volatile struct usbotg_bdtentry_s *otherbdt;
+
+ /* Is the current BDT the EVEN BDT? */
+
+ otherbdt = &g_bdt[EP_OUT_EVEN(epno)];
+ if (bdtout == otherbdt)
+ {
+ /* Yes.. select the ODD BDT */
+
+ otherbdt++;
+ }
+
+ /* Is the other BDT available? */
+
+ if (otherbdt->status || otherbdt->addr)
+ {
+ /* Neither are available... we cannot accept the request now */
+
+ return -EBUSY;
+ }
+
+ /* Use the other BDT */
+
+ bdtout = otherbdt;
+#endif
+ }
+
+ usbtrace(TRACE_READ(USB_EPNO(privep->ep.eplog)), readlen);
+
+ /* Clear status bits (making sure that UOWN is cleared before doing anything
+ * else).
+ */
+
+ bdtout->status = 0;
+
+ /* Set the data pointer, data length, and enable the endpoint */
+
+ bdtout->addr = (uint8_t *)dest;
+
+ /* Get the correct data toggle. */
+
+ if (privep->rxdata1)
+ {
+ status = (USB_BDT_UOWN | USB_BDT_DATA1 | USB_BDT_DTS);
+ privep->rxdata1 = 0;
+ }
+ else
+ {
+ status = (USB_BDT_UOWN | USB_BDT_DATA0 | USB_BDT_DTS);
+ privep->rxdata1 = 1;
+ }
+
+ /* Set the data length (preserving the data toggle). */
+
+ status |= ((uint32_t)readlen << USB_BDT_BYTECOUNT_SHIFT);
+
+ /* Then give the BDT to the USB */
+
+ bdtdbg("EP%d BDT OUT [%p] {%08x, %08x}\n", epno, bdtout, status, bdtout->addr);
+
+ bdtout->status = status;
+ return OK;
+}
+
+/****************************************************************************
+ * Name: khci_rdrequest
+ ****************************************************************************/
+
+static int khci_rdrequest(struct khci_usbdev_s *priv,
+ struct khci_ep_s *privep)
+{
+ struct khci_req_s *privreq;
+ int readlen;
+ int ret;
+
+ /* Check the request at the head of the endpoint request queue */
+
+ privreq = khci_rqhead(&privep->pend);
+ if (!privreq)
+ {
+ /* There is no packet to receive any data. */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPOUTQEMPTY),
+ USB_EPNO(privep->ep.eplog));
+
+ /* Special case reads from to endpoint zero. If there is no transfer in
+ * progress, then we need to configure to received the next SETUP packet.
+ */
+
+ if (USB_EPNO(privep->ep.eplog) == 0 &&
+ priv->ctrlstate == CTRLSTATE_RDREQUEST)
+ {
+ priv->ctrlstate = CTRLSTATE_WAITSETUP;
+ priv->rxbusy = 0;
+ }
+
+ return OK;
+ }
+
+ ullvdbg("EP%d: len=%d\n", USB_EPNO(privep->ep.eplog), privreq->req.len);
+
+ /* Ignore any attempt to receive a zero length packet */
+
+ if (privreq->req.len == 0)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_EPOUTNULLPACKET), 0);
+ khci_reqcomplete(privep, OK);
+ return OK;
+ }
+
+ /* Limit the size of the transfer to either the buffer size or the max
+ * packet size of the endpoint.
+ */
+
+ readlen = MIN(privreq->req.len, privep->ep.maxpacket);
+
+ /* Handle EP0 in a few special ways */
+
+ if (USB_EPNO(privep->ep.eplog) == EP0)
+ {
+ ret = khci_ep0rdsetup(priv, privreq->req.buf, readlen);
+ }
+ else
+ {
+ ret = khci_rdsetup(privep, privreq->req.buf, readlen);
+ }
+
+ /* If the read request was successfully setup, then move the request from
+ * the head of the pending request queue to the tail of the active request
+ * queue.
+ */
+
+ if (ret == OK)
+ {
+ privreq = khci_remfirst(&privep->pend);
+ DEBUGASSERT(privreq != NULL);
+ khci_addlast(&privep->active, privreq);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: khci_cancelrequests
+ ****************************************************************************/
+
+static void khci_cancelrequests(struct khci_ep_s *privep, int16_t result)
+{
+ struct khci_req_s *privreq;
+
+ while ((privreq = khci_remfirst(&privep->active)))
+ {
+ usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd);
+ khci_reqreturn(privep, privreq, result);
+ }
+
+ while ((privreq = khci_remfirst(&privep->pend)))
+ {
+ usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd);
+ khci_reqreturn(privep, privreq, result);
+ }
+}
+
+/****************************************************************************
+ * Interrupt Level Processing
+ ****************************************************************************/
+/****************************************************************************
+ * Name: khci_dispatchrequest
+ ****************************************************************************/
+
+static void khci_dispatchrequest(struct khci_usbdev_s *priv)
+{
+ int ret;
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_DISPATCH), 0);
+ if (priv && priv->driver)
+ {
+ /* Forward to the control request to the class driver implementation */
+
+ ret = CLASS_SETUP(priv->driver, &priv->usbdev, &priv->ctrl, NULL, 0);
+ if (ret < 0)
+ {
+ /* Stall on failure */
+
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_DISPATCHSTALL), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ }
+}
+
+/****************************************************************************
+ * Name: khci_ep0stall
+ ****************************************************************************/
+
+static void khci_ep0stall(struct khci_usbdev_s *priv)
+{
+ uint32_t regval;
+
+ /* Check if EP0 is stalled */
+
+ regval = khci_getreg(KINETIS_USB0_ENDPT0);
+ if ((regval & USB_ENDPT_EPSTALL) != 0)
+ {
+ /* If so, clear the EP0 stall status */
+
+ regval &= ~USB_ENDPT_EPSTALL;
+ khci_putreg(regval, KINETIS_USB0_ENDPT0);
+ }
+}
+
+/****************************************************************************
+ * Name: khci_eptransfer
+ ****************************************************************************/
+
+static void khci_eptransfer(struct khci_usbdev_s *priv, uint8_t epno,
+ uint16_t ustat)
+{
+ struct khci_ep_s *privep;
+ int ret;
+
+ /* Decode and service non control endpoints interrupt */
+
+ privep = &priv->eplist[epno];
+
+ /* Check if the last transaction was an EP0 OUT transaction */
+
+ if ((ustat & USB_STAT_TX) == USB_STAT_TX_OUT)
+ {
+ /* OUT: host-to-device */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPOUTDONE), ustat);
+
+ /* Handle read requests. Call khci_rdcomplete() to complete the OUT
+ * transfer and setup the next out transfer.
+ */
+
+ ret = khci_rdcomplete(priv, privep);
+#ifdef CONFIG_USBDEV_NOREADAHEAD
+ if (ret == OK)
+ {
+ /* If that succeeds, then try to set up another OUT transfer. */
+
+ (void)khci_rdrequest(priv, privep);
+ }
+#else
+ UNUSED(ret);
+#endif
+ }
+ else
+ {
+ /* IN: device-to-host */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPINDONE), ustat);
+
+ /* An outgoing IN packet has completed. Update the number of bytes transferred
+ * and check for completion of the transfer.
+ */
+
+ khci_wrcomplete(priv, privep);
+
+ /* Handle additional queued write requests */
+
+ (void)khci_wrrequest(priv, privep);
+ }
+}
+
+/****************************************************************************
+ * Name: khci_ep0nextsetup
+ *
+ * Description:
+ * This function is called (1) after sucessful completion of an EP0 Setup
+ * command, or (2) after receipt of the OUT complete event (for simple
+ * transfers). It simply sets up the single BDT to accept the next
+ * SETUP commend.
+ *
+ ****************************************************************************/
+
+static void khci_ep0nextsetup(struct khci_usbdev_s *priv)
+{
+ volatile struct usbotg_bdtentry_s *bdt = priv->eplist[EP0].bdtout;
+ uint32_t bytecount;
+
+ /* This operation should be performed no more than once per OUT transaction.
+ * priv->ep0done is set to zero at the beginning of processing of each EP0
+ * transfer. It is set the first time that this function runs after the EP0
+ * transfer.
+ */
+
+ if (!priv->ep0done)
+ {
+ bytecount = (USB_SIZEOF_CTRLREQ << USB_BDT_BYTECOUNT_SHIFT);
+ bdt->addr = (uint8_t *)&priv->ctrl;
+ bdt->status = (USB_BDT_UOWN | bytecount);
+ priv->ep0done = 1;
+ }
+}
+
+/****************************************************************************
+ * Name: khci_ep0rdcomplete
+ *
+ * Description:
+ * This function is called after a sequence of read sequence. In this
+ * context, only one BDT is used. Both BDTs must be prepared to receive
+ * SETUP packets.
+ *
+ ****************************************************************************/
+
+static void khci_ep0rdcomplete(struct khci_usbdev_s *priv)
+{
+ volatile struct usbotg_bdtentry_s *bdt;
+ struct khci_ep_s *ep0;
+ uint32_t physaddr;
+ uint32_t bytecount;
+
+ /* This operation should be performed no more than once per OUT transaction.
+ * priv->ep0done is set to zero at the beginning of processing of each EP0
+ * transfer. It is set the first time that this function runs after the EP0
+ * transfer.
+ */
+
+ if (!priv->ep0done)
+ {
+ bytecount = (USB_SIZEOF_CTRLREQ << USB_BDT_BYTECOUNT_SHIFT);
+ physaddr = &priv->ctrl;
+
+ bdt = &g_bdt[EP0_OUT_EVEN];
+ bdt->addr = (uint8_t *)physaddr;
+ bdt->status = (USB_BDT_UOWN | bytecount);
+
+ bdt = &g_bdt[EP0_OUT_ODD];
+ bdt->addr = (uint8_t *)physaddr;
+ bdt->status = (USB_BDT_UOWN | bytecount);
+
+ priv->ep0done = 1;
+
+ /* Data toggling is not used on SETUP transfers. And IN transfer
+ * resulting from a SETUP command should begin with DATA1.
+ */
+
+ ep0 = &priv->eplist[EP0];
+ ep0->rxdata1 = 0;
+ ep0->txdata1 = 1;
+ }
+}
+
+/****************************************************************************
+ * Name: khci_ep0setup
+ ****************************************************************************/
+
+static void khci_ep0setup(struct khci_usbdev_s *priv)
+{
+ volatile struct usbotg_bdtentry_s *bdt;
+ struct khci_ep_s *ep0;
+ struct khci_ep_s *privep;
+ union wb_u value;
+ union wb_u index;
+ union wb_u len;
+ union wb_u response;
+ uint32_t regval;
+ bool dispatched = false;
+ uint8_t epno;
+ int nbytes = 0; /* Assume zero-length packet */
+ int ret;
+
+ /* Cancel any pending requests. */
+
+ ep0 = &priv->eplist[EP0];
+ khci_cancelrequests(ep0, -EPROTO);
+
+ /* Assume NOT stalled; no TX in progress; no RX overrun. Data 0/1 toggling
+ * is not used on SETUP packets, but any following EP0 IN transfer should
+ * beginning with DATA1.
+ */
+
+ ep0->stalled = false;
+ ep0->rxdata1 = 0;
+ ep0->txdata1 = 1;
+
+ /* Initialize for the SETUP */
+
+ priv->ctrlstate = CTRLSTATE_WAITSETUP;
+
+ /* And extract the little-endian 16-bit values to host order */
+
+ value.w = GETUINT16(priv->ctrl.value);
+ index.w = GETUINT16(priv->ctrl.index);
+ len.w = GETUINT16(priv->ctrl.len);
+
+ ullvdbg("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
+
+ /* Dispatch any non-standard requests */
+
+ if ((priv->ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_NOSTDREQ), priv->ctrl.type);
+
+ /* Let the class implementation handle all non-standar requests */
+
+ khci_dispatchrequest(priv);
+ dispatched = true;
+ goto resume_packet_processing; /* Sorry about the goto */
+ }
+
+ /* Handle standard request. Pick off the things of interest to the
+ * USB device controller driver; pass what is left to the class driver
+ */
+
+ switch (priv->ctrl.req)
+ {
+ case USB_REQ_GETSTATUS:
+ {
+ /* type: device-to-host; recipient = device, interface, endpoint
+ * value: 0
+ * index: zero interface endpoint
+ * len: 2; data = status
+ */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETSTATUS), priv->ctrl.type);
+ if (len.w != 2 || (priv->ctrl.type & USB_REQ_DIR_IN) == 0 ||
+ index.b[MSB] != 0 || value.w != 0)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADEPGETSTATUS), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ else
+ {
+ switch (priv->ctrl.type & USB_REQ_RECIPIENT_MASK)
+ {
+ case USB_REQ_RECIPIENT_ENDPOINT:
+ {
+ epno = USB_EPNO(index.b[LSB]);
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPGETSTATUS), epno);
+ if (epno >= KHCI_NENDPOINTS)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADEPGETSTATUS), epno);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ else
+ {
+ privep = &priv->eplist[epno];
+ response.w = 0; /* Not stalled */
+ nbytes = 2; /* Response size: 2 bytes */
+
+ if (USB_ISEPIN(index.b[LSB]))
+ {
+ /* IN endpoint */
+
+ bdt = privep->bdtin;
+ }
+ else
+ {
+ /* OUT endpoint */
+
+ bdt = privep->bdtout;
+ }
+
+ /* BSTALL set if stalled */
+
+ if ((bdt->status & USB_BDT_BSTALL) != 0)
+ {
+ response.b[LSB] = 1; /* Stalled, set bit 0 */
+ }
+ }
+ }
+ break;
+
+ case USB_REQ_RECIPIENT_DEVICE:
+ {
+ if (index.w == 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_DEVGETSTATUS), 0);
+
+ /* Features: Remote Wakeup=YES; selfpowered=? */
+
+ response.w = 0;
+ response.b[LSB] = (priv->selfpowered << USB_FEATURE_SELFPOWERED) |
+ (priv->rwakeup << USB_FEATURE_REMOTEWAKEUP);
+ nbytes = 2; /* Response size: 2 bytes */
+ }
+ else
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADDEVGETSTATUS), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ }
+ break;
+
+ case USB_REQ_RECIPIENT_INTERFACE:
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_IFGETSTATUS), 0);
+ response.w = 0;
+ nbytes = 2; /* Response size: 2 bytes */
+ }
+ break;
+
+ default:
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADGETSTATUS), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ break;
+ }
+ }
+ }
+ break;
+
+ case USB_REQ_CLEARFEATURE:
+ {
+ /* type: host-to-device; recipient = device, interface or endpoint
+ * value: feature selector
+ * index: zero interface endpoint;
+ * len: zero, data = none
+ */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_CLEARFEATURE), priv->ctrl.type);
+ if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE)
+ {
+ /* Disable B device from performing HNP */
+
+#ifdef CONFIG_USBOTG
+ if (value.w == USBOTG_FEATURE_B_HNP_ENABLE)
+ {
+ /* Disable HNP */
+#warning Missing Logic
+ }
+
+ /* Disable A device HNP support */
+
+ else if (value.w == USBOTG_FEATURE_A_HNP_SUPPORT)
+ {
+ /* Disable HNP support */
+#warning Missing Logic
+ }
+
+ /* Disable alternate HNP support */
+
+ else if (value.w == USBOTG_FEATURE_A_ALT_HNP_SUPPORT)
+ {
+ /* Disable alternate HNP */
+#warning Missing Logic
+ }
+ else
+#endif
+ /* Disable remote wakeup */
+
+ if (value.w == USB_FEATURE_REMOTEWAKEUP)
+ {
+ priv->rwakeup = 0;
+ }
+ else
+ {
+ /* Let the class implementation handle all other device features */
+
+ khci_dispatchrequest(priv);
+ dispatched = true;
+ }
+ }
+ else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_ENDPOINT)
+ {
+ epno = USB_EPNO(index.b[LSB]);
+ if (epno > 0 && epno < KHCI_NENDPOINTS && index.b[MSB] == 0 &&
+ value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0)
+ {
+ privep = &priv->eplist[epno];
+ privep->halted = false;
+ ret = khci_epstall(&privep->ep, true);
+ UNUSED(ret);
+ }
+ else
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADCLEARFEATURE), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ }
+ else
+ {
+ /* Let the class implementation handle all other recipients. */
+
+ khci_dispatchrequest(priv);
+ dispatched = true;
+ }
+ }
+ break;
+
+ case USB_REQ_SETFEATURE:
+ {
+ /* type: host-to-device; recipient = device, interface, endpoint
+ * value: feature selector
+ * index: zero interface endpoint;
+ * len: 0; data = none
+ */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SETFEATURE), priv->ctrl.type);
+
+ if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE)
+ {
+ /* Enable B device to perform HNP */
+
+#ifdef CONFIG_USBOTG
+ if (value.w == USBOTG_FEATURE_B_HNP_ENABLE)
+ {
+ /* Enable HNP */
+#warning "Missing logic"
+ }
+
+ /* Enable A device HNP supports */
+
+ else if (value.w == USBOTG_FEATURE_A_HNP_SUPPORT)
+ {
+ /* Enable HNP support */
+#warning "Missing logic"
+ }
+
+ /* Another port on the A device supports HNP */
+
+ else if (value.w == USBOTG_FEATURE_A_ALT_HNP_SUPPORT)
+ {
+ /* Enable alternate HNP */
+#warning "Missing logic"
+ }
+ else
+#endif
+
+ if (value.w == USB_FEATURE_REMOTEWAKEUP)
+ {
+ priv->rwakeup = 0;
+ }
+ else if (value.w == USB_FEATURE_TESTMODE)
+ {
+ /* Special case recipient=device test mode */
+
+ ullvdbg("test mode: %d\n", index.w);
+ }
+ else
+ {
+ /* Let the class implementation handle all other device features */
+
+ khci_dispatchrequest(priv);
+ dispatched = true;
+ }
+ }
+ else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_ENDPOINT)
+ {
+ /* Handler recipient=endpoint */
+
+ epno = USB_EPNO(index.b[LSB]);
+ if (epno < KHCI_NENDPOINTS && index.b[MSB] == 0 &&
+ value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0)
+ {
+ privep = &priv->eplist[epno];
+ privep->halted = true;
+ ret = khci_epstall(&privep->ep, false);
+ UNUSED(ret);
+ }
+ else
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADSETFEATURE), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ }
+ else
+ {
+ /* The class driver handles all recipients except recipient=endpoint */
+
+ khci_dispatchrequest(priv);
+ dispatched = true;
+ }
+ }
+ break;
+
+ case USB_REQ_SETADDRESS:
+ {
+ /* type: host-to-device; recipient = device
+ * value: device address
+ * index: 0
+ * len: 0; data = none
+ */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0SETUPSETADDRESS), value.w);
+ if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_DEVICE ||
+ index.w != 0 || len.w != 0 || value.w > 127)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADSETADDRESS), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ else
+ {
+ /* Note that setting of the device address will be deferred. A zero-length
+ * packet will be sent and the device address will be set when the zero-
+ * length packet transfer completes.
+ */
+
+ priv->devstate = DEVSTATE_ADDRPENDING;
+ }
+ }
+ break;
+
+ case USB_REQ_GETDESCRIPTOR:
+ /* type: device-to-host; recipient = device
+ * value: descriptor type and index
+ * index: 0 or language ID;
+ * len: descriptor len; data = descriptor
+ */
+ case USB_REQ_SETDESCRIPTOR:
+ /* type: host-to-device; recipient = device
+ * value: descriptor type and index
+ * index: 0 or language ID;
+ * len: descriptor len; data = descriptor
+ */
+
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETSETDESC), priv->ctrl.type);
+ if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE)
+ {
+ /* The request seems valid... let the class implementation handle it */
+
+ khci_dispatchrequest(priv);
+ dispatched = true;
+ }
+ else
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADGETSETDESC), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ }
+ break;
+
+ case USB_REQ_GETCONFIGURATION:
+ /* type: device-to-host; recipient = device
+ * value: 0;
+ * index: 0;
+ * len: 1; data = configuration value
+ */
+
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETCONFIG), priv->ctrl.type);
+ if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE &&
+ value.w == 0 && index.w == 0 && len.w == 1)
+ {
+ /* The request seems valid... let the class implementation handle it */
+
+ khci_dispatchrequest(priv);
+ dispatched = true;
+ }
+ else
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADGETCONFIG), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ }
+ break;
+
+ case USB_REQ_SETCONFIGURATION:
+ /* type: host-to-device; recipient = device
+ * value: configuration value
+ * index: 0;
+ * len: 0; data = none
+ */
+
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SETCONFIG), priv->ctrl.type);
+ if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE &&
+ index.w == 0 && len.w == 0)
+ {
+ /* The request seems valid... let the class implementation handle it */
+
+ khci_dispatchrequest(priv);
+ dispatched = true;
+ }
+ else
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADSETCONFIG), 0);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ }
+ break;
+
+ case USB_REQ_GETINTERFACE:
+ /* type: device-to-host; recipient = interface
+ * value: 0
+ * index: interface;
+ * len: 1; data = alt interface
+ */
+ case USB_REQ_SETINTERFACE:
+ /* type: host-to-device; recipient = interface
+ * value: alternate setting
+ * index: interface;
+ * len: 0; data = none
+ */
+
+ {
+ /* Let the class implementation handle the request */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETSETIF), priv->ctrl.type);
+ khci_dispatchrequest(priv);
+ dispatched = true;
+ }
+ break;
+
+ case USB_REQ_SYNCHFRAME:
+ /* type: device-to-host; recipient = endpoint
+ * value: 0
+ * index: endpoint;
+ * len: 2; data = frame number
+ */
+
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SYNCHFRAME), 0);
+ }
+ break;
+
+ default:
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDCTRLREQ), priv->ctrl.req);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ break;
+ }
+
+ /* PKTDIS bit is set when a Setup Transaction is received. Clear to resume
+ * packet processing.
+ */
+
+resume_packet_processing:
+ regval = khci_getreg(KINETIS_USB0_CTL);
+ regval &= ~USB_CTL_TXSUSPENDTOKENBUSY;
+ khci_putreg(regval, KINETIS_USB0_CTL);
+
+ /* At this point, the request has been handled and there are three possible
+ * outcomes:
+ *
+ * 1. The setup request was successfully handled above and a response packet
+ * must be sent (may be a zero length packet).
+ * 2. The request was successfully handled by the class implementation. In
+ * case, the EP0 IN response has already been queued and the local variable
+ * 'dispatched' will be set to true and ctrlstate != CTRLSTATE_STALL;
+ * 3. An error was detected in either the above logic or by the class implementation
+ * logic. In either case, priv->state will be set CTRLSTATE_STALL
+ * to indicate this case.
+ *
+ * NOTE: Non-standard requests are a special case. They are handled by the
+ * class implementation and this function returned early above, skipping this
+ * logic altogether.
+ */
+
+ if (!dispatched && (priv->ctrlstate != CTRLSTATE_STALL))
+ {
+ /* The SETUP command was not dispatched to the class driver and the SETUP
+ * command did not cause a stall. We will respond. First, restrict the
+ * data length to the length requested in the setup packet
+ */
+
+ if (nbytes > len.w)
+ {
+ nbytes = len.w;
+ }
+
+ /* Send the EP0 SETUP response (might be a zero-length packet) */
+
+ khci_epwrite(ep0, ep0->bdtin, response.b, nbytes);
+ priv->ctrlstate = CTRLSTATE_WAITSETUP;
+ }
+
+ /* Did we stall? This might have occurred from the above logic OR the stall
+ * condition may have been set less obviously in khci_dispatchrequest().
+ * In either case, we handle the stall condition the same.
+ *
+ * However, bad things happen if we try to stall a SETUP packet. So lets
+ * not. If we wait a bit, things will recover. Hmmm.. If we completed
+ * the data phase (perhaps by sending a NULL packet), then I think we
+ * could stall the endpoint and perhaps speed things up a bit???.
+ */
+
+ /* Set up the BDT to accept the next setup commend. */
+
+ khci_ep0nextsetup(priv);
+ priv->ctrlstate = CTRLSTATE_WAITSETUP;
+}
+
+/****************************************************************************
+ * Name: khci_ep0incomplete
+ ****************************************************************************/
+
+static void khci_ep0incomplete(struct khci_usbdev_s *priv)
+{
+ struct khci_ep_s *ep0 = &priv->eplist[EP0];
+ volatile struct usbotg_bdtentry_s *bdtlast;
+ int ret;
+
+ /* Get the last BDT and make sure that we own it. */
+
+ bdtlast = ep0->bdtin;
+
+ /* Make sure that we own the last BDT. */
+
+ bdtlast->status = 0;
+ bdtlast->addr = 0;
+
+ /* Are we processing the completion of one packet of an outgoing request
+ * from the class driver?
+ */
+
+ if (priv->ctrlstate == CTRLSTATE_WRREQUEST)
+ {
+ /* An outgoing EP0 transfer has completed. Update the byte count and
+ * check for the completion of the transfer.
+ *
+ * NOTE: khci_wrcomplete() will toggle bdtin to the other buffer so
+ * we do not need to that for this case.
+ */
+
+ khci_wrcomplete(priv, &priv->eplist[EP0]);
+
+ /* Handle the next queue IN transfer. If there are no further queued
+ * IN transfers, khci_wrrequest will return -ENODATA and that is the
+ * only expected error return value in this context.
+ */
+
+ ret = khci_wrrequest(priv, &priv->eplist[EP0]);
+ if (ret < 0)
+ {
+ DEBUGASSERT(ret == -ENODATA);
+
+ /* If there is nothing to be sent, then we need to configure to
+ * receive the next SETUP packet.
+ */
+
+ priv->ctrlstate = CTRLSTATE_WAITSETUP;
+ }
+ }
+
+ /* No.. Are we processing the completion of a status response? */
+
+ else if (priv->ctrlstate == CTRLSTATE_WAITSETUP)
+ {
+ /* Get the next IN BDT */
+
+ if (bdtlast == &g_bdt[EP0_IN_EVEN])
+ {
+ ep0->bdtin = &g_bdt[EP0_IN_ODD];
+ }
+ else
+ {
+ DEBUGASSERT(bdtlast == &g_bdt[EP0_IN_ODD]);
+ ep0->bdtin = &g_bdt[EP0_IN_EVEN];
+ }
+
+ /* Look at the saved SETUP command. Was it a SET ADDRESS request?
+ * If so, then now is the time to set the address.
+ */
+
+ if (priv->devstate == DEVSTATE_ADDRPENDING)
+ {
+ uint16_t addr = GETUINT16(priv->ctrl.value);
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0ADDRESSSET), addr);
+
+ /* This should be the equivalent state */
+
+ DEBUGASSERT(priv->ctrl.req == USB_REQ_SETADDRESS &&
+ (priv->ctrl.type & REQRECIPIENT_MASK) ==
+ (USB_REQ_TYPE_STANDARD | USB_REQ_RECIPIENT_DEVICE));
+
+ /* Set (or clear) the address */
+
+ khci_putreg(addr, KINETIS_USB0_ADDR);
+ if (addr > 0)
+ {
+ priv->devstate = DEVSTATE_ADDRESS;
+ }
+ else
+ {
+ priv->devstate = DEVSTATE_DEFAULT;
+ }
+ }
+ }
+
+ /* No other state is expected in this context */
+
+ else
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDSTATE), priv->ctrlstate);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+}
+
+/****************************************************************************
+ * Name: khci_ep0outcomplete
+ ****************************************************************************/
+
+static void khci_ep0outcomplete(struct khci_usbdev_s *priv)
+{
+ struct khci_ep_s *ep0 = &priv->eplist[EP0];
+
+ switch (priv->ctrlstate)
+ {
+ /* Read request in progress */
+
+ case CTRLSTATE_RDREQUEST:
+
+ /* Process the next read request for EP0 */
+
+ khci_rdcomplete(priv, ep0);
+
+ /* Was this the end of the OUT transfer? */
+
+ if (priv->ctrlstate == CTRLSTATE_WAITSETUP)
+ {
+ /* Prepare EP0 OUT for the next SETUP transaction. */
+
+ khci_ep0rdcomplete(priv);
+ }
+ break;
+
+ /* No transfer in progress, waiting for SETUP */
+
+ case CTRLSTATE_WAITSETUP:
+ {
+ /* In this case the last OUT transaction must have been a status
+ * stage of a CTRLSTATE_WRREQUEST: Prepare EP0 OUT for the next SETUP
+ * transaction.
+ */
+
+ khci_ep0nextsetup(priv);
+ }
+ break;
+
+ /* Unexpected state OR host aborted the OUT transfer before it completed,
+ * STALL the endpoint in either case
+ */
+
+ default:
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDSTATE), priv->ctrlstate);
+ priv->ctrlstate = CTRLSTATE_STALL;
+ }
+ break;
+ }
+}
+
+/****************************************************************************
+ * Name: khci_ep0transfer
+ ****************************************************************************/
+
+static void khci_ep0transfer(struct khci_usbdev_s *priv, uint16_t ustat)
+{
+ volatile struct usbotg_bdtentry_s *bdt;
+
+ /* The following information is available in the status register :
+ *
+ * ENDPT - The 4 bit endpoint number that cause the interrupt.
+ * DIR - The direction of the endpoint.
+ * PPBI - The ping-pong buffer used in the transaction.
+ */
+
+ priv->ep0done = 0;
+
+ /* Check if the last transaction was an EP0 OUT transaction */
+
+ if ((ustat & USB_STAT_TX) == USB_STAT_TX_OUT)
+ {
+ int index;
+
+ /* It was an EP0 OUT transaction. Get the index to the BDT. */
+
+ index = ((ustat & USB_STAT_ODD) == 0 ? EP0_OUT_EVEN : EP0_OUT_ODD);
+ bdt = &g_bdt[index];
+ priv->eplist[0].bdtout = bdt;
+
+ bdtdbg("EP0 BDT OUT [%p] {%08x, %08x}\n", bdt, bdt->status, bdt->addr);
+
+ /* Check the current EP0 OUT buffer contains a SETUP packet */
+
+ if (((bdt->status & USB_BDT_PID_MASK) >> USB_BDT_PID_SHIFT) == USB_PID_SETUP_TOKEN)
+ {
+ /* Check if the SETUP transaction data went into the priv->ctrl
+ * buffer. If not, then we will need to copy it.
+ */
+
+ if (bdt->addr != (uint8_t *)&priv->ctrl)
+ {
+ void *src = (void *)bdt->addr;
+ void *dest = &priv->ctrl;
+
+ memcpy(dest, src, USB_SIZEOF_CTRLREQ);
+ bdt->addr = (uint8_t *)&priv->ctrl;
+ }
+
+ /* Handle the control OUT transfer */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0SETUPDONE), bdt->status);
+ khci_ep0setup(priv);
+ }
+ else
+ {
+ /* Handle the data OUT transfer */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0OUTDONE), ustat);
+ khci_ep0outcomplete(priv);
+ }
+ }
+
+ /* No.. it was an EP0 IN transfer */
+
+ else /* if ((status & USB_STAT_TX) == USB_STAT_TX_IN) */
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0INDONE), ustat);
+
+ /* Handle the IN transfer complete */
+
+ khci_ep0incomplete(priv);
+ }
+
+ /* Check for a request to stall EP0 */
+
+ if (priv->ctrlstate == CTRLSTATE_STALL)
+ {
+ /* Stall EP0 */
+
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_EP0SETUPSTALLED), priv->ctrlstate);
+ (void)khci_epstall(&priv->eplist[EP0].ep, false);
+ }
+}
+
+/****************************************************************************
+ * Name: khci_interrupt
+ ****************************************************************************/
+
+static int khci_interrupt(int irq, void *context)
+{
+ /* For now there is only one USB controller, but we will always refer to
+ * it using a pointer to make any future ports to multiple USB controllers
+ * easier.
+ */
+
+ struct khci_usbdev_s *priv = &g_usbdev;
+ uint16_t usbir;
+ uint16_t otgir;
+ uint32_t regval;
+ int i;
+
+ /* Get the set of pending USB and OTG interrupts interrupts */
+
+ usbir = khci_getreg(KINETIS_USB0_ISTAT) & khci_getreg(KINETIS_USB0_INTEN);
+ otgir = khci_getreg(KINETIS_USB0_OTGISTAT) & khci_getreg(KINETIS_USB0_OTGICR);
+// ulldbg("Interrupt: ISTAT %04x\n", khci_getreg(KINETIS_USB0_ISTAT));
+// ulldbg("Interrupt: OTGISTAT %04x\n", khci_getreg(KINETIS_USB0_OTGISTAT));
+// ulldbg("Interrupt: ERRSTAT %04x\n", khci_getreg(KINETIS_USB0_ERRSTAT));
+ usbtrace(TRACE_INTENTRY(KHCI_TRACEINTID_INTERRUPT), usbir | otgir);
+
+#ifdef CONFIG_USBOTG
+ /* Session Request Protocol (SRP) Time Out Check */
+
+ /* if USB OTG SRP is ready */
+# warning "Missing logic"
+ {
+ /* Check if the 1 millisecond timer has expired */
+
+ if ((otgir & USBOTG_INT_T1MSEC) != 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_T1MSEC), otgir);
+
+ /* Check for the USB OTG SRP timeout */
+# warning "Missing logic"
+ {
+ /* Handle OTG events of the SRP timeout has expired */
+# warning "Missing logic"
+ }
+
+ /* Clear Interrupt 1 msec timer Flag */
+
+ khci_putreg(USBOTG_INT_T1MSEC, KINETIS_USB0_ISTAT);
+ }
+ }
+#endif
+
+ /* Handle events while we are in the attached state */
+
+ if (priv->devstate == DEVSTATE_ATTACHED)
+ {
+ /* Clear all USB interrupts */
+
+ khci_putreg(USB_INT_ALL, KINETIS_USB0_ISTAT);
+
+ /* Make sure that the USE reset and IDLE detect interrupts are enabled */
+
+ regval = khci_getreg(KINETIS_USB0_INTEN);
+ regval |= (USB_INT_USBRST | USB_INT_SLEEP);
+ khci_putreg(regval, KINETIS_USB0_INTEN);
+
+ /* Now were are in the powered state */
+
+ priv->devstate = DEVSTATE_POWERED;
+ }
+
+#ifdef CONFIG_USBOTG
+ /* Check if the ID Pin Changed State */
+
+ if ((otgir & USBOTG_INT_ID) != 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_OTGID), otgir);
+
+ /* Re-detect and re-initialize */
+#warning "Missing logic"
+
+ khci_putreg(USBOTG_INT_ID, KINETIS_USB0_ISTAT);
+ }
+#endif
+#if 0
+ /* Service the USB Activity Interrupt */
+
+ if ((otgir & USBOTG_INT_ACTV) != 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_WKUP), otgir);
+
+ /* Wake-up from susepnd mode */
+
+ khci_putreg(USBOTG_INT_ACTV, KINETIS_USB0_ISTAT);
+ khci_resume(priv);
+ }
+
+ /* It is pointless to continue servicing if the device is in suspend mode. */
+x
+ if ((khci_getreg(KINETIS_USB0_CTL) & USB_USBCTRL_SUSP) != 0)
+ {
+ /* Just clear the interrupt and return */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SUSPENDED), khci_getreg(KINETIS_USB0_CTL));
+ goto interrupt_exit;
+ }
+#endif
+
+ /* Service USB Bus Reset Interrupt. When bus reset is received during
+ * suspend, ACTVIF will be set first, once the UCONbits.SUSPND is clear,
+ * then the URSTIF bit will be asserted. This is why URSTIF is checked
+ * after ACTVIF. The USB reset flag is masked when the USB state is in
+ * DEVSTATE_DETACHED or DEVSTATE_ATTACHED, and therefore cannot cause a
+ * USB reset event during these two states.
+ */
+
+ if ((usbir & USB_INT_USBRST) != 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_RESET), usbir);
+
+ /* Reset interrupt received. Restore our initial state. NOTE: the
+ * hardware automatically resets the USB address, so we really just
+ * need reset any existing configuration/transfer states.
+ */
+ khci_reset(priv);
+ priv->devstate = DEVSTATE_DEFAULT;
+
+#ifdef CONFIG_USBOTG
+ /* Disable and deactivate HNP */
+#warning Missing Logic
+#endif
+ /* Acknowlege the reset interrupt */
+
+ khci_putreg(USB_INT_USBRST, KINETIS_USB0_ISTAT);
+ goto interrupt_exit;
+ }
+
+ /* Service IDLE interrupts */
+
+ if ((usbir & USB_INT_SLEEP) != 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_IDLE), usbir);
+
+#ifdef CONFIG_USBOTG
+ /* If Suspended, Try to switch to Host */
+#warning "Missing logic"
+#else
+ khci_suspend(priv);
+
+#endif
+ khci_putreg(USB_INT_SLEEP, KINETIS_USB0_ISTAT);
+ }
+
+ /* Service SOF interrupts */
+
+#ifdef CONFIG_USB_SOFINTS
+ if ((usbir & USB_INT_SOFTOK) != 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SOF), 0);
+
+ /* I am not sure why you would ever enable SOF interrupts */
+
+ khci_putreg(USB_INT_SOFTOK, KINETIS_USB0_ISTAT);
+ }
+#endif
+
+ /* Service stall interrupts */
+
+ if ((usbir & USB_INT_STALL) != 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_STALL), usbir);
+
+ khci_ep0stall(priv);
+
+ /* Clear the pending STALL interrupt */
+
+ khci_putreg(USB_INT_STALL, KINETIS_USB0_ISTAT);
+ }
+
+ /* Service error interrupts */
+
+ if ((usbir & USB_INT_ERROR) != 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_UERR), usbir);
+ ulldbg("Error: EIR=%04x\n", khci_getreg(KINETIS_USB0_ERRSTAT));
+
+ /* Clear all pending USB error interrupts */
+
+ khci_putreg(USB_EINT_ALL, KINETIS_USB0_ERRSTAT);
+ }
+
+ /* There is no point in continuing if the host has not sent a bus reset.
+ * Once bus reset is received, the device transitions into the DEFAULT
+ * state and is ready for communication.
+ */
+
+#if 0
+ if (priv->devstate < DEVSTATE_DEFAULT)
+ {
+ /* Just clear the interrupt and return */
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_WAITRESET), priv->devstate);
+ goto interrupt_exit;
+ }
+#endif
+
+ /* Service USB Transaction Complete Interrupt */
+
+ if ((usbir & USB_INT_TOKDNE) != 0)
+ {
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_TRNC), usbir);
+
+ /* Drain the USAT FIFO entries. If the USB FIFO ever gets full, USB
+ * bandwidth utilization can be compromised, and the device won't be
+ * able to receive SETUP packets.
+ */
+
+ for (i = 0; i < 4; i++)
+ {
+ uint8_t epno;
+
+ /* Check the pending interrupt register. Is token processing complete. */
+
+ if ((khci_getreg(KINETIS_USB0_ISTAT) & USB_INT_TOKDNE) != 0)
+ {
+ regval = khci_getreg(KINETIS_USB0_STAT);
+ khci_putreg(USB_INT_TOKDNE, KINETIS_USB0_ISTAT);
+
+ usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_TRNCS), regval);
+
+ /* Handle the endpoint transfer complete event. */
+
+ epno = (regval & USB_STAT_ENDP_MASK) >> USB_STAT_ENDP_SHIFT;
+ if (epno == 0)
+ {
+ khci_ep0transfer(priv, regval);
+ }
+ else
+ {
+ khci_eptransfer(priv, epno, regval);
+ }
+ }
+ else
+ {
+ /* USTAT FIFO must be empty. */
+
+ break;
+ }
+ }
+ }
+
+ /* Clear the pending USB interrupt. Goto is used in the above to assure
+ * that all interrupt exists pass through this logic.
+ */
+
+interrupt_exit:
+ //up_clrpend_irq(KINETIS_IRQ_USBOTG);
+ kinetis_clrpend(KINETIS_IRQ_USBOTG);
+ usbtrace(TRACE_INTEXIT(KHCI_TRACEINTID_INTERRUPT), usbir | otgir);
+ return OK;
+}
+
+/****************************************************************************
+ * Suspend/Resume Helpers
+ ****************************************************************************/
+/****************************************************************************
+ * Name: khci_suspend
+ ****************************************************************************/
+
+static void khci_suspend(struct khci_usbdev_s *priv)
+{
+ uint32_t regval;
+
+ /* Notify the class driver of the suspend event */
+
+ if (priv->driver)
+ {
+ CLASS_SUSPEND(priv->driver, &priv->usbdev);
+ }
+
+ /* Enable the ACTV interrupt.
+ *
+ * NOTE: Do not clear UIRbits.ACTVIF here! Reason: ACTVIF is only
+ * generated once an IDLEIF has been generated. This is a 1:1 ratio
+ * interrupt generation. For every IDLEIF, there will be only one ACTVIF
+ * regardless of the number of subsequent bus transitions. If the ACTIF
+ * is cleared here, a problem could occur. The driver services IDLEIF
+ * first because ACTIVIE=0. If this routine clears the only ACTIVIF,
+ * then it can never get out of the suspend mode.
+ */
+#if 0
+ regval = khci_getreg(KINETIS_USB0_OTGICR);
+ regval |= USBOTG_INT_ACTV;
+ khci_putreg(regval, KINETIS_USB0_OTGICR);
+
+ /* Disable further IDLE interrupts. Once is enough. */
+
+ regval = khci_getreg(KINETIS_USB0_INTEN);
+ regval &= ~USB_INT_SLEEP;
+ khci_putreg(regval, KINETIS_USB0_INTEN);
+#endif
+
+ /* Invoke a callback into board-specific logic. The board-specific logic
+ * may enter into sleep or idle modes or switch to a slower clock, etc.
+ */
+
+ kinetis_usbsuspend((struct usbdev_s *)priv, false);
+}
+
+/****************************************************************************
+ * Name: khci_resume
+ ****************************************************************************/
+
+static void khci_resume(struct khci_usbdev_s *priv)
+{
+ irqstate_t flags;
+ uint32_t regval;
+
+ flags = enter_critical_section();
+
+ /* Start RESUME signaling */
+
+ regval = khci_getreg(KINETIS_USB0_CTL);
+ regval |= USB_CTL_RESUME;
+ khci_putreg(regval, KINETIS_USB0_CTL);
+
+ /* Keep the RESUME line set for 1-13 ms */
+
+ up_mdelay(10);
+
+ regval &= ~USB_CTL_RESUME;
+ khci_putreg(regval, KINETIS_USB0_CTL);
+
+ /* This function is called when the USB activity interrupt occurs.
+ * If using clock switching, this is the place to call out to
+ * logic to restore the original MCU core clock frequency.
+ */
+
+ kinetis_usbsuspend((struct usbdev_s *)priv, true);
+
+ /* Disable further activity interrupts */
+#if 0
+ regval = khci_getreg(KINETIS_USB0_OTGICR);
+ regval &= ~USBOTG_INT_ACTV;
+ khci_putreg(regval, KINETIS_USB0_OTGICR);
+#endif
+
+ /* The ACTVIF bit cannot be cleared immediately after the USB module wakes
+ * up from Suspend or while the USB module is suspended. A few clock cycles
+ * are required to synchronize the internal hardware state machine before
+ * the ACTIVIF bit can be cleared by firmware. Clearing the ACTVIF bit
+ * before the internal hardware is synchronized may not have an effect on
+ * the value of ACTVIF. Additionally, if the USB module uses the clock from
+ * the 96 MHz PLL source, then after clearing the SUSPND bit, the USB
+ * module may not be immediately operational while waiting for the 96 MHz
+ * PLL to lock.
+ */
+
+ khci_putreg(USB_INT_SLEEP, KINETIS_USB0_ISTAT);
+
+ /* Notify the class driver of the resume event */
+
+ if (priv->driver)
+ {
+ CLASS_RESUME(priv->driver, &priv->usbdev);
+ }
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Endpoint Helpers
+ ****************************************************************************/
+/****************************************************************************
+ * Name: khci_epreserve
+ ****************************************************************************/
+
+static inline struct khci_ep_s *
+khci_epreserve(struct khci_usbdev_s *priv, uint8_t epset)
+{
+ struct khci_ep_s *privep = NULL;
+ irqstate_t flags;
+ int epndx = 0;
+
+ flags = enter_critical_section();
+ epset &= priv->epavail;
+ if (epset)
+ {
+ /* Select the lowest bit in the set of matching, available endpoints
+ * (skipping EP0)
+ */
+
+ for (epndx = 1; epndx < KHCI_NENDPOINTS; epndx++)
+ {
+ uint8_t bit = KHCI_ENDP_BIT(epndx);
+ if ((epset & bit) != 0)
+ {
+ /* Mark the endpoint no longer available */
+
+ priv->epavail &= ~bit;
+
+ /* And return the pointer to the standard endpoint structure */
+
+ privep = &priv->eplist[epndx];
+ break;
+ }
+ }
+ }
+
+ leave_critical_section(flags);
+ return privep;
+}
+
+/****************************************************************************
+ * Name: khci_epunreserve
+ ****************************************************************************/
+
+static inline void
+khci_epunreserve(struct khci_usbdev_s *priv, struct khci_ep_s *privep)
+{
+ irqstate_t flags = enter_critical_section();
+ priv->epavail |= KHCI_ENDP_BIT(USB_EPNO(privep->ep.eplog));
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: khci_epreserved
+ ****************************************************************************/
+
+static inline bool
+khci_epreserved(struct khci_usbdev_s *priv, int epno)
+{
+ return ((priv->epavail & KHCI_ENDP_BIT(epno)) == 0);
+}
+
+/****************************************************************************
+ * Name: khci_ep0configure
+ ****************************************************************************/
+
+static void khci_ep0configure(struct khci_usbdev_s *priv)
+{
+ volatile struct usbotg_bdtentry_s *bdt;
+ struct khci_ep_s *ep0;
+ uint32_t bytecount;
+
+ /* Enable the EP0 endpoint */
+
+ khci_putreg(KHCI_EP_CONTROL, KINETIS_USB0_ENDPT0);
+
+ /* Configure the OUT BDTs. We assume that the ping-poing buffer index has
+ * just been reset and we expect to receive on the EVEN BDT first. Data
+ * toggle synchronization is not needed for SETUP packets.
+ */
+
+ ep0 = &priv->eplist[EP0];
+ bytecount = (USB_SIZEOF_CTRLREQ << USB_BDT_BYTECOUNT_SHIFT);
+
+ bdt = &g_bdt[EP0_OUT_EVEN];
+ bdt->addr = (uint8_t *)&priv->ctrl;
+ bdt->status = (USB_BDT_UOWN | bytecount);
+ ep0->bdtout = bdt;
+
+ bdt++;
+ bdt->status = (USB_BDT_UOWN | bytecount);
+ bdt->addr = (uint8_t *)&priv->ctrl;
+
+ /* Configure the IN BDTs. */
+
+ bdt = &g_bdt[EP0_IN_EVEN];
+ bdt->status = 0;
+ bdt->addr = 0;
+ ep0->bdtin = bdt;
+
+ bdt++;
+ bdt->status = 0;
+ bdt->addr = 0;
+
+ /* Data toggling is not used on SETUP transfers. And IN transfer resulting
+ * from a SETUP command should begin with DATA1.
+ */
+
+ ep0->rxdata1 = 0;
+ ep0->txdata1 = 1;
+}
+
+/****************************************************************************
+ * Endpoint operations
+ ****************************************************************************/
+/****************************************************************************
+ * Name: khci_epconfigure
+ ****************************************************************************/
+
+static int khci_epconfigure(struct usbdev_ep_s *ep,
+ const struct usb_epdesc_s *desc,
+ bool last)
+{
+ struct khci_ep_s *privep = (struct khci_ep_s *)ep;
+ volatile struct usbotg_bdtentry_s *bdt;
+ uint16_t maxpacket;
+ uint32_t regval;
+ uint8_t epno;
+ bool epin;
+ bool bidi;
+ int index;
+
+#ifdef CONFIG_DEBUG
+ if (!ep || !desc)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ ulldbg("ERROR: ep=%p desc=%p\n");
+ return -EINVAL;
+ }
+#endif
+
+ /* Get the unadorned endpoint address */
+
+ epno = USB_EPNO(desc->addr);
+ epin = USB_ISEPIN(desc->addr);
+
+ usbtrace(TRACE_EPCONFIGURE, (uint16_t)epno);
+ DEBUGASSERT(epno == USB_EPNO(ep->eplog));
+
+ /* Set the requested type */
+
+ switch (desc->attr & USB_EP_ATTR_XFERTYPE_MASK)
+ {
+ case USB_EP_ATTR_XFER_INT: /* Interrupt endpoint */
+ regval = epin ? KHCI_EP_INTIN : KHCI_EP_INTOUT;
+ break;
+
+ case USB_EP_ATTR_XFER_BULK: /* Bulk endpoint */
+ regval = epin ? KHCI_EP_BULKIN : KHCI_EP_BULKOUT;
+ break;
+
+ case USB_EP_ATTR_XFER_ISOC: /* Isochronous endpoint */
+ regval = epin ? KHCI_EP_ISOCIN : KHCI_EP_ISOCOUT;
+ break;
+
+ case USB_EP_ATTR_XFER_CONTROL: /* Control endpoint */
+ regval = KHCI_EP_CONTROL;
+ bidi = true;
+ break;
+
+ default:
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADEPTYPE), (uint16_t)desc->type);
+ return -EINVAL;
+ }
+
+ /* Enable the endpoint */
+
+ khci_putreg(regval, KINETIS_USB0_ENDPT(epno));
+
+ /* Setup up buffer descriptor table (BDT) entry/ies for this endpoint */
+
+ if (epin || bidi)
+ {
+ /* Get the pointer to BDT entry */
+
+ index = EP(epno, EP_DIR_IN, EP_PP_EVEN);
+ bdt = &g_bdt[index];
+ privep->bdtin = bdt;
+
+ /* Mark that we own the entry */
+
+ bdt->status = 0;
+ bdt->addr = 0;
+
+ bdtdbg("EP%d BDT IN [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr);
+
+ /* Now do the same for the other buffer. */
+
+ bdt++;
+ bdt->status = 0;
+ bdt->addr = 0;
+
+ bdtdbg("EP%d BDT IN [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr);
+ }
+
+ if (!epin || bidi)
+ {
+ index = EP(epno, EP_DIR_OUT, EP_PP_EVEN);
+ bdt = &g_bdt[index];
+ privep->bdtout = bdt;
+
+ /* Mark that we own the entry */
+
+ bdt->status = 0;
+ bdt->addr = 0;
+
+ bdtdbg("EP%d BDT OUT [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr);
+
+ /* Now do the same for the other buffer. */
+
+ bdt++;
+ bdt->status = 0;
+ bdt->addr = 0;
+
+ bdtdbg("EP%d BDT OUT [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr);
+ }
+
+ /* Get the maxpacket size of the endpoint. */
+
+ maxpacket = GETUINT16(desc->mxpacketsize);
+ DEBUGASSERT(maxpacket <= KHCI_MAXPACKET_SIZE);
+ ep->maxpacket = maxpacket;
+
+ /* Set the full, logic EP number (that includes direction encoded in bit 7) */
+
+ if (epin)
+ {
+ ep->eplog = USB_EPIN(epno);
+ }
+ else
+ {
+ ep->eplog = USB_EPOUT(epno);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: khci_epdisable
+ ****************************************************************************/
+
+static int khci_epdisable(struct usbdev_ep_s *ep)
+{
+ struct khci_ep_s *privep;
+ volatile uint32_t *ptr;
+ int epno;
+ int i;
+ irqstate_t flags;
+
+#ifdef CONFIG_DEBUG
+ if (!ep)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ ulldbg("ERROR: ep=%p\n", ep);
+ return -EINVAL;
+ }
+#endif
+
+ privep = (struct khci_ep_s *)ep;
+ epno = USB_EPNO(ep->eplog);
+ usbtrace(TRACE_EPDISABLE, epno);
+
+ /* Cancel any ongoing activity */
+
+ flags = enter_critical_section();
+ khci_cancelrequests(privep, -ESHUTDOWN);
+
+ /* Disable the endpoint */
+
+ khci_putreg(0, KINETIS_USB0_ENDPT(epno));
+
+ /* Reset the BDTs for the endpoint. Four BDT entries per endpoint; Two
+ * 32-bit words per BDT.
+ */
+
+ ptr = (uint32_t *)&g_bdt[EP(epno, EP_DIR_OUT, EP_PP_EVEN)];
+ for (i = 0; i < USB_BDT_WORD_SIZE * USB_NBDTS_PER_EP; i++)
+ {
+ *ptr++ = 0;
+ }
+
+ leave_critical_section(flags);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: khci_epallocreq
+ ****************************************************************************/
+
+static struct usbdev_req_s *khci_epallocreq(struct usbdev_ep_s *ep)
+{
+ struct khci_req_s *privreq;
+
+#ifdef CONFIG_DEBUG
+ if (!ep)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return NULL;
+ }
+#endif
+ usbtrace(TRACE_EPALLOCREQ, USB_EPNO(ep->eplog));
+
+ privreq = (struct khci_req_s *)kmm_malloc(sizeof(struct khci_req_s));
+ if (!privreq)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_ALLOCFAIL), 0);
+ return NULL;
+ }
+
+ memset(privreq, 0, sizeof(struct khci_req_s));
+ return &privreq->req;
+}
+
+/****************************************************************************
+ * Name: khci_epfreereq
+ ****************************************************************************/
+
+static void khci_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
+{
+ struct khci_req_s *privreq = (struct khci_req_s *)req;
+
+#ifdef CONFIG_DEBUG
+ if (!ep || !req)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return;
+ }
+#endif
+ usbtrace(TRACE_EPFREEREQ, USB_EPNO(ep->eplog));
+
+ kmm_free(privreq);
+}
+
+/****************************************************************************
+ * Name: khci_epsubmit
+ ****************************************************************************/
+
+static int khci_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
+{
+ struct khci_req_s *privreq = (struct khci_req_s *)req;
+ struct khci_ep_s *privep = (struct khci_ep_s *)ep;
+ struct khci_usbdev_s *priv;
+ irqstate_t flags;
+ uint8_t epno;
+ int ret = OK;
+
+#ifdef CONFIG_DEBUG
+ if (!req || !req->callback || !req->buf || !ep)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ ulldbg("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+ return -EINVAL;
+ }
+#endif
+
+ usbtrace(TRACE_EPSUBMIT, USB_EPNO(ep->eplog));
+ priv = privep->dev;
+
+#ifdef CONFIG_DEBUG
+ if (!priv->driver)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
+ ulldbg("ERROR: driver=%p\n", priv->driver);
+ return -ESHUTDOWN;
+ }
+#endif
+
+ /* Handle the request from the class driver */
+
+ epno = USB_EPNO(ep->eplog);
+ req->result = -EINPROGRESS;
+ req->xfrd = 0;
+ privreq->inflight[0] = 0;
+#ifndef CONFIG_USBDEV_NOWRITEAHEAD
+ privreq->inflight[1] = 0;
+#endif
+ flags = enter_critical_section();
+
+ /* Add the new request to the request queue for the OUT endpoint */
+
+ khci_addlast(&privep->pend, privreq);
+
+ /* Handle IN (device-to-host) requests. NOTE: If the class device is
+ * using the bi-directional EP0, then we assume that they intend the EP0
+ * IN functionality.
+ */
+
+ if (USB_ISEPIN(ep->eplog) || epno == EP0)
+ {
+ usbtrace(TRACE_INREQQUEUED(epno), req->len);
+
+ /* If the endpoint is not stalled and an IN endpoint BDT is available,
+ * then transfer the data now.
+ */
+
+ if (!privep->stalled)
+ {
+ (void)khci_wrrequest(priv, privep);
+ }
+ }
+
+ /* Handle OUT (host-to-device) requests */
+
+ else
+ {
+ usbtrace(TRACE_OUTREQQUEUED(epno), req->len);
+
+ /* Set up the read operation (unless the endpoint is stalled). Because
+ * the KHCI supports ping-pong* buffering. There may be two pending
+ * read requests. The following call will attempt to setup a read
+ * using this request for this endpoint. It is not harmful if this
+ * fails.
+ */
+
+ if (!privep->stalled)
+ {
+ (void)khci_rdrequest(priv, privep);
+ }
+ }
+
+ leave_critical_section(flags);
+ return ret;
+}
+
+/****************************************************************************
+ * Name: khci_epcancel
+ ****************************************************************************/
+
+static int khci_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
+{
+ struct khci_ep_s *privep = (struct khci_ep_s *)ep;
+ irqstate_t flags;
+
+#ifdef CONFIG_DEBUG
+ if (!ep || !req)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return -EINVAL;
+ }
+#endif
+
+ usbtrace(TRACE_EPCANCEL, USB_EPNO(ep->eplog));
+
+ flags = enter_critical_section();
+ khci_cancelrequests(privep, -EAGAIN);
+ leave_critical_section(flags);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: khci_epbdtstall
+ ****************************************************************************/
+
+static int khci_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin)
+{
+ struct khci_ep_s *privep;
+ struct khci_usbdev_s *priv;
+ volatile struct usbotg_bdtentry_s *bdt;
+ volatile struct usbotg_bdtentry_s *otherbdt;
+ uint32_t regaddr;
+ uint32_t regval;
+ uint8_t epno;
+
+ /* Recover pointers */
+
+ privep = (struct khci_ep_s *)ep;
+ priv = (struct khci_usbdev_s *)privep->dev;
+ epno = USB_EPNO(ep->eplog);
+
+ /* Check for an IN endpoint */
+
+ if (epin)
+ {
+ /* Get a pointer to the current IN BDT */
+
+ bdt = privep->bdtin;
+
+ /* Get the other BDT */
+
+ otherbdt = &g_bdt[EP(epno, EP_DIR_IN, EP_PP_EVEN)];
+ if (otherbdt == bdt)
+ {
+ otherbdt++;
+ }
+
+ /* Reset the data toggle */
+
+ privep->txdata1 = false;
+ }
+
+ /* Otherwise it is an an OUT endpoint. */
+
+ else
+ {
+ /* Get a pointer to the current OUT BDT */
+
+ bdt = privep->bdtout;
+
+ /* Get a pointer to the other BDT */
+
+ otherbdt = &g_bdt[EP(epno, EP_DIR_OUT, EP_PP_EVEN)];
+ if (otherbdt == bdt)
+ {
+ otherbdt++;
+ }
+
+ /* Reset the data toggle */
+
+ privep->rxdata1 = false;
+ }
+
+ /* Handle the resume condition */
+
+ if (resume)
+ {
+ /* Resuming a stalled endpoint */
+
+ usbtrace(TRACE_EPRESUME, epno);
+
+ /* Point to the appropriate EP register */
+
+ regaddr = KINETIS_USB0_ENDPT(epno);
+
+ /* Clear the STALL bit in the UEP register */
+
+ regval = khci_getreg(regaddr);
+ regval &= ~USB_ENDPT_EPSTALL;
+ khci_putreg(regval, regaddr);
+
+ /* Check for the EP0 OUT endpoint. This is a special case because we
+ * need to set it up to receive the next setup packet (Hmmm... what
+ * if there are queued outgoing reponses. We need to revisit this.)
+ */
+
+ if (epno == 0 && !epin)
+ {
+ uint32_t bytecount = (USB_SIZEOF_CTRLREQ << USB_BDT_BYTECOUNT_SHIFT);
+ uint32_t physaddr = &priv->ctrl;
+
+ /* Configure the other BDT to receive a SETUP command. */
+
+ otherbdt->addr = (uint8_t *)physaddr;
+ otherbdt->status = (USB_BDT_UOWN | bytecount);
+
+ /* Configure the current BDT to receive a SETUP command. */
+
+ bdt->addr = (uint8_t *)physaddr;
+ bdt->status = (USB_BDT_UOWN | bytecount);
+
+ bdtdbg("EP0 BDT IN [%p] {%08x, %08x}\n",
+ bdt, bdt->status, bdt->addr);
+ bdtdbg("EP0 BDT IN [%p] {%08x, %08x}\n",
+ otherbdt, otherbdt->status, otherbdt->addr);
+ }
+ else
+ {
+ /* Return the other BDT to the CPU. */
+
+ otherbdt->addr = 0;
+ otherbdt->status = 0;
+
+ /* Return the current BDT to the CPU. */
+
+ bdt->addr = 0;
+ bdt->status = 0;
+
+ bdtdbg("EP%d BDT %s [%p] {%08x, %08x}\n",
+ epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr);
+ bdtdbg("EP%d BDT %s [%p] {%08x, %08x}\n",
+ epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, otherbdt->addr);
+
+ /* Restart any queued requests (after a delay so that we can be assured
+ * that the hardware has recovered from the stall -- I don't know of any
+ * other way to assure this.).
+ */
+
+ khci_delayedrestart(priv, epno);
+ }
+ }
+
+ /* Handle the stall condition */
+
+ else
+ {
+ usbtrace(TRACE_EPSTALL, epno);
+ privep->stalled = true;
+
+ /* Stall the other BDT. */
+
+ otherbdt->status = (USB_BDT_UOWN | USB_BDT_BSTALL);
+ otherbdt->addr = 0;
+
+ /* Stall the current BDT. */
+
+ bdt->status = (USB_BDT_UOWN | USB_BDT_BSTALL);
+ bdt->addr = 0;
+
+ /* Stop any queued requests. Hmmm.. is there a race condition here? */
+
+ khci_rqstop(privep);
+
+ bdtdbg("EP%d BDT %s [%p] {%08x, %08x}\n",
+ epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr);
+ bdtdbg("EP%d BDT %s [%p] {%08x, %08x}\n",
+ epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, otherbdt->addr);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: khci_epstall
+ ****************************************************************************/
+
+static int khci_epstall(struct usbdev_ep_s *ep, bool resume)
+{
+ struct khci_ep_s *privep;
+ irqstate_t flags;
+ int ret;
+
+#ifdef CONFIG_DEBUG
+ if (!ep)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return -EINVAL;
+ }
+#endif
+
+ /* Recover pointers */
+
+ privep = (struct khci_ep_s *)ep;
+
+ /* STALL or RESUME the endpoint */
+
+ flags = enter_critical_section();
+
+ /* Special case EP0. When we stall EP0 we have to stall both the IN and
+ * OUT BDTs.
+ */
+
+ if (USB_EPNO(ep->eplog) == 0)
+ {
+ ret = khci_epbdtstall(ep, resume, true);
+ if (ret == OK)
+ {
+ ret = khci_epbdtstall(ep, resume, false);
+ }
+
+ /* Set the EP0 control state appropriately */
+
+ privep->dev->ctrlstate = resume ? CTRLSTATE_WAITSETUP : CTRLSTATE_STALLED;
+ }
+
+ /* Otherwise, select the BDT for the endpoint direction */
+
+ else
+ {
+ /* It is a unidirectional endpoint */
+
+ ret = khci_epbdtstall(ep, resume, USB_ISEPIN(ep->eplog));
+ }
+
+ leave_critical_section(flags);
+ return ret;
+}
+
+/****************************************************************************
+ * Device Controller Operations
+ ****************************************************************************/
+/****************************************************************************
+ * Name: khci_allocep
+ ****************************************************************************/
+
+static struct usbdev_ep_s *khci_allocep(struct usbdev_s *dev, uint8_t epno,
+ bool epin, uint8_t eptype)
+{
+ struct khci_usbdev_s *priv = (struct khci_usbdev_s *)dev;
+ struct khci_ep_s *privep = NULL;
+ uint16_t epset = KHCI_ENDP_ALLSET;
+
+ usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno);
+#ifdef CONFIG_DEBUG
+ if (!dev)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return NULL;
+ }
+#endif
+
+ /* Ignore any direction bits in the logical address */
+
+ epno = USB_EPNO(epno);
+
+ /* A logical address of 0 means that any endpoint will do */
+
+ if (epno > 0)
+ {
+ /* Otherwise, we will return the endpoint structure only for the requested
+ * 'logical' endpoint. All of the other checks will still be performed.
+ *
+ * First, verify that the logical endpoint is in the range supported by
+ * by the hardware.
+ */
+
+ if (epno >= KHCI_NENDPOINTS)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADEPNO), (uint16_t)epno);
+ return NULL;
+ }
+
+ /* Convert the logical address to a physical OUT endpoint address and
+ * remove all of the candidate endpoints from the bitset except for the
+ * the IN/OUT pair for this logical address.
+ */
+
+ epset = KHCI_ENDP_BIT(epno);
+ }
+
+ /* Check if the selected endpoint number is available */
+
+ privep = khci_epreserve(priv, epset);
+ if (!privep)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_EPRESERVE), (uint16_t)epset);
+ return NULL;
+ }
+
+ return &privep->ep;
+}
+
+/****************************************************************************
+ * Name: khci_freeep
+ ****************************************************************************/
+
+static void khci_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep)
+{
+ struct khci_usbdev_s *priv;
+ struct khci_ep_s *privep;
+
+#ifdef CONFIG_DEBUG
+ if (!dev || !ep)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return;
+ }
+#endif
+
+ priv = (struct khci_usbdev_s *)dev;
+ privep = (struct khci_ep_s *)ep;
+ usbtrace(TRACE_DEVFREEEP, (uint16_t)USB_EPNO(ep->eplog));
+ DEBUGASSERT(priv && privep);
+
+ /* Disable the endpoint */
+
+ (void)khci_epdisable(ep);
+
+ /* Mark the endpoint as available */
+
+ khci_epunreserve(priv, privep);
+}
+
+/****************************************************************************
+ * Name: khci_getframe
+ ****************************************************************************/
+
+static int khci_getframe(struct usbdev_s *dev)
+{
+ uint16_t frml;
+ uint16_t frmh;
+ uint16_t tmp;
+
+#ifdef CONFIG_DEBUG
+ if (!dev)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return -EINVAL;
+ }
+#endif
+
+ /* Return the last frame number detected by the hardware. Thr FRMH/L
+ * registers are updated with the current frame number whenever a SOF
+ * TOKEN is received.
+ */
+
+ do
+ {
+ /* Loop until we can be sure that there was no wrap from the FRML
+ * to the FRMH register.
+ */
+
+ frmh = khci_getreg(KINETIS_USB0_FRMNUMH) & USB_FRMNUMH_MASK;
+ frml = khci_getreg(KINETIS_USB0_FRMNUML) & USB_FRMNUML_MASK;
+ tmp = khci_getreg(KINETIS_USB0_FRMNUMH) & USB_FRMNUMH_MASK;
+ }
+ while (frmh != tmp);
+
+ /* Combine to for the full 11-bit value */
+
+ tmp = (frmh) << 8 | frml;
+ usbtrace(TRACE_DEVGETFRAME, tmp);
+ return tmp;
+}
+
+/****************************************************************************
+ * Name: khci_wakeup
+ ****************************************************************************/
+
+static int khci_wakeup(struct usbdev_s *dev)
+{
+ struct khci_usbdev_s *priv = (struct khci_usbdev_s *)dev;
+
+ usbtrace(TRACE_DEVWAKEUP, 0);
+#ifdef CONFIG_DEBUG
+ if (!dev)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return -EINVAL;
+ }
+#endif
+
+ /* Resume normal operation. */
+
+ khci_resume(priv);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: khci_selfpowered
+ ****************************************************************************/
+
+static int khci_selfpowered(struct usbdev_s *dev, bool selfpowered)
+{
+ struct khci_usbdev_s *priv = (struct khci_usbdev_s *)dev;
+
+ usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered);
+
+#ifdef CONFIG_DEBUG
+ if (!dev)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return -ENODEV;
+ }
+#endif
+
+ priv->selfpowered = selfpowered;
+ return OK;
+}
+
+/****************************************************************************
+ * Initialization/Reset
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: khci_reset
+ *
+ * Description:
+ * Reset the software and hardware states. If the USB controller has been
+ * attached to a host, then connect to the bus as well. At the end of
+ * this reset, the hardware should be in the full up, ready-to-run state.
+ *
+ ****************************************************************************/
+
+static void khci_reset(struct khci_usbdev_s *priv)
+{
+ /* Reset the software configuration */
+
+ khci_swreset(priv);
+
+ /* Re-configure the USB controller in its initial, unconnected state */
+
+ khci_hwreset(priv);
+
+ /* khci_attach() was called, then the attach flag will be set and we
+ * should also attach to the USB bus.
+ */
+
+ if (priv->attached)
+ {
+ /* usbdev_attach() has already been called.. attach to the bus
+ * now
+ */
+
+ khci_attach(priv);
+ }
+}
+
+/****************************************************************************
+ * Name: khci_attach
+ ****************************************************************************/
+
+static void khci_attach(struct khci_usbdev_s *priv)
+{
+ uint32_t regval;
+
+ /* Check if we are in the detached state */
+
+ if (priv->devstate == DEVSTATE_DETACHED)
+ {
+ /* Disable USB interrupts at the interrupt controller */
+
+ up_disable_irq(KINETIS_IRQ_USBOTG);
+
+ /* Initialize registers to known states. */
+
+ //khci_putreg(0, KINETIS_USB0_CTL);
+
+#if 1
+ khci_putreg(0x1,KINETIS_USB0_CTL);
+ khci_putreg(0,KINETIS_USB0_USBCTRL);
+#endif
+
+ /* Enable interrupts at the USB controller */
+
+ khci_putreg(ERROR_INTERRUPTS, KINETIS_USB0_ERREN);
+ khci_putreg(NORMAL_INTERRUPTS, KINETIS_USB0_INTEN);
+
+ /* Configure EP0 */
+
+ khci_ep0configure(priv);
+
+ /* Flush any pending transactions */
+#if 1
+ while ((khci_getreg(KINETIS_USB0_ISTAT) & USB_INT_TOKDNE) != 0)
+ {
+ khci_putreg(USB_INT_TOKDNE, KINETIS_USB0_ISTAT);
+ }
+
+ /* Make sure packet processing is enabled */
+
+ regval = khci_getreg(KINETIS_USB0_CTL);
+ regval &= ~USB_CTL_TXSUSPENDTOKENBUSY;
+ khci_putreg(regval, KINETIS_USB0_CTL);
+
+ /* Enable the USB module and attach to bus */
+
+ do
+ {
+ regval = khci_getreg(KINETIS_USB0_CTL);
+ if ((regval & USB_CTL_USBENSOFEN) == 0)
+ {
+ khci_putreg(regval | USB_CTL_USBENSOFEN, KINETIS_USB0_CTL);
+ }
+ }
+ while ((regval & USB_CTL_USBENSOFEN) == 0);
+
+ /* Enable OTG */
+
+#ifdef CONFIG_USBOTG
+ regval = khci_getreg(KINETIS_USB0_OTGCTL);
+ regval |= (USBOTG_CON_DPPULUP | USBOTG_CON_OTGEN);
+ khci_putreg(regval, KINETIS_USB0_OTGCTL);
+#endif
+
+ /* Transition to the attached state */
+
+ priv->devstate = DEVSTATE_ATTACHED;
+ priv->usbdev.speed = USB_SPEED_FULL;
+
+ /* Clear all pending USB interrupts */
+
+ khci_putreg(USB_EINT_ALL, KINETIS_USB0_ERRSTAT);
+ khci_putreg(USB_INT_ALL, KINETIS_USB0_ISTAT);
+#endif
+
+ /* Enable USB interrupts at the interrupt controller */
+
+ up_enable_irq(KINETIS_IRQ_USBOTG);
+
+ /* Enable pull-up to connect the device. The host should enumerate us
+ * some time after this
+ */
+
+ kinetis_usbpullup(&priv->usbdev, true);
+ }
+}
+
+/****************************************************************************
+ * Name: khci_detach
+ ****************************************************************************/
+
+static void khci_detach(struct khci_usbdev_s *priv)
+{
+ uint32_t regval;
+ /* Disable USB interrupts at the interrupt controller */
+
+ up_disable_irq(KINETIS_IRQ_USBOTG);
+
+ /* Disable the USB controller and detach from the bus. */
+
+ khci_putreg(0, KINETIS_USB0_CTL);
+
+ /* Mask all USB interrupts */
+
+ khci_putreg(0, KINETIS_USB0_INTEN);
+
+ /* We are now in the detached state */
+
+ priv->attached = 0;
+ priv->devstate = DEVSTATE_DETACHED;
+
+#ifdef CONFIG_USBOTG
+ /* Disable the D+ Pullup */
+
+ regval = khci_getreg(KINETIS_USB0_OTGCTL);
+ regval &= ~USBOTG_CON_DPPULUP;
+ khci_putreg(regval, KINETIS_USB0_OTGCTL);
+
+ /* Disable and deactivate HNP */
+#warning Missing Logic
+
+ /* Check if the ID Pin Changed State */
+
+ if ((khci_getreg(KINETIS_USB0_ISTAT) & khci_getreg(KINETIS_USB0_OTGICR) & USBOTG_INT_ID) != 0)
+ {
+ /* Re-detect & Initialize */
+#warning "Missing logic"
+
+ /* Clear ID Interrupt Flag */
+
+ khci_putreg(USBOTG_INT_ID, KINETIS_USB0_ISTAT);
+ }
+#endif
+}
+
+/****************************************************************************
+ * Name: khci_swreset
+ ****************************************************************************/
+
+static void khci_swreset(struct khci_usbdev_s *priv)
+{
+ int epno;
+
+ /* Tell the class driver that we are disconnected. The class driver
+ * should then accept any new configurations.
+ */
+
+ if (priv->driver)
+ {
+ CLASS_DISCONNECT(priv->driver, &priv->usbdev);
+ }
+
+ /* Flush and reset endpoint states (except EP0) */
+
+ for (epno = 1; epno < KHCI_NENDPOINTS; epno++)
+ {
+ struct khci_ep_s *privep = &priv->eplist[epno];
+
+ /* Cancel any queued requests. Since they are canceled
+ * with status -ESHUTDOWN, then will not be requeued
+ * until the configuration is reset. NOTE: This should
+ * not be necessary... the CLASS_DISCONNECT above should
+ * result in the class implementation calling khci_epdisable
+ * for each of its configured endpoints.
+ */
+
+ khci_cancelrequests(privep, -EAGAIN);
+
+ /* Reset endpoint status */
+
+ privep->stalled = false;
+ privep->halted = false;
+ privep->txnullpkt = false;
+ }
+
+ /* Reset to the default address */
+
+ khci_putreg(0, KINETIS_USB0_ADDR);
+
+ /* Unconfigure each endpoint by clearing the endpoint control registers
+ * (except EP0)
+ */
+
+ for (epno = 1; epno < KHCI_NENDPOINTS; epno++)
+ {
+ khci_putreg(0, KINETIS_USB0_ENDPT(epno));
+ }
+
+ /* Reset the control state */
+
+ priv->ctrlstate = CTRLSTATE_WAITSETUP;
+ priv->rxbusy = 0;
+}
+
+/****************************************************************************
+ * Name: khci_hwreset
+ *
+ * Description:
+ * Reset the hardware and leave it in a known, unready state.
+ *
+ ****************************************************************************/
+
+static void khci_hwreset(struct khci_usbdev_s *priv)
+{
+ uint32_t physaddr;
+ uint32_t regval;
+
+#define USB_FLASH_ACCESS
+#ifdef USB_FLASH_ACCESS
+ /* Allow USBOTG-FS Controller to Read from FLASH */
+ regval = getreg32(KINETIS_FMC_PFAPR);
+ regval &= ~(FMC_PFAPR_M4AP_MASK);
+ regval |= (FMC_PFAPR_RDONLY << FMC_PFAPR_M4AP_SHIFT);
+ putreg32(regval, KINETIS_FMC_PFAPR);
+#endif
+
+ /* Clear all of the buffer descriptor table (BDT) entries */
+
+ memset((void *)g_bdt, 0, sizeof(g_bdt));
+
+ /* Soft reset the USB Module*/
+ regval = khci_getreg(KINETIS_USB0_USBTRC0);
+ regval |= USB_USBTRC0_USBRESET;
+ khci_putreg(regval,KINETIS_USB0_USBTRC0);
+
+ //is this really necessary?
+ while (khci_getreg(KINETIS_USB0_USBTRC0) & USB_USBTRC0_USBRESET);
+
+ /* Set the address of the buffer descriptor table (BDT)
+ *
+ * BDTP1: Bit 1-7: Bits 9-15 of the BDT base address
+ * BDTP2: Bit 0-7: Bits 16-23 of the BDT base address
+ * BDTP3: Bit 0-7: Bits 24-31 of the BDT base address
+ */
+
+ khci_putreg((uint8_t)((uint32_t)g_bdt >> 24), KINETIS_USB0_BDTPAGE3);
+ khci_putreg((uint8_t)((uint32_t)g_bdt >> 16), KINETIS_USB0_BDTPAGE2);
+ khci_putreg((uint8_t)(((uint32_t)g_bdt >> 8) & USB_BDTPAGE1_MASK), KINETIS_USB0_BDTPAGE1);
+
+ ulldbg("BDT Address %hhx \n" ,&g_bdt);
+ ulldbg("BDTPAGE3 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE3));
+ ulldbg("BDTPAGE2 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE2));
+ ulldbg("BDTPAGE1 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE1));
+
+
+ /* Clear any pending interrupts */
+
+ khci_putreg(0xFF, KINETIS_USB0_ERRSTAT);
+ khci_putreg(0xFF, KINETIS_USB0_ISTAT);
+ khci_putreg(0xFF,KINETIS_USB0_OTGISTAT);
+
+#if 1
+
+ /* Assert reset request to all of the Ping Pong buffer pointers. This
+ * will reset all Even/Odd buffer pointers to the EVEN BD banks.
+ */
+
+ regval = khci_getreg(KINETIS_USB0_CTL);
+ regval |= USB_CTL_ODDRST;
+ khci_putreg(regval, KINETIS_USB0_CTL);
+
+ /* Bring the ping pong buffer pointers out of reset */
+
+ regval &= ~USB_CTL_ODDRST;
+ khci_putreg(regval, KINETIS_USB0_CTL);
+
+#endif
+
+#if 1
+ /*Undocumented bit*/
+ regval = khci_getreg(KINETIS_USB0_USBTRC0);
+ regval |= 0x40;
+ khci_putreg(regval,KINETIS_USB0_USBTRC0);
+#endif
+
+ priv->devstate = DEVSTATE_DETACHED;
+}
+
+/****************************************************************************
+ * Name: khci_stateinit
+ ****************************************************************************/
+
+static void khci_stateinit(struct khci_usbdev_s *priv)
+{
+ int epno;
+
+ /* Disconnect the device / disable the pull-up. We don't want the
+ * host to enumerate us until the class driver is registered.
+ */
+
+ kinetis_usbpullup(&priv->usbdev, false);
+
+ /* Initialize the device state structure. NOTE: many fields
+ * have the initial value of zero and, hence, are not explicitly
+ * initialized here.
+ */
+
+ memset(priv, 0, sizeof(struct khci_usbdev_s));
+ priv->usbdev.ops = &g_devops;
+ priv->usbdev.ep0 = &priv->eplist[EP0].ep;
+ priv->epavail = KHCI_ENDP_ALLSET & ~KHCI_ENDP_BIT(EP0);
+ priv->rwakeup = 1;
+
+ /* Initialize the endpoint list */
+
+ for (epno = 0; epno < KHCI_NENDPOINTS; epno++)
+ {
+ struct khci_ep_s *privep = &priv->eplist[epno];
+
+ /* Set endpoint operations, reference to driver structure (not
+ * really necessary because there is only one controller), and
+ * the (physical) endpoint number which is just the index to the
+ * endpoint.
+ */
+
+ privep->ep.ops = &g_epops;
+ privep->dev = priv;
+ privep->ep.eplog = epno;
+
+ /* We will use a fixed maxpacket size for all endpoints (perhaps
+ * ISOC endpoints could have larger maxpacket???). A smaller
+ * packet size can be selected when the endpoint is configured.
+ */
+
+ privep->ep.maxpacket = KHCI_MAXPACKET_SIZE;
+ }
+
+ /* Select a smaller endpoint size for EP0 */
+
+#if KHCI_EP0MAXPACKET < KHCI_MAXPACKET_SIZE
+ priv->eplist[EP0].ep.maxpacket = KHCI_EP0MAXPACKET;
+#endif
+}
+
+/****************************************************************************
+ * Name: khci_hwshutdown
+ ****************************************************************************/
+
+static void khci_hwshutdown(struct khci_usbdev_s *priv)
+{
+ uint32_t regval;
+
+ /* Put the hardware and driver in its initial, unconnected state */
+
+ khci_swreset(priv);
+ khci_hwreset(priv);
+ priv->usbdev.speed = USB_SPEED_UNKNOWN;
+
+ /* Disable all interrupts and force the USB controller into reset */
+
+ khci_putreg(0, KINETIS_USB0_ERREN);
+ khci_putreg(0, KINETIS_USB0_INTEN);
+
+ /* Clear any pending interrupts */
+
+ khci_putreg(USB_EINT_ALL, KINETIS_USB0_ERRSTAT);
+ khci_putreg(USB_INT_ALL, KINETIS_USB0_ISTAT);
+
+ /* Disconnect the device / disable the pull-up */
+
+ kinetis_usbpullup(&priv->usbdev, false);
+
+ /* Power down the USB controller */
+#warning FIXME powerdown USB Controller
+#if 0
+ regval = khci_getreg(KHCI_USB_PWRC);
+ regval &= ~USB_PWRC_USBPWR;
+ khci_putreg(regval, KHCI_USB_PWRC);
+#endif
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+/****************************************************************************
+ * Name: up_usbinitialize
+ *
+ * Description:
+ * Initialize the USB driver
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1)
+
+void up_usbinitialize(void)
+{
+ uint32_t regval;
+ /* For now there is only one USB controller, but we will always refer to
+ * it using a pointer to make any future ports to multiple USB controllers
+ * easier.
+ */
+#if 1
+ //1: Select clock source
+ regval = getreg32(KINETIS_SIM_SOPT2);
+ regval |= SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_USBSRC;
+ putreg32(regval, KINETIS_SIM_SOPT2);
+
+ regval = getreg32(KINETIS_SIM_CLKDIV2);
+#if defined(CONFIG_TEENSY_3X_OVERCLOCK)
+ regval = SIM_CLKDIV2_USBDIV(1); //(USBFRAC + 0)/(USBDIV + 1) = (1 + 0)/(1 + 1) = 1/2 for 96Mhz clock
+#else
+ //72Mhz
+ regval = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC;
+#endif
+ putreg32(regval, KINETIS_SIM_CLKDIV2);
+
+ //2: Gate USB clock
+ regval = getreg32(KINETIS_SIM_SCGC4);
+ regval |= SIM_SCGC4_USBOTG;
+ putreg32(regval, KINETIS_SIM_SCGC4);
+
+#endif
+
+
+ struct khci_usbdev_s *priv = &g_usbdev;
+
+ usbtrace(TRACE_DEVINIT, 0);
+
+ /* Initialize the driver state structure */
+
+ khci_stateinit(priv);
+
+ /* Then perform a few one-time initialization operstions. First, initialize
+ * the watchdog timer that is used to perform a delayed queue restart
+ * after recovering from a stall.
+ */
+
+ priv->epstalled = 0;
+ priv->wdog = wd_create();
+
+ /* Attach USB controller interrupt handler. The hardware will not be
+ * initialized and interrupts will not be enabled until the class device
+ * driver is bound. Getting the IRQs here only makes sure that we have
+ * them when we need them later.
+ */
+
+ if (irq_attach(KINETIS_IRQ_USBOTG, khci_interrupt) != 0)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_IRQREGISTRATION),
+ (uint16_t)KINETIS_IRQ_USBOTG);
+ up_usbuninitialize();
+ }
+#ifdef CONFIG_ARCH_IRQPRIO
+ /* Set the interrupt priority */
+
+ up_prioritize_irq(KINETIS_IRQ_USBOTG, 112);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_usbuninitialize
+ * Description:
+ * Initialize the USB driver
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void up_usbuninitialize(void)
+{
+ /* For now there is only one USB controller, but we will always refer to
+ * it using a pointer to make any future ports to multiple USB controllers
+ * easier.
+ */
+
+ struct khci_usbdev_s *priv = &g_usbdev;
+ irqstate_t flags;
+
+ flags = enter_critical_section();
+ usbtrace(TRACE_DEVUNINIT, 0);
+
+ /* Disable and detach the USB IRQs */
+
+ up_disable_irq(KINETIS_IRQ_USBOTG);
+ irq_detach(KINETIS_IRQ_USBOTG);
+
+ if (priv->driver)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_DRIVERREGISTERED), 0);
+ usbdev_unregister(priv->driver);
+ }
+
+ /* Put the hardware in an inactive state */
+
+ khci_hwshutdown(priv);
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: usbdev_register
+ *
+ * Description:
+ * Register a USB device class driver. The class driver's bind() method
+ * will be called to bind it to a USB device driver.
+ *
+ ****************************************************************************/
+
+int usbdev_register(struct usbdevclass_driver_s *driver)
+{
+ /* For now there is only one USB controller, but we will always refer to
+ * it using a pointer to make any future ports to multiple USB controllers
+ * easier.
+ */
+
+ struct khci_usbdev_s *priv = &g_usbdev;
+ int ret;
+
+ usbtrace(TRACE_DEVREGISTER, 0);
+
+#ifdef CONFIG_DEBUG
+ if (!driver || !driver->ops->bind || !driver->ops->unbind ||
+ !driver->ops->disconnect || !driver->ops->setup)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return -EINVAL;
+ }
+
+ if (priv->driver)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_DRIVER), 0);
+ return -EBUSY;
+ }
+#endif
+
+ /* First hook up the driver */
+
+ priv->driver = driver;
+
+ /* Then bind the class driver */
+
+ ret = CLASS_BIND(driver, &priv->usbdev);
+ if (ret)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BINDFAILED), (uint16_t)-ret);
+ priv->driver = NULL;
+ }
+
+ /* The class driver has been successfully bound. */
+
+ else
+ {
+ /* Setup the USB controller in it initial ready-to-run state (might
+ * be connected or unconnected, depending on usbdev_attach() has
+ * been called).
+ */
+
+ DEBUGASSERT(priv->devstate == DEVSTATE_DETACHED);
+ khci_reset(priv);
+ }
+ return ret;
+}
+
+/****************************************************************************
+ * Name: usbdev_unregister
+ *
+ * Description:
+ * Un-register usbdev class driver. If the USB device is connected to a
+ * USB host, it will first disconnect(). The driver is also requested to
+ * unbind() and clean up any device state, before this procedure finally
+ * returns.
+ *
+ ****************************************************************************/
+
+int usbdev_unregister(struct usbdevclass_driver_s *driver)
+{
+ /* For now there is only one USB controller, but we will always refer to
+ * it using a pointer to make any future ports to multiple USB controllers
+ * easier.
+ */
+
+ struct khci_usbdev_s *priv = &g_usbdev;
+ irqstate_t flags;
+
+ usbtrace(TRACE_DEVUNREGISTER, 0);
+
+#ifdef CONFIG_DEBUG
+ if (driver != priv->driver)
+ {
+ usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
+ return -EINVAL;
+ }
+#endif
+
+ /* Reset the hardware and cancel all requests. All requests must be
+ * canceled while the class driver is still bound. This will put
+ * the hardware back into its initial, unconnected state.
+ */
+
+ flags = enter_critical_section();
+ khci_swreset(priv);
+ khci_hwreset(priv);
+
+ /* Unbind the class driver */
+
+ CLASS_UNBIND(driver, &priv->usbdev);
+
+ /* Disable USB controller interrupts (but keep them attached) */
+
+ up_disable_irq(KINETIS_IRQ_USBOTG);
+
+ /* Put the hardware in an inactive state. Then bring the hardware back up
+ * in the reset state (this is probably not necessary, the khci_hwreset()
+ * call above was probably sufficient).
+ */
+
+ khci_hwshutdown(priv);
+ khci_stateinit(priv);
+
+ /* Unhook the driver */
+
+ priv->driver = NULL;
+ leave_critical_section(flags);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: khci_usbattach and khci_usbdetach
+ *
+ * Description:
+ * The USB stack must be notified when the device is attached or detached
+ * by calling one of these functions.
+ *
+ ****************************************************************************/
+
+void khci_usbattach(void)
+{
+ /* For now there is only one USB controller, but we will always refer to
+ * it using a pointer to make any future ports to multiple USB controllers
+ * easier.
+ */
+
+ struct khci_usbdev_s *priv = &g_usbdev;
+
+ /* Mark that we are attached */
+
+ priv->attached = 1;
+
+ /* This API may be called asynchronously from other initialization
+ * interfaces. In particular, we may not want to attach the bus yet...
+ * that should only be done when the class driver is attached. Has
+ * the class driver been attached?
+ */
+
+ if (priv->driver)
+ {
+ /* Yes.. then attach to the bus */
+
+ khci_attach(priv);
+ }
+}
+
+void khci_usbdetach(void)
+{
+ /* For now there is only one USB controller, but we will always refer to
+ * it using a pointer to make any future ports to multiple USB controllers
+ * easier.
+ */
+
+ struct khci_usbdev_s *priv = &g_usbdev;
+
+ /* Detach from the bus */
+
+ khci_detach(priv);
+}
+
+#endif /* CONFIG_USBDEV && CONFIG_KHCI_USB */
diff --git a/arch/arm/src/kinetis/kinetis_usbotg.h b/arch/arm/src/kinetis/kinetis_usbotg.h
index 127c718312..22a474a824 100644
--- a/arch/arm/src/kinetis/kinetis_usbotg.h
+++ b/arch/arm/src/kinetis/kinetis_usbotg.h
@@ -217,6 +217,8 @@
#define USB_INT_ATTACH (1 << 6) /* Bit 6: Attach Interrupt */
#define USB_INT_STALL (1 << 7) /* Bit 7: Stall Interrupt */
+#define USB_INT_ALL 0xFF
+
/* Error Interrupt Status Register and Error Interrupt Enable Register (8-bit) */
#define USB_ERRSTAT_PIDERR (1 << 0) /* Bit 0: This bit is set when the PID check field fails */
@@ -228,6 +230,8 @@
/* Bit 6: Reserved */
#define USB_ERRSTAT_BTSERR (1 << 7) /* Bit 7: Bit stuff error is detected */
+#define USB_EINT_ALL 0xBF
+
/* Status Register (8-bit) */
/* Bits 0-1: Reserved */
@@ -259,6 +263,7 @@
#define USB_BDTPAGE1_MASK (0x7f << USB_BDTPAGE1_SHIFT)
/* Frame Number Register Low (8-bit, bits 0-7 of the 11 bit frame number) */
+#define USB_FRMNUML_MASK 0xFF
/* Frame Number Register High (8-bit) */
/* Bits 3-7: Reserved */
#define USB_FRMNUMH_SHIFT (0) /* Bits 0-2: Bits 8-10 of the 11-bit frame number */
@@ -313,9 +318,50 @@
#define USB_USBTRC0_SYNC_DET (1 << 1) /* Bit 1: Synchronous USB Interrupt Detect */
#define USB_USBTRC0_RESUME_INT (1 << 0) /* Bit 0: USB Asynchronous Interrupt */
-/********************************************************************************************
+/* Buffer Descriptor Table (BDT) ****************************************************/
+/* Offset 0: On write (software->hardware) */
+
+#define USB_BDT_STATUS_MASK 0xfc /* Bits 2-7: Status bits */
+#define USB_BDT_BSTALL (1 << 2) /* Bit 2: Buffer Stall Enable bit */
+#define USB_BDT_DTS (1 << 3) /* Bit 3: Data Toggle Synchronization Enable bit */
+#define USB_BDT_NINC (1 << 4) /* Bit 4: DMA Address Increment Disable bit */
+#define USB_BDT_KEEP (1 << 5) /* Bit 5: BD Keep Enable bit */
+#define USB_BDT_DATA01 (1 << 6) /* Bit 6: Data Toggle Packet bit */
+#define USB_BDT_UOWN (1 << 7) /* Bit 7: USB Own bit */
+#define USB_BDT_BYTECOUNT_SHIFT (16) /* Bits 16-25: Byte Count bits */
+#define USB_BDT_BYTECOUNT_MASK (0x3ff << USB_BDT_BYTECOUNT_SHIFT)
+
+#define USB_BDT_DATA0 0 /* DATA0 packet expected next */
+#define USB_BDT_DATA1 USB_BDT_DATA01 /* DATA1 packet expected next */
+#define USB_BDT_COWN 0 /* CPU owns the descriptor */
+
+/* Offset 0: On read (hardware->software) */
+
+#define USB_BDT_PID_SHIFT (2) /* Bits 2-5: Packet Identifier bits */
+#define USB_BDT_PID_MASK (15 << USB_BDT_PID_SHIFT)
+ /* Bit 7: USB Own bit (same) */
+ /* Bits 16-25: Byte Count bits (same) */
+
+/* Offset 4: BUFFER_ADDRESS, 32-bit Buffer Address bits */
+
+#define USB_BDT_BYTES_SIZE 8 /* Eight bytes per BDT */
+#define USB_BDT_WORD_SIZE 2 /* Two 32-bit words per BDT */
+#define USB_NBDTS_PER_EP 4 /* Number of BDTS per endpoint: IN/OUT and EVEN/ODD */
+
+/************************************************************************************
* Public Types
- ********************************************************************************************/
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* Buffer Descriptor Status Register layout. */
+
+struct usbotg_bdtentry_s
+{
+ uint32_t status; /* Status, byte count, and PID */
+ uint8_t *addr; /* Buffer address */
+};
+#endif
/********************************************************************************************
* Public Data
@@ -325,4 +371,9 @@
* Public Functions
********************************************************************************************/
+struct usbdev_s;
+int kinetis_usbpullup(FAR struct usbdev_s *dev, bool enable);
+void kinetis_usbsuspend(FAR struct usbdev_s *dev, bool resume);
+void khci_usbattach(void);
+
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_USBOTG_H */
--
GitLab
From 983ac18c51cd475d11ca4c66baf26f56fc28997d Mon Sep 17 00:00:00 2001
From: kfazz
Date: Mon, 6 Jun 2016 14:00:02 -0400
Subject: [PATCH 074/400] Teensy 3.x usb support and example configuration
---
configs/teensy-3.x/src/Makefile | 3 +
configs/teensy-3.x/src/k20_appinit.c | 6 +
configs/teensy-3.x/src/k20_usbdev.c | 133 ++++
configs/teensy-3.x/usbnsh/.config | 989 +++++++++++++++++++++++++++
configs/teensy-3.x/usbnsh/Make.defs | 117 ++++
configs/teensy-3.x/usbnsh/defconfig | 989 +++++++++++++++++++++++++++
configs/teensy-3.x/usbnsh/setenv.sh | 80 +++
7 files changed, 2317 insertions(+)
create mode 100644 configs/teensy-3.x/src/k20_usbdev.c
create mode 100644 configs/teensy-3.x/usbnsh/.config
create mode 100644 configs/teensy-3.x/usbnsh/Make.defs
create mode 100644 configs/teensy-3.x/usbnsh/defconfig
create mode 100755 configs/teensy-3.x/usbnsh/setenv.sh
diff --git a/configs/teensy-3.x/src/Makefile b/configs/teensy-3.x/src/Makefile
index ad839632dd..ff73a6953a 100644
--- a/configs/teensy-3.x/src/Makefile
+++ b/configs/teensy-3.x/src/Makefile
@@ -43,6 +43,9 @@ CSRCS += k20_autoleds.c
else
CSRCS += k20_userleds.c
endif
+ifeq ($(CONFIG_KINETIS_USBOTG),y)
+CSRCS += k20_usbdev.c
+endif
ifeq ($(CONFIG_LIB_BOARDCTL),y)
CSRCS += k20_appinit.c
diff --git a/configs/teensy-3.x/src/k20_appinit.c b/configs/teensy-3.x/src/k20_appinit.c
index a66f7a38b0..8512a35d33 100644
--- a/configs/teensy-3.x/src/k20_appinit.c
+++ b/configs/teensy-3.x/src/k20_appinit.c
@@ -74,5 +74,11 @@
int board_app_initialize(uintptr_t arg)
{
+#ifdef CONFIG_USBDEV
+ /* Teensy is powered from usb and (bug?) only boots from being programmed,
+ * so if usb is compiled in signal the controller driver that we're attached now.
+ */
+ khci_usbattach();
+#endif
return OK;
}
diff --git a/configs/teensy-3.x/src/k20_usbdev.c b/configs/teensy-3.x/src/k20_usbdev.c
new file mode 100644
index 0000000000..a2b3c20ddf
--- /dev/null
+++ b/configs/teensy-3.x/src/k20_usbdev.c
@@ -0,0 +1,133 @@
+/************************************************************************************
+ * configs/teensy-3.x/src/k20_usbdev.c
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "up_arch.h"
+#include "kinetis.h"
+#include "kinetis_usbotg.h"
+#include "kinetis_sim.h"
+#include "teensy-3x.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+#define khci_getreg(addr) getreg8(addr)
+#define khci_putreg(val,addr) putreg8(val,addr)
+#define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1)
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: kinetis_usbinitialize
+ *
+ * Description:
+ * Called to setup USB-related GPIO pins for the KwikStik-K40 board.
+ *
+ ************************************************************************************/
+
+void kinetis_usbinitialize(void)
+{
+ uint32_t regval;
+
+// khci_usbattach();
+}
+
+/************************************************************************************
+ * Name: kinetis_usbpullup
+ *
+ * Description:
+ * If USB is supported and the board supports a pullup via GPIO (for USB software
+ * connect and disconnect), then the board software must provide kinetis_pullup.
+ * See include/nuttx/usb/usbdev.h for additional description of this method.
+ * Alternatively, if no pull-up GPIO the following EXTERN can be redefined to be
+ * NULL.
+ *
+ ************************************************************************************/
+
+int kinetis_usbpullup(FAR struct usbdev_s *dev, bool enable)
+{
+ usbtrace(TRACE_DEVPULLUP, (uint16_t)enable);
+ uint32_t regval;
+if (enable)
+khci_putreg(USB_CONTROL_DPPULLUPNONOTG, KINETIS_USB0_CONTROL);
+else
+khci_putreg(0,KINETIS_USB0_CONTROL);
+#if 0
+ regval = khci_getreg(KINETIS_USB0_OTGCTL);
+ if (enable)
+ regval |= (1<<2);
+ else
+ regval &= ~(1<<2);
+ khci_putreg(regval,KINETIS_USB0_OTGCTL);
+#endif
+
+ return OK;
+}
+
+/************************************************************************************
+ * Name: kinetis_usbsuspend
+ *
+ * Description:
+ * Board logic must provide the kinetis_usbsuspend logic if the USBDEV driver is
+ * used. This function is called whenever the USB enters or leaves suspend mode.
+ * This is an opportunity for the board logic to shutdown clocks, power, etc.
+ * while the USB is suspended.
+ *
+ ************************************************************************************/
+
+void kinetis_usbsuspend(FAR struct usbdev_s *dev, bool resume)
+{
+ ulldbg("resume: %d\n", resume);
+#warning "Missing logic"
+}
diff --git a/configs/teensy-3.x/usbnsh/.config b/configs/teensy-3.x/usbnsh/.config
new file mode 100644
index 0000000000..0f0f54c88e
--- /dev/null
+++ b/configs/teensy-3.x/usbnsh/.config
@@ -0,0 +1,989 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Nuttx/ Configuration
+#
+
+#
+# Build Setup
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_DEFAULT_SMALL is not set
+CONFIG_HOST_LINUX=y
+# CONFIG_HOST_OSX is not set
+# CONFIG_HOST_WINDOWS is not set
+# CONFIG_HOST_OTHER is not set
+
+#
+# Build Configuration
+#
+CONFIG_APPS_DIR="../apps"
+CONFIG_BUILD_FLAT=y
+# CONFIG_BUILD_2PASS is not set
+
+#
+# Binary Output Formats
+#
+# CONFIG_RRLOAD_BINARY is not set
+CONFIG_INTELHEX_BINARY=y
+# CONFIG_MOTOROLA_SREC is not set
+CONFIG_RAW_BINARY=y
+# CONFIG_UBOOT_UIMAGE is not set
+
+#
+# Customize Header Files
+#
+# CONFIG_ARCH_STDINT_H is not set
+# CONFIG_ARCH_STDBOOL_H is not set
+# CONFIG_ARCH_MATH_H is not set
+# CONFIG_ARCH_FLOAT_H is not set
+# CONFIG_ARCH_STDARG_H is not set
+# CONFIG_ARCH_DEBUG_H is not set
+
+#
+# Debug Options
+#
+CONFIG_DEBUG=y
+# CONFIG_ARCH_HAVE_HEAPCHECK is not set
+# CONFIG_DEBUG_VERBOSE is not set
+
+#
+# Subsystem Debug Options
+#
+# CONFIG_DEBUG_BINFMT is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_DEBUG_GRAPHICS is not set
+# CONFIG_DEBUG_LIB is not set
+# CONFIG_DEBUG_MM is not set
+# CONFIG_DEBUG_SCHED is not set
+
+#
+# OS Function Debug Options
+#
+# CONFIG_DEBUG_IRQ is not set
+
+#
+# Driver Debug Options
+#
+# CONFIG_DEBUG_LEDS is not set
+# CONFIG_DEBUG_ANALOG is not set
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_DEBUG_SPI is not set
+# CONFIG_DEBUG_USB is not set
+CONFIG_ARCH_HAVE_STACKCHECK=y
+# CONFIG_STACK_COLORATION is not set
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_ARCH_HAVE_CUSTOMOPT=y
+# CONFIG_DEBUG_NOOPT is not set
+# CONFIG_DEBUG_CUSTOMOPT is not set
+CONFIG_DEBUG_FULLOPT=y
+
+#
+# System Type
+#
+CONFIG_ARCH_ARM=y
+# CONFIG_ARCH_AVR is not set
+# CONFIG_ARCH_HC is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_RGMP is not set
+# CONFIG_ARCH_SH is not set
+# CONFIG_ARCH_SIM is not set
+# CONFIG_ARCH_X86 is not set
+# CONFIG_ARCH_Z16 is not set
+# CONFIG_ARCH_Z80 is not set
+CONFIG_ARCH="arm"
+
+#
+# ARM Options
+#
+# CONFIG_ARCH_CHIP_A1X is not set
+# CONFIG_ARCH_CHIP_C5471 is not set
+# CONFIG_ARCH_CHIP_CALYPSO is not set
+# CONFIG_ARCH_CHIP_DM320 is not set
+# CONFIG_ARCH_CHIP_EFM32 is not set
+# CONFIG_ARCH_CHIP_IMX1 is not set
+# CONFIG_ARCH_CHIP_IMX6 is not set
+CONFIG_ARCH_CHIP_KINETIS=y
+# CONFIG_ARCH_CHIP_KL is not set
+# CONFIG_ARCH_CHIP_LM is not set
+# CONFIG_ARCH_CHIP_TIVA is not set
+# CONFIG_ARCH_CHIP_LPC11XX is not set
+# CONFIG_ARCH_CHIP_LPC17XX is not set
+# CONFIG_ARCH_CHIP_LPC214X is not set
+# CONFIG_ARCH_CHIP_LPC2378 is not set
+# CONFIG_ARCH_CHIP_LPC31XX is not set
+# CONFIG_ARCH_CHIP_LPC43XX is not set
+# CONFIG_ARCH_CHIP_NUC1XX is not set
+# CONFIG_ARCH_CHIP_SAMA5 is not set
+# CONFIG_ARCH_CHIP_SAMD is not set
+# CONFIG_ARCH_CHIP_SAML is not set
+# CONFIG_ARCH_CHIP_SAM34 is not set
+# CONFIG_ARCH_CHIP_SAMV7 is not set
+# CONFIG_ARCH_CHIP_STM32 is not set
+# CONFIG_ARCH_CHIP_STM32F7 is not set
+# CONFIG_ARCH_CHIP_STM32L4 is not set
+# CONFIG_ARCH_CHIP_STR71X is not set
+# CONFIG_ARCH_CHIP_TMS570 is not set
+# CONFIG_ARCH_CHIP_MOXART is not set
+# CONFIG_ARCH_ARM7TDMI is not set
+# CONFIG_ARCH_ARM926EJS is not set
+# CONFIG_ARCH_ARM920T is not set
+# CONFIG_ARCH_CORTEXM0 is not set
+# CONFIG_ARCH_CORTEXM3 is not set
+CONFIG_ARCH_CORTEXM4=y
+# CONFIG_ARCH_CORTEXM7 is not set
+# CONFIG_ARCH_CORTEXA5 is not set
+# CONFIG_ARCH_CORTEXA8 is not set
+# CONFIG_ARCH_CORTEXA9 is not set
+# CONFIG_ARCH_CORTEXR4 is not set
+# CONFIG_ARCH_CORTEXR4F is not set
+# CONFIG_ARCH_CORTEXR5 is not set
+# CONFIG_ARCH_CORTEX5F is not set
+# CONFIG_ARCH_CORTEXR7 is not set
+# CONFIG_ARCH_CORTEXR7F is not set
+CONFIG_ARCH_FAMILY="armv7-m"
+CONFIG_ARCH_CHIP="kinetis"
+# CONFIG_ARMV7M_USEBASEPRI is not set
+CONFIG_ARCH_HAVE_FPU=y
+# CONFIG_ARCH_HAVE_DPFPU is not set
+# CONFIG_ARCH_FPU is not set
+# CONFIG_ARCH_HAVE_TRUSTZONE is not set
+CONFIG_ARM_HAVE_MPU_UNIFIED=y
+# CONFIG_ARM_MPU is not set
+# CONFIG_DEBUG_HARDFAULT is not set
+
+#
+# ARMV7M Configuration Options
+#
+# CONFIG_ARMV7M_HAVE_ICACHE is not set
+# CONFIG_ARMV7M_HAVE_DCACHE is not set
+# CONFIG_ARMV7M_HAVE_ITCM is not set
+# CONFIG_ARMV7M_HAVE_DTCM is not set
+# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
+# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
+# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
+CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y
+# CONFIG_ARMV7M_HAVE_STACKCHECK is not set
+# CONFIG_ARMV7M_ITMSYSLOG is not set
+
+#
+# Kinetis Configuration Options
+#
+# CONFIG_ARCH_CHIP_MK20DN32VLH5 is not set
+# CONFIG_ARCH_CHIP_MK20DX32VLH5 is not set
+# CONFIG_ARCH_CHIP_MK20DN64VLH5 is not set
+# CONFIG_ARCH_CHIP_MK20DX64VLH5 is not set
+# CONFIG_ARCH_CHIP_MK20DN128VLH5 is not set
+# CONFIG_ARCH_CHIP_MK20DX128VLH5 is not set
+# CONFIG_ARCH_CHIP_MK20DX64VLH7 is not set
+# CONFIG_ARCH_CHIP_MK20DX128VLH7 is not set
+CONFIG_ARCH_CHIP_MK20DX256VLH7=y
+# CONFIG_ARCH_CHIP_MK40N512VLQ100 is not set
+# CONFIG_ARCH_CHIP_MK40N512VMD100 is not set
+# CONFIG_ARCH_CHIP_MK40X128VLQ100 is not set
+# CONFIG_ARCH_CHIP_MK40X128VMD100 is not set
+# CONFIG_ARCH_CHIP_MK40X256VLQ100 is not set
+# CONFIG_ARCH_CHIP_MK40X256VMD100 is not set
+# CONFIG_ARCH_CHIP_MK60N256VLQ100 is not set
+# CONFIG_ARCH_CHIP_MK60N256VMD100 is not set
+# CONFIG_ARCH_CHIP_MK60N512VLL100 is not set
+# CONFIG_ARCH_CHIP_MK60N512VLQ100 is not set
+# CONFIG_ARCH_CHIP_MK60N512VMD100 is not set
+# CONFIG_ARCH_CHIP_MK60X256VLQ100 is not set
+# CONFIG_ARCH_CHIP_MK60X256VMD100 is not set
+CONFIG_ARCH_FAMILY_K20=y
+# CONFIG_ARCH_FAMILY_K40 is not set
+# CONFIG_ARCH_FAMILY_K60 is not set
+
+#
+# Kinetis Peripheral Support
+#
+# CONFIG_KINETIS_TRACE is not set
+# CONFIG_KINETIS_FLEXBUS is not set
+CONFIG_KINETIS_UART0=y
+# CONFIG_KINETIS_UART1 is not set
+# CONFIG_KINETIS_UART2 is not set
+# CONFIG_KINETIS_UART3 is not set
+# CONFIG_KINETIS_UART4 is not set
+# CONFIG_KINETIS_UART5 is not set
+# CONFIG_KINETIS_FLEXCAN0 is not set
+# CONFIG_KINETIS_FLEXCAN1 is not set
+# CONFIG_KINETIS_SPI0 is not set
+# CONFIG_KINETIS_SPI1 is not set
+# CONFIG_KINETIS_SPI2 is not set
+# CONFIG_KINETIS_I2C0 is not set
+# CONFIG_KINETIS_I2C1 is not set
+# CONFIG_KINETIS_I2S is not set
+# CONFIG_KINETIS_DAC0 is not set
+# CONFIG_KINETIS_DAC1 is not set
+# CONFIG_KINETIS_ADC0 is not set
+# CONFIG_KINETIS_ADC1 is not set
+# CONFIG_KINETIS_CMP is not set
+# CONFIG_KINETIS_VREF is not set
+# CONFIG_KINETIS_SDHC is not set
+# CONFIG_KINETIS_FTM0 is not set
+# CONFIG_KINETIS_FTM1 is not set
+# CONFIG_KINETIS_FTM2 is not set
+# CONFIG_KINETIS_LPTIMER is not set
+# CONFIG_KINETIS_RTC is not set
+# CONFIG_KINETIS_EWM is not set
+# CONFIG_KINETIS_CMT is not set
+CONFIG_KINETIS_USBOTG=y
+# CONFIG_KINETIS_USBDCD is not set
+# CONFIG_KINETIS_LLWU is not set
+# CONFIG_KINETIS_TSI is not set
+# CONFIG_KINETIS_FTFL is not set
+# CONFIG_KINETIS_DMA is not set
+# CONFIG_KINETIS_CRC is not set
+# CONFIG_KINETIS_PDB is not set
+# CONFIG_KINETIS_PIT is not set
+
+#
+# Kinetis GPIO Interrupt Configuration
+#
+# CONFIG_GPIO_IRQ is not set
+
+#
+# Kinetis UART Configuration
+#
+CONFIG_KINETIS_UARTFIFOS=y
+
+#
+# Architecture Options
+#
+# CONFIG_ARCH_NOINTC is not set
+# CONFIG_ARCH_VECNOTIRQ is not set
+# CONFIG_ARCH_DMA is not set
+CONFIG_ARCH_HAVE_IRQPRIO=y
+# CONFIG_ARCH_L2CACHE is not set
+# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set
+# CONFIG_ARCH_HAVE_ADDRENV is not set
+# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set
+# CONFIG_ARCH_HAVE_MULTICPU is not set
+CONFIG_ARCH_HAVE_VFORK=y
+# CONFIG_ARCH_HAVE_MMU is not set
+CONFIG_ARCH_HAVE_MPU=y
+# CONFIG_ARCH_NAND_HWECC is not set
+# CONFIG_ARCH_HAVE_EXTCLK is not set
+# CONFIG_ARCH_HAVE_POWEROFF is not set
+CONFIG_ARCH_HAVE_RESET=y
+# CONFIG_ARCH_USE_MPU is not set
+# CONFIG_ARCH_IRQPRIO is not set
+CONFIG_ARCH_STACKDUMP=y
+# CONFIG_ARCH_USBDUMP is not set
+# CONFIG_ENDIAN_BIG is not set
+# CONFIG_ARCH_IDLE_CUSTOM is not set
+CONFIG_ARCH_HAVE_RAMFUNCS=y
+CONFIG_ARCH_RAMFUNCS=y
+CONFIG_ARCH_HAVE_RAMVECTORS=y
+# CONFIG_ARCH_RAMVECTORS is not set
+
+#
+# Board Settings
+#
+CONFIG_BOARD_LOOPSPERMSEC=6024
+# CONFIG_ARCH_CALIBRATION is not set
+
+#
+# Interrupt options
+#
+CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
+CONFIG_ARCH_INTERRUPTSTACK=0
+CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y
+# CONFIG_ARCH_HIPRI_INTERRUPT is not set
+
+#
+# Boot options
+#
+# CONFIG_BOOT_RUNFROMEXTSRAM is not set
+CONFIG_BOOT_RUNFROMFLASH=y
+# CONFIG_BOOT_RUNFROMISRAM is not set
+# CONFIG_BOOT_RUNFROMSDRAM is not set
+# CONFIG_BOOT_COPYTORAM is not set
+
+#
+# Boot Memory Configuration
+#
+CONFIG_RAM_START=0x1fff8000
+CONFIG_RAM_SIZE=65536
+# CONFIG_ARCH_HAVE_SDRAM is not set
+
+#
+# Board Selection
+#
+CONFIG_ARCH_BOARD_TEENSY_3X=y
+# CONFIG_ARCH_BOARD_CUSTOM is not set
+CONFIG_ARCH_BOARD="teensy-3.x"
+
+#
+# Common Board Options
+#
+CONFIG_ARCH_HAVE_LEDS=y
+CONFIG_ARCH_LEDS=y
+CONFIG_NSH_MMCSDMINOR=0
+
+#
+# Board-Specific Options
+#
+# CONFIG_TEENSY_3X_OVERCLOCK is not set
+CONFIG_LIB_BOARDCTL=y
+# CONFIG_BOARDCTL_RESET is not set
+# CONFIG_BOARDCTL_UNIQUEID is not set
+CONFIG_BOARDCTL_USBDEVCTRL=y
+# CONFIG_BOARDCTL_TSCTEST is not set
+# CONFIG_BOARDCTL_ADCTEST is not set
+# CONFIG_BOARDCTL_PWMTEST is not set
+# CONFIG_BOARDCTL_GRAPHICS is not set
+# CONFIG_BOARDCTL_IOCTL is not set
+
+#
+# RTOS Features
+#
+CONFIG_DISABLE_OS_API=y
+# CONFIG_DISABLE_POSIX_TIMERS is not set
+# CONFIG_DISABLE_PTHREAD is not set
+# CONFIG_DISABLE_SIGNALS is not set
+# CONFIG_DISABLE_MQUEUE is not set
+# CONFIG_DISABLE_ENVIRON is not set
+
+#
+# Clocks and Timers
+#
+CONFIG_USEC_PER_TICK=10000
+# CONFIG_SYSTEM_TIME64 is not set
+# CONFIG_CLOCK_MONOTONIC is not set
+# CONFIG_JULIAN_TIME is not set
+CONFIG_START_YEAR=2011
+CONFIG_START_MONTH=12
+CONFIG_START_DAY=6
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_PREALLOC_WDOGS=16
+CONFIG_WDOG_INTRESERVE=4
+CONFIG_PREALLOC_TIMERS=4
+
+#
+# Tasks and Scheduling
+#
+# CONFIG_SPINLOCK is not set
+# CONFIG_INIT_NONE is not set
+CONFIG_INIT_ENTRYPOINT=y
+# CONFIG_INIT_FILEPATH is not set
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_RR_INTERVAL=200
+# CONFIG_SCHED_SPORADIC is not set
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_MAX_TASKS=16
+# CONFIG_SCHED_HAVE_PARENT is not set
+CONFIG_SCHED_WAITPID=y
+
+#
+# Pthread Options
+#
+# CONFIG_MUTEX_TYPES is not set
+CONFIG_NPTHREAD_KEYS=4
+
+#
+# Performance Monitoring
+#
+# CONFIG_SCHED_CPULOAD is not set
+# CONFIG_SCHED_INSTRUMENTATION is not set
+
+#
+# Files and I/O
+#
+CONFIG_DEV_CONSOLE=y
+# CONFIG_FDCLONE_DISABLE is not set
+# CONFIG_FDCLONE_STDIO is not set
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NAME_MAX=32
+# CONFIG_PRIORITY_INHERITANCE is not set
+
+#
+# RTOS hooks
+#
+# CONFIG_BOARD_INITIALIZE is not set
+# CONFIG_SCHED_STARTHOOK is not set
+# CONFIG_SCHED_ATEXIT is not set
+# CONFIG_SCHED_ONEXIT is not set
+
+#
+# Signal Numbers
+#
+CONFIG_SIG_SIGUSR1=1
+CONFIG_SIG_SIGUSR2=2
+CONFIG_SIG_SIGALARM=3
+CONFIG_SIG_SIGCONDTIMEDOUT=16
+
+#
+# POSIX Message Queue Options
+#
+CONFIG_PREALLOC_MQ_MSGS=4
+CONFIG_MQ_MAXMSGSIZE=32
+# CONFIG_MODULE is not set
+
+#
+# Work queue support
+#
+# CONFIG_SCHED_WORKQUEUE is not set
+# CONFIG_SCHED_HPWORK is not set
+# CONFIG_SCHED_LPWORK is not set
+
+#
+# Stack and heap information
+#
+CONFIG_IDLETHREAD_STACKSIZE=1024
+CONFIG_USERMAIN_STACKSIZE=2048
+CONFIG_PTHREAD_STACK_MIN=256
+CONFIG_PTHREAD_STACK_DEFAULT=2048
+# CONFIG_LIB_SYSCALL is not set
+
+#
+# Device Drivers
+#
+CONFIG_DISABLE_POLL=y
+CONFIG_DEV_NULL=y
+# CONFIG_DEV_ZERO is not set
+# CONFIG_DEV_LOOP is not set
+
+#
+# Buffering
+#
+# CONFIG_DRVR_WRITEBUFFER is not set
+# CONFIG_DRVR_READAHEAD is not set
+# CONFIG_RAMDISK is not set
+# CONFIG_CAN is not set
+# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set
+# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set
+# CONFIG_PWM is not set
+# CONFIG_ARCH_HAVE_I2CRESET is not set
+# CONFIG_I2C is not set
+CONFIG_SPI=y
+# CONFIG_SPI_SLAVE is not set
+CONFIG_SPI_EXCHANGE=y
+# CONFIG_SPI_CMDDATA is not set
+# CONFIG_SPI_CALLBACK is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_HWFEATURES is not set
+# CONFIG_SPI_CRCGENERATION is not set
+# CONFIG_I2S is not set
+
+#
+# Timer Driver Support
+#
+# CONFIG_TIMER is not set
+# CONFIG_RTC is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_ANALOG is not set
+# CONFIG_AUDIO_DEVICES is not set
+# CONFIG_VIDEO_DEVICES is not set
+# CONFIG_BCH is not set
+# CONFIG_INPUT is not set
+# CONFIG_IOEXPANDER is not set
+# CONFIG_LCD is not set
+
+#
+# LED Support
+#
+# CONFIG_USERLED is not set
+# CONFIG_RGBLED is not set
+# CONFIG_PCA9635PW is not set
+# CONFIG_MMCSD is not set
+# CONFIG_MODEM is not set
+# CONFIG_MTD is not set
+# CONFIG_EEPROM is not set
+# CONFIG_PIPES is not set
+# CONFIG_PM is not set
+# CONFIG_POWER is not set
+# CONFIG_SENSORS is not set
+# CONFIG_SERCOMM_CONSOLE is not set
+CONFIG_SERIAL=y
+# CONFIG_DEV_LOWCONSOLE is not set
+CONFIG_SERIAL_REMOVABLE=y
+# CONFIG_16550_UART is not set
+# CONFIG_ARCH_HAVE_UART is not set
+CONFIG_ARCH_HAVE_UART0=y
+# CONFIG_ARCH_HAVE_UART1 is not set
+# CONFIG_ARCH_HAVE_UART2 is not set
+# CONFIG_ARCH_HAVE_UART3 is not set
+# CONFIG_ARCH_HAVE_UART4 is not set
+# CONFIG_ARCH_HAVE_UART5 is not set
+# CONFIG_ARCH_HAVE_UART6 is not set
+# CONFIG_ARCH_HAVE_UART7 is not set
+# CONFIG_ARCH_HAVE_UART8 is not set
+# CONFIG_ARCH_HAVE_SCI0 is not set
+# CONFIG_ARCH_HAVE_SCI1 is not set
+# CONFIG_ARCH_HAVE_USART0 is not set
+# CONFIG_ARCH_HAVE_USART1 is not set
+# CONFIG_ARCH_HAVE_USART2 is not set
+# CONFIG_ARCH_HAVE_USART3 is not set
+# CONFIG_ARCH_HAVE_USART4 is not set
+# CONFIG_ARCH_HAVE_USART5 is not set
+# CONFIG_ARCH_HAVE_USART6 is not set
+# CONFIG_ARCH_HAVE_USART7 is not set
+# CONFIG_ARCH_HAVE_USART8 is not set
+# CONFIG_ARCH_HAVE_OTHER_UART is not set
+
+#
+# USART Configuration
+#
+CONFIG_MCU_SERIAL=y
+CONFIG_STANDARD_SERIAL=y
+# CONFIG_SERIAL_IFLOWCONTROL is not set
+# CONFIG_SERIAL_OFLOWCONTROL is not set
+# CONFIG_SERIAL_DMA is not set
+# CONFIG_SERIAL_TIOCSERGSTRUCT is not set
+# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set
+CONFIG_UART0_SERIAL_CONSOLE=y
+# CONFIG_OTHER_SERIAL_CONSOLE is not set
+# CONFIG_NO_SERIAL_CONSOLE is not set
+
+#
+# UART0 Configuration
+#
+CONFIG_UART0_RXBUFSIZE=256
+CONFIG_UART0_TXBUFSIZE=256
+CONFIG_UART0_BAUD=115200
+CONFIG_UART0_BITS=8
+CONFIG_UART0_PARITY=0
+CONFIG_UART0_2STOP=0
+# CONFIG_UART0_IFLOWCONTROL is not set
+# CONFIG_UART0_OFLOWCONTROL is not set
+# CONFIG_UART0_DMA is not set
+CONFIG_USBDEV=y
+
+#
+# USB Device Controller Driver Options
+#
+# CONFIG_USBDEV_ISOCHRONOUS is not set
+CONFIG_USBDEV_DUALSPEED=y
+CONFIG_USBDEV_SELFPOWERED=y
+# CONFIG_USBDEV_BUSPOWERED is not set
+CONFIG_USBDEV_MAXPOWER=100
+# CONFIG_USBDEV_DMA is not set
+# CONFIG_ARCH_USBDEV_STALLQUEUE is not set
+CONFIG_USBDEV_TRACE=y
+CONFIG_USBDEV_TRACE_NRECORDS=128
+CONFIG_USBDEV_TRACE_INITIALIDSET=y
+
+#
+# USB Device Class Driver Options
+#
+# CONFIG_USBDEV_COMPOSITE is not set
+# CONFIG_PL2303 is not set
+CONFIG_CDCACM=y
+# CONFIG_CDCACM_CONSOLE is not set
+# CONFIG_CDCACM_IFLOWCONTROL is not set
+CONFIG_CDCACM_EP0MAXPACKET=64
+CONFIG_CDCACM_EPINTIN=1
+CONFIG_CDCACM_EPINTIN_FSSIZE=64
+CONFIG_CDCACM_EPINTIN_HSSIZE=64
+CONFIG_CDCACM_EPBULKOUT=3
+CONFIG_CDCACM_EPBULKOUT_FSSIZE=64
+CONFIG_CDCACM_EPBULKOUT_HSSIZE=512
+CONFIG_CDCACM_EPBULKIN=2
+CONFIG_CDCACM_EPBULKIN_FSSIZE=64
+CONFIG_CDCACM_EPBULKIN_HSSIZE=512
+CONFIG_CDCACM_NRDREQS=4
+CONFIG_CDCACM_NWRREQS=4
+CONFIG_CDCACM_BULKIN_REQLEN=768
+CONFIG_CDCACM_RXBUFSIZE=513
+CONFIG_CDCACM_TXBUFSIZE=769
+CONFIG_CDCACM_VENDORID=0x0525
+CONFIG_CDCACM_PRODUCTID=0xa4a7
+CONFIG_CDCACM_VENDORSTR="NuttX"
+CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial"
+# CONFIG_USBMSC is not set
+# CONFIG_USBHOST is not set
+# CONFIG_DRIVERS_WIRELESS is not set
+
+#
+# System Logging Device Options
+#
+
+#
+# System Logging
+#
+# CONFIG_RAMLOG is not set
+# CONFIG_SYSLOG_CONSOLE is not set
+
+#
+# Networking Support
+#
+# CONFIG_ARCH_HAVE_NET is not set
+# CONFIG_ARCH_HAVE_PHY is not set
+# CONFIG_NET is not set
+
+#
+# Crypto API
+#
+# CONFIG_CRYPTO is not set
+
+#
+# File Systems
+#
+
+#
+# File system configuration
+#
+# CONFIG_DISABLE_MOUNTPOINT is not set
+# CONFIG_FS_AUTOMOUNTER is not set
+# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set
+# CONFIG_FS_READABLE is not set
+# CONFIG_FS_WRITABLE is not set
+# CONFIG_FS_NAMED_SEMAPHORES is not set
+CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
+# CONFIG_FS_RAMMAP is not set
+# CONFIG_FS_FAT is not set
+# CONFIG_FS_NXFFS is not set
+# CONFIG_FS_ROMFS is not set
+# CONFIG_FS_TMPFS is not set
+# CONFIG_FS_SMARTFS is not set
+# CONFIG_FS_BINFS is not set
+# CONFIG_FS_PROCFS is not set
+# CONFIG_FS_UNIONFS is not set
+
+#
+# System Logging
+#
+# CONFIG_SYSLOG is not set
+# CONFIG_SYSLOG_TIMESTAMP is not set
+
+#
+# Graphics Support
+#
+# CONFIG_NX is not set
+
+#
+# Memory Management
+#
+# CONFIG_MM_SMALL is not set
+CONFIG_MM_REGIONS=1
+# CONFIG_ARCH_HAVE_HEAP2 is not set
+# CONFIG_GRAN is not set
+
+#
+# Audio Support
+#
+# CONFIG_AUDIO is not set
+
+#
+# Wireless Support
+#
+# CONFIG_WIRELESS is not set
+
+#
+# Binary Loader
+#
+# CONFIG_BINFMT_DISABLE is not set
+# CONFIG_BINFMT_EXEPATH is not set
+# CONFIG_NXFLAT is not set
+# CONFIG_ELF is not set
+CONFIG_BUILTIN=y
+# CONFIG_PIC is not set
+# CONFIG_SYMTAB_ORDEREDBYNAME is not set
+
+#
+# Library Routines
+#
+
+#
+# Standard C Library Options
+#
+CONFIG_STDIO_BUFFER_SIZE=64
+CONFIG_STDIO_LINEBUFFER=y
+CONFIG_NUNGET_CHARS=2
+CONFIG_LIB_HOMEDIR="/"
+# CONFIG_LIBM is not set
+# CONFIG_NOPRINTF_FIELDWIDTH is not set
+# CONFIG_LIBC_FLOATINGPOINT is not set
+CONFIG_LIBC_LONG_LONG=y
+# CONFIG_LIBC_IOCTL_VARIADIC is not set
+CONFIG_LIB_RAND_ORDER=1
+# CONFIG_EOL_IS_CR is not set
+# CONFIG_EOL_IS_LF is not set
+# CONFIG_EOL_IS_BOTH_CRLF is not set
+CONFIG_EOL_IS_EITHER_CRLF=y
+# CONFIG_LIBC_EXECFUNCS is not set
+CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024
+CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048
+# CONFIG_LIBC_STRERROR is not set
+# CONFIG_LIBC_PERROR_STDOUT is not set
+CONFIG_ARCH_LOWPUTC=y
+# CONFIG_LIBC_LOCALTIME is not set
+# CONFIG_TIME_EXTENDED is not set
+CONFIG_LIB_SENDFILE_BUFSIZE=512
+# CONFIG_ARCH_ROMGETC is not set
+# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
+CONFIG_ARCH_HAVE_TLS=y
+# CONFIG_TLS is not set
+# CONFIG_LIBC_NETDB is not set
+
+#
+# Non-standard Library Support
+#
+# CONFIG_LIB_KBDCODEC is not set
+# CONFIG_LIB_SLCDCODEC is not set
+
+#
+# Basic CXX Support
+#
+# CONFIG_C99_BOOL8 is not set
+# CONFIG_HAVE_CXX is not set
+
+#
+# Application Configuration
+#
+
+#
+# Built-In Applications
+#
+CONFIG_BUILTIN_PROXY_STACKSIZE=1024
+
+#
+# CAN Utilities
+#
+
+#
+# Examples
+#
+# CONFIG_EXAMPLES_CHAT is not set
+# CONFIG_EXAMPLES_CONFIGDATA is not set
+# CONFIG_EXAMPLES_CPUHOG is not set
+# CONFIG_EXAMPLES_DHCPD is not set
+# CONFIG_EXAMPLES_ELF is not set
+# CONFIG_EXAMPLES_FTPC is not set
+# CONFIG_EXAMPLES_FTPD is not set
+# CONFIG_EXAMPLES_HELLO is not set
+# CONFIG_EXAMPLES_JSON is not set
+# CONFIG_EXAMPLES_HIDKBD is not set
+# CONFIG_EXAMPLES_KEYPADTEST is not set
+# CONFIG_EXAMPLES_IGMP is not set
+# CONFIG_EXAMPLES_MEDIA is not set
+# CONFIG_EXAMPLES_MM is not set
+# CONFIG_EXAMPLES_MODBUS is not set
+# CONFIG_EXAMPLES_MOUNT is not set
+# CONFIG_EXAMPLES_NRF24L01TERM is not set
+CONFIG_EXAMPLES_NSH=y
+# CONFIG_EXAMPLES_NULL is not set
+# CONFIG_EXAMPLES_NX is not set
+# CONFIG_EXAMPLES_NXTERM is not set
+# CONFIG_EXAMPLES_NXFFS is not set
+# CONFIG_EXAMPLES_NXHELLO is not set
+# CONFIG_EXAMPLES_NXIMAGE is not set
+# CONFIG_EXAMPLES_NXLINES is not set
+# CONFIG_EXAMPLES_NXTEXT is not set
+# CONFIG_EXAMPLES_OSTEST is not set
+# CONFIG_EXAMPLES_PCA9635 is not set
+# CONFIG_EXAMPLES_PIPE is not set
+# CONFIG_EXAMPLES_PPPD is not set
+# CONFIG_EXAMPLES_POSIXSPAWN is not set
+# CONFIG_EXAMPLES_RGBLED is not set
+# CONFIG_EXAMPLES_RGMP is not set
+# CONFIG_EXAMPLES_SENDMAIL is not set
+# CONFIG_EXAMPLES_SERIALBLASTER is not set
+# CONFIG_EXAMPLES_SERIALRX is not set
+# CONFIG_EXAMPLES_SERLOOP is not set
+# CONFIG_EXAMPLES_SLCD is not set
+# CONFIG_EXAMPLES_SMART_TEST is not set
+# CONFIG_EXAMPLES_SMART is not set
+# CONFIG_EXAMPLES_SMP is not set
+# CONFIG_EXAMPLES_TCPECHO is not set
+# CONFIG_EXAMPLES_TELNETD is not set
+# CONFIG_EXAMPLES_TIFF is not set
+# CONFIG_EXAMPLES_TOUCHSCREEN is not set
+# CONFIG_EXAMPLES_WEBSERVER is not set
+# CONFIG_EXAMPLES_USBSERIAL is not set
+# CONFIG_EXAMPLES_USBTERM is not set
+# CONFIG_EXAMPLES_WATCHDOG is not set
+
+#
+# File System Utilities
+#
+# CONFIG_FSUTILS_INIFILE is not set
+
+#
+# GPS Utilities
+#
+# CONFIG_GPSUTILS_MINMEA_LIB is not set
+
+#
+# Graphics Support
+#
+# CONFIG_TIFF is not set
+# CONFIG_GRAPHICS_TRAVELER is not set
+
+#
+# Interpreters
+#
+# CONFIG_INTERPRETERS_FICL is not set
+# CONFIG_INTERPRETERS_PCODE is not set
+# CONFIG_INTERPRETERS_MICROPYTHON is not set
+
+#
+# FreeModBus
+#
+# CONFIG_MODBUS is not set
+
+#
+# Network Utilities
+#
+# CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_FTPC is not set
+# CONFIG_NETUTILS_JSON is not set
+# CONFIG_NETUTILS_SMTP is not set
+
+#
+# NSH Library
+#
+CONFIG_NSH_LIBRARY=y
+# CONFIG_NSH_MOTD is not set
+
+#
+# Command Line Configuration
+#
+CONFIG_NSH_READLINE=y
+# CONFIG_NSH_CLE is not set
+CONFIG_NSH_LINELEN=64
+# CONFIG_NSH_DISABLE_SEMICOLON is not set
+# CONFIG_NSH_CMDPARMS is not set
+CONFIG_NSH_MAXARGUMENTS=6
+# CONFIG_NSH_ARGCAT is not set
+CONFIG_NSH_NESTDEPTH=3
+# CONFIG_NSH_DISABLEBG is not set
+CONFIG_NSH_BUILTIN_APPS=y
+
+#
+# Disable Individual commands
+#
+# CONFIG_NSH_DISABLE_ADDROUTE is not set
+# CONFIG_NSH_DISABLE_BASENAME is not set
+# CONFIG_NSH_DISABLE_CAT is not set
+# CONFIG_NSH_DISABLE_CD is not set
+# CONFIG_NSH_DISABLE_CP is not set
+# CONFIG_NSH_DISABLE_CMP is not set
+CONFIG_NSH_DISABLE_DATE=y
+# CONFIG_NSH_DISABLE_DD is not set
+# CONFIG_NSH_DISABLE_DF is not set
+# CONFIG_NSH_DISABLE_DELROUTE is not set
+# CONFIG_NSH_DISABLE_DIRNAME is not set
+# CONFIG_NSH_DISABLE_ECHO is not set
+# CONFIG_NSH_DISABLE_EXEC is not set
+# CONFIG_NSH_DISABLE_EXIT is not set
+# CONFIG_NSH_DISABLE_FREE is not set
+# CONFIG_NSH_DISABLE_GET is not set
+# CONFIG_NSH_DISABLE_HELP is not set
+# CONFIG_NSH_DISABLE_HEXDUMP is not set
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+# CONFIG_NSH_DISABLE_KILL is not set
+# CONFIG_NSH_DISABLE_LOSETUP is not set
+CONFIG_NSH_DISABLE_LOSMART=y
+# CONFIG_NSH_DISABLE_LS is not set
+# CONFIG_NSH_DISABLE_MB is not set
+# CONFIG_NSH_DISABLE_MKDIR is not set
+# CONFIG_NSH_DISABLE_MKFIFO is not set
+# CONFIG_NSH_DISABLE_MKRD is not set
+# CONFIG_NSH_DISABLE_MH is not set
+# CONFIG_NSH_DISABLE_MOUNT is not set
+# CONFIG_NSH_DISABLE_MV is not set
+# CONFIG_NSH_DISABLE_MW is not set
+# CONFIG_NSH_DISABLE_PS is not set
+# CONFIG_NSH_DISABLE_PUT is not set
+# CONFIG_NSH_DISABLE_PWD is not set
+# CONFIG_NSH_DISABLE_RM is not set
+# CONFIG_NSH_DISABLE_RMDIR is not set
+# CONFIG_NSH_DISABLE_SET is not set
+# CONFIG_NSH_DISABLE_SH is not set
+# CONFIG_NSH_DISABLE_SLEEP is not set
+# CONFIG_NSH_DISABLE_TIME is not set
+# CONFIG_NSH_DISABLE_TEST is not set
+# CONFIG_NSH_DISABLE_UMOUNT is not set
+# CONFIG_NSH_DISABLE_UNAME is not set
+# CONFIG_NSH_DISABLE_UNSET is not set
+# CONFIG_NSH_DISABLE_USLEEP is not set
+# CONFIG_NSH_DISABLE_WGET is not set
+# CONFIG_NSH_DISABLE_XD is not set
+
+#
+# Configure Command Options
+#
+# CONFIG_NSH_CMDOPT_DF_H is not set
+CONFIG_NSH_CODECS_BUFSIZE=128
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+CONFIG_NSH_FILEIOSIZE=512
+
+#
+# Scripting Support
+#
+# CONFIG_NSH_DISABLESCRIPT is not set
+# CONFIG_NSH_DISABLE_ITEF is not set
+# CONFIG_NSH_DISABLE_LOOPS is not set
+
+#
+# Console Configuration
+#
+CONFIG_NSH_CONSOLE=y
+CONFIG_NSH_USBCONSOLE=y
+CONFIG_NSH_USBCONDEV="/dev/ttyACM0"
+CONFIG_USBDEV_MINOR=0
+
+#
+# USB Device Trace Support
+#
+# CONFIG_NSH_USBDEV_TRACE is not set
+CONFIG_NSH_ARCHINIT=y
+# CONFIG_NSH_LOGIN is not set
+# CONFIG_NSH_CONSOLE_LOGIN is not set
+
+#
+# NxWidgets/NxWM
+#
+
+#
+# Platform-specific Support
+#
+# CONFIG_PLATFORM_CONFIGDATA is not set
+
+#
+# System Libraries and NSH Add-Ons
+#
+# CONFIG_SYSTEM_FREE is not set
+# CONFIG_SYSTEM_CLE is not set
+# CONFIG_SYSTEM_CUTERM is not set
+# CONFIG_SYSTEM_INSTALL is not set
+# CONFIG_SYSTEM_HEX2BIN is not set
+CONFIG_SYSTEM_HEXED=y
+CONFIG_SYSTEM_HEXED_STACKSIZE=2048
+CONFIG_SYSTEM_HEXED_PRIORITY=100
+CONFIG_SYSTEM_RAMTEST=y
+CONFIG_READLINE_HAVE_EXTMATCH=y
+CONFIG_SYSTEM_READLINE=y
+CONFIG_READLINE_ECHO=y
+CONFIG_READLINE_TABCOMPLETION=y
+CONFIG_READLINE_MAX_BUILTINS=64
+CONFIG_READLINE_MAX_EXTCMDS=64
+CONFIG_READLINE_CMD_HISTORY=y
+CONFIG_READLINE_CMD_HISTORY_LINELEN=80
+CONFIG_READLINE_CMD_HISTORY_LEN=16
+# CONFIG_SYSTEM_SDCARD is not set
+# CONFIG_SYSTEM_SUDOKU is not set
+# CONFIG_SYSTEM_VI is not set
+CONFIG_SYSTEM_CDCACM=y
+CONFIG_SYSTEM_CDCACM_DEVMINOR=0
+# CONFIG_SYSTEM_CDCACM_TRACEINIT is not set
+# CONFIG_SYSTEM_CDCACM_TRACECLASS is not set
+# CONFIG_SYSTEM_CDCACM_TRACETRANSFERS is not set
+# CONFIG_SYSTEM_CDCACM_TRACECONTROLLER is not set
+# CONFIG_SYSTEM_CDCACM_TRACEINTERRUPTS is not set
+# CONFIG_SYSTEM_UBLOXMODEM is not set
+CONFIG_SYSTEM_USBMONITOR=y
+CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048
+CONFIG_SYSTEM_USBMONITOR_PRIORITY=50
+CONFIG_SYSTEM_USBMONITOR_INTERVAL=2
+CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y
+CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y
+CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y
+CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y
+CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y
+# CONFIG_SYSTEM_ZMODEM is not set
diff --git a/configs/teensy-3.x/usbnsh/Make.defs b/configs/teensy-3.x/usbnsh/Make.defs
new file mode 100644
index 0000000000..597d2e8cf3
--- /dev/null
+++ b/configs/teensy-3.x/usbnsh/Make.defs
@@ -0,0 +1,117 @@
+############################################################################
+# configs/teensy-3.1/nsh/Make.defs
+#
+# Copyright (C) 2015 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
+
+ifeq ($(CONFIG_ARCH_CHIP_MK20DX256VLH7),y)
+ LDSCRIPT = mk20dx256vlh7.ld
+else ifeq ($(CONFIG_ARCH_CHIP_MK20DX128VLH5),y)
+ LDSCRIPT = mk20dx128vlh5.ld
+endif
+
+ifeq ($(WINTOOL),y)
+ # Windows-native toolchains
+ DIRLINK = $(TOPDIR)/tools/copydir.sh
+ DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+ MKDEP = $(TOPDIR)/tools/mkwindeps.sh
+ ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+ ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+ ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
+else
+ # Linux/Cygwin-native toolchain
+ MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
+ ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+ ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+ ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
+endif
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+AR = $(ARCROSSDEV)ar rcs
+NM = $(ARCROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ ARCHOPTIMIZATION = -g
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+ ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
+ARCHWARNINGSXX = -Wall -Wshadow -Wundef
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+ASMEXT = .S
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-nuttx-elf-)
+ LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ LDFLAGS += -g
+endif
+
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
+HOSTLDFLAGS =
+
diff --git a/configs/teensy-3.x/usbnsh/defconfig b/configs/teensy-3.x/usbnsh/defconfig
new file mode 100644
index 0000000000..0f0f54c88e
--- /dev/null
+++ b/configs/teensy-3.x/usbnsh/defconfig
@@ -0,0 +1,989 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Nuttx/ Configuration
+#
+
+#
+# Build Setup
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_DEFAULT_SMALL is not set
+CONFIG_HOST_LINUX=y
+# CONFIG_HOST_OSX is not set
+# CONFIG_HOST_WINDOWS is not set
+# CONFIG_HOST_OTHER is not set
+
+#
+# Build Configuration
+#
+CONFIG_APPS_DIR="../apps"
+CONFIG_BUILD_FLAT=y
+# CONFIG_BUILD_2PASS is not set
+
+#
+# Binary Output Formats
+#
+# CONFIG_RRLOAD_BINARY is not set
+CONFIG_INTELHEX_BINARY=y
+# CONFIG_MOTOROLA_SREC is not set
+CONFIG_RAW_BINARY=y
+# CONFIG_UBOOT_UIMAGE is not set
+
+#
+# Customize Header Files
+#
+# CONFIG_ARCH_STDINT_H is not set
+# CONFIG_ARCH_STDBOOL_H is not set
+# CONFIG_ARCH_MATH_H is not set
+# CONFIG_ARCH_FLOAT_H is not set
+# CONFIG_ARCH_STDARG_H is not set
+# CONFIG_ARCH_DEBUG_H is not set
+
+#
+# Debug Options
+#
+CONFIG_DEBUG=y
+# CONFIG_ARCH_HAVE_HEAPCHECK is not set
+# CONFIG_DEBUG_VERBOSE is not set
+
+#
+# Subsystem Debug Options
+#
+# CONFIG_DEBUG_BINFMT is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_DEBUG_GRAPHICS is not set
+# CONFIG_DEBUG_LIB is not set
+# CONFIG_DEBUG_MM is not set
+# CONFIG_DEBUG_SCHED is not set
+
+#
+# OS Function Debug Options
+#
+# CONFIG_DEBUG_IRQ is not set
+
+#
+# Driver Debug Options
+#
+# CONFIG_DEBUG_LEDS is not set
+# CONFIG_DEBUG_ANALOG is not set
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_DEBUG_SPI is not set
+# CONFIG_DEBUG_USB is not set
+CONFIG_ARCH_HAVE_STACKCHECK=y
+# CONFIG_STACK_COLORATION is not set
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_ARCH_HAVE_CUSTOMOPT=y
+# CONFIG_DEBUG_NOOPT is not set
+# CONFIG_DEBUG_CUSTOMOPT is not set
+CONFIG_DEBUG_FULLOPT=y
+
+#
+# System Type
+#
+CONFIG_ARCH_ARM=y
+# CONFIG_ARCH_AVR is not set
+# CONFIG_ARCH_HC is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_RGMP is not set
+# CONFIG_ARCH_SH is not set
+# CONFIG_ARCH_SIM is not set
+# CONFIG_ARCH_X86 is not set
+# CONFIG_ARCH_Z16 is not set
+# CONFIG_ARCH_Z80 is not set
+CONFIG_ARCH="arm"
+
+#
+# ARM Options
+#
+# CONFIG_ARCH_CHIP_A1X is not set
+# CONFIG_ARCH_CHIP_C5471 is not set
+# CONFIG_ARCH_CHIP_CALYPSO is not set
+# CONFIG_ARCH_CHIP_DM320 is not set
+# CONFIG_ARCH_CHIP_EFM32 is not set
+# CONFIG_ARCH_CHIP_IMX1 is not set
+# CONFIG_ARCH_CHIP_IMX6 is not set
+CONFIG_ARCH_CHIP_KINETIS=y
+# CONFIG_ARCH_CHIP_KL is not set
+# CONFIG_ARCH_CHIP_LM is not set
+# CONFIG_ARCH_CHIP_TIVA is not set
+# CONFIG_ARCH_CHIP_LPC11XX is not set
+# CONFIG_ARCH_CHIP_LPC17XX is not set
+# CONFIG_ARCH_CHIP_LPC214X is not set
+# CONFIG_ARCH_CHIP_LPC2378 is not set
+# CONFIG_ARCH_CHIP_LPC31XX is not set
+# CONFIG_ARCH_CHIP_LPC43XX is not set
+# CONFIG_ARCH_CHIP_NUC1XX is not set
+# CONFIG_ARCH_CHIP_SAMA5 is not set
+# CONFIG_ARCH_CHIP_SAMD is not set
+# CONFIG_ARCH_CHIP_SAML is not set
+# CONFIG_ARCH_CHIP_SAM34 is not set
+# CONFIG_ARCH_CHIP_SAMV7 is not set
+# CONFIG_ARCH_CHIP_STM32 is not set
+# CONFIG_ARCH_CHIP_STM32F7 is not set
+# CONFIG_ARCH_CHIP_STM32L4 is not set
+# CONFIG_ARCH_CHIP_STR71X is not set
+# CONFIG_ARCH_CHIP_TMS570 is not set
+# CONFIG_ARCH_CHIP_MOXART is not set
+# CONFIG_ARCH_ARM7TDMI is not set
+# CONFIG_ARCH_ARM926EJS is not set
+# CONFIG_ARCH_ARM920T is not set
+# CONFIG_ARCH_CORTEXM0 is not set
+# CONFIG_ARCH_CORTEXM3 is not set
+CONFIG_ARCH_CORTEXM4=y
+# CONFIG_ARCH_CORTEXM7 is not set
+# CONFIG_ARCH_CORTEXA5 is not set
+# CONFIG_ARCH_CORTEXA8 is not set
+# CONFIG_ARCH_CORTEXA9 is not set
+# CONFIG_ARCH_CORTEXR4 is not set
+# CONFIG_ARCH_CORTEXR4F is not set
+# CONFIG_ARCH_CORTEXR5 is not set
+# CONFIG_ARCH_CORTEX5F is not set
+# CONFIG_ARCH_CORTEXR7 is not set
+# CONFIG_ARCH_CORTEXR7F is not set
+CONFIG_ARCH_FAMILY="armv7-m"
+CONFIG_ARCH_CHIP="kinetis"
+# CONFIG_ARMV7M_USEBASEPRI is not set
+CONFIG_ARCH_HAVE_FPU=y
+# CONFIG_ARCH_HAVE_DPFPU is not set
+# CONFIG_ARCH_FPU is not set
+# CONFIG_ARCH_HAVE_TRUSTZONE is not set
+CONFIG_ARM_HAVE_MPU_UNIFIED=y
+# CONFIG_ARM_MPU is not set
+# CONFIG_DEBUG_HARDFAULT is not set
+
+#
+# ARMV7M Configuration Options
+#
+# CONFIG_ARMV7M_HAVE_ICACHE is not set
+# CONFIG_ARMV7M_HAVE_DCACHE is not set
+# CONFIG_ARMV7M_HAVE_ITCM is not set
+# CONFIG_ARMV7M_HAVE_DTCM is not set
+# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
+# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
+# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
+CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y
+# CONFIG_ARMV7M_HAVE_STACKCHECK is not set
+# CONFIG_ARMV7M_ITMSYSLOG is not set
+
+#
+# Kinetis Configuration Options
+#
+# CONFIG_ARCH_CHIP_MK20DN32VLH5 is not set
+# CONFIG_ARCH_CHIP_MK20DX32VLH5 is not set
+# CONFIG_ARCH_CHIP_MK20DN64VLH5 is not set
+# CONFIG_ARCH_CHIP_MK20DX64VLH5 is not set
+# CONFIG_ARCH_CHIP_MK20DN128VLH5 is not set
+# CONFIG_ARCH_CHIP_MK20DX128VLH5 is not set
+# CONFIG_ARCH_CHIP_MK20DX64VLH7 is not set
+# CONFIG_ARCH_CHIP_MK20DX128VLH7 is not set
+CONFIG_ARCH_CHIP_MK20DX256VLH7=y
+# CONFIG_ARCH_CHIP_MK40N512VLQ100 is not set
+# CONFIG_ARCH_CHIP_MK40N512VMD100 is not set
+# CONFIG_ARCH_CHIP_MK40X128VLQ100 is not set
+# CONFIG_ARCH_CHIP_MK40X128VMD100 is not set
+# CONFIG_ARCH_CHIP_MK40X256VLQ100 is not set
+# CONFIG_ARCH_CHIP_MK40X256VMD100 is not set
+# CONFIG_ARCH_CHIP_MK60N256VLQ100 is not set
+# CONFIG_ARCH_CHIP_MK60N256VMD100 is not set
+# CONFIG_ARCH_CHIP_MK60N512VLL100 is not set
+# CONFIG_ARCH_CHIP_MK60N512VLQ100 is not set
+# CONFIG_ARCH_CHIP_MK60N512VMD100 is not set
+# CONFIG_ARCH_CHIP_MK60X256VLQ100 is not set
+# CONFIG_ARCH_CHIP_MK60X256VMD100 is not set
+CONFIG_ARCH_FAMILY_K20=y
+# CONFIG_ARCH_FAMILY_K40 is not set
+# CONFIG_ARCH_FAMILY_K60 is not set
+
+#
+# Kinetis Peripheral Support
+#
+# CONFIG_KINETIS_TRACE is not set
+# CONFIG_KINETIS_FLEXBUS is not set
+CONFIG_KINETIS_UART0=y
+# CONFIG_KINETIS_UART1 is not set
+# CONFIG_KINETIS_UART2 is not set
+# CONFIG_KINETIS_UART3 is not set
+# CONFIG_KINETIS_UART4 is not set
+# CONFIG_KINETIS_UART5 is not set
+# CONFIG_KINETIS_FLEXCAN0 is not set
+# CONFIG_KINETIS_FLEXCAN1 is not set
+# CONFIG_KINETIS_SPI0 is not set
+# CONFIG_KINETIS_SPI1 is not set
+# CONFIG_KINETIS_SPI2 is not set
+# CONFIG_KINETIS_I2C0 is not set
+# CONFIG_KINETIS_I2C1 is not set
+# CONFIG_KINETIS_I2S is not set
+# CONFIG_KINETIS_DAC0 is not set
+# CONFIG_KINETIS_DAC1 is not set
+# CONFIG_KINETIS_ADC0 is not set
+# CONFIG_KINETIS_ADC1 is not set
+# CONFIG_KINETIS_CMP is not set
+# CONFIG_KINETIS_VREF is not set
+# CONFIG_KINETIS_SDHC is not set
+# CONFIG_KINETIS_FTM0 is not set
+# CONFIG_KINETIS_FTM1 is not set
+# CONFIG_KINETIS_FTM2 is not set
+# CONFIG_KINETIS_LPTIMER is not set
+# CONFIG_KINETIS_RTC is not set
+# CONFIG_KINETIS_EWM is not set
+# CONFIG_KINETIS_CMT is not set
+CONFIG_KINETIS_USBOTG=y
+# CONFIG_KINETIS_USBDCD is not set
+# CONFIG_KINETIS_LLWU is not set
+# CONFIG_KINETIS_TSI is not set
+# CONFIG_KINETIS_FTFL is not set
+# CONFIG_KINETIS_DMA is not set
+# CONFIG_KINETIS_CRC is not set
+# CONFIG_KINETIS_PDB is not set
+# CONFIG_KINETIS_PIT is not set
+
+#
+# Kinetis GPIO Interrupt Configuration
+#
+# CONFIG_GPIO_IRQ is not set
+
+#
+# Kinetis UART Configuration
+#
+CONFIG_KINETIS_UARTFIFOS=y
+
+#
+# Architecture Options
+#
+# CONFIG_ARCH_NOINTC is not set
+# CONFIG_ARCH_VECNOTIRQ is not set
+# CONFIG_ARCH_DMA is not set
+CONFIG_ARCH_HAVE_IRQPRIO=y
+# CONFIG_ARCH_L2CACHE is not set
+# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set
+# CONFIG_ARCH_HAVE_ADDRENV is not set
+# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set
+# CONFIG_ARCH_HAVE_MULTICPU is not set
+CONFIG_ARCH_HAVE_VFORK=y
+# CONFIG_ARCH_HAVE_MMU is not set
+CONFIG_ARCH_HAVE_MPU=y
+# CONFIG_ARCH_NAND_HWECC is not set
+# CONFIG_ARCH_HAVE_EXTCLK is not set
+# CONFIG_ARCH_HAVE_POWEROFF is not set
+CONFIG_ARCH_HAVE_RESET=y
+# CONFIG_ARCH_USE_MPU is not set
+# CONFIG_ARCH_IRQPRIO is not set
+CONFIG_ARCH_STACKDUMP=y
+# CONFIG_ARCH_USBDUMP is not set
+# CONFIG_ENDIAN_BIG is not set
+# CONFIG_ARCH_IDLE_CUSTOM is not set
+CONFIG_ARCH_HAVE_RAMFUNCS=y
+CONFIG_ARCH_RAMFUNCS=y
+CONFIG_ARCH_HAVE_RAMVECTORS=y
+# CONFIG_ARCH_RAMVECTORS is not set
+
+#
+# Board Settings
+#
+CONFIG_BOARD_LOOPSPERMSEC=6024
+# CONFIG_ARCH_CALIBRATION is not set
+
+#
+# Interrupt options
+#
+CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
+CONFIG_ARCH_INTERRUPTSTACK=0
+CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y
+# CONFIG_ARCH_HIPRI_INTERRUPT is not set
+
+#
+# Boot options
+#
+# CONFIG_BOOT_RUNFROMEXTSRAM is not set
+CONFIG_BOOT_RUNFROMFLASH=y
+# CONFIG_BOOT_RUNFROMISRAM is not set
+# CONFIG_BOOT_RUNFROMSDRAM is not set
+# CONFIG_BOOT_COPYTORAM is not set
+
+#
+# Boot Memory Configuration
+#
+CONFIG_RAM_START=0x1fff8000
+CONFIG_RAM_SIZE=65536
+# CONFIG_ARCH_HAVE_SDRAM is not set
+
+#
+# Board Selection
+#
+CONFIG_ARCH_BOARD_TEENSY_3X=y
+# CONFIG_ARCH_BOARD_CUSTOM is not set
+CONFIG_ARCH_BOARD="teensy-3.x"
+
+#
+# Common Board Options
+#
+CONFIG_ARCH_HAVE_LEDS=y
+CONFIG_ARCH_LEDS=y
+CONFIG_NSH_MMCSDMINOR=0
+
+#
+# Board-Specific Options
+#
+# CONFIG_TEENSY_3X_OVERCLOCK is not set
+CONFIG_LIB_BOARDCTL=y
+# CONFIG_BOARDCTL_RESET is not set
+# CONFIG_BOARDCTL_UNIQUEID is not set
+CONFIG_BOARDCTL_USBDEVCTRL=y
+# CONFIG_BOARDCTL_TSCTEST is not set
+# CONFIG_BOARDCTL_ADCTEST is not set
+# CONFIG_BOARDCTL_PWMTEST is not set
+# CONFIG_BOARDCTL_GRAPHICS is not set
+# CONFIG_BOARDCTL_IOCTL is not set
+
+#
+# RTOS Features
+#
+CONFIG_DISABLE_OS_API=y
+# CONFIG_DISABLE_POSIX_TIMERS is not set
+# CONFIG_DISABLE_PTHREAD is not set
+# CONFIG_DISABLE_SIGNALS is not set
+# CONFIG_DISABLE_MQUEUE is not set
+# CONFIG_DISABLE_ENVIRON is not set
+
+#
+# Clocks and Timers
+#
+CONFIG_USEC_PER_TICK=10000
+# CONFIG_SYSTEM_TIME64 is not set
+# CONFIG_CLOCK_MONOTONIC is not set
+# CONFIG_JULIAN_TIME is not set
+CONFIG_START_YEAR=2011
+CONFIG_START_MONTH=12
+CONFIG_START_DAY=6
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_PREALLOC_WDOGS=16
+CONFIG_WDOG_INTRESERVE=4
+CONFIG_PREALLOC_TIMERS=4
+
+#
+# Tasks and Scheduling
+#
+# CONFIG_SPINLOCK is not set
+# CONFIG_INIT_NONE is not set
+CONFIG_INIT_ENTRYPOINT=y
+# CONFIG_INIT_FILEPATH is not set
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_RR_INTERVAL=200
+# CONFIG_SCHED_SPORADIC is not set
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_MAX_TASKS=16
+# CONFIG_SCHED_HAVE_PARENT is not set
+CONFIG_SCHED_WAITPID=y
+
+#
+# Pthread Options
+#
+# CONFIG_MUTEX_TYPES is not set
+CONFIG_NPTHREAD_KEYS=4
+
+#
+# Performance Monitoring
+#
+# CONFIG_SCHED_CPULOAD is not set
+# CONFIG_SCHED_INSTRUMENTATION is not set
+
+#
+# Files and I/O
+#
+CONFIG_DEV_CONSOLE=y
+# CONFIG_FDCLONE_DISABLE is not set
+# CONFIG_FDCLONE_STDIO is not set
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NAME_MAX=32
+# CONFIG_PRIORITY_INHERITANCE is not set
+
+#
+# RTOS hooks
+#
+# CONFIG_BOARD_INITIALIZE is not set
+# CONFIG_SCHED_STARTHOOK is not set
+# CONFIG_SCHED_ATEXIT is not set
+# CONFIG_SCHED_ONEXIT is not set
+
+#
+# Signal Numbers
+#
+CONFIG_SIG_SIGUSR1=1
+CONFIG_SIG_SIGUSR2=2
+CONFIG_SIG_SIGALARM=3
+CONFIG_SIG_SIGCONDTIMEDOUT=16
+
+#
+# POSIX Message Queue Options
+#
+CONFIG_PREALLOC_MQ_MSGS=4
+CONFIG_MQ_MAXMSGSIZE=32
+# CONFIG_MODULE is not set
+
+#
+# Work queue support
+#
+# CONFIG_SCHED_WORKQUEUE is not set
+# CONFIG_SCHED_HPWORK is not set
+# CONFIG_SCHED_LPWORK is not set
+
+#
+# Stack and heap information
+#
+CONFIG_IDLETHREAD_STACKSIZE=1024
+CONFIG_USERMAIN_STACKSIZE=2048
+CONFIG_PTHREAD_STACK_MIN=256
+CONFIG_PTHREAD_STACK_DEFAULT=2048
+# CONFIG_LIB_SYSCALL is not set
+
+#
+# Device Drivers
+#
+CONFIG_DISABLE_POLL=y
+CONFIG_DEV_NULL=y
+# CONFIG_DEV_ZERO is not set
+# CONFIG_DEV_LOOP is not set
+
+#
+# Buffering
+#
+# CONFIG_DRVR_WRITEBUFFER is not set
+# CONFIG_DRVR_READAHEAD is not set
+# CONFIG_RAMDISK is not set
+# CONFIG_CAN is not set
+# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set
+# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set
+# CONFIG_PWM is not set
+# CONFIG_ARCH_HAVE_I2CRESET is not set
+# CONFIG_I2C is not set
+CONFIG_SPI=y
+# CONFIG_SPI_SLAVE is not set
+CONFIG_SPI_EXCHANGE=y
+# CONFIG_SPI_CMDDATA is not set
+# CONFIG_SPI_CALLBACK is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_HWFEATURES is not set
+# CONFIG_SPI_CRCGENERATION is not set
+# CONFIG_I2S is not set
+
+#
+# Timer Driver Support
+#
+# CONFIG_TIMER is not set
+# CONFIG_RTC is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_ANALOG is not set
+# CONFIG_AUDIO_DEVICES is not set
+# CONFIG_VIDEO_DEVICES is not set
+# CONFIG_BCH is not set
+# CONFIG_INPUT is not set
+# CONFIG_IOEXPANDER is not set
+# CONFIG_LCD is not set
+
+#
+# LED Support
+#
+# CONFIG_USERLED is not set
+# CONFIG_RGBLED is not set
+# CONFIG_PCA9635PW is not set
+# CONFIG_MMCSD is not set
+# CONFIG_MODEM is not set
+# CONFIG_MTD is not set
+# CONFIG_EEPROM is not set
+# CONFIG_PIPES is not set
+# CONFIG_PM is not set
+# CONFIG_POWER is not set
+# CONFIG_SENSORS is not set
+# CONFIG_SERCOMM_CONSOLE is not set
+CONFIG_SERIAL=y
+# CONFIG_DEV_LOWCONSOLE is not set
+CONFIG_SERIAL_REMOVABLE=y
+# CONFIG_16550_UART is not set
+# CONFIG_ARCH_HAVE_UART is not set
+CONFIG_ARCH_HAVE_UART0=y
+# CONFIG_ARCH_HAVE_UART1 is not set
+# CONFIG_ARCH_HAVE_UART2 is not set
+# CONFIG_ARCH_HAVE_UART3 is not set
+# CONFIG_ARCH_HAVE_UART4 is not set
+# CONFIG_ARCH_HAVE_UART5 is not set
+# CONFIG_ARCH_HAVE_UART6 is not set
+# CONFIG_ARCH_HAVE_UART7 is not set
+# CONFIG_ARCH_HAVE_UART8 is not set
+# CONFIG_ARCH_HAVE_SCI0 is not set
+# CONFIG_ARCH_HAVE_SCI1 is not set
+# CONFIG_ARCH_HAVE_USART0 is not set
+# CONFIG_ARCH_HAVE_USART1 is not set
+# CONFIG_ARCH_HAVE_USART2 is not set
+# CONFIG_ARCH_HAVE_USART3 is not set
+# CONFIG_ARCH_HAVE_USART4 is not set
+# CONFIG_ARCH_HAVE_USART5 is not set
+# CONFIG_ARCH_HAVE_USART6 is not set
+# CONFIG_ARCH_HAVE_USART7 is not set
+# CONFIG_ARCH_HAVE_USART8 is not set
+# CONFIG_ARCH_HAVE_OTHER_UART is not set
+
+#
+# USART Configuration
+#
+CONFIG_MCU_SERIAL=y
+CONFIG_STANDARD_SERIAL=y
+# CONFIG_SERIAL_IFLOWCONTROL is not set
+# CONFIG_SERIAL_OFLOWCONTROL is not set
+# CONFIG_SERIAL_DMA is not set
+# CONFIG_SERIAL_TIOCSERGSTRUCT is not set
+# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set
+CONFIG_UART0_SERIAL_CONSOLE=y
+# CONFIG_OTHER_SERIAL_CONSOLE is not set
+# CONFIG_NO_SERIAL_CONSOLE is not set
+
+#
+# UART0 Configuration
+#
+CONFIG_UART0_RXBUFSIZE=256
+CONFIG_UART0_TXBUFSIZE=256
+CONFIG_UART0_BAUD=115200
+CONFIG_UART0_BITS=8
+CONFIG_UART0_PARITY=0
+CONFIG_UART0_2STOP=0
+# CONFIG_UART0_IFLOWCONTROL is not set
+# CONFIG_UART0_OFLOWCONTROL is not set
+# CONFIG_UART0_DMA is not set
+CONFIG_USBDEV=y
+
+#
+# USB Device Controller Driver Options
+#
+# CONFIG_USBDEV_ISOCHRONOUS is not set
+CONFIG_USBDEV_DUALSPEED=y
+CONFIG_USBDEV_SELFPOWERED=y
+# CONFIG_USBDEV_BUSPOWERED is not set
+CONFIG_USBDEV_MAXPOWER=100
+# CONFIG_USBDEV_DMA is not set
+# CONFIG_ARCH_USBDEV_STALLQUEUE is not set
+CONFIG_USBDEV_TRACE=y
+CONFIG_USBDEV_TRACE_NRECORDS=128
+CONFIG_USBDEV_TRACE_INITIALIDSET=y
+
+#
+# USB Device Class Driver Options
+#
+# CONFIG_USBDEV_COMPOSITE is not set
+# CONFIG_PL2303 is not set
+CONFIG_CDCACM=y
+# CONFIG_CDCACM_CONSOLE is not set
+# CONFIG_CDCACM_IFLOWCONTROL is not set
+CONFIG_CDCACM_EP0MAXPACKET=64
+CONFIG_CDCACM_EPINTIN=1
+CONFIG_CDCACM_EPINTIN_FSSIZE=64
+CONFIG_CDCACM_EPINTIN_HSSIZE=64
+CONFIG_CDCACM_EPBULKOUT=3
+CONFIG_CDCACM_EPBULKOUT_FSSIZE=64
+CONFIG_CDCACM_EPBULKOUT_HSSIZE=512
+CONFIG_CDCACM_EPBULKIN=2
+CONFIG_CDCACM_EPBULKIN_FSSIZE=64
+CONFIG_CDCACM_EPBULKIN_HSSIZE=512
+CONFIG_CDCACM_NRDREQS=4
+CONFIG_CDCACM_NWRREQS=4
+CONFIG_CDCACM_BULKIN_REQLEN=768
+CONFIG_CDCACM_RXBUFSIZE=513
+CONFIG_CDCACM_TXBUFSIZE=769
+CONFIG_CDCACM_VENDORID=0x0525
+CONFIG_CDCACM_PRODUCTID=0xa4a7
+CONFIG_CDCACM_VENDORSTR="NuttX"
+CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial"
+# CONFIG_USBMSC is not set
+# CONFIG_USBHOST is not set
+# CONFIG_DRIVERS_WIRELESS is not set
+
+#
+# System Logging Device Options
+#
+
+#
+# System Logging
+#
+# CONFIG_RAMLOG is not set
+# CONFIG_SYSLOG_CONSOLE is not set
+
+#
+# Networking Support
+#
+# CONFIG_ARCH_HAVE_NET is not set
+# CONFIG_ARCH_HAVE_PHY is not set
+# CONFIG_NET is not set
+
+#
+# Crypto API
+#
+# CONFIG_CRYPTO is not set
+
+#
+# File Systems
+#
+
+#
+# File system configuration
+#
+# CONFIG_DISABLE_MOUNTPOINT is not set
+# CONFIG_FS_AUTOMOUNTER is not set
+# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set
+# CONFIG_FS_READABLE is not set
+# CONFIG_FS_WRITABLE is not set
+# CONFIG_FS_NAMED_SEMAPHORES is not set
+CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
+# CONFIG_FS_RAMMAP is not set
+# CONFIG_FS_FAT is not set
+# CONFIG_FS_NXFFS is not set
+# CONFIG_FS_ROMFS is not set
+# CONFIG_FS_TMPFS is not set
+# CONFIG_FS_SMARTFS is not set
+# CONFIG_FS_BINFS is not set
+# CONFIG_FS_PROCFS is not set
+# CONFIG_FS_UNIONFS is not set
+
+#
+# System Logging
+#
+# CONFIG_SYSLOG is not set
+# CONFIG_SYSLOG_TIMESTAMP is not set
+
+#
+# Graphics Support
+#
+# CONFIG_NX is not set
+
+#
+# Memory Management
+#
+# CONFIG_MM_SMALL is not set
+CONFIG_MM_REGIONS=1
+# CONFIG_ARCH_HAVE_HEAP2 is not set
+# CONFIG_GRAN is not set
+
+#
+# Audio Support
+#
+# CONFIG_AUDIO is not set
+
+#
+# Wireless Support
+#
+# CONFIG_WIRELESS is not set
+
+#
+# Binary Loader
+#
+# CONFIG_BINFMT_DISABLE is not set
+# CONFIG_BINFMT_EXEPATH is not set
+# CONFIG_NXFLAT is not set
+# CONFIG_ELF is not set
+CONFIG_BUILTIN=y
+# CONFIG_PIC is not set
+# CONFIG_SYMTAB_ORDEREDBYNAME is not set
+
+#
+# Library Routines
+#
+
+#
+# Standard C Library Options
+#
+CONFIG_STDIO_BUFFER_SIZE=64
+CONFIG_STDIO_LINEBUFFER=y
+CONFIG_NUNGET_CHARS=2
+CONFIG_LIB_HOMEDIR="/"
+# CONFIG_LIBM is not set
+# CONFIG_NOPRINTF_FIELDWIDTH is not set
+# CONFIG_LIBC_FLOATINGPOINT is not set
+CONFIG_LIBC_LONG_LONG=y
+# CONFIG_LIBC_IOCTL_VARIADIC is not set
+CONFIG_LIB_RAND_ORDER=1
+# CONFIG_EOL_IS_CR is not set
+# CONFIG_EOL_IS_LF is not set
+# CONFIG_EOL_IS_BOTH_CRLF is not set
+CONFIG_EOL_IS_EITHER_CRLF=y
+# CONFIG_LIBC_EXECFUNCS is not set
+CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024
+CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048
+# CONFIG_LIBC_STRERROR is not set
+# CONFIG_LIBC_PERROR_STDOUT is not set
+CONFIG_ARCH_LOWPUTC=y
+# CONFIG_LIBC_LOCALTIME is not set
+# CONFIG_TIME_EXTENDED is not set
+CONFIG_LIB_SENDFILE_BUFSIZE=512
+# CONFIG_ARCH_ROMGETC is not set
+# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
+CONFIG_ARCH_HAVE_TLS=y
+# CONFIG_TLS is not set
+# CONFIG_LIBC_NETDB is not set
+
+#
+# Non-standard Library Support
+#
+# CONFIG_LIB_KBDCODEC is not set
+# CONFIG_LIB_SLCDCODEC is not set
+
+#
+# Basic CXX Support
+#
+# CONFIG_C99_BOOL8 is not set
+# CONFIG_HAVE_CXX is not set
+
+#
+# Application Configuration
+#
+
+#
+# Built-In Applications
+#
+CONFIG_BUILTIN_PROXY_STACKSIZE=1024
+
+#
+# CAN Utilities
+#
+
+#
+# Examples
+#
+# CONFIG_EXAMPLES_CHAT is not set
+# CONFIG_EXAMPLES_CONFIGDATA is not set
+# CONFIG_EXAMPLES_CPUHOG is not set
+# CONFIG_EXAMPLES_DHCPD is not set
+# CONFIG_EXAMPLES_ELF is not set
+# CONFIG_EXAMPLES_FTPC is not set
+# CONFIG_EXAMPLES_FTPD is not set
+# CONFIG_EXAMPLES_HELLO is not set
+# CONFIG_EXAMPLES_JSON is not set
+# CONFIG_EXAMPLES_HIDKBD is not set
+# CONFIG_EXAMPLES_KEYPADTEST is not set
+# CONFIG_EXAMPLES_IGMP is not set
+# CONFIG_EXAMPLES_MEDIA is not set
+# CONFIG_EXAMPLES_MM is not set
+# CONFIG_EXAMPLES_MODBUS is not set
+# CONFIG_EXAMPLES_MOUNT is not set
+# CONFIG_EXAMPLES_NRF24L01TERM is not set
+CONFIG_EXAMPLES_NSH=y
+# CONFIG_EXAMPLES_NULL is not set
+# CONFIG_EXAMPLES_NX is not set
+# CONFIG_EXAMPLES_NXTERM is not set
+# CONFIG_EXAMPLES_NXFFS is not set
+# CONFIG_EXAMPLES_NXHELLO is not set
+# CONFIG_EXAMPLES_NXIMAGE is not set
+# CONFIG_EXAMPLES_NXLINES is not set
+# CONFIG_EXAMPLES_NXTEXT is not set
+# CONFIG_EXAMPLES_OSTEST is not set
+# CONFIG_EXAMPLES_PCA9635 is not set
+# CONFIG_EXAMPLES_PIPE is not set
+# CONFIG_EXAMPLES_PPPD is not set
+# CONFIG_EXAMPLES_POSIXSPAWN is not set
+# CONFIG_EXAMPLES_RGBLED is not set
+# CONFIG_EXAMPLES_RGMP is not set
+# CONFIG_EXAMPLES_SENDMAIL is not set
+# CONFIG_EXAMPLES_SERIALBLASTER is not set
+# CONFIG_EXAMPLES_SERIALRX is not set
+# CONFIG_EXAMPLES_SERLOOP is not set
+# CONFIG_EXAMPLES_SLCD is not set
+# CONFIG_EXAMPLES_SMART_TEST is not set
+# CONFIG_EXAMPLES_SMART is not set
+# CONFIG_EXAMPLES_SMP is not set
+# CONFIG_EXAMPLES_TCPECHO is not set
+# CONFIG_EXAMPLES_TELNETD is not set
+# CONFIG_EXAMPLES_TIFF is not set
+# CONFIG_EXAMPLES_TOUCHSCREEN is not set
+# CONFIG_EXAMPLES_WEBSERVER is not set
+# CONFIG_EXAMPLES_USBSERIAL is not set
+# CONFIG_EXAMPLES_USBTERM is not set
+# CONFIG_EXAMPLES_WATCHDOG is not set
+
+#
+# File System Utilities
+#
+# CONFIG_FSUTILS_INIFILE is not set
+
+#
+# GPS Utilities
+#
+# CONFIG_GPSUTILS_MINMEA_LIB is not set
+
+#
+# Graphics Support
+#
+# CONFIG_TIFF is not set
+# CONFIG_GRAPHICS_TRAVELER is not set
+
+#
+# Interpreters
+#
+# CONFIG_INTERPRETERS_FICL is not set
+# CONFIG_INTERPRETERS_PCODE is not set
+# CONFIG_INTERPRETERS_MICROPYTHON is not set
+
+#
+# FreeModBus
+#
+# CONFIG_MODBUS is not set
+
+#
+# Network Utilities
+#
+# CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_FTPC is not set
+# CONFIG_NETUTILS_JSON is not set
+# CONFIG_NETUTILS_SMTP is not set
+
+#
+# NSH Library
+#
+CONFIG_NSH_LIBRARY=y
+# CONFIG_NSH_MOTD is not set
+
+#
+# Command Line Configuration
+#
+CONFIG_NSH_READLINE=y
+# CONFIG_NSH_CLE is not set
+CONFIG_NSH_LINELEN=64
+# CONFIG_NSH_DISABLE_SEMICOLON is not set
+# CONFIG_NSH_CMDPARMS is not set
+CONFIG_NSH_MAXARGUMENTS=6
+# CONFIG_NSH_ARGCAT is not set
+CONFIG_NSH_NESTDEPTH=3
+# CONFIG_NSH_DISABLEBG is not set
+CONFIG_NSH_BUILTIN_APPS=y
+
+#
+# Disable Individual commands
+#
+# CONFIG_NSH_DISABLE_ADDROUTE is not set
+# CONFIG_NSH_DISABLE_BASENAME is not set
+# CONFIG_NSH_DISABLE_CAT is not set
+# CONFIG_NSH_DISABLE_CD is not set
+# CONFIG_NSH_DISABLE_CP is not set
+# CONFIG_NSH_DISABLE_CMP is not set
+CONFIG_NSH_DISABLE_DATE=y
+# CONFIG_NSH_DISABLE_DD is not set
+# CONFIG_NSH_DISABLE_DF is not set
+# CONFIG_NSH_DISABLE_DELROUTE is not set
+# CONFIG_NSH_DISABLE_DIRNAME is not set
+# CONFIG_NSH_DISABLE_ECHO is not set
+# CONFIG_NSH_DISABLE_EXEC is not set
+# CONFIG_NSH_DISABLE_EXIT is not set
+# CONFIG_NSH_DISABLE_FREE is not set
+# CONFIG_NSH_DISABLE_GET is not set
+# CONFIG_NSH_DISABLE_HELP is not set
+# CONFIG_NSH_DISABLE_HEXDUMP is not set
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+# CONFIG_NSH_DISABLE_KILL is not set
+# CONFIG_NSH_DISABLE_LOSETUP is not set
+CONFIG_NSH_DISABLE_LOSMART=y
+# CONFIG_NSH_DISABLE_LS is not set
+# CONFIG_NSH_DISABLE_MB is not set
+# CONFIG_NSH_DISABLE_MKDIR is not set
+# CONFIG_NSH_DISABLE_MKFIFO is not set
+# CONFIG_NSH_DISABLE_MKRD is not set
+# CONFIG_NSH_DISABLE_MH is not set
+# CONFIG_NSH_DISABLE_MOUNT is not set
+# CONFIG_NSH_DISABLE_MV is not set
+# CONFIG_NSH_DISABLE_MW is not set
+# CONFIG_NSH_DISABLE_PS is not set
+# CONFIG_NSH_DISABLE_PUT is not set
+# CONFIG_NSH_DISABLE_PWD is not set
+# CONFIG_NSH_DISABLE_RM is not set
+# CONFIG_NSH_DISABLE_RMDIR is not set
+# CONFIG_NSH_DISABLE_SET is not set
+# CONFIG_NSH_DISABLE_SH is not set
+# CONFIG_NSH_DISABLE_SLEEP is not set
+# CONFIG_NSH_DISABLE_TIME is not set
+# CONFIG_NSH_DISABLE_TEST is not set
+# CONFIG_NSH_DISABLE_UMOUNT is not set
+# CONFIG_NSH_DISABLE_UNAME is not set
+# CONFIG_NSH_DISABLE_UNSET is not set
+# CONFIG_NSH_DISABLE_USLEEP is not set
+# CONFIG_NSH_DISABLE_WGET is not set
+# CONFIG_NSH_DISABLE_XD is not set
+
+#
+# Configure Command Options
+#
+# CONFIG_NSH_CMDOPT_DF_H is not set
+CONFIG_NSH_CODECS_BUFSIZE=128
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+CONFIG_NSH_FILEIOSIZE=512
+
+#
+# Scripting Support
+#
+# CONFIG_NSH_DISABLESCRIPT is not set
+# CONFIG_NSH_DISABLE_ITEF is not set
+# CONFIG_NSH_DISABLE_LOOPS is not set
+
+#
+# Console Configuration
+#
+CONFIG_NSH_CONSOLE=y
+CONFIG_NSH_USBCONSOLE=y
+CONFIG_NSH_USBCONDEV="/dev/ttyACM0"
+CONFIG_USBDEV_MINOR=0
+
+#
+# USB Device Trace Support
+#
+# CONFIG_NSH_USBDEV_TRACE is not set
+CONFIG_NSH_ARCHINIT=y
+# CONFIG_NSH_LOGIN is not set
+# CONFIG_NSH_CONSOLE_LOGIN is not set
+
+#
+# NxWidgets/NxWM
+#
+
+#
+# Platform-specific Support
+#
+# CONFIG_PLATFORM_CONFIGDATA is not set
+
+#
+# System Libraries and NSH Add-Ons
+#
+# CONFIG_SYSTEM_FREE is not set
+# CONFIG_SYSTEM_CLE is not set
+# CONFIG_SYSTEM_CUTERM is not set
+# CONFIG_SYSTEM_INSTALL is not set
+# CONFIG_SYSTEM_HEX2BIN is not set
+CONFIG_SYSTEM_HEXED=y
+CONFIG_SYSTEM_HEXED_STACKSIZE=2048
+CONFIG_SYSTEM_HEXED_PRIORITY=100
+CONFIG_SYSTEM_RAMTEST=y
+CONFIG_READLINE_HAVE_EXTMATCH=y
+CONFIG_SYSTEM_READLINE=y
+CONFIG_READLINE_ECHO=y
+CONFIG_READLINE_TABCOMPLETION=y
+CONFIG_READLINE_MAX_BUILTINS=64
+CONFIG_READLINE_MAX_EXTCMDS=64
+CONFIG_READLINE_CMD_HISTORY=y
+CONFIG_READLINE_CMD_HISTORY_LINELEN=80
+CONFIG_READLINE_CMD_HISTORY_LEN=16
+# CONFIG_SYSTEM_SDCARD is not set
+# CONFIG_SYSTEM_SUDOKU is not set
+# CONFIG_SYSTEM_VI is not set
+CONFIG_SYSTEM_CDCACM=y
+CONFIG_SYSTEM_CDCACM_DEVMINOR=0
+# CONFIG_SYSTEM_CDCACM_TRACEINIT is not set
+# CONFIG_SYSTEM_CDCACM_TRACECLASS is not set
+# CONFIG_SYSTEM_CDCACM_TRACETRANSFERS is not set
+# CONFIG_SYSTEM_CDCACM_TRACECONTROLLER is not set
+# CONFIG_SYSTEM_CDCACM_TRACEINTERRUPTS is not set
+# CONFIG_SYSTEM_UBLOXMODEM is not set
+CONFIG_SYSTEM_USBMONITOR=y
+CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048
+CONFIG_SYSTEM_USBMONITOR_PRIORITY=50
+CONFIG_SYSTEM_USBMONITOR_INTERVAL=2
+CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y
+CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y
+CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y
+CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y
+CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y
+# CONFIG_SYSTEM_ZMODEM is not set
diff --git a/configs/teensy-3.x/usbnsh/setenv.sh b/configs/teensy-3.x/usbnsh/setenv.sh
new file mode 100755
index 0000000000..e96a2ff345
--- /dev/null
+++ b/configs/teensy-3.x/usbnsh/setenv.sh
@@ -0,0 +1,80 @@
+#!/bin/bash
+# configs/teensy-3.1/nsh/setenv.sh
+#
+# Copyright (C) 2015 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+if [ "$_" = "$0" ] ; then
+ echo "You must source this script, not run it!" 1>&2
+ exit 1
+fi
+
+WD=`pwd`
+if [ ! -x "setenv.sh" ]; then
+ echo "This script must be executed from the top-level NuttX build directory"
+ exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then
+ export PATH_ORIG="${PATH}"
+fi
+
+# This is the Cygwin path to the location where I installed the RIDE
+# toolchain under windows. You will also have to edit this if you install
+# the RIDE toolchain in any other location
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin"
+
+# This is the Cygwin path to the location where I installed the CodeSourcery
+# toolchain under windows. You will also have to edit this if you install
+# the CodeSourcery toolchain in any other location
+# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
+# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
+
+# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors"
+# You can this free toolchain here https://launchpad.net/gcc-arm-embedded
+export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin"
+
+# These are the Cygwin paths to the locations where I installed the Atollic
+# toolchain under windows. You will also have to edit this if you install
+# the Atollic toolchain in any other location. /usr/bin is added before
+# the Atollic bin path because there is are binaries named gcc.exe and g++.exe
+# at those locations as well.
+#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin"
+#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin"
+
+# This is the Cygwin path to the location where I build the buildroot
+# toolchain.
+#export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin"
+
+# Add the path to the toolchain to the PATH variable
+export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
+
+echo "PATH : ${PATH}"
--
GitLab
From a39ff55340408ef6e10b9eea70014ff962078e7d Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Mon, 6 Jun 2016 12:53:03 -0600
Subject: [PATCH 075/400] Update TODO and README.txt files
---
README.txt | 18 +++++++++++-------
TODO | 5 +++++
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/README.txt b/README.txt
index db0e5e6c10..b3cb19a407 100644
--- a/README.txt
+++ b/README.txt
@@ -960,10 +960,13 @@ Native Windows Build
In this build, you cannot use a Cygwin or MSYS shell. Rather the build must
be performed in a Windows console window. Here is a better terminal than the
standard issue, CMD.exe terminal: ConEmu which can be downloaded from:
- http://code.google.com/p/conemu-maximus5/
+ https://sourceforge.net/projects/conemu/ or https://conemu.github.io/ .
Build Tools. The build still relies on some Unix-like commands. I use
- the GNUWin32 tools that can be downloaded from http://gnuwin32.sourceforge.net/.
+ the GNUWin32 tools that can be downloaded from http://gnuwin32.sourceforge.net/
+ using the 'Download all' selection. Individual packages can be download
+ instead if you know what you are doing and want a faster download (No, I
+ can't tell you which packages you should or should not download).
Host Compiler: I use the MingGW GCC compiler which can be downloaded from
http://www.mingw.org/. If you are using GNUWin32, then it is recommended
@@ -971,12 +974,13 @@ Native Windows Build
This capability should still be considered a work in progress because:
- (1) It has not been verified on all targets and tools, and
- (2) it still lacks some of the creature-comforts of the more mature environments.
+ (1) It has not been verified on all targets and tools, and
+ (2) it still lacks some of the creature-comforts of the more mature
+ environments.
- There is an alternative to the setenv.sh script available for the Windows
- native environment: tools/configure.bat. See tools/README.txt for additional
- information.
+ There is an alternative to the setenv.sh script available for the Windows
+ native environment: tools/configure.bat. See tools/README.txt for additional
+ information.
Installing GNUWin32
-------------------
diff --git a/TODO b/TODO
index 0ce0c457ef..a4c960e2e1 100644
--- a/TODO
+++ b/TODO
@@ -1605,6 +1605,11 @@ o Build system
Description: The way that apps/ no generates Kmenu files depends on changes added
to apps/tools/mkkconfig.sh. Similar changes need to be made to
apps/tools/mkkconfig.bat to restore the Windows Native build.
+ UPDATE: The mkkconfig.bat script has been updated and appears to work.
+ A native build has still not been attempted and there could likely be
+ issues the carriage returns in Kconfig files. There are also some
+ issues the interpreters/ficl and bas directories during 'make menuconfig'
+ that still need to be investigated.
Status: Open
Priority: Low, since I am not aware of anyone using the Windows Native build.
But, of course, very high if you want to use it.
--
GitLab
From f75837a1109eab571528ccc0a5fc699c546f9d60 Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Mon, 6 Jun 2016 13:35:27 -0600
Subject: [PATCH 076/400] Changes from review of the last PR
---
arch/arm/src/kinetis/kinetis_usbdev.c | 346 +++++----
arch/arm/src/kinetis/kinetis_usbotg.h | 6 +-
configs/teensy-3.x/src/k20_appinit.c | 2 +
configs/teensy-3.x/src/k20_usbdev.c | 40 +-
configs/teensy-3.x/usbnsh/.config | 989 --------------------------
configs/teensy-3.x/usbnsh/Make.defs | 3 +-
configs/teensy-3.x/usbnsh/defconfig | 125 ++--
configs/teensy-3.x/usbnsh/setenv.sh | 12 +-
8 files changed, 253 insertions(+), 1270 deletions(-)
delete mode 100644 configs/teensy-3.x/usbnsh/.config
diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c
index 75fcdb2cc7..287f0f3abd 100644
--- a/arch/arm/src/kinetis/kinetis_usbdev.c
+++ b/arch/arm/src/kinetis/kinetis_usbdev.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/kinetis/kinetis_usbdev.c
*
- * Copyright (C) 2011-2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011-2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* References:
@@ -65,8 +65,6 @@
#include
#include "up_arch.h"
-//#include "pic32mx.h"
-//#include "pic32mx-usbotg.h"
#include "kinetis.h"
#include "kinetis_usbotg.h"
#include "kinetis_sim.h"
@@ -77,9 +75,8 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
-/* Configuration ************************************************************/
-//#define CONFIG_USBOTG
+/* Configuration ************************************************************/
#ifndef CONFIG_USBDEV_EP0_MAXSIZE
# define CONFIG_USBDEV_EP0_MAXSIZE 64
@@ -94,9 +91,6 @@
# undef CONFIG_KHCI_USBDEV_BDTDEBUG
#endif
-//#define CONFIG_KHCI_USBDEV_REGDEBUG
-//#define CONFIG_KHCI_USBDEV_BDTDEBUG
-
/* Disable this logic because it is buggy. It works most of the time but
* has some lurking issues that keep this higher performance solution from
* being usable.
@@ -110,8 +104,6 @@
/* Interrupts ***************************************************************/
/* Initial interrupt sets */
-//#define CONFIG_USB_SOFINTS
-
#ifdef CONFIG_USB_SOFINTS
# define USB_SOF_INTERRUPT USB_INT_SOFTOK
#else
@@ -122,29 +114,31 @@
USB_ERRSTAT_CRC16 | USB_ERRSTAT_DFN8 | USB_ERRSTAT_BTOERR | \
USB_ERRSTAT_BTSERR)
-#define NORMAL_INTERRUPTS (USB_INT_USBRST | USB_INT_ERROR | USB_SOF_INTERRUPT | \
+#define NORMAL_INTERRUPTS (USB_INT_USBRST | USB_INT_ERROR | USB_SOF_INTERRUPT | \
USB_INT_TOKDNE | USB_INT_SLEEP | USB_INT_STALL)
/* Endpoints ****************************************************************/
-#define USB_STAT_ENDPT(n) ((n) << USB_STAT_ENDP_SHIFT) /* Endpoint n, n=0..15 */
+#define USB_STAT_ENDPT(n) ((n) << USB_STAT_ENDP_SHIFT) /* Endpoint n, n=0..15 */
-#define USB_STAT_ODD_ODD USB_STAT_ODD /* The last transaction was to the ODD BD bank */
-#define USB_STAT_ODD_EVEN 0 /* The last transaction was to the EVEN BD bank */
+#define USB_STAT_ODD_ODD USB_STAT_ODD /* The last transaction was to the ODD BD bank */
+#define USB_STAT_ODD_EVEN 0 /* The last transaction was to the EVEN BD bank */
-#define USB_STAT_TX_IN USB_STAT_TX /* Last transaction was a transmit transfer (TX) */
-#define USB_STAT_TX_OUT 0 /* Last transaction was a receive transfer (RX) */
+#define USB_STAT_TX_IN USB_STAT_TX /* Last transaction was a transmit transfer (TX) */
+#define USB_STAT_TX_OUT 0 /* Last transaction was a receive transfer (RX) */
-#define KHCI_NENDPOINTS (16)
+#define KHCI_NENDPOINTS (16)
#define EP0 (0)
-#define KHCI_ENDP_BIT(ep) (1 << (ep))
-#define KHCI_ENDP_ALLSET 0xffff
+#define KHCI_ENDP_BIT(ep) (1 << (ep))
+#define KHCI_ENDP_ALLSET 0xffff
+
+#define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1)
/* BDT Table Indexing. The BDT is addressed in the hardware as follows:
*
* Bits 9-31: These come the BDT address bits written into the BDTP3,
- * BDTP2, and BDTP1 registers
+ * BDTP2, and BDTP1 registers
* Bits 5-8: The endpoint number
* Bit 4: Direction:
* 1 = Transmit: SETUP/OUT for host, IN for function
@@ -170,32 +164,32 @@
/* Packet sizes. We use a fixed 64 max packet size for all endpoint types */
-#define KHCI_MAXPACKET_SHIFT (6)
-#define KHCI_MAXPACKET_SIZE (1 << (KHCI_MAXPACKET_SHIFT))
+#define KHCI_MAXPACKET_SHIFT (6)
+#define KHCI_MAXPACKET_SIZE (1 << (KHCI_MAXPACKET_SHIFT))
-#define KHCI_EP0MAXPACKET KHCI_MAXPACKET_SIZE
+#define KHCI_EP0MAXPACKET KHCI_MAXPACKET_SIZE
/* Endpoint register initialization parameters */
-#define KHCI_EP_CONTROL (USB_ENDPT_EPHSHK|USB_ENDPT_EPTXEN|USB_ENDPT_EPRXEN)
-#define KHCI_EP_BULKIN (USB_ENDPT_EPTXEN|USB_ENDPT_EPCTLDIS|USB_ENDPT_EPHSHK)
-#define KHCI_EP_BULKOUT (USB_ENDPT_EPRXEN|USB_ENDPT_EPCTLDIS|USB_ENDPT_EPHSHK)
-#define KHCI_EP_INTIN (USB_ENDPT_EPTXEN|USB_ENDPT_EPCTLDIS|USB_ENDPT_EPHSHK)
-#define KHCI_EP_INTOUT (USB_ENDPT_EPRXEN|USB_ENDPT_EPCTLDIS|USB_ENDPT_EPHSHK)
-#define KHCI_EP_ISOCIN (USB_ENDPT_EPTXEN|USB_ENDPT_EPCTLDIS)
-#define KHCI_EP_ISOCOUT (USB_ENDPT_EPRXEN|USB_ENDPT_EPCTLDIS)
+#define KHCI_EP_CONTROL (USB_ENDPT_EPHSHK | USB_ENDPT_EPTXEN | USB_ENDPT_EPRXEN)
+#define KHCI_EP_BULKIN (USB_ENDPT_EPTXEN | USB_ENDPT_EPCTLDIS | USB_ENDPT_EPHSHK)
+#define KHCI_EP_BULKOUT (USB_ENDPT_EPRXEN | USB_ENDPT_EPCTLDIS | USB_ENDPT_EPHSHK)
+#define KHCI_EP_INTIN (USB_ENDPT_EPTXEN | USB_ENDPT_EPCTLDIS | USB_ENDPT_EPHSHK)
+#define KHCI_EP_INTOUT (USB_ENDPT_EPRXEN | USB_ENDPT_EPCTLDIS | USB_ENDPT_EPHSHK)
+#define KHCI_EP_ISOCIN (USB_ENDPT_EPTXEN | USB_ENDPT_EPCTLDIS)
+#define KHCI_EP_ISOCOUT (USB_ENDPT_EPRXEN | USB_ENDPT_EPCTLDIS)
/* USB-related masks */
-#define REQRECIPIENT_MASK (USB_REQ_TYPE_MASK | USB_REQ_RECIPIENT_MASK)
+#define REQRECIPIENT_MASK (USB_REQ_TYPE_MASK | USB_REQ_RECIPIENT_MASK)
/* Request queue operations *************************************************/
-#define khci_rqempty(q) ((q)->head == NULL)
-#define khci_rqhead(q) ((q)->head)
-#define khci_rqtail(q) ((q)->tail)
+#define khci_rqempty(q) ((q)->head == NULL)
+#define khci_rqhead(q) ((q)->head)
+#define khci_rqtail(q) ((q)->tail)
-#define RESTART_DELAY (150 * CLOCKS_PER_SEC / 1000)
+#define RESTART_DELAY (150 * CLOCKS_PER_SEC / 1000)
/* USB trace ****************************************************************/
/* Trace error codes */
@@ -266,47 +260,45 @@
#define KHCI_TRACEINTID_SUSPENDED 0x0023
#define KHCI_TRACEINTID_WAITRESET 0x0024
-
-
#ifdef CONFIG_USBDEV_TRACE_STRINGS
const struct trace_msg_t g_usb_trace_strings_intdecode[] =
{
- TRACE_STR(KHCI_TRACEINTID_CLEARFEATURE ), //0001
- TRACE_STR(KHCI_TRACEINTID_DEVGETSTATUS ), //0002
- TRACE_STR(KHCI_TRACEINTID_DISPATCH ), //0003
- TRACE_STR(KHCI_TRACEINTID_EP0IN ), //0004
- TRACE_STR(KHCI_TRACEINTID_EP0INDONE ), //0005
- TRACE_STR(KHCI_TRACEINTID_EP0OUTDONE ), //0006
- TRACE_STR(KHCI_TRACEINTID_EP0SETUPDONE ), //0007
- TRACE_STR(KHCI_TRACEINTID_EP0SETUPSETADDRESS ), //0008
- TRACE_STR(KHCI_TRACEINTID_EP0ADDRESSSET ), //0009
- TRACE_STR(KHCI_TRACEINTID_EPGETSTATUS ), //000a
- TRACE_STR(KHCI_TRACEINTID_EPINDONE ), //000b
- TRACE_STR(KHCI_TRACEINTID_EPINQEMPTY ), //000c
- TRACE_STR(KHCI_TRACEINTID_EPOUTDONE ), //000d
- TRACE_STR(KHCI_TRACEINTID_EPOUTQEMPTY ), //000e
- TRACE_STR(KHCI_TRACEINTID_SOF ), //000f
- TRACE_STR(KHCI_TRACEINTID_GETCONFIG ), //0010
- TRACE_STR(KHCI_TRACEINTID_GETSETDESC ), //0011
- TRACE_STR(KHCI_TRACEINTID_GETSETIF ), //0012
- TRACE_STR(KHCI_TRACEINTID_GETSTATUS ), //0013
- TRACE_STR(KHCI_TRACEINTID_IFGETSTATUS ), //0014
- TRACE_STR(KHCI_TRACEINTID_TRNC ), //0015
- TRACE_STR(KHCI_TRACEINTID_TRNCS ), //0016
- TRACE_STR(KHCI_TRACEINTID_INTERRUPT ), //0017
- TRACE_STR(KHCI_TRACEINTID_NOSTDREQ ), //0018
- TRACE_STR(KHCI_TRACEINTID_RESET ), //0019
- TRACE_STR(KHCI_TRACEINTID_SETCONFIG ), //001a
- TRACE_STR(KHCI_TRACEINTID_SETFEATURE ), //001b
- TRACE_STR(KHCI_TRACEINTID_IDLE ), //001c
- TRACE_STR(KHCI_TRACEINTID_SYNCHFRAME ), //001d
- TRACE_STR(KHCI_TRACEINTID_WKUP ), //001e
- TRACE_STR(KHCI_TRACEINTID_T1MSEC ), //001f
- TRACE_STR(KHCI_TRACEINTID_OTGID ), //0020
- TRACE_STR(KHCI_TRACEINTID_STALL ), //0021
- TRACE_STR(KHCI_TRACEINTID_UERR ), //0022
- TRACE_STR(KHCI_TRACEINTID_SUSPENDED ), //0023
- TRACE_STR(KHCI_TRACEINTID_WAITRESET ), //0024
+ TRACE_STR(KHCI_TRACEINTID_CLEARFEATURE ), /* 0x0001 */
+ TRACE_STR(KHCI_TRACEINTID_DEVGETSTATUS ), /* 0x0002 */
+ TRACE_STR(KHCI_TRACEINTID_DISPATCH ), /* 0x0003 */
+ TRACE_STR(KHCI_TRACEINTID_EP0IN ), /* 0x0004 */
+ TRACE_STR(KHCI_TRACEINTID_EP0INDONE ), /* 0x0005 */
+ TRACE_STR(KHCI_TRACEINTID_EP0OUTDONE ), /* 0x0006 */
+ TRACE_STR(KHCI_TRACEINTID_EP0SETUPDONE ), /* 0x0007 */
+ TRACE_STR(KHCI_TRACEINTID_EP0SETUPSETADDRESS ), /* 0x0008 */
+ TRACE_STR(KHCI_TRACEINTID_EP0ADDRESSSET ), /* 0x0009 */
+ TRACE_STR(KHCI_TRACEINTID_EPGETSTATUS ), /* 0x000a */
+ TRACE_STR(KHCI_TRACEINTID_EPINDONE ), /* 0x000b */
+ TRACE_STR(KHCI_TRACEINTID_EPINQEMPTY ), /* 0x000c */
+ TRACE_STR(KHCI_TRACEINTID_EPOUTDONE ), /* 0x000d */
+ TRACE_STR(KHCI_TRACEINTID_EPOUTQEMPTY ), /* 0x000e */
+ TRACE_STR(KHCI_TRACEINTID_SOF ), /* 0x000f */
+ TRACE_STR(KHCI_TRACEINTID_GETCONFIG ), /* 0x0010 */
+ TRACE_STR(KHCI_TRACEINTID_GETSETDESC ), /* 0x0011 */
+ TRACE_STR(KHCI_TRACEINTID_GETSETIF ), /* 0x0012 */
+ TRACE_STR(KHCI_TRACEINTID_GETSTATUS ), /* 0x0013 */
+ TRACE_STR(KHCI_TRACEINTID_IFGETSTATUS ), /* 0x0014 */
+ TRACE_STR(KHCI_TRACEINTID_TRNC ), /* 0x0015 */
+ TRACE_STR(KHCI_TRACEINTID_TRNCS ), /* 0x0016 */
+ TRACE_STR(KHCI_TRACEINTID_INTERRUPT ), /* 0x0017 */
+ TRACE_STR(KHCI_TRACEINTID_NOSTDREQ ), /* 0x0018 */
+ TRACE_STR(KHCI_TRACEINTID_RESET ), /* 0x0019 */
+ TRACE_STR(KHCI_TRACEINTID_SETCONFIG ), /* 0x001a */
+ TRACE_STR(KHCI_TRACEINTID_SETFEATURE ), /* 0x001b */
+ TRACE_STR(KHCI_TRACEINTID_IDLE ), /* 0x001c */
+ TRACE_STR(KHCI_TRACEINTID_SYNCHFRAME ), /* 0x001d */
+ TRACE_STR(KHCI_TRACEINTID_WKUP ), /* 0x001e */
+ TRACE_STR(KHCI_TRACEINTID_T1MSEC ), /* 0x001f */
+ TRACE_STR(KHCI_TRACEINTID_OTGID ), /* 0x0020 */
+ TRACE_STR(KHCI_TRACEINTID_STALL ), /* 0x0021 */
+ TRACE_STR(KHCI_TRACEINTID_UERR ), /* 0x0022 */
+ TRACE_STR(KHCI_TRACEINTID_SUSPENDED ), /* 0x0023 */
+ TRACE_STR(KHCI_TRACEINTID_WAITRESET ), /* 0x0024 */
TRACE_STR_END
};
#endif
@@ -314,32 +306,32 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] =
#ifdef CONFIG_USBDEV_TRACE_STRINGS
const struct trace_msg_t g_usb_trace_strings_deverror[] =
{
- TRACE_STR(KHCI_TRACEERR_ALLOCFAIL ), //0001
- TRACE_STR(KHCI_TRACEERR_BADCLEARFEATURE ), //0002
- TRACE_STR(KHCI_TRACEERR_BADDEVGETSTATUS ), //0003
- TRACE_STR(KHCI_TRACEERR_BADEPGETSTATUS ), //0004
- TRACE_STR(KHCI_TRACEERR_BADEPNO ), //0005
- TRACE_STR(KHCI_TRACEERR_BADEPTYPE ), //0006
- TRACE_STR(KHCI_TRACEERR_BADGETCONFIG ), //0007
- TRACE_STR(KHCI_TRACEERR_BADGETSETDESC ), //0008
- TRACE_STR(KHCI_TRACEERR_BADGETSTATUS ), //0009
- TRACE_STR(KHCI_TRACEERR_BADSETADDRESS ), //000a
- TRACE_STR(KHCI_TRACEERR_BADSETCONFIG ), //000b
- TRACE_STR(KHCI_TRACEERR_BADSETFEATURE ), //000c
- TRACE_STR(KHCI_TRACEERR_BINDFAILED ), //000d
- TRACE_STR(KHCI_TRACEERR_DISPATCHSTALL ), //000e
- TRACE_STR(KHCI_TRACEERR_DRIVER ), //000f
- TRACE_STR(KHCI_TRACEERR_DRIVERREGISTERED ), //0010
- TRACE_STR(KHCI_TRACEERR_EP0SETUPSTALLED ), //0011
- TRACE_STR(KHCI_TRACEERR_EPDISABLED ), //0012
- TRACE_STR(KHCI_TRACEERR_EPOUTNULLPACKET ), //0013
- TRACE_STR(KHCI_TRACEERR_EPRESERVE ), //0014
- TRACE_STR(KHCI_TRACEERR_INVALIDCTRLREQ ), //0015
- TRACE_STR(KHCI_TRACEERR_INVALIDPARMS ), //0016
- TRACE_STR(KHCI_TRACEERR_IRQREGISTRATION ), //0017
- TRACE_STR(KHCI_TRACEERR_NOTCONFIGURED ), //0018
- TRACE_STR(KHCI_TRACEERR_REQABORTED ), //0019
- TRACE_STR(KHCI_TRACEERR_INVALIDSTATE ), //001a
+ TRACE_STR(KHCI_TRACEERR_ALLOCFAIL ), /* 0x0001 */
+ TRACE_STR(KHCI_TRACEERR_BADCLEARFEATURE ), /* 0x0002 */
+ TRACE_STR(KHCI_TRACEERR_BADDEVGETSTATUS ), /* 0x0003 */
+ TRACE_STR(KHCI_TRACEERR_BADEPGETSTATUS ), /* 0x0004 */
+ TRACE_STR(KHCI_TRACEERR_BADEPNO ), /* 0x0005 */
+ TRACE_STR(KHCI_TRACEERR_BADEPTYPE ), /* 0x0006 */
+ TRACE_STR(KHCI_TRACEERR_BADGETCONFIG ), /* 0x0007 */
+ TRACE_STR(KHCI_TRACEERR_BADGETSETDESC ), /* 0x0008 */
+ TRACE_STR(KHCI_TRACEERR_BADGETSTATUS ), /* 0x0009 */
+ TRACE_STR(KHCI_TRACEERR_BADSETADDRESS ), /* 0x000a */
+ TRACE_STR(KHCI_TRACEERR_BADSETCONFIG ), /* 0x000b */
+ TRACE_STR(KHCI_TRACEERR_BADSETFEATURE ), /* 0x000c */
+ TRACE_STR(KHCI_TRACEERR_BINDFAILED ), /* 0x000d */
+ TRACE_STR(KHCI_TRACEERR_DISPATCHSTALL ), /* 0x000e */
+ TRACE_STR(KHCI_TRACEERR_DRIVER ), /* 0x000f */
+ TRACE_STR(KHCI_TRACEERR_DRIVERREGISTERED ), /* 0x0010 */
+ TRACE_STR(KHCI_TRACEERR_EP0SETUPSTALLED ), /* 0x0011 */
+ TRACE_STR(KHCI_TRACEERR_EPDISABLED ), /* 0x0012 */
+ TRACE_STR(KHCI_TRACEERR_EPOUTNULLPACKET ), /* 0x0013 */
+ TRACE_STR(KHCI_TRACEERR_EPRESERVE ), /* 0x0014 */
+ TRACE_STR(KHCI_TRACEERR_INVALIDCTRLREQ ), /* 0x0015 */
+ TRACE_STR(KHCI_TRACEERR_INVALIDPARMS ), /* 0x0016 */
+ TRACE_STR(KHCI_TRACEERR_IRQREGISTRATION ), /* 0x0017 */
+ TRACE_STR(KHCI_TRACEERR_NOTCONFIGURED ), /* 0x0018 */
+ TRACE_STR(KHCI_TRACEERR_REQABORTED ), /* 0x0019 */
+ TRACE_STR(KHCI_TRACEERR_INVALIDSTATE ), /* 0x001a */
TRACE_STR_END
};
#endif
@@ -451,21 +443,21 @@ union wb_u
struct khci_req_s
{
- struct usbdev_req_s req; /* Standard USB request */
+ struct usbdev_req_s req; /* Standard USB request */
#ifdef CONFIG_USBDEV_NOWRITEAHEAD
- uint16_t inflight[1]; /* The number of bytes "in-flight" */
+ uint16_t inflight[1]; /* The number of bytes "in-flight" */
#else
- uint16_t inflight[2]; /* The number of bytes "in-flight" */
+ uint16_t inflight[2]; /* The number of bytes "in-flight" */
#endif
- struct khci_req_s *flink; /* Supports a singly linked list */
+ struct khci_req_s *flink; /* Supports a singly linked list */
};
/* This structure represents the 'head' of a singly linked list of requests */
struct khci_queue_s
{
- struct khci_req_s *head; /* Head of the request queue */
- struct khci_req_s *tail; /* Tail of the request queue */
+ struct khci_req_s *head; /* Head of the request queue */
+ struct khci_req_s *tail; /* Tail of the request queue */
};
/* This is the internal representation of an endpoint */
@@ -477,18 +469,18 @@ struct khci_ep_s
* to struct khci_ep_s.
*/
- struct usbdev_ep_s ep; /* Standard endpoint structure */
+ struct usbdev_ep_s ep; /* Standard endpoint structure */
/* KHCI-specific fields */
- struct khci_usbdev_s *dev; /* Reference to private driver data */
- struct khci_queue_s pend; /* List of pending (inactive) requests for this endpoint */
- struct khci_queue_s active; /* List of active requests for this endpoint */
- uint8_t stalled:1; /* true: Endpoint is stalled */
- uint8_t halted:1; /* true: Endpoint feature halted */
- uint8_t txnullpkt:1; /* Null packet needed at end of TX transfer */
- uint8_t txdata1:1; /* Data0/1 of next TX transfer */
- uint8_t rxdata1:1; /* Data0/1 of next RX transfer */
+ struct khci_usbdev_s *dev; /* Reference to private driver data */
+ struct khci_queue_s pend; /* List of pending (inactive) requests for this endpoint */
+ struct khci_queue_s active; /* List of active requests for this endpoint */
+ uint8_t stalled:1; /* true: Endpoint is stalled */
+ uint8_t halted:1; /* true: Endpoint feature halted */
+ uint8_t txnullpkt:1; /* Null packet needed at end of TX transfer */
+ uint8_t txdata1:1; /* Data0/1 of next TX transfer */
+ uint8_t rxdata1:1; /* Data0/1 of next RX transfer */
volatile struct usbotg_bdtentry_s *bdtin; /* BDT entry for the IN transaction */
volatile struct usbotg_bdtentry_s *bdtout; /* BDT entry for the OUT transaction */
};
@@ -508,21 +500,21 @@ struct khci_usbdev_s
/* KHCI-specific fields */
- struct usb_ctrlreq_s ctrl; /* Last EP0 request */
- uint8_t devstate; /* Driver state (see enum khci_devstate_e) */
- uint8_t ctrlstate; /* Control EP state (see enum khci_ctrlstate_e) */
- uint8_t selfpowered:1; /* 1: Device is self powered */
- uint8_t rwakeup:1; /* 1: Device supports remote wakeup */
- uint8_t attached:1; /* Device is attached to the host */
- uint8_t ep0done:1; /* EP0 OUT already prepared */
- uint8_t rxbusy:1; /* EP0 OUT data transfer in progress */
- uint16_t epavail; /* Bitset of available endpoints */
- uint16_t epstalled; /* Bitset of stalled endpoints */
- WDOG_ID wdog; /* Supports the restart delay */
+ struct usb_ctrlreq_s ctrl; /* Last EP0 request */
+ uint8_t devstate; /* Driver state (see enum khci_devstate_e) */
+ uint8_t ctrlstate; /* Control EP state (see enum khci_ctrlstate_e) */
+ uint8_t selfpowered:1; /* 1: Device is self powered */
+ uint8_t rwakeup:1; /* 1: Device supports remote wakeup */
+ uint8_t attached:1; /* Device is attached to the host */
+ uint8_t ep0done:1; /* EP0 OUT already prepared */
+ uint8_t rxbusy:1; /* EP0 OUT data transfer in progress */
+ uint16_t epavail; /* Bitset of available endpoints */
+ uint16_t epstalled; /* Bitset of stalled endpoints */
+ WDOG_ID wdog; /* Supports the restart delay */
/* The endpoint list */
- struct khci_ep_s eplist[KHCI_NENDPOINTS];
+ struct khci_ep_s eplist[KHCI_NENDPOINTS];
};
/****************************************************************************
@@ -548,7 +540,7 @@ static struct khci_req_s *khci_remlast(struct khci_queue_s *queue);
static void khci_addlast(struct khci_queue_s *queue,
struct khci_req_s *req);
static void khci_addfirst(struct khci_queue_s *queue,
- struct khci_req_s *req);
+ struct khci_req_s *req);
/* Request Helpers **********************************************************/
@@ -601,7 +593,7 @@ static inline struct khci_ep_s *
khci_epreserve(struct khci_usbdev_s *priv, uint8_t epset);
static inline void
khci_epunreserve(struct khci_usbdev_s *priv,
- struct khci_ep_s *privep);
+ struct khci_ep_s *privep);
static inline bool
khci_epreserved(struct khci_usbdev_s *priv, int epno);
static void khci_ep0configure(struct khci_usbdev_s *priv);
@@ -689,10 +681,6 @@ static const struct usbdev_ops_s g_devops =
static volatile struct usbotg_bdtentry_s g_bdt[4*KHCI_NENDPOINTS]
__attribute__ ((aligned(512)));
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
/****************************************************************************
* Private Private Functions
****************************************************************************/
@@ -700,7 +688,8 @@ static volatile struct usbotg_bdtentry_s g_bdt[4*KHCI_NENDPOINTS]
/****************************************************************************
* Register Operations
****************************************************************************/
-/****************************************************************************
+
+ /****************************************************************************
* Name: khci_getreg
****************************************************************************/
@@ -778,6 +767,7 @@ static void khci_putreg(uint32_t val, uint32_t addr)
/****************************************************************************
* Request Helpers
****************************************************************************/
+
/****************************************************************************
* Name: khci_remfirst
****************************************************************************/
@@ -867,6 +857,7 @@ static void khci_addfirst(struct khci_queue_s *queue, struct khci_req_s *req)
{
queue->tail = req;
}
+
queue->head = req;
}
@@ -1781,6 +1772,7 @@ static void khci_cancelrequests(struct khci_ep_s *privep, int16_t result)
/****************************************************************************
* Interrupt Level Processing
****************************************************************************/
+
/****************************************************************************
* Name: khci_dispatchrequest
****************************************************************************/
@@ -1967,17 +1959,17 @@ static void khci_ep0rdcomplete(struct khci_usbdev_s *priv)
static void khci_ep0setup(struct khci_usbdev_s *priv)
{
volatile struct usbotg_bdtentry_s *bdt;
- struct khci_ep_s *ep0;
- struct khci_ep_s *privep;
- union wb_u value;
- union wb_u index;
- union wb_u len;
- union wb_u response;
- uint32_t regval;
- bool dispatched = false;
- uint8_t epno;
- int nbytes = 0; /* Assume zero-length packet */
- int ret;
+ struct khci_ep_s *ep0;
+ struct khci_ep_s *privep;
+ union wb_u value;
+ union wb_u index;
+ union wb_u len;
+ union wb_u response;
+ uint32_t regval;
+ bool dispatched = false;
+ uint8_t epno;
+ int nbytes = 0; /* Assume zero-length packet */
+ int ret;
/* Cancel any pending requests. */
@@ -1989,9 +1981,9 @@ static void khci_ep0setup(struct khci_usbdev_s *priv)
* beginning with DATA1.
*/
- ep0->stalled = false;
- ep0->rxdata1 = 0;
- ep0->txdata1 = 1;
+ ep0->stalled = false;
+ ep0->rxdata1 = 0;
+ ep0->txdata1 = 1;
/* Initialize for the SETUP */
@@ -2760,9 +2752,7 @@ static int khci_interrupt(int irq, void *context)
usbir = khci_getreg(KINETIS_USB0_ISTAT) & khci_getreg(KINETIS_USB0_INTEN);
otgir = khci_getreg(KINETIS_USB0_OTGISTAT) & khci_getreg(KINETIS_USB0_OTGICR);
-// ulldbg("Interrupt: ISTAT %04x\n", khci_getreg(KINETIS_USB0_ISTAT));
-// ulldbg("Interrupt: OTGISTAT %04x\n", khci_getreg(KINETIS_USB0_OTGISTAT));
-// ulldbg("Interrupt: ERRSTAT %04x\n", khci_getreg(KINETIS_USB0_ERRSTAT));
+
usbtrace(TRACE_INTENTRY(KHCI_TRACEINTID_INTERRUPT), usbir | otgir);
#ifdef CONFIG_USBOTG
@@ -2995,7 +2985,6 @@ x
*/
interrupt_exit:
- //up_clrpend_irq(KINETIS_IRQ_USBOTG);
kinetis_clrpend(KINETIS_IRQ_USBOTG);
usbtrace(TRACE_INTEXIT(KHCI_TRACEINTID_INTERRUPT), usbir | otgir);
return OK;
@@ -3227,6 +3216,7 @@ static void khci_ep0configure(struct khci_usbdev_s *priv)
/****************************************************************************
* Endpoint operations
****************************************************************************/
+
/****************************************************************************
* Name: khci_epconfigure
****************************************************************************/
@@ -3422,6 +3412,7 @@ static struct usbdev_req_s *khci_epallocreq(struct usbdev_ep_s *ep)
return NULL;
}
#endif
+
usbtrace(TRACE_EPALLOCREQ, USB_EPNO(ep->eplog));
privreq = (struct khci_req_s *)kmm_malloc(sizeof(struct khci_req_s));
@@ -3450,6 +3441,7 @@ static void khci_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
return;
}
#endif
+
usbtrace(TRACE_EPFREEREQ, USB_EPNO(ep->eplog));
kmm_free(privreq);
@@ -4026,11 +4018,9 @@ static void khci_attach(struct khci_usbdev_s *priv)
/* Initialize registers to known states. */
- //khci_putreg(0, KINETIS_USB0_CTL);
-
#if 1
khci_putreg(0x1,KINETIS_USB0_CTL);
- khci_putreg(0,KINETIS_USB0_USBCTRL);
+ khci_putreg(0,KINETIS_USB0_USBCTRL);
#endif
/* Enable interrupts at the USB controller */
@@ -4221,6 +4211,7 @@ static void khci_hwreset(struct khci_usbdev_s *priv)
#define USB_FLASH_ACCESS
#ifdef USB_FLASH_ACCESS
/* Allow USBOTG-FS Controller to Read from FLASH */
+
regval = getreg32(KINETIS_FMC_PFAPR);
regval &= ~(FMC_PFAPR_M4AP_MASK);
regval |= (FMC_PFAPR_RDONLY << FMC_PFAPR_M4AP_SHIFT);
@@ -4231,13 +4222,15 @@ static void khci_hwreset(struct khci_usbdev_s *priv)
memset((void *)g_bdt, 0, sizeof(g_bdt));
- /* Soft reset the USB Module*/
+ /* Soft reset the USB Module */
+
regval = khci_getreg(KINETIS_USB0_USBTRC0);
regval |= USB_USBTRC0_USBRESET;
khci_putreg(regval,KINETIS_USB0_USBTRC0);
- //is this really necessary?
- while (khci_getreg(KINETIS_USB0_USBTRC0) & USB_USBTRC0_USBRESET);
+ /* Is this really necessary? */
+
+ while (khci_getreg(KINETIS_USB0_USBTRC0) & USB_USBTRC0_USBRESET);
/* Set the address of the buffer descriptor table (BDT)
*
@@ -4245,7 +4238,7 @@ static void khci_hwreset(struct khci_usbdev_s *priv)
* BDTP2: Bit 0-7: Bits 16-23 of the BDT base address
* BDTP3: Bit 0-7: Bits 24-31 of the BDT base address
*/
-
+
khci_putreg((uint8_t)((uint32_t)g_bdt >> 24), KINETIS_USB0_BDTPAGE3);
khci_putreg((uint8_t)((uint32_t)g_bdt >> 16), KINETIS_USB0_BDTPAGE2);
khci_putreg((uint8_t)(((uint32_t)g_bdt >> 8) & USB_BDTPAGE1_MASK), KINETIS_USB0_BDTPAGE1);
@@ -4255,7 +4248,6 @@ static void khci_hwreset(struct khci_usbdev_s *priv)
ulldbg("BDTPAGE2 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE2));
ulldbg("BDTPAGE1 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE1));
-
/* Clear any pending interrupts */
khci_putreg(0xFF, KINETIS_USB0_ERRSTAT);
@@ -4263,7 +4255,6 @@ static void khci_hwreset(struct khci_usbdev_s *priv)
khci_putreg(0xFF,KINETIS_USB0_OTGISTAT);
#if 1
-
/* Assert reset request to all of the Ping Pong buffer pointers. This
* will reset all Even/Odd buffer pointers to the EVEN BD banks.
*/
@@ -4276,11 +4267,11 @@ static void khci_hwreset(struct khci_usbdev_s *priv)
regval &= ~USB_CTL_ODDRST;
khci_putreg(regval, KINETIS_USB0_CTL);
-
#endif
#if 1
- /*Undocumented bit*/
+ /* Undocumented bit */
+
regval = khci_getreg(KINETIS_USB0_USBTRC0);
regval |= 0x40;
khci_putreg(regval,KINETIS_USB0_USBTRC0);
@@ -4385,6 +4376,7 @@ static void khci_hwshutdown(struct khci_usbdev_s *priv)
/****************************************************************************
* Public Functions
****************************************************************************/
+
/****************************************************************************
* Name: up_usbinitialize
*
@@ -4399,39 +4391,41 @@ static void khci_hwshutdown(struct khci_usbdev_s *priv)
*
****************************************************************************/
-#define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1)
-
void up_usbinitialize(void)
{
+ struct khci_usbdev_s *priv = &g_usbdev;
uint32_t regval;
+
/* For now there is only one USB controller, but we will always refer to
* it using a pointer to make any future ports to multiple USB controllers
* easier.
*/
#if 1
- //1: Select clock source
+ /* 1: Select clock source */
+
regval = getreg32(KINETIS_SIM_SOPT2);
regval |= SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_USBSRC;
putreg32(regval, KINETIS_SIM_SOPT2);
regval = getreg32(KINETIS_SIM_CLKDIV2);
#if defined(CONFIG_TEENSY_3X_OVERCLOCK)
- regval = SIM_CLKDIV2_USBDIV(1); //(USBFRAC + 0)/(USBDIV + 1) = (1 + 0)/(1 + 1) = 1/2 for 96Mhz clock
+ /* (USBFRAC + 0)/(USBDIV + 1) = (1 + 0)/(1 + 1) = 1/2 for 96Mhz clock */
+
+ regval = SIM_CLKDIV2_USBDIV(1);
#else
- //72Mhz
+ /* 72Mhz */
+
regval = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC;
#endif
putreg32(regval, KINETIS_SIM_CLKDIV2);
-
- //2: Gate USB clock
+
+ /* 2: Gate USB clock */
+
regval = getreg32(KINETIS_SIM_SCGC4);
regval |= SIM_SCGC4_USBOTG;
putreg32(regval, KINETIS_SIM_SCGC4);
-
-#endif
-
- struct khci_usbdev_s *priv = &g_usbdev;
+#endif
usbtrace(TRACE_DEVINIT, 0);
@@ -4459,10 +4453,11 @@ void up_usbinitialize(void)
(uint16_t)KINETIS_IRQ_USBOTG);
up_usbuninitialize();
}
+
#ifdef CONFIG_ARCH_IRQPRIO
- /* Set the interrupt priority */
+ /* Set the interrupt priority */
- up_prioritize_irq(KINETIS_IRQ_USBOTG, 112);
+ up_prioritize_irq(KINETIS_IRQ_USBOTG, 112);
#endif
}
@@ -4569,6 +4564,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
DEBUGASSERT(priv->devstate == DEVSTATE_DETACHED);
khci_reset(priv);
}
+
return ret;
}
diff --git a/arch/arm/src/kinetis/kinetis_usbotg.h b/arch/arm/src/kinetis/kinetis_usbotg.h
index 22a474a824..de53d51293 100644
--- a/arch/arm/src/kinetis/kinetis_usbotg.h
+++ b/arch/arm/src/kinetis/kinetis_usbotg.h
@@ -1,7 +1,7 @@
/********************************************************************************************
* arch/arm/src/kinetis/kinetis_usbotg.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -363,10 +363,6 @@ struct usbotg_bdtentry_s
};
#endif
-/********************************************************************************************
- * Public Data
- ********************************************************************************************/
-
/********************************************************************************************
* Public Functions
********************************************************************************************/
diff --git a/configs/teensy-3.x/src/k20_appinit.c b/configs/teensy-3.x/src/k20_appinit.c
index 8512a35d33..c4d9e3fd44 100644
--- a/configs/teensy-3.x/src/k20_appinit.c
+++ b/configs/teensy-3.x/src/k20_appinit.c
@@ -78,7 +78,9 @@ int board_app_initialize(uintptr_t arg)
/* Teensy is powered from usb and (bug?) only boots from being programmed,
* so if usb is compiled in signal the controller driver that we're attached now.
*/
+
khci_usbattach();
#endif
+
return OK;
}
diff --git a/configs/teensy-3.x/src/k20_usbdev.c b/configs/teensy-3.x/src/k20_usbdev.c
index a2b3c20ddf..d8b801193a 100644
--- a/configs/teensy-3.x/src/k20_usbdev.c
+++ b/configs/teensy-3.x/src/k20_usbdev.c
@@ -1,7 +1,7 @@
/************************************************************************************
* configs/teensy-3.x/src/k20_usbdev.c
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -56,13 +56,10 @@
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
+
#define khci_getreg(addr) getreg8(addr)
#define khci_putreg(val,addr) putreg8(val,addr)
-#define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1)
-
-/************************************************************************************
- * Private Functions
- ************************************************************************************/
+#define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1)
/************************************************************************************
* Public Functions
@@ -78,9 +75,6 @@
void kinetis_usbinitialize(void)
{
- uint32_t regval;
-
-// khci_usbattach();
}
/************************************************************************************
@@ -99,16 +93,28 @@ int kinetis_usbpullup(FAR struct usbdev_s *dev, bool enable)
{
usbtrace(TRACE_DEVPULLUP, (uint16_t)enable);
uint32_t regval;
-if (enable)
-khci_putreg(USB_CONTROL_DPPULLUPNONOTG, KINETIS_USB0_CONTROL);
-else
-khci_putreg(0,KINETIS_USB0_CONTROL);
+
+ if (enable)
+ {
+ khci_putreg(USB_CONTROL_DPPULLUPNONOTG, KINETIS_USB0_CONTROL);
+ }
+ else
+ {
+ khci_putreg(0,KINETIS_USB0_CONTROL);
+ }
+
#if 0
regval = khci_getreg(KINETIS_USB0_OTGCTL);
- if (enable)
- regval |= (1<<2);
- else
- regval &= ~(1<<2);
+
+ if (enable)
+ {
+ regval |= (1 << 2);
+ }
+ else
+ {
+ regval &= ~(1 << 2);
+ }
+
khci_putreg(regval,KINETIS_USB0_OTGCTL);
#endif
diff --git a/configs/teensy-3.x/usbnsh/.config b/configs/teensy-3.x/usbnsh/.config
deleted file mode 100644
index 0f0f54c88e..0000000000
--- a/configs/teensy-3.x/usbnsh/.config
+++ /dev/null
@@ -1,989 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# Nuttx/ Configuration
-#
-
-#
-# Build Setup
-#
-CONFIG_EXPERIMENTAL=y
-# CONFIG_DEFAULT_SMALL is not set
-CONFIG_HOST_LINUX=y
-# CONFIG_HOST_OSX is not set
-# CONFIG_HOST_WINDOWS is not set
-# CONFIG_HOST_OTHER is not set
-
-#
-# Build Configuration
-#
-CONFIG_APPS_DIR="../apps"
-CONFIG_BUILD_FLAT=y
-# CONFIG_BUILD_2PASS is not set
-
-#
-# Binary Output Formats
-#
-# CONFIG_RRLOAD_BINARY is not set
-CONFIG_INTELHEX_BINARY=y
-# CONFIG_MOTOROLA_SREC is not set
-CONFIG_RAW_BINARY=y
-# CONFIG_UBOOT_UIMAGE is not set
-
-#
-# Customize Header Files
-#
-# CONFIG_ARCH_STDINT_H is not set
-# CONFIG_ARCH_STDBOOL_H is not set
-# CONFIG_ARCH_MATH_H is not set
-# CONFIG_ARCH_FLOAT_H is not set
-# CONFIG_ARCH_STDARG_H is not set
-# CONFIG_ARCH_DEBUG_H is not set
-
-#
-# Debug Options
-#
-CONFIG_DEBUG=y
-# CONFIG_ARCH_HAVE_HEAPCHECK is not set
-# CONFIG_DEBUG_VERBOSE is not set
-
-#
-# Subsystem Debug Options
-#
-# CONFIG_DEBUG_BINFMT is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_DEBUG_GRAPHICS is not set
-# CONFIG_DEBUG_LIB is not set
-# CONFIG_DEBUG_MM is not set
-# CONFIG_DEBUG_SCHED is not set
-
-#
-# OS Function Debug Options
-#
-# CONFIG_DEBUG_IRQ is not set
-
-#
-# Driver Debug Options
-#
-# CONFIG_DEBUG_LEDS is not set
-# CONFIG_DEBUG_ANALOG is not set
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_DEBUG_SPI is not set
-# CONFIG_DEBUG_USB is not set
-CONFIG_ARCH_HAVE_STACKCHECK=y
-# CONFIG_STACK_COLORATION is not set
-CONFIG_DEBUG_SYMBOLS=y
-CONFIG_ARCH_HAVE_CUSTOMOPT=y
-# CONFIG_DEBUG_NOOPT is not set
-# CONFIG_DEBUG_CUSTOMOPT is not set
-CONFIG_DEBUG_FULLOPT=y
-
-#
-# System Type
-#
-CONFIG_ARCH_ARM=y
-# CONFIG_ARCH_AVR is not set
-# CONFIG_ARCH_HC is not set
-# CONFIG_ARCH_MIPS is not set
-# CONFIG_ARCH_RGMP is not set
-# CONFIG_ARCH_SH is not set
-# CONFIG_ARCH_SIM is not set
-# CONFIG_ARCH_X86 is not set
-# CONFIG_ARCH_Z16 is not set
-# CONFIG_ARCH_Z80 is not set
-CONFIG_ARCH="arm"
-
-#
-# ARM Options
-#
-# CONFIG_ARCH_CHIP_A1X is not set
-# CONFIG_ARCH_CHIP_C5471 is not set
-# CONFIG_ARCH_CHIP_CALYPSO is not set
-# CONFIG_ARCH_CHIP_DM320 is not set
-# CONFIG_ARCH_CHIP_EFM32 is not set
-# CONFIG_ARCH_CHIP_IMX1 is not set
-# CONFIG_ARCH_CHIP_IMX6 is not set
-CONFIG_ARCH_CHIP_KINETIS=y
-# CONFIG_ARCH_CHIP_KL is not set
-# CONFIG_ARCH_CHIP_LM is not set
-# CONFIG_ARCH_CHIP_TIVA is not set
-# CONFIG_ARCH_CHIP_LPC11XX is not set
-# CONFIG_ARCH_CHIP_LPC17XX is not set
-# CONFIG_ARCH_CHIP_LPC214X is not set
-# CONFIG_ARCH_CHIP_LPC2378 is not set
-# CONFIG_ARCH_CHIP_LPC31XX is not set
-# CONFIG_ARCH_CHIP_LPC43XX is not set
-# CONFIG_ARCH_CHIP_NUC1XX is not set
-# CONFIG_ARCH_CHIP_SAMA5 is not set
-# CONFIG_ARCH_CHIP_SAMD is not set
-# CONFIG_ARCH_CHIP_SAML is not set
-# CONFIG_ARCH_CHIP_SAM34 is not set
-# CONFIG_ARCH_CHIP_SAMV7 is not set
-# CONFIG_ARCH_CHIP_STM32 is not set
-# CONFIG_ARCH_CHIP_STM32F7 is not set
-# CONFIG_ARCH_CHIP_STM32L4 is not set
-# CONFIG_ARCH_CHIP_STR71X is not set
-# CONFIG_ARCH_CHIP_TMS570 is not set
-# CONFIG_ARCH_CHIP_MOXART is not set
-# CONFIG_ARCH_ARM7TDMI is not set
-# CONFIG_ARCH_ARM926EJS is not set
-# CONFIG_ARCH_ARM920T is not set
-# CONFIG_ARCH_CORTEXM0 is not set
-# CONFIG_ARCH_CORTEXM3 is not set
-CONFIG_ARCH_CORTEXM4=y
-# CONFIG_ARCH_CORTEXM7 is not set
-# CONFIG_ARCH_CORTEXA5 is not set
-# CONFIG_ARCH_CORTEXA8 is not set
-# CONFIG_ARCH_CORTEXA9 is not set
-# CONFIG_ARCH_CORTEXR4 is not set
-# CONFIG_ARCH_CORTEXR4F is not set
-# CONFIG_ARCH_CORTEXR5 is not set
-# CONFIG_ARCH_CORTEX5F is not set
-# CONFIG_ARCH_CORTEXR7 is not set
-# CONFIG_ARCH_CORTEXR7F is not set
-CONFIG_ARCH_FAMILY="armv7-m"
-CONFIG_ARCH_CHIP="kinetis"
-# CONFIG_ARMV7M_USEBASEPRI is not set
-CONFIG_ARCH_HAVE_FPU=y
-# CONFIG_ARCH_HAVE_DPFPU is not set
-# CONFIG_ARCH_FPU is not set
-# CONFIG_ARCH_HAVE_TRUSTZONE is not set
-CONFIG_ARM_HAVE_MPU_UNIFIED=y
-# CONFIG_ARM_MPU is not set
-# CONFIG_DEBUG_HARDFAULT is not set
-
-#
-# ARMV7M Configuration Options
-#
-# CONFIG_ARMV7M_HAVE_ICACHE is not set
-# CONFIG_ARMV7M_HAVE_DCACHE is not set
-# CONFIG_ARMV7M_HAVE_ITCM is not set
-# CONFIG_ARMV7M_HAVE_DTCM is not set
-# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
-# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
-# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
-CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y
-# CONFIG_ARMV7M_HAVE_STACKCHECK is not set
-# CONFIG_ARMV7M_ITMSYSLOG is not set
-
-#
-# Kinetis Configuration Options
-#
-# CONFIG_ARCH_CHIP_MK20DN32VLH5 is not set
-# CONFIG_ARCH_CHIP_MK20DX32VLH5 is not set
-# CONFIG_ARCH_CHIP_MK20DN64VLH5 is not set
-# CONFIG_ARCH_CHIP_MK20DX64VLH5 is not set
-# CONFIG_ARCH_CHIP_MK20DN128VLH5 is not set
-# CONFIG_ARCH_CHIP_MK20DX128VLH5 is not set
-# CONFIG_ARCH_CHIP_MK20DX64VLH7 is not set
-# CONFIG_ARCH_CHIP_MK20DX128VLH7 is not set
-CONFIG_ARCH_CHIP_MK20DX256VLH7=y
-# CONFIG_ARCH_CHIP_MK40N512VLQ100 is not set
-# CONFIG_ARCH_CHIP_MK40N512VMD100 is not set
-# CONFIG_ARCH_CHIP_MK40X128VLQ100 is not set
-# CONFIG_ARCH_CHIP_MK40X128VMD100 is not set
-# CONFIG_ARCH_CHIP_MK40X256VLQ100 is not set
-# CONFIG_ARCH_CHIP_MK40X256VMD100 is not set
-# CONFIG_ARCH_CHIP_MK60N256VLQ100 is not set
-# CONFIG_ARCH_CHIP_MK60N256VMD100 is not set
-# CONFIG_ARCH_CHIP_MK60N512VLL100 is not set
-# CONFIG_ARCH_CHIP_MK60N512VLQ100 is not set
-# CONFIG_ARCH_CHIP_MK60N512VMD100 is not set
-# CONFIG_ARCH_CHIP_MK60X256VLQ100 is not set
-# CONFIG_ARCH_CHIP_MK60X256VMD100 is not set
-CONFIG_ARCH_FAMILY_K20=y
-# CONFIG_ARCH_FAMILY_K40 is not set
-# CONFIG_ARCH_FAMILY_K60 is not set
-
-#
-# Kinetis Peripheral Support
-#
-# CONFIG_KINETIS_TRACE is not set
-# CONFIG_KINETIS_FLEXBUS is not set
-CONFIG_KINETIS_UART0=y
-# CONFIG_KINETIS_UART1 is not set
-# CONFIG_KINETIS_UART2 is not set
-# CONFIG_KINETIS_UART3 is not set
-# CONFIG_KINETIS_UART4 is not set
-# CONFIG_KINETIS_UART5 is not set
-# CONFIG_KINETIS_FLEXCAN0 is not set
-# CONFIG_KINETIS_FLEXCAN1 is not set
-# CONFIG_KINETIS_SPI0 is not set
-# CONFIG_KINETIS_SPI1 is not set
-# CONFIG_KINETIS_SPI2 is not set
-# CONFIG_KINETIS_I2C0 is not set
-# CONFIG_KINETIS_I2C1 is not set
-# CONFIG_KINETIS_I2S is not set
-# CONFIG_KINETIS_DAC0 is not set
-# CONFIG_KINETIS_DAC1 is not set
-# CONFIG_KINETIS_ADC0 is not set
-# CONFIG_KINETIS_ADC1 is not set
-# CONFIG_KINETIS_CMP is not set
-# CONFIG_KINETIS_VREF is not set
-# CONFIG_KINETIS_SDHC is not set
-# CONFIG_KINETIS_FTM0 is not set
-# CONFIG_KINETIS_FTM1 is not set
-# CONFIG_KINETIS_FTM2 is not set
-# CONFIG_KINETIS_LPTIMER is not set
-# CONFIG_KINETIS_RTC is not set
-# CONFIG_KINETIS_EWM is not set
-# CONFIG_KINETIS_CMT is not set
-CONFIG_KINETIS_USBOTG=y
-# CONFIG_KINETIS_USBDCD is not set
-# CONFIG_KINETIS_LLWU is not set
-# CONFIG_KINETIS_TSI is not set
-# CONFIG_KINETIS_FTFL is not set
-# CONFIG_KINETIS_DMA is not set
-# CONFIG_KINETIS_CRC is not set
-# CONFIG_KINETIS_PDB is not set
-# CONFIG_KINETIS_PIT is not set
-
-#
-# Kinetis GPIO Interrupt Configuration
-#
-# CONFIG_GPIO_IRQ is not set
-
-#
-# Kinetis UART Configuration
-#
-CONFIG_KINETIS_UARTFIFOS=y
-
-#
-# Architecture Options
-#
-# CONFIG_ARCH_NOINTC is not set
-# CONFIG_ARCH_VECNOTIRQ is not set
-# CONFIG_ARCH_DMA is not set
-CONFIG_ARCH_HAVE_IRQPRIO=y
-# CONFIG_ARCH_L2CACHE is not set
-# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set
-# CONFIG_ARCH_HAVE_ADDRENV is not set
-# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set
-# CONFIG_ARCH_HAVE_MULTICPU is not set
-CONFIG_ARCH_HAVE_VFORK=y
-# CONFIG_ARCH_HAVE_MMU is not set
-CONFIG_ARCH_HAVE_MPU=y
-# CONFIG_ARCH_NAND_HWECC is not set
-# CONFIG_ARCH_HAVE_EXTCLK is not set
-# CONFIG_ARCH_HAVE_POWEROFF is not set
-CONFIG_ARCH_HAVE_RESET=y
-# CONFIG_ARCH_USE_MPU is not set
-# CONFIG_ARCH_IRQPRIO is not set
-CONFIG_ARCH_STACKDUMP=y
-# CONFIG_ARCH_USBDUMP is not set
-# CONFIG_ENDIAN_BIG is not set
-# CONFIG_ARCH_IDLE_CUSTOM is not set
-CONFIG_ARCH_HAVE_RAMFUNCS=y
-CONFIG_ARCH_RAMFUNCS=y
-CONFIG_ARCH_HAVE_RAMVECTORS=y
-# CONFIG_ARCH_RAMVECTORS is not set
-
-#
-# Board Settings
-#
-CONFIG_BOARD_LOOPSPERMSEC=6024
-# CONFIG_ARCH_CALIBRATION is not set
-
-#
-# Interrupt options
-#
-CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
-CONFIG_ARCH_INTERRUPTSTACK=0
-CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y
-# CONFIG_ARCH_HIPRI_INTERRUPT is not set
-
-#
-# Boot options
-#
-# CONFIG_BOOT_RUNFROMEXTSRAM is not set
-CONFIG_BOOT_RUNFROMFLASH=y
-# CONFIG_BOOT_RUNFROMISRAM is not set
-# CONFIG_BOOT_RUNFROMSDRAM is not set
-# CONFIG_BOOT_COPYTORAM is not set
-
-#
-# Boot Memory Configuration
-#
-CONFIG_RAM_START=0x1fff8000
-CONFIG_RAM_SIZE=65536
-# CONFIG_ARCH_HAVE_SDRAM is not set
-
-#
-# Board Selection
-#
-CONFIG_ARCH_BOARD_TEENSY_3X=y
-# CONFIG_ARCH_BOARD_CUSTOM is not set
-CONFIG_ARCH_BOARD="teensy-3.x"
-
-#
-# Common Board Options
-#
-CONFIG_ARCH_HAVE_LEDS=y
-CONFIG_ARCH_LEDS=y
-CONFIG_NSH_MMCSDMINOR=0
-
-#
-# Board-Specific Options
-#
-# CONFIG_TEENSY_3X_OVERCLOCK is not set
-CONFIG_LIB_BOARDCTL=y
-# CONFIG_BOARDCTL_RESET is not set
-# CONFIG_BOARDCTL_UNIQUEID is not set
-CONFIG_BOARDCTL_USBDEVCTRL=y
-# CONFIG_BOARDCTL_TSCTEST is not set
-# CONFIG_BOARDCTL_ADCTEST is not set
-# CONFIG_BOARDCTL_PWMTEST is not set
-# CONFIG_BOARDCTL_GRAPHICS is not set
-# CONFIG_BOARDCTL_IOCTL is not set
-
-#
-# RTOS Features
-#
-CONFIG_DISABLE_OS_API=y
-# CONFIG_DISABLE_POSIX_TIMERS is not set
-# CONFIG_DISABLE_PTHREAD is not set
-# CONFIG_DISABLE_SIGNALS is not set
-# CONFIG_DISABLE_MQUEUE is not set
-# CONFIG_DISABLE_ENVIRON is not set
-
-#
-# Clocks and Timers
-#
-CONFIG_USEC_PER_TICK=10000
-# CONFIG_SYSTEM_TIME64 is not set
-# CONFIG_CLOCK_MONOTONIC is not set
-# CONFIG_JULIAN_TIME is not set
-CONFIG_START_YEAR=2011
-CONFIG_START_MONTH=12
-CONFIG_START_DAY=6
-CONFIG_MAX_WDOGPARMS=2
-CONFIG_PREALLOC_WDOGS=16
-CONFIG_WDOG_INTRESERVE=4
-CONFIG_PREALLOC_TIMERS=4
-
-#
-# Tasks and Scheduling
-#
-# CONFIG_SPINLOCK is not set
-# CONFIG_INIT_NONE is not set
-CONFIG_INIT_ENTRYPOINT=y
-# CONFIG_INIT_FILEPATH is not set
-CONFIG_USER_ENTRYPOINT="nsh_main"
-CONFIG_RR_INTERVAL=200
-# CONFIG_SCHED_SPORADIC is not set
-CONFIG_TASK_NAME_SIZE=0
-CONFIG_MAX_TASKS=16
-# CONFIG_SCHED_HAVE_PARENT is not set
-CONFIG_SCHED_WAITPID=y
-
-#
-# Pthread Options
-#
-# CONFIG_MUTEX_TYPES is not set
-CONFIG_NPTHREAD_KEYS=4
-
-#
-# Performance Monitoring
-#
-# CONFIG_SCHED_CPULOAD is not set
-# CONFIG_SCHED_INSTRUMENTATION is not set
-
-#
-# Files and I/O
-#
-CONFIG_DEV_CONSOLE=y
-# CONFIG_FDCLONE_DISABLE is not set
-# CONFIG_FDCLONE_STDIO is not set
-CONFIG_SDCLONE_DISABLE=y
-CONFIG_NFILE_DESCRIPTORS=8
-CONFIG_NFILE_STREAMS=8
-CONFIG_NAME_MAX=32
-# CONFIG_PRIORITY_INHERITANCE is not set
-
-#
-# RTOS hooks
-#
-# CONFIG_BOARD_INITIALIZE is not set
-# CONFIG_SCHED_STARTHOOK is not set
-# CONFIG_SCHED_ATEXIT is not set
-# CONFIG_SCHED_ONEXIT is not set
-
-#
-# Signal Numbers
-#
-CONFIG_SIG_SIGUSR1=1
-CONFIG_SIG_SIGUSR2=2
-CONFIG_SIG_SIGALARM=3
-CONFIG_SIG_SIGCONDTIMEDOUT=16
-
-#
-# POSIX Message Queue Options
-#
-CONFIG_PREALLOC_MQ_MSGS=4
-CONFIG_MQ_MAXMSGSIZE=32
-# CONFIG_MODULE is not set
-
-#
-# Work queue support
-#
-# CONFIG_SCHED_WORKQUEUE is not set
-# CONFIG_SCHED_HPWORK is not set
-# CONFIG_SCHED_LPWORK is not set
-
-#
-# Stack and heap information
-#
-CONFIG_IDLETHREAD_STACKSIZE=1024
-CONFIG_USERMAIN_STACKSIZE=2048
-CONFIG_PTHREAD_STACK_MIN=256
-CONFIG_PTHREAD_STACK_DEFAULT=2048
-# CONFIG_LIB_SYSCALL is not set
-
-#
-# Device Drivers
-#
-CONFIG_DISABLE_POLL=y
-CONFIG_DEV_NULL=y
-# CONFIG_DEV_ZERO is not set
-# CONFIG_DEV_LOOP is not set
-
-#
-# Buffering
-#
-# CONFIG_DRVR_WRITEBUFFER is not set
-# CONFIG_DRVR_READAHEAD is not set
-# CONFIG_RAMDISK is not set
-# CONFIG_CAN is not set
-# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set
-# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set
-# CONFIG_PWM is not set
-# CONFIG_ARCH_HAVE_I2CRESET is not set
-# CONFIG_I2C is not set
-CONFIG_SPI=y
-# CONFIG_SPI_SLAVE is not set
-CONFIG_SPI_EXCHANGE=y
-# CONFIG_SPI_CMDDATA is not set
-# CONFIG_SPI_CALLBACK is not set
-# CONFIG_SPI_BITBANG is not set
-# CONFIG_SPI_HWFEATURES is not set
-# CONFIG_SPI_CRCGENERATION is not set
-# CONFIG_I2S is not set
-
-#
-# Timer Driver Support
-#
-# CONFIG_TIMER is not set
-# CONFIG_RTC is not set
-# CONFIG_WATCHDOG is not set
-# CONFIG_ANALOG is not set
-# CONFIG_AUDIO_DEVICES is not set
-# CONFIG_VIDEO_DEVICES is not set
-# CONFIG_BCH is not set
-# CONFIG_INPUT is not set
-# CONFIG_IOEXPANDER is not set
-# CONFIG_LCD is not set
-
-#
-# LED Support
-#
-# CONFIG_USERLED is not set
-# CONFIG_RGBLED is not set
-# CONFIG_PCA9635PW is not set
-# CONFIG_MMCSD is not set
-# CONFIG_MODEM is not set
-# CONFIG_MTD is not set
-# CONFIG_EEPROM is not set
-# CONFIG_PIPES is not set
-# CONFIG_PM is not set
-# CONFIG_POWER is not set
-# CONFIG_SENSORS is not set
-# CONFIG_SERCOMM_CONSOLE is not set
-CONFIG_SERIAL=y
-# CONFIG_DEV_LOWCONSOLE is not set
-CONFIG_SERIAL_REMOVABLE=y
-# CONFIG_16550_UART is not set
-# CONFIG_ARCH_HAVE_UART is not set
-CONFIG_ARCH_HAVE_UART0=y
-# CONFIG_ARCH_HAVE_UART1 is not set
-# CONFIG_ARCH_HAVE_UART2 is not set
-# CONFIG_ARCH_HAVE_UART3 is not set
-# CONFIG_ARCH_HAVE_UART4 is not set
-# CONFIG_ARCH_HAVE_UART5 is not set
-# CONFIG_ARCH_HAVE_UART6 is not set
-# CONFIG_ARCH_HAVE_UART7 is not set
-# CONFIG_ARCH_HAVE_UART8 is not set
-# CONFIG_ARCH_HAVE_SCI0 is not set
-# CONFIG_ARCH_HAVE_SCI1 is not set
-# CONFIG_ARCH_HAVE_USART0 is not set
-# CONFIG_ARCH_HAVE_USART1 is not set
-# CONFIG_ARCH_HAVE_USART2 is not set
-# CONFIG_ARCH_HAVE_USART3 is not set
-# CONFIG_ARCH_HAVE_USART4 is not set
-# CONFIG_ARCH_HAVE_USART5 is not set
-# CONFIG_ARCH_HAVE_USART6 is not set
-# CONFIG_ARCH_HAVE_USART7 is not set
-# CONFIG_ARCH_HAVE_USART8 is not set
-# CONFIG_ARCH_HAVE_OTHER_UART is not set
-
-#
-# USART Configuration
-#
-CONFIG_MCU_SERIAL=y
-CONFIG_STANDARD_SERIAL=y
-# CONFIG_SERIAL_IFLOWCONTROL is not set
-# CONFIG_SERIAL_OFLOWCONTROL is not set
-# CONFIG_SERIAL_DMA is not set
-# CONFIG_SERIAL_TIOCSERGSTRUCT is not set
-# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set
-CONFIG_UART0_SERIAL_CONSOLE=y
-# CONFIG_OTHER_SERIAL_CONSOLE is not set
-# CONFIG_NO_SERIAL_CONSOLE is not set
-
-#
-# UART0 Configuration
-#
-CONFIG_UART0_RXBUFSIZE=256
-CONFIG_UART0_TXBUFSIZE=256
-CONFIG_UART0_BAUD=115200
-CONFIG_UART0_BITS=8
-CONFIG_UART0_PARITY=0
-CONFIG_UART0_2STOP=0
-# CONFIG_UART0_IFLOWCONTROL is not set
-# CONFIG_UART0_OFLOWCONTROL is not set
-# CONFIG_UART0_DMA is not set
-CONFIG_USBDEV=y
-
-#
-# USB Device Controller Driver Options
-#
-# CONFIG_USBDEV_ISOCHRONOUS is not set
-CONFIG_USBDEV_DUALSPEED=y
-CONFIG_USBDEV_SELFPOWERED=y
-# CONFIG_USBDEV_BUSPOWERED is not set
-CONFIG_USBDEV_MAXPOWER=100
-# CONFIG_USBDEV_DMA is not set
-# CONFIG_ARCH_USBDEV_STALLQUEUE is not set
-CONFIG_USBDEV_TRACE=y
-CONFIG_USBDEV_TRACE_NRECORDS=128
-CONFIG_USBDEV_TRACE_INITIALIDSET=y
-
-#
-# USB Device Class Driver Options
-#
-# CONFIG_USBDEV_COMPOSITE is not set
-# CONFIG_PL2303 is not set
-CONFIG_CDCACM=y
-# CONFIG_CDCACM_CONSOLE is not set
-# CONFIG_CDCACM_IFLOWCONTROL is not set
-CONFIG_CDCACM_EP0MAXPACKET=64
-CONFIG_CDCACM_EPINTIN=1
-CONFIG_CDCACM_EPINTIN_FSSIZE=64
-CONFIG_CDCACM_EPINTIN_HSSIZE=64
-CONFIG_CDCACM_EPBULKOUT=3
-CONFIG_CDCACM_EPBULKOUT_FSSIZE=64
-CONFIG_CDCACM_EPBULKOUT_HSSIZE=512
-CONFIG_CDCACM_EPBULKIN=2
-CONFIG_CDCACM_EPBULKIN_FSSIZE=64
-CONFIG_CDCACM_EPBULKIN_HSSIZE=512
-CONFIG_CDCACM_NRDREQS=4
-CONFIG_CDCACM_NWRREQS=4
-CONFIG_CDCACM_BULKIN_REQLEN=768
-CONFIG_CDCACM_RXBUFSIZE=513
-CONFIG_CDCACM_TXBUFSIZE=769
-CONFIG_CDCACM_VENDORID=0x0525
-CONFIG_CDCACM_PRODUCTID=0xa4a7
-CONFIG_CDCACM_VENDORSTR="NuttX"
-CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial"
-# CONFIG_USBMSC is not set
-# CONFIG_USBHOST is not set
-# CONFIG_DRIVERS_WIRELESS is not set
-
-#
-# System Logging Device Options
-#
-
-#
-# System Logging
-#
-# CONFIG_RAMLOG is not set
-# CONFIG_SYSLOG_CONSOLE is not set
-
-#
-# Networking Support
-#
-# CONFIG_ARCH_HAVE_NET is not set
-# CONFIG_ARCH_HAVE_PHY is not set
-# CONFIG_NET is not set
-
-#
-# Crypto API
-#
-# CONFIG_CRYPTO is not set
-
-#
-# File Systems
-#
-
-#
-# File system configuration
-#
-# CONFIG_DISABLE_MOUNTPOINT is not set
-# CONFIG_FS_AUTOMOUNTER is not set
-# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set
-# CONFIG_FS_READABLE is not set
-# CONFIG_FS_WRITABLE is not set
-# CONFIG_FS_NAMED_SEMAPHORES is not set
-CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
-# CONFIG_FS_RAMMAP is not set
-# CONFIG_FS_FAT is not set
-# CONFIG_FS_NXFFS is not set
-# CONFIG_FS_ROMFS is not set
-# CONFIG_FS_TMPFS is not set
-# CONFIG_FS_SMARTFS is not set
-# CONFIG_FS_BINFS is not set
-# CONFIG_FS_PROCFS is not set
-# CONFIG_FS_UNIONFS is not set
-
-#
-# System Logging
-#
-# CONFIG_SYSLOG is not set
-# CONFIG_SYSLOG_TIMESTAMP is not set
-
-#
-# Graphics Support
-#
-# CONFIG_NX is not set
-
-#
-# Memory Management
-#
-# CONFIG_MM_SMALL is not set
-CONFIG_MM_REGIONS=1
-# CONFIG_ARCH_HAVE_HEAP2 is not set
-# CONFIG_GRAN is not set
-
-#
-# Audio Support
-#
-# CONFIG_AUDIO is not set
-
-#
-# Wireless Support
-#
-# CONFIG_WIRELESS is not set
-
-#
-# Binary Loader
-#
-# CONFIG_BINFMT_DISABLE is not set
-# CONFIG_BINFMT_EXEPATH is not set
-# CONFIG_NXFLAT is not set
-# CONFIG_ELF is not set
-CONFIG_BUILTIN=y
-# CONFIG_PIC is not set
-# CONFIG_SYMTAB_ORDEREDBYNAME is not set
-
-#
-# Library Routines
-#
-
-#
-# Standard C Library Options
-#
-CONFIG_STDIO_BUFFER_SIZE=64
-CONFIG_STDIO_LINEBUFFER=y
-CONFIG_NUNGET_CHARS=2
-CONFIG_LIB_HOMEDIR="/"
-# CONFIG_LIBM is not set
-# CONFIG_NOPRINTF_FIELDWIDTH is not set
-# CONFIG_LIBC_FLOATINGPOINT is not set
-CONFIG_LIBC_LONG_LONG=y
-# CONFIG_LIBC_IOCTL_VARIADIC is not set
-CONFIG_LIB_RAND_ORDER=1
-# CONFIG_EOL_IS_CR is not set
-# CONFIG_EOL_IS_LF is not set
-# CONFIG_EOL_IS_BOTH_CRLF is not set
-CONFIG_EOL_IS_EITHER_CRLF=y
-# CONFIG_LIBC_EXECFUNCS is not set
-CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024
-CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048
-# CONFIG_LIBC_STRERROR is not set
-# CONFIG_LIBC_PERROR_STDOUT is not set
-CONFIG_ARCH_LOWPUTC=y
-# CONFIG_LIBC_LOCALTIME is not set
-# CONFIG_TIME_EXTENDED is not set
-CONFIG_LIB_SENDFILE_BUFSIZE=512
-# CONFIG_ARCH_ROMGETC is not set
-# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
-CONFIG_ARCH_HAVE_TLS=y
-# CONFIG_TLS is not set
-# CONFIG_LIBC_NETDB is not set
-
-#
-# Non-standard Library Support
-#
-# CONFIG_LIB_KBDCODEC is not set
-# CONFIG_LIB_SLCDCODEC is not set
-
-#
-# Basic CXX Support
-#
-# CONFIG_C99_BOOL8 is not set
-# CONFIG_HAVE_CXX is not set
-
-#
-# Application Configuration
-#
-
-#
-# Built-In Applications
-#
-CONFIG_BUILTIN_PROXY_STACKSIZE=1024
-
-#
-# CAN Utilities
-#
-
-#
-# Examples
-#
-# CONFIG_EXAMPLES_CHAT is not set
-# CONFIG_EXAMPLES_CONFIGDATA is not set
-# CONFIG_EXAMPLES_CPUHOG is not set
-# CONFIG_EXAMPLES_DHCPD is not set
-# CONFIG_EXAMPLES_ELF is not set
-# CONFIG_EXAMPLES_FTPC is not set
-# CONFIG_EXAMPLES_FTPD is not set
-# CONFIG_EXAMPLES_HELLO is not set
-# CONFIG_EXAMPLES_JSON is not set
-# CONFIG_EXAMPLES_HIDKBD is not set
-# CONFIG_EXAMPLES_KEYPADTEST is not set
-# CONFIG_EXAMPLES_IGMP is not set
-# CONFIG_EXAMPLES_MEDIA is not set
-# CONFIG_EXAMPLES_MM is not set
-# CONFIG_EXAMPLES_MODBUS is not set
-# CONFIG_EXAMPLES_MOUNT is not set
-# CONFIG_EXAMPLES_NRF24L01TERM is not set
-CONFIG_EXAMPLES_NSH=y
-# CONFIG_EXAMPLES_NULL is not set
-# CONFIG_EXAMPLES_NX is not set
-# CONFIG_EXAMPLES_NXTERM is not set
-# CONFIG_EXAMPLES_NXFFS is not set
-# CONFIG_EXAMPLES_NXHELLO is not set
-# CONFIG_EXAMPLES_NXIMAGE is not set
-# CONFIG_EXAMPLES_NXLINES is not set
-# CONFIG_EXAMPLES_NXTEXT is not set
-# CONFIG_EXAMPLES_OSTEST is not set
-# CONFIG_EXAMPLES_PCA9635 is not set
-# CONFIG_EXAMPLES_PIPE is not set
-# CONFIG_EXAMPLES_PPPD is not set
-# CONFIG_EXAMPLES_POSIXSPAWN is not set
-# CONFIG_EXAMPLES_RGBLED is not set
-# CONFIG_EXAMPLES_RGMP is not set
-# CONFIG_EXAMPLES_SENDMAIL is not set
-# CONFIG_EXAMPLES_SERIALBLASTER is not set
-# CONFIG_EXAMPLES_SERIALRX is not set
-# CONFIG_EXAMPLES_SERLOOP is not set
-# CONFIG_EXAMPLES_SLCD is not set
-# CONFIG_EXAMPLES_SMART_TEST is not set
-# CONFIG_EXAMPLES_SMART is not set
-# CONFIG_EXAMPLES_SMP is not set
-# CONFIG_EXAMPLES_TCPECHO is not set
-# CONFIG_EXAMPLES_TELNETD is not set
-# CONFIG_EXAMPLES_TIFF is not set
-# CONFIG_EXAMPLES_TOUCHSCREEN is not set
-# CONFIG_EXAMPLES_WEBSERVER is not set
-# CONFIG_EXAMPLES_USBSERIAL is not set
-# CONFIG_EXAMPLES_USBTERM is not set
-# CONFIG_EXAMPLES_WATCHDOG is not set
-
-#
-# File System Utilities
-#
-# CONFIG_FSUTILS_INIFILE is not set
-
-#
-# GPS Utilities
-#
-# CONFIG_GPSUTILS_MINMEA_LIB is not set
-
-#
-# Graphics Support
-#
-# CONFIG_TIFF is not set
-# CONFIG_GRAPHICS_TRAVELER is not set
-
-#
-# Interpreters
-#
-# CONFIG_INTERPRETERS_FICL is not set
-# CONFIG_INTERPRETERS_PCODE is not set
-# CONFIG_INTERPRETERS_MICROPYTHON is not set
-
-#
-# FreeModBus
-#
-# CONFIG_MODBUS is not set
-
-#
-# Network Utilities
-#
-# CONFIG_NETUTILS_CODECS is not set
-# CONFIG_NETUTILS_FTPC is not set
-# CONFIG_NETUTILS_JSON is not set
-# CONFIG_NETUTILS_SMTP is not set
-
-#
-# NSH Library
-#
-CONFIG_NSH_LIBRARY=y
-# CONFIG_NSH_MOTD is not set
-
-#
-# Command Line Configuration
-#
-CONFIG_NSH_READLINE=y
-# CONFIG_NSH_CLE is not set
-CONFIG_NSH_LINELEN=64
-# CONFIG_NSH_DISABLE_SEMICOLON is not set
-# CONFIG_NSH_CMDPARMS is not set
-CONFIG_NSH_MAXARGUMENTS=6
-# CONFIG_NSH_ARGCAT is not set
-CONFIG_NSH_NESTDEPTH=3
-# CONFIG_NSH_DISABLEBG is not set
-CONFIG_NSH_BUILTIN_APPS=y
-
-#
-# Disable Individual commands
-#
-# CONFIG_NSH_DISABLE_ADDROUTE is not set
-# CONFIG_NSH_DISABLE_BASENAME is not set
-# CONFIG_NSH_DISABLE_CAT is not set
-# CONFIG_NSH_DISABLE_CD is not set
-# CONFIG_NSH_DISABLE_CP is not set
-# CONFIG_NSH_DISABLE_CMP is not set
-CONFIG_NSH_DISABLE_DATE=y
-# CONFIG_NSH_DISABLE_DD is not set
-# CONFIG_NSH_DISABLE_DF is not set
-# CONFIG_NSH_DISABLE_DELROUTE is not set
-# CONFIG_NSH_DISABLE_DIRNAME is not set
-# CONFIG_NSH_DISABLE_ECHO is not set
-# CONFIG_NSH_DISABLE_EXEC is not set
-# CONFIG_NSH_DISABLE_EXIT is not set
-# CONFIG_NSH_DISABLE_FREE is not set
-# CONFIG_NSH_DISABLE_GET is not set
-# CONFIG_NSH_DISABLE_HELP is not set
-# CONFIG_NSH_DISABLE_HEXDUMP is not set
-# CONFIG_NSH_DISABLE_IFCONFIG is not set
-CONFIG_NSH_DISABLE_IFUPDOWN=y
-# CONFIG_NSH_DISABLE_KILL is not set
-# CONFIG_NSH_DISABLE_LOSETUP is not set
-CONFIG_NSH_DISABLE_LOSMART=y
-# CONFIG_NSH_DISABLE_LS is not set
-# CONFIG_NSH_DISABLE_MB is not set
-# CONFIG_NSH_DISABLE_MKDIR is not set
-# CONFIG_NSH_DISABLE_MKFIFO is not set
-# CONFIG_NSH_DISABLE_MKRD is not set
-# CONFIG_NSH_DISABLE_MH is not set
-# CONFIG_NSH_DISABLE_MOUNT is not set
-# CONFIG_NSH_DISABLE_MV is not set
-# CONFIG_NSH_DISABLE_MW is not set
-# CONFIG_NSH_DISABLE_PS is not set
-# CONFIG_NSH_DISABLE_PUT is not set
-# CONFIG_NSH_DISABLE_PWD is not set
-# CONFIG_NSH_DISABLE_RM is not set
-# CONFIG_NSH_DISABLE_RMDIR is not set
-# CONFIG_NSH_DISABLE_SET is not set
-# CONFIG_NSH_DISABLE_SH is not set
-# CONFIG_NSH_DISABLE_SLEEP is not set
-# CONFIG_NSH_DISABLE_TIME is not set
-# CONFIG_NSH_DISABLE_TEST is not set
-# CONFIG_NSH_DISABLE_UMOUNT is not set
-# CONFIG_NSH_DISABLE_UNAME is not set
-# CONFIG_NSH_DISABLE_UNSET is not set
-# CONFIG_NSH_DISABLE_USLEEP is not set
-# CONFIG_NSH_DISABLE_WGET is not set
-# CONFIG_NSH_DISABLE_XD is not set
-
-#
-# Configure Command Options
-#
-# CONFIG_NSH_CMDOPT_DF_H is not set
-CONFIG_NSH_CODECS_BUFSIZE=128
-# CONFIG_NSH_CMDOPT_HEXDUMP is not set
-CONFIG_NSH_FILEIOSIZE=512
-
-#
-# Scripting Support
-#
-# CONFIG_NSH_DISABLESCRIPT is not set
-# CONFIG_NSH_DISABLE_ITEF is not set
-# CONFIG_NSH_DISABLE_LOOPS is not set
-
-#
-# Console Configuration
-#
-CONFIG_NSH_CONSOLE=y
-CONFIG_NSH_USBCONSOLE=y
-CONFIG_NSH_USBCONDEV="/dev/ttyACM0"
-CONFIG_USBDEV_MINOR=0
-
-#
-# USB Device Trace Support
-#
-# CONFIG_NSH_USBDEV_TRACE is not set
-CONFIG_NSH_ARCHINIT=y
-# CONFIG_NSH_LOGIN is not set
-# CONFIG_NSH_CONSOLE_LOGIN is not set
-
-#
-# NxWidgets/NxWM
-#
-
-#
-# Platform-specific Support
-#
-# CONFIG_PLATFORM_CONFIGDATA is not set
-
-#
-# System Libraries and NSH Add-Ons
-#
-# CONFIG_SYSTEM_FREE is not set
-# CONFIG_SYSTEM_CLE is not set
-# CONFIG_SYSTEM_CUTERM is not set
-# CONFIG_SYSTEM_INSTALL is not set
-# CONFIG_SYSTEM_HEX2BIN is not set
-CONFIG_SYSTEM_HEXED=y
-CONFIG_SYSTEM_HEXED_STACKSIZE=2048
-CONFIG_SYSTEM_HEXED_PRIORITY=100
-CONFIG_SYSTEM_RAMTEST=y
-CONFIG_READLINE_HAVE_EXTMATCH=y
-CONFIG_SYSTEM_READLINE=y
-CONFIG_READLINE_ECHO=y
-CONFIG_READLINE_TABCOMPLETION=y
-CONFIG_READLINE_MAX_BUILTINS=64
-CONFIG_READLINE_MAX_EXTCMDS=64
-CONFIG_READLINE_CMD_HISTORY=y
-CONFIG_READLINE_CMD_HISTORY_LINELEN=80
-CONFIG_READLINE_CMD_HISTORY_LEN=16
-# CONFIG_SYSTEM_SDCARD is not set
-# CONFIG_SYSTEM_SUDOKU is not set
-# CONFIG_SYSTEM_VI is not set
-CONFIG_SYSTEM_CDCACM=y
-CONFIG_SYSTEM_CDCACM_DEVMINOR=0
-# CONFIG_SYSTEM_CDCACM_TRACEINIT is not set
-# CONFIG_SYSTEM_CDCACM_TRACECLASS is not set
-# CONFIG_SYSTEM_CDCACM_TRACETRANSFERS is not set
-# CONFIG_SYSTEM_CDCACM_TRACECONTROLLER is not set
-# CONFIG_SYSTEM_CDCACM_TRACEINTERRUPTS is not set
-# CONFIG_SYSTEM_UBLOXMODEM is not set
-CONFIG_SYSTEM_USBMONITOR=y
-CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048
-CONFIG_SYSTEM_USBMONITOR_PRIORITY=50
-CONFIG_SYSTEM_USBMONITOR_INTERVAL=2
-CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y
-CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y
-CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y
-CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y
-CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y
-# CONFIG_SYSTEM_ZMODEM is not set
diff --git a/configs/teensy-3.x/usbnsh/Make.defs b/configs/teensy-3.x/usbnsh/Make.defs
index 597d2e8cf3..e750c7b570 100644
--- a/configs/teensy-3.x/usbnsh/Make.defs
+++ b/configs/teensy-3.x/usbnsh/Make.defs
@@ -1,7 +1,7 @@
############################################################################
# configs/teensy-3.1/nsh/Make.defs
#
-# Copyright (C) 2015 Gregory Nutt. All rights reserved.
+# Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt
#
# Redistribution and use in source and binary forms, with or without
@@ -114,4 +114,3 @@ HOSTCC = gcc
HOSTINCLUDES = -I.
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
HOSTLDFLAGS =
-
diff --git a/configs/teensy-3.x/usbnsh/defconfig b/configs/teensy-3.x/usbnsh/defconfig
index 0f0f54c88e..1e750e8e6f 100644
--- a/configs/teensy-3.x/usbnsh/defconfig
+++ b/configs/teensy-3.x/usbnsh/defconfig
@@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y
#
# Build Configuration
#
-CONFIG_APPS_DIR="../apps"
+# CONFIG_APPS_DIR="../apps"
CONFIG_BUILD_FLAT=y
# CONFIG_BUILD_2PASS is not set
@@ -42,36 +42,11 @@ CONFIG_RAW_BINARY=y
#
# Debug Options
#
-CONFIG_DEBUG=y
+# CONFIG_DEBUG is not set
# CONFIG_ARCH_HAVE_HEAPCHECK is not set
-# CONFIG_DEBUG_VERBOSE is not set
-
-#
-# Subsystem Debug Options
-#
-# CONFIG_DEBUG_BINFMT is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_DEBUG_GRAPHICS is not set
-# CONFIG_DEBUG_LIB is not set
-# CONFIG_DEBUG_MM is not set
-# CONFIG_DEBUG_SCHED is not set
-
-#
-# OS Function Debug Options
-#
-# CONFIG_DEBUG_IRQ is not set
-
-#
-# Driver Debug Options
-#
-# CONFIG_DEBUG_LEDS is not set
-# CONFIG_DEBUG_ANALOG is not set
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_DEBUG_SPI is not set
-# CONFIG_DEBUG_USB is not set
CONFIG_ARCH_HAVE_STACKCHECK=y
# CONFIG_STACK_COLORATION is not set
-CONFIG_DEBUG_SYMBOLS=y
+# CONFIG_DEBUG_SYMBOLS is not set
CONFIG_ARCH_HAVE_CUSTOMOPT=y
# CONFIG_DEBUG_NOOPT is not set
# CONFIG_DEBUG_CUSTOMOPT is not set
@@ -142,6 +117,8 @@ CONFIG_ARCH_CORTEXM4=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARCH_CHIP="kinetis"
+# CONFIG_ARM_TOOLCHAIN_IAR is not set
+CONFIG_ARM_TOOLCHAIN_GNU=y
# CONFIG_ARMV7M_USEBASEPRI is not set
CONFIG_ARCH_HAVE_FPU=y
# CONFIG_ARCH_HAVE_DPFPU is not set
@@ -149,7 +126,6 @@ CONFIG_ARCH_HAVE_FPU=y
# CONFIG_ARCH_HAVE_TRUSTZONE is not set
CONFIG_ARM_HAVE_MPU_UNIFIED=y
# CONFIG_ARM_MPU is not set
-# CONFIG_DEBUG_HARDFAULT is not set
#
# ARMV7M Configuration Options
@@ -158,6 +134,7 @@ CONFIG_ARM_HAVE_MPU_UNIFIED=y
# CONFIG_ARMV7M_HAVE_DCACHE is not set
# CONFIG_ARMV7M_HAVE_ITCM is not set
# CONFIG_ARMV7M_HAVE_DTCM is not set
+# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set
# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
@@ -480,7 +457,12 @@ CONFIG_SPI_EXCHANGE=y
# CONFIG_BCH is not set
# CONFIG_INPUT is not set
# CONFIG_IOEXPANDER is not set
+
+#
+# LCD Driver Support
+#
# CONFIG_LCD is not set
+# CONFIG_SLCD is not set
#
# LED Support
@@ -501,38 +483,33 @@ CONFIG_SERIAL=y
# CONFIG_DEV_LOWCONSOLE is not set
CONFIG_SERIAL_REMOVABLE=y
# CONFIG_16550_UART is not set
-# CONFIG_ARCH_HAVE_UART is not set
-CONFIG_ARCH_HAVE_UART0=y
-# CONFIG_ARCH_HAVE_UART1 is not set
-# CONFIG_ARCH_HAVE_UART2 is not set
-# CONFIG_ARCH_HAVE_UART3 is not set
-# CONFIG_ARCH_HAVE_UART4 is not set
-# CONFIG_ARCH_HAVE_UART5 is not set
-# CONFIG_ARCH_HAVE_UART6 is not set
-# CONFIG_ARCH_HAVE_UART7 is not set
-# CONFIG_ARCH_HAVE_UART8 is not set
-# CONFIG_ARCH_HAVE_SCI0 is not set
-# CONFIG_ARCH_HAVE_SCI1 is not set
-# CONFIG_ARCH_HAVE_USART0 is not set
-# CONFIG_ARCH_HAVE_USART1 is not set
-# CONFIG_ARCH_HAVE_USART2 is not set
-# CONFIG_ARCH_HAVE_USART3 is not set
-# CONFIG_ARCH_HAVE_USART4 is not set
-# CONFIG_ARCH_HAVE_USART5 is not set
-# CONFIG_ARCH_HAVE_USART6 is not set
-# CONFIG_ARCH_HAVE_USART7 is not set
-# CONFIG_ARCH_HAVE_USART8 is not set
-# CONFIG_ARCH_HAVE_OTHER_UART is not set
-
-#
-# USART Configuration
-#
+# CONFIG_UART_SERIALDRIVER is not set
+CONFIG_UART0_SERIALDRIVER=y
+# CONFIG_UART1_SERIALDRIVER is not set
+# CONFIG_UART2_SERIALDRIVER is not set
+# CONFIG_UART3_SERIALDRIVER is not set
+# CONFIG_UART4_SERIALDRIVER is not set
+# CONFIG_UART5_SERIALDRIVER is not set
+# CONFIG_UART6_SERIALDRIVER is not set
+# CONFIG_UART7_SERIALDRIVER is not set
+# CONFIG_UART8_SERIALDRIVER is not set
+# CONFIG_SCI0_SERIALDRIVER is not set
+# CONFIG_SCI1_SERIALDRIVER is not set
+# CONFIG_USART0_SERIALDRIVER is not set
+# CONFIG_USART1_SERIALDRIVER is not set
+# CONFIG_USART2_SERIALDRIVER is not set
+# CONFIG_USART3_SERIALDRIVER is not set
+# CONFIG_USART4_SERIALDRIVER is not set
+# CONFIG_USART5_SERIALDRIVER is not set
+# CONFIG_USART6_SERIALDRIVER is not set
+# CONFIG_USART7_SERIALDRIVER is not set
+# CONFIG_USART8_SERIALDRIVER is not set
+# CONFIG_OTHER_UART_SERIALDRIVER is not set
CONFIG_MCU_SERIAL=y
CONFIG_STANDARD_SERIAL=y
# CONFIG_SERIAL_IFLOWCONTROL is not set
# CONFIG_SERIAL_OFLOWCONTROL is not set
# CONFIG_SERIAL_DMA is not set
-# CONFIG_SERIAL_TIOCSERGSTRUCT is not set
# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set
CONFIG_UART0_SERIAL_CONSOLE=y
# CONFIG_OTHER_SERIAL_CONSOLE is not set
@@ -755,10 +732,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
# CONFIG_EXAMPLES_FTPC is not set
# CONFIG_EXAMPLES_FTPD is not set
# CONFIG_EXAMPLES_HELLO is not set
-# CONFIG_EXAMPLES_JSON is not set
# CONFIG_EXAMPLES_HIDKBD is not set
-# CONFIG_EXAMPLES_KEYPADTEST is not set
# CONFIG_EXAMPLES_IGMP is not set
+# CONFIG_EXAMPLES_JSON is not set
+# CONFIG_EXAMPLES_KEYPADTEST is not set
# CONFIG_EXAMPLES_MEDIA is not set
# CONFIG_EXAMPLES_MM is not set
# CONFIG_EXAMPLES_MODBUS is not set
@@ -767,17 +744,17 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
CONFIG_EXAMPLES_NSH=y
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
-# CONFIG_EXAMPLES_NXTERM is not set
# CONFIG_EXAMPLES_NXFFS is not set
# CONFIG_EXAMPLES_NXHELLO is not set
# CONFIG_EXAMPLES_NXIMAGE is not set
# CONFIG_EXAMPLES_NXLINES is not set
+# CONFIG_EXAMPLES_NXTERM is not set
# CONFIG_EXAMPLES_NXTEXT is not set
# CONFIG_EXAMPLES_OSTEST is not set
# CONFIG_EXAMPLES_PCA9635 is not set
# CONFIG_EXAMPLES_PIPE is not set
-# CONFIG_EXAMPLES_PPPD is not set
# CONFIG_EXAMPLES_POSIXSPAWN is not set
+# CONFIG_EXAMPLES_PPPD is not set
# CONFIG_EXAMPLES_RGBLED is not set
# CONFIG_EXAMPLES_RGMP is not set
# CONFIG_EXAMPLES_SENDMAIL is not set
@@ -785,17 +762,17 @@ CONFIG_EXAMPLES_NSH=y
# CONFIG_EXAMPLES_SERIALRX is not set
# CONFIG_EXAMPLES_SERLOOP is not set
# CONFIG_EXAMPLES_SLCD is not set
-# CONFIG_EXAMPLES_SMART_TEST is not set
# CONFIG_EXAMPLES_SMART is not set
+# CONFIG_EXAMPLES_SMART_TEST is not set
# CONFIG_EXAMPLES_SMP is not set
# CONFIG_EXAMPLES_TCPECHO is not set
# CONFIG_EXAMPLES_TELNETD is not set
# CONFIG_EXAMPLES_TIFF is not set
# CONFIG_EXAMPLES_TOUCHSCREEN is not set
-# CONFIG_EXAMPLES_WEBSERVER is not set
# CONFIG_EXAMPLES_USBSERIAL is not set
# CONFIG_EXAMPLES_USBTERM is not set
# CONFIG_EXAMPLES_WATCHDOG is not set
+# CONFIG_EXAMPLES_WEBSERVER is not set
#
# File System Utilities
@@ -817,8 +794,8 @@ CONFIG_EXAMPLES_NSH=y
# Interpreters
#
# CONFIG_INTERPRETERS_FICL is not set
-# CONFIG_INTERPRETERS_PCODE is not set
# CONFIG_INTERPRETERS_MICROPYTHON is not set
+# CONFIG_INTERPRETERS_PCODE is not set
#
# FreeModBus
@@ -829,6 +806,7 @@ CONFIG_EXAMPLES_NSH=y
# Network Utilities
#
# CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_ESP8266 is not set
# CONFIG_NETUTILS_FTPC is not set
# CONFIG_NETUTILS_JSON is not set
# CONFIG_NETUTILS_SMTP is not set
@@ -948,14 +926,21 @@ CONFIG_NSH_ARCHINIT=y
#
# System Libraries and NSH Add-Ons
#
-# CONFIG_SYSTEM_FREE is not set
+CONFIG_SYSTEM_CDCACM=y
+CONFIG_SYSTEM_CDCACM_DEVMINOR=0
+# CONFIG_SYSTEM_CDCACM_TRACEINIT is not set
+# CONFIG_SYSTEM_CDCACM_TRACECLASS is not set
+# CONFIG_SYSTEM_CDCACM_TRACETRANSFERS is not set
+# CONFIG_SYSTEM_CDCACM_TRACECONTROLLER is not set
+# CONFIG_SYSTEM_CDCACM_TRACEINTERRUPTS is not set
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
-# CONFIG_SYSTEM_INSTALL is not set
+# CONFIG_SYSTEM_FREE is not set
# CONFIG_SYSTEM_HEX2BIN is not set
CONFIG_SYSTEM_HEXED=y
CONFIG_SYSTEM_HEXED_STACKSIZE=2048
CONFIG_SYSTEM_HEXED_PRIORITY=100
+# CONFIG_SYSTEM_INSTALL is not set
CONFIG_SYSTEM_RAMTEST=y
CONFIG_READLINE_HAVE_EXTMATCH=y
CONFIG_SYSTEM_READLINE=y
@@ -966,16 +951,7 @@ CONFIG_READLINE_MAX_EXTCMDS=64
CONFIG_READLINE_CMD_HISTORY=y
CONFIG_READLINE_CMD_HISTORY_LINELEN=80
CONFIG_READLINE_CMD_HISTORY_LEN=16
-# CONFIG_SYSTEM_SDCARD is not set
# CONFIG_SYSTEM_SUDOKU is not set
-# CONFIG_SYSTEM_VI is not set
-CONFIG_SYSTEM_CDCACM=y
-CONFIG_SYSTEM_CDCACM_DEVMINOR=0
-# CONFIG_SYSTEM_CDCACM_TRACEINIT is not set
-# CONFIG_SYSTEM_CDCACM_TRACECLASS is not set
-# CONFIG_SYSTEM_CDCACM_TRACETRANSFERS is not set
-# CONFIG_SYSTEM_CDCACM_TRACECONTROLLER is not set
-# CONFIG_SYSTEM_CDCACM_TRACEINTERRUPTS is not set
# CONFIG_SYSTEM_UBLOXMODEM is not set
CONFIG_SYSTEM_USBMONITOR=y
CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048
@@ -986,4 +962,5 @@ CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y
CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y
CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y
CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y
+# CONFIG_SYSTEM_VI is not set
# CONFIG_SYSTEM_ZMODEM is not set
diff --git a/configs/teensy-3.x/usbnsh/setenv.sh b/configs/teensy-3.x/usbnsh/setenv.sh
index e96a2ff345..dedab5191e 100755
--- a/configs/teensy-3.x/usbnsh/setenv.sh
+++ b/configs/teensy-3.x/usbnsh/setenv.sh
@@ -1,7 +1,7 @@
#!/bin/bash
# configs/teensy-3.1/nsh/setenv.sh
#
-# Copyright (C) 2015 Gregory Nutt. All rights reserved.
+# Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt
#
# Redistribution and use in source and binary forms, with or without
@@ -62,13 +62,9 @@ fi
# You can this free toolchain here https://launchpad.net/gcc-arm-embedded
export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin"
-# These are the Cygwin paths to the locations where I installed the Atollic
-# toolchain under windows. You will also have to edit this if you install
-# the Atollic toolchain in any other location. /usr/bin is added before
-# the Atollic bin path because there is are binaries named gcc.exe and g++.exe
-# at those locations as well.
-#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin"
-#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin"
+# This is the path to the location where I installed the devkitARM toolchain
+# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin"
# This is the Cygwin path to the location where I build the buildroot
# toolchain.
--
GitLab
From 3fc7b6f0e5875efcf92359541ecebaf234f630ae Mon Sep 17 00:00:00 2001
From: Konstantin Berezenko
Date: Mon, 6 Jun 2016 12:29:24 -0700
Subject: [PATCH 077/400] Add stm32f105r support
---
arch/arm/include/stm32/chip.h | 37 +++
arch/arm/src/stm32/Kconfig | 10 +
arch/arm/src/stm32/chip.h | 3 +
arch/arm/src/stm32/chip/stm32f105r_pinmap.h | 328 ++++++++++++++++++++
arch/arm/src/stm32/chip/stm32f105v_pinmap.h | 38 ---
5 files changed, 378 insertions(+), 38 deletions(-)
create mode 100644 arch/arm/src/stm32/chip/stm32f105r_pinmap.h
diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h
index 0a920ccee0..e476bff892 100644
--- a/arch/arm/include/stm32/chip.h
+++ b/arch/arm/include/stm32/chip.h
@@ -903,6 +903,43 @@
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
+#elif defined(CONFIG_ARCH_CHIP_STM32F105RB)
+# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
+# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
+# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
+# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
+# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
+# undef CONFIG_STM32_VALUELINE /* STM32F100x */
+# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
+# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
+# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
+# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
+# define STM32_NFSMC 1 /* FSMC */
+# define STM32_NATIM 1 /* One advanced timers TIM1 */
+# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
+# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
+# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define STM32_NDMA 2 /* DMA1-2 */
+# define STM32_NSPI 3 /* SPI1-3 */
+# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define STM32_NUSART 5 /* USART1-3, UART 4-5 */
+# define STM32_NI2C 2 /* I2C1-2 */
+# define STM32_NCAN 2 /* CAN1-2 */
+# define STM32_NSDIO 0 /* No SDIO */
+# define STM32_NLCD 0 /* No LCD */
+# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
+# define STM32_NGPIO 51 /* GPIOA-E */
+# define STM32_NADC 2 /* ADC1-2 */
+# define STM32_NDAC 2 /* DAC1-2 */
+# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define STM32_NCRC 1 /* CRC */
+# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */
+# define STM32_NRNG 0 /* No random number generator (RNG) */
+# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
+
#elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig
index c871fdf30c..a9b89773ea 100644
--- a/arch/arm/src/stm32/Kconfig
+++ b/arch/arm/src/stm32/Kconfig
@@ -484,6 +484,16 @@ config ARCH_CHIP_STM32F105VB
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
+config ARCH_CHIP_STM32F105RB
+ bool "STM32F105RB"
+ select ARCH_CORTEXM3
+ select STM32_STM32F10XX
+ select STM32_CONNECTIVITYLINE
+ select STM32_HAVE_DAC1
+ select STM32_HAVE_DAC2
+ select STM32_HAVE_I2C2
+ select STM32_HAVE_TIM4
+
config ARCH_CHIP_STM32F107VC
bool "STM32F107VC"
select ARCH_CORTEXM3
diff --git a/arch/arm/src/stm32/chip.h b/arch/arm/src/stm32/chip.h
index bba330edfa..4542a3885f 100644
--- a/arch/arm/src/stm32/chip.h
+++ b/arch/arm/src/stm32/chip.h
@@ -109,6 +109,9 @@
# elif defined(CONFIG_ARCH_CHIP_STM32F105VB)
# include "chip/stm32f105v_pinmap.h"
+# elif defined(CONFIG_ARCH_CHIP_STM32F105RB)
+# include "chip/stm32f105r_pinmap.h"
+
# elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
# include "chip/stm32f107v_pinmap.h"
# else
diff --git a/arch/arm/src/stm32/chip/stm32f105r_pinmap.h b/arch/arm/src/stm32/chip/stm32f105r_pinmap.h
new file mode 100644
index 0000000000..ffd3ef35c4
--- /dev/null
+++ b/arch/arm/src/stm32/chip/stm32f105r_pinmap.h
@@ -0,0 +1,328 @@
+/************************************************************************************
+ * arch/arm/src/stm32/chip/stm32f105r_pinmap.h
+ *
+ * Copyright (C) 2009, 2011, 2014, 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F105R_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_CHIP_STM32F105R_PINMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include "stm32_gpio.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Alternate Pin Functions: */
+
+#define GPIO_ADC12_IN0 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_ADC12_IN1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_ADC12_IN10 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
+#define GPIO_ADC12_IN11 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
+#define GPIO_ADC12_IN12 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
+#define GPIO_ADC12_IN13 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)
+#define GPIO_ADC12_IN14 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN4)
+#define GPIO_ADC12_IN15 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5)
+#define GPIO_ADC12_IN2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_ADC12_IN3 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_ADC12_IN4 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_ADC12_IN5 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_ADC12_IN6 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_ADC12_IN7 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_ADC12_IN8 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_ADC12_IN9 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
+
+#if defined(CONFIG_STM32_CAN1_REMAP1)
+# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN8)
+# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
+#else
+# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
+# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
+#endif
+
+#if defined(CONFIG_STM32_CAN2_REMAP)
+# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN5)
+# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
+#else
+# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
+# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
+#endif
+
+#if 0 /* Needs further investigation */
+#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
+#endif
+
+#if defined(CONFIG_STM32_I2C1_REMAP)
+# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
+# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
+#else
+# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
+# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
+#endif
+#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+
+#define GPIO_I2C2_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_I2C2_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_I2C2_SMBA (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_I2S2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_I2S2_MCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
+#define GPIO_I2S2_WS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
+
+#define GPIO_I2S3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_I2S3_MCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
+#define GPIO_I2S3_SD (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_I2S3_WS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
+
+#define GPIO_MCO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
+
+#define GPIO_OTGFS_DM (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_OTGFS_DP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_OTGFS_ID (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_OTGFS_SOF (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_OTGFS_VBUS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
+
+#if defined(CONFIG_STM32_SPI1_REMAP)
+# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
+# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
+# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
+# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+#else
+# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
+# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN5)
+# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
+# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
+#endif
+
+#define GPIO_SPI2_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_SPI2_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_SPI2_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_SPI2_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
+
+#if defined(CONFIG_STM32_SPI3_REMAP)
+# define GPIO_SPI3_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
+# define GPIO_SPI3_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
+# define GPIO_SPI3_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
+# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
+#else
+# define GPIO_SPI3_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
+# define GPIO_SPI3_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
+# define GPIO_SPI3_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
+# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+#endif
+
+#if 0 /* Needs further investigation */
+#define GPIO_TAMPER_RTC (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN13)
+#endif
+
+#if defined(CONFIG_STM32_TIM1_PARTIAL_REMAP)
+# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
+# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
+# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
+# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
+# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
+# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
+#else
+# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
+# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
+# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
+# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
+# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
+# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
+# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
+#endif
+
+#if defined(CONFIG_STM32_TIM2_FULL_REMAP)
+# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
+# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
+# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
+# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3)
+# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
+# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10)
+# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
+# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
+# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
+#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_1)
+# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
+# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
+# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
+# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3)
+# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
+# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
+# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
+#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_2)
+# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
+# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
+# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10)
+# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
+# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
+# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
+#else
+# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
+# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
+# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
+# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
+#endif
+
+#if defined(CONFIG_STM32_TIM3_FULL_REMAP)
+# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN6)
+# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
+# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN7)
+# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
+# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN8)
+# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
+# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN9)
+# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
+#elif defined(CONFIG_STM32_TIM3_PARTIAL_REMAP)
+# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
+# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
+# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN5)
+# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
+# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
+#else
+# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
+# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
+# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
+# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
+# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
+# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
+#endif
+#define GPIO_TIM3_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN2)
+
+#define GPIO_TIM4_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_TIM4_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_TIM4_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_TIM4_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_TIM4_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_TIM4_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_TIM4_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_TIM4_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
+
+#define GPIO_TIM5_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TIM5_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TIM5_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_TIM5_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_TIM5_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_TIM5_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_TIM5_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_TIM5_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
+
+#if 0 /* Needs further investigation */
+#if defined(CONFIG_STM32_TRACESWO_REMAP)
+# define GPIO_TRACESWO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
+#endif
+#endif
+
+#define GPIO_USART1_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_USART1_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_USART1_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
+#if defined(CONFIG_STM32_USART1_REMAP)
+# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
+#else
+# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
+#endif
+
+#define GPIO_USART2_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_USART2_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_USART2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_USART2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_USART2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
+
+#if defined(CONFIG_STM32_USART3_PARTIAL_REMAP)
+# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
+# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
+# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
+# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
+# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
+#else
+# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
+# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
+# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
+# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
+# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
+#endif
+
+#define GPIO_UART4_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
+#define GPIO_UART4_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
+
+#define GPIO_UART5_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN2)
+#define GPIO_UART5_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
+
+#define GPIO_WKUP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
+
+/* Some GPIOs are accessible only as remapped, alternate functions */
+
+#if 0 /* Needs further investigation */
+#define GPIO_PA13 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN13)
+#define GPIO_PA14 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN14)
+#define GPIO_PA15 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_PB3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_PB4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
+#endif
+
+#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F105R_PINMAP_H */
diff --git a/arch/arm/src/stm32/chip/stm32f105v_pinmap.h b/arch/arm/src/stm32/chip/stm32f105v_pinmap.h
index 71ffe84648..5fd7029e2c 100644
--- a/arch/arm/src/stm32/chip/stm32f105v_pinmap.h
+++ b/arch/arm/src/stm32/chip/stm32f105v_pinmap.h
@@ -91,44 +91,6 @@
#define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
#endif
-#if 0 /* Needs further investigation */
-#define GPIO_ETH_MDC (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN1)
-#define GPIO_ETH_MDIO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
-#define GPIO_ETH_MIICOL (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
-#define GPIO_ETH_MIICRSWKUP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
-#define GPIO_ETH_MIIRXCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
-
-#if defined(CONFIG_STM32_ETH_REMAP)
-# define GPIO_ETH_MIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN9)
-# define GPIO_ETH_MIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
-# define GPIO_ETH_MIIRXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN11)
-# define GPIO_ETH_MIIRXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
-# define GPIO_ETH_MIIRXDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
-#else
-# define GPIO_ETH_MIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
-# define GPIO_ETH_MIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
-# define GPIO_ETH_MIIRXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
-# define GPIO_ETH_MIIRXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
-# define GPIO_ETH_MIIRXDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
-#endif
-
-#define GPIO_ETH_MIIRXER (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
-#define GPIO_ETH_MIITXCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN3)
-#define GPIO_ETH_MIITXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
-#define GPIO_ETH_MIITXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
-#define GPIO_ETH_MIITXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN2)
-#define GPIO_ETH_MIITXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
-#define GPIO_ETH_MIITXEN (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
-#define GPIO_ETH_PPSOUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
-#define GPIO_ETH_RMIICRSDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
-#define GPIO_ETH_RMIIREFCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
-#define GPIO_ETH_RMIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
-#define GPIO_ETH_RMIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
-#define GPIO_ETH_RMIITXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
-#define GPIO_ETH_RMIITXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
-#define GPIO_ETH_RMIITXEN (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
-#endif
-
#if defined(CONFIG_STM32_I2C1_REMAP)
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
--
GitLab
From 08fd09b8fe95bd51b2a5ed85c174bd6e0a26aedc Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Mon, 6 Jun 2016 15:01:25 -0600
Subject: [PATCH 078/400] Update ChangeLog
---
ChangeLog | 28 ++++++++++++++++++++--------
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/ChangeLog b/ChangeLog
index 36041eb279..9ca199d45d 100755
--- a/ChangeLog
+++ b/ChangeLog
@@ -11887,6 +11887,14 @@
violated the OS/application interface -- by calling flash_eraseall().
The old code can be found in the Obsoleted' repository (and a revised
version can be found at apps/fsutils/flash_eraseall) (2016-06-03).
+ * arch/arm/src/stm32: STM32 Timer Driver: Change calculation of per-
+ timer pre-scaler value. Add support for all timers (2016-6-03)
+ * drivers/lcd: Correct conditional compilation in ST7565 driver. From
+ Pierre-noel Bouteville (2016-6-03)
+ * arch/arm/src/stm32: Correct conditional compilation in STM32 timer
+ capture logic. From Pierre-noel Bouteville (2016-6-03)
+ * arch/arm/src/efm32: Fix EFM32 FLASH conditional compilation. From
+ Pierre-noel Bouteville (2016-6-03)
* arch/arm/src/lpc43xx: Fix errors in GPIO interrupt logic. From v01d
(phreakuencies) (2016-06-04)
* arch/arm/src/kl and lpc11xx: rename xyz_lowputc to up_putc. Remove
@@ -11896,11 +11904,15 @@
* arch/arm/src/stm32: Add the up_getc() function to STM32 in order to
support the minnsh configuration. From Alan Carvalho de Assis
(2016-06-04).
- * arch/arm/src/stm32: STM32 Timer Driver: Change calculation of per-
- timer pre-scaler value. Add support for all timers (2016-6-03)
- * drivers/lcd: Correct conditional compilation in ST7565 driver. From
- Pierre-noel Bouteville (2016-6-03)
- * arch/arm/src/stm32: Correct conditional compilation in STM32 timer
- capture logic. From Pierre-noel Bouteville (2016-6-03)
- * arch/arm/src/efm32: Fix EFM32 FLASH conditional compilation. From
- Pierre-noel Bouteville (2016-6-03)
+ * include/sys/boardctl.h: Needs to be usable with C++ files (2016-06-05).
+ * tools/tesbuild.sh will now build NxWM configurations (2016-06-05).
+ * arch/arm/src/stm32: In PWM driver, just update duty if frequency is
+ not changed and PSM started. This removeis glitch or blinking when
+ only duty is frequently changed. From Pierre-noel Bouteville (2016-06-05).
+ * arch/arm/src/kinetis: Add a USB device controller driver. Derived from
+ the pic32mx usb driver, which uses the same usb controller. From kfazz
+ (2016-06).
+ * configs/teensy-3.x: Add USB support and a usbnsh configuration. From
+ kfazz (2016-06).
+ * arch/arm/src/stm32: Add support for the STM32F105R. From Konstantin
+ Berezenko (2016-06-06).
--
GitLab
From c939bbe47a962d8c906af910440b09148ab72447 Mon Sep 17 00:00:00 2001
From: Aleksandr Vyhovanec
Date: Tue, 7 Jun 2016 06:56:19 -0600
Subject: [PATCH 079/400] include/signal.h: Change type of SIG_IGN and related
defines to _sa_handler_t
---
ChangeLog | 3 +++
include/signal.h | 17 ++++++++---------
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/ChangeLog b/ChangeLog
index 9ca199d45d..bbd62c3cc0 100755
--- a/ChangeLog
+++ b/ChangeLog
@@ -11916,3 +11916,6 @@
kfazz (2016-06).
* arch/arm/src/stm32: Add support for the STM32F105R. From Konstantin
Berezenko (2016-06-06).
+ * include/signal.h: Change type of SIG_ERR, SIG_IGN, ... to
+ _sa_handler_t. They type void does not work with the IAR toolchain.
+ From Aleksandr Vyhovanec (2016-06-07).
diff --git a/include/signal.h b/include/signal.h
index 12585c91e3..7cfc93b136 100644
--- a/include/signal.h
+++ b/include/signal.h
@@ -175,22 +175,21 @@
/* Special values of of sa_handler used by sigaction and sigset. They are all
* treated like NULL for now. This is okay for SIG_DFL and SIG_IGN because
* in NuttX, the default action for all signals is to ignore them.
- *
- * REVISIT: Need to distinguish the value of SIG_HOLD. It is needed in the
- * implementation of sigset() but would need to be recognized in all signal
- * functions that deal with signal disposition.
*/
-#define SIG_ERR ((CODE void *)-1) /* And error occurred */
-#define SIG_DFL ((CODE void *)0) /* Default is SIG_IGN for all signals */
-#define SIG_IGN ((CODE void *)0) /* Ignore the signal */
-#define SIG_HOLD ((CODE void *)1) /* Used only with sigset() */
+#define SIG_ERR ((_sa_handler_t)-1) /* And error occurred */
+#define SIG_DFL ((_sa_handler_t)0) /* Default is SIG_IGN for all signals */
+#define SIG_IGN ((_sa_handler_t)0) /* Ignore the signal */
+#define SIG_HOLD ((_sa_handler_t)1) /* Used only with sigset() */
/********************************************************************************
* Public Type Definitions
********************************************************************************/
-/* This defines a set of 32 signals (numbered 0 through 31). */
+/* This defines a set of 32 signals (numbered 0 through 31).
+ * REVISIT: Signal 0 is, however, not generally usable since that value has
+ * special meaning in some circumstances (e.g., kill()).
+ */
typedef uint32_t sigset_t; /* Bit set of 32 signals */
#define __SIGSET_T_DEFINED 1
--
GitLab
From db470d8ffd859a7e45d9e1eea47918fbba5befff Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Tue, 7 Jun 2016 08:42:42 -0600
Subject: [PATCH 080/400] Update README
---
configs/stm32f103-minimum/README.txt | 87 ++++++++++++++++++++++++++++
1 file changed, 87 insertions(+)
diff --git a/configs/stm32f103-minimum/README.txt b/configs/stm32f103-minimum/README.txt
index 96e7be7a79..4ddee1fb07 100644
--- a/configs/stm32f103-minimum/README.txt
+++ b/configs/stm32f103-minimum/README.txt
@@ -428,6 +428,49 @@ Where is one of the following:
configuration. This configuration has far fewer features than the nsh
configuration but is also a fraction of the size.
+ This minnsh configuration is a "proof-of-concept" and not very usable in
+ its current state. This configuration was created by disabling
+ everything possible INCLUDING file system support. Without file system
+ support, NuttX is pretty much crippled. Here are some of the
+ consequences of disabling the file system:
+
+ - All features that depend on the file system are lost: device drivers,
+ mountpoints, message queues, named semaphores.
+
+ - Without device drivers, you cannot interact with the RTOS using POSIX
+ interfaces. You would have to work with NuttX as with those other
+ tiny RTOSs: As a scheduler and a callable hardare abstraction layer
+ (HAL).
+
+ - You cannot use any of the NuttX upper half device drivers since they
+ depend on the pseudo-file system and device nodes. You can, of
+ course, continue to use the lower half drivers either directly. Or,
+ perhaps, you could write some custom minnsh upper half drivers that
+ do not depend on a file system and expose a HAL interface.
+
+ There is a special version of readline() the NSH uses when there is no
+ file system. It uses a special up_putc() to write data to the console
+ and a special function up_getc() to read data from the console.
+
+ - The current up_getc() implementationsa are a kludge. They are
+ analogous to the up_putc() implementations: They directly poll the
+ hardware for serial availability, locking up all lower priority tasks
+ in the entire system while they poll. So a version of NSH that uses
+ up_getc() essentially blocks the system until a character is received.
+
+ This, of course, could be fixed by creating a special, upper half
+ implementation of the interrupt-driven serial lower half (like
+ stm32_serial) that just supports single character console I/O
+ (perhaps called up_putc and up_getc?). The NSH could wait for serial
+ input without blocking the system. But then that would increase the
+ footprint too.
+
+ So although the minnsh configurations are a good starting point for
+ making things small, they not are really very practical. Why might
+ you want a NuttX minnsh solution? Perhaps you have software that runs
+ on a family of chips including some very tiny MCUs. Then perhaps having
+ the RTOS compatibility would justify the loss of functionality?
+
STATUS:
2016-06-03: Using that config I got this:
@@ -446,6 +489,50 @@ Where is one of the following:
Mem: 18624 2328 16296 16296
nsh>
+ 2016-06-07: As another experiment, I tried enabling just (1) the file
+ system, (2) the console device, and (3) the upper half serial driver in
+ the minnsh configuration. With these changes, NSH should behave better
+ nd we preserve the device driver interface. I made the following
+ configuration changes:
+
+ Enable the file system:
+ CONFIG_NFILE_DESCRIPTORS=5
+ CONFIG_NFILE_STREAMS=5
+
+ Enable the console device:
+ CONFIG_DEV_CONSOLE=y
+
+ Disable most new NSH commands. Some like 'ls' are really mandatory
+ with a file system:
+ CONFIG_NSH_DISABLE_xxx=y
+
+ Enable the upper half serial driver:
+ CONFIG_SERIAL=y
+ CONFIG_STANDARD_SERIAL=y
+
+ Enable the USART1 serial driver:
+ CONFIG_STM32_USART1=y
+ CONFIG_STM32_USART1_SERIALDRIVER=y
+ CONFIG_USART1_SERIAL_CONSOLE=y
+
+ CONFIG_USART1_2STOP=0
+ CONFIG_USART1_BAUD=115200
+ CONFIG_USART1_BITS=8
+ CONFIG_USART1_PARITY=0
+ CONFIG_USART1_RXBUFSIZE=16
+ CONFIG_USART1_TXBUFSIZE=16
+
+ The resulting code was bigger as expected:
+
+ $ arm-none-eabi-size nuttx
+ text data bss dec hex filename
+ 20093 88 876 21057 5241 nuttx
+
+ I am sure that other things that could be disabled were also drawn into
+ the build, so perhaps this could be reduced. But as a ballpark
+ estimate, it looks like the cost of basic file system and serial console
+ driver support is around 7+KB.
+
nsh:
---
Configures the NuttShell (nsh) located at apps/examples/nsh. This
--
GitLab
From d4c101d2cf475a8e1ae6cc3e739dd4b77e5627df Mon Sep 17 00:00:00 2001
From: Gregory Nutt
Date: Tue, 7 Jun 2016 11:28:46 -0600
Subject: [PATCH 081/400] Update README files
---
configs/freedom-kl25z/README.txt | 80 +++++++++++++++++++++++++++
configs/freedom-kl26z/README.txt | 80 +++++++++++++++++++++++++++
configs/lpcxpresso-lpc1115/README.txt | 80 +++++++++++++++++++++++++++
configs/stm32f103-minimum/README.txt | 27 +++++++--
4 files changed, 261 insertions(+), 6 deletions(-)
diff --git a/configs/freedom-kl25z/README.txt b/configs/freedom-kl25z/README.txt
index 23390503de..f2cc8e0c02 100644
--- a/configs/freedom-kl25z/README.txt
+++ b/configs/freedom-kl25z/README.txt
@@ -301,6 +301,86 @@ Where is one of the following:
configuration. This configuration has far fewer features than the nsh
configuration but is also a fraction of the size.
+ This minnsh configuration is a "proof-of-concept" and not very usable in
+ its current state. This configuration was created by disabling
+ everything possible INCLUDING file system support. Without file system
+ support, NuttX is pretty much crippled. Here are some of the
+ consequences of disabling the file system:
+
+ - All features that depend on the file system are lost: device drivers,
+ mountpoints, message queues, named semaphores.
+
+ - Without device drivers, you cannot interact with the RTOS using POSIX
+ interfaces. You would have to work with NuttX as with those other
+ tiny RTOSs: As a scheduler and a callable hardare abstraction layer
+ (HAL).
+
+ - You cannot use any of the NuttX upper half device drivers since they
+ depend on the pseudo-file system and device nodes. You can, of
+ course, continue to use the lower half drivers either directly. Or,
+ perhaps, you could write some custom minnsh upper half drivers that
+ do not depend on a file system and expose a HAL interface.
+
+ There is a special version of readline() the NSH uses when there is no
+ file system. It uses a special up_putc() to write data to the console
+ and a special function up_getc() to read data from the console.
+
+ - The current up_getc() implementationsa are a kludge. They are
+ analogous to the up_putc() implementations: They directly poll the
+ hardware for serial availability, locking up all lower priority tasks
+ in the entire system while they poll. So a version of NSH that uses
+ up_getc() essentially blocks the system until a character is received.
+
+ This, of course, could be fixed by creating a special, upper half
+ implementation of the interrupt-driven serial lower half (like
+ stm32_serial) that just supports single character console I/O
+ (perhaps called up_putc and up_getc?). The NSH could wait for serial
+ input without blocking the system. But then that would increase the
+ footprint too.
+
+ So although the minnsh configurations are a good starting point for
+ making things small, they not are really very practical. Why might
+ you want a NuttX minnsh solution? Perhaps you have software that runs
+ on a family of chips including some very tiny MCUs. Then perhaps having
+ the RTOS compatibility would justify the loss of functionality?
+
+ You can re-enable the file system and (true) serial console with
+ these settings:
+
+ Enable the file system:
+ CONFIG_NFILE_DESCRIPTORS=5
+ CONFIG_NFILE_STREAMS=5
+
+ Enable the console device:
+ CONFIG_DEV_CONSOLE=y
+
+ Disable most new NSH commands. Some like 'ls' are really mandatory
+ with a file system:
+ CONFIG_NSH_DISABLE_xxx=y
+
+ Enable the upper half serial driver:
+ CONFIG_SERIAL=y
+ CONFIG_STANDARD_SERIAL=y
+
+ Enable the USART1 serial driver:
+ CONFIG_STM32_USART1=y
+ CONFIG_STM32_USART1_SERIALDRIVER=y
+ CONFIG_USART1_SERIAL_CONSOLE=y
+
+ CONFIG_USART1_2STOP=0
+ CONFIG_USART1_BAUD=115200
+ CONFIG_USART1_BITS=8
+ CONFIG_USART1_PARITY=0
+ CONFIG_USART1_RXBUFSIZE=16
+ CONFIG_USART1_TXBUFSIZE=16
+
+ With these changes, NSH should behave better and we preserve the device
+ driver interface. But this result in a total size increase of about
+ 7KB: That is about 5KB of additional OS support for the file system and
+ serial console PLUS about 2KB for the 'ls' command logic (including OS
+ support for opendir(), readdir(), closedir(), stat(), and probably other
+ things).
+
nsh:
---
Configures the NuttShell (nsh) located at apps/examples/nsh. The
diff --git a/configs/freedom-kl26z/README.txt b/configs/freedom-kl26z/README.txt
index 260ee1b6be..55f593c7d0 100644
--- a/configs/freedom-kl26z/README.txt
+++ b/configs/freedom-kl26z/README.txt
@@ -279,6 +279,86 @@ Where is one of the following:
configuration. This configuration has far fewer features than the nsh
configuration but is also a fraction of the size.
+ This minnsh configuration is a "proof-of-concept" and not very usable in
+ its current state. This configuration was created by disabling
+ everything possible INCLUDING file system support. Without file system
+ support, NuttX is pretty much crippled. Here are some of the
+ consequences of disabling the file system:
+
+ - All features that depend on the file system are lost: device drivers,
+ mountpoints, message queues, named semaphores.
+
+ - Without device drivers, you cannot interact with the RTOS using POSIX
+ interfaces. You would have to work with NuttX as with those other
+ tiny RTOSs: As a scheduler and a callable hardare abstraction layer
+ (HAL).
+
+ - You cannot use any of the NuttX upper half device drivers since they
+ depend on the pseudo-file system and device nodes. You can, of
+ course, continue to use the lower half drivers either directly. Or,
+ perhaps, you could write some custom minnsh upper half drivers that
+ do not depend on a file system and expose a HAL interface.
+
+ There is a special version of readline() the NSH uses when there is no
+ file system. It uses a special up_putc() to write data to the console
+ and a special function up_getc() to read data from the console.
+
+ - The current up_getc() implementationsa are a kludge. They are
+ analogous to the up_putc() implementations: They directly poll the
+ hardware for serial availability, locking up all lower priority tasks
+ in the entire system while they poll. So a version of NSH that uses
+ up_getc() essentially blocks the system until a character is received.
+
+ This, of course, could be fixed by creating a special, upper half
+ implementation of the interrupt-driven serial lower half (like
+ stm32_serial) that just supports single character console I/O
+ (perhaps called up_putc and up_getc?). The NSH could wait for serial
+ input without blocking the system. But then that would increase the
+ footprint too.
+
+ So although the minnsh configurations are a good starting point for
+ making things small, they not are really very practical. Why might
+ you want a NuttX minnsh solution? Perhaps you have software that runs
+ on a family of chips including some very tiny MCUs. Then perhaps having
+ the RTOS compatibility would justify the loss of functionality?
+
+ You can re-enable the file system and (true) serial console with
+ these settings:
+
+ Enable the file system:
+ CONFIG_NFILE_DESCRIPTORS=5
+ CONFIG_NFILE_STREAMS=5
+
+ Enable the console device:
+ CONFIG_DEV_CONSOLE=y
+
+ Disable most new NSH commands. Some like 'ls' are really mandatory
+ with a file system:
+ CONFIG_NSH_DISABLE_xxx=y
+
+ Enable the upper half serial driver:
+ CONFIG_SERIAL=y
+ CONFIG_STANDARD_SERIAL=y
+
+ Enable the USART1 serial driver:
+ CONFIG_STM32_USART1=y
+ CONFIG_STM32_USART1_SERIALDRIVER=y
+ CONFIG_USART1_SERIAL_CONSOLE=y
+
+ CONFIG_USART1_2STOP=0
+ CONFIG_USART1_BAUD=115200
+ CONFIG_USART1_BITS=8
+ CONFIG_USART1_PARITY=0
+ CONFIG_USART1_RXBUFSIZE=16
+ CONFIG_USART1_TXBUFSIZE=16
+
+ With these changes, NSH should behave better and we preserve the device
+ driver interface. But this result in a total size increase of about
+ 7KB: That is about 5KB of additional OS support for the file system and
+ serial console PLUS about 2KB for the 'ls' command logic (including OS
+ support for opendir(), readdir(), closedir(), stat(), and probably other
+ things).
+
nsh:
---
Configures the NuttShell (nsh) located at apps/examples/nsh. The
diff --git a/configs/lpcxpresso-lpc1115/README.txt b/configs/lpcxpresso-lpc1115/README.txt
index 3a0beb1e7f..bfe29dc6d5 100644
--- a/configs/lpcxpresso-lpc1115/README.txt
+++ b/configs/lpcxpresso-lpc1115/README.txt
@@ -687,6 +687,86 @@ Where is one of the following:
configuration. This configuration has far fewer features than the nsh
configuration but is also a fraction of the size.
+ This minnsh configuration is a "proof-of-concept" and not very usable in
+ its current state. This configuration was created by disabling
+ everything possible INCLUDING file system support. Without file system
+ support, NuttX is pretty much crippled. Here are some of the
+ consequences of disabling the file system:
+
+ - All features that depend on the file system are lost: device drivers,
+ mountpoints, message queues, named semaphores.
+
+ - Without device drivers, you cannot interact with the RTOS using POSIX
+ interfaces. You would have to work with NuttX as with those other
+ tiny RTOSs: As a scheduler and a callable hardare abstraction layer
+ (HAL).
+
+ - You cannot use any of the NuttX upper half device drivers since they
+ depend on the pseudo-file system and device nodes. You can, of
+ course, continue to use the lower half drivers either directly. Or,
+ perhaps, you could write some custom minnsh upper half drivers that
+ do not depend on a file system and expose a HAL interface.
+
+ There is a special version of readline() the NSH uses when there is no
+ file system. It uses a special up_putc() to write data to the console
+ and a special function up_getc() to read data from the console.
+
+ - The current up_getc() implementationsa are a kludge. They are
+ analogous to the up_putc() implementations: They directly poll the
+ hardware for serial availability, locking up all lower priority tasks
+ in the entire system while they poll. So a version of NSH that uses
+ up_getc() essentially blocks the system until a character is received.
+
+ This, of course, could be fixed by creating a special, upper half
+ implementation of the interrupt-driven serial lower half (like
+ stm32_serial) that just supports single character console I/O
+ (perhaps called up_putc and up_getc?). The NSH could wait for serial
+ input without blocking the system. But then that would increase the
+ footprint too.
+
+ So although the minnsh configurations are a good starting point for
+ making things small, they not are really very practical. Why might
+ you want a NuttX minnsh solution? Perhaps you have software that runs
+ on a family of chips including some very tiny MCUs. Then perhaps having
+ the RTOS compatibility would justify the loss of functionality?
+
+ You can re-enable the file system and (true) serial console with
+ these settings:
+
+ Enable the file system:
+ CONFIG_NFILE_DESCRIPTORS=5
+ CONFIG_NFILE_STREAMS=5
+
+ Enable the console device:
+ CONFIG_DEV_CONSOLE=y
+
+ Disable most new NSH commands. Some like 'ls' are really mandatory
+ with a file system:
+ CONFIG_NSH_DISABLE_xxx=y
+
+ Enable the upper half serial driver:
+ CONFIG_SERIAL=y
+ CONFIG_STANDARD_SERIAL=y
+
+ Enable the USART1 serial driver:
+ CONFIG_STM32_USART1=y
+ CONFIG_STM32_USART1_SERIALDRIVER=y
+ CONFIG_USART1_SERIAL_CONSOLE=y
+
+ CONFIG_USART1_2STOP=0
+ CONFIG_USART1_BAUD=115200
+ CONFIG_USART1_BITS=8
+ CONFIG_USART1_PARITY=0
+ CONFIG_USART1_RXBUFSIZE=16
+ CONFIG_USART1_TXBUFSIZE=16
+
+ With these changes, NSH should behave better and we preserve the device
+ driver interface. But this result in a total size increase of about
+ 7KB: That is about 5KB of additional OS support for the file system and
+ serial console PLUS about 2KB for the 'ls' command logic (including OS
+ support for opendir(), readdir(), closedir(), stat(), and probably other
+ things).
+
STATUS:
2015-6-10
The nuttx.bin minnsh firmware file size:
diff --git a/configs/stm32f103-minimum/README.txt b/configs/stm32f103-minimum/README.txt
index 4ddee1fb07..4f8ff5849f 100644
--- a/configs/stm32f103-minimum/README.txt
+++ b/configs/stm32f103-minimum/README.txt
@@ -492,7 +492,7 @@ Where is one of the following:
2016-06-07: As another experiment, I tried enabling just (1) the file
system, (2) the console device, and (3) the upper half serial driver in
the minnsh configuration. With these changes, NSH should behave better
- nd we preserve the device driver interface. I made the following
+ and we preserve the device driver interface. I made the following
configuration changes:
Enable the file system:
@@ -525,13 +525,28 @@ Where is one of the following:
The resulting code was bigger as expected:
$ arm-none-eabi-size nuttx
- text data bss dec hex filename
- 20093 88 876 21057 5241 nuttx
+ text data bss dec hex filename
+ 19853 88 876 20817 5151 nuttx
I am sure that other things that could be disabled were also drawn into
- the build, so perhaps this could be reduced. But as a ballpark
- estimate, it looks like the cost of basic file system and serial console
- driver support is around 7+KB.
+ the build, so perhaps this could be reduced. This amounts to a size
+ increase of around 7KB.
+
+ One major part of this size increase is due to the addition of the NSH
+ 'ls' command. Now, if I disable the 'ls' command, I get:
+
+ $ arm-none-eabi-size nuttx
+ text data bss dec hex filename
+ 17804 80 864 18748 493c nuttx
+
+ Or an increase of only 5.1 KB. This, of course, not only excludes the
+ 'ls' command logic, but also the things that were drawn into the link
+ when 'ls' was enabled: opendir(), readdir(), closedir(), stat(), and
+ probably other things.
+
+ So I think we can say that the cost of the file system and true serial
+ console device was about 5 KB (primarily OS support) and the cost of
+ the NSH 'ls' command (including OS support) is about 2KB.
nsh:
---
--
GitLab
From 44da2c0add3492cefcb7a3681e489210e43a710b Mon Sep 17 00:00:00 2001
From: David Sidrane
Date: Wed, 8 Jun 2016 07:52:19 -0600
Subject: [PATCH 082/400] Refactored configs/nucleo-144 sub-directories to
support additional nucleo-144 board. Add support for the Nucleo-F767ZI
board.
---
ChangeLog | 3 +
configs/Kconfig | 11 +-
configs/README.txt | 9 +-
configs/nucleo-144/Kconfig | 215 ++++
configs/nucleo-144/README.txt | 249 +++-
configs/nucleo-144/f746-evalos/Make.defs | 114 ++
.../{evalos => f746-evalos}/defconfig | 0
.../{evalos => f746-evalos}/setenv.sh | 2 +-
.../nucleo-144/{nsh => f746-nsh}/Make.defs | 7 +-
.../nucleo-144/{nsh => f746-nsh}/defconfig | 147 ++-
.../nucleo-144/{nsh => f746-nsh}/setenv.sh | 2 +-
configs/nucleo-144/f767-evalos/Make.defs | 114 ++
configs/nucleo-144/f767-evalos/defconfig | 1047 +++++++++++++++++
configs/nucleo-144/f767-evalos/setenv.sh | 78 ++
.../nucleo-144/{evalos => f767-nsh}/Make.defs | 9 +-
configs/nucleo-144/f767-nsh/defconfig | 1021 ++++++++++++++++
configs/nucleo-144/f767-nsh/setenv.sh | 77 ++
configs/nucleo-144/include/board.h | 172 +--
.../scripts/{flash.ld => f746-flash.ld} | 25 +-
configs/nucleo-144/scripts/f767-flash.ld | 146 +++
configs/nucleo-144/src/Makefile | 11 +-
configs/nucleo-144/src/nucleo-144.h | 145 ++-
configs/nucleo-144/src/stm32_appinitialize.c | 51 +-
configs/nucleo-144/src/stm32_autoleds.c | 124 +-
configs/nucleo-144/src/stm32_boot.c | 22 +-
configs/nucleo-144/src/stm32_buttons.c | 12 +-
configs/nucleo-144/src/stm32_dma_alloc.c | 117 ++
configs/nucleo-144/src/stm32_sdio.c | 176 +++
configs/nucleo-144/src/stm32_spi.c | 216 +++-
configs/nucleo-144/src/stm32_userleds.c | 30 +-
30 files changed, 4070 insertions(+), 282 deletions(-)
create mode 100644 configs/nucleo-144/f746-evalos/Make.defs
rename configs/nucleo-144/{evalos => f746-evalos}/defconfig (100%)
rename configs/nucleo-144/{evalos => f746-evalos}/setenv.sh (98%)
rename configs/nucleo-144/{nsh => f746-nsh}/Make.defs (96%)
rename configs/nucleo-144/{nsh => f746-nsh}/defconfig (82%)
rename configs/nucleo-144/{nsh => f746-nsh}/setenv.sh (98%)
create mode 100644 configs/nucleo-144/f767-evalos/Make.defs
create mode 100644 configs/nucleo-144/f767-evalos/defconfig
create mode 100644 configs/nucleo-144/f767-evalos/setenv.sh
rename configs/nucleo-144/{evalos => f767-nsh}/Make.defs (96%)
create mode 100644 configs/nucleo-144/f767-nsh/defconfig
create mode 100644 configs/nucleo-144/f767-nsh/setenv.sh
rename configs/nucleo-144/scripts/{flash.ld => f746-flash.ld} (83%)
create mode 100644 configs/nucleo-144/scripts/f767-flash.ld
create mode 100644 configs/nucleo-144/src/stm32_dma_alloc.c
create mode 100644 configs/nucleo-144/src/stm32_sdio.c
diff --git a/ChangeLog b/ChangeLog
index bbd62c3cc0..b3ea24e379 100755
--- a/ChangeLog
+++ b/ChangeLog
@@ -11919,3 +11919,6 @@
* include/signal.h: Change type of SIG_ERR, SIG_IGN, ... to
_sa_handler_t. They type void does not work with the IAR toolchain.
From Aleksandr Vyhovanec (2016-06-07).
+ * Refactoring configs/nucleo-144 sub-directories to support additional
+ nucleo-144 board. Add support for the Nucleo-F767ZI board. From David
+ Sidrane (2016-06-08).
diff --git a/configs/Kconfig b/configs/Kconfig
index c8169d0086..e4d6ec4e5f 100644
--- a/configs/Kconfig
+++ b/configs/Kconfig
@@ -649,14 +649,17 @@ config ARCH_BOARD_PIRELLI_DPL10
config ARCH_BOARD_NUCLEO_144
bool "STMicro NUCLEO-144"
- depends on ARCH_CHIP_STM32F746
+ depends on ARCH_CHIP_STM32F746 || ARCH_CHIP_STM32F767
select ARCH_HAVE_LEDS
select ARCH_HAVE_BUTTONS
select ARCH_HAVE_IRQBUTTONS
---help---
- STMicro Nucleo-144 development board featuring the STM32F746ZGT6U
- MCU. The STM32F746ZGT6U is a 216MHz Cortex-M7 operation with 1024Kb Flash
- memory and 300Kb SRAM.
+ STMicro Nucleo-144 development board family. Included support for (1) the
+ Nucleo-F767ZG board featuring the STM32F746ZGT6U MCU. The STM32F746ZGT6U
+ is a 216MHz Cortex-M7 operation with 1024Kb Flash memory and 320Kb SRAM.
+ And (2) the Nucleo-F746ZG board featuring the STM32F767ZIT6 MCU. The
+ STM32F767ZIT6 is a 216MHz Cortex-M7 operation with 2048Kb Flash memory
+ and 512Kb SRAM.
config ARCH_BOARD_NUCLEO_F303RE
bool "STM32F303 Nucleo F303RE"
diff --git a/configs/README.txt b/configs/README.txt
index 9b1c8486ba..45f06d0fa0 100644
--- a/configs/README.txt
+++ b/configs/README.txt
@@ -393,9 +393,12 @@ configs/ntosd-dm320
NuttX 0.2.1 release.
configs/nucleo-144
- STMicro Nucleo-144 development board featuring the STM32F746ZGT6U MCU. The
- STM32F746ZGT6U is a 216MHz Cortex-M7 operation with 1024Kb Flash memory
- and 300Kb SRAM.
+ STMicro Nucleo-144 development board family. Included support for (1) the
+ Nucleo-F767ZG board featuring the STM32F746ZGT6U MCU. The STM32F746ZGT6U
+ is a 216MHz Cortex-M7 operation with 1024Kb Flash memory and 320Kb SRAM.
+ And (2) the Nucleo-F746ZG board featuring the STM32F767ZIT6 MCU. The
+ STM32F767ZIT6 is a 216MHz Cortex-M7 operation with 2048Kb Flash memory
+ and 512Kb SRAM.
configs/nucleo-f4x1re
STMicro ST Nucleo F401RE and F411RE boards. See
diff --git a/configs/nucleo-144/Kconfig b/configs/nucleo-144/Kconfig
index 57585efaff..96427a9a5e 100644
--- a/configs/nucleo-144/Kconfig
+++ b/configs/nucleo-144/Kconfig
@@ -5,4 +5,219 @@
if ARCH_BOARD_NUCLEO_144
+choice
+ prompt "Select Console wiring."
+ default NUCLEO_ARDUINO
+ ---help---
+ Select where you will connect the console.
+
+ Virtual COM Port:
+
+ Advantage: Use the ST-Link as a console. No Extra wiring
+ neded.
+
+ Disdvantage: Not the best choice for initanl bring up.
+
+ ARDUINO Connector:
+
+ Advantage: You have a shield so it is
+ easy.
+
+ Disdvantage: You loose the use of the
+ other functions on PC6, PC7
+
+ STM32F7
+ ARDUIONO FUNCTION GPIO
+ -- ----- --------- ----
+ DO RX USART6_RX PG9
+ D1 TX USART6_TX PG14
+ -- ----- --------- ---
+
+ OR
+
+ Morpho Connector:
+
+ STM32F7
+ MORPHO FUNCTION GPIO
+ -------- --------- -----
+ CN12-64 USART8_RX PE0
+ CN11-61 USART8_TX PE1
+ -------- --------- -----
+
+config NUCLEO_CONSOLE_ARDUINO
+ bool "ARDUINO Connector"
+ select STM32F7_USART6
+ select USART6_SERIALDRIVER
+ select USART6_SERIAL_CONSOLE
+
+config NUCLEO_CONSOLE_VIRTUAL
+ bool "Virtual Comport"
+ select STM32F7_USART3
+ select USART3_SERIALDRIVER
+ select USART3_SERIAL_CONSOLE
+
+config NUCLEO_CONSOLE_MORPHO
+ bool "Morpho Connector"
+ select STM32F7_UART8
+ select UART8_SERIALDRIVER
+ select UART8_SERIAL_CONSOLE
+
+config NUCLEO_CONSOLE_NONE
+ bool "No Console"
+
+endchoice # "Select Console wiring"
+
+config NUCLEO_SPI_TEST
+ bool "Enable SPI test"
+ default n
+ ---help---
+ Enable Spi test - initalize and configure SPI to send
+ NUCLEO_SPI_TEST_MESSAGE text. The text is sent on the
+ selected SPI Buses with the configured parameters.
+ Note the CS lines will not be asserted.
+
+if NUCLEO_SPI_TEST
+
+config NUCLEO_SPI_TEST_MESSAGE
+ string "Text to Send on SPI Bus(es)"
+ default "Hello World"
+ depends on NUCLEO_SPI_TEST
+ ---help---
+ Text to sent on SPI bus(es)
+
+config NUCLEO_SPI1_TEST
+ bool "Test SPI bus 1"
+ default n
+ depends on NUCLEO_SPI_TEST
+ ---help---
+ Enable Spi test - on SPI BUS 1
+
+if NUCLEO_SPI1_TEST
+
+config NUCLEO_SPI1_TEST_FREQ
+ int "SPI 1 Clock Freq in Hz"
+ default 1000000
+ depends on NUCLEO_SPI1_TEST
+ ---help---
+ Sets SPI 1 Clock Freq
+
+config NUCLEO_SPI1_TEST_BITS
+ int "SPI 1 number of bits"
+ default 8
+ depends on NUCLEO_SPI1_TEST
+ ---help---
+ Sets SPI 1 bit length
+
+choice
+ prompt "SPI BUS 1 Clock Mode"
+ default NUCLEO_SPI1_TEST_MODE3
+ ---help---
+ Sets SPI 1 clock mode
+
+config NUCLEO_SPI1_TEST_MODE0
+ bool "CPOL=0 CHPHA=0"
+
+config NUCLEO_SPI1_TEST_MODE1
+ bool "CPOL=0 CHPHA=1"
+
+config NUCLEO_SPI1_TEST_MODE2
+ bool "CPOL=1 CHPHA=0"
+
+config NUCLEO_SPI1_TEST_MODE3
+ bool "CPOL=1 CHPHA=1"
+
+endchoice # "SPI BUS 1 Clock Mode"
+
+endif # NUCLEO_SPI1_TEST
+
+config NUCLEO_SPI2_TEST
+ bool "Test SPI bus 2"
+ default n
+ depends on NUCLEO_SPI_TEST
+ ---help---
+ Enable Spi test - on SPI BUS 2
+
+if NUCLEO_SPI2_TEST
+
+config NUCLEO_SPI2_TEST_FREQ
+ int "SPI 2 Clock Freq in Hz"
+ default 12000000
+ depends on NUCLEO_SPI2_TEST
+ ---help---
+ Sets SPI 2 Clock Freq
+
+config NUCLEO_SPI2_TEST_BITS
+ int "SPI 2 number of bits"
+ default 8
+ depends on NUCLEO_SPI2_TEST
+ ---help---
+ Sets SPI 2 bit length
+
+choice
+ prompt "SPI BUS 2 Clock Mode"
+ default NUCLEO_SPI2_TEST_MODE3
+ ---help---
+ Sets SPI 2 clock mode
+
+config NUCLEO_SPI2_TEST_MODE0
+ bool "CPOL=0 CHPHA=0"
+
+config NUCLEO_SPI2_TEST_MODE1
+ bool "CPOL=0 CHPHA=1"
+
+config NUCLEO_SPI2_TEST_MODE2
+ bool "CPOL=1 CHPHA=0"
+
+config NUCLEO_SPI2_TEST_MODE3
+ bool "CPOL=1 CHPHA=1"
+
+endchoice # "SPI BUS 2 Clock Mode"
+
+endif # NUCLEO_SPI2_TEST
+
+config NUCLEO_SPI3_TEST
+ bool "Test SPI bus 3"
+ default n
+ depends on NUCLEO_SPI_TEST
+ ---help---
+ Enable Spi test - on SPI BUS 3
+
+if NUCLEO_SPI3_TEST
+
+config NUCLEO_SPI3_TEST_FREQ
+ int "SPI 3 Clock Freq in Hz"
+ default 40000000
+ depends on NUCLEO_SPI3_TEST
+ ---help---
+ Sets SPI 3 Clock Freq
+
+config NUCLEO_SPI3_TEST_BITS
+ int "SPI 3 number of bits"
+ default 8
+ depends on NUCLEO_SPI3_TEST
+ ---help---
+ Sets SPI 3 bit length
+
+choice
+ prompt "SPI BUS 3 Clock Mode"
+ default NUCLEO_SPI3_TEST_MODE3
+ ---help---
+ Sets SPI 3 clock mode
+
+config NUCLEO_SPI3_TEST_MODE0
+ bool "CPOL=0 CHPHA=0"
+
+config NUCLEO_SPI3_TEST_MODE1
+ bool "CPOL=0 CHPHA=1"
+
+config NUCLEO_SPI3_TEST_MODE2
+ bool "CPOL=1 CHPHA=0"
+
+config NUCLEO_SPI3_TEST_MODE3
+ bool "CPOL=1 CHPHA=1"
+
+endchoice # "SPI BUS 3 Clock Mode"
+
+endif # NUCLEO_SPI3_TEST
+endif # NUCLEO_SPI_TEST
endif # ARCH_BOARD_NUCLEO_144
diff --git a/configs/nucleo-144/README.txt b/configs/nucleo-144/README.txt
index e99cd427de..1a5d6f4b3b 100644
--- a/configs/nucleo-144/README.txt
+++ b/configs/nucleo-144/README.txt
@@ -11,6 +11,7 @@ Contents
- Nucleo-144 Boards
- Nucleo F746ZG
+ - Nucleo F767ZI
- Development Environment
- IDEs
- Basic configuaration & build steps
@@ -18,7 +19,11 @@ Contents
- Button
- LED
- U[S]ARTs and Serial Consoles
+ - SPI
+ - SDIO - MMC
- Configurations
+ f7xx-nsh
+ f7xx-evalos
Nucleo-144 Boards:
=================
@@ -63,7 +68,7 @@ Common Board Features:
Nucleo F746ZG
=============
-At present only the ST Nucleo F746ZG board from ST Micro is supported. See
+ST Nucleo F746ZG board from ST Micro is supported. See
http://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-nucleo/nucleo-f746zg.html
@@ -80,7 +85,7 @@ NUCLEO-F746ZG Features:
+ 16KB of instruction TCM RAM + 4KB of backup SRAM
ADC: 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in
triple interleaved mode
- DMA: 16-stream DMA controllers with FIFOs and burst support
+ DMA: 2 X 16-stream DMA controllers with FIFOs and burst support
Timers: Up to 18 timers: up to thirteen 16-bit (1x 16-bit lowpower),
two 32-bit timers, 2x watchdogs, SysTick
GPIO: 114 I/O ports with interrupt capability
@@ -105,9 +110,58 @@ NUCLEO-F746ZG Features:
TRG: True random number generator
RTC
-See https://developer.mbed.org/platforms/ST-Nucleo-F746ZG form additional
+See https://developer.mbed.org/platforms/ST-Nucleo-F746ZG for additional
information about this board.
+Nucleo F767ZI
+=============
+
+ST Nucleo F7467ZI board from ST Micro is supported. See
+
+http://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-nucleo/nucleo-f767zi.html
+
+The Nucleo F767ZI order part number is NUCLEO-F767ZI. It is one member of
+the STM32 Nucleo-144 board family.
+
+NUCLEO-F767ZI Features:
+----------------------
+
+ Microprocessor: STM32F767ZIT6 Core: ARM 32-bit Cortex®-M7 CPU with DPFPU,
+ L1-cache: 16KB data cache and 16KB instruction cache, up to
+ 216 MHz, MPU, and DSP instructions.
+ Memory: 2048 KB Flash 512KB of SRAM (including 128KB of data TCM RAM)
+ + 16KB of instruction TCM RAM + 4KB of backup SRAM
+ ADC: 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in
+ triple interleaved mode
+ DMA: 2 X 16-stream DMA controllers with FIFOs and burst support
+ Timers: Up to 18 timers: up to thirteen 16-bit (1x 16-bit lowpower),
+ two 32-bit timers, 2x watchdogs, SysTick
+ GPIO: 114 I/O ports with interrupt capability
+ LCD: LCD-TFT Controllerwith (DMA2D), Parallel interface
+ I2C: 4 × I2C interfaces (SMBus/PMBus)
+ U[S]ARTs: 4 USARTs, 4 UARTs (27 Mbit/s, ISO7816 interface, LIN, IrDA,
+ modem control)
+ SPI/12Ss: 6/3 (simplex) (up to 50 Mbit/s), 3 with muxed simplex I2S
+ for audio class accuracy via internal audio PLL or external
+ clock
+ QSPI: Dual mode Quad-SPI
+ SAIs: 2 Serial Audio Interfaces
+ CAN: 3 X CAN interface
+ SDMMC interface
+ SPDIFRX interface
+ USB: USB 2.0 full/High-speed device/host/OTG controller with on-chip
+ PHY
+ 10/100 Ethernet: MAC with dedicated DMA: supports IEEE 1588v2 hardware,
+ MII/RMII
+ Camera Interface: 8/14 Bit
+ CRC calculation unit
+ TRG: True random number generator
+ RTC subsecond accuracy, hardware calendar
+
+As of this writting the NUCLEO-F767ZI is not available on developer.mbed.org
+However, See https://developer.mbed.org/platforms/ST-Nucleo-F746ZG for additional
+useful information.
+
Development Environment
=======================
@@ -154,8 +208,8 @@ Basic configuration & build steps
Hardware
========
- GPIO - there are 144 I/O lines on the STM32F746ZGT6 with various pins pined out
- on the Nucleo F746ZG.
+ GPIO - there are 144 I/O lines on the STM32F7xxZxT6 with various pins pined out
+ on the Nucleo 144.
See https://developer.mbed.org/platforms/ST-Nucleo-F746ZG/ for slick graphic
pinouts.
@@ -168,19 +222,47 @@ Hardware
Our main concern is establishing a console and LED utilization for
debugging. Because so many pins can be multiplexed with so many functions,
- the above mentioned graphic is super helpful in indentifying a serial port
- that will not rob us of another IO feature. Namely Serial Port 8 (UART8)
- with TX on PE1 and RX on PE0. Of course if your design has used those
- pins you can choose another IO configuration to bring out Serial Port 8
- or choose a completely different U[S]ART to use as the console.
- In that Case, You will need to edit the include/board.h to select different
- U[S]ART and / or pin selections.
-
- Serial
- ------
+ the above mentioned graphic may be helpful in indentifying a serial port.
+
+ There are 4 choices that can be made from the menuconfig:
+
+ CONFIG_NUCLEO_CONSOLE_ARDUINO or CONFIG_NUCLEO_CONSOLE_MORPHO or
+ CONFIG_NUCLEO_CONSOLE_VIRTUAL or CONFIG_NUCLEO_CONSOLE_NONE
+
+ The CONFIG_NUCLEO_CONSOLE_NONE makes no preset for the console. YOu shuld still visit
+ the U[S]ART selection and Device Drivers to disable any U[S]ART reamaing.
- SERIAL_RX PE_0
- SERIAL_TX PE_1
+ The CONFIG_NUCLEO_CONSOLE_ARDUINO configurations assume that you are using a
+ standard Arduio RS-232 shield with the serial interface with RX on pin D0 and
+ TX on pin D1 from USART6:
+
+ -------- ---------------
+ STM32F7
+ ARDUIONO FUNCTION GPIO
+ -- ----- --------- -----
+ DO RX USART6_RX PG9
+ D1 TX USART6_TX PG14
+ -- ----- --------- -----
+
+ The CONFIG_NUCLEO_CONSOLE_MORPHO configurations uses Serial Port 8 (USART8)
+ with TX on PE1 and RX on PE0.
+ Serial
+ ------
+ SERIAL_RX PE_0
+ SERIAL_TX PE_1
+
+ The CONFIG_NUCLEO_CONSOLE_VIRTUAL configurations uses Serial Port 3 (USART3)
+ with TX on PD8 and RX on PD9.
+ Serial
+ ------
+ SERIAL_RX PD9
+ SERIAL_TX PD8
+
+ These signals are internalaly connected to the on board ST-Link
+
+ Of course if your design has used those pins you can choose a completely
+ different U[S]ART to use as the console. In that Case, you will need to edit
+ the include/board.h to select different U[S]ART and / or pin selections.
Buttons
-------
@@ -202,32 +284,36 @@ Hardware
include/board.h and src/stm32_autoleds.c. The LEDs are used to encode OS
related events as follows when the LEDs are available:
- SYMBOL Meaning RED GREEN BLUE
- ------------------- ----------------------- -----------
+ SYMBOL Meaning RED GREEN BLUE
+ ------------------- ----------------------- --- ----- ----
+
+ LED_STARTED NuttX has been started OFF OFF OFF
+ LED_HEAPALLOCATE Heap has been allocated OFF OFF ON
+ LED_IRQSENABLED Interrupts enabled OFF ON OFF
+ LED_STACKCREATED Idle stack created OFF ON ON
+ LED_INIRQ In an interrupt NC NC ON (momentary)
+ LED_SIGNAL In a signal handler NC ON OFF (momentary)
+ LED_ASSERTION An assertion failed ON NC ON (momentary)
+ LED_PANIC The system has crashed ON OFF OFF (flashing 2Hz)
+ LED_IDLE MCU is is sleep mode ON OFF OFF
- LED_STARTED 0 OFF OFF OFF
- LED_HEAPALLOCATE 0 OFF OFF OFF
- LED_IRQSENABLED 0 OFF OFF OFF
- LED_STACKCREATED 1 OFF ON OFF
- LED_INIRQ 2 NC NC ON (momentary)
- LED_SIGNAL 2 NC NC ON (momentary)
- LED_ASSERTION 3 ON NC NC (momentary)
- LED_PANIC 4 ON OFF OFF (flashing 2Hz)
-OFF - means that the OS is still initializing. Initialization is very fast so
- if you see this at all, it probably means that the system is hanging up
- somewhere in the initialization phases.
+OFF - means that the OS is still initializing. Initialization is very fast
+ so if you see this at all, it probably means that the system is
+ hanging up somewhere in the initialization phases.
-GREEN - This means that the OS completed initialization.
+GREEN - This means that the OS completed initialization.
-BLUE - Whenever and interrupt or signal handler is entered, the BLUE LED is
- illuminated and extinguished when the interrupt or signal handler exits.
+BLUE - Whenever and interrupt or signal handler is entered, the BLUE LED is
+ illuminated and extinguished when the interrupt or signal handler
+ exits.
-RED - If a recovered assertion occurs, the RED LED will be illuminated
- briefly while the assertion is handled. You will probably never see this.
+VIOLET - If a recovered assertion occurs, the RED and blue LED will be
+ illuminated briefly while the assertion is handled. You will
+ probably never see this.
Flashing RED - In the event of a fatal crash, all other LEDs will be
-extinguished and RED LED will FLASH at a 2Hz rate.
+ extinguished and RED LED will FLASH at a 2Hz rate.
Thus if the GREEN LED is lit, NuttX has successfully booted and is,
@@ -238,30 +324,67 @@ extinguished and RED LED will FLASH at a 2Hz rate.
Serial Consoles
===============
- USART8
+ USART6 (CONFIG_NUCLEO_CONSOLE_ARDUINO)
------
+ STM32F7
+ ARDUIONO FUNCTION GPIO
+ -- ----- --------- -----
+ DO RX USART6_RX PG9
+ D1 TX USART6_TX PG14
+ -- ----- --------- -----
+
+ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL
+
+ Nucleo 144 FTDI TTL-232R-3V3
+ ------------- -------------------
+ TXD - D1-TXD - RXD - Pin 5 (Yellow)
+ RXD - D0-RXD - TXD - Pin 4 (Orange)
+ GND GND - GND Pin 1 (Black)
+ ------------- -------------------
+
+ *Note you will be reverse RX/TX
+
+ Use make menuconfig to configure USART6 as the console:
+
+ CONFIG_STM32F7_USART6=y
+ CONFIG_USARTs_SERIALDRIVER=y
+ CONFIG_USARTS_SERIAL_CONSOLE=y
+ CONFIG_USART6_RXBUFSIZE=256
+ CONFIG_USART6_TXBUFSIZE=256
+ CONFIG_USART6_BAUD=115200
+ CONFIG_USART6_BITS=8
+ CONFIG_USART6_PARITY=0
+ CONFIG_USART6_2STOP=0
+
+ USART8 (CONFIG_NUCLEO_CONSOLE_MORPHO)
+ ------
+
Pins and Connectors:
- GPIO Connector NAME
- RXD: PE0 CN11 pin 64, PE0
- CN10 pin 33, D34
+ FUNC GPIO Connector
+ Pin NAME
+ ---- --- ------- ----
+ TXD: PE1 CN11-61, PE1
+ RXD: PE0 CN12-64, PE0
+ CN10-33, D34
+ ---- --- ------- ----
- TXD: PE1 CN11 pin 61, PE1
You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL
Nucleo 144 FTDI TTL-232R-3V3
- ----------- ------------
- TXD - CN11 pin 64 - RXD - Pin 5 (Yellow)
- RXD - CN11 pin 61 - TXD - Pin 4 (Orange)
- GND CN11 pin 63 GND Pin 1 (Black)
+ ------------- -------------------
+ TXD - CN11-61 - RXD - Pin 5 (Yellow)
+ RXD - CN12-64 - TXD - Pin 4 (Orange)
+ GND CN12-63 - GND Pin 1 (Black)
+ ------------- -------------------
*Note you will be reverse RX/TX
Use make menuconfig to configure USART8 as the console:
CONFIG_STM32F7_UART8=y
- CONFIG_USART8_SERIALDRIVER=y
- CONFIG_USART8_SERIAL_CONSOLE=y
+ CONFIG_UART8_SERIALDRIVER=y
+ CONFIG_UART8_SERIAL_CONSOLE=y
CONFIG_UART8_RXBUFSIZE=256
CONFIG_UART8_TXBUFSIZE=256
CONFIG_UART8_BAUD=115200
@@ -269,7 +392,7 @@ Serial Consoles
CONFIG_UART8_PARITY=0
CONFIG_UART8_2STOP=0
- Virtual COM Port
+ Virtual COM Port (CONFIG_NUCLEO_CONSOLE_VIRTUAL)
----------------
Yet another option is to use USART3 and the USB virtual COM port. This
option may be more convenient for long term development, but is painful
@@ -290,14 +413,38 @@ Serial Consoles
As shipped, SB4 and SB7 are open and SB5 and SB6 closed, so the
virtual COM port is enabled.
+
+SPI
+---
+ Since this board is so generic, having a quick way to vet the SPI
+ configuration seams in order. So the board provides a quick test
+ that can be selected vi CONFIG_NUCLEO_SPI_TEST that will initalise
+ the selected buses (SPI1-SPI3) and send some text on the bus at
+ application initalization time board_app_initialize.
+
+SDIO
+----
+ To test the SD performace one can use a SparkFun microSD Sniffer
+ from https://www.sparkfun.com/products/9419 or similar board
+ and connect it as follows:
+
+ VCC V3.3 CN11 16
+ GND GND CN11-8
+ CMD PD2 CN11-4
+ CLK PC12 CN11-3
+ DAT0 - PC8 CN12-2
+ DAT1 - PC9 CN12-1
+ DAT2 PC10 CN11-1
+ CD PC11 CN11-2
+
Configurations
==============
-nsh:
+f7xx-nsh:
----
Configures the NuttShell (nsh) located at apps/examples/nsh for the
Nucleo-144 boards. The Configuration enables the serial interfaces
- on UART6. Support for builtin applications is enabled, but in the base
+ on USART6. Support for builtin applications is enabled, but in the base
configuration no builtin applications are selected (see NOTES below).
NOTES:
@@ -333,7 +480,7 @@ nsh:
device configured for UART8 (see instruction above under "Serial
Consoles).
-evalos:
+f7xx-evalos:
-------
This configuration is designed to test the features of the board.
- Configures the NuttShell (nsh) located at apps/examples/nsh for the
diff --git a/configs/nucleo-144/f746-evalos/Make.defs b/configs/nucleo-144/f746-evalos/Make.defs
new file mode 100644
index 0000000000..62c52e12f4
--- /dev/null
+++ b/configs/nucleo-144/f746-evalos/Make.defs
@@ -0,0 +1,114 @@
+############################################################################
+# configs/nucleo-144/f746-evalos/Make.defs
+#
+# Copyright (C) 2016 Gregory Nutt. All rights reserved.
+# Authors: Gregory Nutt
+# Mark Olsson
+# David Sidrane
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
+
+LDSCRIPT = f746-flash.ld
+
+ifeq ($(WINTOOL),y)
+ # Windows-native toolchains
+ DIRLINK = $(TOPDIR)/tools/copydir.sh
+ DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+ MKDEP = $(TOPDIR)/tools/mkwindeps.sh
+ ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+ ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+ ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
+else
+ # Linux/Cygwin-native toolchain
+ MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
+ ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+ ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+ ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
+endif
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+AR = $(ARCROSSDEV)ar rcs
+NM = $(ARCROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ ARCHOPTIMIZATION = -g
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+ ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
+ARCHWARNINGSXX = -Wall -Wshadow -Wundef
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+ASMEXT = .S
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-nuttx-elf-)
+ LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ LDFLAGS += -g
+endif
+
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
+HOSTLDFLAGS =
diff --git a/configs/nucleo-144/evalos/defconfig b/configs/nucleo-144/f746-evalos/defconfig
similarity index 100%
rename from configs/nucleo-144/evalos/defconfig
rename to configs/nucleo-144/f746-evalos/defconfig
diff --git a/configs/nucleo-144/evalos/setenv.sh b/configs/nucleo-144/f746-evalos/setenv.sh
similarity index 98%
rename from configs/nucleo-144/evalos/setenv.sh
rename to configs/nucleo-144/f746-evalos/setenv.sh
index 0f767948bf..84db5f90ee 100644
--- a/configs/nucleo-144/evalos/setenv.sh
+++ b/configs/nucleo-144/f746-evalos/setenv.sh
@@ -1,5 +1,5 @@
#!/bin/bash
-# configs/nucleo-144/evalos/setenv.sh
+# configs/nucleo-144/f746-evalos/setenv.sh
#
# Copyright (C) 2016 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt
diff --git a/configs/nucleo-144/nsh/Make.defs b/configs/nucleo-144/f746-nsh/Make.defs
similarity index 96%
rename from configs/nucleo-144/nsh/Make.defs
rename to configs/nucleo-144/f746-nsh/Make.defs
index 45b3f5f4ae..758b9eadb8 100644
--- a/configs/nucleo-144/nsh/Make.defs
+++ b/configs/nucleo-144/f746-nsh/Make.defs
@@ -1,8 +1,9 @@
############################################################################
-# configs/nucleo-144/nsh/Make.defs
+# configs/nucleo-144/f746-nsh/Make.defs
#
# Copyright (C) 2016 Gregory Nutt. All rights reserved.
-# Author: Gregory Nutt
+# Authors: Gregory Nutt
+# David Sidrane
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
@@ -37,7 +38,7 @@ include ${TOPDIR}/.config
include ${TOPDIR}/tools/Config.mk
include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
-LDSCRIPT = flash.ld
+LDSCRIPT = f746-flash.ld
ifeq ($(WINTOOL),y)
# Windows-native toolchains
diff --git a/configs/nucleo-144/nsh/defconfig b/configs/nucleo-144/f746-nsh/defconfig
similarity index 82%
rename from configs/nucleo-144/nsh/defconfig
rename to configs/nucleo-144/f746-nsh/defconfig
index cb59abca25..b8bcde84fe 100644
--- a/configs/nucleo-144/nsh/defconfig
+++ b/configs/nucleo-144/f746-nsh/defconfig
@@ -24,7 +24,7 @@ CONFIG_BUILD_FLAT=y
# Binary Output Formats
#
# CONFIG_RRLOAD_BINARY is not set
-CONFIG_INTELHEX_BINARY=y
+# CONFIG_INTELHEX_BINARY is not set
# CONFIG_MOTOROLA_SREC is not set
CONFIG_RAW_BINARY=y
# CONFIG_UBOOT_UIMAGE is not set
@@ -45,7 +45,7 @@ CONFIG_RAW_BINARY=y
# CONFIG_DEBUG is not set
CONFIG_ARCH_HAVE_HEAPCHECK=y
CONFIG_ARCH_HAVE_STACKCHECK=y
-# CONFIG_STACK_COLORATION is not set
+CONFIG_STACK_COLORATION=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_ARCH_HAVE_CUSTOMOPT=y
CONFIG_DEBUG_NOOPT=y
@@ -124,7 +124,7 @@ CONFIG_ARCH_HAVE_CMNVECTOR=y
CONFIG_ARMV7M_CMNVECTOR=y
# CONFIG_ARMV7M_LAZYFPU is not set
CONFIG_ARCH_HAVE_FPU=y
-CONFIG_ARCH_HAVE_DPFPU=y
+# CONFIG_ARCH_HAVE_DPFPU is not set
# CONFIG_ARCH_FPU is not set
# CONFIG_ARCH_HAVE_TRUSTZONE is not set
CONFIG_ARM_HAVE_MPU_UNIFIED=y
@@ -151,22 +151,118 @@ CONFIG_ARMV7M_HAVE_STACKCHECK=y
# CONFIG_ARMV7M_STACKCHECK is not set
# CONFIG_ARMV7M_ITMSYSLOG is not set
# CONFIG_SERIAL_TERMIOS is not set
+# CONFIG_USART6_RS485 is not set
+CONFIG_SERIAL_DISABLE_REORDERING=y
#
# STM32 F7 Configuration Options
#
-# CONFIG_ARCH_CHIP_STM32F745 is not set
-CONFIG_ARCH_CHIP_STM32F746=y
-# CONFIG_ARCH_CHIP_STM32F756 is not set
+# CONFIG_ARCH_CHIP_STM32F745VG is not set
+# CONFIG_ARCH_CHIP_STM32F745VE is not set
+# CONFIG_ARCH_CHIP_STM32F745IG is not set
+# CONFIG_ARCH_CHIP_STM32F745IE is not set
+# CONFIG_ARCH_CHIP_STM32F745ZE is not set
+# CONFIG_ARCH_CHIP_STM32F745ZG is not set
+# CONFIG_ARCH_CHIP_STM32F746BG is not set
+# CONFIG_ARCH_CHIP_STM32F746VG is not set
+# CONFIG_ARCH_CHIP_STM32F746VE is not set
+# CONFIG_ARCH_CHIP_STM32F746BE is not set
+CONFIG_ARCH_CHIP_STM32F746ZG=y
+# CONFIG_ARCH_CHIP_STM32F746IE is not set
+# CONFIG_ARCH_CHIP_STM32F746NG is not set
+# CONFIG_ARCH_CHIP_STM32F746NE is not set
+# CONFIG_ARCH_CHIP_STM32F746ZE is not set
+# CONFIG_ARCH_CHIP_STM32F746IG is not set
+# CONFIG_ARCH_CHIP_STM32F756NG is not set
+# CONFIG_ARCH_CHIP_STM32F756BG is not set
+# CONFIG_ARCH_CHIP_STM32F756IG is not set
+# CONFIG_ARCH_CHIP_STM32F756VG is not set
+# CONFIG_ARCH_CHIP_STM32F756ZG is not set
+# CONFIG_ARCH_CHIP_STM32F765NI is not set
+# CONFIG_ARCH_CHIP_STM32F765VI is not set
+# CONFIG_ARCH_CHIP_STM32F765VG is not set
+# CONFIG_ARCH_CHIP_STM32F765BI is not set
+# CONFIG_ARCH_CHIP_STM32F765NG is not set
+# CONFIG_ARCH_CHIP_STM32F765ZG is not set
+# CONFIG_ARCH_CHIP_STM32F765ZI is not set
+# CONFIG_ARCH_CHIP_STM32F765IG is not set
+# CONFIG_ARCH_CHIP_STM32F765BG is not set
+# CONFIG_ARCH_CHIP_STM32F765II is not set
+# CONFIG_ARCH_CHIP_STM32F767NG is not set
+# CONFIG_ARCH_CHIP_STM32F767IG is not set
+# CONFIG_ARCH_CHIP_STM32F767VG is not set
+# CONFIG_ARCH_CHIP_STM32F767ZG is not set
+# CONFIG_ARCH_CHIP_STM32F767NI is not set
+# CONFIG_ARCH_CHIP_STM32F767VI is not set
+# CONFIG_ARCH_CHIP_STM32F767BG is not set
+# CONFIG_ARCH_CHIP_STM32F767ZI is not set
+# CONFIG_ARCH_CHIP_STM32F767II is not set
+# CONFIG_ARCH_CHIP_STM32F769BI is not set
+# CONFIG_ARCH_CHIP_STM32F769II is not set
+# CONFIG_ARCH_CHIP_STM32F769BG is not set
+# CONFIG_ARCH_CHIP_STM32F769NI is not set
+# CONFIG_ARCH_CHIP_STM32F769AI is not set
+# CONFIG_ARCH_CHIP_STM32F769NG is not set
+# CONFIG_ARCH_CHIP_STM32F769IG is not set
+# CONFIG_ARCH_CHIP_STM32F777ZI is not set
+# CONFIG_ARCH_CHIP_STM32F777VI is not set
+# CONFIG_ARCH_CHIP_STM32F777NI is not set
+# CONFIG_ARCH_CHIP_STM32F777BI is not set
+# CONFIG_ARCH_CHIP_STM32F777II is not set
+# CONFIG_ARCH_CHIP_STM32F778AI is not set
+# CONFIG_ARCH_CHIP_STM32F779II is not set
+# CONFIG_ARCH_CHIP_STM32F779NI is not set
+# CONFIG_ARCH_CHIP_STM32F779BI is not set
+# CONFIG_ARCH_CHIP_STM32F779AI is not set
CONFIG_STM32F7_STM32F74XX=y
# CONFIG_STM32F7_STM32F75XX is not set
-# CONFIG_STM32F7_FLASH_512KB is not set
-CONFIG_STM32F7_FLASH_1024KB=y
+# CONFIG_STM32F7_STM32F76XX is not set
+# CONFIG_STM32F7_STM32F77XX is not set
+# CONFIG_STM32F7_IO_CONFIG_V is not set
+# CONFIG_STM32F7_IO_CONFIG_I is not set
+CONFIG_STM32F7_IO_CONFIG_Z=y
+# CONFIG_STM32F7_IO_CONFIG_N is not set
+# CONFIG_STM32F7_IO_CONFIG_B is not set
+# CONFIG_STM32F7_IO_CONFIG_A is not set
+# CONFIG_STM32F7_STM32F745XX is not set
+CONFIG_STM32F7_STM32F746XX=y
+# CONFIG_STM32F7_STM32F756XX is not set
+# CONFIG_STM32F7_STM32F765XX is not set
+# CONFIG_STM32F7_STM32F767XX is not set
+# CONFIG_STM32F7_STM32F768XX is not set
+# CONFIG_STM32F7_STM32F768AX is not set
+# CONFIG_STM32F7_STM32F769XX is not set
+# CONFIG_STM32F7_STM32F769AX is not set
+# CONFIG_STM32F7_STM32F777XX is not set
+# CONFIG_STM32F7_STM32F778XX is not set
+# CONFIG_STM32F7_STM32F778AX is not set
+# CONFIG_STM32F7_STM32F779XX is not set
+# CONFIG_STM32F7_STM32F779AX is not set
+# CONFIG_STM32F7_FLASH_CONFIG_E is not set
+# CONFIG_STM32F7_FLASH_CONFIG_I is not set
+CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT=y
+# CONFIG_STM32F7_FLASH_OVERRIDE_E is not set
+# CONFIG_STM32F7_FLASH_OVERRIDE_G is not set
+# CONFIG_STM32F7_FLASH_OVERRIDE_I is not set
#
# STM32 Peripheral Support
#
CONFIG_STM32F7_HAVE_LTDC=y
+CONFIG_STM32F7_HAVE_FSMC=y
+CONFIG_STM32F7_HAVE_ETHRNET=y
+CONFIG_STM32F7_HAVE_RNG=y
+CONFIG_STM32F7_HAVE_SPI5=y
+CONFIG_STM32F7_HAVE_SPI6=y
+# CONFIG_STM32F7_HAVE_SDMMC2 is not set
+# CONFIG_STM32F7_HAVE_CAN3 is not set
+CONFIG_STM32F7_HAVE_DCMI=y
+# CONFIG_STM32F7_HAVE_DSIHOST is not set
+CONFIG_STM32F7_HAVE_DMA2D=y
+# CONFIG_STM32F7_HAVE_JPEG is not set
+# CONFIG_STM32F7_HAVE_CRYP is not set
+# CONFIG_STM32F7_HAVE_HASH is not set
+# CONFIG_STM32F7_HAVE_DFSDM1 is not set
# CONFIG_STM32F7_ADC is not set
# CONFIG_STM32F7_CAN is not set
# CONFIG_STM32F7_DAC is not set
@@ -183,12 +279,12 @@ CONFIG_STM32F7_USART=y
# CONFIG_STM32F7_CAN2 is not set
# CONFIG_STM32F7_CEC is not set
# CONFIG_STM32F7_CRC is not set
-# CONFIG_STM32F7_CRYP is not set
# CONFIG_STM32F7_DMA1 is not set
# CONFIG_STM32F7_DMA2 is not set
# CONFIG_STM32F7_DAC1 is not set
# CONFIG_STM32F7_DAC2 is not set
# CONFIG_STM32F7_DCMI is not set
+# CONFIG_STM32F7_DMA2D is not set
# CONFIG_STM32F7_ETHMAC is not set
# CONFIG_STM32F7_FSMC is not set
# CONFIG_STM32F7_I2C1 is not set
@@ -196,12 +292,11 @@ CONFIG_STM32F7_USART=y
# CONFIG_STM32F7_I2C3 is not set
# CONFIG_STM32F7_LPTIM1 is not set
# CONFIG_STM32F7_LTDC is not set
-# CONFIG_STM32F7_DMA2D is not set
# CONFIG_STM32F7_OTGFS is not set
# CONFIG_STM32F7_OTGHS is not set
# CONFIG_STM32F7_QUADSPI is not set
-# CONFIG_STM32F7_SAI1 is not set
# CONFIG_STM32F7_RNG is not set
+# CONFIG_STM32F7_SAI1 is not set
# CONFIG_STM32F7_SAI2 is not set
# CONFIG_STM32F7_SDMMC1 is not set
# CONFIG_STM32F7_SPDIFRX is not set
@@ -236,6 +331,13 @@ CONFIG_STM32F7_USART6=y
# CONFIG_STM32F7_UART8 is not set
# CONFIG_STM32F7_IWDG is not set
# CONFIG_STM32F7_WWDG is not set
+
+#
+# U[S]ART Configuration
+#
+CONFIG_STM32F7_FLOWCONTROL_BROKEN=y
+CONFIG_STM32F7_USART_BREAKS=y
+CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y
# CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set
#
@@ -299,7 +401,6 @@ CONFIG_RAM_SIZE=245760
#
# Board Selection
#
-# CONFIG_ARCH_BOARD_STM32F746G_DISCO is not set
CONFIG_ARCH_BOARD_NUCLEO_144=y
# CONFIG_ARCH_BOARD_CUSTOM is not set
CONFIG_ARCH_BOARD="nucleo-144"
@@ -318,6 +419,11 @@ CONFIG_NSH_MMCSDMINOR=0
#
# Board-Specific Options
#
+CONFIG_NUCLEO_CONSOLE_ARDUINO=y
+# CONFIG_NUCLEO_CONSOLE_VIRTUAL is not set
+# CONFIG_NUCLEO_CONSOLE_MORPHO is not set
+# CONFIG_NUCLEO_CONSOLE_NONE is not set
+# CONFIG_NUCLEO_SPI_TEST is not set
# CONFIG_LIB_BOARDCTL is not set
#
@@ -337,9 +443,9 @@ CONFIG_USEC_PER_TICK=10000
# CONFIG_SYSTEM_TIME64 is not set
# CONFIG_CLOCK_MONOTONIC is not set
# CONFIG_JULIAN_TIME is not set
-CONFIG_START_YEAR=2011
-CONFIG_START_MONTH=12
-CONFIG_START_DAY=6
+CONFIG_START_YEAR=2015
+CONFIG_START_MONTH=11
+CONFIG_START_DAY=30
CONFIG_MAX_WDOGPARMS=2
CONFIG_PREALLOC_WDOGS=4
CONFIG_WDOG_INTRESERVE=0
@@ -464,7 +570,12 @@ CONFIG_SPI_EXCHANGE=y
# CONFIG_BCH is not set
# CONFIG_INPUT is not set
# CONFIG_IOEXPANDER is not set
+
+#
+# LCD Driver Support
+#
# CONFIG_LCD is not set
+# CONFIG_SLCD is not set
#
# LED Support
@@ -506,10 +617,6 @@ CONFIG_USART6_SERIALDRIVER=y
# CONFIG_USART7_SERIALDRIVER is not set
# CONFIG_USART8_SERIALDRIVER is not set
# CONFIG_OTHER_UART_SERIALDRIVER is not set
-
-#
-# USART Configuration
-#
CONFIG_MCU_SERIAL=y
CONFIG_STANDARD_SERIAL=y
# CONFIG_SERIAL_IFLOWCONTROL is not set
@@ -777,6 +884,7 @@ CONFIG_EXAMPLES_NSH=y
# Network Utilities
#
# CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_ESP8266 is not set
# CONFIG_NETUTILS_FTPC is not set
# CONFIG_NETUTILS_JSON is not set
# CONFIG_NETUTILS_SMTP is not set
@@ -903,5 +1011,6 @@ CONFIG_READLINE_ECHO=y
# CONFIG_READLINE_CMD_HISTORY is not set
# CONFIG_SYSTEM_SUDOKU is not set
# CONFIG_SYSTEM_VI is not set
+# CONFIG_SYSTEM_STACKMONITOR is not set
# CONFIG_SYSTEM_UBLOXMODEM is not set
# CONFIG_SYSTEM_ZMODEM is not set
diff --git a/configs/nucleo-144/nsh/setenv.sh b/configs/nucleo-144/f746-nsh/setenv.sh
similarity index 98%
rename from configs/nucleo-144/nsh/setenv.sh
rename to configs/nucleo-144/f746-nsh/setenv.sh
index 8498950aed..6a5fa6c801 100644
--- a/configs/nucleo-144/nsh/setenv.sh
+++ b/configs/nucleo-144/f746-nsh/setenv.sh
@@ -1,5 +1,5 @@
#!/bin/bash
-# configs/nucleo-144/nsh/setenv.sh
+# configs/nucleo-144/f746-nsh/setenv.sh
#
# Copyright (C) 2016 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt
diff --git a/configs/nucleo-144/f767-evalos/Make.defs b/configs/nucleo-144/f767-evalos/Make.defs
new file mode 100644
index 0000000000..3e25864217
--- /dev/null
+++ b/configs/nucleo-144/f767-evalos/Make.defs
@@ -0,0 +1,114 @@
+############################################################################
+# configs/nucleo-144/f767-evalos/Make.defs
+#
+# Copyright (C) 2016 Gregory Nutt. All rights reserved.
+# Authors: Gregory Nutt
+# Mark Olsson
+# David Sidrane
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
+
+LDSCRIPT = f767-flash.ld
+
+ifeq ($(WINTOOL),y)
+ # Windows-native toolchains
+ DIRLINK = $(TOPDIR)/tools/copydir.sh
+ DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+ MKDEP = $(TOPDIR)/tools/mkwindeps.sh
+ ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+ ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+ ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
+else
+ # Linux/Cygwin-native toolchain
+ MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
+ ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+ ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+ ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
+endif
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+AR = $(ARCROSSDEV)ar rcs
+NM = $(ARCROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ ARCHOPTIMIZATION = -g
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+ ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
+ARCHWARNINGSXX = -Wall -Wshadow -Wundef
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+ASMEXT = .S
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-nuttx-elf-)
+ LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ LDFLAGS += -g
+endif
+
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
+HOSTLDFLAGS =
diff --git a/configs/nucleo-144/f767-evalos/defconfig b/configs/nucleo-144/f767-evalos/defconfig
new file mode 100644
index 0000000000..e4165fa20d
--- /dev/null
+++ b/configs/nucleo-144/f767-evalos/defconfig
@@ -0,0 +1,1047 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Nuttx/ Configuration
+#
+
+#
+# Build Setup
+#
+# CONFIG_EXPERIMENTAL is not set
+# CONFIG_DEFAULT_SMALL is not set
+CONFIG_HOST_LINUX=y
+# CONFIG_HOST_OSX is not set
+# CONFIG_HOST_WINDOWS is not set
+# CONFIG_HOST_OTHER is not set
+
+#
+# Build Configuration
+#
+CONFIG_APPS_DIR="../apps"
+CONFIG_BUILD_FLAT=y
+# CONFIG_BUILD_2PASS is not set
+
+#
+# Binary Output Formats
+#
+# CONFIG_RRLOAD_BINARY is not set
+# CONFIG_INTELHEX_BINARY is not set
+# CONFIG_MOTOROLA_SREC is not set
+CONFIG_RAW_BINARY=y
+# CONFIG_UBOOT_UIMAGE is not set
+
+#
+# Customize Header Files
+#
+# CONFIG_ARCH_STDINT_H is not set
+# CONFIG_ARCH_STDBOOL_H is not set
+# CONFIG_ARCH_MATH_H is not set
+# CONFIG_ARCH_FLOAT_H is not set
+# CONFIG_ARCH_STDARG_H is not set
+# CONFIG_ARCH_DEBUG_H is not set
+
+#
+# Debug Options
+#
+# CONFIG_DEBUG is not set
+CONFIG_ARCH_HAVE_HEAPCHECK=y
+CONFIG_ARCH_HAVE_STACKCHECK=y
+CONFIG_STACK_COLORATION=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_ARCH_HAVE_CUSTOMOPT=y
+CONFIG_DEBUG_NOOPT=y
+# CONFIG_DEBUG_CUSTOMOPT is not set
+# CONFIG_DEBUG_FULLOPT is not set
+
+#
+# System Type
+#
+CONFIG_ARCH_ARM=y
+# CONFIG_ARCH_AVR is not set
+# CONFIG_ARCH_HC is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_RGMP is not set
+# CONFIG_ARCH_SH is not set
+# CONFIG_ARCH_SIM is not set
+# CONFIG_ARCH_X86 is not set
+# CONFIG_ARCH_Z16 is not set
+# CONFIG_ARCH_Z80 is not set
+CONFIG_ARCH="arm"
+
+#
+# ARM Options
+#
+# CONFIG_ARCH_CHIP_A1X is not set
+# CONFIG_ARCH_CHIP_C5471 is not set
+# CONFIG_ARCH_CHIP_CALYPSO is not set
+# CONFIG_ARCH_CHIP_DM320 is not set
+# CONFIG_ARCH_CHIP_EFM32 is not set
+# CONFIG_ARCH_CHIP_IMX1 is not set
+# CONFIG_ARCH_CHIP_IMX6 is not set
+# CONFIG_ARCH_CHIP_KINETIS is not set
+# CONFIG_ARCH_CHIP_KL is not set
+# CONFIG_ARCH_CHIP_LM is not set
+# CONFIG_ARCH_CHIP_TIVA is not set
+# CONFIG_ARCH_CHIP_LPC11XX is not set
+# CONFIG_ARCH_CHIP_LPC17XX is not set
+# CONFIG_ARCH_CHIP_LPC214X is not set
+# CONFIG_ARCH_CHIP_LPC2378 is not set
+# CONFIG_ARCH_CHIP_LPC31XX is not set
+# CONFIG_ARCH_CHIP_LPC43XX is not set
+# CONFIG_ARCH_CHIP_NUC1XX is not set
+# CONFIG_ARCH_CHIP_SAMA5 is not set
+# CONFIG_ARCH_CHIP_SAMD is not set
+# CONFIG_ARCH_CHIP_SAML is not set
+# CONFIG_ARCH_CHIP_SAM34 is not set
+# CONFIG_ARCH_CHIP_SAMV7 is not set
+# CONFIG_ARCH_CHIP_STM32 is not set
+CONFIG_ARCH_CHIP_STM32F7=y
+# CONFIG_ARCH_CHIP_STM32L4 is not set
+# CONFIG_ARCH_CHIP_STR71X is not set
+# CONFIG_ARCH_CHIP_TMS570 is not set
+# CONFIG_ARCH_CHIP_MOXART is not set
+# CONFIG_ARCH_ARM7TDMI is not set
+# CONFIG_ARCH_ARM926EJS is not set
+# CONFIG_ARCH_ARM920T is not set
+# CONFIG_ARCH_CORTEXM0 is not set
+# CONFIG_ARCH_CORTEXM3 is not set
+# CONFIG_ARCH_CORTEXM4 is not set
+CONFIG_ARCH_CORTEXM7=y
+# CONFIG_ARCH_CORTEXA5 is not set
+# CONFIG_ARCH_CORTEXA8 is not set
+# CONFIG_ARCH_CORTEXA9 is not set
+# CONFIG_ARCH_CORTEXR4 is not set
+# CONFIG_ARCH_CORTEXR4F is not set
+# CONFIG_ARCH_CORTEXR5 is not set
+# CONFIG_ARCH_CORTEX5F is not set
+# CONFIG_ARCH_CORTEXR7 is not set
+# CONFIG_ARCH_CORTEXR7F is not set
+CONFIG_ARCH_FAMILY="armv7-m"
+CONFIG_ARCH_CHIP="stm32f7"
+# CONFIG_ARM_TOOLCHAIN_IAR is not set
+CONFIG_ARM_TOOLCHAIN_GNU=y
+# CONFIG_ARMV7M_USEBASEPRI is not set
+CONFIG_ARCH_HAVE_CMNVECTOR=y
+CONFIG_ARMV7M_CMNVECTOR=y
+# CONFIG_ARMV7M_LAZYFPU is not set
+CONFIG_ARCH_HAVE_FPU=y
+CONFIG_ARCH_HAVE_DPFPU=y
+# CONFIG_ARCH_FPU is not set
+# CONFIG_ARCH_HAVE_TRUSTZONE is not set
+CONFIG_ARM_HAVE_MPU_UNIFIED=y
+# CONFIG_ARM_MPU is not set
+
+#
+# ARMV7M Configuration Options
+#
+CONFIG_ARMV7M_HAVE_ICACHE=y
+CONFIG_ARMV7M_HAVE_DCACHE=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
+CONFIG_ARMV7M_HAVE_ITCM=y
+CONFIG_ARMV7M_HAVE_DTCM=y
+# CONFIG_ARMV7M_ITCM is not set
+CONFIG_ARMV7M_DTCM=y
+# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set
+# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
+# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
+# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
+CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y
+CONFIG_ARMV7M_HAVE_STACKCHECK=y
+# CONFIG_ARMV7M_STACKCHECK is not set
+# CONFIG_ARMV7M_ITMSYSLOG is not set
+# CONFIG_SERIAL_TERMIOS is not set
+# CONFIG_USART3_RS485 is not set
+CONFIG_SERIAL_DISABLE_REORDERING=y
+
+#
+# STM32 F7 Configuration Options
+#
+# CONFIG_ARCH_CHIP_STM32F745VG is not set
+# CONFIG_ARCH_CHIP_STM32F745VE is not set
+# CONFIG_ARCH_CHIP_STM32F745IG is not set
+# CONFIG_ARCH_CHIP_STM32F745IE is not set
+# CONFIG_ARCH_CHIP_STM32F745ZE is not set
+# CONFIG_ARCH_CHIP_STM32F745ZG is not set
+# CONFIG_ARCH_CHIP_STM32F746BG is not set
+# CONFIG_ARCH_CHIP_STM32F746VG is not set
+# CONFIG_ARCH_CHIP_STM32F746VE is not set
+# CONFIG_ARCH_CHIP_STM32F746BE is not set
+# CONFIG_ARCH_CHIP_STM32F746ZG is not set
+# CONFIG_ARCH_CHIP_STM32F746IE is not set
+# CONFIG_ARCH_CHIP_STM32F746NG is not set
+# CONFIG_ARCH_CHIP_STM32F746NE is not set
+# CONFIG_ARCH_CHIP_STM32F746ZE is not set
+# CONFIG_ARCH_CHIP_STM32F746IG is not set
+# CONFIG_ARCH_CHIP_STM32F756NG is not set
+# CONFIG_ARCH_CHIP_STM32F756BG is not set
+# CONFIG_ARCH_CHIP_STM32F756IG is not set
+# CONFIG_ARCH_CHIP_STM32F756VG is not set
+# CONFIG_ARCH_CHIP_STM32F756ZG is not set
+# CONFIG_ARCH_CHIP_STM32F765NI is not set
+# CONFIG_ARCH_CHIP_STM32F765VI is not set
+# CONFIG_ARCH_CHIP_STM32F765VG is not set
+# CONFIG_ARCH_CHIP_STM32F765BI is not set
+# CONFIG_ARCH_CHIP_STM32F765NG is not set
+# CONFIG_ARCH_CHIP_STM32F765ZG is not set
+# CONFIG_ARCH_CHIP_STM32F765ZI is not set
+# CONFIG_ARCH_CHIP_STM32F765IG is not set
+# CONFIG_ARCH_CHIP_STM32F765BG is not set
+# CONFIG_ARCH_CHIP_STM32F765II is not set
+# CONFIG_ARCH_CHIP_STM32F767NG is not set
+# CONFIG_ARCH_CHIP_STM32F767IG is not set
+# CONFIG_ARCH_CHIP_STM32F767VG is not set
+# CONFIG_ARCH_CHIP_STM32F767ZG is not set
+# CONFIG_ARCH_CHIP_STM32F767NI is not set
+# CONFIG_ARCH_CHIP_STM32F767VI is not set
+# CONFIG_ARCH_CHIP_STM32F767BG is not set
+CONFIG_ARCH_CHIP_STM32F767ZI=y
+# CONFIG_ARCH_CHIP_STM32F767II is not set
+# CONFIG_ARCH_CHIP_STM32F769BI is not set
+# CONFIG_ARCH_CHIP_STM32F769II is not set
+# CONFIG_ARCH_CHIP_STM32F769BG is not set
+# CONFIG_ARCH_CHIP_STM32F769NI is not set
+# CONFIG_ARCH_CHIP_STM32F769AI is not set
+# CONFIG_ARCH_CHIP_STM32F769NG is not set
+# CONFIG_ARCH_CHIP_STM32F769IG is not set
+# CONFIG_ARCH_CHIP_STM32F777ZI is not set
+# CONFIG_ARCH_CHIP_STM32F777VI is not set
+# CONFIG_ARCH_CHIP_STM32F777NI is not set
+# CONFIG_ARCH_CHIP_STM32F777BI is not set
+# CONFIG_ARCH_CHIP_STM32F777II is not set
+# CONFIG_ARCH_CHIP_STM32F778AI is not set
+# CONFIG_ARCH_CHIP_STM32F779II is not set
+# CONFIG_ARCH_CHIP_STM32F779NI is not set
+# CONFIG_ARCH_CHIP_STM32F779BI is not set
+# CONFIG_ARCH_CHIP_STM32F779AI is not set
+# CONFIG_STM32F7_STM32F74XX is not set
+# CONFIG_STM32F7_STM32F75XX is not set
+CONFIG_STM32F7_STM32F76XX=y
+# CONFIG_STM32F7_STM32F77XX is not set
+# CONFIG_STM32F7_IO_CONFIG_V is not set
+# CONFIG_STM32F7_IO_CONFIG_I is not set
+CONFIG_STM32F7_IO_CONFIG_Z=y
+# CONFIG_STM32F7_IO_CONFIG_N is not set
+# CONFIG_STM32F7_IO_CONFIG_B is not set
+# CONFIG_STM32F7_IO_CONFIG_A is not set
+# CONFIG_STM32F7_STM32F745XX is not set
+# CONFIG_STM32F7_STM32F746XX is not set
+# CONFIG_STM32F7_STM32F756XX is not set
+# CONFIG_STM32F7_STM32F765XX is not set
+CONFIG_STM32F7_STM32F767XX=y
+# CONFIG_STM32F7_STM32F768XX is not set
+# CONFIG_STM32F7_STM32F768AX is not set
+# CONFIG_STM32F7_STM32F769XX is not set
+# CONFIG_STM32F7_STM32F769AX is not set
+# CONFIG_STM32F7_STM32F777XX is not set
+# CONFIG_STM32F7_STM32F778XX is not set
+# CONFIG_STM32F7_STM32F778AX is not set
+# CONFIG_STM32F7_STM32F779XX is not set
+# CONFIG_STM32F7_STM32F779AX is not set
+# CONFIG_STM32F7_FLASH_CONFIG_E is not set
+CONFIG_STM32F7_FLASH_CONFIG_I=y
+CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT=y
+# CONFIG_STM32F7_FLASH_OVERRIDE_E is not set
+# CONFIG_STM32F7_FLASH_OVERRIDE_G is not set
+# CONFIG_STM32F7_FLASH_OVERRIDE_I is not set
+
+#
+# STM32 Peripheral Support
+#
+CONFIG_STM32F7_HAVE_LTDC=y
+CONFIG_STM32F7_HAVE_FSMC=y
+CONFIG_STM32F7_HAVE_ETHRNET=y
+CONFIG_STM32F7_HAVE_RNG=y
+CONFIG_STM32F7_HAVE_SPI5=y
+CONFIG_STM32F7_HAVE_SPI6=y
+CONFIG_STM32F7_HAVE_SDMMC2=y
+CONFIG_STM32F7_HAVE_CAN3=y
+CONFIG_STM32F7_HAVE_DCMI=y
+# CONFIG_STM32F7_HAVE_DSIHOST is not set
+CONFIG_STM32F7_HAVE_DMA2D=y
+CONFIG_STM32F7_HAVE_JPEG=y
+# CONFIG_STM32F7_HAVE_CRYP is not set
+# CONFIG_STM32F7_HAVE_HASH is not set
+CONFIG_STM32F7_HAVE_DFSDM1=y
+# CONFIG_STM32F7_ADC is not set
+# CONFIG_STM32F7_CAN is not set
+# CONFIG_STM32F7_DAC is not set
+# CONFIG_STM32F7_DMA is not set
+# CONFIG_STM32F7_I2C is not set
+# CONFIG_STM32F7_SAI is not set
+# CONFIG_STM32F7_SPI is not set
+CONFIG_STM32F7_USART=y
+# CONFIG_STM32F7_ADC1 is not set
+# CONFIG_STM32F7_ADC2 is not set
+# CONFIG_STM32F7_ADC3 is not set
+# CONFIG_STM32F7_BKPSRAM is not set
+# CONFIG_STM32F7_CAN1 is not set
+# CONFIG_STM32F7_CAN2 is not set
+# CONFIG_STM32F7_CAN3 is not set
+# CONFIG_STM32F7_CEC is not set
+# CONFIG_STM32F7_CRC is not set
+# CONFIG_STM32F7_DFSDM1 is not set
+# CONFIG_STM32F7_DMA1 is not set
+# CONFIG_STM32F7_DMA2 is not set
+# CONFIG_STM32F7_DAC1 is not set
+# CONFIG_STM32F7_DAC2 is not set
+# CONFIG_STM32F7_DCMI is not set
+# CONFIG_STM32F7_DMA2D is not set
+# CONFIG_STM32F7_JPEG is not set
+# CONFIG_STM32F7_ETHMAC is not set
+# CONFIG_STM32F7_FSMC is not set
+# CONFIG_STM32F7_I2C1 is not set
+# CONFIG_STM32F7_I2C2 is not set
+# CONFIG_STM32F7_I2C3 is not set
+# CONFIG_STM32F7_LPTIM1 is not set
+# CONFIG_STM32F7_LTDC is not set
+# CONFIG_STM32F7_OTGFS is not set
+# CONFIG_STM32F7_OTGHS is not set
+# CONFIG_STM32F7_QUADSPI is not set
+# CONFIG_STM32F7_RNG is not set
+# CONFIG_STM32F7_SAI1 is not set
+# CONFIG_STM32F7_SAI2 is not set
+# CONFIG_STM32F7_SDMMC1 is not set
+# CONFIG_STM32F7_SDMMC2 is not set
+# CONFIG_STM32F7_SPDIFRX is not set
+# CONFIG_STM32F7_SPI1 is not set
+# CONFIG_STM32F7_SPI2 is not set
+# CONFIG_STM32F7_SPI3 is not set
+# CONFIG_STM32F7_SPI4 is not set
+# CONFIG_STM32F7_SPI5 is not set
+# CONFIG_STM32F7_SPI6 is not set
+# CONFIG_STM32F7_TIM1 is not set
+# CONFIG_STM32F7_TIM2 is not set
+# CONFIG_STM32F7_TIM3 is not set
+# CONFIG_STM32F7_TIM4 is not set
+# CONFIG_STM32F7_TIM5 is not set
+# CONFIG_STM32F7_TIM6 is not set
+# CONFIG_STM32F7_TIM7 is not set
+# CONFIG_STM32F7_TIM8 is not set
+# CONFIG_STM32F7_TIM9 is not set
+# CONFIG_STM32F7_TIM10 is not set
+# CONFIG_STM32F7_TIM11 is not set
+# CONFIG_STM32F7_TIM12 is not set
+# CONFIG_STM32F7_TIM13 is not set
+# CONFIG_STM32F7_TIM14 is not set
+# CONFIG_STM32F7_TIM15 is not set
+# CONFIG_STM32F7_USART1 is not set
+# CONFIG_STM32F7_USART2 is not set
+CONFIG_STM32F7_USART3=y
+# CONFIG_STM32F7_UART4 is not set
+# CONFIG_STM32F7_UART5 is not set
+# CONFIG_STM32F7_USART6 is not set
+# CONFIG_STM32F7_UART7 is not set
+# CONFIG_STM32F7_UART8 is not set
+# CONFIG_STM32F7_IWDG is not set
+# CONFIG_STM32F7_WWDG is not set
+
+#
+# U[S]ART Configuration
+#
+CONFIG_STM32F7_FLOWCONTROL_BROKEN=y
+CONFIG_STM32F7_USART_BREAKS=y
+CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y
+# CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set
+
+#
+# Architecture Options
+#
+# CONFIG_ARCH_NOINTC is not set
+# CONFIG_ARCH_VECNOTIRQ is not set
+# CONFIG_ARCH_DMA is not set
+CONFIG_ARCH_HAVE_IRQPRIO=y
+# CONFIG_ARCH_L2CACHE is not set
+# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set
+# CONFIG_ARCH_HAVE_ADDRENV is not set
+# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set
+# CONFIG_ARCH_HAVE_MULTICPU is not set
+CONFIG_ARCH_HAVE_VFORK=y
+# CONFIG_ARCH_HAVE_MMU is not set
+CONFIG_ARCH_HAVE_MPU=y
+# CONFIG_ARCH_NAND_HWECC is not set
+# CONFIG_ARCH_HAVE_EXTCLK is not set
+# CONFIG_ARCH_HAVE_POWEROFF is not set
+# CONFIG_ARCH_HAVE_RESET is not set
+# CONFIG_ARCH_USE_MPU is not set
+# CONFIG_ARCH_IRQPRIO is not set
+CONFIG_ARCH_STACKDUMP=y
+# CONFIG_ENDIAN_BIG is not set
+# CONFIG_ARCH_IDLE_CUSTOM is not set
+# CONFIG_ARCH_HAVE_RAMFUNCS is not set
+CONFIG_ARCH_HAVE_RAMVECTORS=y
+# CONFIG_ARCH_RAMVECTORS is not set
+
+#
+# Board Settings
+#
+CONFIG_BOARD_LOOPSPERMSEC=43103
+# CONFIG_ARCH_CALIBRATION is not set
+
+#
+# Interrupt options
+#
+CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
+CONFIG_ARCH_INTERRUPTSTACK=0
+CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y
+# CONFIG_ARCH_HIPRI_INTERRUPT is not set
+
+#
+# Boot options
+#
+# CONFIG_BOOT_RUNFROMEXTSRAM is not set
+CONFIG_BOOT_RUNFROMFLASH=y
+# CONFIG_BOOT_RUNFROMISRAM is not set
+# CONFIG_BOOT_RUNFROMSDRAM is not set
+# CONFIG_BOOT_COPYTORAM is not set
+
+#
+# Boot Memory Configuration
+#
+CONFIG_RAM_START=0x20010000
+CONFIG_RAM_SIZE=245760
+# CONFIG_ARCH_HAVE_SDRAM is not set
+
+#
+# Board Selection
+#
+CONFIG_ARCH_BOARD_NUCLEO_144=y
+# CONFIG_ARCH_BOARD_CUSTOM is not set
+CONFIG_ARCH_BOARD="nucleo-144"
+
+#
+# Common Board Options
+#
+CONFIG_ARCH_HAVE_LEDS=y
+# CONFIG_ARCH_LEDS is not set
+CONFIG_ARCH_HAVE_BUTTONS=y
+CONFIG_ARCH_BUTTONS=y
+CONFIG_ARCH_HAVE_IRQBUTTONS=y
+# CONFIG_ARCH_IRQBUTTONS is not set
+CONFIG_NSH_MMCSDMINOR=0
+
+#
+# Board-Specific Options
+#
+# CONFIG_NUCLEO_CONSOLE_ARDUINO is not set
+CONFIG_NUCLEO_CONSOLE_VIRTUAL=y
+# CONFIG_NUCLEO_CONSOLE_MORPHO is not set
+# CONFIG_NUCLEO_CONSOLE_NONE is not set
+# CONFIG_NUCLEO_SPI_TEST is not set
+CONFIG_LIB_BOARDCTL=y
+# CONFIG_BOARDCTL_UNIQUEID is not set
+# CONFIG_BOARDCTL_TSCTEST is not set
+# CONFIG_BOARDCTL_ADCTEST is not set
+# CONFIG_BOARDCTL_PWMTEST is not set
+# CONFIG_BOARDCTL_GRAPHICS is not set
+# CONFIG_BOARDCTL_IOCTL is not set
+
+#
+# RTOS Features
+#
+# CONFIG_DISABLE_OS_API is not set
+
+#
+# Clocks and Timers
+#
+CONFIG_USEC_PER_TICK=10000
+# CONFIG_SYSTEM_TIME64 is not set
+# CONFIG_CLOCK_MONOTONIC is not set
+# CONFIG_JULIAN_TIME is not set
+CONFIG_START_YEAR=2015
+CONFIG_START_MONTH=11
+CONFIG_START_DAY=30
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_PREALLOC_WDOGS=4
+CONFIG_WDOG_INTRESERVE=0
+CONFIG_PREALLOC_TIMERS=4
+
+#
+# Tasks and Scheduling
+#
+# CONFIG_INIT_NONE is not set
+CONFIG_INIT_ENTRYPOINT=y
+# CONFIG_INIT_FILEPATH is not set
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_RR_INTERVAL=200
+# CONFIG_SCHED_SPORADIC is not set
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_MAX_TASKS=16
+# CONFIG_SCHED_HAVE_PARENT is not set
+CONFIG_SCHED_WAITPID=y
+
+#
+# Pthread Options
+#
+# CONFIG_MUTEX_TYPES is not set
+CONFIG_NPTHREAD_KEYS=4
+
+#
+# Performance Monitoring
+#
+# CONFIG_SCHED_CPULOAD is not set
+# CONFIG_SCHED_INSTRUMENTATION is not set
+
+#
+# Files and I/O
+#
+CONFIG_DEV_CONSOLE=y
+# CONFIG_FDCLONE_DISABLE is not set
+# CONFIG_FDCLONE_STDIO is not set
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NAME_MAX=32
+CONFIG_PRIORITY_INHERITANCE=y
+CONFIG_SEM_PREALLOCHOLDERS=16
+CONFIG_SEM_NNESTPRIO=16
+
+#
+# RTOS hooks
+#
+# CONFIG_BOARD_INITIALIZE is not set
+# CONFIG_SCHED_STARTHOOK is not set
+# CONFIG_SCHED_ATEXIT is not set
+# CONFIG_SCHED_ONEXIT is not set
+# CONFIG_SIG_EVTHREAD is not set
+
+#
+# Signal Numbers
+#
+CONFIG_SIG_SIGUSR1=1
+CONFIG_SIG_SIGUSR2=2
+CONFIG_SIG_SIGALARM=3
+CONFIG_SIG_SIGCONDTIMEDOUT=16
+CONFIG_SIG_SIGWORK=17
+
+#
+# POSIX Message Queue Options
+#
+CONFIG_PREALLOC_MQ_MSGS=4
+CONFIG_MQ_MAXMSGSIZE=32
+# CONFIG_MODULE is not set
+
+#
+# Work queue support
+#
+CONFIG_SCHED_WORKQUEUE=y
+CONFIG_SCHED_HPWORK=y
+CONFIG_SCHED_HPWORKPRIORITY=224
+CONFIG_SCHED_HPWORKPERIOD=100000
+CONFIG_SCHED_HPWORKSTACKSIZE=2048
+CONFIG_SCHED_LPWORK=y
+CONFIG_SCHED_LPNTHREADS=1
+CONFIG_SCHED_LPWORKPRIORITY=50
+CONFIG_SCHED_LPWORKPRIOMAX=176
+CONFIG_SCHED_LPWORKPERIOD=50000
+CONFIG_SCHED_LPWORKSTACKSIZE=2048
+
+#
+# Stack and heap information
+#
+CONFIG_IDLETHREAD_STACKSIZE=1024
+CONFIG_USERMAIN_STACKSIZE=2048
+CONFIG_PTHREAD_STACK_MIN=256
+CONFIG_PTHREAD_STACK_DEFAULT=2048
+# CONFIG_LIB_SYSCALL is not set
+
+#
+# Device Drivers
+#
+CONFIG_DISABLE_POLL=y
+CONFIG_DEV_NULL=y
+# CONFIG_DEV_ZERO is not set
+# CONFIG_DEV_LOOP is not set
+
+#
+# Buffering
+#
+# CONFIG_DRVR_WRITEBUFFER is not set
+# CONFIG_DRVR_READAHEAD is not set
+# CONFIG_RAMDISK is not set
+# CONFIG_CAN is not set
+# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set
+# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set
+# CONFIG_PWM is not set
+CONFIG_ARCH_HAVE_I2CRESET=y
+# CONFIG_I2C is not set
+CONFIG_SPI=y
+# CONFIG_SPI_SLAVE is not set
+CONFIG_SPI_EXCHANGE=y
+# CONFIG_SPI_CMDDATA is not set
+# CONFIG_SPI_CALLBACK is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_HWFEATURES is not set
+# CONFIG_SPI_CRCGENERATION is not set
+# CONFIG_I2S is not set
+
+#
+# Timer Driver Support
+#
+# CONFIG_TIMER is not set
+# CONFIG_RTC is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_ANALOG is not set
+# CONFIG_AUDIO_DEVICES is not set
+# CONFIG_VIDEO_DEVICES is not set
+# CONFIG_BCH is not set
+# CONFIG_INPUT is not set
+# CONFIG_IOEXPANDER is not set
+
+#
+# LCD Driver Support
+#
+# CONFIG_LCD is not set
+# CONFIG_SLCD is not set
+
+#
+# LED Support
+#
+CONFIG_USERLED=y
+CONFIG_USERLED_LOWER=y
+# CONFIG_RGBLED is not set
+# CONFIG_PCA9635PW is not set
+# CONFIG_MMCSD is not set
+# CONFIG_MODEM is not set
+# CONFIG_MTD is not set
+# CONFIG_EEPROM is not set
+# CONFIG_PIPES is not set
+# CONFIG_PM is not set
+# CONFIG_POWER is not set
+# CONFIG_SENSORS is not set
+# CONFIG_SERCOMM_CONSOLE is not set
+CONFIG_SERIAL=y
+# CONFIG_DEV_LOWCONSOLE is not set
+# CONFIG_16550_UART is not set
+# CONFIG_UART_SERIALDRIVER is not set
+# CONFIG_UART0_SERIALDRIVER is not set
+# CONFIG_UART1_SERIALDRIVER is not set
+# CONFIG_UART2_SERIALDRIVER is not set
+# CONFIG_UART3_SERIALDRIVER is not set
+# CONFIG_UART4_SERIALDRIVER is not set
+# CONFIG_UART5_SERIALDRIVER is not set
+# CONFIG_UART6_SERIALDRIVER is not set
+# CONFIG_UART7_SERIALDRIVER is not set
+# CONFIG_UART8_SERIALDRIVER is not set
+# CONFIG_SCI0_SERIALDRIVER is not set
+# CONFIG_SCI1_SERIALDRIVER is not set
+# CONFIG_USART0_SERIALDRIVER is not set
+# CONFIG_USART1_SERIALDRIVER is not set
+# CONFIG_USART2_SERIALDRIVER is not set
+CONFIG_USART3_SERIALDRIVER=y
+# CONFIG_USART4_SERIALDRIVER is not set
+# CONFIG_USART5_SERIALDRIVER is not set
+# CONFIG_USART6_SERIALDRIVER is not set
+# CONFIG_USART7_SERIALDRIVER is not set
+# CONFIG_USART8_SERIALDRIVER is not set
+# CONFIG_OTHER_UART_SERIALDRIVER is not set
+CONFIG_MCU_SERIAL=y
+CONFIG_STANDARD_SERIAL=y
+# CONFIG_SERIAL_IFLOWCONTROL is not set
+# CONFIG_SERIAL_OFLOWCONTROL is not set
+# CONFIG_SERIAL_DMA is not set
+CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y
+CONFIG_USART3_SERIAL_CONSOLE=y
+# CONFIG_UART8_SERIAL_CONSOLE is not set
+# CONFIG_OTHER_SERIAL_CONSOLE is not set
+# CONFIG_NO_SERIAL_CONSOLE is not set
+
+#
+# USART3 Configuration
+#
+CONFIG_USART3_RXBUFSIZE=256
+CONFIG_USART3_TXBUFSIZE=256
+CONFIG_USART3_BAUD=115200
+CONFIG_USART3_BITS=8
+CONFIG_USART3_PARITY=0
+CONFIG_USART3_2STOP=0
+# CONFIG_USART3_IFLOWCONTROL is not set
+# CONFIG_USART3_OFLOWCONTROL is not set
+# CONFIG_USART3_DMA is not set
+# CONFIG_USBDEV is not set
+# CONFIG_USBHOST is not set
+# CONFIG_DRIVERS_WIRELESS is not set
+
+#
+# System Logging Device Options
+#
+
+#
+# System Logging
+#
+# CONFIG_RAMLOG is not set
+# CONFIG_SYSLOG_CONSOLE is not set
+
+#
+# Networking Support
+#
+# CONFIG_ARCH_HAVE_NET is not set
+# CONFIG_ARCH_HAVE_PHY is not set
+# CONFIG_NET is not set
+
+#
+# Crypto API
+#
+# CONFIG_CRYPTO is not set
+
+#
+# File Systems
+#
+
+#
+# File system configuration
+#
+# CONFIG_DISABLE_MOUNTPOINT is not set
+# CONFIG_FS_AUTOMOUNTER is not set
+# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set
+# CONFIG_FS_READABLE is not set
+# CONFIG_FS_WRITABLE is not set
+# CONFIG_FS_AIO is not set
+# CONFIG_FS_NAMED_SEMAPHORES is not set
+CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
+# CONFIG_FS_RAMMAP is not set
+# CONFIG_FS_FAT is not set
+# CONFIG_FS_NXFFS is not set
+# CONFIG_FS_ROMFS is not set
+# CONFIG_FS_TMPFS is not set
+# CONFIG_FS_SMARTFS is not set
+# CONFIG_FS_BINFS is not set
+# CONFIG_FS_PROCFS is not set
+# CONFIG_FS_UNIONFS is not set
+
+#
+# System Logging
+#
+# CONFIG_SYSLOG is not set
+# CONFIG_SYSLOG_TIMESTAMP is not set
+
+#
+# Graphics Support
+#
+# CONFIG_NX is not set
+
+#
+# Memory Management
+#
+# CONFIG_MM_SMALL is not set
+CONFIG_MM_REGIONS=2
+# CONFIG_ARCH_HAVE_HEAP2 is not set
+# CONFIG_GRAN is not set
+
+#
+# Audio Support
+#
+# CONFIG_AUDIO is not set
+
+#
+# Wireless Support
+#
+
+#
+# Binary Loader
+#
+# CONFIG_BINFMT_DISABLE is not set
+# CONFIG_BINFMT_EXEPATH is not set
+# CONFIG_NXFLAT is not set
+# CONFIG_ELF is not set
+CONFIG_BUILTIN=y
+# CONFIG_PIC is not set
+# CONFIG_SYMTAB_ORDEREDBYNAME is not set
+
+#
+# Library Routines
+#
+
+#
+# Standard C Library Options
+#
+CONFIG_STDIO_BUFFER_SIZE=64
+CONFIG_STDIO_LINEBUFFER=y
+CONFIG_NUNGET_CHARS=2
+CONFIG_LIB_HOMEDIR="/"
+# CONFIG_LIBM is not set
+# CONFIG_NOPRINTF_FIELDWIDTH is not set
+# CONFIG_LIBC_FLOATINGPOINT is not set
+CONFIG_LIBC_LONG_LONG=y
+# CONFIG_LIBC_IOCTL_VARIADIC is not set
+CONFIG_LIB_RAND_ORDER=1
+# CONFIG_EOL_IS_CR is not set
+# CONFIG_EOL_IS_LF is not set
+# CONFIG_EOL_IS_BOTH_CRLF is not set
+CONFIG_EOL_IS_EITHER_CRLF=y
+# CONFIG_LIBC_EXECFUNCS is not set
+CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024
+CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048
+# CONFIG_LIBC_STRERROR is not set
+# CONFIG_LIBC_PERROR_STDOUT is not set
+CONFIG_ARCH_LOWPUTC=y
+# CONFIG_LIBC_LOCALTIME is not set
+# CONFIG_TIME_EXTENDED is not set
+CONFIG_LIB_SENDFILE_BUFSIZE=512
+# CONFIG_ARCH_ROMGETC is not set
+# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
+CONFIG_ARCH_HAVE_TLS=y
+# CONFIG_TLS is not set
+# CONFIG_LIBC_NETDB is not set
+
+#
+# Non-standard Library Support
+#
+# CONFIG_LIB_KBDCODEC is not set
+# CONFIG_LIB_SLCDCODEC is not set
+
+#
+# Basic CXX Support
+#
+# CONFIG_C99_BOOL8 is not set
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+# CONFIG_CXX_NEWLONG is not set
+
+#
+# uClibc++ Standard C++ Library
+#
+# CONFIG_UCLIBCXX is not set
+
+#
+# Application Configuration
+#
+
+#
+# Built-In Applications
+#
+CONFIG_BUILTIN_PROXY_STACKSIZE=1024
+
+#
+# CAN Utilities
+#
+
+#
+# Examples
+#
+# CONFIG_EXAMPLES_BUTTONS is not set
+# CONFIG_EXAMPLES_CHAT is not set
+# CONFIG_EXAMPLES_CONFIGDATA is not set
+# CONFIG_EXAMPLES_CPUHOG is not set
+# CONFIG_EXAMPLES_CXXTEST is not set
+# CONFIG_EXAMPLES_DHCPD is not set
+# CONFIG_EXAMPLES_ELF is not set
+# CONFIG_EXAMPLES_FTPC is not set
+# CONFIG_EXAMPLES_FTPD is not set
+# CONFIG_EXAMPLES_HELLO is not set
+CONFIG_EXAMPLES_HELLOXX=y
+CONFIG_EXAMPLES_HELLOXX_CXXINITIALIZE=y
+# CONFIG_EXAMPLES_JSON is not set
+# CONFIG_EXAMPLES_HIDKBD is not set
+# CONFIG_EXAMPLES_KEYPADTEST is not set
+# CONFIG_EXAMPLES_IGMP is not set
+CONFIG_EXAMPLES_LEDS=y
+CONFIG_EXAMPLES_LEDS_PRIORITY=100
+CONFIG_EXAMPLES_LEDS_STACKSIZE=2048
+CONFIG_EXAMPLES_LEDS_DEVPATH="/dev/userleds"
+CONFIG_EXAMPLES_LEDS_LEDSET=0x0f
+# CONFIG_EXAMPLES_MEDIA is not set
+# CONFIG_EXAMPLES_MM is not set
+# CONFIG_EXAMPLES_MODBUS is not set
+# CONFIG_EXAMPLES_MOUNT is not set
+# CONFIG_EXAMPLES_NRF24L01TERM is not set
+CONFIG_EXAMPLES_NSH=y
+CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
+# CONFIG_EXAMPLES_NULL is not set
+# CONFIG_EXAMPLES_NX is not set
+# CONFIG_EXAMPLES_NXTERM is not set
+# CONFIG_EXAMPLES_NXFFS is not set
+# CONFIG_EXAMPLES_NXHELLO is not set
+# CONFIG_EXAMPLES_NXIMAGE is not set
+# CONFIG_EXAMPLES_NXLINES is not set
+# CONFIG_EXAMPLES_NXTEXT is not set
+# CONFIG_EXAMPLES_OSTEST is not set
+# CONFIG_EXAMPLES_PCA9635 is not set
+# CONFIG_EXAMPLES_PIPE is not set
+# CONFIG_EXAMPLES_PPPD is not set
+# CONFIG_EXAMPLES_POSIXSPAWN is not set
+# CONFIG_EXAMPLES_RGBLED is not set
+# CONFIG_EXAMPLES_RGMP is not set
+# CONFIG_EXAMPLES_SENDMAIL is not set
+# CONFIG_EXAMPLES_SERIALBLASTER is not set
+# CONFIG_EXAMPLES_SERIALRX is not set
+# CONFIG_EXAMPLES_SERLOOP is not set
+# CONFIG_EXAMPLES_SLCD is not set
+# CONFIG_EXAMPLES_SMART_TEST is not set
+# CONFIG_EXAMPLES_SMART is not set
+# CONFIG_EXAMPLES_SMP is not set
+# CONFIG_EXAMPLES_TCPECHO is not set
+# CONFIG_EXAMPLES_TELNETD is not set
+# CONFIG_EXAMPLES_TIFF is not set
+# CONFIG_EXAMPLES_TOUCHSCREEN is not set
+# CONFIG_EXAMPLES_WEBSERVER is not set
+# CONFIG_EXAMPLES_USBSERIAL is not set
+# CONFIG_EXAMPLES_USBTERM is not set
+# CONFIG_EXAMPLES_WATCHDOG is not set
+
+#
+# File System Utilities
+#
+# CONFIG_FSUTILS_INIFILE is not set
+
+#
+# GPS Utilities
+#
+# CONFIG_GPSUTILS_MINMEA_LIB is not set
+
+#
+# Graphics Support
+#
+# CONFIG_TIFF is not set
+# CONFIG_GRAPHICS_TRAVELER is not set
+
+#
+# Interpreters
+#
+# CONFIG_INTERPRETERS_FICL is not set
+# CONFIG_INTERPRETERS_PCODE is not set
+# CONFIG_INTERPRETERS_MICROPYTHON is not set
+
+#
+# FreeModBus
+#
+# CONFIG_MODBUS is not set
+
+#
+# Network Utilities
+#
+# CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_ESP8266 is not set
+# CONFIG_NETUTILS_FTPC is not set
+# CONFIG_NETUTILS_JSON is not set
+# CONFIG_NETUTILS_SMTP is not set
+
+#
+# NSH Library
+#
+CONFIG_NSH_LIBRARY=y
+# CONFIG_NSH_MOTD is not set
+
+#
+# Command Line Configuration
+#
+CONFIG_NSH_READLINE=y
+# CONFIG_NSH_CLE is not set
+CONFIG_NSH_LINELEN=64
+# CONFIG_NSH_DISABLE_SEMICOLON is not set
+CONFIG_NSH_CMDPARMS=y
+CONFIG_NSH_MAXARGUMENTS=6
+CONFIG_NSH_ARGCAT=y
+CONFIG_NSH_NESTDEPTH=3
+# CONFIG_NSH_DISABLEBG is not set
+CONFIG_NSH_BUILTIN_APPS=y
+
+#
+# Disable Individual commands
+#
+# CONFIG_NSH_DISABLE_ADDROUTE is not set
+# CONFIG_NSH_DISABLE_BASENAME is not set
+# CONFIG_NSH_DISABLE_CAT is not set
+# CONFIG_NSH_DISABLE_CD is not set
+# CONFIG_NSH_DISABLE_CP is not set
+# CONFIG_NSH_DISABLE_CMP is not set
+# CONFIG_NSH_DISABLE_DATE is not set
+# CONFIG_NSH_DISABLE_DD is not set
+# CONFIG_NSH_DISABLE_DF is not set
+# CONFIG_NSH_DISABLE_DELROUTE is not set
+# CONFIG_NSH_DISABLE_DIRNAME is not set
+# CONFIG_NSH_DISABLE_ECHO is not set
+# CONFIG_NSH_DISABLE_EXEC is not set
+# CONFIG_NSH_DISABLE_EXIT is not set
+# CONFIG_NSH_DISABLE_FREE is not set
+# CONFIG_NSH_DISABLE_GET is not set
+# CONFIG_NSH_DISABLE_HELP is not set
+# CONFIG_NSH_DISABLE_HEXDUMP is not set
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+# CONFIG_NSH_DISABLE_KILL is not set
+# CONFIG_NSH_DISABLE_LOSETUP is not set
+CONFIG_NSH_DISABLE_LOSMART=y
+# CONFIG_NSH_DISABLE_LS is not set
+# CONFIG_NSH_DISABLE_MB is not set
+# CONFIG_NSH_DISABLE_MKDIR is not set
+# CONFIG_NSH_DISABLE_MKFIFO is not set
+# CONFIG_NSH_DISABLE_MKRD is not set
+# CONFIG_NSH_DISABLE_MH is not set
+# CONFIG_NSH_DISABLE_MOUNT is not set
+# CONFIG_NSH_DISABLE_MV is not set
+# CONFIG_NSH_DISABLE_MW is not set
+# CONFIG_NSH_DISABLE_PS is not set
+# CONFIG_NSH_DISABLE_PUT is not set
+# CONFIG_NSH_DISABLE_PWD is not set
+# CONFIG_NSH_DISABLE_RM is not set
+# CONFIG_NSH_DISABLE_RMDIR is not set
+# CONFIG_NSH_DISABLE_SET is not set
+# CONFIG_NSH_DISABLE_SH is not set
+# CONFIG_NSH_DISABLE_SLEEP is not set
+# CONFIG_NSH_DISABLE_TIME is not set
+# CONFIG_NSH_DISABLE_TEST is not set
+# CONFIG_NSH_DISABLE_UMOUNT is not set
+# CONFIG_NSH_DISABLE_UNAME is not set
+# CONFIG_NSH_DISABLE_UNSET is not set
+# CONFIG_NSH_DISABLE_USLEEP is not set
+# CONFIG_NSH_DISABLE_WGET is not set
+# CONFIG_NSH_DISABLE_XD is not set
+
+#
+# Configure Command Options
+#
+CONFIG_NSH_CMDOPT_DF_H=y
+CONFIG_NSH_CODECS_BUFSIZE=128
+CONFIG_NSH_CMDOPT_HEXDUMP=y
+CONFIG_NSH_FILEIOSIZE=512
+
+#
+# Scripting Support
+#
+# CONFIG_NSH_DISABLESCRIPT is not set
+# CONFIG_NSH_DISABLE_ITEF is not set
+# CONFIG_NSH_DISABLE_LOOPS is not set
+
+#
+# Console Configuration
+#
+CONFIG_NSH_CONSOLE=y
+# CONFIG_NSH_ALTCONDEV is not set
+CONFIG_NSH_ARCHINIT=y
+# CONFIG_NSH_LOGIN is not set
+# CONFIG_NSH_CONSOLE_LOGIN is not set
+
+#
+# NxWidgets/NxWM
+#
+
+#
+# Platform-specific Support
+#
+# CONFIG_PLATFORM_CONFIGDATA is not set
+
+#
+# System Libraries and NSH Add-Ons
+#
+# CONFIG_SYSTEM_FREE is not set
+# CONFIG_SYSTEM_CLE is not set
+# CONFIG_SYSTEM_CUTERM is not set
+# CONFIG_SYSTEM_INSTALL is not set
+# CONFIG_SYSTEM_HEX2BIN is not set
+# CONFIG_SYSTEM_HEXED is not set
+# CONFIG_SYSTEM_RAMTEST is not set
+CONFIG_READLINE_HAVE_EXTMATCH=y
+CONFIG_SYSTEM_READLINE=y
+CONFIG_READLINE_ECHO=y
+CONFIG_READLINE_TABCOMPLETION=y
+CONFIG_READLINE_MAX_BUILTINS=64
+CONFIG_READLINE_MAX_EXTCMDS=64
+CONFIG_READLINE_CMD_HISTORY=y
+CONFIG_READLINE_CMD_HISTORY_LINELEN=80
+CONFIG_READLINE_CMD_HISTORY_LEN=16
+# CONFIG_SYSTEM_SUDOKU is not set
+# CONFIG_SYSTEM_VI is not set
+# CONFIG_SYSTEM_STACKMONITOR is not set
+# CONFIG_SYSTEM_UBLOXMODEM is not set
+# CONFIG_SYSTEM_ZMODEM is not set
diff --git a/configs/nucleo-144/f767-evalos/setenv.sh b/configs/nucleo-144/f767-evalos/setenv.sh
new file mode 100644
index 0000000000..cf10804e84
--- /dev/null
+++ b/configs/nucleo-144/f767-evalos/setenv.sh
@@ -0,0 +1,78 @@
+#!/bin/bash
+# configs/nucleo-144/f767-evalos/setenv.sh
+#
+# Copyright (C) 2016 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt
+# Author: Mark Olsson
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+if [ "$_" = "$0" ] ; then
+ echo "You must source this script, not run it!" 1>&2
+ exit 1
+fi
+
+WD=`pwd`
+if [ ! -x "setenv.sh" ]; then
+ echo "This script must be executed from the top-level NuttX build directory"
+ exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then
+ export PATH_ORIG="${PATH}"
+fi
+
+# This is the Cygwin path to the location where I installed the Atmel GCC
+# toolchain under Windows. You will also have to edit this if you install
+# this toolchain in any other location
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin"
+
+# This is the Cygwin path to the location where I installed the CodeSourcery
+# toolchain under windows. You will also have to edit this if you install
+# the CodeSourcery toolchain in any other location
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
+# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
+
+# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors"
+# You can this free toolchain here https://launchpad.net/gcc-arm-embedded
+export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin"
+
+# This is the path to the location where I installed the devkitARM toolchain
+# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin"
+
+# This is the Cygwin path to the location where I build the buildroot
+# toolchain.
+# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin"
+
+# Add the path to the toolchain to the PATH varialble
+export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
+
+echo "PATH : ${PATH}"
diff --git a/configs/nucleo-144/evalos/Make.defs b/configs/nucleo-144/f767-nsh/Make.defs
similarity index 96%
rename from configs/nucleo-144/evalos/Make.defs
rename to configs/nucleo-144/f767-nsh/Make.defs
index 210c5ff074..9b667c97ef 100644
--- a/configs/nucleo-144/evalos/Make.defs
+++ b/configs/nucleo-144/f767-nsh/Make.defs
@@ -1,9 +1,9 @@
############################################################################
-# configs/nucleo-144/evalos/Make.defs
+# configs/nucleo-144/f767-nsh/Make.defs
#
# Copyright (C) 2016 Gregory Nutt. All rights reserved.
-# Author: Gregory Nutt
-# Author: Mark Olsson
+# Authors: Gregory Nutt
+# David Sidrane
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
@@ -38,7 +38,7 @@ include ${TOPDIR}/.config
include ${TOPDIR}/tools/Config.mk
include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
-LDSCRIPT = flash.ld
+LDSCRIPT = f767-flash.ld
ifeq ($(WINTOOL),y)
# Windows-native toolchains
@@ -111,3 +111,4 @@ HOSTCC = gcc
HOSTINCLUDES = -I.
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
HOSTLDFLAGS =
+
diff --git a/configs/nucleo-144/f767-nsh/defconfig b/configs/nucleo-144/f767-nsh/defconfig
new file mode 100644
index 0000000000..8e7fae13a4
--- /dev/null
+++ b/configs/nucleo-144/f767-nsh/defconfig
@@ -0,0 +1,1021 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Nuttx/ Configuration
+#
+
+#
+# Build Setup
+#
+# CONFIG_EXPERIMENTAL is not set
+# CONFIG_DEFAULT_SMALL is not set
+CONFIG_HOST_LINUX=y
+# CONFIG_HOST_OSX is not set
+# CONFIG_HOST_WINDOWS is not set
+# CONFIG_HOST_OTHER is not set
+
+#
+# Build Configuration
+#
+CONFIG_APPS_DIR="../apps"
+CONFIG_BUILD_FLAT=y
+# CONFIG_BUILD_2PASS is not set
+
+#
+# Binary Output Formats
+#
+# CONFIG_RRLOAD_BINARY is not set
+# CONFIG_INTELHEX_BINARY is not set
+# CONFIG_MOTOROLA_SREC is not set
+CONFIG_RAW_BINARY=y
+# CONFIG_UBOOT_UIMAGE is not set
+
+#
+# Customize Header Files
+#
+# CONFIG_ARCH_STDINT_H is not set
+# CONFIG_ARCH_STDBOOL_H is not set
+# CONFIG_ARCH_MATH_H is not set
+# CONFIG_ARCH_FLOAT_H is not set
+# CONFIG_ARCH_STDARG_H is not set
+# CONFIG_ARCH_DEBUG_H is not set
+
+#
+# Debug Options
+#
+# CONFIG_DEBUG is not set
+CONFIG_ARCH_HAVE_HEAPCHECK=y
+CONFIG_ARCH_HAVE_STACKCHECK=y
+CONFIG_STACK_COLORATION=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_ARCH_HAVE_CUSTOMOPT=y
+CONFIG_DEBUG_NOOPT=y
+# CONFIG_DEBUG_CUSTOMOPT is not set
+# CONFIG_DEBUG_FULLOPT is not set
+
+#
+# System Type
+#
+CONFIG_ARCH_ARM=y
+# CONFIG_ARCH_AVR is not set
+# CONFIG_ARCH_HC is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_RGMP is not set
+# CONFIG_ARCH_SH is not set
+# CONFIG_ARCH_SIM is not set
+# CONFIG_ARCH_X86 is not set
+# CONFIG_ARCH_Z16 is not set
+# CONFIG_ARCH_Z80 is not set
+CONFIG_ARCH="arm"
+
+#
+# ARM Options
+#
+# CONFIG_ARCH_CHIP_A1X is not set
+# CONFIG_ARCH_CHIP_C5471 is not set
+# CONFIG_ARCH_CHIP_CALYPSO is not set
+# CONFIG_ARCH_CHIP_DM320 is not set
+# CONFIG_ARCH_CHIP_EFM32 is not set
+# CONFIG_ARCH_CHIP_IMX1 is not set
+# CONFIG_ARCH_CHIP_IMX6 is not set
+# CONFIG_ARCH_CHIP_KINETIS is not set
+# CONFIG_ARCH_CHIP_KL is not set
+# CONFIG_ARCH_CHIP_LM is not set
+# CONFIG_ARCH_CHIP_TIVA is not set
+# CONFIG_ARCH_CHIP_LPC11XX is not set
+# CONFIG_ARCH_CHIP_LPC17XX is not set
+# CONFIG_ARCH_CHIP_LPC214X is not set
+# CONFIG_ARCH_CHIP_LPC2378 is not set
+# CONFIG_ARCH_CHIP_LPC31XX is not set
+# CONFIG_ARCH_CHIP_LPC43XX is not set
+# CONFIG_ARCH_CHIP_NUC1XX is not set
+# CONFIG_ARCH_CHIP_SAMA5 is not set
+# CONFIG_ARCH_CHIP_SAMD is not set
+# CONFIG_ARCH_CHIP_SAML is not set
+# CONFIG_ARCH_CHIP_SAM34 is not set
+# CONFIG_ARCH_CHIP_SAMV7 is not set
+# CONFIG_ARCH_CHIP_STM32 is not set
+CONFIG_ARCH_CHIP_STM32F7=y
+# CONFIG_ARCH_CHIP_STM32L4 is not set
+# CONFIG_ARCH_CHIP_STR71X is not set
+# CONFIG_ARCH_CHIP_TMS570 is not set
+# CONFIG_ARCH_CHIP_MOXART is not set
+# CONFIG_ARCH_ARM7TDMI is not set
+# CONFIG_ARCH_ARM926EJS is not set
+# CONFIG_ARCH_ARM920T is not set
+# CONFIG_ARCH_CORTEXM0 is not set
+# CONFIG_ARCH_CORTEXM3 is not set
+# CONFIG_ARCH_CORTEXM4 is not set
+CONFIG_ARCH_CORTEXM7=y
+# CONFIG_ARCH_CORTEXA5 is not set
+# CONFIG_ARCH_CORTEXA8 is not set
+# CONFIG_ARCH_CORTEXA9 is not set
+# CONFIG_ARCH_CORTEXR4 is not set
+# CONFIG_ARCH_CORTEXR4F is not set
+# CONFIG_ARCH_CORTEXR5 is not set
+# CONFIG_ARCH_CORTEX5F is not set
+# CONFIG_ARCH_CORTEXR7 is not set
+# CONFIG_ARCH_CORTEXR7F is not set
+CONFIG_ARCH_FAMILY="armv7-m"
+CONFIG_ARCH_CHIP="stm32f7"
+# CONFIG_ARM_TOOLCHAIN_IAR is not set
+CONFIG_ARM_TOOLCHAIN_GNU=y
+# CONFIG_ARMV7M_USEBASEPRI is not set
+CONFIG_ARCH_HAVE_CMNVECTOR=y
+CONFIG_ARMV7M_CMNVECTOR=y
+# CONFIG_ARMV7M_LAZYFPU is not set
+CONFIG_ARCH_HAVE_FPU=y
+CONFIG_ARCH_HAVE_DPFPU=y
+# CONFIG_ARCH_FPU is not set
+# CONFIG_ARCH_HAVE_TRUSTZONE is not set
+CONFIG_ARM_HAVE_MPU_UNIFIED=y
+# CONFIG_ARM_MPU is not set
+
+#
+# ARMV7M Configuration Options
+#
+CONFIG_ARMV7M_HAVE_ICACHE=y
+CONFIG_ARMV7M_HAVE_DCACHE=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
+CONFIG_ARMV7M_HAVE_ITCM=y
+CONFIG_ARMV7M_HAVE_DTCM=y
+# CONFIG_ARMV7M_ITCM is not set
+CONFIG_ARMV7M_DTCM=y
+# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set
+# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
+# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
+# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
+CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y
+CONFIG_ARMV7M_HAVE_STACKCHECK=y
+# CONFIG_ARMV7M_STACKCHECK is not set
+# CONFIG_ARMV7M_ITMSYSLOG is not set
+# CONFIG_SERIAL_TERMIOS is not set
+# CONFIG_USART6_RS485 is not set
+CONFIG_SERIAL_DISABLE_REORDERING=y
+
+#
+# STM32 F7 Configuration Options
+#
+# CONFIG_ARCH_CHIP_STM32F745VG is not set
+# CONFIG_ARCH_CHIP_STM32F745VE is not set
+# CONFIG_ARCH_CHIP_STM32F745IG is not set
+# CONFIG_ARCH_CHIP_STM32F745IE is not set
+# CONFIG_ARCH_CHIP_STM32F745ZE is not set
+# CONFIG_ARCH_CHIP_STM32F745ZG is not set
+# CONFIG_ARCH_CHIP_STM32F746BG is not set
+# CONFIG_ARCH_CHIP_STM32F746VG is not set
+# CONFIG_ARCH_CHIP_STM32F746VE is not set
+# CONFIG_ARCH_CHIP_STM32F746BE is not set
+# CONFIG_ARCH_CHIP_STM32F746ZG is not set
+# CONFIG_ARCH_CHIP_STM32F746IE is not set
+# CONFIG_ARCH_CHIP_STM32F746NG is not set
+# CONFIG_ARCH_CHIP_STM32F746NE is not set
+# CONFIG_ARCH_CHIP_STM32F746ZE is not set
+# CONFIG_ARCH_CHIP_STM32F746IG is not set
+# CONFIG_ARCH_CHIP_STM32F756NG is not set
+# CONFIG_ARCH_CHIP_STM32F756BG is not set
+# CONFIG_ARCH_CHIP_STM32F756IG is not set
+# CONFIG_ARCH_CHIP_STM32F756VG is not set
+# CONFIG_ARCH_CHIP_STM32F756ZG is not set
+# CONFIG_ARCH_CHIP_STM32F765NI is not set
+# CONFIG_ARCH_CHIP_STM32F765VI is not set
+# CONFIG_ARCH_CHIP_STM32F765VG is not set
+# CONFIG_ARCH_CHIP_STM32F765BI is not set
+# CONFIG_ARCH_CHIP_STM32F765NG is not set
+# CONFIG_ARCH_CHIP_STM32F765ZG is not set
+# CONFIG_ARCH_CHIP_STM32F765ZI is not set
+# CONFIG_ARCH_CHIP_STM32F765IG is not set
+# CONFIG_ARCH_CHIP_STM32F765BG is not set
+# CONFIG_ARCH_CHIP_STM32F765II is not set
+# CONFIG_ARCH_CHIP_STM32F767NG is not set
+# CONFIG_ARCH_CHIP_STM32F767IG is not set
+# CONFIG_ARCH_CHIP_STM32F767VG is not set
+# CONFIG_ARCH_CHIP_STM32F767ZG is not set
+# CONFIG_ARCH_CHIP_STM32F767NI is not set
+# CONFIG_ARCH_CHIP_STM32F767VI is not set
+# CONFIG_ARCH_CHIP_STM32F767BG is not set
+CONFIG_ARCH_CHIP_STM32F767ZI=y
+# CONFIG_ARCH_CHIP_STM32F767II is not set
+# CONFIG_ARCH_CHIP_STM32F769BI is not set
+# CONFIG_ARCH_CHIP_STM32F769II is not set
+# CONFIG_ARCH_CHIP_STM32F769BG is not set
+# CONFIG_ARCH_CHIP_STM32F769NI is not set
+# CONFIG_ARCH_CHIP_STM32F769AI is not set
+# CONFIG_ARCH_CHIP_STM32F769NG is not set
+# CONFIG_ARCH_CHIP_STM32F769IG is not set
+# CONFIG_ARCH_CHIP_STM32F777ZI is not set
+# CONFIG_ARCH_CHIP_STM32F777VI is not set
+# CONFIG_ARCH_CHIP_STM32F777NI is not set
+# CONFIG_ARCH_CHIP_STM32F777BI is not set
+# CONFIG_ARCH_CHIP_STM32F777II is not set
+# CONFIG_ARCH_CHIP_STM32F778AI is not set
+# CONFIG_ARCH_CHIP_STM32F779II is not set
+# CONFIG_ARCH_CHIP_STM32F779NI is not set
+# CONFIG_ARCH_CHIP_STM32F779BI is not set
+# CONFIG_ARCH_CHIP_STM32F779AI is not set
+# CONFIG_STM32F7_STM32F74XX is not set
+# CONFIG_STM32F7_STM32F75XX is not set
+CONFIG_STM32F7_STM32F76XX=y
+# CONFIG_STM32F7_STM32F77XX is not set
+# CONFIG_STM32F7_IO_CONFIG_V is not set
+# CONFIG_STM32F7_IO_CONFIG_I is not set
+CONFIG_STM32F7_IO_CONFIG_Z=y
+# CONFIG_STM32F7_IO_CONFIG_N is not set
+# CONFIG_STM32F7_IO_CONFIG_B is not set
+# CONFIG_STM32F7_IO_CONFIG_A is not set
+# CONFIG_STM32F7_STM32F745XX is not set
+# CONFIG_STM32F7_STM32F746XX is not set
+# CONFIG_STM32F7_STM32F756XX is not set
+# CONFIG_STM32F7_STM32F765XX is not set
+CONFIG_STM32F7_STM32F767XX=y
+# CONFIG_STM32F7_STM32F768XX is not set
+# CONFIG_STM32F7_STM32F768AX is not set
+# CONFIG_STM32F7_STM32F769XX is not set
+# CONFIG_STM32F7_STM32F769AX is not set
+# CONFIG_STM32F7_STM32F777XX is not set
+# CONFIG_STM32F7_STM32F778XX is not set
+# CONFIG_STM32F7_STM32F778AX is not set
+# CONFIG_STM32F7_STM32F779XX is not set
+# CONFIG_STM32F7_STM32F779AX is not set
+# CONFIG_STM32F7_FLASH_CONFIG_E is not set
+CONFIG_STM32F7_FLASH_CONFIG_I=y
+CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT=y
+# CONFIG_STM32F7_FLASH_OVERRIDE_E is not set
+# CONFIG_STM32F7_FLASH_OVERRIDE_G is not set
+# CONFIG_STM32F7_FLASH_OVERRIDE_I is not set
+
+#
+# STM32 Peripheral Support
+#
+CONFIG_STM32F7_HAVE_LTDC=y
+CONFIG_STM32F7_HAVE_FSMC=y
+CONFIG_STM32F7_HAVE_ETHRNET=y
+CONFIG_STM32F7_HAVE_RNG=y
+CONFIG_STM32F7_HAVE_SPI5=y
+CONFIG_STM32F7_HAVE_SPI6=y
+CONFIG_STM32F7_HAVE_SDMMC2=y
+CONFIG_STM32F7_HAVE_CAN3=y
+CONFIG_STM32F7_HAVE_DCMI=y
+# CONFIG_STM32F7_HAVE_DSIHOST is not set
+CONFIG_STM32F7_HAVE_DMA2D=y
+CONFIG_STM32F7_HAVE_JPEG=y
+# CONFIG_STM32F7_HAVE_CRYP is not set
+# CONFIG_STM32F7_HAVE_HASH is not set
+CONFIG_STM32F7_HAVE_DFSDM1=y
+# CONFIG_STM32F7_ADC is not set
+# CONFIG_STM32F7_CAN is not set
+# CONFIG_STM32F7_DAC is not set
+# CONFIG_STM32F7_DMA is not set
+# CONFIG_STM32F7_I2C is not set
+# CONFIG_STM32F7_SAI is not set
+# CONFIG_STM32F7_SPI is not set
+CONFIG_STM32F7_USART=y
+# CONFIG_STM32F7_ADC1 is not set
+# CONFIG_STM32F7_ADC2 is not set
+# CONFIG_STM32F7_ADC3 is not set
+# CONFIG_STM32F7_BKPSRAM is not set
+# CONFIG_STM32F7_CAN1 is not set
+# CONFIG_STM32F7_CAN2 is not set
+# CONFIG_STM32F7_CAN3 is not set
+# CONFIG_STM32F7_CEC is not set
+# CONFIG_STM32F7_CRC is not set
+# CONFIG_STM32F7_DFSDM1 is not set
+# CONFIG_STM32F7_DMA1 is not set
+# CONFIG_STM32F7_DMA2 is not set
+# CONFIG_STM32F7_DAC1 is not set
+# CONFIG_STM32F7_DAC2 is not set
+# CONFIG_STM32F7_DCMI is not set
+# CONFIG_STM32F7_DMA2D is not set
+# CONFIG_STM32F7_JPEG is not set
+# CONFIG_STM32F7_ETHMAC is not set
+# CONFIG_STM32F7_FSMC is not set
+# CONFIG_STM32F7_I2C1 is not set
+# CONFIG_STM32F7_I2C2 is not set
+# CONFIG_STM32F7_I2C3 is not set
+# CONFIG_STM32F7_LPTIM1 is not set
+# CONFIG_STM32F7_LTDC is not set
+# CONFIG_STM32F7_OTGFS is not set
+# CONFIG_STM32F7_OTGHS is not set
+# CONFIG_STM32F7_QUADSPI is not set
+# CONFIG_STM32F7_RNG is not set
+# CONFIG_STM32F7_SAI1 is not set
+# CONFIG_STM32F7_SAI2 is not set
+# CONFIG_STM32F7_SDMMC1 is not set
+# CONFIG_STM32F7_SDMMC2 is not set
+# CONFIG_STM32F7_SPDIFRX is not set
+# CONFIG_STM32F7_SPI1 is not set
+# CONFIG_STM32F7_SPI2 is not set
+# CONFIG_STM32F7_SPI3 is not set
+# CONFIG_STM32F7_SPI4 is not set
+# CONFIG_STM32F7_SPI5 is not set
+# CONFIG_STM32F7_SPI6 is not set
+# CONFIG_STM32F7_TIM1 is not set
+# CONFIG_STM32F7_TIM2 is not set
+# CONFIG_STM32F7_TIM3 is not set
+# CONFIG_STM32F7_TIM4 is not set
+# CONFIG_STM32F7_TIM5 is not set
+# CONFIG_STM32F7_TIM6 is not set
+# CONFIG_STM32F7_TIM7 is not set
+# CONFIG_STM32F7_TIM8 is not set
+# CONFIG_STM32F7_TIM9 is not set
+# CONFIG_STM32F7_TIM10 is not set
+# CONFIG_STM32F7_TIM11 is not set
+# CONFIG_STM32F7_TIM12 is not set
+# CONFIG_STM32F7_TIM13 is not set
+# CONFIG_STM32F7_TIM14 is not set
+# CONFIG_STM32F7_TIM15 is not set
+# CONFIG_STM32F7_USART1 is not set
+# CONFIG_STM32F7_USART2 is not set
+# CONFIG_STM32F7_USART3 is not set
+# CONFIG_STM32F7_UART4 is not set
+# CONFIG_STM32F7_UART5 is not set
+CONFIG_STM32F7_USART6=y
+# CONFIG_STM32F7_UART7 is not set
+# CONFIG_STM32F7_UART8 is not set
+# CONFIG_STM32F7_IWDG is not set
+# CONFIG_STM32F7_WWDG is not set
+
+#
+# U[S]ART Configuration
+#
+CONFIG_STM32F7_FLOWCONTROL_BROKEN=y
+CONFIG_STM32F7_USART_BREAKS=y
+CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y
+# CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set
+
+#
+# Architecture Options
+#
+# CONFIG_ARCH_NOINTC is not set
+# CONFIG_ARCH_VECNOTIRQ is not set
+# CONFIG_ARCH_DMA is not set
+CONFIG_ARCH_HAVE_IRQPRIO=y
+# CONFIG_ARCH_L2CACHE is not set
+# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set
+# CONFIG_ARCH_HAVE_ADDRENV is not set
+# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set
+# CONFIG_ARCH_HAVE_MULTICPU is not set
+CONFIG_ARCH_HAVE_VFORK=y
+# CONFIG_ARCH_HAVE_MMU is not set
+CONFIG_ARCH_HAVE_MPU=y
+# CONFIG_ARCH_NAND_HWECC is not set
+# CONFIG_ARCH_HAVE_EXTCLK is not set
+# CONFIG_ARCH_HAVE_POWEROFF is not set
+# CONFIG_ARCH_HAVE_RESET is not set
+# CONFIG_ARCH_USE_MPU is not set
+# CONFIG_ARCH_IRQPRIO is not set
+CONFIG_ARCH_STACKDUMP=y
+# CONFIG_ENDIAN_BIG is not set
+# CONFIG_ARCH_IDLE_CUSTOM is not set
+# CONFIG_ARCH_HAVE_RAMFUNCS is not set
+CONFIG_ARCH_HAVE_RAMVECTORS=y
+# CONFIG_ARCH_RAMVECTORS is not set
+
+#
+# Board Settings
+#
+CONFIG_BOARD_LOOPSPERMSEC=43103
+# CONFIG_ARCH_CALIBRATION is not set
+
+#
+# Interrupt options
+#
+CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
+CONFIG_ARCH_INTERRUPTSTACK=0
+CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y
+# CONFIG_ARCH_HIPRI_INTERRUPT is not set
+
+#
+# Boot options
+#
+# CONFIG_BOOT_RUNFROMEXTSRAM is not set
+CONFIG_BOOT_RUNFROMFLASH=y
+# CONFIG_BOOT_RUNFROMISRAM is not set
+# CONFIG_BOOT_RUNFROMSDRAM is not set
+# CONFIG_BOOT_COPYTORAM is not set
+
+#
+# Boot Memory Configuration
+#
+CONFIG_RAM_START=0x20010000
+CONFIG_RAM_SIZE=245760
+# CONFIG_ARCH_HAVE_SDRAM is not set
+
+#
+# Board Selection
+#
+CONFIG_ARCH_BOARD_NUCLEO_144=y
+# CONFIG_ARCH_BOARD_CUSTOM is not set
+CONFIG_ARCH_BOARD="nucleo-144"
+
+#
+# Common Board Options
+#
+CONFIG_ARCH_HAVE_LEDS=y
+CONFIG_ARCH_LEDS=y
+CONFIG_ARCH_HAVE_BUTTONS=y
+CONFIG_ARCH_BUTTONS=y
+CONFIG_ARCH_HAVE_IRQBUTTONS=y
+# CONFIG_ARCH_IRQBUTTONS is not set
+CONFIG_NSH_MMCSDMINOR=0
+
+#
+# Board-Specific Options
+#
+CONFIG_NUCLEO_CONSOLE_ARDUINO=y
+# CONFIG_NUCLEO_CONSOLE_VIRTUAL is not set
+# CONFIG_NUCLEO_CONSOLE_MORPHO is not set
+# CONFIG_NUCLEO_CONSOLE_NONE is not set
+# CONFIG_NUCLEO_SPI_TEST is not set
+# CONFIG_LIB_BOARDCTL is not set
+
+#
+# RTOS Features
+#
+CONFIG_DISABLE_OS_API=y
+# CONFIG_DISABLE_POSIX_TIMERS is not set
+# CONFIG_DISABLE_PTHREAD is not set
+# CONFIG_DISABLE_SIGNALS is not set
+# CONFIG_DISABLE_MQUEUE is not set
+# CONFIG_DISABLE_ENVIRON is not set
+
+#
+# Clocks and Timers
+#
+CONFIG_USEC_PER_TICK=10000
+# CONFIG_SYSTEM_TIME64 is not set
+# CONFIG_CLOCK_MONOTONIC is not set
+# CONFIG_JULIAN_TIME is not set
+CONFIG_START_YEAR=2015
+CONFIG_START_MONTH=11
+CONFIG_START_DAY=30
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_PREALLOC_WDOGS=4
+CONFIG_WDOG_INTRESERVE=0
+CONFIG_PREALLOC_TIMERS=4
+
+#
+# Tasks and Scheduling
+#
+# CONFIG_INIT_NONE is not set
+CONFIG_INIT_ENTRYPOINT=y
+# CONFIG_INIT_FILEPATH is not set
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_RR_INTERVAL=200
+# CONFIG_SCHED_SPORADIC is not set
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_MAX_TASKS=16
+# CONFIG_SCHED_HAVE_PARENT is not set
+CONFIG_SCHED_WAITPID=y
+
+#
+# Pthread Options
+#
+# CONFIG_MUTEX_TYPES is not set
+CONFIG_NPTHREAD_KEYS=4
+
+#
+# Performance Monitoring
+#
+# CONFIG_SCHED_CPULOAD is not set
+# CONFIG_SCHED_INSTRUMENTATION is not set
+
+#
+# Files and I/O
+#
+CONFIG_DEV_CONSOLE=y
+# CONFIG_FDCLONE_DISABLE is not set
+# CONFIG_FDCLONE_STDIO is not set
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NAME_MAX=32
+# CONFIG_PRIORITY_INHERITANCE is not set
+
+#
+# RTOS hooks
+#
+# CONFIG_BOARD_INITIALIZE is not set
+# CONFIG_SCHED_STARTHOOK is not set
+# CONFIG_SCHED_ATEXIT is not set
+# CONFIG_SCHED_ONEXIT is not set
+
+#
+# Signal Numbers
+#
+CONFIG_SIG_SIGUSR1=1
+CONFIG_SIG_SIGUSR2=2
+CONFIG_SIG_SIGALARM=3
+CONFIG_SIG_SIGCONDTIMEDOUT=16
+
+#
+# POSIX Message Queue Options
+#
+CONFIG_PREALLOC_MQ_MSGS=4
+CONFIG_MQ_MAXMSGSIZE=32
+# CONFIG_MODULE is not set
+
+#
+# Work queue support
+#
+# CONFIG_SCHED_WORKQUEUE is not set
+# CONFIG_SCHED_HPWORK is not set
+# CONFIG_SCHED_LPWORK is not set
+
+#
+# Stack and heap information
+#
+CONFIG_IDLETHREAD_STACKSIZE=1024
+CONFIG_USERMAIN_STACKSIZE=2048
+CONFIG_PTHREAD_STACK_MIN=256
+CONFIG_PTHREAD_STACK_DEFAULT=2048
+# CONFIG_LIB_SYSCALL is not set
+
+#
+# Device Drivers
+#
+CONFIG_DISABLE_POLL=y
+CONFIG_DEV_NULL=y
+# CONFIG_DEV_ZERO is not set
+# CONFIG_DEV_LOOP is not set
+
+#
+# Buffering
+#
+# CONFIG_DRVR_WRITEBUFFER is not set
+# CONFIG_DRVR_READAHEAD is not set
+# CONFIG_RAMDISK is not set
+# CONFIG_CAN is not set
+# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set
+# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set
+# CONFIG_PWM is not set
+CONFIG_ARCH_HAVE_I2CRESET=y
+# CONFIG_I2C is not set
+CONFIG_SPI=y
+# CONFIG_SPI_SLAVE is not set
+CONFIG_SPI_EXCHANGE=y
+# CONFIG_SPI_CMDDATA is not set
+# CONFIG_SPI_CALLBACK is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_HWFEATURES is not set
+# CONFIG_SPI_CRCGENERATION is not set
+# CONFIG_I2S is not set
+
+#
+# Timer Driver Support
+#
+# CONFIG_TIMER is not set
+# CONFIG_RTC is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_ANALOG is not set
+# CONFIG_AUDIO_DEVICES is not set
+# CONFIG_VIDEO_DEVICES is not set
+# CONFIG_BCH is not set
+# CONFIG_INPUT is not set
+# CONFIG_IOEXPANDER is not set
+
+#
+# LCD Driver Support
+#
+# CONFIG_LCD is not set
+# CONFIG_SLCD is not set
+
+#
+# LED Support
+#
+# CONFIG_USERLED is not set
+# CONFIG_RGBLED is not set
+# CONFIG_PCA9635PW is not set
+# CONFIG_MMCSD is not set
+# CONFIG_MODEM is not set
+# CONFIG_MTD is not set
+# CONFIG_EEPROM is not set
+# CONFIG_PIPES is not set
+# CONFIG_PM is not set
+# CONFIG_POWER is not set
+# CONFIG_SENSORS is not set
+# CONFIG_SERCOMM_CONSOLE is not set
+CONFIG_SERIAL=y
+# CONFIG_DEV_LOWCONSOLE is not set
+# CONFIG_16550_UART is not set
+# CONFIG_UART_SERIALDRIVER is not set
+# CONFIG_UART0_SERIALDRIVER is not set
+# CONFIG_UART1_SERIALDRIVER is not set
+# CONFIG_UART2_SERIALDRIVER is not set
+# CONFIG_UART3_SERIALDRIVER is not set
+# CONFIG_UART4_SERIALDRIVER is not set
+# CONFIG_UART5_SERIALDRIVER is not set
+# CONFIG_UART6_SERIALDRIVER is not set
+# CONFIG_UART7_SERIALDRIVER is not set
+# CONFIG_UART8_SERIALDRIVER is not set
+# CONFIG_SCI0_SERIALDRIVER is not set
+# CONFIG_SCI1_SERIALDRIVER is not set
+# CONFIG_USART0_SERIALDRIVER is not set
+# CONFIG_USART1_SERIALDRIVER is not set
+# CONFIG_USART2_SERIALDRIVER is not set
+# CONFIG_USART3_SERIALDRIVER is not set
+# CONFIG_USART4_SERIALDRIVER is not set
+# CONFIG_USART5_SERIALDRIVER is not set
+CONFIG_USART6_SERIALDRIVER=y
+# CONFIG_USART7_SERIALDRIVER is not set
+# CONFIG_USART8_SERIALDRIVER is not set
+# CONFIG_OTHER_UART_SERIALDRIVER is not set
+CONFIG_MCU_SERIAL=y
+CONFIG_STANDARD_SERIAL=y
+# CONFIG_SERIAL_IFLOWCONTROL is not set
+# CONFIG_SERIAL_OFLOWCONTROL is not set
+# CONFIG_SERIAL_DMA is not set
+CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y
+CONFIG_USART6_SERIAL_CONSOLE=y
+# CONFIG_UART8_SERIAL_CONSOLE is not set
+# CONFIG_OTHER_SERIAL_CONSOLE is not set
+# CONFIG_NO_SERIAL_CONSOLE is not set
+
+#
+# USART6 Configuration
+#
+CONFIG_USART6_RXBUFSIZE=256
+CONFIG_USART6_TXBUFSIZE=256
+CONFIG_USART6_BAUD=115200
+CONFIG_USART6_BITS=8
+CONFIG_USART6_PARITY=0
+CONFIG_USART6_2STOP=0
+# CONFIG_USART6_IFLOWCONTROL is not set
+# CONFIG_USART6_OFLOWCONTROL is not set
+# CONFIG_USART6_DMA is not set
+# CONFIG_USBDEV is not set
+# CONFIG_USBHOST is not set
+# CONFIG_DRIVERS_WIRELESS is not set
+
+#
+# System Logging Device Options
+#
+
+#
+# System Logging
+#
+# CONFIG_RAMLOG is not set
+# CONFIG_SYSLOG_CONSOLE is not set
+
+#
+# Networking Support
+#
+# CONFIG_ARCH_HAVE_NET is not set
+# CONFIG_ARCH_HAVE_PHY is not set
+# CONFIG_NET is not set
+
+#
+# Crypto API
+#
+# CONFIG_CRYPTO is not set
+
+#
+# File Systems
+#
+
+#
+# File system configuration
+#
+# CONFIG_DISABLE_MOUNTPOINT is not set
+# CONFIG_FS_AUTOMOUNTER is not set
+# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set
+# CONFIG_FS_READABLE is not set
+# CONFIG_FS_WRITABLE is not set
+# CONFIG_FS_NAMED_SEMAPHORES is not set
+CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
+# CONFIG_FS_RAMMAP is not set
+# CONFIG_FS_FAT is not set
+# CONFIG_FS_NXFFS is not set
+# CONFIG_FS_ROMFS is not set
+# CONFIG_FS_TMPFS is not set
+# CONFIG_FS_SMARTFS is not set
+# CONFIG_FS_BINFS is not set
+# CONFIG_FS_PROCFS is not set
+# CONFIG_FS_UNIONFS is not set
+
+#
+# System Logging
+#
+# CONFIG_SYSLOG is not set
+# CONFIG_SYSLOG_TIMESTAMP is not set
+
+#
+# Graphics Support
+#
+# CONFIG_NX is not set
+
+#
+# Memory Management
+#
+# CONFIG_MM_SMALL is not set
+CONFIG_MM_REGIONS=2
+# CONFIG_ARCH_HAVE_HEAP2 is not set
+# CONFIG_GRAN is not set
+
+#
+# Audio Support
+#
+# CONFIG_AUDIO is not set
+
+#
+# Wireless Support
+#
+
+#
+# Binary Loader
+#
+# CONFIG_BINFMT_DISABLE is not set
+# CONFIG_BINFMT_EXEPATH is not set
+# CONFIG_NXFLAT is not set
+# CONFIG_ELF is not set
+CONFIG_BUILTIN=y
+# CONFIG_PIC is not set
+# CONFIG_SYMTAB_ORDEREDBYNAME is not set
+
+#
+# Library Routines
+#
+
+#
+# Standard C Library Options
+#
+CONFIG_STDIO_BUFFER_SIZE=64
+CONFIG_STDIO_LINEBUFFER=y
+CONFIG_NUNGET_CHARS=2
+CONFIG_LIB_HOMEDIR="/"
+# CONFIG_LIBM is not set
+# CONFIG_NOPRINTF_FIELDWIDTH is not set
+# CONFIG_LIBC_FLOATINGPOINT is not set
+CONFIG_LIBC_LONG_LONG=y
+# CONFIG_LIBC_IOCTL_VARIADIC is not set
+CONFIG_LIB_RAND_ORDER=1
+# CONFIG_EOL_IS_CR is not set
+# CONFIG_EOL_IS_LF is not set
+# CONFIG_EOL_IS_BOTH_CRLF is not set
+CONFIG_EOL_IS_EITHER_CRLF=y
+# CONFIG_LIBC_EXECFUNCS is not set
+CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024
+CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048
+# CONFIG_LIBC_STRERROR is not set
+# CONFIG_LIBC_PERROR_STDOUT is not set
+CONFIG_ARCH_LOWPUTC=y
+# CONFIG_LIBC_LOCALTIME is not set
+# CONFIG_TIME_EXTENDED is not set
+CONFIG_LIB_SENDFILE_BUFSIZE=512
+# CONFIG_ARCH_ROMGETC is not set
+# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
+CONFIG_ARCH_HAVE_TLS=y
+# CONFIG_TLS is not set
+# CONFIG_LIBC_NETDB is not set
+
+#
+# Non-standard Library Support
+#
+# CONFIG_LIB_KBDCODEC is not set
+# CONFIG_LIB_SLCDCODEC is not set
+
+#
+# Basic CXX Support
+#
+# CONFIG_C99_BOOL8 is not set
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+# CONFIG_CXX_NEWLONG is not set
+
+#
+# uClibc++ Standard C++ Library
+#
+# CONFIG_UCLIBCXX is not set
+
+#
+# Application Configuration
+#
+
+#
+# Built-In Applications
+#
+CONFIG_BUILTIN_PROXY_STACKSIZE=1024
+
+#
+# CAN Utilities
+#
+
+#
+# Examples
+#
+# CONFIG_EXAMPLES_BUTTONS is not set
+# CONFIG_EXAMPLES_CHAT is not set
+# CONFIG_EXAMPLES_CONFIGDATA is not set
+# CONFIG_EXAMPLES_CPUHOG is not set
+# CONFIG_EXAMPLES_CXXTEST is not set
+# CONFIG_EXAMPLES_DHCPD is not set
+# CONFIG_EXAMPLES_ELF is not set
+# CONFIG_EXAMPLES_FTPC is not set
+# CONFIG_EXAMPLES_FTPD is not set
+# CONFIG_EXAMPLES_HELLO is not set
+# CONFIG_EXAMPLES_HELLOXX is not set
+# CONFIG_EXAMPLES_JSON is not set
+# CONFIG_EXAMPLES_HIDKBD is not set
+# CONFIG_EXAMPLES_KEYPADTEST is not set
+# CONFIG_EXAMPLES_IGMP is not set
+# CONFIG_EXAMPLES_MEDIA is not set
+# CONFIG_EXAMPLES_MM is not set
+# CONFIG_EXAMPLES_MODBUS is not set
+# CONFIG_EXAMPLES_MOUNT is not set
+# CONFIG_EXAMPLES_NRF24L01TERM is not set
+CONFIG_EXAMPLES_NSH=y
+# CONFIG_EXAMPLES_NSH_CXXINITIALIZE is not set
+# CONFIG_EXAMPLES_NULL is not set
+# CONFIG_EXAMPLES_NX is not set
+# CONFIG_EXAMPLES_NXTERM is not set
+# CONFIG_EXAMPLES_NXFFS is not set
+# CONFIG_EXAMPLES_NXHELLO is not set
+# CONFIG_EXAMPLES_NXIMAGE is not set
+# CONFIG_EXAMPLES_NXLINES is not set
+# CONFIG_EXAMPLES_NXTEXT is not set
+# CONFIG_EXAMPLES_OSTEST is not set
+# CONFIG_EXAMPLES_PCA9635 is not set
+# CONFIG_EXAMPLES_PIPE is not set
+# CONFIG_EXAMPLES_PPPD is not set
+# CONFIG_EXAMPLES_POSIXSPAWN is not set
+# CONFIG_EXAMPLES_RGBLED is not set
+# CONFIG_EXAMPLES_RGMP is not set
+# CONFIG_EXAMPLES_SENDMAIL is not set
+# CONFIG_EXAMPLES_SERIALBLASTER is not set
+# CONFIG_EXAMPLES_SERIALRX is not set
+# CONFIG_EXAMPLES_SERLOOP is not set
+# CONFIG_EXAMPLES_SLCD is not set
+# CONFIG_EXAMPLES_SMART_TEST is not set
+# CONFIG_EXAMPLES_SMART is not set
+# CONFIG_EXAMPLES_SMP is not set
+# CONFIG_EXAMPLES_TCPECHO is not set
+# CONFIG_EXAMPLES_TELNETD is not set
+# CONFIG_EXAMPLES_TIFF is not set
+# CONFIG_EXAMPLES_TOUCHSCREEN is not set
+# CONFIG_EXAMPLES_WEBSERVER is not set
+# CONFIG_EXAMPLES_USBTERM is not set
+# CONFIG_EXAMPLES_WATCHDOG is not set
+
+#
+# File System Utilities
+#
+# CONFIG_FSUTILS_INIFILE is not set
+
+#
+# GPS Utilities
+#
+# CONFIG_GPSUTILS_MINMEA_LIB is not set
+
+#
+# Graphics Support
+#
+# CONFIG_TIFF is not set
+# CONFIG_GRAPHICS_TRAVELER is not set
+
+#
+# Interpreters
+#
+# CONFIG_INTERPRETERS_FICL is not set
+# CONFIG_INTERPRETERS_PCODE is not set
+# CONFIG_INTERPRETERS_MICROPYTHON is not set
+
+#
+# FreeModBus
+#
+# CONFIG_MODBUS is not set
+
+#
+# Network Utilities
+#
+# CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_ESP8266 is not set
+# CONFIG_NETUTILS_FTPC is not set
+# CONFIG_NETUTILS_JSON is not set
+# CONFIG_NETUTILS_SMTP is not set
+
+#
+# NSH Library
+#
+CONFIG_NSH_LIBRARY=y
+# CONFIG_NSH_MOTD is not set
+
+#
+# Command Line Configuration
+#
+CONFIG_NSH_READLINE=y
+# CONFIG_NSH_CLE is not set
+CONFIG_NSH_LINELEN=64
+# CONFIG_NSH_DISABLE_SEMICOLON is not set
+CONFIG_NSH_CMDPARMS=y
+CONFIG_NSH_MAXARGUMENTS=6
+CONFIG_NSH_ARGCAT=y
+CONFIG_NSH_NESTDEPTH=3
+# CONFIG_NSH_DISABLEBG is not set
+CONFIG_NSH_BUILTIN_APPS=y
+
+#
+# Disable Individual commands
+#
+# CONFIG_NSH_DISABLE_ADDROUTE is not set
+# CONFIG_NSH_DISABLE_BASENAME is not set
+# CONFIG_NSH_DISABLE_CAT is not set
+# CONFIG_NSH_DISABLE_CD is not set
+# CONFIG_NSH_DISABLE_CP is not set
+# CONFIG_NSH_DISABLE_CMP is not set
+CONFIG_NSH_DISABLE_DATE=y
+# CONFIG_NSH_DISABLE_DD is not set
+# CONFIG_NSH_DISABLE_DF is not set
+# CONFIG_NSH_DISABLE_DELROUTE is not set
+# CONFIG_NSH_DISABLE_DIRNAME is not set
+# CONFIG_NSH_DISABLE_ECHO is not set
+# CONFIG_NSH_DISABLE_EXEC is not set
+# CONFIG_NSH_DISABLE_EXIT is not set
+# CONFIG_NSH_DISABLE_FREE is not set
+# CONFIG_NSH_DISABLE_GET is not set
+# CONFIG_NSH_DISABLE_HELP is not set
+# CONFIG_NSH_DISABLE_HEXDUMP is not set
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+# CONFIG_NSH_DISABLE_KILL is not set
+# CONFIG_NSH_DISABLE_LOSETUP is not set
+CONFIG_NSH_DISABLE_LOSMART=y
+# CONFIG_NSH_DISABLE_LS is not set
+# CONFIG_NSH_DISABLE_MB is not set
+# CONFIG_NSH_DISABLE_MKDIR is not set
+# CONFIG_NSH_DISABLE_MKFIFO is not set
+# CONFIG_NSH_DISABLE_MKRD is not set
+# CONFIG_NSH_DISABLE_MH is not set
+# CONFIG_NSH_DISABLE_MOUNT is not set
+# CONFIG_NSH_DISABLE_MV is not set
+# CONFIG_NSH_DISABLE_MW is not set
+# CONFIG_NSH_DISABLE_PS is not set
+# CONFIG_NSH_DISABLE_PUT is not set
+# CONFIG_NSH_DISABLE_PWD is not set
+# CONFIG_NSH_DISABLE_RM is not set
+# CONFIG_NSH_DISABLE_RMDIR is not set
+# CONFIG_NSH_DISABLE_SET is not set
+# CONFIG_NSH_DISABLE_SH is not set
+# CONFIG_NSH_DISABLE_SLEEP is not set
+# CONFIG_NSH_DISABLE_TIME is not set
+# CONFIG_NSH_DISABLE_TEST is not set
+# CONFIG_NSH_DISABLE_UMOUNT is not set
+# CONFIG_NSH_DISABLE_UNAME is not set
+# CONFIG_NSH_DISABLE_UNSET is not set
+# CONFIG_NSH_DISABLE_USLEEP is not set
+# CONFIG_NSH_DISABLE_WGET is not set
+# CONFIG_NSH_DISABLE_XD is not set
+
+#
+# Configure Command Options
+#
+CONFIG_NSH_CMDOPT_DF_H=y
+CONFIG_NSH_CODECS_BUFSIZE=128
+CONFIG_NSH_CMDOPT_HEXDUMP=y
+CONFIG_NSH_FILEIOSIZE=512
+
+#
+# Scripting Support
+#
+# CONFIG_NSH_DISABLESCRIPT is not set
+# CONFIG_NSH_DISABLE_ITEF is not set
+# CONFIG_NSH_DISABLE_LOOPS is not set
+
+#
+# Console Configuration
+#
+CONFIG_NSH_CONSOLE=y
+# CONFIG_NSH_ALTCONDEV is not set
+# CONFIG_NSH_ARCHINIT is not set
+# CONFIG_NSH_LOGIN is not set
+# CONFIG_NSH_CONSOLE_LOGIN is not set
+
+#
+# NxWidgets/NxWM
+#
+
+#
+# Platform-specific Support
+#
+# CONFIG_PLATFORM_CONFIGDATA is not set
+
+#
+# System Libraries and NSH Add-Ons
+#
+# CONFIG_SYSTEM_FREE is not set
+# CONFIG_SYSTEM_CLE is not set
+# CONFIG_SYSTEM_CUTERM is not set
+# CONFIG_SYSTEM_INSTALL is not set
+# CONFIG_SYSTEM_HEX2BIN is not set
+# CONFIG_SYSTEM_HEXED is not set
+# CONFIG_SYSTEM_RAMTEST is not set
+CONFIG_READLINE_HAVE_EXTMATCH=y
+CONFIG_SYSTEM_READLINE=y
+CONFIG_READLINE_ECHO=y
+# CONFIG_READLINE_TABCOMPLETION is not set
+# CONFIG_READLINE_CMD_HISTORY is not set
+# CONFIG_SYSTEM_SUDOKU is not set
+# CONFIG_SYSTEM_VI is not set
+# CONFIG_SYSTEM_STACKMONITOR is not set
+# CONFIG_SYSTEM_UBLOXMODEM is not set
+# CONFIG_SYSTEM_ZMODEM is not set
diff --git a/configs/nucleo-144/f767-nsh/setenv.sh b/configs/nucleo-144/f767-nsh/setenv.sh
new file mode 100644
index 0000000000..e6eabd1f70
--- /dev/null
+++ b/configs/nucleo-144/f767-nsh/setenv.sh
@@ -0,0 +1,77 @@
+#!/bin/bash
+# configs/nucleo-144/f767-nsh/setenv.sh
+#
+# Copyright (C) 2016 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+if [ "$_" = "$0" ] ; then
+ echo "You must source this script, not run it!" 1>&2
+ exit 1
+fi
+
+WD=`pwd`
+if [ ! -x "setenv.sh" ]; then
+ echo "This script must be executed from the top-level NuttX build directory"
+ exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then
+ export PATH_ORIG="${PATH}"
+fi
+
+# This is the Cygwin path to the location where I installed the Atmel GCC
+# toolchain under Windows. You will also have to edit this if you install
+# this toolchain in any other location
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin"
+
+# This is the Cygwin path to the location where I installed the CodeSourcery
+# toolchain under windows. You will also have to edit this if you install
+# the CodeSourcery toolchain in any other location
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
+# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
+
+# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors"
+# You can this free toolchain here https://launchpad.net/gcc-arm-embedded
+export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin"
+
+# This is the path to the location where I installed the devkitARM toolchain
+# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin"
+
+# This is the Cygwin path to the location where I build the buildroot
+# toolchain.
+# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin"
+
+# Add the path to the toolchain to the PATH varialble
+export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
+
+echo "PATH : ${PATH}"
diff --git a/configs/nucleo-144/include/board.h b/configs/nucleo-144/include/board.h
index 63eb5df084..d309e13938 100644
--- a/configs/nucleo-144/include/board.h
+++ b/configs/nucleo-144/include/board.h
@@ -2,8 +2,9 @@
* configs/nucleo-144/include/board.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
- * Author: Mark Olsson
+ * Authors: Gregory Nutt
+ * Mark Olsson
+ * David Sidrane
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -59,17 +60,17 @@
************************************************************************************/
/* Clocking *************************************************************************/
-/* The STM32F7 Discovery board provides the following clock sources:
+/* The Nucleo-144 board provides the following clock sources:
*
- * X1: 24 MHz oscillator for USB OTG HS PHY and camera module (daughter board)
- * X2: 25 MHz oscillator for STM32F746NGH6 microcontroller and Ethernet PHY.
- * X3: 32.768 KHz crystal for STM32F746NGH6 embedded RTC
+ * MCO: 8 MHz from MCO output of ST-LINK is used as input clock
+ * X2: 32.768 KHz crystal for LSE
+ * X3: HSE crystal oscillator (not provided)
*
* So we have these clock source available within the STM32
*
* HSI: 16 MHz RC factory-trimmed
* LSI: 32 KHz RC
- * HSE: On-board crystal frequency is 25MHz
+ * HSE: 8 MHz from MCO output of ST-LINK
* LSE: 32.768 kHz
*/
@@ -106,56 +107,53 @@
* 2 <= PLLQ <= 15
*/
-#if defined(CONFIG_STM32F7_USBOTHFS)
/* Highest SYSCLK with USB OTG FS clock = 48 MHz
*
- * PLL_VCO = (8,000,000 / 8) * 384 = 384 MHz
- * SYSCLK = 384 MHz / 2 = 192 MHz
- * USB OTG FS, SDMMC and RNG Clock = 384 MHz / 8 = 48MHz
+ * PLL_VCO = (8,000,000 / 4) * 216 = 432 MHz
+ * SYSCLK = 432 MHz / 2 = 216 MHz
+ * USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48MHz
*/
-#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
-#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384)
+#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4)
+#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(216)
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
-#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
+#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(9)
-#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 8) * 384)
+#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 4) * 216)
#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
-#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 8)
+#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9)
-#elif defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_RNG)
-/* Highest SYSCLK with USB OTG FS clock <= 48MHz
- *
- * PLL_VCO = (8,000,000 / 8) * 432 = 432 MHz
- * SYSCLK = 432 MHz / 2 = 216 MHz
- * USB OTG FS, SDMMC and RNG Clock = 432 MHz / 10 = 43.2 MHz
- */
+/* Configure factors for PLLSAI clock */
-#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
-#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432)
-#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
-#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(10)
+#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192)
+#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2)
+#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2)
+#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
-#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 8) * 432)
-#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
-#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 10)
+/* Configure Dedicated Clock Configuration Register */
-#else
-/* Highest SYSCLK
- *
- * PLL_VCO = (8,000,000 / 8) * 432 = 432 MHz
- * SYSCLK = 432 MHz / 2 = 216 MHz
- */
+#define STM32_RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ(1)
+#define STM32_RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ(1)
+#define STM32_RCC_DCKCFGR_SAI1SRC RCC_DCKCFGR_SAI1SRC_PLLSAI
+#define STM32_RCC_DCKCFGR_SAI2SRC RCC_DCKCFGR_SAI2SRC_PLLSAI
+#define STM32_RCC_DCKCFGR_TIMPRE 0
+#define STM32_RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_SAI1SRC_PLL
+#define STM32_RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_SAI2SRC_PLL
-#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
-#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432)
-#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
-#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(10)
+/* Configure factors for PLLI2S clock */
-#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 8) * 432)
-#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
-#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 10)
-#endif
+#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
+#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
+#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
+#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
+
+/* Configure Dedicated Clock Configuration Register 2 */
+
+#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB
+#define STM32_RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_HSI
+#define STM32_RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_PLLSAI
+#define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ
+#define STM32_RCC_DCKCFGR2_SPDIFRXSEL RCC_DCKCFGR2_SPDIFRXSEL_PLL
/* Several prescalers allow the configuration of the two AHB buses, the
* high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
@@ -215,12 +213,9 @@
#define BOARD_FLASH_WAITSTATES 7
/* LED definitions ******************************************************************/
-/* The STM32F746G-DISCO board has numerous LEDs but only one, LD1 located near the
- * reset button, that can be controlled by software (LD2 is a power indicator, LD3-6
- * indicate USB status, LD7 is controlled by the ST-Link).
- *
- * LD1 is controlled by PI1 which is also the SPI2_SCK at the Arduino interface.
- * One end of LD1 is grounded so a high output on PI1 will illuminate the LED.
+/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, LD2 a Blue
+ * LED and LD3 a Red LED, that can be controlled by software. The following
+ * definitions assume the default Solder Bridges are installed.
*
* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way.
* The following definitions are used to access individual LEDs.
@@ -233,9 +228,9 @@
#define BOARD_LED3 2
#define BOARD_NLEDS 3
-#define BOARD_LD1 BOARD_LED1
-#define BOARD_LD2 BOARD_LED2
-#define BOARD_LD3 BOARD_LED3
+#define BOARD_LED_GREEN BOARD_LED1
+#define BOARD_LED_BLUE BOARD_LED2
+#define BOARD_LED_RED BOARD_LED3
/* LED bits for use with board_userled_all() */
@@ -247,33 +242,29 @@
* include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related
* events as follows:
*
- * SYMBOL Meaning LD1
- * ------------------- ----------------------- ------
- * LED_STARTED NuttX has been started OFF
- * LED_HEAPALLOCATE Heap has been allocated OFF
- * LED_IRQSENABLED Interrupts enabled OFF
- * LED_STACKCREATED Idle stack created ON
- * LED_INIRQ In an interrupt N/C
- * LED_SIGNAL In a signal handler N/C
- * LED_ASSERTION An assertion failed N/C
- * LED_PANIC The system has crashed FLASH
*
- * Thus is LD1 is statically on, NuttX has successfully booted and is,
- * apparently, running normally. If LD1 is flashing at approximately
- * 2Hz, then a fatal error has been detected and the system has halted.
+ * SYMBOL Meaning LED state
+ * Red Green Blue
+ * ---------------------- -------------------------- ------ ------ ----*/
+
+#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */
+#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */
+#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */
+#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */
+#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */
+#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */
+#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */
+#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */
+#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */
+
+/* Thus if the Green LED is statically on, NuttX has successfully booted and
+ * is, apparently, running normally. If the Red LED is flashing at
+ * approximately 2Hz, then a fatal error has been detected and the system
+ * has halted.
*/
-#define LED_STARTED 0 /* LD1=OFF */
-#define LED_HEAPALLOCATE 0 /* LD1=OFF */
-#define LED_IRQSENABLED 0 /* LD1=OFF */
-#define LED_STACKCREATED 1 /* LD1=ON */
-#define LED_INIRQ 2 /* LD1=no change */
-#define LED_SIGNAL 2 /* LD1=no change */
-#define LED_ASSERTION 2 /* LD1=no change */
-#define LED_PANIC 3 /* LD1=flashing */
-
/* Button definitions ***************************************************************/
-/* The STM32F7 Discovery supports one button: Pushbutton B1, labelled "User", is
+/* The STM32F7 Discovery supports one button: Pushbutton B1, labeled "User", is
* connected to GPIO PI11. A high value will be sensed when the button is depressed.
*/
@@ -283,6 +274,7 @@
/* Alternate function pin selections ************************************************/
+#if defined(CONFIG_NUCLEO_CONSOLE_ARDUINO)
/* USART6:
*
* These configurations assume that you are using a standard Arduio RS-232 shield
@@ -292,16 +284,32 @@
* STM32F7
* ARDUIONO FUNCTION GPIO
* -- ----- --------- -----
- * DO RX USART6_RX PC7
- * D1 TX USART6_TX PC6
+ * DO RX USART6_RX PG9
+ * D1 TX USART6_TX PG14
* -- ----- --------- -----
*/
- #define GPIO_USART6_RX GPIO_USART6_RX_1
- #define GPIO_USART6_TX GPIO_USART6_TX_1
+ # define GPIO_USART6_RX GPIO_USART6_RX_2
+ # define GPIO_USART6_TX GPIO_USART6_TX_2
+#endif
+
+/* USART3:
+ * Use USART3 and the USB virtual COM port
+*/
+#if defined(CONFIG_NUCLEO_CONSOLE_VIRTUAL)
+ # define GPIO_USART3_RX GPIO_USART3_RX_3
+ # define GPIO_USART3_TX GPIO_USART3_TX_3
+#endif
+
+/* USART8:
+ *
+ * This configurations assume that you are connecting to the Morpho connector
+ * with the serial interface with the adaptor's RX on pin CN11 pin 64 and
+ * TX on pin CN11 pin 61
+ *
+ * USART8: has noit remap
+ */
- #define GPIO_USART3_RX GPIO_USART3_RX_3
- #define GPIO_USART3_TX GPIO_USART3_TX_3
/* The STM32 F7 connects to a SMSC LAN8742A PHY using these pins:
*
diff --git a/configs/nucleo-144/scripts/flash.ld b/configs/nucleo-144/scripts/f746-flash.ld
similarity index 83%
rename from configs/nucleo-144/scripts/flash.ld
rename to configs/nucleo-144/scripts/f746-flash.ld
index 90e589ed8a..bc8b07e4fa 100644
--- a/configs/nucleo-144/scripts/flash.ld
+++ b/configs/nucleo-144/scripts/f746-flash.ld
@@ -1,10 +1,9 @@
/****************************************************************************
- * configs/nucleo-144/scripts/flash.ld
+ * configs/nucleo-144/scripts/f746-flash.ld
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
- * Modified 11/4/2013 for STM32F429 support
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -35,14 +34,14 @@
*
****************************************************************************/
-/* The STM32F746NGH6 has 1024Kb of main FLASH memory. This FLASH memory can
- * be accessed from either the AXIM interface at address 0x0800:0000 or from
- * the ITCM interface at address 0x0020:0000.
+/* The STM32F746ZGT6 has 1024 KiB of main FLASH memory. This FLASH memory
+ * can be accessed from either the AXIM interface at address 0x0800:0000 or
+ * from the ITCM interface at address 0x0020:0000.
*
* Additional information, including the option bytes, is available at at
* FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM).
*
- * In the STM32F746NGH6, two different boot spaces can be selected through
+ * In the STM32F746ZGT6, two different boot spaces can be selected through
* the BOOT pin and the boot base address programmed in the BOOT_ADD0 and
* BOOT_ADD1 option bytes:
*
@@ -51,16 +50,16 @@
* 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
* ST programmed value: System bootloader at 0x0010:0000
*
- * NuttX does not modify these option byes. On the unmodified STM32F746G
- * DISCO board, the BOOT0 pin is at ground so by default, the STM32 will boot
- * to address 0x0020:0000 in ITCM FLASH.
+ * NuttX does not modify these option byes. On the unmodified NUCLEO-144
+ * board, the BOOT0 pin is at ground so by default, the STM32F746ZGT6 will
+ * boot from address 0x0020:0000 in ITCM FLASH.
*
- * The STM32F746NGH6 also has 320Kb of data SRAM (in addition to ITCM SRAM).
+ * The STM32F746ZGT6 also has 320 KiB of data SRAM (in addition to ITCM SRAM).
* SRAM is split up into three blocks:
*
- * 1) 64Kb of DTCM SRM beginning at address 0x2000:0000
- * 2) 240Kb of SRAM1 beginning at address 0x2001:0000
- * 3) 16Kb of SRAM2 beginning at address 0x2004:c000
+ * 1) 64 KiB of DTCM SRM beginning at address 0x2000:0000
+ * 2) 240 KiB of SRAM1 beginning at address 0x2001:0000
+ * 3) 16 KiB of SRAM2 beginning at address 0x2004:c000
*
* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
* where the code expects to begin execution by jumping to the entry point in
diff --git a/configs/nucleo-144/scripts/f767-flash.ld b/configs/nucleo-144/scripts/f767-flash.ld
new file mode 100644
index 0000000000..6654a139fe
--- /dev/null
+++ b/configs/nucleo-144/scripts/f767-flash.ld
@@ -0,0 +1,146 @@
+/****************************************************************************
+ * configs/nucleo-144/scripts/f767-flash.ld
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt |