diff --git a/arch/sh/include/m16c/irq.h b/arch/sh/include/m16c/irq.h
index 77a3e31e1d6a88491a92fd9a9564ef8ebbcb99ec..2e29f6500564324e0ac02118c6c9ce3a4821300f 100644
--- a/arch/sh/include/m16c/irq.h
+++ b/arch/sh/include/m16c/irq.h
@@ -51,10 +51,150 @@
* Definitions
************************************************************************************/
-/* IRQ numbers -- to be provided */
+/* IRQ numbers **********************************************************************/
+
+/* Fixed vector table */
+
+#define M16C_UNDEFINST_IRQ 0 /* fffdc: Undefined instruction */
+#define M16C_OVERFLOW_IRQ 1 /* fffe0: Overflow */
+#define M16C_BRK_IRQ 2 /* fffe4: BRK instruction */
+#define M16C_ADDRMATCH_IRQ 3 /* fffe8: Address match */
+#ifdef CONFIG_M16C_DEBUGGER
+# define M16C_SSTEP_IRQ 4 /* fffec: Single step */
+# define M16C_WDOG_IRQ 5 /* ffff0: Watchdog timer */
+# define M16C_DBC_IRQ 6 /* ffff4: DBC */
+# define M16C_NMI_IRQ 7 /* ffff8: NMI */
+# define M16C_RESET_IRQ 8 /* ffffc: Reset */
+# define _LAST_FIXED 8
+#else
+# define M16C_WDOG_IRQ 4 /* ffff0: Watchdog timer */
+# define M16C_NMI_IRQ 5 /* ffff8: NMI */
+# define M16C_RESET_IRQ 6 /* ffffc: Reset */
+# define _LAST_FIXED 6
+#endif
+
+/* Variable vector table (fixed at address 0xffd00) */
+
+#ifdef CONFIG_M16C_SWINTS
+# define M16C_BRK_IRQ (_LAST_FIXED+1) /* ffd00: BRK instruction */
+# define M16C_SWINT0_IRQ M16C_BRK_IRQ /* S/W interrupt 0 */
+# define M16C_INT3_IRQ (_LAST_FIXED+2) /* ffd10: INT3 */
+# define M16C_SWINT4_IRQ M16C_INT3_IRQ /* S/W interrupt 4 */
+# define M16C_SWINT5_IRQ (_LAST_FIXED+3) /* ffd14: Reserved / S/W interrupt 5 */
+# define M16C_SWINT6_IRQ (_LAST_FIXED+4) /* ffd18: Reserved / S/W interrupt 6 */
+# define M16C_SWINT7_IRQ (_LAST_FIXED+5) /* ffd1c: Reserved / S/W interrupt 7 */
+# define M16C_INT5_IRQ (_LAST_FIXED+6) /* ffd20: INT5 */
+# define M16C_SWINT8_IRQ M16C_INT5_IRQ /* S/W interrupt 8 */
+# define M16C_INT4_IRQ (_LAST_FIXED+7) /* ffd24: INT4 */
+# define M16C_SWINT9_IRQ M16C_INT4_IRQ /* S/W interrupt 9 */
+# define M16C_UART2BCD_IRQ (_LAST_FIXED+8) /* ffd28: UART2 bus collision detection */
+# define M16C_SWINT10_IRQ M16C_UART2BCD_IRQ /* S/W interrupt 10 */
+# define M16C_DMA0_IRQ (_LAST_FIXED+9) /* ffd2c: DMA0 */
+# define M16C_SWINT11_IRQ M16C_DMA0_IRQ /* S/W interrupt 11 */
+# define M16C_DMA1_IRQ (_LAST_FIXED+10) /* ffd30: DMA1 */
+# define M16C_SWINT12_IRQ M16C_DMA1_IRQ /* S/W interrupt 12 */
+# define M16C_KEYINP_IRQ (_LAST_FIXED+11) /* ffd34: Key input interrupt */
+# define M16C_SWINT13_IRQ M16C_KEYINP_IRQ /* S/W interrupt 13 */
+# define M16C_ADC_IRQ (_LAST_FIXED+12) /* ffd38: A-D */
+# define M16C_SWINT14_IRQ M16C_ADC_IRQ /* S/W interrupt 14 */
+# define M16C_UARTXNAK_IRQ (_LAST_FIXED+13) /* ffd3c UART2 transmit/NACK2 */
+# define M16C_SWINT15_IRQ M16C_UARTNAK_IRQ /* S/W interrupt 15 */
+# define M16C_UARTRACK_IRQ (_LAST_FIXED+14) /* ffd40: UART2 receive/ACK2 */
+# define M16C_SWINT16_IRQ M16C_UARTRACK_IRQ /* S/W interrupt 16 */
+# define M16C_UART0XMT_IRQ (_LAST_FIXED+15) /* ffd44: UART0 transmit */
+# define M16C_SWINT17_IRQ M16C_UART0XMT_IRQ /* S/W interrupt 17 */
+# define M16C_UART0RCV_IRQ (_LAST_FIXED+16) /* ffd48: UART0 receive */
+# define M16C_SWINT18_IRQ M16C_UART0RCV_IRQ /* S/W interrupt 18 */
+# define M16C_UART1XMT_IRQ (_LAST_FIXED+17) /* ffd4c: UART1 transmit */
+# define M16C_SWINT19_IRQ M16C_UART1XMT_IRQ /* S/W interrupt 19 */
+# define M16C_UART1RCV_IRQ (_LAST_FIXED+18) /* ffd50: UART1 receive */
+# define M16C_SWINT20_IRQ M16C_UART1RCV_IRQ /* S/W interrupt 20 */
+# define M16C_TMRA0_IRQ (_LAST_FIXED+19) /* ffd54: Timer A0 */
+# define M16C_SWINT21_IRQ M16C_TMRA0_IRQ /* S/W interrupt 21 */
+# define M16C_TMRA1_IRQ (_LAST_FIXED+20) /* ffd58: Timer A1 */
+# define M16C_SWINT22_IRQ M16C_TMRA1_IRQ /* S/W interrupt 22 */
+# define M16C_TMRA2_IRQ (_LAST_FIXED+21) /* ffd5c: Timer A2 */
+# define M16C_SWINT23_IRQ M16C_TMRA2_IRQ /* S/W interrupt 23 */
+# define M16C_TMRA3_IRQ (_LAST_FIXED+22) /* ffd60: Timer A3 */
+# define M16C_SWINT24_IRQ M16C_TMRA3_IRQ /* S/W interrupt 24 */
+# define M16C_TMRA4_IRQ (_LAST_FIXED+23) /* ffd64: Timer A4 */
+# define M16C_SWINT25_IRQ M16C_TMRA4_IRQ /* S/W interrupt 25 */
+# define M16C_TMRB0_IRQ (_LAST_FIXED+24) /* ffd68: Timer B0 */
+# define M16C_SWINT26_IRQ M16C_TMRB0_IRQ /* S/W interrupt 26 */
+# define M16C_TMRB1_IRQ (_LAST_FIXED+25) /* ffd6c: Timer B1 */
+# define M16C_SWINT27_IRQ M16C_TMRB1_IRQ /* S/W interrupt 27 */
+# define M16C_TMRB2_IRQ (_LAST_FIXED+26) /* ffd70: Timer B2 */
+# define M16C_SWINT28_IRQ M16C_TMRB2_IRQ /* S/W interrupt 28 */
+# define M16C_INT0_IRQ (_LAST_FIXED+27) /* ffd74: INT0 */
+# define M16C_SWINT29_IRQ M16C_INT0_IRQ /* S/W interrupt 29 */
+# define M16C_INT1_IRQ (_LAST_FIXED+28) /* ffd78: INT1 */
+# define M16C_SWINT30_IRQ M16C_INT1_IRQ /* S/W interrupt 30 */
+# define M16C_SWINT31_IRQ (_LAST_FIXED+29) /* ffd7c: Reserved / S/W interrupt 31 */
+# define M16C_SWINT32_IRQ (_LAST_FIXED+30) /* ffd80: S/W interrupt 32 */
+# define M16C_SWINT33_IRQ (_LAST_FIXED+31) /* ffd84: S/W interrupt 33 */
+# define M16C_SWINT34_IRQ (_LAST_FIXED+32) /* ffd88: S/W interrupt 34 */
+# define M16C_SWINT35_IRQ (_LAST_FIXED+33) /* ffd8c: S/W interrupt 35 */
+# define M16C_SWINT36_IRQ (_LAST_FIXED+34) /* ffd90: S/W interrupt 36 */
+# define M16C_SWINT37_IRQ (_LAST_FIXED+35) /* ffd94: S/W interrupt 37 */
+# define M16C_SWINT38_IRQ (_LAST_FIXED+36) /* ffd98: S/W interrupt 38 */
+# define M16C_SWINT39_IRQ (_LAST_FIXED+37) /* ffd9c: S/W interrupt 39 */
+# define M16C_SWINT40_IRQ (_LAST_FIXED+38) /* ffda0: S/W interrupt 40 */
+# define M16C_SWINT41_IRQ (_LAST_FIXED+39) /* ffda4: S/W interrupt 41 */
+# define M16C_SWINT42_IRQ (_LAST_FIXED+40) /* ffda8: S/W interrupt 42 */
+# define M16C_SWINT43_IRQ (_LAST_FIXED+41) /* ffdac: S/W interrupt 43 */
+# define M16C_SWINT44_IRQ (_LAST_FIXED+42) /* ffdb0: S/W interrupt 44 */
+# define M16C_SWINT45_IRQ (_LAST_FIXED+43) /* ffdb4: S/W interrupt 45 */
+# define M16C_SWINT46_IRQ (_LAST_FIXED+44) /* ffdb8: S/W interrupt 46 */
+# define M16C_SWINT47_IRQ (_LAST_FIXED+45) /* ffdbc: S/W interrupt 47 */
+# define M16C_SWINT48_IRQ (_LAST_FIXED+46) /* ffdc0: S/W interrupt 48 */
+# define M16C_SWINT49_IRQ (_LAST_FIXED+47) /* ffdc4: S/W interrupt 49 */
+# define M16C_SWINT50_IRQ (_LAST_FIXED+48) /* ffdc8: S/W interrupt 50 */
+# define M16C_SWINT51_IRQ (_LAST_FIXED+49) /* ffdcc: S/W interrupt 51 */
+# define M16C_SWINT52_IRQ (_LAST_FIXED+50) /* ffdd0: S/W interrupt 52 */
+# define M16C_SWINT53_IRQ (_LAST_FIXED+51) /* ffdd4: S/W interrupt 53 */
+# define M16C_SWINT54_IRQ (_LAST_FIXED+52) /* ffdd8: S/W interrupt 54 */
+# define M16C_SWINT55_IRQ (_LAST_FIXED+53) /* ffddc: S/W interrupt 55 */
+# define M16C_SWINT56_IRQ (_LAST_FIXED+54) /* ffde0: S/W interrupt 56 */
+# define M16C_SWINT57_IRQ (_LAST_FIXED+55) /* ffde4: S/W interrupt 57 */
+# define M16C_SWINT58_IRQ (_LAST_FIXED+56) /* ffde8: S/W interrupt 58 */
+# define M16C_SWINT59_IRQ (_LAST_FIXED+57) /* ffdec: S/W interrupt 59 */
+# define M16C_SWINT60_IRQ (_LAST_FIXED+58) /* ffdf0: S/W interrupt 60 */
+# define M16C_SWINT61_IRQ (_LAST_FIXED+59) /* ffdf4: S/W interrupt 61 */
+# define M16C_SWINT62_IRQ (_LAST_FIXED+60) /* ffdf8: S/W interrupt 62 */
+# define M16C_SWINT63_IRQ (_LAST_FIXED+61) /* ffdfc: S/W interrupt 63 */
+
+# define NR_IRQS (_LAST_FIXED+62) /* Total number of supported IRQs */
+#else
+# define M16C_BRK_IRQ (_LAST_FIXED+1) /* ffd00: BRK instruction */
+# define M16C_INT3_IRQ (_LAST_FIXED+2) /* ffd10: INT3 */
+# define M16C_INT5_IRQ (_LAST_FIXED+3) /* ffd20: INT5 */
+# define M16C_INT4_IRQ (_LAST_FIXED+4) /* ffd24: INT4 */
+# define M16C_UART2BCD_IRQ (_LAST_FIXED+5) /* ffd28: UART2 bus collision detection */
+# define M16C_DMA0_IRQ (_LAST_FIXED+6) /* ffd2c: DMA0 */
+# define M16C_DMA1_IRQ (_LAST_FIXED+7) /* ffd30: DMA1 */
+# define M16C_KEYINP_IRQ (_LAST_FIXED+8) /* ffd34: Key input interrupt */
+# define M16C_ADC_IRQ (_LAST_FIXED+9) /* ffd38: A-D */
+# define M16C_UARTXNAK_IRQ (_LAST_FIXED+10) /* ffd3c UART2 transmit/NACK2 */
+# define M16C_UARTRACK_IRQ (_LAST_FIXED+11) /* ffd40: UART2 receive/ACK2 */
+# define M16C_UART0XMT_IRQ (_LAST_FIXED+12) /* ffd44: UART0 transmit */
+# define M16C_UART0RCV_IRQ (_LAST_FIXED+13) /* ffd48: UART0 receive */
+# define M16C_UART1XMT_IRQ (_LAST_FIXED+14) /* ffd4c: UART1 transmit */
+# define M16C_UART1RCV_IRQ (_LAST_FIXED+15) /* ffd50: UART1 receive */
+# define M16C_TMRA0_IRQ (_LAST_FIXED+16) /* ffd54: Timer A0 */
+# define M16C_TMRA1_IRQ (_LAST_FIXED+17) /* ffd58: Timer A1 */
+# define M16C_TMRA2_IRQ (_LAST_FIXED+18) /* ffd5c: Timer A2 */
+# define M16C_TMRA3_IRQ (_LAST_FIXED+19) /* ffd60: Timer A3 */
+# define M16C_TMRA4_IRQ (_LAST_FIXED+20) /* ffd64: Timer A4 */
+# define M16C_TMRB0_IRQ (_LAST_FIXED+21) /* ffd68: Timer B0 */
+# define M16C_TMRB1_IRQ (_LAST_FIXED+22) /* ffd6c: Timer B1 */
+# define M16C_TMRB2_IRQ (_LAST_FIXED+23) /* ffd70: Timer B2 */
+# define M16C_INT0_IRQ (_LAST_FIXED+24) /* ffd74: INT0 */
+# define M16C_INT1_IRQ (_LAST_FIXED+25) /* ffd78: INT1 */
+
+# define NR_IRQS (_LAST_FIXED+26 /* Total number of supported IRQs */
+#endif
-#define NR_IRQS 1 /* Total number of supported IRQs */
-#define M16C_SYSTIMER_IRQ 1
+#define M16C_SYSTIMER_IRQ M16C_TMRA0_IRQ
/* IRQ Stack Frame Format. The SH-1 has a push down stack. The PC
* and SR are pushed by hardware at the time an IRQ is taken.
@@ -62,8 +202,8 @@
/* To be provided */
-#define XCPTCONTEXT_REGS (1)
-#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
+#define XCPTCONTEXT_REGS (1)
+#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
/************************************************************************************
* Public Types
diff --git a/configs/skp16c26/include/board.h b/configs/skp16c26/include/board.h
index de04e1e194e2a536f9e0a8ad3f86dbe54f375ad3..5f694f5deef9d752190752f05713c43c3f709ad2 100644
--- a/configs/skp16c26/include/board.h
+++ b/configs/skp16c26/include/board.h
@@ -44,11 +44,54 @@
#ifndef __ASSEMBLY__
# include <sys/types.h>
#endif
+#include "sfr262.h" /* M16C/26 special function register definitions */
+#include "skp_lcd.h" /* SKP LCD function definitions */
/************************************************************************************
* Definitions
************************************************************************************/
+/* Xin Freq */
+
+#define XIN_FREQ 20e6 /* 20MHz */
+
+/* Switches */
+
+#define S1 p8_3
+#define S2 p8_2
+#define S3 p8_1
+#define S1_DDR pd8_3
+#define S2_DDR pd8_2
+#define S3_DDR pd8_1
+
+/* LEDs */
+#define RED_LED p8_0
+#define YLW_LED p7_4
+#define GRN_LED p7_2
+
+#define RED_DDR pd8_0 // LED port direction register
+#define YLW_DDR pd7_4
+#define GRN_DDR pd7_2
+
+/********************************************************************************/
+/* Macro Definitions */
+/********************************************************************************/
+
+#define LED_ON 0
+#define LED_OFF 1
+
+#define ENABLE_IRQ {_asm(" FSET I");}
+#define DISABLE_IRQ {_asm(" FCLR I");}
+
+/* Use these macros for switch inputs */
+
+#define ENABLE_SWITCHES {S1_DDR = 0; S2_DDR = 0; S3_DDR = 0;}
+
+/* Use these macros to control the LEDs */
+
+#define LED(led, state) ((led) = !state)
+#define ENABLE_LEDS {RED_LED = LED_OFF; YLW_LED = LED_OFF; GRN_LED = LED_OFF; RED_DDR = 1; YLW_DDR = 1; GRN_DDR = 1; }
+
/************************************************************************************
* Inline Functions
************************************************************************************/
diff --git a/configs/skp16c26/ostest/ld.script b/configs/skp16c26/ostest/ld.script
index 63cfeccdbec1f480b11e3dce69394f38738ba5e3..6474929170115d6a0fafb72d34ad1968889316c7 100644
--- a/configs/skp16c26/ostest/ld.script
+++ b/configs/skp16c26/ostest/ld.script
@@ -37,9 +37,12 @@ OUTPUT_ARCH(m32c)
ENTRY(_stext)
SECTIONS
{
- /* The OS entry point is here */
+ /* Flash memory begins at address 0xf0000 for the M20262F8 part and
+ * ends at address 0xfffff (all parts). The program entry point is
+ * the first address in flash
+ */
- . = 0x00008000;
+ . = 0xf0000;
.text : {
_stext = ABSOLUTE(.);
*(.text)
@@ -52,8 +55,42 @@ SECTIONS
_etext = ABSOLUTE(.);
}
- _eronly = ABSOLUTE(.); /* See below */
- . = ALIGN(4096);
+ _eronly = ABSOLUTE(.); /* End of read-only values */
+ /* .data will be relocated from */
+ /* this address */
+
+ /* The "variable" vector table will be fixed at the following address */
+
+ . = 0xffd00
+ .varvect : {
+ _svarvect = ABSOLUTE(.);
+ *(.varvect)
+ _evarvect = ABSOLUTE(.);
+ }
+
+ /* Followed by the special page/fixed vector table. */
+
+ . = 0xffe00
+ .specpg : {
+ _sspecpg = ABSOLUTE(.);
+ *(.specpg)
+ _especpg = ABSOLUTE(.);
+ }
+
+ . = 0xfffdc
+ .fixvect : {
+ _sfixvect = ABSOLUTE(.);
+ *(.fixvect)
+ _efixvect = ABSOLUTE(.);
+ }
+
+ /* Internal RAM begins at address 0x00400 (all parts) and ends at
+ * address 0x00bff (M20262F6 and M20262F8 parts). With the RAM
+ * region, used is .data followed by .bss. The remainder of RAM
+ * carved up by the start-up code into stacks and heaps.
+ */
+
+ . = 0x00400;
.data : {
_sdata = ABSOLUTE(.);