diff --git a/ChangeLog b/ChangeLog
index 055d540aeafde0c8c9216b0883fea13828185dc2..ee37fbdd33beda12e20fa8e5425e6d81a9394096 100755
--- a/ChangeLog
+++ b/ChangeLog
@@ -17445,7 +17445,7 @@
* The lcdrw example has been removed because it violates the portable OS
interface (2017-10-14).
* All configurations that use NXIMAGE or NXHELLO must select
- NX_MULTIUSER. All configuratinos that use examples/nxterm must enable
+ NX_MULTIUSER. All configurations that use examples/nxterm must enable
CONFIG_LIB_BOARDCTL (2017-10-14).
* configs/stm32f103-minimum: Add support for LM75 in the
stm32f103-minimum board. From Alan Carvalho de Assis (2017-10-14).
diff --git a/Documentation/NXGraphicsSubsystem.html b/Documentation/NXGraphicsSubsystem.html
index 3a58de35fc3337ede6e38300dd09cc80bfd69930..efb8cbf1fe4a1c9690e968a47fdcec4f2ed645e5 100644
--- a/Documentation/NXGraphicsSubsystem.html
+++ b/Documentation/NXGraphicsSubsystem.html
@@ -12,7 +12,7 @@
NX Graphics Subsystem
- Last Updated: October 17, 2017
+ Last Updated: January 21, 2018
@@ -542,7 +542,7 @@ void nxgl_yuv2rgb(uint8_t y, uint8_t u, uint8_t v, uint8_t *r, uint8_t *g, uint8
Description:
- Convert 8-bit RGB triplet to 8-bit YUV triplet.
+ Convert 8-bit YUV triplet to 8-bit RGB triplet.
diff --git a/Documentation/NuttShell.html b/Documentation/NuttShell.html
index c23950484cd83895c4f1a664914846070a2625fd..6095357a5cea6da41103aa1b234a90a8decc09ed 100644
--- a/Documentation/NuttShell.html
+++ b/Documentation/NuttShell.html
@@ -8,7 +8,7 @@
NuttShell (NSH)
- Last Updated: January 10, 2018
+ Last Updated: January 12, 2018
|
@@ -251,259 +251,265 @@
|
- 2.28 Send a signal to a task (kill)
+ 2.28 Show Interrupt Status (irqinfo)
|
|
- 2.29 Setup/teardown the Loop Device (losetup)
+ 2.29 Send a signal to a task (kill)
|
|
- 2.30 List to a File or Directory (ln)
+ 2.30 Setup/teardown the Loop Device (losetup)
|
|
- 2.31 List Directory Contents (ls)
+ 2.31 List to a File or Directory (ln)
|
|
- 2.32 Show information about installed OS modules (lsmod)
+ 2.32 List Directory Contents (ls)
|
|
- 2.33 Calculate MD5 (md5)
+ 2.33 Show information about installed OS modules (lsmod)
|
|
- 2.34 Access Memory (mb, mh, and mw)
+ 2.34 Calculate MD5 (md5)
|
|
- 2.35 Show Current Tasks and Threads (ps)
+ 2.35 Access Memory (mb, mh, and mw)
|
|
- 2.36 Create a Directory (mkdir)
+ 2.36 Show Current Tasks and Threads (ps)
|
|
- 2.37 Create a FAT File System (mkfatfs)
+ 2.37 Create a Directory (mkdir)
|
|
- 2.38 Create a FIFO (mkfifo)
+ 2.38 Create a FAT File System (mkfatfs)
|
|
- 2.39 Create a RAMDISK (mkrd)
+ 2.39 Create a FIFO (mkfifo)
|
|
- 2.40 Mount a File System (mount)
+ 2.40 Create a RAMDISK (mkrd)
|
|
- 2.41 Rename a File (mv)
+ 2.41 Mount a File System (mount)
|
|
- 2.42 Mount an NFS File System (nfsmount)
+ 2.42 Rename a File (mv)
|
|
- 2.43 Lookup a network address (nslookup)
+ 2.43 Mount an NFS File System (nfsmount)
|
|
- 2.44 Change a User's Password (passwd)
+ 2.44 Lookup a network address (nslookup)
|
|
- 2.45 Shut the system down (poweroff)
+ 2.45 Change a User's Password (passwd)
|
|
- 2.46 Send File Via TFTP (put)
+ 2.46 Shut the system down (poweroff)
|
|
- 2.47 Show Current Working Directory (pwd)
+ 2.47 Send File Via TFTP (put)
|
|
- 2.48 Show target of a link (readlink)
+ 2.48 Show Current Working Directory (pwd)
|
|
- 2.49 Reset and reboot the system (reboot)
+ 2.49 Show target of a link (readlink)
|
|
- 2.50 Remove a File (rm)
+ 2.50 Reset and reboot the system (reboot)
|
|
- 2.51 Remove a Directory (rmdir)
+ 2.51 Remove a File (rm)
|
|
- 2.52 Remove on OS Module (rmmod)
+ 2.52 Remove a Directory (rmdir)
|
|
- 2.53 Show routing table (route)
+ 2.53 Remove on OS Module (rmmod)
|
|
- 2.54 Set an Environment Variable (set)
+ 2.54 Show routing table (route)
|
|
- 2.55 Execute an NSH Script (sh)
+ 2.55 Set an Environment Variable (set)
|
|
- 2.56 Shut the system down (shutdown)
+ 2.56 Execute an NSH Script (sh)
|
|
- 2.57 Wait for Seconds (sleep)
+ 2.57 Shut the system down (shutdown)
|
|
- 2.58 Start the Telnet Daemon (telnetd)
+ 2.58 Wait for Seconds (sleep)
|
|
- 2.59 Time execution of another command (time)
+ 2.59 Start the Telnet Daemon (telnetd)
|
|
- 2.60 Set the Size of a File (truncate)
+ 2.60 Time execution of another command (time)
|
|
- 2.61 Unmount a File System (umount)
+ 2.61 Set the Size of a File (truncate)
|
|
- 2.62 Print system information (uname)
+ 2.62 Unmount a File System (umount)
|
|
- 2.63 Unset an Environment Variable (unset)
+ 2.63 Print system information (uname)
|
|
- 2.64 URL Decode (urldecode)
+ 2.64 Unset an Environment Variable (unset)
|
|
- 2.65 URL Encode (urlencode)
+ 2.65 URL Decode (urldecode)
|
|
- 2.66 Add a New User (useradd)
+ 2.66 URL Encode (urlencode)
|
|
- 2.67 Delete a user (userdel)
+ 2.67 Add a New User (useradd)
|
|
- 2.68 Wait for Microseconds (usleep)
+ 2.68 Delete a user (userdel)
|
|
- 2.69 Get File Via HTTP (wget)
+ 2.69 Wait for Microseconds (usleep)
|
|
- 2.70 Hexadecimal Dump of Memory (xd)
+ 2.70 Get File Via HTTP (wget)
+ |
+
+
+
|
+
+ 2.71 Hexadecimal Dump of Memory (xd)
|
@@ -1941,7 +1947,34 @@ mydriver 20404659 20404625 0 20404580 552 204047a8 0
+
+Command Syntax:
+
+irqinfo
+
+
+ Synopsis.
+ Show the current count of interrupts taken on all attached interrupts.
+
+
+ Example:.
+
+
+nsh> irqinfo
+IRQ HANDLER ARGUMENT COUNT RATE
+ 3 00001b3d 00000000 156 19.122
+ 15 0000800d 00000000 817 100.000
+ 30 00000fd5 20000018 20 2.490
+
+
+
@@ -1983,7 +2016,7 @@ nsh>
@@ -2036,7 +2069,7 @@ losetup d <dev-path>
@@ -2061,7 +2094,7 @@ ln [-s] <target> <link>
@@ -2099,7 +2132,7 @@ ls [-lRs] <dir-path>
@@ -2132,7 +2165,7 @@ mydriver 20404659 20404625 0 20404580 552 204047a8 0
@@ -2149,7 +2182,7 @@ md5 [-f] <string or filepath>
@@ -2202,7 +2235,7 @@ nsh>
@@ -2236,7 +2269,7 @@ nsh> mount -t procfs /proc
@@ -2271,7 +2304,7 @@ nsh>
@@ -2296,7 +2329,7 @@ mkfatfs [-F <fatsize>] <block-driver>
@@ -2334,7 +2367,7 @@ nsh>
@@ -2385,7 +2418,7 @@ nsh>
@@ -2464,7 +2497,7 @@ nsh> mount
@@ -2482,7 +2515,7 @@ mv <old-path> <new-path>
@@ -2501,7 +2534,7 @@ nfsmount <server-address> <mount-point> <remote-path>
@@ -2518,7 +2551,7 @@ nslookup <host-name>
@@ -2535,7 +2568,7 @@ passwd <username> <password>
@@ -2557,7 +2590,7 @@ poweroff
@@ -2592,7 +2625,7 @@ put [-b|-n] [-f <remote-path>] -h <ip-address> <local-path>
@@ -2622,7 +2655,7 @@ nsh>
@@ -2639,7 +2672,7 @@ readlink <link>
@@ -2660,7 +2693,7 @@ reboot
@@ -2694,7 +2727,7 @@ nsh>
@@ -2729,7 +2762,7 @@ nsh>
@@ -2757,7 +2790,7 @@ nsh>
@@ -2777,7 +2810,7 @@ route ipv4|ipv6
@@ -2846,7 +2879,7 @@ nsh>
@@ -2864,7 +2897,7 @@ sh <script-path>
@@ -2885,7 +2918,7 @@ shutdown [--reboot]
@@ -2902,7 +2935,7 @@ sleep <sec>
@@ -2928,7 +2961,7 @@ telnetd
@@ -2986,7 +3019,7 @@ nsh>
@@ -3014,7 +3047,7 @@ truncate -s <length> <file-path>
@@ -3044,7 +3077,7 @@ nsh>
@@ -3111,7 +3144,7 @@ uname [-a | -imnoprsv]
@@ -3137,7 +3170,7 @@ nsh>
@@ -3154,7 +3187,7 @@ urldecode [-f] <string or filepath>
@@ -3171,7 +3204,7 @@ urlencode [-f] <string or filepath>
@@ -3188,7 +3221,7 @@ useradd <username> <password>
@@ -3205,7 +3238,7 @@ userdel <username>
@@ -3222,7 +3255,7 @@ usleep <usec>
@@ -3249,7 +3282,7 @@ wget [-o <local-path>] <url>
@@ -3506,6 +3539,11 @@ nsh>
CONFIG_MODULE |
CONFIG_NSH_DISABLE_MODCMDS |
+
+ irqinfo |
+ !CONFIG_DISABLE_MOUNTPOINT && CONFIG_FS_PROCFS && CONFIG_SCHED_IRQMONITOR |
+
|
+
kill |
!CONFIG_DISABLE_SIGNALS |
@@ -5486,10 +5524,10 @@ xxd -i romfs_img >nsh_romfsimg.h
CONFIG_NSH_ROMFSMOUNTPT
CONFIG_NSH_ROMFSSECTSIZE
CONFIG_NSH_STRERROR
+ CONFIG_NSH_TELNET
|
- - NSH library (
nshlib)
- NSH library (
nshlib)
nsh_consolemain()nsh_initialize()
NuttX RTOS Porting Guide
- Last Updated: October 12, 2017
+ Last Updated: February 14, 2018
|
@@ -1563,6 +1563,33 @@ The specific environmental definitions are unique for each board but should incl
Sometimes the board name is too long so stm32_ would be okay too.
These should be prototyped in configs/<board>/src/<board>.h and should not be used outside of that directory since board-specific definitions have no meaning outside of the board directory.
+
+
+ Scope of Inclusions.
+ Header files are made accessible to internal OS logic and to applications through symbolic links and through include paths that are provided to the C/C++ compiler.
+ Through these include paths, the NuttX build system also enforces modularity in the design.
+ For example, one important design principle is architectural layering.
+ In this case I am referring to the OS as layered into application interface, common internal OS logic, and lower level platform-specific layers.
+ The platform-specific layers all reside in the either arch/ sub-directories on the config/ subdirectories: The former sub-directories are reserved for microcontroller-specific logic and the latter for board-specific logic.
+
+
+ In the strict, layered NuttX architecture, the upper level OS services are always available to platform-specific logic. However, the opposite is not true: Common OS logic must never have any dependency on the lower level platform-specific code. The OS logic must be totally agnostic about its hardware environment. Similarly, microcontroller-specific logic was be completely ignorant of board-specific logic.
+
+
+ This strict layering is enforced in the NuttX build system by controlling the compiler include paths: Higher level code can never include header files from either; of the platform-specific source directories; microcontroller-specific code can never include header files from the board-specific source directories. The board-specific directories are, then, at the bottom of the layered hierarchy.
+
+
+ An exception to these inclusion restrictions is the platform-specific include/. These are made available to higher level OS logic. The microcontroller-specific include directory will be linked at include/arch/chip and, hence, can be included like #include <arch/chip/chip.h.
+ Similarly, the board-specific include directory will be linked at include/arch/board and, hence, can be included like #include <arch/board/board.h.
+
+
+ Keeping in the spirit of the layered architecture, these publicly visible header files must not export platform-specific definitions; Only platform-specific realizations of standardized declarations should be visible.
+ Those standardized declarations should appear in common header files such as those provided by include/nuttx/arch.h and include/nuttx/board.h.
+ Similarly, these publicly visible header file must not include files that reside in the inaccessible platform-specific source directories.
+ For example, the board-specific configs/<board>/include/board.h header file must never include microcontroller-specific header files that reside in arch/<arch>/src/<mcu>.
+ That practice will cause inclusion failures when the publicly visible file is included in common logic outside of the platform-specific source directories.
+
+
@@ -2605,7 +2632,7 @@ pointer to a watchdog structure.
Returned Value:
-- OK or ERROR
+
- Zero (
OK) is returned on success; a negated errno value is return to indicate the nature of any failure.
@@ -2662,7 +2689,7 @@ wd_start() on a given watchdog ID has any effect.
Returned Value:
-- OK or ERROR
+
- Zero (
OK) is returned on success; a negated errno value is return to indicate the nature of any failure.
@@ -3852,7 +3879,7 @@ void sched_timer_expiration(void);
NOTE: The other interfaces described in this document are internal OS interface.
boardctl() is an application interface to the OS.
- There is not point, in fact, of using boardctl() within the OS;
+ There is no point, in fact, of using boardctl() within the OS;
the board interfaces prototyped in include/nuttx/board.h may be called directly from within the OS.
diff --git a/README.txt b/README.txt
index adfead108410b4af248e67e7279135c3dfcb0157..032554efcac265a6b17df6c4f978706894f9686f 100644
--- a/README.txt
+++ b/README.txt
@@ -76,10 +76,10 @@ ENVIRONMENTS
is that it is closer to a native Windows environment and uses only a
minimal of add-on POSIX-land tools.
- - NuttX can also be installed and built on a native Windows system, but
- with some potential tool-related issues (see the discussion "Native
- Windows Build" under "Building NuttX" below). GNUWin32 is used to
- provide compatible native windows tools.
+ NuttX can also be installed and built on a native Windows system, but with
+ some potential tool-related issues (see the discussion "Native Windows
+ Build" under "Building NuttX" below). GNUWin32 is used to provide
+ compatible native windows tools.
Installing Cygwin
-----------------
@@ -635,7 +635,7 @@ Instantiating "Canned" Configurations
refreshing the configuration as described below.
NOTE: NuttX uses only compressed defconfig files. For the NuttX
- defconfig files, this refrshing step is *NOT* optional; it is also
+ defconfig files, this refreshing step is *NOT* optional; it is also
necessary to uncompress and regenerate the full making file. This is
discussed further below.
@@ -1040,6 +1040,14 @@ NuttX Configuration Tool under DOS
that can be used:
http://uvc.de/posts/linux-kernel-configuration-tool-mconf-under-windows.html
+ The configuration steps most recent versions of NuttX require the
+ kconfig-tweak tool that is not not available in the the above. However,
+ there has been an update to this Kconfig Windows tools that does include
+ kconfig-tweak: http://reclonelabs.com/more-kconfig-awesomeness-for-windows/
+
+ Source code is available here: https://github.com/reclone/kconfig-frontends-win32
+ and https://github.com/reclone/kconfig-frontends-win32/releases
+
It is also possible to use the version of kconfig-frontends built
under Cygwin outside of the Cygwin "sandbox" in a native Windows
environment:
@@ -1260,7 +1268,7 @@ Build Targets and Options
Perform the distclean operation only in the user application directory.
The apps/.config file is preserved so that this is not a "full" distclean
- but more of a configuration "reset."
+ but more of a configuration "reset" for the application directory.
export
@@ -1318,7 +1326,6 @@ Native Windows Build
The windows native build logic initiated if CONFIG_WINDOWS_NATIVE=y is
defined in the NuttX configuration file:
-
This build:
- Uses all Windows style paths
@@ -1415,6 +1422,22 @@ Installing GNUWin32
CYGWIN BUILD PROBLEMS
^^^^^^^^^^^^^^^^^^^^^
+Performance
+-----------
+
+ Build performance under Cygwin is really not so bad, certainly not as good
+ as a Linux build. However, often you will find that the performance is
+ not just bad but terrible. If you are seeing awful performance.. like two
+ or three compilations per second.. the culprit is usually your Windows
+ Anti-Virus protection interfering with the build tool program execution.
+
+ I use Cygwin quite often and I use Windows Defender. In order to get good
+ build performance, I routinely keep the Windows Defender "Virus & Threat
+ Protections Settings" screen up: I disable "Real-Time Protection" just
+ before entering 'make' then turn "Real-Time Protection" back on when the
+ build completes. With this additional nuisance step, I find that build
+ performance under Cygwin is completely acceptable.
+
Strange Path Problems
---------------------
@@ -1468,6 +1491,7 @@ Window Native Toolchain Issues
if you are using a native Windows toolchain. That bring us to #3:
General Pre-built Toolchain Issues
+----------------------------------
To continue with the list of "Window Native Toolchain Issues" we can add
the following. These, however, are really just issues that you will have
@@ -1521,6 +1545,7 @@ General Pre-built Toolchain Issues
binutils and possibly different ABIs.
Building Original Linux Boards in Cygwin
+----------------------------------------
Some default board configurations are set to build under Linux and others
to build under Windows with Cygwin. Various default toolchains may also
@@ -1539,6 +1564,7 @@ Building Original Linux Boards in Cygwin
("Run As" option, right button) you find errors like "Permission denied".
Recovering from Bad Configurations
+----------------------------------
Many people make the mistake of configuring NuttX with the "canned"
configuration and then just typing 'make' with disastrous consequences;
diff --git a/ReleaseNotes b/ReleaseNotes
index d3302c654ece99e39973764ebd62d9a0a5c59cbd..aaa960e996106203aaf0a8246ab1285d7d802c65 100644
--- a/ReleaseNotes
+++ b/ReleaseNotes
@@ -16669,7 +16669,7 @@ detailed bugfix information):
* Examples/Tests: apps/examples:
- All configurations that use NXIMAGE or NXHELLO must select
- NX_MULTIUSER. All configuratinos that use examples/nxterm must
+ NX_MULTIUSER. All configurations that use examples/nxterm must
enable CONFIG_LIB_BOARDCTL.
- All configurations that use NXLINES must select NX_MULTIUSER. All
configurations that use the NX server need to have larger POSIX
diff --git a/TODO b/TODO
index 3d92fd7ee2cc84745d03d4b523cd06576d4728fd..7801c545aaa30d5ef4ed2b83fee7c9cdd3be65c4 100644
--- a/TODO
+++ b/TODO
@@ -1,15 +1,15 @@
-NuttX TODO List (Last updated January 3, 2018)
+NuttX TODO List (Last updated January 23, 2018)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This file summarizes known NuttX bugs, limitations, inconsistencies with
standards, things that could be improved, and ideas for enhancements. This
-TODO list does not include issues associated with individual boar ports. See
+TODO list does not include issues associated with individual board ports. See
also the individual README.txt files in the configs/ sub-directories for
issues related to each board port.
nuttx/:
- (12) Task/Scheduler (sched/)
+ (14) Task/Scheduler (sched/)
(1) SMP
(1) Memory Management (mm/)
(0) Power Management (drivers/pm)
@@ -19,7 +19,7 @@ nuttx/:
(8) Kernel/Protected Build
(3) C++ Support
(6) Binary loaders (binfmt/)
- (17) Network (net/, drivers/net)
+ (16) Network (net/, drivers/net)
(4) USB (drivers/usbdev, drivers/usbhost)
(0) Other drivers (drivers/)
(12) Libraries (libc/, libm/)
@@ -47,7 +47,7 @@ o Task/Scheduler (sched/)
Status: Closed. No, this behavior will not be implemented.
Priority: Medium, required for good emulation of process/pthread model.
The current behavior allows for the main thread of a task to
- exit() and any child pthreads will perist. That does raise
+ exit() and any child pthreads will persist. That does raise
some issues: The main thread is treated much like just-another-
pthread but must follow the semantics of a task or a process.
That results in some inconsistencies (for example, with robust
@@ -124,7 +124,7 @@ o Task/Scheduler (sched/)
The fix for all of these issues it to have the callbacks
run on the caller's thread as is currently done with
signal handlers. Signals are delivered differently in
- PROTECTED and KERNEL modes: The deliver is involes a
+ PROTECTED and KERNEL modes: The delivery involves a
signal handling trampoline function in the user address
space and two signal handlers: One to call the signal
handler trampoline in user mode (SYS_signal_handler) and
@@ -170,9 +170,14 @@ o Task/Scheduler (sched/)
to make this change: Just move the pterrno field from
struct tcb_s to struct task_group_s. However, I am still not
sure if this should be done or not.
- Status: Closed. The existing solution is better (although its
- incompatibilities could show up in porting some code).
- Priority: Low
+ NOTE: glibc behaves this way unless __thread is defined then,
+ in that case, it behaves like NuttX (using TLS to save the
+ thread local errno).
+ Status: Closed. The existing solution is better and compatible with
+ thread-aware GLIBC (although its incompatibilities could show
+ up in porting some code). I will retain this issue for
+ referencei only.
+ Priority: N/A
Title: SCALABILITY
Description: Task control information is retained in simple lists. This
@@ -198,7 +203,7 @@ o Task/Scheduler (sched/)
Description: The internal NuttX logic uses the same interfaces as does
the application. That sometime produces a problem because
there is "overloaded" functionality in those user interfaces
- that are not desireable.
+ that are not desirable.
For example, having cancellation points hidden inside of the
OS can cause non-cancellation point interfaces to behave
@@ -255,11 +260,14 @@ o Task/Scheduler (sched/)
message queue used in the OS. I am keeping this issue
open because (1) there are some known remaining calls that
that will modify the errno (such as dup(), dup2(),
- sched_getparam(), sched_reprioritize(). sched_setaffinity(),
- task_activate(), mq_open(), mq_close(), and others) and (2)
- there may still be calls that create cancellation points.
- Need to check things like open(), close(), read(), write(),
- and possibly others.
+ task_activate(), kthread_create(), exec(), mq_open(),
+ mq_close(), and others) and (2) there may still be calls that
+ create cancellation points. Need to check things like open(),
+ close(), read(), write(), and possibly others.
+ 2018-01-30: This change has been completed for the case of
+ scheduler functions used within the OS: sched_getparam(),
+ sched_setparam(), sched_getscheduler(), sched_setschedule(),
+ and sched_setaffinity(),
Status: Open
Priority: Low. Things are working OK the way they are. But the design
@@ -327,6 +335,59 @@ o Task/Scheduler (sched/)
Status: Open
Priority: Low, only needed for more complete debug.
+ Title: PRIORITY INHERITANCE WITH SPORADIC SCHEDULER
+ Description: The sporadic scheduler manages CPU utilization by a task by
+ alternating between a high and a low priority. In either
+ state, it may have its priority boosted. However, under
+ some circumstances, it is impossible in the current design to
+ switch to the correct priority if a semaphore held by the
+ sporadic thread is participating in priority inheritance:
+
+ There is an issue when switching from the high to the low
+ priority state. If the priority was NOT boosted above the
+ higher priority, it still may still need to boosted with
+ respect to the lower priority. If the highest priority
+ thread waiting on a semaphore held by the sporadic thread is
+ higher in priority than the low priority but less than the
+ higher priority, then new thread priority should be set to
+ that middle priority, not to the lower priority.
+
+ In order to do this we would need to know the highest
+ priority from among all tasks waiting for the all semaphores
+ held by the sporadic task. That information could be
+ retained by the priority inheritance logic for use by the
+ sporadic scheduler. The boost priority could be retained in
+ a new field of the TCB (say, pend_priority). That
+ pend_priority could then be used when switching from the
+ higher to the lower priority.
+ Status: Open
+ Priority: Low. Does anyone actually use the sporadic scheduler?
+
+ Title: SIMPLIFY SPORADIC SCHEDULER DESIGN
+ Description: I have been planning to re-implement sporadic scheduling for
+ some time. I believe that the current implementation is
+ unnecessarily complex. There is no clear statement for the
+ requirements of sporadic scheduling that I could find, so I
+ based the design on some behaviors of another OS that I saw
+ published (QNX as I recall).
+
+ But I think that the bottom line requirement for sporadic
+ scheduling is that is it should make a best attempt to
+ control a fixed percentage of CPU bandwidth for a task in
+ during an interval only by modifying it is priority between
+ a low and a high priority. The current design involves
+ several timers: A "budget" timer plus a variable number of
+ "replenishment" timers and a lot of nonsense to duplicate QNX
+ behavior that I think I not necessary.
+
+ It think that the sporadic scheduler could be re-implemented
+ with only the single "budget" timer. Instead of starting a
+ new "replenishment" timer when the task is resumed, that
+ single timer could just be extended.
+ Status: Open
+ Priority: Low. This is an enhancement. And does anyone actually use
+ the sporadic scheduler?
+
o SMP
^^^
@@ -572,7 +633,7 @@ o pthreads (sched/pthreads)
group structure. I am, however, hesitant to make this change:
In the FLAT build model, there is nothing that prevents people
from accessing the inter-thread controls from threads in
- differnt task groups. Making this change, while correct,
+ different task groups. Making this change, while correct,
might introduce subtle bugs in code by people who are not
using NuttX correctly.
Status: Open
@@ -745,7 +806,7 @@ o Kernel/Protected Build
Title: USER MODE TASKS CAN MODIFY PRIVILEGED TASKS
Description: Certain interfaces, such as sched_setparam(),
sched_setscheduler(), etc. can be used by user mode tasks to
- modify the behavior of priviledged kernel threads.
+ modify the behavior of privileged kernel threads.
For a truly secure system. Privileges need to be checked in
every interface that permits one thread to modify the
properties of another thread.
@@ -1022,23 +1083,19 @@ o Network (net/, drivers/net)
Title: POLL/SELECT ON TCP/UDP SOCKETS NEEDS READ-AHEAD
Description: poll()/select() only works for availability of buffered TCP/UDP
read data (when read-ahead is enabled). The way writing is
- handled in the network layer, all sockets must wait when send and
- cannot be notified when they can send without waiting.
+ handled in the network layer, either (1) If CONFIG_UDP/TCP_WRITE_BUFFERS=y
+ then we never have to wait to send; otherwise, we always have
+ to wait to send. So it is impossible to notify the caller
+ when it can send without waiting.
+
+ An exception "never having to wait" is the case where we are
+ out of memory for use in write buffering. In that case, the
+ blocking send()/sendto() would have to wait for the memory
+ to become available.
Status: Open, probably will not be fixed.
Priority: Medium... this does effect porting of applications that expect
different behavior from poll()/select()
- Title: SOCKETS DO NOT ALWAYS SUPPORT O_NONBLOCK
- Description: sockets do not support all modes for O_NONBLOCK. Sockets
- support nonblocking operations only (1) for TCP/IP non-
- blocking read operations when read-ahead buffering is
- enabled, (2) TCP/IP accept() operations when TCP/IP
- connection backlog is enabled, (2) UDP/IP read() operations
- when UDP read-ahead is enabled, and (3) non-blocking
- operations on Unix domain sockets.
- Status: Open
- Priority: Low.
-
Title: INTERFACES TO LEAVE/JOIN IGMP MULTICAST GROUP
Description: The interfaces used to leave/join IGMP multicast groups is non-standard.
RFC3678 (IGMPv3) suggests ioctl() commands to do this (SIOCSIPMSFILTER) but
@@ -1071,8 +1128,8 @@ o Network (net/, drivers/net)
however. Others support the address filtering interfaces but
have never been verifed:
- C5471, LM3S, ez80, DM0x90 NIC, PIC: Do not support address
- filtering.
+ C5471, LM3S, ez80, DM0x90 NIC, PIC, LPC54: Do not support
+ address filtering.
Kinetis, LPC17xx, LPC43xx: Untested address filter support
Status: Open
@@ -1282,7 +1339,7 @@ o Network (net/, drivers/net)
however, because its priority is low and so it is blocked
from execution.
- In the mean time, the remote host sends a
- packet which is presumeably caught in the read-ahead buffer.
+ packet which is presumably caught in the read-ahead buffer.
- Then the remote host closes the socket. Nothing happens on
the target side because net_start_monitor() has not yet been
called.
@@ -1838,7 +1895,7 @@ o File system / Generic drivers (fs/, drivers/)
(using pctl() instead sysctl()). My objective was to be able
to control the number of available file descriptors on a task-
by-task basis. The complexity due to the partitioning of
- desciptor space in a range for file descriptors and a range
+ descriptor space in a range for file descriptors and a range
for socket descriptors made this feature nearly impossible to
implement.
Status: Open
@@ -1920,8 +1977,8 @@ o File system / Generic drivers (fs/, drivers/)
4) When comparing the checksum in the long file name
entry with the checksum of the short file name, the
checksum fails and the entire directory sequence is
- ignored by readder() logic. This the file does not
- appear in the 'ls'.
+ ignored by readdir() logic. This is why the file does
+ not appear in the 'ls'.
o Graphics Subsystem (graphics/)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -2014,7 +2071,7 @@ o Graphics Subsystem (graphics/)
Title: LOW-RES FRAMEBUFFER RENDERERING
Description: There are obvious issues in the low-res, < 8 BPP, implemenation of
- the framebuffer rendereing logic of graphics/nxglib/fb. I see two
+ the framebuffer rendering logic of graphics/nxglib/fb. I see two
obvious problems in reviewing nxglib_copyrectangle():
1. The masking logic might work 1 BPP, but is insufficient for other
@@ -2026,7 +2083,7 @@ o Graphics Subsystem (graphics/)
derives from nxglib_copyrectangle() and all of those issues have been
resolved in that file.
- Other frambuffer rendering functions probably have similary issues.
+ Other frambuffer rendering functions probably have similar issues.
Status: Open
Priority: Low. It is not surprising that there would be bugs in this logic:
I have never encountered a hardware framebuffer with sub-byte pixel
@@ -2279,11 +2336,11 @@ o Modbus (apps/modbus)
Title: MODBUS NOT USABLE WITH USB SERIAL
Description: Modbus can be used with USB serial, however, if the USB
- serial connectiont is lost, Modbus will hang in an infinite
+ serial connection is lost, Modbus will hang in an infinite
loop.
This is a problem in the handling of select() and read()
- and could probabaly resolved by studying the Modbus error
+ and could probably resolved by studying the Modbus error
handling.
A more USB-friendly solution would be to: (1) Re-connect and
diff --git a/arch/Kconfig b/arch/Kconfig
index 1efa5d52c2a4bd2ebeb961dcd9466204f56665e4..f1bd17077a6f6b6440bb6a9b5411550257b3f326 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -202,10 +202,23 @@ config ARCH_HAVE_RESET
bool
default n
+config ARCH_HAVE_FETCHADD
+ bool
+ default n
+
config ARCH_HAVE_RTC_SUBSECONDS
bool
default n
+config ARCH_GLOBAL_IRQDISABLE
+ bool
+ default n
+ ---help---
+ Indicates that disabling interrupts on one CPU will either (1) disable
+ all interrupts globally on all CPUs, or (2) will disable interprocessor
+ interrupts as well so that no context switches can occur on the CPU
+ that disabled "local" interrupts.
+
config ARCH_USE_MMU
bool "Enable MMU"
default n
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 63ca64635c4beb812ee091ff5b1490fdc14886c2..337f9910c21a30c13544acc0542cbd15fc138688 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -16,6 +16,7 @@ config ARCH_CHIP_A1X
select ARCH_HAVE_FPU
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_LOWVECTORS
+ select ARCH_HAVE_FETCHADD
select ARCH_HAVE_SDRAM
select BOOT_RUNFROMSDRAM
select ARCH_HAVE_ADDRENV
@@ -51,6 +52,7 @@ config ARCH_CHIP_EFM32
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_SPI_BITORDER
select ARMV7M_CMNVECTOR
+ select ARCH_HAVE_FETCHADD
---help---
Energy Micro EFM32 microcontrollers (ARM Cortex-M).
@@ -69,6 +71,7 @@ config ARCH_CHIP_IMX6
select ARCH_HAVE_FPU
select ARCH_HAVE_TRUSTZONE
select ARCH_HAVE_LOWVECTORS
+ select ARCH_HAVE_FETCHADD
select ARCH_HAVE_SDRAM
select BOOT_RUNFROMSDRAM
select ARCH_HAVE_ADDRENV
@@ -82,6 +85,7 @@ config ARCH_CHIP_KINETIS
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_FPU
+ select ARCH_HAVE_FETCHADD
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_I2CRESET
@@ -103,6 +107,7 @@ config ARCH_CHIP_LC823450
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_MULTICPU
select ARCH_HAVE_I2CRESET
+ select ARCH_GLOBAL_IRQDISABLE
---help---
ON Semiconductor LC823450 architectures (ARM dual Cortex-M3)
@@ -114,15 +119,6 @@ config ARCH_CHIP_LM
---help---
TI/Luminary Stellaris LMS3 and LM4F architectures (ARM Cortex-M3/4)
-config ARCH_CHIP_TIVA
- bool "TI Tiva"
- select ARCH_HAVE_CMNVECTOR
- select ARCH_HAVE_MPU
- select ARM_HAVE_MPU_UNIFIED
- select ARCH_HAVE_FPU
- ---help---
- TI Tiva TM4C architectures (ARM Cortex-M4)
-
config ARCH_CHIP_LPC11XX
bool "NXP LPC11xx"
select ARCH_CORTEXM0
@@ -136,6 +132,7 @@ config ARCH_CHIP_LPC17XX
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
+ select ARCH_HAVE_FETCHADD
---help---
NXP LPC17xx architectures (ARM Cortex-M3)
@@ -168,6 +165,7 @@ config ARCH_CHIP_LPC43XX
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_FPU
+ select ARCH_HAVE_FETCHADD
---help---
NPX LPC43XX architectures (ARM Cortex-M4).
@@ -179,6 +177,7 @@ config ARCH_CHIP_LPC54XX
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_FPU
+ select ARCH_HAVE_FETCHADD
---help---
NPX LPC54XX architectures (ARM Cortex-M4).
@@ -203,6 +202,7 @@ config ARCH_CHIP_SAMA5
select ARCH_HAVE_FPU
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_LOWVECTORS
+ select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_ADDRENV
@@ -229,6 +229,7 @@ config ARCH_CHIP_SAM34
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
+ select ARCH_HAVE_FETCHADD
select ARCH_HAVE_RAMFUNCS
select ARMV7M_HAVE_STACKCHECK
---help---
@@ -239,6 +240,7 @@ config ARCH_CHIP_SAMV7
select ARCH_HAVE_CMNVECTOR
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
+ select ARCH_HAVE_FETCHADD
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_I2CRESET
@@ -253,6 +255,7 @@ config ARCH_CHIP_STM32
bool "STMicro STM32 F1/F2/F3/F4"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU
+ select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
@@ -276,6 +279,7 @@ config ARCH_CHIP_STM32F7
select ARCH_HAVE_CMNVECTOR
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
+ select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_SPI_BITORDER
@@ -312,17 +316,29 @@ config ARCH_CHIP_TMS570
bool "TI TMS570"
select ENDIAN_BIG
select ARCH_HAVE_LOWVECTORS
+ select ARCH_HAVE_FETCHADD
select ARCH_HAVE_RAMFUNCS
select ARMV7R_MEMINIT
select ARMV7R_HAVE_DECODEFIQ
---help---
TI TMS570 family
+config ARCH_CHIP_TIVA
+ bool "TI Tiva"
+ select ARCH_HAVE_CMNVECTOR
+ select ARCH_HAVE_MPU
+ select ARM_HAVE_MPU_UNIFIED
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_FETCHADD
+ ---help---
+ TI Tiva TM4C architectures (ARM Cortex-M4)
+
config ARCH_CHIP_XMC4
bool "Infineon XMC4xxx"
select ARCH_HAVE_CMNVECTOR
select ARCH_CORTEXM4
select ARCH_HAVE_MPU
+ select ARCH_HAVE_FETCHADD
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_I2CRESET
select ARM_HAVE_MPU_UNIFIED
diff --git a/arch/arm/include/samdl/samd21_irq.h b/arch/arm/include/samdl/samd21_irq.h
index e0b26bf962a8b0c4bc1e06a420b166e048e6139d..8c44ed256d8fc74eefa576034bccabcb1f050ed9 100644
--- a/arch/arm/include/samdl/samd21_irq.h
+++ b/arch/arm/include/samdl/samd21_irq.h
@@ -86,9 +86,9 @@
#define SAM_IRQ_NINTS (28) /* Total number of interrupts */
#define SAM_IRQ_NIRQS (SAM_IRQ_INTERRUPT+28) /* The number of real interrupts */
-/* GPIO interrupts. Up to 16 pins may be configured to support interrupts */
+/* EIC interrupts. Up to 16 pins may be configured to support interrupts */
-#ifdef CONFIG_SAMDL_GPIOIRQ
+#ifdef CONFIG_SAMDL_EIC
# define SAM_IRQ_EXTINT0 (SAM_IRQ_NIRQS+0) /* External interrupt 0 */
# define SAM_IRQ_EXTINT1 (SAM_IRQ_NIRQS+1) /* External interrupt 1 */
# define SAM_IRQ_EXTINT2 (SAM_IRQ_NIRQS+2) /* External interrupt 2 */
diff --git a/arch/arm/include/spinlock.h b/arch/arm/include/spinlock.h
index 16079cc81a333f6fed72d3e7b80662859eb0390f..4a129faccabd5d395d76b06329c220f7704b824b 100644
--- a/arch/arm/include/spinlock.h
+++ b/arch/arm/include/spinlock.h
@@ -130,7 +130,7 @@ typedef uint8_t spinlock_t;
* Description:
* Perform an atomic test and set operation on the provided spinlock.
*
- * This function must be provided via the architecture-specific logoic.
+ * This function must be provided via the architecture-specific logic.
*
* Input Parameters:
* lock - The address of spinlock object.
diff --git a/arch/arm/src/a1x/Make.defs b/arch/arm/src/a1x/Make.defs
index 7ffb41537e9ea2cdac4c22f0fd332bff095c2302..2697e5363d4539446f3440e95b8fbbef13605707 100644
--- a/arch/arm/src/a1x/Make.defs
+++ b/arch/arm/src/a1x/Make.defs
@@ -55,7 +55,7 @@ endif
CMN_ASRCS += arm_vectors.S arm_fpuconfig.S arm_fullcontextrestore.S
CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S arm_vfork.S
-CMN_ASRCS += arm_testset.S
+CMN_ASRCS += arm_testset.S arm_fetchadd.S
CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S
diff --git a/arch/arm/src/a1x/a1x_boot.c b/arch/arm/src/a1x/a1x_boot.c
index 1dc27fd636520bc0cc3214c363b84cd3b64907c9..95bfc97aa1a7a245c1eef573eb29df107355fd5f 100644
--- a/arch/arm/src/a1x/a1x_boot.c
+++ b/arch/arm/src/a1x/a1x_boot.c
@@ -124,7 +124,7 @@ static const struct section_mapping_s section_mapping[] =
/****************************************************************************
* Name: a1x_setupmappings
*
- * Description
+ * Description:
* Map all of the initial memory regions defined in section_mapping[]
*
****************************************************************************/
diff --git a/arch/arm/src/a1x/a1x_serial.c b/arch/arm/src/a1x/a1x_serial.c
index 307dac2d5e0f7d9d1b18fe773488376bc968bbaa..0a91003a28a2d50d26e7d325916231238fdb1d03 100644
--- a/arch/arm/src/a1x/a1x_serial.c
+++ b/arch/arm/src/a1x/a1x_serial.c
@@ -710,7 +710,7 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
/************************************************************************************
* Name: a1x_uart0config, uart1config, uart2config, ..., uart7config
*
- * Descrption:
+ * Description:
* Configure the UART
*
************************************************************************************/
@@ -886,7 +886,7 @@ static inline void a1x_uart7config(void)
/************************************************************************************
* Name: a1x_uartdl
*
- * Descrption:
+ * Description:
* Select a divider to produce the BAUD from the UART PCLK.
*
* BAUD = PCLK / (16 * DL), or
diff --git a/arch/arm/src/arm/pg_macros.h b/arch/arm/src/arm/pg_macros.h
index 47616b426ae20f77dfe1dc346c85a8f6acc7afed..94263c7eb533f84421c8ee728284971a1ab30608 100644
--- a/arch/arm/src/arm/pg_macros.h
+++ b/arch/arm/src/arm/pg_macros.h
@@ -377,7 +377,7 @@
* ldr r3, =MMUFLAGS <-- L2 MMU flags
* pg_l2map r0, r1, r2, r3, r4
*
- * Inputs:
+ * Input Parameters:
* l2 - Physical or virtual start address in the L2 page table, depending
* upon the context. (modified)
* ppage - The physical address of the start of the region to span. Must
@@ -448,7 +448,7 @@
* ldr r4, =MMU_L1_PGTABFLAGS <-- L1 MMU flags
* pg_l1span r0, r1, r2, r3, r4, r4
*
- * Inputs (unmodified unless noted):
+ * Input Parameters (unmodified unless noted):
* l1 - Physical or virtual address in the L1 table to begin writing (modified)
* l2 - Physical start address in the L2 page table (modified)
* npages - Number of pages to required to span that memory region (modified)
@@ -462,7 +462,7 @@
* ppage - After the first page, this will be the full number of pages.
* tmp - scratch
*
- * Return:
+ * Returned Value:
* Nothing of interest.
*
* Assumptions:
diff --git a/arch/arm/src/arm/up_blocktask.c b/arch/arm/src/arm/up_blocktask.c
index 716966714561b7eae8a8e399edaa6f471d440f3a..97d1838d8a2f186790b8e3c920432aaf99287ba9 100644
--- a/arch/arm/src/arm/up_blocktask.c
+++ b/arch/arm/src/arm/up_blocktask.c
@@ -62,7 +62,7 @@
* the ready to run list must be stopped. Save its context
* and move it to the inactive list specified by task_state.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to a task in the ready-to-run list (normally
* the task at the head of the list). It most be
* stopped, its context saved and moved into one of the
diff --git a/arch/arm/src/arm/up_dataabort.c b/arch/arm/src/arm/up_dataabort.c
index 318c59232c46ab0464c2a6c3be1ec2885247cdf7..2a348b401e2911e232a8cd057791e44e488cb54c 100644
--- a/arch/arm/src/arm/up_dataabort.c
+++ b/arch/arm/src/arm/up_dataabort.c
@@ -59,7 +59,7 @@
/****************************************************************************
* Name: up_dataabort
*
- * Input parameters:
+ * Input Parameters:
* regs - The standard, ARM register save array.
*
* If CONFIG_PAGING is selected in the NuttX configuration file, then these
diff --git a/arch/arm/src/arm/up_prefetchabort.c b/arch/arm/src/arm/up_prefetchabort.c
index ab97efd5737264712b8b8e4b20e68e35d7ad9f00..7fc02b11df320753e88c719c871d11b948d186d9 100644
--- a/arch/arm/src/arm/up_prefetchabort.c
+++ b/arch/arm/src/arm/up_prefetchabort.c
@@ -69,7 +69,7 @@
/****************************************************************************
* Name: up_prefetchabort
*
- * Description;
+ * Description:
* This is the prefetch abort exception handler. The ARM prefetch abort
* exception occurs when a memory fault is detected during an an
* instruction fetch.
diff --git a/arch/arm/src/arm/up_reprioritizertr.c b/arch/arm/src/arm/up_reprioritizertr.c
index 95679e31dd7276d9b11c1c24d8a8dfa25e7c1e1c..10175b0df511ffccea33472afcf1512658ce4d99 100644
--- a/arch/arm/src/arm/up_reprioritizertr.c
+++ b/arch/arm/src/arm/up_reprioritizertr.c
@@ -68,7 +68,7 @@
* the priority of the current, running task and it now has the
* priority.
*
- * Inputs:
+ * Input Parameters:
* tcb: The TCB of the task that has been reprioritized
* priority: The new task priority
*
diff --git a/arch/arm/src/arm/up_unblocktask.c b/arch/arm/src/arm/up_unblocktask.c
index 12cb984d831bb31fc86a9d26052d0ae87972b139..e94c81de0c5cedd835d8c5ccf37f6c01988b0107 100644
--- a/arch/arm/src/arm/up_unblocktask.c
+++ b/arch/arm/src/arm/up_unblocktask.c
@@ -61,7 +61,7 @@
* but has been prepped to execute. Move the TCB to the
* ready-to-run list, restore its context, and start execution.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to the tcb to be unblocked. This tcb is
* in one of the waiting tasks lists. It must be moved to
* the ready-to-run list and, if it is the highest priority
diff --git a/arch/arm/src/arm/vfork.S b/arch/arm/src/arm/vfork.S
index 161315466fe81dd18b3bea6b31dd026500ec1244..661546daabe5a3ab79435d4b556fb2ed0e0a5825 100644
--- a/arch/arm/src/arm/vfork.S
+++ b/arch/arm/src/arm/vfork.S
@@ -86,10 +86,10 @@
* 5) up_vfork() then calls task_vforkstart()
* 6) task_vforkstart() then executes the child thread.
*
- * Input Paremeters:
+ * Input Parameters:
* None
*
- * Return:
+ * Returned Value:
* Upon successful completion, vfork() returns 0 to the child process and returns
* the process ID of the child process to the parent process. Otherwise, -1 is
* returned to the parent, no child process is created, and errno is set to
diff --git a/arch/arm/src/armv6-m/up_blocktask.c b/arch/arm/src/armv6-m/up_blocktask.c
index 2a95163cca220e9fedaf323a7f0ebc88d02771d2..c01894715a41cbee523c6c2e6f86b0e913fcd9e2 100644
--- a/arch/arm/src/armv6-m/up_blocktask.c
+++ b/arch/arm/src/armv6-m/up_blocktask.c
@@ -61,7 +61,7 @@
* be stopped. Save its context and move it to the inactive list specified
* by task_state.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to a task in the ready-to-run list (normally the task at
* the head of the list). It most be stopped, its context saved and
* moved into one of the waiting task lists. It it was the task at the
diff --git a/arch/arm/src/armv6-m/up_fullcontextrestore.S b/arch/arm/src/armv6-m/up_fullcontextrestore.S
index 048c468749d44feff5c0c0eb6deaf4a23f38fbea..4ec6a32a7ed743d7c59b40bc3a2765c6ad40ffdc 100644
--- a/arch/arm/src/armv6-m/up_fullcontextrestore.S
+++ b/arch/arm/src/armv6-m/up_fullcontextrestore.S
@@ -70,7 +70,7 @@
*
* void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
*
- * Return:
+ * Returned Value:
* None
*
************************************************************************************/
diff --git a/arch/arm/src/armv6-m/up_reprioritizertr.c b/arch/arm/src/armv6-m/up_reprioritizertr.c
index 41f0c8700d33b9b6859c372b6a134087d4ed89e7..0f99b917407ec6efc46c6caa0d1cebc2f3ee95dc 100644
--- a/arch/arm/src/armv6-m/up_reprioritizertr.c
+++ b/arch/arm/src/armv6-m/up_reprioritizertr.c
@@ -67,7 +67,7 @@
* the priority of the current, running task and it now has the
* priority.
*
- * Inputs:
+ * Input Parameters:
* tcb: The TCB of the task that has been reprioritized
* priority: The new task priority
*
diff --git a/arch/arm/src/armv6-m/up_saveusercontext.S b/arch/arm/src/armv6-m/up_saveusercontext.S
index bfc9a70ea884a35f1a6cfb71df9a72e53f60bd16..55e6461b2b40ab27589d4f3badd0b6bf3c457a6f 100644
--- a/arch/arm/src/armv6-m/up_saveusercontext.S
+++ b/arch/arm/src/armv6-m/up_saveusercontext.S
@@ -70,7 +70,7 @@
*
* int up_saveusercontext(uint32_t *saveregs);
*
- * Return:
+ * Returned Value:
* 0: Normal return
* 1: Context switch return
*
diff --git a/arch/arm/src/armv6-m/up_signal_dispatch.c b/arch/arm/src/armv6-m/up_signal_dispatch.c
index fa3cea62224a18debaf5079b8cc5b89c285a155f..45446a2b5e47a3d2dfc4e747fd515cc71c2f5a11 100644
--- a/arch/arm/src/armv6-m/up_signal_dispatch.c
+++ b/arch/arm/src/armv6-m/up_signal_dispatch.c
@@ -78,12 +78,12 @@
* user-space, signal handler trampoline function. It is called from
* up_signal_dispatch() in user-mode.
*
- * Inputs:
+ * Input Parameters:
* sighand - The address user-space signal handling function
* signo, info, and ucontext - Standard arguments to be passed to the
* signal handling function.
*
- * Return:
+ * Returned Value:
* None. This function does not return in the normal sense. It returns
* via an architecture specific system call made by up_signal_handler().
* However, this will look like a normal return by the caller of
diff --git a/arch/arm/src/armv6-m/up_signal_handler.S b/arch/arm/src/armv6-m/up_signal_handler.S
index f294db9fc805872e268044ddd079a4791fd9e32d..9ad7ec81330d055ffa60067b8a92fa0e508fdf66 100644
--- a/arch/arm/src/armv6-m/up_signal_handler.S
+++ b/arch/arm/src/armv6-m/up_signal_handler.S
@@ -65,13 +65,13 @@
* This function is the user-space, signal handler trampoline function. It
* is called from up_signal_dispatch() in user-mode.
*
- * Inputs:
+ * Input Parameters:
* R0 = sighand
* The address user-space signal handling function
* R1-R3 = signo, info, and ucontext
* Standard arguments to be passed to the signal handling function.
*
- * Return:
+ * Returned Value:
* None. This function does not return in the normal sense. It returns
* via the SYS_signal_handler_return (see svcall.h)
*
diff --git a/arch/arm/src/armv6-m/up_switchcontext.S b/arch/arm/src/armv6-m/up_switchcontext.S
index c24f501fc2e6958d588a6e54cc7ad33d5e759a61..dc5aca9169bf56a123c1cc46f96552453390b38f 100644
--- a/arch/arm/src/armv6-m/up_switchcontext.S
+++ b/arch/arm/src/armv6-m/up_switchcontext.S
@@ -71,7 +71,7 @@
*
* void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs);
*
- * Return:
+ * Returned Value:
* None
*
************************************************************************************/
diff --git a/arch/arm/src/armv6-m/up_unblocktask.c b/arch/arm/src/armv6-m/up_unblocktask.c
index 62ec07d90a31c2688a5283d50d78c2e1de8672d1..1fbae1295093789f78430c893a46a018aad288cc 100644
--- a/arch/arm/src/armv6-m/up_unblocktask.c
+++ b/arch/arm/src/armv6-m/up_unblocktask.c
@@ -60,7 +60,7 @@
* execute. Move the TCB to the ready-to-run list, restore its context,
* and start execution.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to the tcb to be unblocked. This tcb is in one of the
* waiting tasks lists. It must be moved to the ready-to-run list and,
* if it is the highest priority ready to run taks, executed.
diff --git a/arch/arm/src/armv6-m/vfork.S b/arch/arm/src/armv6-m/vfork.S
index 20c003d3ea9fbb7b8d7dd22789810c28b31d5192..c64e96e22cff780737965efa18142bb6e0cb32e4 100644
--- a/arch/arm/src/armv6-m/vfork.S
+++ b/arch/arm/src/armv6-m/vfork.S
@@ -87,10 +87,10 @@
* 5) up_vfork() then calls task_vforkstart()
* 6) task_vforkstart() then executes the child thread.
*
- * Input Paremeters:
+ * Input Parameters:
* None
*
- * Return:
+ * Returned Value:
* Upon successful completion, vfork() returns 0 to the child process and returns
* the process ID of the child process to the parent process. Otherwise, -1 is
* returned to the parent, no child process is created, and errno is set to
diff --git a/arch/arm/src/armv7-a/arm_blocktask.c b/arch/arm/src/armv7-a/arm_blocktask.c
index 3f02e46b362b80cc8e1e00311b4c57d6acac62bb..8fdbef00a36fa573155dddcfc1b4a24b71491389 100644
--- a/arch/arm/src/armv7-a/arm_blocktask.c
+++ b/arch/arm/src/armv7-a/arm_blocktask.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-a/up_blocktask.c
*
- * Copyright (C) 2013-2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013-2015, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -62,7 +62,7 @@
* the ready to run list must be stopped. Save its context
* and move it to the inactive list specified by task_state.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to a task in the ready-to-run list (normally
* the task at the head of the list). It most be
* stopped, its context saved and moved into one of the
@@ -76,8 +76,21 @@
void up_block_task(struct tcb_s *tcb, tstate_t task_state)
{
- struct tcb_s *rtcb = this_task();
+ struct tcb_s *rtcb;
bool switch_needed;
+#ifdef CONFIG_SMP
+ int cpu;
+
+ /* Get the TCB of the currently executing task on this CPU (avoid using
+ * this_task() because the TCBs may be in an inappropriate state right
+ * now).
+ */
+
+ cpu = this_cpu();
+ rtcb = current_task(cpu);
+#else
+ rtcb = this_task();
+#endif
/* Verify that the context switch can be performed */
@@ -128,7 +141,11 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
* of the ready-to-run task list.
*/
+#ifdef CONFIG_SMP
+ rtcb = current_task(cpu);
+#else
rtcb = this_task();
+#endif
/* Reset scheduler parameters */
@@ -152,7 +169,11 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
* of the ready-to-run task list.
*/
+#ifdef CONFIG_SMP
+ rtcb = current_task(cpu);
+#else
rtcb = this_task();
+#endif
#ifdef CONFIG_ARCH_ADDRENV
/* Make sure that the address environment for the previously
diff --git a/arch/arm/src/armv7-a/arm_cpuhead.S b/arch/arm/src/armv7-a/arm_cpuhead.S
index 02735e36d50c39df1d5ff8a558fcf138d66df0fa..3ed001656d387490bcaacb66c744e68573c1cd94 100644
--- a/arch/arm/src/armv7-a/arm_cpuhead.S
+++ b/arch/arm/src/armv7-a/arm_cpuhead.S
@@ -93,7 +93,7 @@
*
* These functions are provided by the common ARMv7-A logic.
*
- * Input parameters:
+ * Input Parameters:
* None
*
* Returned Value:
diff --git a/arch/arm/src/armv7-a/arm_cpuidlestack.c b/arch/arm/src/armv7-a/arm_cpuidlestack.c
index dd264d25c148c4e3f42adef1fc36860a5b953909..1648de2fdb89ba1a694d69e28eec8a0e7e96d500 100644
--- a/arch/arm/src/armv7-a/arm_cpuidlestack.c
+++ b/arch/arm/src/armv7-a/arm_cpuidlestack.c
@@ -112,7 +112,7 @@ static FAR const uint32_t *g_cpu_stackalloc[CONFIG_SMP_NCPUS] =
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
* the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - cpu: CPU index that indicates which CPU the IDLE task is
* being created for.
* - tcb: The TCB of new CPU IDLE task
diff --git a/arch/arm/src/armv7-a/arm_dataabort.c b/arch/arm/src/armv7-a/arm_dataabort.c
index 50c95a20188001fd7013b49f8822ce9ec930d9bc..17073a925e0c27a5c4c356fa20c44ac7de7004c2 100644
--- a/arch/arm/src/armv7-a/arm_dataabort.c
+++ b/arch/arm/src/armv7-a/arm_dataabort.c
@@ -59,7 +59,7 @@
/****************************************************************************
* Name: arm_dataabort
*
- * Input parameters:
+ * Input Parameters:
* regs - The standard, ARM register save array.
*
* If CONFIG_PAGING is selected in the NuttX configuration file, then these
diff --git a/arch/arm/src/armv7-a/arm_fetchadd.S b/arch/arm/src/armv7-a/arm_fetchadd.S
new file mode 100644
index 0000000000000000000000000000000000000000..84b0b7d482359f802c8d7fe1c4779b7d1b33030f
--- /dev/null
+++ b/arch/arm/src/armv7-a/arm_fetchadd.S
@@ -0,0 +1,255 @@
+/****************************************************************************
+ * arch/arm/src/armv7-a/arm_fetchadd.S
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+ .file "arm_fetchadd.S"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+ .text
+
+/****************************************************************************
+ * Name: up_fetchadd32
+ *
+ * Description:
+ * Perform an atomic fetch add operation on the provided 32-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 32-bit value to be incremented.
+ * value - The 32-bit addend
+ *
+ * Returned Value:
+ * The incremented value (volatile!)
+ *
+ ****************************************************************************/
+
+ .globl up_fetchadd32
+ .type up_fetchadd32, %function
+
+up_fetchadd32:
+
+1:
+ ldrex r2, [r0] /* Fetch the value to be incremented */
+ add r2, r2, r1 /* Add the addend */
+
+ strex r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strex failed */
+ bne 1b /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the incremented value */
+ bx lr /* Successful! */
+ .size up_fetchadd32, . - up_fetchadd32
+
+/****************************************************************************
+ * Name: up_fetchsub32
+ *
+ * Description:
+ * Perform an atomic fetch subtract operation on the provided 32-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 32-bit value to be decremented.
+ * value - The 32-bit subtrahend
+ *
+ * Returned Value:
+ * The decremented value (volatile!)
+ *
+ ****************************************************************************/
+
+ .globl up_fetchsub32
+ .type up_fetchsub32, %function
+
+up_fetchsub32:
+
+1:
+ ldrex r2, [r0] /* Fetch the value to be decremented */
+ sub r2, r2, r1 /* Subtract the subtrahend */
+
+ strex r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strex failed */
+ bne 1b /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the decremented value */
+ bx lr /* Successful! */
+ .size up_fetchsub32, . - up_fetchsub32
+
+/****************************************************************************
+ * Name: up_fetchadd16
+ *
+ * Description:
+ * Perform an atomic fetch add operation on the provided 16-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 16-bit value to be incremented.
+ * value - The 16-bit addend
+ *
+ * Returned Value:
+ * The incremented value (volatile!)
+ *
+ ****************************************************************************/
+
+ .globl up_fetchadd16
+ .type up_fetchadd16, %function
+
+up_fetchadd16:
+
+1:
+ ldrexh r2, [r0] /* Fetch the value to be incremented */
+ add r2, r2, r1 /* Add the addend */
+
+ strexh r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strexh failed */
+ bne 1b /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the incremented value */
+ bx lr /* Successful! */
+ .size up_fetchadd16, . - up_fetchadd16
+
+/****************************************************************************
+ * Name: up_fetchsub16
+ *
+ * Description:
+ * Perform an atomic fetch subtract operation on the provided 16-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 16-bit value to be decremented.
+ * value - The 16-bit subtrahend
+ *
+ * Returned Value:
+ * The decremented value (volatile!)
+ *
+ ****************************************************************************/
+
+ .globl up_fetchsub16
+ .type up_fetchsub16, %function
+
+up_fetchsub16:
+
+1:
+ ldrexh r2, [r0] /* Fetch the value to be decremented */
+ sub r2, r2, r1 /* Subtract the subtrahend */
+
+ /* Attempt to save the decremented value */
+
+ strexh r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strexh failed */
+ bne 1b /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the decremented value */
+ bx lr /* Successful! */
+ .size up_fetchsub16, . - up_fetchsub16
+
+/****************************************************************************
+ * Name: up_fetchadd8
+ *
+ * Description:
+ * Perform an atomic fetch add operation on the provided 8-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 8-bit value to be incremented.
+ * value - The 8-bit addend
+ *
+ * Returned Value:
+ * The incremented value (volatile!)
+ *
+ ****************************************************************************/
+
+ .globl up_fetchadd8
+ .type up_fetchadd8, %function
+
+up_fetchadd8:
+
+1:
+ ldrexb r2, [r0] /* Fetch the value to be incremented */
+ add r2, r2, r1 /* Add the addend */
+
+ strexb r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strexb failed */
+ bne 1b /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the incremented value */
+ bx lr /* Successful! */
+ .size up_fetchadd8, . - up_fetchadd8
+
+/****************************************************************************
+ * Name: up_fetchsub8
+ *
+ * Description:
+ * Perform an atomic fetch subtract operation on the provided 8-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 8-bit value to be decremented.
+ * value - The 8-bit subtrahend
+ *
+ * Returned Value:
+ * The decremented value (volatile!)
+ *
+ ****************************************************************************/
+
+ .globl up_fetchsub8
+ .type up_fetchsub8, %function
+
+up_fetchsub8:
+
+1:
+ ldrexb r2, [r0] /* Fetch the value to be decremented */
+ sub r2, r2, r1 /* Subtract the subtrahend */
+
+ strexb r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strexb failed */
+ bne 1b /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the decremented value */
+ bx lr /* Successful! */
+ .size up_fetchsub8, . - up_fetchsub8
+ .end
diff --git a/arch/arm/src/armv7-a/arm_fullcontextrestore.S b/arch/arm/src/armv7-a/arm_fullcontextrestore.S
index 64f74c8a98f9f4ab0b8754f46a20b5a3a6e1e94c..f65adbfadb3ff26d3aa56606a264431dab526f4f 100644
--- a/arch/arm/src/armv7-a/arm_fullcontextrestore.S
+++ b/arch/arm/src/armv7-a/arm_fullcontextrestore.S
@@ -62,7 +62,7 @@
*
* void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
*
- * Return:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/armv7-a/arm_gicv2.c b/arch/arm/src/armv7-a/arm_gicv2.c
index 0232685dc828fa01fde4bddc51a3cd5b7f189655..8c6eee1509ac0372ea477b3f22ec320bc3cfe518 100644
--- a/arch/arm/src/armv7-a/arm_gicv2.c
+++ b/arch/arm/src/armv7-a/arm_gicv2.c
@@ -372,7 +372,7 @@ void arm_gic_initialize(void)
* the irq number of the interrupt and then to call arm_doirq to dispatch
* the interrupt.
*
- * Input parameters:
+ * Input Parameters:
* regs - A pointer to the register save area on the stack.
*
****************************************************************************/
@@ -532,7 +532,7 @@ int up_prioritize_irq(int irq, int priority)
* Since this API is not supported on all architectures, it should be
* avoided in common implementations where possible.
*
- * Input Paramters:
+ * Input Parameters:
* irq - The interrupt request to modify.
* edge - False: Active HIGH level sensitive, True: Rising edge sensitive
*
diff --git a/arch/arm/src/armv7-a/arm_prefetchabort.c b/arch/arm/src/armv7-a/arm_prefetchabort.c
index 0bb8cd37932f68ed9c101f5ad575b3a7f7f16f38..a10f703287c2b7ef0bdedfaae7db56a29b0d8d1e 100644
--- a/arch/arm/src/armv7-a/arm_prefetchabort.c
+++ b/arch/arm/src/armv7-a/arm_prefetchabort.c
@@ -57,7 +57,7 @@
/****************************************************************************
* Name: arm_prefetchabort
*
- * Description;
+ * Description:
* This is the prefetch abort exception handler. The ARM prefetch abort
* exception occurs when a memory fault is detected during an an
* instruction fetch.
diff --git a/arch/arm/src/armv7-a/arm_releasepending.c b/arch/arm/src/armv7-a/arm_releasepending.c
index 7afc6989a75829f647ee14ba35e2a6b3ef991415..b4a811f7d2ff4dc34e03f265f1889d8256820368 100644
--- a/arch/arm/src/armv7-a/arm_releasepending.c
+++ b/arch/arm/src/armv7-a/arm_releasepending.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-a/arm_releasepending.c
*
- * Copyright (C) 2013-2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013-2015, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -56,16 +56,28 @@
* Name: up_release_pending
*
* Description:
- * Release and ready-to-run tasks that have
- * collected in the pending task list. This can call a
- * context switch if a new task is placed at the head of
- * the ready to run list.
+ * Release and ready-to-run tasks that have collected in the pending task
+ * list. This can call a context switch if a new task is placed at the
+ * head of the ready to run list.
*
****************************************************************************/
void up_release_pending(void)
{
- struct tcb_s *rtcb = this_task();
+ struct tcb_s *rtcb;
+#ifdef CONFIG_SMP
+ int cpu;
+
+ /* Get the TCB of the currently executing task on this CPU (avoid using
+ * this_task() because the TCBs may be in an inappropriate state right
+ * now).
+ */
+
+ cpu = this_cpu();
+ rtcb = current_task(cpu);
+#else
+ rtcb = this_task();
+#endif
sinfo("From TCB=%p\n", rtcb);
@@ -96,7 +108,11 @@ void up_release_pending(void)
* of the ready-to-run task list.
*/
+#ifdef CONFIG_SMP
+ rtcb = current_task(cpu);
+#else
rtcb = this_task();
+#endif
/* Update scheduler parameters */
@@ -121,7 +137,11 @@ void up_release_pending(void)
* of the ready-to-run task list.
*/
+#ifdef CONFIG_SMP
+ rtcb = current_task(cpu);
+#else
rtcb = this_task();
+#endif
#ifdef CONFIG_ARCH_ADDRENV
/* Make sure that the address environment for the previously
diff --git a/arch/arm/src/armv7-a/arm_reprioritizertr.c b/arch/arm/src/armv7-a/arm_reprioritizertr.c
index 4381178e05b311e620c620b6d9465e10cec5a333..359392e990b6324a946d194ac4db97ef8f2dd500 100644
--- a/arch/arm/src/armv7-a/arm_reprioritizertr.c
+++ b/arch/arm/src/armv7-a/arm_reprioritizertr.c
@@ -68,7 +68,7 @@
* the priority of the current, running task and it now has the
* priority.
*
- * Inputs:
+ * Input Parameters:
* tcb: The TCB of the task that has been reprioritized
* priority: The new task priority
*
@@ -92,8 +92,21 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
}
else
{
- struct tcb_s *rtcb = this_task();
+ struct tcb_s *rtcb;
bool switch_needed;
+#ifdef CONFIG_SMP
+ int cpu;
+
+ /* Get the TCB of the currently executing task on this CPU (avoid
+ * using this_task() because the TCBs may be in an inappropriate
+ * state right now).
+ */
+
+ cpu = this_cpu();
+ rtcb = current_task(cpu);
+#else
+ rtcb = this_task();
+#endif
sinfo("TCB=%p PRI=%d\n", tcb, priority);
@@ -150,7 +163,11 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
* of the ready-to-run task list.
*/
+#ifdef CONFIG_SMP
+ rtcb = current_task(cpu);
+#else
rtcb = this_task();
+#endif
/* Update scheduler parameters */
@@ -174,7 +191,11 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
* of the ready-to-run task list.
*/
+#ifdef CONFIG_SMP
+ rtcb = current_task(cpu);
+#else
rtcb = this_task();
+#endif
#ifdef CONFIG_ARCH_ADDRENV
/* Make sure that the address environment for the previously
diff --git a/arch/arm/src/armv7-a/arm_schedulesigaction.c b/arch/arm/src/armv7-a/arm_schedulesigaction.c
index 9f1a46f67542b2a245d73006af5bec0462302d7a..2bb30374a399f85d2a7d59e191436b3b114789b8 100644
--- a/arch/arm/src/armv7-a/arm_schedulesigaction.c
+++ b/arch/arm/src/armv7-a/arm_schedulesigaction.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-a/arm_schedulesigaction.c
*
- * Copyright (C) 2013, 2015-2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2015-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -116,7 +116,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
if (tcb == this_task())
{
/* CASE 1: We are not in an interrupt handler and a task is
- * signalling itself for some reason.
+ * signaling itself for some reason.
*/
if (!CURRENT_REGS)
@@ -133,7 +133,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*
* Hmmm... there looks like a latent bug here: The following logic
* would fail in the strange case where we are in an interrupt
- * handler, the thread is signalling itself, but a context switch
+ * handler, the thread is signaling itself, but a context switch
* to another task has occurred so that CURRENT_REGS does not
* refer to the thread of this_task()!
*/
@@ -166,7 +166,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
/* Otherwise, we are (1) signaling a task is not running from an
* interrupt handler or (2) we are not in an interrupt handler and the
- * running task is signalling some other non-running task.
+ * running task is signaling some other non-running task.
*/
else
@@ -222,7 +222,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
cpu = tcb->cpu;
/* CASE 1: We are not in an interrupt handler and a task is
- * signalling itself for some reason.
+ * signaling itself for some reason.
*/
if (cpu == me && !CURRENT_REGS)
@@ -238,51 +238,36 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* CPU. In the former case, we will have to PAUSE the other CPU
* first. But in either case, we will have to modify the return
* state as well as the state in the TCB.
- *
- * Hmmm... there looks like a latent bug here: The following logic
- * would fail in the strange case where we are in an interrupt
- * handler, the thread is signalling itself, but a context switch
- * to another task has occurred so that CURRENT_REGS does not
- * refer to the thread of this_task()!
*/
else
{
- /* If we signalling a task running on the other CPU, we have
+ /* If we signaling a task running on the other CPU, we have
* to PAUSE the other CPU.
*/
if (cpu != me)
{
+ /* Pause the CPU */
+
up_cpu_pause(cpu);
- }
- /* Save the return lr and cpsr and one scratch register
- * These will be restored by the signal trampoline after
- * the signals have been delivered.
- */
+ /* Wait while the pause request is pending */
- tcb->xcp.sigdeliver = sigdeliver;
- tcb->xcp.saved_pc = CURRENT_REGS[REG_PC];
- tcb->xcp.saved_cpsr = CURRENT_REGS[REG_CPSR];
+ while (up_cpu_pausereq(cpu))
+ {
+ }
- /* Increment the IRQ lock count so that when the task is restarted,
- * it will hold the IRQ spinlock.
- */
+ /* Now tcb on the other CPU can be accessed safely */
- DEBUGASSERT(tcb->irqcount < INT16_MAX);
- tcb->irqcount++;
+ /* Copy tcb->xcp.regs to tcp.xcp.saved. These will be restored
+ * by the signal trampoline after the signal has been delivered.
+ */
- /* Handle a possible race condition where the TCB was suspended
- * just before we paused the other CPU. The critical section
- * established above will prevent new threads from running on
- * that CPU, but it will not guarantee that the running thread
- * did not suspend itself (allowing any threads "assigned" to
- * the CPU to run).
- */
+ tcb->xcp.sigdeliver = sigdeliver;
+ tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC];
+ tcb->xcp.saved_cpsr = tcb->xcp.regs[REG_CPSR];
- if (tcb->task_state != TSTATE_TASK_RUNNING)
- {
/* Then set up to vector to the trampoline with interrupts
* disabled
*/
@@ -292,22 +277,25 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
}
else
{
- /* Then set up to vector to the trampoline with interrupts
- * disabled
+ /* tcb is running on the same CPU */
+
+ /* Save the return PC, CPSR and either the BASEPRI or PRIMASK
+ * registers (and perhaps also the LR). These will be
+ * restored by the signal trampoline after the signal has been
+ * delivered.
*/
- CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
- CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
+ tcb->xcp.sigdeliver = (FAR void *)sigdeliver;
+ tcb->xcp.saved_pc = CURRENT_REGS[REG_PC];
+ tcb->xcp.saved_cpsr = CURRENT_REGS[REG_CPSR];
- /* In an SMP configuration, the interrupt disable logic also
- * involves spinlocks that are configured per the TCB irqcount
- * field. This is logically equivalent to enter_critical_section().
- * The matching call to leave_critical_section() will be
- * performed in up_sigdeliver().
+ /* Then set up vector to the trampoline with interrupts
+ * disabled. The kernel-space trampoline must run in
+ * privileged thread mode.
*/
- spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock,
- &g_cpu_irqlock);
+ CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
+ CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
/* And make sure that the saved context in the TCB is the same
* as the interrupt return context.
@@ -316,6 +304,23 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
up_savestate(tcb->xcp.regs);
}
+ /* Increment the IRQ lock count so that when the task is restarted,
+ * it will hold the IRQ spinlock.
+ */
+
+ DEBUGASSERT(tcb->irqcount < INT16_MAX);
+ tcb->irqcount++;
+
+ /* In an SMP configuration, the interrupt disable logic also
+ * involves spinlocks that are configured per the TCB irqcount
+ * field. This is logically equivalent to enter_critical_section().
+ * The matching call to leave_critical_section() will be
+ * performed in up_sigdeliver().
+ */
+
+ spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock,
+ &g_cpu_irqlock);
+
/* RESUME the other CPU if it was PAUSED */
if (cpu != me)
@@ -327,7 +332,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
/* Otherwise, we are (1) signaling a task is not running from an
* interrupt handler or (2) we are not in an interrupt handler and the
- * running task is signalling some other non-running task.
+ * running task is signaling some other non-running task.
*/
else
diff --git a/arch/arm/src/armv7-a/arm_signal_dispatch.c b/arch/arm/src/armv7-a/arm_signal_dispatch.c
index 5925923760fe5aea3ba112b801c821a9038f1430..1b461f5cb922b17e8a4ec0b943f279a0f38ecb62 100644
--- a/arch/arm/src/armv7-a/arm_signal_dispatch.c
+++ b/arch/arm/src/armv7-a/arm_signal_dispatch.c
@@ -67,12 +67,12 @@
* user-space, signal handler trampoline function. It is called from
* up_signal_dispatch() in user-mode.
*
- * Inputs:
+ * Input Parameters:
* sighand - The address user-space signal handling function
* signo, info, and ucontext - Standard arguments to be passed to the
* signal handling function.
*
- * Return:
+ * Returned Value:
* None. This function does not return in the normal sense. It returns
* via an architecture specific system call made by up_signal_handler().
* However, this will look like a normal return by the caller of
diff --git a/arch/arm/src/armv7-a/arm_testset.S b/arch/arm/src/armv7-a/arm_testset.S
index 638736e4d6729815674902098a7e3c867ee42760..feb3ea3df466e323841461456be872bd6ecb569d 100644
--- a/arch/arm/src/armv7-a/arm_testset.S
+++ b/arch/arm/src/armv7-a/arm_testset.S
@@ -72,7 +72,7 @@
* Description:
* Perform an atomic test and set operation on the provided spinlock.
*
- * This function must be provided via the architecture-specific logoic.
+ * This function must be provided via the architecture-specific logic.
*
* Input Parameters:
* lock - The address of spinlock object (r0).
diff --git a/arch/arm/src/armv7-a/arm_unblocktask.c b/arch/arm/src/armv7-a/arm_unblocktask.c
index e3d2fa3fc79ca0597e0c23195b98320f00adf472..906d33796b69cdaeda7bc5284560705a5989f105 100644
--- a/arch/arm/src/armv7-a/arm_unblocktask.c
+++ b/arch/arm/src/armv7-a/arm_unblocktask.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-a/arm_unblocktask.c
*
- * Copyright (C) 2013-2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013-2015, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -61,7 +61,7 @@
* but has been prepped to execute. Move the TCB to the
* ready-to-run list, restore its context, and start execution.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to the tcb to be unblocked. This tcb is
* in one of the waiting tasks lists. It must be moved to
* the ready-to-run list and, if it is the highest priority
@@ -71,7 +71,20 @@
void up_unblock_task(struct tcb_s *tcb)
{
- struct tcb_s *rtcb = this_task();
+ struct tcb_s *rtcb;
+#ifdef CONFIG_SMP
+ int cpu;
+
+ /* Get the TCB of the currently executing task on this CPU (avoid using
+ * this_task() because the TCBs may be in an inappropriate state right
+ * now).
+ */
+
+ cpu = this_cpu();
+ rtcb = current_task(cpu);
+#else
+ rtcb = this_task();
+#endif
/* Verify that the context switch can be performed */
@@ -110,7 +123,11 @@ void up_unblock_task(struct tcb_s *tcb)
* of the ready-to-run task list.
*/
+#ifdef CONFIG_SMP
+ rtcb = current_task(cpu);
+#else
rtcb = this_task();
+#endif
/* Update scheduler parameters */
@@ -136,7 +153,11 @@ void up_unblock_task(struct tcb_s *tcb)
* ready-to-run task list.
*/
+#ifdef CONFIG_SMP
+ rtcb = current_task(cpu);
+#else
rtcb = this_task();
+#endif
#ifdef CONFIG_ARCH_ADDRENV
/* Make sure that the address environment for the previously
diff --git a/arch/arm/src/armv7-a/arm_vfork.S b/arch/arm/src/armv7-a/arm_vfork.S
index b7abc1c0f22a306161c9b7fa3f133510370e5857..2e10c9509903ba9242cbb763e09430d995371852 100644
--- a/arch/arm/src/armv7-a/arm_vfork.S
+++ b/arch/arm/src/armv7-a/arm_vfork.S
@@ -88,10 +88,10 @@
* 5) up_vfork() then calls task_vforkstart()
* 6) task_vforkstart() then executes the child thread.
*
- * Input Paremeters:
+ * Input Parameters:
* None
*
- * Return:
+ * Returned Value:
* Upon successful completion, vfork() returns 0 to the child process and
* returns the process ID of the child process to the parent process.
* Otherwise, -1 is returned to the parent, no child process is created,
diff --git a/arch/arm/src/armv7-a/crt0.c b/arch/arm/src/armv7-a/crt0.c
index a06e3f858e24bdeced0d4793a184f30f1228af88..f13148aa9b85669b19ef003b5ecd032f0144f79f 100644
--- a/arch/arm/src/armv7-a/crt0.c
+++ b/arch/arm/src/armv7-a/crt0.c
@@ -67,13 +67,13 @@ int main(int argc, char *argv[]);
* R4-R10 - static registers must be preserved
* R12-R14 - LR and SP must be preserved
*
- * Inputs:
+ * Input Parameters:
* R0 = sighand
* The address user-space signal handling function
* R1-R3 = signo, info, and ucontext
* Standard arguments to be passed to the signal handling function.
*
- * Return:
+ * Returned Value:
* None. This function does not return in the normal sense. It returns
* via the SYS_signal_handler_return (see svcall.h)
*
diff --git a/arch/arm/src/armv7-a/gic.h b/arch/arm/src/armv7-a/gic.h
index 8c882ad6ddc2c8711c978f0885c83fe11b8a9afa..0281abae6786ffd7b12775fa924c6a82c839a542 100644
--- a/arch/arm/src/armv7-a/gic.h
+++ b/arch/arm/src/armv7-a/gic.h
@@ -634,7 +634,7 @@ static inline unsigned int arm_gic_nlines(void)
* If CONFIG_SMP is not selected, the cpuset is ignored and SGI is sent
* only to the current CPU.
*
- * Input Paramters
+ * Input Parameters:
* sgi - The SGI interrupt ID (0-15)
* cpuset - The set of CPUs to receive the SGI
*
@@ -714,7 +714,7 @@ void arm_gic_initialize(void);
* Since this API is not supported on all architectures, it should be
* avoided in common implementations where possible.
*
- * Input Paramters:
+ * Input Parameters:
* irq - The interrupt request to modify.
* edge - False: Active HIGH level sensitive, True: Rising edge sensitive
*
@@ -735,7 +735,7 @@ int arm_gic_irq_trigger(int irq, bool edge);
* the irq number of the interrupt and then to call arm_doirq to dispatch
* the interrupt.
*
- * Input parameters:
+ * Input Parameters:
* regs - A pointer to the register save area on the stack.
*
****************************************************************************/
diff --git a/arch/arm/src/armv7-a/gtm.h b/arch/arm/src/armv7-a/gtm.h
index 347085f6737a8b6498d8b693c09e8c8f9cb5ebd0..4fa10f318418db5bd2bd4a51355ad764e30ebf9e 100644
--- a/arch/arm/src/armv7-a/gtm.h
+++ b/arch/arm/src/armv7-a/gtm.h
@@ -111,17 +111,6 @@ extern "C"
#define EXTERN extern
#endif
-/****************************************************************************
- * Name:
- *
- * Description:
- *
- * Input Parameters:
- *
- * Returned Value:
- *
- ****************************************************************************/
-
/* Clocking:
* CLK - This is the main clock of the Cortex-A9 processor. All Cortex-A9
* processors in the Cortex-A9 MPCore processor and the SCU are clocked
diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h
index c6338d33378b30395f574085ac6aac80ed98a4f6..ba0870c235234c8b736337948ca14916290978a0 100644
--- a/arch/arm/src/armv7-a/mmu.h
+++ b/arch/arm/src/armv7-a/mmu.h
@@ -897,7 +897,7 @@ struct section_mapping_s
* Description:
* Disable the MMU
*
- * Inputs:
+ * Input Parameters:
* None
*
************************************************************************************/
@@ -919,7 +919,7 @@ struct section_mapping_s
* instruction that performs the operation. Software does not have to write a
* value to the register before issuing the MCR instruction.
*
- * Inputs:
+ * Input Parameters:
* None
*
************************************************************************************/
@@ -934,7 +934,7 @@ struct section_mapping_s
* Description:
* Invalidate unified TLB entry by MVA all ASID Inner Shareable
*
- * Inputs:
+ * Input Parameters:
* vaddr - The virtual address to be invalidated
*
************************************************************************************/
@@ -952,7 +952,7 @@ struct section_mapping_s
* Description:
* Write the Domain Access Control Register (DACR)
*
- * Inputs:
+ * Input Parameters:
* dacr - The new value of the DACR
*
************************************************************************************/
@@ -979,7 +979,7 @@ struct section_mapping_s
* Table Base Register 0 (TTBR0). Then it clears the TTB control
* register (TTBCR), indicating that we are using TTBR0.
*
- * Inputs:
+ * Input Parameters:
* ttb - The new value of the TTBR0 register
*
************************************************************************************/
@@ -1012,7 +1012,7 @@ struct section_mapping_s
* ldr r3, =MMUFLAGS <-- L2 MMU flags
* pg_l2map r0, r1, r2, r3, r4
*
- * Inputs:
+ * Input Parameters:
* l2 - Physical or virtual start address in the L2 page table, depending
* upon the context. (modified)
* ppage - The physical address of the start of the region to span. Must
@@ -1083,7 +1083,7 @@ struct section_mapping_s
* ldr r4, =MMU_L1_PGTABFLAGS <-- L1 MMU flags
* pg_l1span r0, r1, r2, r3, r4, r4
*
- * Inputs (unmodified unless noted):
+ * Input Parameters (unmodified unless noted):
* l1 - Physical or virtual address in the L1 table to begin writing (modified)
* l2 - Physical start address in the L2 page table (modified)
* npages - Number of pages to required to span that memory region (modified)
@@ -1097,7 +1097,7 @@ struct section_mapping_s
* ppage - After the first page, this will be the full number of pages.
* tmp - scratch
*
- * Return:
+ * Returned Value:
* Nothing of interest.
*
* Assumptions:
@@ -1159,7 +1159,7 @@ struct section_mapping_s
* Description:
* Disable the MMU
*
- * Inputs:
+ * Input Parameters:
* None
*
************************************************************************************/
@@ -1188,7 +1188,7 @@ static inline void cp15_disable_mmu(void)
* instruction that performs the operation. Software does not have to write a
* value to the register before issuing the MCR instruction.
*
- * Inputs:
+ * Input Parameters:
* None
*
************************************************************************************/
@@ -1210,7 +1210,7 @@ static inline void cp15_invalidate_tlbs(void)
* Description:
* Invalidate unified TLB entry by MVA all ASID Inner Shareable
*
- * Inputs:
+ * Input Parameters:
* vaddr - The virtual address to be invalidated
*
************************************************************************************/
@@ -1235,7 +1235,7 @@ static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr)
* Description:
* Write the Domain Access Control Register (DACR)
*
- * Inputs:
+ * Input Parameters:
* dacr - The new value of the DACR
*
************************************************************************************/
@@ -1269,7 +1269,7 @@ static inline void cp15_wrdacr(unsigned int dacr)
* Table Base Register 0 (TTBR0). Then it clears the TTB control
* register (TTBCR), indicating that we are using TTBR0.
*
- * Inputs:
+ * Input Parameters:
* ttb - The new value of the TTBR0 register
*
************************************************************************************/
diff --git a/arch/arm/src/armv7-a/smp.h b/arch/arm/src/armv7-a/smp.h
index 7c9d1cc72af68cd3678a4718cd6037a0077ee532..1ae2bbfad8f8552f51ef428167a8b4d7d8a08440 100644
--- a/arch/arm/src/armv7-a/smp.h
+++ b/arch/arm/src/armv7-a/smp.h
@@ -93,7 +93,7 @@ extern uint32_t g_cpu3_idlestack[SMP_STACK_WORDS];
*
* These functions are provided by the common ARMv7-A logic.
*
- * Input parameters:
+ * Input Parameters:
* None
*
* Returned Value:
@@ -129,7 +129,7 @@ void __cpu3_start(void);
* This function must be provided by the each ARMv7-A MCU and implement
* MCU-specific initialization logic.
*
- * Input parameters:
+ * Input Parameters:
* cpu - The CPU index. This is the same value that would be obtained by
* calling up_cpu_index();
*
diff --git a/arch/arm/src/armv7-m/gnu/up_fetchadd.S b/arch/arm/src/armv7-m/gnu/up_fetchadd.S
new file mode 100644
index 0000000000000000000000000000000000000000..143c38e5163234965cceb3971e7ef0d39108a9c1
--- /dev/null
+++ b/arch/arm/src/armv7-m/gnu/up_fetchadd.S
@@ -0,0 +1,257 @@
+/****************************************************************************
+ * arch/arm/src/armv7-m/gnu/up_fetchadd.S
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+ .syntax unified
+ .thumb
+ .file "up_fetchadd.S"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+ .text
+
+/****************************************************************************
+ * Name: up_fetchadd32
+ *
+ * Description:
+ * Perform an atomic fetch add operation on the provided 32-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 32-bit value to be incremented.
+ * value - The 32-bit addend
+ *
+ * Returned Value:
+ * The incremented value (volatile!)
+ *
+ ****************************************************************************/
+
+ .globl up_fetchadd32
+ .type up_fetchadd32, %function
+
+up_fetchadd32:
+
+1:
+ ldrex r2, [r0] /* Fetch the value to be incremented */
+ add r2, r2, r1 /* Add the addend */
+
+ strex r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strex failed */
+ bne 1b /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the incremented value */
+ bx lr /* Successful! */
+ .size up_fetchadd32, . - up_fetchadd32
+
+/****************************************************************************
+ * Name: up_fetchsub32
+ *
+ * Description:
+ * Perform an atomic fetch subtract operation on the provided 32-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 32-bit value to be decremented.
+ * value - The 32-bit subtrahend
+ *
+ * Returned Value:
+ * The decremented value (volatile!)
+ *
+ ****************************************************************************/
+
+ .globl up_fetchsub32
+ .type up_fetchsub32, %function
+
+up_fetchsub32:
+
+1:
+ ldrex r2, [r0] /* Fetch the value to be decremented */
+ sub r2, r2, r1 /* Subtract the subtrahend */
+
+ strex r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strex failed */
+ bne 1b /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the decremented value */
+ bx lr /* Successful! */
+ .size up_fetchsub32, . - up_fetchsub32
+
+/****************************************************************************
+ * Name: up_fetchadd16
+ *
+ * Description:
+ * Perform an atomic fetch add operation on the provided 16-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 16-bit value to be incremented.
+ * value - The 16-bit addend
+ *
+ * Returned Value:
+ * The incremented value (volatile!)
+ *
+ ****************************************************************************/
+
+ .globl up_fetchadd16
+ .type up_fetchadd16, %function
+
+up_fetchadd16:
+
+1:
+ ldrexh r2, [r0] /* Fetch the value to be incremented */
+ add r2, r2, r1 /* Add the addend */
+
+ strexh r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strexh failed */
+ bne 1b /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the incremented value */
+ bx lr /* Successful! */
+ .size up_fetchadd16, . - up_fetchadd16
+
+/****************************************************************************
+ * Name: up_fetchsub16
+ *
+ * Description:
+ * Perform an atomic fetch subtract operation on the provided 16-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 16-bit value to be decremented.
+ * value - The 16-bit subtrahend
+ *
+ * Returned Value:
+ * The decremented value (volatile!)
+ *
+ ****************************************************************************/
+
+ .globl up_fetchsub16
+ .type up_fetchsub16, %function
+
+up_fetchsub16:
+
+1:
+ ldrexh r2, [r0] /* Fetch the value to be decremented */
+ sub r2, r2, r1 /* Subtract the subtrahend */
+
+ /* Attempt to save the decremented value */
+
+ strexh r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strexh failed */
+ bne 1b /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the decremented value */
+ bx lr /* Successful! */
+ .size up_fetchsub16, . - up_fetchsub16
+
+/****************************************************************************
+ * Name: up_fetchadd8
+ *
+ * Description:
+ * Perform an atomic fetch add operation on the provided 8-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 8-bit value to be incremented.
+ * value - The 8-bit addend
+ *
+ * Returned Value:
+ * The incremented value (volatile!)
+ *
+ ****************************************************************************/
+
+ .globl up_fetchadd8
+ .type up_fetchadd8, %function
+
+up_fetchadd8:
+
+1:
+ ldrexb r2, [r0] /* Fetch the value to be incremented */
+ add r2, r2, r1 /* Add the addend */
+
+ strexb r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strexb failed */
+ bne 1b /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the incremented value */
+ bx lr /* Successful! */
+ .size up_fetchadd8, . - up_fetchadd8
+
+/****************************************************************************
+ * Name: up_fetchsub8
+ *
+ * Description:
+ * Perform an atomic fetch subtract operation on the provided 8-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 8-bit value to be decremented.
+ * value - The 8-bit subtrahend
+ *
+ * Returned Value:
+ * The decremented value (volatile!)
+ *
+ ****************************************************************************/
+
+ .globl up_fetchsub8
+ .type up_fetchsub8, %function
+
+up_fetchsub8:
+
+1:
+ ldrexb r2, [r0] /* Fetch the value to be decremented */
+ sub r2, r2, r1 /* Subtract the subtrahend */
+
+ strexb r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strexb failed */
+ bne 1b /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the decremented value */
+ bx lr /* Successful! */
+ .size up_fetchsub8, . - up_fetchsub8
+ .end
diff --git a/arch/arm/src/armv7-m/gnu/up_fullcontextrestore.S b/arch/arm/src/armv7-m/gnu/up_fullcontextrestore.S
index a9ccb0d572c0b9208e25fb3365382d0e1b4436fd..7b5171a449218b47c780853efb54058bfac941a2 100644
--- a/arch/arm/src/armv7-m/gnu/up_fullcontextrestore.S
+++ b/arch/arm/src/armv7-m/gnu/up_fullcontextrestore.S
@@ -71,7 +71,7 @@
*
* void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
*
- * Return:
+ * Returned Value:
* None
*
************************************************************************************/
diff --git a/arch/arm/src/armv7-m/gnu/up_saveusercontext.S b/arch/arm/src/armv7-m/gnu/up_saveusercontext.S
index 7ebd2e4836a79d94b77c5cbfcd73e86fa444377f..a4d96ef8fa5fa1a3ff6813675b85af155ab877a0 100644
--- a/arch/arm/src/armv7-m/gnu/up_saveusercontext.S
+++ b/arch/arm/src/armv7-m/gnu/up_saveusercontext.S
@@ -71,7 +71,7 @@
*
* int up_saveusercontext(uint32_t *saveregs);
*
- * Return:
+ * Returned Value:
* 0: Normal return
* 1: Context switch return
*
diff --git a/arch/arm/src/armv7-m/gnu/up_signal_handler.S b/arch/arm/src/armv7-m/gnu/up_signal_handler.S
index 2cc31da4d19fe67be41c4caf0ce4a97d16e6b098..daf9448c14e2e3e79b67cbb9918702774c9a5269 100644
--- a/arch/arm/src/armv7-m/gnu/up_signal_handler.S
+++ b/arch/arm/src/armv7-m/gnu/up_signal_handler.S
@@ -71,13 +71,13 @@
* R4-R10 - static registers must be preserved
* R12-R14 - LR and SP must be preserved
*
- * Inputs:
+ * Input Parameters:
* R0 = sighand
* The address user-space signal handling function
* R1-R3 = signo, info, and ucontext
* Standard arguments to be passed to the signal handling function.
*
- * Return:
+ * Returned Value:
* None. This function does not return in the normal sense. It returns
* via the SYS_signal_handler_return (see svcall.h)
*
diff --git a/arch/arm/src/armv7-m/gnu/up_switchcontext.S b/arch/arm/src/armv7-m/gnu/up_switchcontext.S
index c0ddf151627c485681cdbfc39ee167b908a02c51..7c72411d3e5a16d60f65e8ea3a64ff69f1060cb3 100644
--- a/arch/arm/src/armv7-m/gnu/up_switchcontext.S
+++ b/arch/arm/src/armv7-m/gnu/up_switchcontext.S
@@ -72,7 +72,7 @@
*
* void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs);
*
- * Return:
+ * Returned Value:
* None
*
************************************************************************************/
diff --git a/arch/arm/src/armv7-m/gnu/up_testset.S b/arch/arm/src/armv7-m/gnu/up_testset.S
index c1888c56a98fcc5a64381b053c0e8903c585c65e..10929b0780da3c1b60a356eb929e632446f99b6a 100644
--- a/arch/arm/src/armv7-m/gnu/up_testset.S
+++ b/arch/arm/src/armv7-m/gnu/up_testset.S
@@ -74,7 +74,7 @@
* Description:
* Perform an atomic test and set operation on the provided spinlock.
*
- * This function must be provided via the architecture-specific logoic.
+ * This function must be provided via the architecture-specific logic.
*
* Input Parameters:
* lock - The address of spinlock object.
diff --git a/arch/arm/src/armv7-m/gnu/vfork.S b/arch/arm/src/armv7-m/gnu/vfork.S
index 784ab83ce7b065113b69dd7a3dd48c780ff2644b..fa3cfc1bea621d6116d863378b479c5b12218400 100644
--- a/arch/arm/src/armv7-m/gnu/vfork.S
+++ b/arch/arm/src/armv7-m/gnu/vfork.S
@@ -88,10 +88,10 @@
* 5) up_vfork() then calls task_vforkstart()
* 6) task_vforkstart() then executes the child thread.
*
- * Input Paremeters:
+ * Input Parameters:
* None
*
- * Return:
+ * Returned Value:
* Upon successful completion, vfork() returns 0 to the child process and returns
* the process ID of the child process to the parent process. Otherwise, -1 is
* returned to the parent, no child process is created, and errno is set to
diff --git a/arch/arm/src/armv7-m/iar/up_fetchadd.S b/arch/arm/src/armv7-m/iar/up_fetchadd.S
new file mode 100644
index 0000000000000000000000000000000000000000..f5db1837f642a69a2e17224b097b7ce2ce4f7fb0
--- /dev/null
+++ b/arch/arm/src/armv7-m/iar/up_fetchadd.S
@@ -0,0 +1,238 @@
+/****************************************************************************
+ * arch/arm/src/armv7-m/iar/up_fetchadd.S
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+ MODULE up_testset
+ SECTION .text:CODE:NOROOT(2)
+
+/****************************************************************************
+ * Public Symbols
+ ****************************************************************************/
+
+ PUBLIC up_fetchadd32
+ PUBLIC up_fetchsub32
+ PUBLIC up_fetchadd16
+ PUBLIC up_fetchsub16
+ PUBLIC up_fetchadd8
+ PUBLIC up_fetchsub8
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+ THUMB
+
+/****************************************************************************
+ * Name: up_fetchadd32
+ *
+ * Description:
+ * Perform an atomic fetch add operation on the provided 32-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 32-bit value to be incremented.
+ * value - The 32-bit addend
+ *
+ * Returned Value:
+ * The incremented value (volatile!)
+ *
+ ****************************************************************************/
+
+up_fetchadd32:
+
+ ldrex r2, [r0] /* Fetch the value to be incremented */
+ add r2, r2, r1 /* Add the addend */
+
+ strex r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strex failed */
+ bne up_fetchadd32 /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the incremented value */
+ bx lr /* Successful! */
+
+/****************************************************************************
+ * Name: up_fetchsub32
+ *
+ * Description:
+ * Perform an atomic fetch subtract operation on the provided 32-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 32-bit value to be decremented.
+ * value - The 32-bit subtrahend
+ *
+ * Returned Value:
+ * The decremented value (volatile!)
+ *
+ ****************************************************************************/
+
+up_fetchsub32:
+
+ ldrex r2, [r0] /* Fetch the value to be decremented */
+ sub r2, r2, r1 /* Subtract the subtrahend */
+
+ strex r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strex failed */
+ bne up_fetchsub32 /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the decremented value */
+ bx lr /* Successful! */
+
+/****************************************************************************
+ * Name: up_fetchadd16
+ *
+ * Description:
+ * Perform an atomic fetch add operation on the provided 16-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 16-bit value to be incremented.
+ * value - The 16-bit addend
+ *
+ * Returned Value:
+ * The incremented value (volatile!)
+ *
+ ****************************************************************************/
+
+up_fetchadd16:
+
+ ldrexh r2, [r0] /* Fetch the value to be incremented */
+ add r2, r2, r1 /* Add the addend */
+
+ strexh r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strexh failed */
+ bne up_fetchadd16 /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the incremented value */
+ bx lr /* Successful! */
+
+/****************************************************************************
+ * Name: up_fetchsub16
+ *
+ * Description:
+ * Perform an atomic fetch subtract operation on the provided 16-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 16-bit value to be decremented.
+ * value - The 16-bit subtrahend
+ *
+ * Returned Value:
+ * The decremented value (volatile!)
+ *
+ ****************************************************************************/
+
+up_fetchsub16:
+
+ ldrexh r2, [r0] /* Fetch the value to be decremented */
+ sub r2, r2, r1 /* Subtract the subtrahend */
+
+ /* Attempt to save the decremented value */
+
+ strexh r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strexh failed */
+ bne up_fetchsub16 /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the decremented value */
+ bx lr /* Successful! */
+
+/****************************************************************************
+ * Name: up_fetchadd8
+ *
+ * Description:
+ * Perform an atomic fetch add operation on the provided 8-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 8-bit value to be incremented.
+ * value - The 8-bit addend
+ *
+ * Returned Value:
+ * The incremented value (volatile!)
+ *
+ ****************************************************************************/
+
+up_fetchadd8:
+
+ ldrexb r2, [r0] /* Fetch the value to be incremented */
+ add r2, r2, r1 /* Add the addend */
+
+ strexb r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strexb failed */
+ bne up_fetchadd8 /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the incremented value */
+ bx lr /* Successful! */
+
+/****************************************************************************
+ * Name: up_fetchsub8
+ *
+ * Description:
+ * Perform an atomic fetch subtract operation on the provided 8-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 8-bit value to be decremented.
+ * value - The 8-bit subtrahend
+ *
+ * Returned Value:
+ * The decremented value (volatile!)
+ *
+ ****************************************************************************/
+
+up_fetchsub8:
+
+ ldrexb r2, [r0] /* Fetch the value to be decremented */
+ sub r2, r2, r1 /* Subtract the subtrahend */
+
+ strexb r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strexb failed */
+ bne up_fetchsub8 /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the decremented value */
+ bx lr /* Successful! */
+
+ END
diff --git a/arch/arm/src/armv7-m/iar/up_fullcontextrestore.S b/arch/arm/src/armv7-m/iar/up_fullcontextrestore.S
index 045c903a32ade7ae13a05f8fd18031233a6186ac..034bbfc8e845f7f1ec32c4765290f3b8c10c78cb 100644
--- a/arch/arm/src/armv7-m/iar/up_fullcontextrestore.S
+++ b/arch/arm/src/armv7-m/iar/up_fullcontextrestore.S
@@ -72,7 +72,7 @@
*
* void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
*
- * Return:
+ * Returned Value:
* None
*
************************************************************************************/
diff --git a/arch/arm/src/armv7-m/iar/up_saveusercontext.S b/arch/arm/src/armv7-m/iar/up_saveusercontext.S
index b8f27a7772cbac54ea11701e5337a2c2f3e439e3..07a82c620ae9323a066bc6b93b9a74a6c6213989 100644
--- a/arch/arm/src/armv7-m/iar/up_saveusercontext.S
+++ b/arch/arm/src/armv7-m/iar/up_saveusercontext.S
@@ -72,7 +72,7 @@
*
* int up_saveusercontext(uint32_t *saveregs);
*
- * Return:
+ * Returned Value:
* 0: Normal return
* 1: Context switch return
*
diff --git a/arch/arm/src/armv7-m/iar/up_switchcontext.S b/arch/arm/src/armv7-m/iar/up_switchcontext.S
index 5936503d73fe27c3ce9516f4fa2bd209de95c945..a115a498bf0e8ce6d9dd71b89e32138579119407 100644
--- a/arch/arm/src/armv7-m/iar/up_switchcontext.S
+++ b/arch/arm/src/armv7-m/iar/up_switchcontext.S
@@ -73,7 +73,7 @@
*
* void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs);
*
- * Return:
+ * Returned Value:
* None
*
************************************************************************************/
diff --git a/arch/arm/src/armv7-m/iar/up_testset.S b/arch/arm/src/armv7-m/iar/up_testset.S
index e690aed3de9d7f6ae88d9374e67b6f71d04d32ae..72874dff3367b03ea415c1a09e8f570e58df7918 100644
--- a/arch/arm/src/armv7-m/iar/up_testset.S
+++ b/arch/arm/src/armv7-m/iar/up_testset.S
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/armv7-m/gnu/up_testset.S
+ * arch/arm/src/armv7-m/iar/up_testset.S
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -59,7 +59,7 @@
* Description:
* Perform an atomic test and set operation on the provided spinlock.
*
- * This function must be provided via the architecture-specific logoic.
+ * This function must be provided via the architecture-specific logic.
*
* Input Parameters:
* lock - The address of spinlock object.
diff --git a/arch/arm/src/armv7-m/iar/vfork.S b/arch/arm/src/armv7-m/iar/vfork.S
index 6018a28a00a7bda8d1f6177d865f9a234cbd6fd9..e7352aee1ee18b857feb532416d4432de0c64493 100644
--- a/arch/arm/src/armv7-m/iar/vfork.S
+++ b/arch/arm/src/armv7-m/iar/vfork.S
@@ -89,10 +89,10 @@
* 5) up_vfork() then calls task_vforkstart()
* 6) task_vforkstart() then executes the child thread.
*
- * Input Paremeters:
+ * Input Parameters:
* None
*
- * Return:
+ * Returned Value:
* Upon successful completion, vfork() returns 0 to the child process and returns
* the process ID of the child process to the parent process. Otherwise, -1 is
* returned to the parent, no child process is created, and errno is set to
diff --git a/arch/arm/src/armv7-m/up_blocktask.c b/arch/arm/src/armv7-m/up_blocktask.c
index 5e62e0fb9fc3c4d9e021e4087560d84ad1efbed1..68151cb09b38cf6ce4330079c30f93511d43c2b8 100644
--- a/arch/arm/src/armv7-m/up_blocktask.c
+++ b/arch/arm/src/armv7-m/up_blocktask.c
@@ -61,7 +61,7 @@
* the ready to run list must be stopped. Save its context
* and move it to the inactive list specified by task_state.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to a task in the ready-to-run list (normally
* the task at the head of the list). It most be
* stopped, its context saved and moved into one of the
diff --git a/arch/arm/src/armv7-m/up_reprioritizertr.c b/arch/arm/src/armv7-m/up_reprioritizertr.c
index 5e65a3d33837b16d3928614b6fbd726d2009b34d..22c80ed298ebaeee8833fc179a233a042fb6f095 100644
--- a/arch/arm/src/armv7-m/up_reprioritizertr.c
+++ b/arch/arm/src/armv7-m/up_reprioritizertr.c
@@ -67,7 +67,7 @@
* the priority of the current, running task and it now has the
* priority.
*
- * Inputs:
+ * Input Parameters:
* tcb: The TCB of the task that has been reprioritized
* priority: The new task priority
*
diff --git a/arch/arm/src/armv7-m/up_schedulesigaction.c b/arch/arm/src/armv7-m/up_schedulesigaction.c
index 42aa2932ba64ce13f56a3ef67af8512a83780ba1..698b8a3c2c945c949d9e6f830c51fcc196e9545c 100644
--- a/arch/arm/src/armv7-m/up_schedulesigaction.c
+++ b/arch/arm/src/armv7-m/up_schedulesigaction.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-m/up_schedulesigaction.c
*
- * Copyright (C) 2009-2014, 2016-2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009-2014, 2016-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -118,7 +118,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
if (tcb == this_task())
{
/* CASE 1: We are not in an interrupt handler and a task is
- * signalling itself for some reason.
+ * signaling itself for some reason.
*/
if (!CURRENT_REGS)
@@ -176,9 +176,9 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
}
}
- /* Otherwise, we are (1) signalling a task is not running from an
+ /* Otherwise, we are (1) signaling a task is not running from an
* interrupt handler or (2) we are not in an interrupt handler and the
- * running task is signalling* some non-running task.
+ * running task is signaling* some non-running task.
*/
else
@@ -250,7 +250,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
cpu = tcb->cpu;
/* CASE 1: We are not in an interrupt handler and a task is
- * signalling itself for some reason.
+ * signaling itself for some reason.
*/
if (cpu == me && !CURRENT_REGS)
@@ -266,60 +266,45 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* CPU. In the former case, we will have to PAUSE the other CPU
* first. But in either case, we will have to modify the return
* state as well as the state in the TCB.
- *
- * Hmmm... there looks like a latent bug here: The following logic
- * would fail in the strange case where we are in an interrupt
- * handler, the thread is signalling itself, but a context switch
- * to another task has occurred so that CURRENT_REGS does not
- * refer to the thread of this_task()!
*/
else
{
- /* If we signalling a task running on the other CPU, we have
+ /* If we signaling a task running on the other CPU, we have
* to PAUSE the other CPU.
*/
if (cpu != me)
{
+ /* Pause the CPU */
+
up_cpu_pause(cpu);
- }
- /* Save the return PC, CPSR and either the BASEPRI or PRIMASK
- * registers (and perhaps also the LR). These will be
- * restored by the signal trampoline after the signal has been
- * delivered.
- */
+ /* Wait while the pause request is pending */
- tcb->xcp.sigdeliver = (FAR void *)sigdeliver;
- tcb->xcp.saved_pc = CURRENT_REGS[REG_PC];
+ while (up_cpu_pausereq(cpu))
+ {
+ }
+
+ /* Now tcb on the other CPU can be accessed safely */
+
+ /* Copy tcb->xcp.regs to tcp.xcp.saved. These will be restored
+ * by the signal trampoline after the signal has been delivered.
+ */
+
+ tcb->xcp.sigdeliver = (FAR void *)sigdeliver;
+ tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC];
#ifdef CONFIG_ARMV7M_USEBASEPRI
- tcb->xcp.saved_basepri = CURRENT_REGS[REG_BASEPRI];
+ tcb->xcp.saved_basepri = tcb->xcp.regs[REG_BASEPRI];
#else
- tcb->xcp.saved_primask = CURRENT_REGS[REG_PRIMASK];
+ tcb->xcp.saved_primask = tcb->xcp.regs[REG_PRIMASK];
#endif
- tcb->xcp.saved_xpsr = CURRENT_REGS[REG_XPSR];
+ tcb->xcp.saved_xpsr = tcb->xcp.regs[REG_XPSR];
#ifdef CONFIG_BUILD_PROTECTED
- tcb->xcp.saved_lr = CURRENT_REGS[REG_LR];
+ tcb->xcp.saved_lr = tcb->xcp.regs[REG_LR];
#endif
- /* Increment the IRQ lock count so that when the task is restarted,
- * it will hold the IRQ spinlock.
- */
-
- DEBUGASSERT(tcb->irqcount < INT16_MAX);
- tcb->irqcount++;
- /* Handle a possible race condition where the TCB was suspended
- * just before we paused the other CPU. The critical section
- * established above will prevent new threads from running on
- * that CPU, but it will not guarantee that the running thread
- * did not suspend itself (allowing any threads "assigned" to
- * the CPU to run).
- */
-
- if (tcb->task_state != TSTATE_TASK_RUNNING)
- {
- /* Then set up to vector to the trampoline with interrupts
+ /* Then set up vector to the trampoline with interrupts
* disabled. We must already be in privileged thread mode
* to be here.
*/
@@ -337,8 +322,29 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
}
else
{
- /* Then set up to vector to the trampoline with interrupts
- * disabled
+ /* tcb is running on the same CPU */
+
+ /* Save the return PC, CPSR and either the BASEPRI or PRIMASK
+ * registers (and perhaps also the LR). These will be
+ * restored by the signal trampoline after the signal has been
+ * delivered.
+ */
+
+ tcb->xcp.sigdeliver = (FAR void *)sigdeliver;
+ tcb->xcp.saved_pc = CURRENT_REGS[REG_PC];
+#ifdef CONFIG_ARMV7M_USEBASEPRI
+ tcb->xcp.saved_basepri = CURRENT_REGS[REG_BASEPRI];
+#else
+ tcb->xcp.saved_primask = CURRENT_REGS[REG_PRIMASK];
+#endif
+ tcb->xcp.saved_xpsr = CURRENT_REGS[REG_XPSR];
+#ifdef CONFIG_BUILD_PROTECTED
+ tcb->xcp.saved_lr = CURRENT_REGS[REG_LR];
+#endif
+
+ /* Then set up vector to the trampoline with interrupts
+ * disabled. The kernel-space trampoline must run in
+ * privileged thread mode.
*/
CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
@@ -351,15 +357,6 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
#ifdef CONFIG_BUILD_PROTECTED
CURRENT_REGS[REG_LR] = EXC_RETURN_PRIVTHR;
#endif
- /* In an SMP configuration, the interrupt disable logic also
- * involves spinlocks that are configured per the TCB irqcount
- * field. This is logically equivalent to enter_critical_section().
- * The matching call to leave_critical_section() will be
- * performed in up_sigdeliver().
- */
-
- spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock,
- &g_cpu_irqlock);
/* And make sure that the saved context in the TCB is the same
* as the interrupt return context.
@@ -368,6 +365,24 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
up_savestate(tcb->xcp.regs);
}
+ /* Increment the IRQ lock count so that when the task is restarted,
+ * it will hold the IRQ spinlock.
+ */
+
+ DEBUGASSERT(tcb->irqcount < INT16_MAX);
+ tcb->irqcount++;
+
+ /* In an SMP configuration, the interrupt disable logic also
+ * involves spinlocks that are configured per the TCB irqcount
+ * field. This is logically equivalent to enter_critical_section().
+ * The matching call to leave_critical_section() will be
+ * performed in up_sigdeliver().
+ */
+
+ spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock,
+ &g_cpu_irqlock);
+
+
/* RESUME the other CPU if it was PAUSED */
if (cpu != me)
@@ -379,7 +394,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
/* Otherwise, we are (1) signaling a task is not running from an
* interrupt handler or (2) we are not in an interrupt handler and the
- * running task is signalling some other non-running task.
+ * running task is signaling some other non-running task.
*/
else
diff --git a/arch/arm/src/armv7-m/up_signal_dispatch.c b/arch/arm/src/armv7-m/up_signal_dispatch.c
index 9ec7d151529ca35f84e4dc939165e35f8882d9a5..63f2c56fc8215fc1f4989c3bb0eeaa69ed13f386 100644
--- a/arch/arm/src/armv7-m/up_signal_dispatch.c
+++ b/arch/arm/src/armv7-m/up_signal_dispatch.c
@@ -60,18 +60,18 @@
* This kernel-mode stub will then be called transfer control to the user
* mode signal handler by calling this function.
*
- * Normally the a user-mode signalling handling stub will also execute
+ * Normally the a user-mode signaling handling stub will also execute
* before the ultimate signal handler is called. See
* arch/arm/src/armv[6\7]/up_signal_handler. This function is the
* user-space, signal handler trampoline function. It is called from
* up_signal_dispatch() in user-mode.
*
- * Inputs:
+ * Input Parameters:
* sighand - The address user-space signal handling function
* signo, info, and ucontext - Standard arguments to be passed to the
* signal handling function.
*
- * Return:
+ * Returned Value:
* None. This function does not return in the normal sense. It returns
* via an architecture specific system call made by up_signal_handler().
* However, this will look like a normal return by the caller of
diff --git a/arch/arm/src/armv7-m/up_unblocktask.c b/arch/arm/src/armv7-m/up_unblocktask.c
index 3c9ae8df14780afc49037b67f6666882c72dcffc..7ecbbd0e577f5b2defbd8d2a9f4db8d50420a90f 100644
--- a/arch/arm/src/armv7-m/up_unblocktask.c
+++ b/arch/arm/src/armv7-m/up_unblocktask.c
@@ -60,7 +60,7 @@
* but has been prepped to execute. Move the TCB to the
* ready-to-run list, restore its context, and start execution.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to the tcb to be unblocked. This tcb is
* in one of the waiting tasks lists. It must be moved to
* the ready-to-run list and, if it is the highest priority
diff --git a/arch/arm/src/armv7-r/arm_blocktask.c b/arch/arm/src/armv7-r/arm_blocktask.c
index 58cefee3cfe8a4e88fcf9b61b05dddcdc1e0fc1d..c35093df074d85d5b30170d70a91830067208a65 100644
--- a/arch/arm/src/armv7-r/arm_blocktask.c
+++ b/arch/arm/src/armv7-r/arm_blocktask.c
@@ -62,7 +62,7 @@
* the ready to run list must be stopped. Save its context
* and move it to the inactive list specified by task_state.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to a task in the ready-to-run list (normally
* the task at the head of the list). It most be
* stopped, its context saved and moved into one of the
diff --git a/arch/arm/src/armv7-r/arm_dataabort.c b/arch/arm/src/armv7-r/arm_dataabort.c
index 52f5d124365dbe84f502b6f133721e76e174faa2..f5939f80e5fa68ec80d1fa0d6df91527295ab636 100644
--- a/arch/arm/src/armv7-r/arm_dataabort.c
+++ b/arch/arm/src/armv7-r/arm_dataabort.c
@@ -54,7 +54,7 @@
/****************************************************************************
* Name: arm_dataabort
*
- * Input parameters:
+ * Input Parameters:
* regs - The standard, ARM register save array.
* dfar - Fault address register.
* dfsr - Fault status register.
diff --git a/arch/arm/src/armv7-r/arm_fetchadd.S b/arch/arm/src/armv7-r/arm_fetchadd.S
new file mode 100644
index 0000000000000000000000000000000000000000..77f661b98489def3fc00b135b174a8114fd7ba68
--- /dev/null
+++ b/arch/arm/src/armv7-r/arm_fetchadd.S
@@ -0,0 +1,255 @@
+/****************************************************************************
+ * arch/arm/src/armv7-r/up_fetchadd.S
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+ .file "arm_fetchadd.S"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+ .text
+
+/****************************************************************************
+ * Name: up_fetchadd32
+ *
+ * Description:
+ * Perform an atomic fetch add operation on the provided 32-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 32-bit value to be incremented.
+ * value - The 32-bit addend
+ *
+ * Returned Value:
+ * The incremented value (volatile!)
+ *
+ ****************************************************************************/
+
+ .globl up_fetchadd32
+ .type up_fetchadd32, %function
+
+up_fetchadd32:
+
+1:
+ ldrex r2, [r0] /* Fetch the value to be incremented */
+ add r2, r2, r1 /* Add the addend */
+
+ strex r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strex failed */
+ bne 1b /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the incremented value */
+ bx lr /* Successful! */
+ .size up_fetchadd32, . - up_fetchadd32
+
+/****************************************************************************
+ * Name: up_fetchsub32
+ *
+ * Description:
+ * Perform an atomic fetch subtract operation on the provided 32-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 32-bit value to be decremented.
+ * value - The 32-bit subtrahend
+ *
+ * Returned Value:
+ * The decremented value (volatile!)
+ *
+ ****************************************************************************/
+
+ .globl up_fetchsub32
+ .type up_fetchsub32, %function
+
+up_fetchsub32:
+
+1:
+ ldrex r2, [r0] /* Fetch the value to be decremented */
+ sub r2, r2, r1 /* Subtract the subtrahend */
+
+ strex r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strex failed */
+ bne 1b /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the decremented value */
+ bx lr /* Successful! */
+ .size up_fetchsub32, . - up_fetchsub32
+
+/****************************************************************************
+ * Name: up_fetchadd16
+ *
+ * Description:
+ * Perform an atomic fetch add operation on the provided 16-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 16-bit value to be incremented.
+ * value - The 16-bit addend
+ *
+ * Returned Value:
+ * The incremented value (volatile!)
+ *
+ ****************************************************************************/
+
+ .globl up_fetchadd16
+ .type up_fetchadd16, %function
+
+up_fetchadd16:
+
+1:
+ ldrexh r2, [r0] /* Fetch the value to be incremented */
+ add r2, r2, r1 /* Add the addend */
+
+ strexh r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strexh failed */
+ bne 1b /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the incremented value */
+ bx lr /* Successful! */
+ .size up_fetchadd16, . - up_fetchadd16
+
+/****************************************************************************
+ * Name: up_fetchsub16
+ *
+ * Description:
+ * Perform an atomic fetch subtract operation on the provided 16-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 16-bit value to be decremented.
+ * value - The 16-bit subtrahend
+ *
+ * Returned Value:
+ * The decremented value (volatile!)
+ *
+ ****************************************************************************/
+
+ .globl up_fetchsub16
+ .type up_fetchsub16, %function
+
+up_fetchsub16:
+
+1:
+ ldrexh r2, [r0] /* Fetch the value to be decremented */
+ sub r2, r2, r1 /* Subtract the subtrahend */
+
+ /* Attempt to save the decremented value */
+
+ strexh r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strexh failed */
+ bne 1b /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the decremented value */
+ bx lr /* Successful! */
+ .size up_fetchsub16, . - up_fetchsub16
+
+/****************************************************************************
+ * Name: up_fetchadd8
+ *
+ * Description:
+ * Perform an atomic fetch add operation on the provided 8-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 8-bit value to be incremented.
+ * value - The 8-bit addend
+ *
+ * Returned Value:
+ * The incremented value (volatile!)
+ *
+ ****************************************************************************/
+
+ .globl up_fetchadd8
+ .type up_fetchadd8, %function
+
+up_fetchadd8:
+
+1:
+ ldrexb r2, [r0] /* Fetch the value to be incremented */
+ add r2, r2, r1 /* Add the addend */
+
+ strexb r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strexb failed */
+ bne 1b /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the incremented value */
+ bx lr /* Successful! */
+ .size up_fetchadd8, . - up_fetchadd8
+
+/****************************************************************************
+ * Name: up_fetchsub8
+ *
+ * Description:
+ * Perform an atomic fetch subtract operation on the provided 8-bit value.
+ *
+ * This function must be provided via the architecture-specific logic.
+ *
+ * Input Parameters:
+ * addr - The address of 8-bit value to be decremented.
+ * value - The 8-bit subtrahend
+ *
+ * Returned Value:
+ * The decremented value (volatile!)
+ *
+ ****************************************************************************/
+
+ .globl up_fetchsub8
+ .type up_fetchsub8, %function
+
+up_fetchsub8:
+
+1:
+ ldrexb r2, [r0] /* Fetch the value to be decremented */
+ sub r2, r2, r1 /* Subtract the subtrahend */
+
+ strexb r3, r2, [r0] /* Attempt to save the result */
+ teq r3, #0 /* r2 will be 1 is strexb failed */
+ bne 1b /* Failed to lock... try again */
+
+ mov r0, r2 /* Return the decremented value */
+ bx lr /* Successful! */
+ .size up_fetchsub8, . - up_fetchsub8
+ .end
diff --git a/arch/arm/src/armv7-r/arm_fullcontextrestore.S b/arch/arm/src/armv7-r/arm_fullcontextrestore.S
index 06daa2218262b5b223219b0f85450e505786911e..9de8e405b75dc918a91d4cca1087e4fcbbc23be5 100644
--- a/arch/arm/src/armv7-r/arm_fullcontextrestore.S
+++ b/arch/arm/src/armv7-r/arm_fullcontextrestore.S
@@ -75,7 +75,7 @@
*
* void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
*
- * Return:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/armv7-r/arm_prefetchabort.c b/arch/arm/src/armv7-r/arm_prefetchabort.c
index 74713f5ad3eae3be527be24885bab7aaea3df460..7d5fd7cd86a1899a89abdd5527532931e4648093 100644
--- a/arch/arm/src/armv7-r/arm_prefetchabort.c
+++ b/arch/arm/src/armv7-r/arm_prefetchabort.c
@@ -54,7 +54,7 @@
/****************************************************************************
* Name: arm_prefetchabort
*
- * Description;
+ * Description:
* This is the prefetch abort exception handler. The ARM prefetch abort
* exception occurs when a memory fault is detected during an an
* instruction fetch.
diff --git a/arch/arm/src/armv7-r/arm_reprioritizertr.c b/arch/arm/src/armv7-r/arm_reprioritizertr.c
index db96424eb2f4d6042c672334f327784d4fcecbee..85b8ee22c0ce42ff51f77ab2d4e765ff25923669 100644
--- a/arch/arm/src/armv7-r/arm_reprioritizertr.c
+++ b/arch/arm/src/armv7-r/arm_reprioritizertr.c
@@ -68,7 +68,7 @@
* the priority of the current, running task and it now has the
* priority.
*
- * Inputs:
+ * Input Parameters:
* tcb: The TCB of the task that has been reprioritized
* priority: The new task priority
*
diff --git a/arch/arm/src/armv7-r/arm_signal_dispatch.c b/arch/arm/src/armv7-r/arm_signal_dispatch.c
index 5fa1b3a647769ae46991415dd56ee175ac3576a3..c09c1481b6c0b445e30ae5494e9712ee0a8c684f 100644
--- a/arch/arm/src/armv7-r/arm_signal_dispatch.c
+++ b/arch/arm/src/armv7-r/arm_signal_dispatch.c
@@ -79,12 +79,12 @@
* user-space, signal handler trampoline function. It is called from
* up_signal_dispatch() in user-mode.
*
- * Inputs:
+ * Input Parameters:
* sighand - The address user-space signal handling function
* signo, info, and ucontext - Standard arguments to be passed to the
* signal handling function.
*
- * Return:
+ * Returned Value:
* None. This function does not return in the normal sense. It returns
* via an architecture specific system call made by up_signal_handler().
* However, this will look like a normal return by the caller of
diff --git a/arch/arm/src/armv7-r/arm_signal_handler.S b/arch/arm/src/armv7-r/arm_signal_handler.S
index 43f629a3ba9254f8e84ab949648e2bdb28ae7296..f2812a934fd06ebb8ac263470157d48b855683e3 100644
--- a/arch/arm/src/armv7-r/arm_signal_handler.S
+++ b/arch/arm/src/armv7-r/arm_signal_handler.S
@@ -76,13 +76,13 @@
* R4-R10 - static registers must be preserved
* R12-R14 - LR and SP must be preserved
*
- * Inputs:
+ * Input Parameters:
* R0 = sighand
* The address user-space signal handling function
* R1-R3 = signo, info, and ucontext
* Standard arguments to be passed to the signal handling function.
*
- * Return:
+ * Returned Value:
* None. This function does not return in the normal sense. It returns
* via the SYS_signal_handler_return (see svcall.h)
*
diff --git a/arch/arm/src/armv7-r/arm_testset.S b/arch/arm/src/armv7-r/arm_testset.S
index f82837d5fe8f688779b5620a0ad03fa029631071..703f466b1989a459480f12fca50d2c5355590900 100644
--- a/arch/arm/src/armv7-r/arm_testset.S
+++ b/arch/arm/src/armv7-r/arm_testset.S
@@ -72,7 +72,7 @@
* Description:
* Perform an atomic test and set operation on the provided spinlock.
*
- * This function must be provided via the architecture-specific logoic.
+ * This function must be provided via the architecture-specific logic.
*
* Input Parameters:
* lock - The address of spinlock object.
diff --git a/arch/arm/src/armv7-r/arm_unblocktask.c b/arch/arm/src/armv7-r/arm_unblocktask.c
index 0361c1cc816f19903bb5c95e52796c25bca5c547..10188aac106458462165ee566dc9184cd2756f7f 100644
--- a/arch/arm/src/armv7-r/arm_unblocktask.c
+++ b/arch/arm/src/armv7-r/arm_unblocktask.c
@@ -73,7 +73,7 @@
* but has been prepped to execute. Move the TCB to the
* ready-to-run list, restore its context, and start execution.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to the tcb to be unblocked. This tcb is
* in one of the waiting tasks lists. It must be moved to
* the ready-to-run list and, if it is the highest priority
diff --git a/arch/arm/src/armv7-r/arm_vfork.S b/arch/arm/src/armv7-r/arm_vfork.S
index 635a5759c461a41c2688408c8f1d16c66b68c5ab..5b9a49588fe73264c396d61bf88ec76ad2ea491d 100644
--- a/arch/arm/src/armv7-r/arm_vfork.S
+++ b/arch/arm/src/armv7-r/arm_vfork.S
@@ -88,10 +88,10 @@
* 5) up_vfork() then calls task_vforkstart()
* 6) task_vforkstart() then executes the child thread.
*
- * Input Paremeters:
+ * Input Parameters:
* None
*
- * Return:
+ * Returned Value:
* Upon successful completion, vfork() returns 0 to the child process and
* returns the process ID of the child process to the parent process.
* Otherwise, -1 is returned to the parent, no child process is created,
diff --git a/arch/arm/src/bcm2708/bcm_boot.c b/arch/arm/src/bcm2708/bcm_boot.c
index a73dbf5e66787065f614b0f6d54dcd99eaf2fe80..7dbc32cb812179b1bbaaa6803f7a40b5000d3750 100644
--- a/arch/arm/src/bcm2708/bcm_boot.c
+++ b/arch/arm/src/bcm2708/bcm_boot.c
@@ -104,7 +104,7 @@ static inline void bcm_set_level1entry(uint32_t paddr, uint32_t vaddr,
/****************************************************************************
* Name: bcm_setupmappings
*
- * Description
+ * Description:
* Map all of the initial memory regions defined in g_section_mapping[]
*
****************************************************************************/
diff --git a/arch/arm/src/bcm2708/bcm_miniuart.c b/arch/arm/src/bcm2708/bcm_miniuart.c
index dc17851f61f86a965f7f594c6975804437cd98ce..a035bd12136f8f0e16ba34db9cfc2bc339fe6bab 100644
--- a/arch/arm/src/bcm2708/bcm_miniuart.c
+++ b/arch/arm/src/bcm2708/bcm_miniuart.c
@@ -640,7 +640,7 @@ static bool bcm_rxavailable(struct uart_dev_s *dev)
* Return true if UART activated RX flow control to block more incoming
* data
*
- * Input parameters:
+ * Input Parameters:
* dev - UART device instance
* nbuffered - the number of characters currently buffered
* (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is
diff --git a/arch/arm/src/c5471/c5471_ethernet.c b/arch/arm/src/c5471/c5471_ethernet.c
index b98fd6ecac9eb28e3615c24b167d58b474ba5b43..b92f2f20948691b6d9dac2383bba00af3050273c 100644
--- a/arch/arm/src/c5471/c5471_ethernet.c
+++ b/arch/arm/src/c5471/c5471_ethernet.c
@@ -439,7 +439,7 @@ static void c5471_macassign(struct c5471_driver_s *priv);
/****************************************************************************
* Name: c5471_dumpbuffer
*
- * Description
+ * Description:
* Debug only
*
****************************************************************************/
@@ -461,7 +461,7 @@ static inline void c5471_dumpbuffer(const char *msg, const uint8_t *buffer,
/****************************************************************************
* Name: c5471_mdtxbit
*
- * Description
+ * Description:
* A helper routine used when serially communicating with the c547X's
* external ethernet transeiver device. GPIO pins are connected to the
* transeiver's MDCLK and MDIO pins and are used to accomplish the serial
@@ -528,7 +528,7 @@ static void c5471_mdtxbit (int bit_state)
/****************************************************************************
* Name: c5471_mdrxbit
*
- * Description
+ * Description:
* A helper routine used when serially communicating with the c547X's
* external ethernet transeiver device. GPIO pins are connected to the
* transeiver's MDCLK and MDIO pins and are used to accomplish the serial
@@ -589,7 +589,7 @@ static int c5471_mdrxbit (void)
/****************************************************************************
* Name: c5471_mdwrite
*
- * Description
+ * Description:
* A helper routine used when serially communicating with the c547X's
* external ethernet transeiver device. GPIO pins are connected to the
* transeiver's MDCLK and MDIO pins and are used to accomplish the serial
@@ -651,7 +651,7 @@ static void c5471_mdwrite (int adr, int reg, int data)
/****************************************************************************
* Name: c5471_mdread
*
- * Description
+ * Description:
* A helper routine used when serially communicating with the c547X's
* external ethernet transeiver device. GPIO pins are connected to the
* transeiver's MDCLK and MDIO pins and are used to accomplish the serial
@@ -716,7 +716,7 @@ static int c5471_mdread (int adr, int reg)
/****************************************************************************
* Name: c5471_phyinit
*
- * Description
+ * Description:
* The c547X EVM board uses a Lucent LU3X31T-T64 transeiver device to
* handle the physical layer (PHY). It's a h/w block that on the one end
* offers a Media Independent Interface (MII) which is connected to the
@@ -820,7 +820,7 @@ static int c5471_phyinit (void)
/****************************************************************************
* Name: c5471_inctxcpu
*
- * Description
+ * Description:
*
****************************************************************************/
@@ -843,7 +843,7 @@ static inline void c5471_inctxcpu(struct c5471_driver_s *priv)
/****************************************************************************
* Name: c5471_incrxcpu
*
- * Description
+ * Description:
*
****************************************************************************/
@@ -2073,7 +2073,7 @@ static int c5471_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
/****************************************************************************
* Name: c5471_eimreset
*
- * Description
+ * Description:
* The C547x docs states that a module should generally be reset according
* to the following algorithm:
*
@@ -2121,7 +2121,7 @@ static void c5471_eimreset (struct c5471_driver_s *priv)
/****************************************************************************
* Name: c5471_eimconfig
*
- * Description
+ * Description:
* Assumes that all registers are currently in the power-up reset state.
* This routine then modifies that state to provide our specific ethernet
* configuration.
@@ -2332,7 +2332,7 @@ static void c5471_eimconfig(struct c5471_driver_s *priv)
/****************************************************************************
* Name: c5471_reset
*
- * Description
+ * Description:
*
****************************************************************************/
@@ -2352,7 +2352,7 @@ static void c5471_reset(struct c5471_driver_s *priv)
/****************************************************************************
* Name: c5471_macassign
*
- * Description
+ * Description:
* Set the mac address of our CPU ether port so that when the SWITCH
* receives packets from the PROMISCUOUS ENET0 it will switch them to the
* CPU port and cause a packet arrival event on the Switch's CPU TX queue
@@ -2447,7 +2447,7 @@ void up_netinitialize(void)
#endif
g_c5471[0].c_dev.d_private = (void *)g_c5471; /* Used to recover private state from dev */
- /* Create a watchdog for timing polling for and timing of transmisstions */
+ /* Create a watchdog for timing polling for and timing of transmissions */
g_c5471[0].c_txpoll = wd_create(); /* Create periodic poll timer */
g_c5471[0].c_txtimeout = wd_create(); /* Create TX timeout timer */
diff --git a/arch/arm/src/common/up_checkstack.c b/arch/arm/src/common/up_checkstack.c
index 03423fd426a28deb0cfd3674253a158dee409c65..fe75ed99cd32b4ececd61068b4abe616671afa31 100644
--- a/arch/arm/src/common/up_checkstack.c
+++ b/arch/arm/src/common/up_checkstack.c
@@ -72,7 +72,7 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size, bool int_stack);
* alloc - Allocation base address of the stack
* size - The size of the stack in bytes
*
- * Returned value:
+ * Returned Value:
* The estimated amount of stack space used.
*
****************************************************************************/
@@ -182,7 +182,7 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size, bool int_stack)
* Input Parameters:
* None
*
- * Returned value:
+ * Returned Value:
* The estimated amount of stack space used.
*
****************************************************************************/
diff --git a/arch/arm/src/common/up_createstack.c b/arch/arm/src/common/up_createstack.c
index 6643f94def72428f18b55ea1abd5805c581f9d5e..2f3bd3b4d4c1941c29ab7c67f4ea067998de7b8b 100644
--- a/arch/arm/src/common/up_createstack.c
+++ b/arch/arm/src/common/up_createstack.c
@@ -97,7 +97,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
* the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The requested stack size. At least this much
* must be allocated.
diff --git a/arch/arm/src/common/up_releasestack.c b/arch/arm/src/common/up_releasestack.c
index 9be9740a5b5b6f91cbafc41fb596a2a6a7f0fc13..7090916dde2ca6782523f937e9e4182ab2be9089 100644
--- a/arch/arm/src/common/up_releasestack.c
+++ b/arch/arm/src/common/up_releasestack.c
@@ -69,7 +69,7 @@
* A task has been stopped. Free all stack related resources retained in
* the defunct TCB.
*
- * Input Parmeters
+ * Input Parameters:
* - dtcb: The TCB containing information about the stack to be released
* - ttype: The thread type. This may be one of following (defined in
* include/nuttx/sched.h):
diff --git a/arch/arm/src/common/up_stackframe.c b/arch/arm/src/common/up_stackframe.c
index dace2e9239fa7f4071a5e4ca3491271d9e0d4261..c3a1f055eb449ad42bce0514515452a5c4bb5ec2 100644
--- a/arch/arm/src/common/up_stackframe.c
+++ b/arch/arm/src/common/up_stackframe.c
@@ -98,7 +98,7 @@
* been removed from the stack. This will still be the initial value
* of the stack pointer when the task is started.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - frame_size: The size of the stack frame to allocate.
*
diff --git a/arch/arm/src/common/up_usestack.c b/arch/arm/src/common/up_usestack.c
index 55c6a0526f5645787d7ed7d03665015814e1edec..7748fbd652eac64bc458cca79dd5a50652352096 100644
--- a/arch/arm/src/common/up_usestack.c
+++ b/arch/arm/src/common/up_usestack.c
@@ -89,7 +89,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The
* initial value of the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The allocated stack size.
*
diff --git a/arch/arm/src/common/up_vfork.c b/arch/arm/src/common/up_vfork.c
index 5a69e310e3815d92adb927e505fa9d283d132c7b..ff43c9cc970fb2fd269512119edafe6b3fbb9c57 100644
--- a/arch/arm/src/common/up_vfork.c
+++ b/arch/arm/src/common/up_vfork.c
@@ -101,7 +101,7 @@
* Input Parameters:
* context - Caller context information saved by vfork()
*
- * Return:
+ * Returned Value:
* Upon successful completion, vfork() returns 0 to the child process and
* returns the process ID of the child process to the parent process.
* Otherwise, -1 is returned to the parent, no child process is created,
diff --git a/arch/arm/src/dm320/dm320_framebuffer.c b/arch/arm/src/dm320/dm320_framebuffer.c
index dcedcb62e5d277cd46d2280e1055017ef09db437..94b69e65d3b96b9e5420586c9b40719c6e1c8ab0 100644
--- a/arch/arm/src/dm320/dm320_framebuffer.c
+++ b/arch/arm/src/dm320/dm320_framebuffer.c
@@ -1367,7 +1367,7 @@ static int dm320_setcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_setcurs
* Description:
* Initialize the framebuffer video hardware associated with the display.
*
- * Input parameters:
+ * Input Parameters:
* display - In the case of hardware with multiple displays, this
* specifies the display. Normally this is zero.
*
@@ -1403,7 +1403,7 @@ int up_fbinitialize(int display)
* Return a a reference to the framebuffer object for the specified video
* plane of the specified plane. Many OSDs support multiple planes of video.
*
- * Input parameters:
+ * Input Parameters:
* display - In the case of hardware with multiple displays, this
* specifies the display. Normally this is zero.
* vplane - Identifies the plane being queried.
diff --git a/arch/arm/src/efm32/Make.defs b/arch/arm/src/efm32/Make.defs
index e02561c77bb5908b34ceef36521334f737d14501..9d24cd2c37b12585eedfb102e3c408dd6b43d09d 100644
--- a/arch/arm/src/efm32/Make.defs
+++ b/arch/arm/src/efm32/Make.defs
@@ -39,7 +39,7 @@ CMN_UASRCS =
CMN_UCSRCS =
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
-CMN_ASRCS += up_testset.S vfork.S
+CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copyfullstate.c
CMN_CSRCS += up_createstack.c up_doirq.c up_exit.c up_hardfault.c
diff --git a/arch/arm/src/efm32/efm32_adc.c b/arch/arm/src/efm32/efm32_adc.c
index e79c2a61ef53b568ffbc67e4557d9e62e2e87f06..abe463ca37562278d92a5ea20bb6cf2f9e113374 100644
--- a/arch/arm/src/efm32/efm32_adc.c
+++ b/arch/arm/src/efm32/efm32_adc.c
@@ -705,7 +705,7 @@ endif /* defined(ADC_COUNT) && (ADC_COUNT > 0) */
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the ADC block status
*
* Returned Value:
@@ -847,9 +847,9 @@ static void adc_hw_reset(struct efm32_dev_s *priv, bool reset)
/****************************************************************************
* Name: adc_enable
*
- * Description : Enables or disables the specified ADC peripheral.
- * Also, starts a conversion when the ADC is not
- * triggered by timers
+ * Description:
+ * Enables or disables the specified ADC peripheral. Also, starts a
+ * conversion when the ADC is not triggered by timers
*
* Input Parameters:
*
diff --git a/arch/arm/src/efm32/efm32_bitband.c b/arch/arm/src/efm32/efm32_bitband.c
index fa45b660b8348279fe4c020d3b42c1ff312a9e66..a4810705c35c3d76e2fbc04b1cdfb13dd4f80740 100644
--- a/arch/arm/src/efm32/efm32_bitband.c
+++ b/arch/arm/src/efm32/efm32_bitband.c
@@ -86,7 +86,7 @@
* Note
* This function is only atomic on cores which fully support bitbanding.
*
- * Input Parmeters:
+ * Input Parameters:
* addr Peripheral address location to modify bit in.
* bit Bit position to modify, 0-31.
* val Value to set bit to, 0 or 1.
@@ -115,7 +115,7 @@ inline void bitband_set_peripheral(uint32_t addr, uint32_t bit, uint32_t val)
* Note
* This function is only atomic on cores which fully support bitbanding.
*
- * Input Parmeters:
+ * Input Parameters:
* addr Peripheral address location to read.
* bit Bit position to modify, 0-31.
*
@@ -145,7 +145,7 @@ inline uint32_t bitband_get_peripheral(uint32_t addr, uint32_t bit)
* Note
* This function is only atomic on cores which fully support bitbanding.
*
- * Input Parmeters:
+ * Input Parameters:
* addr SRAM address location to modify bit in.
* bit Bit position to modify, 0-31.
* val Value to set bit to, 0 or 1.
@@ -174,7 +174,7 @@ inline void bitband_set_sram(uint32_t addr, uint32_t bit, uint32_t val)
* Note
* This function is only atomic on cores which fully support bitbanding.
*
- * Input Parmeters:
+ * Input Parameters:
* addr Peripheral address location to read.
* bit Bit position to modify, 0-31.
*
diff --git a/arch/arm/src/efm32/efm32_dma.c b/arch/arm/src/efm32/efm32_dma.c
index ef97e08d6c503fbe163b2ca2f41a881feb6e1547..f93497b4d30d3a4372e9e2146b6ad06e9cf8a0a2 100644
--- a/arch/arm/src/efm32/efm32_dma.c
+++ b/arch/arm/src/efm32/efm32_dma.c
@@ -319,7 +319,7 @@ void weak_function up_dmainitialize(void)
* until the holder of a channel relinquishes the channel by calling
* efm32_dmafree().
*
- * Input parameters:
+ * Input Parameters:
* None
*
* Returned Value:
diff --git a/arch/arm/src/efm32/efm32_dma.h b/arch/arm/src/efm32/efm32_dma.h
index 813b30bf703d4cfb63b6e67a150001aefe0fea3d..19eec8b0e930cb1a578cecfe8eb0601b33ed0f30 100644
--- a/arch/arm/src/efm32/efm32_dma.h
+++ b/arch/arm/src/efm32/efm32_dma.h
@@ -173,7 +173,7 @@ extern "C"
* If no DMA channel is available, then efm32_dmachannel() will wait until the
* holder of a channel relinquishes the channel by calling efm32_dmafree().
*
- * Input parameters:
+ * Input Parameters:
* None
*
* Returned Value:
diff --git a/arch/arm/src/efm32/efm32_flash.c b/arch/arm/src/efm32/efm32_flash.c
index 1353bbbdb12f2cccec47425947f324cf1eb913c2..d02f9d2fa53cc31052d685bf5b9237d6854b60eb 100644
--- a/arch/arm/src/efm32/efm32_flash.c
+++ b/arch/arm/src/efm32/efm32_flash.c
@@ -258,7 +258,7 @@ int __ramfunc__ msc_load_verify_address(uint32_t *address)
}
/****************************************************************************
- * Name:msc_load_data
+ * Name: msc_load_data
*
* Description:
* Perform data phase of FLASH write cycle.
diff --git a/arch/arm/src/efm32/efm32_i2c.h b/arch/arm/src/efm32/efm32_i2c.h
index 16e51434bef338805e641197a898d2ca2cb2ac98..6218da8435e9ef943717b29c1286b9d5ecaf5a02 100644
--- a/arch/arm/src/efm32/efm32_i2c.h
+++ b/arch/arm/src/efm32/efm32_i2c.h
@@ -56,7 +56,7 @@
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
@@ -72,7 +72,7 @@ FAR struct i2c_master_s *efm32_i2cbus_initialize(int port);
* Description:
* De-initialize the selected I2C port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the efm32_i2cbus_initialize()
*
* Returned Value:
diff --git a/arch/arm/src/efm32/efm32_pm.h b/arch/arm/src/efm32/efm32_pm.h
index 6846de31a394e61ba9f5c9c0aba60de1401acab2..413eda45c1d51037ad84c09e9ecbbd0482a68b04 100644
--- a/arch/arm/src/efm32/efm32_pm.h
+++ b/arch/arm/src/efm32/efm32_pm.h
@@ -110,7 +110,7 @@ int efm32_pmstop(bool lpds);
* Input Parameters:
* None
*
- * Returned Value.
+ * Returned Value:
* On success, this function will not return (STANDBY mode can only be
* terminated with a reset event). Otherwise, STANDBY mode did not occur
* and a negated errno value is returned to indicate the cause of the
diff --git a/arch/arm/src/efm32/efm32_pwm.c b/arch/arm/src/efm32/efm32_pwm.c
index b9c7bd0271d7fc47ec791c2410c2daacc29d8dbd..ec0ac7955515b7aa13bb4a302005e64a02bf6322 100644
--- a/arch/arm/src/efm32/efm32_pwm.c
+++ b/arch/arm/src/efm32/efm32_pwm.c
@@ -284,7 +284,7 @@ static void pwm_putreg(struct efm32_pwmtimer_s *priv, int offset, uint32_t value
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the PWM block status
*
* Returned Value:
@@ -345,7 +345,7 @@ static void pwm_dumpregs(struct efm32_pwmtimer_s *priv, FAR const char *msg)
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -433,7 +433,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
* Description:
* Handle timer interrupts.
*
- * Input parameters:
+ * Input Parameters:
* Standard interrupt handler arguments.
*
* Returned Value:
@@ -529,7 +529,7 @@ static int pwm_interrupt(int irq, void *context, FAR void *arg)
* Description:
* Pick an optimal pulse count to program the RCR.
*
- * Input parameters:
+ * Input Parameters:
* count - The total count remaining
*
* Returned Value:
@@ -583,7 +583,7 @@ static uint8_t pwm_pulsecount(uint32_t count)
* should configure and initialize the device so that it is ready for use.
* It should not, however, output pulses until the start method is called.
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -643,7 +643,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
* stop pulsed output, free any resources, disable the timer hardware, and
* put the system into the lowest possible power usage state
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -678,7 +678,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -717,7 +717,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
* Description:
* Stop the pulsed output and reset the timer resources
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -761,7 +761,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
* Description:
* Lower-half logic may support platform-specific ioctl commands
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* cmd - The ioctl command
* arg - The argument accompanying the ioctl command
diff --git a/arch/arm/src/efm32/efm32_rmu.c b/arch/arm/src/efm32/efm32_rmu.c
index 57d7b0e02b76d82a03a67010b6d0da4a6f98163b..fbed325339ef3de000d4006c36395450920d1287 100644
--- a/arch/arm/src/efm32/efm32_rmu.c
+++ b/arch/arm/src/efm32/efm32_rmu.c
@@ -184,7 +184,7 @@ uint32_t g_efm32_rstcause;
* Description:
* Return next reset cause string, NULL if no more reset cause.
*
- * Input Parmeters:
+ * Input Parameters:
* reg: reset cause register to decode (like g_efm32_rstcause)
* idx: Use to keep in maind reset cause decoding position.
* set *idx to zero before first call.
diff --git a/arch/arm/src/efm32/efm32_rmu.h b/arch/arm/src/efm32/efm32_rmu.h
index 1bcfec2d33f0952fbd1bc9753dcc1aec951dcda1..9a7a32dbdc810692822c0bcc48dd82a78b16a85b 100644
--- a/arch/arm/src/efm32/efm32_rmu.h
+++ b/arch/arm/src/efm32/efm32_rmu.h
@@ -90,7 +90,7 @@ const char* efm32_reset_cause_list_str(uint32_t reg, unsigned int *idx);
* Description:
* Return next reset cause string, NULL if no more reset cause.
*
- * Input Parmeters:
+ * Input Parameters:
* reg: reset cause register to decode (like g_efm32_rstcause)
* idx: Use to keep in maind reset cause decoding position.
* set *idx to zero before first call.
diff --git a/arch/arm/src/efm32/efm32_spi.c b/arch/arm/src/efm32/efm32_spi.c
index f16d196e64a7521fdfaf7f0fc2db9260a0b5c171..7fe5139666d49fb80cf07616a41c5c3454f2b8e3 100644
--- a/arch/arm/src/efm32/efm32_spi.c
+++ b/arch/arm/src/efm32/efm32_spi.c
@@ -1493,7 +1493,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
ret = wd_start(priv->wdog, (int)ticks, spi_dma_timeout, 1, (uint32_t)priv);
if (ret < 0)
{
- spierr("ERROR: Failed to start timeout\n");
+ spierr("ERROR: Failed to start timeout: %d\n", ret);
}
/* Then wait for each to complete. TX should complete first */
@@ -1570,7 +1570,7 @@ static void spi_recvblock(struct spi_dev_s *dev, void *rxbuffer,
* Initialize the selected SPI port in its default state (Master, 8-bit,
* mode 0, etc.)
*
- * Input Parameter:
+ * Input Parameters:
* priv - private SPI device structure
*
* Returned Value:
@@ -1695,7 +1695,7 @@ errout:
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* port - SPI port number to initialize. One of {0,1,2}
*
* Returned Value:
diff --git a/arch/arm/src/efm32/efm32_spi.h b/arch/arm/src/efm32/efm32_spi.h
index 9e84fb68dc3f0686b4f36214ccefac2c898c5544..bcaff84e134a294386d8cbaf32f57a75c5dd4ff0 100644
--- a/arch/arm/src/efm32/efm32_spi.h
+++ b/arch/arm/src/efm32/efm32_spi.h
@@ -59,7 +59,7 @@ struct spi_dev_s; /* Forward reference */
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* port - SPI port number to initialize. One of {0,1,2}
*
* Returned Value:
diff --git a/arch/arm/src/efm32/efm32_timer.c b/arch/arm/src/efm32/efm32_timer.c
index 6264c3a378243369f4b713c9dae04b20982c787a..f8c1b1eaafea6ba2dae7936a396b1d573f094233 100644
--- a/arch/arm/src/efm32/efm32_timer.c
+++ b/arch/arm/src/efm32/efm32_timer.c
@@ -77,7 +77,7 @@
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* base - A base address of timer
*
* Returned Value:
@@ -132,7 +132,7 @@ void efm32_timer_dumpregs(uintptr_t base, FAR const char *msg)
* Description:
* reset timer into reset state
*
- * Input parameters:
+ * Input Parameters:
* base - A base address of timer
*
* Returned Value:
@@ -192,7 +192,7 @@ void efm32_timer_reset(uintptr_t base)
* Description:
* set prescaler and top timer with best value to have "freq"
*
- * Input parameters:
+ * Input Parameters:
* base - A base address of timer
* clk_freq - Clock soure of timer.
* freq - Wanted freqency.
diff --git a/arch/arm/src/efm32/efm32_usbhost.c b/arch/arm/src/efm32/efm32_usbhost.c
index cce11725fdd9454bf69acbb6d19339758a5a5406..8c1866a7977fc9fd1cea06c06f914d925722462f 100644
--- a/arch/arm/src/efm32/efm32_usbhost.c
+++ b/arch/arm/src/efm32/efm32_usbhost.c
@@ -1340,7 +1340,7 @@ static int efm32_ctrlchan_alloc(FAR struct efm32_usbhost_s *priv,
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -1402,7 +1402,7 @@ static int efm32_ctrlep_alloc(FAR struct efm32_usbhost_s *priv,
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3791,7 +3791,7 @@ static void efm32_txfe_enable(FAR struct efm32_usbhost_s *priv, int chidx)
* hport - The location to return the hub port descriptor that detected the
* connection related event.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success when a device in connected or
* disconnected. This function will not return until either (1) a device is
* connected or disconnect to/from any hub port or until (2) some failure
@@ -3882,7 +3882,7 @@ static int efm32_wait(FAR struct usbhost_connection_s *conn,
* hport - The descriptor of the hub port that has the newly connected
* device.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4010,7 +4010,7 @@ static int efm32_enumerate(FAR struct usbhost_connection_s *conn,
* maxpacketsize - The maximum number of bytes that can be sent to or
* received from the endpoint in a single data packet
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4069,7 +4069,7 @@ static int efm32_ep0configure(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4126,7 +4126,7 @@ static int efm32_epalloc(FAR struct usbhost_driver_s *drvr,
* the class create() method.
* ep - The endpoint to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4194,7 +4194,7 @@ static int efm32_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
* maxlen - The address of a memory location provided by the caller in which to
* return the maximum size of the allocated buffer memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4240,7 +4240,7 @@ static int efm32_alloc(FAR struct usbhost_driver_s *drvr,
* the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4276,7 +4276,7 @@ static int efm32_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer)
* return the allocated buffer memory address.
* buflen - The size of the buffer required.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4320,7 +4320,7 @@ static int efm32_ioalloc(FAR struct usbhost_driver_s *drvr,
* the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4363,7 +4363,7 @@ static int efm32_iofree(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer)
* NOTE: On an IN transaction, req and buffer may refer to the same allocated
* memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4566,7 +4566,7 @@ static int efm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
* (IN endpoint). buffer must have been allocated using DRVR_ALLOC
* buflen - The length of the data to be sent or received.
*
- * Returned Values:
+ * Returned Value:
* On success, a non-negative value is returned that indicates the number
* of bytes successfully transferred. On a failure, a negated errno value is
* returned that indicates the nature of the failure:
@@ -4638,7 +4638,7 @@ static ssize_t efm32_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep
* arg - The arbitrary parameter that will be passed to the callback function
* when the transfer completes.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4694,7 +4694,7 @@ static int efm32_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
* ep - The IN or OUT endpoint descriptor for the device endpoint on which an
* asynchronous transfer should be transferred.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -4783,7 +4783,7 @@ static int efm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
* related event
* connected - True: device connected; false: device disconnected
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -4834,7 +4834,7 @@ static int efm32_connect(FAR struct usbhost_driver_s *drvr,
* drvr - The USB host driver instance obtained as a parameter from the call to
* the class create() method.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
diff --git a/arch/arm/src/imx1/imx_cspi.h b/arch/arm/src/imx1/imx_cspi.h
index f15872c49b142751513eb924aacf6120df7b0391..3d80a3d540b161ce041ce3d6adaf5de02fdb54b3 100644
--- a/arch/arm/src/imx1/imx_cspi.h
+++ b/arch/arm/src/imx1/imx_cspi.h
@@ -193,7 +193,7 @@ struct spi_dev_s; /* Forward reference */
* required. Theregore, all GPIO chip management is deferred to board-
* specific logic.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/imx1/imx_spi.c b/arch/arm/src/imx1/imx_spi.c
index 92208b78be3faf92b3144cab3a2d0f1bcd9b91d4..682805fdb7055a08cc4460e37f4f7d9ce84fdad0 100644
--- a/arch/arm/src/imx1/imx_spi.c
+++ b/arch/arm/src/imx1/imx_spi.c
@@ -1024,7 +1024,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
* required. Theregore, all GPIO chip management is deferred to board-
* specific logic.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/imx6/Make.defs b/arch/arm/src/imx6/Make.defs
index c551c22d97b3d024a5c728914f4cfb99b4eba5b9..3950f54a98d5bfb2b963570a77d5e87a8d6c1ab8 100644
--- a/arch/arm/src/imx6/Make.defs
+++ b/arch/arm/src/imx6/Make.defs
@@ -58,7 +58,7 @@ endif
CMN_ASRCS += arm_vectors.S arm_fpuconfig.S arm_fullcontextrestore.S
CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S arm_vfork.S
-CMN_ASRCS += arm_testset.S
+CMN_ASRCS += arm_testset.S arm_fetchadd.S
CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S
diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c
index 6abc6f8b15753ea4479657b7a8a341b6d0ff7703..f48b3e70a286caf79e7fb407f2642c38097c6477 100644
--- a/arch/arm/src/imx6/imx_boot.c
+++ b/arch/arm/src/imx6/imx_boot.c
@@ -91,7 +91,7 @@ extern uint32_t _vector_end; /* End+1 of vector block */
/****************************************************************************
* Name: imx_setupmappings
*
- * Description
+ * Description:
* Map all of the initial memory regions defined in g_section_mapping[]
*
****************************************************************************/
@@ -115,7 +115,7 @@ static inline void imx_setupmappings(void)
/****************************************************************************
* Name: imx_remap
*
- * Description
+ * Description:
* Map all of the final memory regions defined in g_operational_mapping[]
*
****************************************************************************/
diff --git a/arch/arm/src/imx6/imx_cpuboot.c b/arch/arm/src/imx6/imx_cpuboot.c
index 818b327a4bc4c3cee317fbefdb7d7c8ee3891685..e747b701cfa19399adb5d842daf08253e331aff7 100644
--- a/arch/arm/src/imx6/imx_cpuboot.c
+++ b/arch/arm/src/imx6/imx_cpuboot.c
@@ -249,7 +249,7 @@ void imx_cpu_enable(void)
* This function must be provided by the each ARMv7-A MCU and implement
* MCU-specific initialization logic.
*
- * Input parameters:
+ * Input Parameters:
* cpu - The CPU index. This is the same value that would be obtained by
* calling up_cpu_index();
*
diff --git a/arch/arm/src/imx6/imx_ecspi.c b/arch/arm/src/imx6/imx_ecspi.c
index 42c8017fc0c0a9c83936230df9dfd0bf0e4eab00..0a20c514b9f47cab28a1f7eab8a83179e676d95d 100644
--- a/arch/arm/src/imx6/imx_ecspi.c
+++ b/arch/arm/src/imx6/imx_ecspi.c
@@ -1209,7 +1209,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
* required. Theregore, all GPIO chip management is deferred to board-
* specific logic.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/imx6/imx_ecspi.h b/arch/arm/src/imx6/imx_ecspi.h
index ac30d2291f9428ff331c50e7a3860450ed13268b..4e3f8b977e12bca4619ab8acfab027bbe409e83f 100644
--- a/arch/arm/src/imx6/imx_ecspi.h
+++ b/arch/arm/src/imx6/imx_ecspi.h
@@ -85,7 +85,7 @@ struct spi_dev_s; /* Forward reference */
* required. Theregore, all GPIO chip management is deferred to board-
* specific logic.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/kinetis/Make.defs b/arch/arm/src/kinetis/Make.defs
index 4d9907907ed95856c97d4c3d67c240d9ee00a3bf..7e47c09e0357acf9b10338f2238df88cb7846c8c 100644
--- a/arch/arm/src/kinetis/Make.defs
+++ b/arch/arm/src/kinetis/Make.defs
@@ -43,7 +43,7 @@ CMN_UASRCS =
CMN_UCSRCS =
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
-CMN_ASRCS += up_testset.S vfork.S
+CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S
CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c
CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_initialize.c up_memfault.c
diff --git a/arch/arm/src/kinetis/kinetis.h b/arch/arm/src/kinetis/kinetis.h
index a1558179fd07f1ac446e6cc583a58821cc4b18b1..ef91886626725884639345cf7637dafc3a9fad53 100644
--- a/arch/arm/src/kinetis/kinetis.h
+++ b/arch/arm/src/kinetis/kinetis.h
@@ -418,7 +418,7 @@ void kinetis_lowsetup(void);
* Input Parameters:
* first: - First TTY number to assign
*
- * Returns Value:
+ * Returned Value:
* The next TTY number available for assignment
*
****************************************************************************/
@@ -437,7 +437,7 @@ unsigned int kinetis_uart_serialinit(unsigned int first);
* Input Parameters:
* first: - First TTY number to assign
*
- * Returns Value:
+ * Returned Value:
* The next TTY number available for assignment
*
****************************************************************************/
@@ -587,7 +587,7 @@ void kinetis_pinirqinitialize(void);
* pinisr - Pin interrupt service routine
* arg - An argument that will be provided to the interrupt service routine.
*
- * Return Value:
+ * Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on any
* failure to indicate the nature of the failure.
*
@@ -678,10 +678,10 @@ void kinetis_clrpend(int irq);
* Description:
* Initialize SDIO for operation.
*
- * Input parameters:
+ * Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
@@ -705,7 +705,7 @@ FAR struct sdio_dev_s *sdhc_initialize(int slotno);
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -725,7 +725,7 @@ void sdhc_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is writeprotected.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c
index 8f51cc6a7b8706e6c5baab83a331540f76a23f88..73d2f76892e5b60048b234bfdaccb6675ec859c9 100644
--- a/arch/arm/src/kinetis/kinetis_enet.c
+++ b/arch/arm/src/kinetis/kinetis_enet.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/kinetis/kinetis_enet.c
*
- * Copyright (C) 2011-2012, 2014-2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011-2012, 2014-2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt
* David Sidrane
*
@@ -158,19 +158,21 @@
# define BOARD_PHYID1 MII_PHYID1_KSZ8041
# define BOARD_PHYID2 MII_PHYID2_KSZ8041
# define BOARD_PHY_STATUS MII_KSZ8041_PHYCTRL2
+# define BOARD_PHY_10BASET(s) (((s) & MII_PHYCTRL2_MODE_10HDX) != 0)
+# define BOARD_PHY_100BASET(s) (((s) & MII_PHYCTRL2_MODE_100HDX) != 0)
+# define BOARD_PHY_ISDUPLEX(s) (((s) & MII_PHYCTRL2_MODE_DUPLEX) != 0)
#elif defined(CONFIG_ETH0_PHY_KSZ8081)
# define BOARD_PHY_NAME "KSZ8081"
# define BOARD_PHYID1 MII_PHYID1_KSZ8081
# define BOARD_PHYID2 MII_PHYID2_KSZ8081
-# define BOARD_PHY_STATUS MII_KSZ8081_PHYCTRL2
+# define BOARD_PHY_STATUS MII_KSZ8081_PHYCTRL1
+# define BOARD_PHY_10BASET(s) (((s) & MII_PHYCTRL1_MODE_10HDX) != 0)
+# define BOARD_PHY_100BASET(s) (((s) & MII_PHYCTRL1_MODE_100HDX) != 0)
+# define BOARD_PHY_ISDUPLEX(s) (((s) & MII_PHYCTRL1_MODE_DUPLEX) != 0)
#else
# error "Unrecognized or missing PHY selection"
#endif
-#define BOARD_PHY_10BASET(s) (((s) & (1 << MII_PHYCTRL2_MODE_SHIFT)) != 0)
-#define BOARD_PHY_100BASET(s) (((s) & (2 << MII_PHYCTRL2_MODE_SHIFT)) != 0)
-#define BOARD_PHY_ISDUPLEX(s) (((s) & (4 << MII_PHYCTRL2_MODE_SHIFT)) != 0)
-
/* Estimate the MII_SPEED in order to get an MDC close to 2.5MHz,
based on the internal module (ENET) clock:
*
@@ -310,7 +312,7 @@ static int kinetis_addmac(struct net_driver_s *dev,
static int kinetis_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac);
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
static int kinetis_ioctl(struct net_driver_s *dev, int cmd,
unsigned long arg);
#endif
@@ -1449,48 +1451,52 @@ static int kinetis_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
*
****************************************************************************/
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
static int kinetis_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
{
- int ret;
+#ifdef CONFIG_NETDEV_PHY_IOCTL
FAR struct kinetis_driver_s *priv =
(FAR struct kinetis_driver_s *)dev->d_private;
+#endif
+ int ret;
switch (cmd)
- {
- case SIOCGMIIPHY: /* Get MII PHY address */
{
- struct mii_ioctl_data_s *req =
- (struct mii_ioctl_data_s *)((uintptr_t)arg);
- req->phy_id = priv->phyaddr;
- ret = OK;
- }
- break;
+#ifdef CONFIG_NETDEV_PHY_IOCTL
+ case SIOCGMIIPHY: /* Get MII PHY address */
+ {
+ struct mii_ioctl_data_s *req =
+ (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ req->phy_id = priv->phyaddr;
+ ret = OK;
+ }
+ break;
- case SIOCGMIIREG: /* Get register from MII PHY */
- {
- struct mii_ioctl_data_s *req =
- (struct mii_ioctl_data_s *)((uintptr_t)arg);
- ret = kinetis_readmii(priv, req->phy_id, req->reg_num, &req->val_out);
- }
- break;
+ case SIOCGMIIREG: /* Get register from MII PHY */
+ {
+ struct mii_ioctl_data_s *req =
+ (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ ret = kinetis_readmii(priv, req->phy_id, req->reg_num, &req->val_out);
+ }
+ break;
- case SIOCSMIIREG: /* Set register in MII PHY */
- {
- struct mii_ioctl_data_s *req =
- (struct mii_ioctl_data_s *)((uintptr_t)arg);
- ret = kinetis_writemii(priv, req->phy_id, req->reg_num, req->val_in);
- }
- break;
+ case SIOCSMIIREG: /* Set register in MII PHY */
+ {
+ struct mii_ioctl_data_s *req =
+ (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ ret = kinetis_writemii(priv, req->phy_id, req->reg_num, req->val_in);
+ }
+ break;
+#endif /* ifdef CONFIG_NETDEV_PHY_IOCTL */
- default:
- ret = -ENOTTY;
- break;
- }
+ default:
+ ret = -ENOTTY;
+ break;
+ }
return ret;
}
-#endif /* CONFIG_NETDEV_PHY_IOCTL */
+#endif /* CONFIG_NETDEV_IOCTL */
/****************************************************************************
* Function: kinetis_initmii
@@ -2127,12 +2133,12 @@ int kinetis_netinitialize(int intf)
priv->dev.d_addmac = kinetis_addmac; /* Add multicast MAC address */
priv->dev.d_rmmac = kinetis_rmmac; /* Remove multicast MAC address */
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = kinetis_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void *)g_enet; /* Used to recover private state from dev */
- /* Create a watchdog for timing polling for and timing of transmisstions */
+ /* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create(); /* Create periodic poll timer */
priv->txtimeout = wd_create(); /* Create TX timeout timer */
diff --git a/arch/arm/src/kinetis/kinetis_i2c.c b/arch/arm/src/kinetis/kinetis_i2c.c
index 3e409986501b5eb00577643d691c12f4169db1c9..1a7af792a83d41129fcf3b76c31c527066d4882b 100644
--- a/arch/arm/src/kinetis/kinetis_i2c.c
+++ b/arch/arm/src/kinetis/kinetis_i2c.c
@@ -1183,8 +1183,8 @@ static int kinetis_i2c_transfer(struct i2c_master_s *dev,
/* Wait for transfer complete */
- wd_start(priv->timeout, I2C_TIMEOUT, kinetis_i2c_timeout, 1,
- (uint32_t) priv);
+ (void)wd_start(priv->timeout, I2C_TIMEOUT, kinetis_i2c_timeout, 1,
+ (uint32_t)priv);
kinetis_i2c_wait(priv);
wd_cancel(priv->timeout);
diff --git a/arch/arm/src/kinetis/kinetis_i2c.h b/arch/arm/src/kinetis/kinetis_i2c.h
index 098e4d39add5981788688eff46db049908210a33..8cb4246a17faba5745ccb6708da4c0fec774a217 100644
--- a/arch/arm/src/kinetis/kinetis_i2c.h
+++ b/arch/arm/src/kinetis/kinetis_i2c.h
@@ -57,7 +57,7 @@
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
@@ -73,7 +73,7 @@ FAR struct i2c_master_s *kinetis_i2cbus_initialize(int port);
* Description:
* De-initialize the selected I2C port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the lpc43_i2cbus_initialize()
*
* Returned Value:
diff --git a/arch/arm/src/kinetis/kinetis_lpserial.c b/arch/arm/src/kinetis/kinetis_lpserial.c
index 262bda4a8a4e907e989b5cfaf16a5cf4aae74655..3de8f6e3a6ca63e5facd752602438aa61a7496ad 100644
--- a/arch/arm/src/kinetis/kinetis_lpserial.c
+++ b/arch/arm/src/kinetis/kinetis_lpserial.c
@@ -965,7 +965,7 @@ static bool kinetis_rxavailable(struct uart_dev_s *dev)
* Return true if UART activated RX flow control to block more incoming
* data
*
- * Input parameters:
+ * Input Parameters:
* dev - UART device instance
* nbuffered - the number of characters currently buffered
* (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is
@@ -1145,7 +1145,7 @@ void kinetis_lpuart_earlyserialinit(void)
* Input Parameters:
* first: - First TTY number to assign
*
- * Returns Value:
+ * Returned Value:
* The next TTY number available for assignment
*
****************************************************************************/
diff --git a/arch/arm/src/kinetis/kinetis_pin.c b/arch/arm/src/kinetis/kinetis_pin.c
index 8a2e3294321a6ce237c2dd19be73404fa4751d50..4a084f6c27527bd7a33ac5a7501bd0893fca4e5c 100644
--- a/arch/arm/src/kinetis/kinetis_pin.c
+++ b/arch/arm/src/kinetis/kinetis_pin.c
@@ -214,7 +214,7 @@ int kinetis_pinconfig(uint32_t cfgset)
* Configure the digital filter associated with a port. The digital filter
* capabilities of the PORT module are available in all digital pin muxing modes.
*
- * Input parmeters:
+ * Input Parameters:
* port - Port number. See KINETIS_PORTn definitions in kinetis_port.h
* lpo - true: Digital Filters are clocked by the bus clock
* false: Digital Filters are clocked by the 1 kHz LPO clock
diff --git a/arch/arm/src/kinetis/kinetis_pinirq.c b/arch/arm/src/kinetis/kinetis_pinirq.c
index f40be80a8e44cadd302da347df4a194cf10e9588..0a015b6ad49d37006ae78dde156392463d2535ee 100644
--- a/arch/arm/src/kinetis/kinetis_pinirq.c
+++ b/arch/arm/src/kinetis/kinetis_pinirq.c
@@ -267,7 +267,7 @@ void kinetis_pinirqinitialize(void)
* pinisr - Pin interrupt service routine
* arg - An argument that will be provided to the interrupt service routine.
*
- * Returns:
+ * Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on any
* failure to indicate the nature of the failure.
*
diff --git a/arch/arm/src/kinetis/kinetis_pwm.c b/arch/arm/src/kinetis/kinetis_pwm.c
index 83f6c76699bea27e692439aa3d842e97df1e00be..b4dd646c9a641c489db61163b0e5eb16a9a6dfbf 100644
--- a/arch/arm/src/kinetis/kinetis_pwm.c
+++ b/arch/arm/src/kinetis/kinetis_pwm.c
@@ -248,7 +248,7 @@ static void pwm_putreg(struct kinetis_pwmtimer_s *priv, int offset, uint32_t val
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the PWM block status
*
* Returned Value:
@@ -347,7 +347,7 @@ static void pwm_dumpregs(struct kinetis_pwmtimer_s *priv, FAR const char *msg)
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -541,7 +541,7 @@ static int pwm_timer(FAR struct kinetis_pwmtimer_s *priv,
* should configure and initialize the device so that it is ready for use.
* It should not, however, output pulses until the start method is called.
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -589,7 +589,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
* stop pulsed output, free any resources, disable the timer hardware, and
* put the system into the lowest possible power usage state
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -622,7 +622,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -644,7 +644,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
* Description:
* Stop the pulsed output and reset the timer resources
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -728,7 +728,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
* Description:
* Lower-half logic may support platform-specific ioctl commands
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* cmd - The ioctl command
* arg - The argument accompanying the ioctl command
diff --git a/arch/arm/src/kinetis/kinetis_sdhc.c b/arch/arm/src/kinetis/kinetis_sdhc.c
index 1a3a0b53b7f443b80b9a9549b625eb598b512b80..816a4ee18b38c5d4438d53b0d3daaee9755c4f13 100644
--- a/arch/arm/src/kinetis/kinetis_sdhc.c
+++ b/arch/arm/src/kinetis/kinetis_sdhc.c
@@ -2465,7 +2465,7 @@ static sdio_eventset_t kinetis_eventwait(FAR struct sdio_dev_s *dev,
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay, (wdentry_t)kinetis_eventtimeout,
1, (uint32_t)priv);
- if (ret != OK)
+ if (ret < 0)
{
mcerr("ERROR: wd_start failed: %d\n", ret);
}
@@ -2795,7 +2795,7 @@ static void kinetis_callback(void *arg)
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
@@ -2909,7 +2909,7 @@ FAR struct sdio_dev_s *sdhc_initialize(int slotno)
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -2956,7 +2956,7 @@ void sdhc_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is writeprotected.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c
index 0f2a4b2ee46dbdaf05771af1585bf09f8453cc74..23d327ec09acb593403162ba189cc13103a6aaf2 100644
--- a/arch/arm/src/kinetis/kinetis_serial.c
+++ b/arch/arm/src/kinetis/kinetis_serial.c
@@ -1334,7 +1334,7 @@ static bool up_rxavailable(struct uart_dev_s *dev)
* Return true if UART activated RX flow control to block more incoming
* data
*
- * Input parameters:
+ * Input Parameters:
* dev - UART device instance
* nbuffered - the number of characters currently buffered
* (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is
@@ -1561,7 +1561,7 @@ void kinetis_uart_earlyserialinit(void)
* Input Parameters:
* first: - First TTY number to assign
*
- * Returns Value:
+ * Returned Value:
* The next TTY number available for assignment
*
****************************************************************************/
diff --git a/arch/arm/src/kinetis/kinetis_spi.c b/arch/arm/src/kinetis/kinetis_spi.c
index 3fc63b901e4e84328cf3d12e2320ad5f72a9e5fd..ce3971518e8a20878d36d86b26af4691dbb04dc5 100644
--- a/arch/arm/src/kinetis/kinetis_spi.c
+++ b/arch/arm/src/kinetis/kinetis_spi.c
@@ -1109,7 +1109,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, size_t
* Description:
* Initialize the selected SPI port.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/kinetis/kinetis_spi.h b/arch/arm/src/kinetis/kinetis_spi.h
index 8222af442467f44bbd8e7e5dfcf519f26ba4a70a..4d3ce60ce241526809b1f7ff54a1c43b49969719 100644
--- a/arch/arm/src/kinetis/kinetis_spi.h
+++ b/arch/arm/src/kinetis/kinetis_spi.h
@@ -75,7 +75,7 @@ struct spi_dev_s;
* Description:
* Initialize the selected SPI bus
*
- * Input Parameter:
+ * Input Parameters:
* bus number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c
index 4d10d422fd7021a268e9014fe32733648fb34b8a..9fd71b3e78432b7cede413f718439c804b7d85a2 100644
--- a/arch/arm/src/kinetis/kinetis_usbdev.c
+++ b/arch/arm/src/kinetis/kinetis_usbdev.c
@@ -1112,7 +1112,8 @@ static void khci_delayedrestart(struct khci_usbdev_s *priv, uint8_t epno)
/* And start (or re-start) the watchdog timer */
- wd_start(priv->wdog, RESTART_DELAY, khci_rqrestart, 1, (uint32_t)priv);
+ (void)wd_start(priv->wdog, RESTART_DELAY, khci_rqrestart, 1,
+ (uint32_t)priv);
}
/****************************************************************************
diff --git a/arch/arm/src/kl/kl_gpio.h b/arch/arm/src/kl/kl_gpio.h
index 4a81acd27e46ce2c5f8f00d050c307fa7e96140c..78f7fdc122273c883fb4cc6452e6aebb3daf51e4 100644
--- a/arch/arm/src/kl/kl_gpio.h
+++ b/arch/arm/src/kl/kl_gpio.h
@@ -370,7 +370,7 @@ bool kl_gpioread(uint32_t pinset);
* - pinisr: Pin interrupt service routine
* - pinarg: The argument that will accompany the pin interrupt
*
- * Returns:
+ * Returned Value:
* Zero (OK) is returned on success; On any failure, a negated errno value is
* returned to indicate the nature of the failure.
*
diff --git a/arch/arm/src/kl/kl_gpioirq.c b/arch/arm/src/kl/kl_gpioirq.c
index 38f30c0870f1e9f29895ef9744e6e1b1460a75d3..a42be056ab7edd1c3d83532a63519f9526b51a20 100644
--- a/arch/arm/src/kl/kl_gpioirq.c
+++ b/arch/arm/src/kl/kl_gpioirq.c
@@ -230,8 +230,8 @@ void kl_gpioirqinitialize(void)
* - pinisr: Pin interrupt service routine
* - pinarg: The argument that will accompany the pin interrupt
*
- * Returns:
- * Returns:
+ * Returned Value:
+ * Returned Value:
* Zero (OK) is returned on success; On any failure, a negated errno value is
* returned to indicate the nature of the failure.
*
diff --git a/arch/arm/src/kl/kl_pwm.c b/arch/arm/src/kl/kl_pwm.c
index a34aa0f8175b08e9130051208edd70ce36301a19..cfa024b4779b246948dbe53beb7c0312bf902c89 100644
--- a/arch/arm/src/kl/kl_pwm.c
+++ b/arch/arm/src/kl/kl_pwm.c
@@ -226,7 +226,7 @@ static void pwm_putreg(struct kl_pwmtimer_s *priv, int offset, uint32_t value)
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the PWM block status
*
* Returned Value:
@@ -307,7 +307,7 @@ static void pwm_dumpregs(struct kl_pwmtimer_s *priv, FAR const char *msg)
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -488,7 +488,7 @@ static int pwm_timer(FAR struct kl_pwmtimer_s *priv,
* should configure and initialize the device so that it is ready for use.
* It should not, however, output pulses until the start method is called.
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -529,7 +529,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
* stop pulsed output, free any resources, disable the timer hardware, and
* put the system into the lowest possible power usage state
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -562,7 +562,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -584,7 +584,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
* Description:
* Stop the pulsed output and reset the timer resources
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -660,7 +660,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
* Description:
* Lower-half logic may support platform-specific ioctl commands
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* cmd - The ioctl command
* arg - The argument accompanying the ioctl command
diff --git a/arch/arm/src/kl/kl_spi.c b/arch/arm/src/kl/kl_spi.c
index 81cda9c9da5e159a2c2ee53d0a83c10b27609f00..187ae75e9e1b9ef168ad78c613b1517c4866dd1e 100644
--- a/arch/arm/src/kl/kl_spi.c
+++ b/arch/arm/src/kl/kl_spi.c
@@ -612,7 +612,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, size_t
* Description:
* Initialize the selected SPI port.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/kl/kl_spi.h b/arch/arm/src/kl/kl_spi.h
index fd621858a61eee7808139f5bd4d2055f29f5921e..968cf6abeff7779ad4bfbe0c56eeb64195cc22ba 100644
--- a/arch/arm/src/kl/kl_spi.h
+++ b/arch/arm/src/kl/kl_spi.h
@@ -71,7 +71,7 @@ struct spi_dev_s; /* Forward reference */
* Description:
* Initialize the selected SPI port.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lc823450/lc823450_cpuidlestack.c b/arch/arm/src/lc823450/lc823450_cpuidlestack.c
index e9418abfcc87c142d22a26029967cfbfb1baf1f5..3c7a6e58fdbb99b2f676e543695e1f185b6befaf 100644
--- a/arch/arm/src/lc823450/lc823450_cpuidlestack.c
+++ b/arch/arm/src/lc823450/lc823450_cpuidlestack.c
@@ -82,7 +82,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
* the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - cpu: CPU index that indicates which CPU the IDLE task is
* being created for.
* - tcb: The TCB of new CPU IDLE task
diff --git a/arch/arm/src/lc823450/lc823450_i2s.c b/arch/arm/src/lc823450/lc823450_i2s.c
index 3eced5cb4f246d282cf4b122b2ac7adf91330c6e..2b993d6a1c988ecea256f04f99a1e1559a5e604b 100644
--- a/arch/arm/src/lc823450/lc823450_i2s.c
+++ b/arch/arm/src/lc823450/lc823450_i2s.c
@@ -45,12 +45,17 @@
#include
#include
+#include
#include
#include
#include
#include
#include
+#ifdef CONFIG_SMP
+# include
+#endif
+
#include "up_arch.h"
#include "lc823450_dma.h"
#include "lc823450_i2s.h"
@@ -460,8 +465,32 @@ FAR struct i2s_dev_s *lc823450_i2sdev_initialize(void)
nxsem_init(&_sem_txdma, 0, 0);
nxsem_init(&_sem_buf_under, 0, 0);
+#ifdef CONFIG_SMP
+ cpu_set_t cpuset0;
+ cpu_set_t cpuset1;
+
+ CPU_ZERO(&cpuset1);
+ CPU_SET(0, &cpuset1);
+
+ /* Backup the current affinity */
+
+ (void)nxsched_getaffinity(getpid(), sizeof(cpuset0), &cpuset0);
+
+ /* Set the new affinity which assigns to CPU0 */
+
+ (void)nxsched_setaffinity(getpid(), sizeof(cpuset1), &cpuset1);
+ nxsig_usleep(10 * 1000);
+#endif
+
irq_attach(LC823450_IRQ_AUDIOBUF0, _i2s_isr, NULL);
+#ifdef CONFIG_SMP
+ /* Restore the original affinity */
+
+ (void)nxsched_setaffinity(getpid(), sizeof(cpuset0), &cpuset0);
+ nxsig_usleep(10 * 1000);
+#endif
+
/* Enable IRQ for Audio Buffer */
up_enable_irq(LC823450_IRQ_AUDIOBUF0);
diff --git a/arch/arm/src/lc823450/lc823450_irq.c b/arch/arm/src/lc823450/lc823450_irq.c
index 9339f7cd632a291821f2668b6d3b1ab27d707cbc..bd159ef545e6c25a551e76e8ffd388c81530d88d 100644
--- a/arch/arm/src/lc823450/lc823450_irq.c
+++ b/arch/arm/src/lc823450/lc823450_irq.c
@@ -711,7 +711,9 @@ void up_ack_irq(int irq)
#ifdef CONFIG_SMP
if (irq > LC823450_IRQ_LPDSP0 && 1 == up_cpu_index())
{
- irqwarn("*** warning irq(%d) handled on CPU1.");
+ /* IRQ should be handled on CPU0 */
+
+ ASSERT(false);
}
#endif
diff --git a/arch/arm/src/lc823450/lc823450_sdc.c b/arch/arm/src/lc823450/lc823450_sdc.c
index b0f0a357e2e299ce1cff0d3d63df6584e1c7438f..e47ab04dcb6258ec69d5ba4139d1ae15dfa33c98 100644
--- a/arch/arm/src/lc823450/lc823450_sdc.c
+++ b/arch/arm/src/lc823450/lc823450_sdc.c
@@ -355,7 +355,9 @@ int lc823450_sdc_setclock(uint32_t ch, uint32_t limitclk, uint32_t sysclk)
/****************************************************************************
* Name: lc823450_sdc_refmediatype
*
- * Return Values: 0(sd), 1(emmc)
+ * Returned Value:
+ * 0(sd), 1(emmc)
+ *
****************************************************************************/
int lc823450_sdc_refmediatype(uint32_t ch)
diff --git a/arch/arm/src/lc823450/lc823450_spi.c b/arch/arm/src/lc823450/lc823450_spi.c
index 038351d79a8c781eee8ed63d94c0bc9f0c33113f..51451b6001db2b9691c4e2a4a5987227159ef717 100644
--- a/arch/arm/src/lc823450/lc823450_spi.c
+++ b/arch/arm/src/lc823450/lc823450_spi.c
@@ -512,7 +512,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
* Description:
* Initialize the selected SPI port.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lc823450/lc823450_syscontrol.c b/arch/arm/src/lc823450/lc823450_syscontrol.c
index 82e6c2ee01885489de549b52033781fe0b4087d2..cd5458729b4cc581f358112d322bcf11c4238a21 100644
--- a/arch/arm/src/lc823450/lc823450_syscontrol.c
+++ b/arch/arm/src/lc823450/lc823450_syscontrol.c
@@ -102,7 +102,7 @@ uint32_t get_cpu_ver(void)
/****************************************************************************
* Name: mod_stby_regs
*
- * Input parameters:
+ * Input Parameters:
* enabits : specify regions to be enabled
* disbits : specify regions to be disabled
*
diff --git a/arch/arm/src/lc823450/lc823450_wdt.c b/arch/arm/src/lc823450/lc823450_wdt.c
index 80f7b49c2153e034f5cc5d49ad76e60e2e01c9a2..cdd351c095ca5c2c7b56703418e0c891bf8313be 100644
--- a/arch/arm/src/lc823450/lc823450_wdt.c
+++ b/arch/arm/src/lc823450/lc823450_wdt.c
@@ -182,7 +182,7 @@ static void wdg_work_func(void *arg)
* Input Parameters:
* Usual interrupt handler arguments.
*
- * Returned Values:
+ * Returned Value:
* Always returns OK.
*
****************************************************************************/
@@ -223,7 +223,7 @@ static int lc823450_wdt_interrupt(int irq, FAR void *context, FAR void *arg)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -246,7 +246,7 @@ static int lc823450_wdt_start(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -271,7 +271,7 @@ static int lc823450_wdt_stop(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -299,7 +299,7 @@ static int lc823450_wdt_keepalive(FAR struct watchdog_lowerhalf_s *lower)
* driver state structure.
* stawtus - The location to return the watchdog status information.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -362,7 +362,7 @@ static int lc823450_wdt_getstatus(FAR struct watchdog_lowerhalf_s *lower,
* driver state structure.
* timeout - The new timeout value in millisecnds.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -430,7 +430,7 @@ static int lc823450_wdt_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* function pointer is NULL, then the reset-on-expiration
* behavior is restored,
*
- * Returned Values:
+ * Returned Value:
* The previous watchdog expiration function pointer or NULL is there was
* no previous function pointer, i.e., if the previous behavior was
* reset-on-expiration (NULL is also returned if an error occurs).
@@ -496,7 +496,7 @@ static xcpt_t lc823450_wdt_capture(FAR struct watchdog_lowerhalf_s *lower,
* interpretation of this argument depends on the particular
* command.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -526,7 +526,7 @@ static int lc823450_wdt_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
* Input Parameters:
* None
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/lpc11xx/lpc11_i2c.c b/arch/arm/src/lpc11xx/lpc11_i2c.c
index 1c94939da92933f9d35f98c0ef6e26059b17c0a5..5873a18ff3a556ae502377da6382a61015891bc1 100644
--- a/arch/arm/src/lpc11xx/lpc11_i2c.c
+++ b/arch/arm/src/lpc11xx/lpc11_i2c.c
@@ -215,7 +215,8 @@ static int lpc11_i2c_start(struct lpc11_i2cdev_s *priv)
priv->base + LPC11_I2C_CONCLR_OFFSET);
putreg32(I2C_CONSET_STA, priv->base + LPC11_I2C_CONSET_OFFSET);
- wd_start(priv->timeout, I2C_TIMEOUT, lpc11_i2c_timeout, 1, (uint32_t)priv);
+ (void)wd_start(priv->timeout, I2C_TIMEOUT, lpc11_i2c_timeout, 1,
+ (uint32_t)priv);
nxsem_wait(&priv->wait);
wd_cancel(priv->timeout);
diff --git a/arch/arm/src/lpc11xx/lpc11_i2c.h b/arch/arm/src/lpc11xx/lpc11_i2c.h
index a9bc6fa3f75fd87660a3fb5d34fd84042a157ae4..cd739be1a3a4c76837a8b3eaf71b498d9a0797ae 100644
--- a/arch/arm/src/lpc11xx/lpc11_i2c.h
+++ b/arch/arm/src/lpc11xx/lpc11_i2c.h
@@ -57,7 +57,7 @@
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
@@ -73,7 +73,7 @@ FAR struct i2c_master_s *lpc11_i2cbus_initialize(int port);
* Description:
* De-initialize the selected I2C port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the lpc11_i2cbus_initialize()
*
* Returned Value:
diff --git a/arch/arm/src/lpc11xx/lpc11_serial.c b/arch/arm/src/lpc11xx/lpc11_serial.c
index 941a4475b4b148195b15b37bab2fcea93e153313..4799e4ed514f03d524f7f2977b0213ebee0a75bf 100644
--- a/arch/arm/src/lpc11xx/lpc11_serial.c
+++ b/arch/arm/src/lpc11xx/lpc11_serial.c
@@ -362,7 +362,7 @@ static inline void lpc11_uart0config(void)
/************************************************************************************
* Name: lpc11_uartdl
*
- * Descrption:
+ * Description:
* Select a divider to produce the BAUD from the UART PCLK.
*
* BAUD = PCLK / (16 * DL), or
diff --git a/arch/arm/src/lpc11xx/lpc11_spi.c b/arch/arm/src/lpc11xx/lpc11_spi.c
index 363cd6466adde7add1322a675226347c623546ea..e1bb8e0d6cad1d8dab1e697c9619aa59635bcbd9 100644
--- a/arch/arm/src/lpc11xx/lpc11_spi.c
+++ b/arch/arm/src/lpc11xx/lpc11_spi.c
@@ -526,7 +526,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
* Description:
* Initialize the selected SPI port.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lpc11xx/lpc11_spi.h b/arch/arm/src/lpc11xx/lpc11_spi.h
index 1a6786d2180e012ee2f0fcf6657d8e8e4a0f76d0..30ee2bbecff8673b7e1121910ec9705b6e93e8d7 100644
--- a/arch/arm/src/lpc11xx/lpc11_spi.h
+++ b/arch/arm/src/lpc11xx/lpc11_spi.h
@@ -76,7 +76,7 @@ extern "C"
* Description:
* Initialize the selected SPI port.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lpc11xx/lpc11_ssp.c b/arch/arm/src/lpc11xx/lpc11_ssp.c
index 32cccc29f36ff0440a3b5ad16800b5930a03dcc1..c0c1498f7e6cb59ab0a871910f5827c708919245 100644
--- a/arch/arm/src/lpc11xx/lpc11_ssp.c
+++ b/arch/arm/src/lpc11xx/lpc11_ssp.c
@@ -776,7 +776,7 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
* Description:
* Initialize the SSP0
*
- * Input Parameter:
+ * Input Parameters:
* None
*
* Returned Value:
@@ -830,7 +830,7 @@ static inline FAR struct lpc11_sspdev_s *lpc11_ssp0initialize(void)
* Description:
* Initialize the SSP1
*
- * Input Parameter:
+ * Input Parameters:
* None
*
* Returned Value:
@@ -884,7 +884,7 @@ static inline FAR struct lpc11_sspdev_s *lpc11_ssp1initialize(void)
* Description:
* Initialize the SSP2
*
- * Input Parameter:
+ * Input Parameters:
* None
*
* Returned Value:
@@ -941,7 +941,7 @@ static inline FAR struct lpc11_sspdev_s *lpc11_ssp2initialize(void)
* Description:
* Initialize the selected SSP port.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lpc11xx/lpc11_ssp.h b/arch/arm/src/lpc11xx/lpc11_ssp.h
index f117b1cf034d6b23a5545888779fec7280ccee26..825c67faa3afffbd430f71363baf7d010e454a9f 100644
--- a/arch/arm/src/lpc11xx/lpc11_ssp.h
+++ b/arch/arm/src/lpc11xx/lpc11_ssp.h
@@ -76,7 +76,7 @@ extern "C"
* Description:
* Initialize the selected SSP port.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lpc11xx/lpc11_timer.c b/arch/arm/src/lpc11xx/lpc11_timer.c
index a9ce65a073a57645e8953559dbad8e060657a096..75d3d334a43234a244a15297f44ff2132d1a2d8e 100644
--- a/arch/arm/src/lpc11xx/lpc11_timer.c
+++ b/arch/arm/src/lpc11xx/lpc11_timer.c
@@ -214,7 +214,7 @@ static void timer_putreg(struct lpc11_timer_s *priv, int offset,
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the PWM block status
*
* Returned Value:
@@ -256,7 +256,7 @@ static void timer_dumpregs(struct lpc11_timer_s *priv, FAR const char *msg)
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -291,7 +291,7 @@ static int timer_timer(FAR struct lpc11_timer_s *priv,
* Description:
* Handle timer interrupts.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -325,7 +325,7 @@ static int timer_interrupt(struct lpc11_timer_s *priv)
* Description:
* Handle timer 1 and 8 interrupts.
*
- * Input parameters:
+ * Input Parameters:
* Standard NuttX interrupt inputs
*
* Returned Value:
@@ -348,7 +348,7 @@ static int timer_tim1interrupt(int irq, void *context)
* should configure and initialize the device so that it is ready for use.
* It should not, however, output pulses until the start method is called.
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -436,7 +436,7 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev)
* stop pulsed output, free any resources, disable the timer hardware, and
* put the system into the lowest possible power usage state
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half TIMER driver state structure
*
* Returned Value:
@@ -462,7 +462,7 @@ static int timer_shutdown(FAR struct pwm_lowerhalf_s *dev)
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half TIMER driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -484,7 +484,7 @@ static int timer_start(FAR struct pwm_lowerhalf_s *dev,
* Description:
* Stop the pulsed output and reset the timer resources
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half TIMER driver state structure
*
* Returned Value:
@@ -542,7 +542,7 @@ static int timer_stop(FAR struct pwm_lowerhalf_s *dev)
* Description:
* Lower-half logic may support platform-specific ioctl commands
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half TIMER driver state structure
* cmd - The ioctl command
* arg - The argument accompanying the ioctl command
diff --git a/arch/arm/src/lpc17xx/Make.defs b/arch/arm/src/lpc17xx/Make.defs
index 115a3222a2b19fba204dac39bef454b796b03e02..c164c95f13f6ff291f370d1b2a163bc29c892d96 100644
--- a/arch/arm/src/lpc17xx/Make.defs
+++ b/arch/arm/src/lpc17xx/Make.defs
@@ -47,7 +47,7 @@ CMN_UASRCS =
CMN_UCSRCS =
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
-CMN_ASRCS += up_testset.S vfork.S
+CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S
CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c
CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_initialize.c up_memfault.c
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_uart.h b/arch/arm/src/lpc17xx/chip/lpc17_uart.h
index d7706561cd8a31abf94b07c317582f00d1255041..478c18b70a21cbbd06e0377b7d46bcbf5c62de9c 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_uart.h
+++ b/arch/arm/src/lpc17xx/chip/lpc17_uart.h
@@ -342,7 +342,7 @@
#define UART_FDR_DIVADDVAL_SHIFT (0) /* Bits 0-3: Baud-rate generation pre-scaler divisor value */
#define UART_FDR_DIVADDVAL_MASK (15 << UART_FDR_DIVADDVAL_SHIFT)
-#define UART_FDR_MULVAL_SHIFT (3) /* Bits 4-7 Baud-rate pre-scaler multiplier value */
+#define UART_FDR_MULVAL_SHIFT (4) /* Bits 4-7 Baud-rate pre-scaler multiplier value */
#define UART_FDR_MULVAL_MASK (15 << UART_FDR_MULVAL_SHIFT)
/* Bits 8-31: Reserved */
/* TER Transmit Enable Register (all) */
diff --git a/arch/arm/src/lpc17xx/lpc17_can.c b/arch/arm/src/lpc17xx/lpc17_can.c
index 94f1987280c41aeadc4ee8ad8c7994231d2be2e5..d7e8fcc461be15152fe07b1593e0457a9529abf0 100644
--- a/arch/arm/src/lpc17xx/lpc17_can.c
+++ b/arch/arm/src/lpc17xx/lpc17_can.c
@@ -1109,7 +1109,7 @@ static int can12_interrupt(int irq, void *context, FAR void *arg)
* Where:
* Tcan is the period of the APB clock (PCLK = CCLK / CONFIG_CAN1_DIVISOR).
*
- * Input Parameter:
+ * Input Parameters:
* priv - A reference to the CAN block status
*
* Returned Value:
@@ -1210,7 +1210,7 @@ static int can_bittiming(struct up_dev_s *priv)
* Description:
* Initialize the selected can port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple can interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lpc17xx/lpc17_can.h b/arch/arm/src/lpc17xx/lpc17_can.h
index e15eaced5a5aa02cb8d9bf787523c9f2480be6d7..2cbb8014a9f8e1c9f3803018e39e40f2a2d09c00 100644
--- a/arch/arm/src/lpc17xx/lpc17_can.h
+++ b/arch/arm/src/lpc17xx/lpc17_can.h
@@ -71,7 +71,7 @@ extern "C"
* Description:
* Initialize the selected can port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple can interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.c b/arch/arm/src/lpc17xx/lpc17_ethernet.c
index dd1c05d0d143f9d45a2cd6a1e6008314192cf1ed..196b15bab83b74e75e5167bb47f4581d2be48e67 100644
--- a/arch/arm/src/lpc17xx/lpc17_ethernet.c
+++ b/arch/arm/src/lpc17xx/lpc17_ethernet.c
@@ -3056,7 +3056,7 @@ static inline int lpc17_ethinitialize(int intf)
priv->lp_irq = ??; /* Ethernet controller IRQ number */
#endif
- /* Create a watchdog for timing polling for and timing of transmisstions */
+ /* Create a watchdog for timing polling for and timing of transmissions */
priv->lp_txpoll = wd_create(); /* Create periodic poll timer */
priv->lp_txtimeout = wd_create(); /* Create TX timeout timer */
diff --git a/arch/arm/src/lpc17xx/lpc17_i2c.c b/arch/arm/src/lpc17xx/lpc17_i2c.c
index 579e943336af10724438a568977f821cfdffed26..522afae6836f127cde0332a694b376efa9d5e473 100644
--- a/arch/arm/src/lpc17xx/lpc17_i2c.c
+++ b/arch/arm/src/lpc17xx/lpc17_i2c.c
@@ -215,7 +215,8 @@ static int lpc17_i2c_start(struct lpc17_i2cdev_s *priv)
priv->base + LPC17_I2C_CONCLR_OFFSET);
putreg32(I2C_CONSET_STA, priv->base + LPC17_I2C_CONSET_OFFSET);
- wd_start(priv->timeout, I2C_TIMEOUT, lpc17_i2c_timeout, 1, (uint32_t)priv);
+ (void)wd_start(priv->timeout, I2C_TIMEOUT, lpc17_i2c_timeout, 1,
+ (uint32_t)priv);
nxsem_wait(&priv->wait);
wd_cancel(priv->timeout);
diff --git a/arch/arm/src/lpc17xx/lpc17_i2c.h b/arch/arm/src/lpc17xx/lpc17_i2c.h
index a7a6322461940cbcc88af415d024d38f12a82437..044f0560c778ba5aaa2941e51b65a963c11cc8ec 100644
--- a/arch/arm/src/lpc17xx/lpc17_i2c.h
+++ b/arch/arm/src/lpc17xx/lpc17_i2c.h
@@ -57,7 +57,7 @@
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
@@ -73,7 +73,7 @@ FAR struct i2c_master_s *lpc17_i2cbus_initialize(int port);
* Description:
* De-initialize the selected I2C port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the lpc17_i2cbus_initialize()
*
* Returned Value:
diff --git a/arch/arm/src/lpc17xx/lpc17_lcd.c b/arch/arm/src/lpc17xx/lpc17_lcd.c
index 90332fc12e9d072bde96e8e135d4deea28650b12..e7aebe109fa6e577d0d442f8878708cda7f1476f 100644
--- a/arch/arm/src/lpc17xx/lpc17_lcd.c
+++ b/arch/arm/src/lpc17xx/lpc17_lcd.c
@@ -458,7 +458,7 @@ static int lpc17_setcursor(FAR struct fb_vtable_s *vtable,
* Description:
* Initialize the framebuffer video hardware associated with the display.
*
- * Input parameters:
+ * Input Parameters:
* display - In the case of hardware with multiple displays, this
* specifies the display. Normally this is zero.
*
@@ -717,7 +717,7 @@ int up_fbinitialize(int display)
* Return a a reference to the framebuffer object for the specified video
* plane of the specified plane. Many OSDs support multiple planes of video.
*
- * Input parameters:
+ * Input Parameters:
* display - In the case of hardware with multiple displays, this
* specifies the display. Normally this is zero.
* vplane - Identifies the plane being queried.
diff --git a/arch/arm/src/lpc17xx/lpc17_lowputc.c b/arch/arm/src/lpc17xx/lpc17_lowputc.c
index 3670014588087c8175003b8407a837f871707969..8f163f3440383511235cbd377140cdfe9493ce52 100644
--- a/arch/arm/src/lpc17xx/lpc17_lowputc.c
+++ b/arch/arm/src/lpc17xx/lpc17_lowputc.c
@@ -389,6 +389,13 @@ void lpc17_lowsetup(void)
putreg32(UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8,
CONSOLE_BASE + LPC17_UART_FCR_OFFSET);
+ /* Disable FDR (fractional divider),
+ * ignored by baudrate calculation => has to be disabled
+ */
+
+ putreg32((1 << UART_FDR_MULVAL_SHIFT) + (0 << UART_FDR_DIVADDVAL_SHIFT),
+ CONSOLE_BASE + LPC17_UART_FDR_OFFSET);
+
/* Set up the LCR and set DLAB=1 */
putreg32(CONSOLE_LCR_VALUE | UART_LCR_DLAB,
diff --git a/arch/arm/src/lpc17xx/lpc17_mcpwm.c b/arch/arm/src/lpc17xx/lpc17_mcpwm.c
index db0d1a9d67de95932697df6894bc0a8bc6e6ff23..c076a10ce5eb6f820fdc9a50ee717f97543a34b8 100644
--- a/arch/arm/src/lpc17xx/lpc17_mcpwm.c
+++ b/arch/arm/src/lpc17xx/lpc17_mcpwm.c
@@ -215,7 +215,7 @@ static void mcpwm_putreg(struct lpc17_mcpwmtimer_s *priv, int offset, uint32_t v
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the PWM block status
*
* Returned Value:
@@ -258,7 +258,7 @@ static void mcpwm_dumpregs(FAR struct lpc17_mcpwmtimer_s *priv,
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -290,7 +290,7 @@ static int mcpwm_timer(FAR struct lpc17_mcpwmtimer_s *priv,
* Description:
* Handle timer interrupts.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -324,7 +324,7 @@ static int mcpwm_interrupt(struct lpc17_mcpwmtimer_s *priv)
* Description:
* Handle timer 1 and 8 interrupts.
*
- * Input parameters:
+ * Input Parameters:
* Standard NuttX interrupt inputs
*
* Returned Value:
@@ -343,7 +343,7 @@ static int mcpwm_tim1interrupt(int irq, void *context)
* Description:
* Enable or disable APB clock for the timer peripheral
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* on - Enable clock if 'on' is 'true' and disable if 'false'
*
@@ -387,7 +387,7 @@ static void mcpwm_set_apb_clock(FAR struct lpc17_mcpwmtimer_s *priv, bool on)
* should configure and initialize the device so that it is ready for use.
* It should not, however, output pulses until the start method is called.
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -488,7 +488,7 @@ static int mcpwm_setup(FAR struct pwm_lowerhalf_s *dev)
* stop pulsed output, free any resources, disable the timer hardware, and
* put the system into the lowest possible power usage state
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -514,7 +514,7 @@ static int mcpwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -536,7 +536,7 @@ static int mcpwm_start(FAR struct pwm_lowerhalf_s *dev,
* Description:
* Stop the pulsed output and reset the timer resources
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -594,7 +594,7 @@ static int mcpwm_stop(FAR struct pwm_lowerhalf_s *dev)
* Description:
* Lower-half logic may support platform-specific ioctl commands
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* cmd - The ioctl command
* arg - The argument accompanying the ioctl command
diff --git a/arch/arm/src/lpc17xx/lpc17_pwm.c b/arch/arm/src/lpc17xx/lpc17_pwm.c
index df3be30a74a95a79911ea2983c238f66a6764b7a..f28c0996267123090724dd1d56802c68ae679c99 100644
--- a/arch/arm/src/lpc17xx/lpc17_pwm.c
+++ b/arch/arm/src/lpc17xx/lpc17_pwm.c
@@ -231,7 +231,7 @@ static void pwm_putreg(struct lpc17_pwmtimer_s *priv, int offset, uint32_t value
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the PWM block status
*
* Returned Value:
@@ -273,7 +273,7 @@ static void pwm_dumpregs(struct lpc17_pwmtimer_s *priv, FAR const char *msg)
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -308,7 +308,7 @@ static int pwm_timer(FAR struct lpc17_pwmtimer_s *priv,
* Description:
* Handle timer interrupts.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -342,7 +342,7 @@ static int pwm_interrupt(struct lpc17_pwmtimer_s *priv)
* Description:
* Handle timer 1 and 8 interrupts.
*
- * Input parameters:
+ * Input Parameters:
* Standard NuttX interrupt inputs
*
* Returned Value:
@@ -361,7 +361,7 @@ static int pwm_tim1interrupt(int irq, void *context, FAR void *arg)
* Description:
* Enable or disable APB clock for the timer peripheral
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* on - Enable clock if 'on' is 'true' and disable if 'false'
*
@@ -405,7 +405,7 @@ static void pwm_set_apb_clock(FAR struct lpc17_pwmtimer_s *priv, bool on)
* should configure and initialize the device so that it is ready for use.
* It should not, however, output pulses until the start method is called.
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -459,7 +459,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
* stop pulsed output, free any resources, disable the timer hardware, and
* put the system into the lowest possible power usage state
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -485,7 +485,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -507,7 +507,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
* Description:
* Stop the pulsed output and reset the timer resources
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -565,7 +565,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
* Description:
* Lower-half logic may support platform-specific ioctl commands
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* cmd - The ioctl command
* arg - The argument accompanying the ioctl command
diff --git a/arch/arm/src/lpc17xx/lpc17_sdcard.c b/arch/arm/src/lpc17xx/lpc17_sdcard.c
index 3d7fdffe705a9378360909c0359960670a714784..1d21e582c5822e7ebc0e998b2b41ff63e7801d6f 100644
--- a/arch/arm/src/lpc17xx/lpc17_sdcard.c
+++ b/arch/arm/src/lpc17xx/lpc17_sdcard.c
@@ -2307,7 +2307,7 @@ static sdio_eventset_t lpc17_eventwait(FAR struct sdio_dev_s *dev,
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay, (wdentry_t)lpc17_eventtimeout,
1, (uint32_t)priv);
- if (ret != OK)
+ if (ret < 0)
{
mcerr("ERROR: wd_start failed: %d\n", ret);
}
@@ -2701,7 +2701,7 @@ static void lpc17_default(void)
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SD card interface structure. NULL is returned on failures.
*
****************************************************************************/
@@ -2787,7 +2787,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -2833,7 +2833,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
* dev - An instance of the SD card driver device state structure.
* wrprotect - true is a card is writeprotected.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/lpc17xx/lpc17_sdcard.h b/arch/arm/src/lpc17xx/lpc17_sdcard.h
index 520175ec25c08347e5f7fe6e948102cb7f136e54..82f94264c7c2009da5f96ed23803758d62bd4532 100644
--- a/arch/arm/src/lpc17xx/lpc17_sdcard.h
+++ b/arch/arm/src/lpc17xx/lpc17_sdcard.h
@@ -71,7 +71,7 @@ extern "C"
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
@@ -93,7 +93,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno);
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -111,7 +111,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is writeprotected.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/lpc17xx/lpc17_serial.c b/arch/arm/src/lpc17xx/lpc17_serial.c
index 9c13a06d4a1986fdb323619b63eac69945ed8724..c321e23eb2f3c3294bdff2f461ba09eb45e7e065 100644
--- a/arch/arm/src/lpc17xx/lpc17_serial.c
+++ b/arch/arm/src/lpc17xx/lpc17_serial.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc17xx/lpc17_serial.c
*
- * Copyright (C) 2010-2013, 2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2010-2013, 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -550,7 +550,7 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
/************************************************************************************
* Name: lpc17_uartcclkdiv
*
- * Descrption:
+ * Description:
* Select a CCLK divider to produce the UART PCLK. The stratey is to select the
* smallest divisor that results in an solution within range of the 16-bit
* DLM and DLL divisor:
@@ -667,7 +667,7 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud)
/************************************************************************************
* Name: lpc17_uart0config, uart1config, uart2config, and uart3config
*
- * Descrption:
+ * Description:
* Configure the UART. UART0/1/2/3 peripherals are configured using the following
* registers:
*
@@ -815,7 +815,7 @@ static inline void lpc17_uart3config(void)
/************************************************************************************
* Name: lpc17_uartdl
*
- * Descrption:
+ * Description:
* Select a divider to produce the BAUD from the UART PCLK.
*
* BAUD = PCLK / (16 * DL), or
@@ -920,6 +920,13 @@ static int up_setup(struct uart_dev_s *dev)
lcr |= (UART_LCR_PE | UART_LCR_PS_EVEN);
}
+ /* Disable FDR (fractional divider),
+ * ignored by baudrate calculation => has to be disabled
+ */
+
+ up_serialout(priv, LPC17_UART_FDR_OFFSET,
+ (1 << UART_FDR_MULVAL_SHIFT) + (0 << UART_FDR_DIVADDVAL_SHIFT));
+
/* Enter DLAB=1 */
up_serialout(priv, LPC17_UART_LCR_OFFSET, (lcr | UART_LCR_DLAB));
diff --git a/arch/arm/src/lpc17xx/lpc17_spi.c b/arch/arm/src/lpc17xx/lpc17_spi.c
index 60deac4fb54f3613e2126b79866f52c33102f862..f653df2d3681914def2e82eecec6b9840c5418d3 100644
--- a/arch/arm/src/lpc17xx/lpc17_spi.c
+++ b/arch/arm/src/lpc17xx/lpc17_spi.c
@@ -518,7 +518,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
* Description:
* Initialize the selected SPI port.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lpc17xx/lpc17_spi.h b/arch/arm/src/lpc17xx/lpc17_spi.h
index 27d9ba8bb935e429e90d6ebc9aed7b28672c96f4..f0be0e9978184178194c3ae0714006151e83bdf0 100644
--- a/arch/arm/src/lpc17xx/lpc17_spi.h
+++ b/arch/arm/src/lpc17xx/lpc17_spi.h
@@ -78,7 +78,7 @@ struct spi_dev_s; /* Forward reference */
* Description:
* Initialize the selected SPI port.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lpc17xx/lpc17_ssp.c b/arch/arm/src/lpc17xx/lpc17_ssp.c
index 98220105dc0bb0f01df1ae9640ceb2dc1d70c8b5..af8fb4bc422a30f907ba6a47ee6bd2bf6bcbd95c 100644
--- a/arch/arm/src/lpc17xx/lpc17_ssp.c
+++ b/arch/arm/src/lpc17xx/lpc17_ssp.c
@@ -765,7 +765,7 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
* Description:
* Initialize the SSP0
*
- * Input Parameter:
+ * Input Parameters:
* None
*
* Returned Value:
@@ -819,7 +819,7 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp0initialize(void)
* Description:
* Initialize the SSP1
*
- * Input Parameter:
+ * Input Parameters:
* None
*
* Returned Value:
@@ -873,7 +873,7 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp1initialize(void)
* Description:
* Initialize the SSP2
*
- * Input Parameter:
+ * Input Parameters:
* None
*
* Returned Value:
@@ -930,7 +930,7 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp2initialize(void)
* Description:
* Initialize the selected SSP port.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lpc17xx/lpc17_ssp.h b/arch/arm/src/lpc17xx/lpc17_ssp.h
index c679206ca1e475b6596e59759b14d47975fb3723..dd8ba3c766f3c2d5dc76965c58d8e1caf07bebd7 100644
--- a/arch/arm/src/lpc17xx/lpc17_ssp.h
+++ b/arch/arm/src/lpc17xx/lpc17_ssp.h
@@ -76,7 +76,7 @@ extern "C"
* Description:
* Initialize the selected SSP port.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lpc17xx/lpc17_timer.c b/arch/arm/src/lpc17xx/lpc17_timer.c
index 434f416021ffaa6775ce31183ba8ba23eb94528f..8540d1b3862c2dde4fc560f03b40c837e810dc9d 100644
--- a/arch/arm/src/lpc17xx/lpc17_timer.c
+++ b/arch/arm/src/lpc17xx/lpc17_timer.c
@@ -215,7 +215,7 @@ static void timer_putreg(struct lpc17_timer_s *priv, int offset,
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the PWM block status
*
* Returned Value:
@@ -257,7 +257,7 @@ static void timer_dumpregs(struct lpc17_timer_s *priv, FAR const char *msg)
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -292,7 +292,7 @@ static int timer_timer(FAR struct lpc17_timer_s *priv,
* Description:
* Handle timer interrupts.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -326,7 +326,7 @@ static int timer_interrupt(struct lpc17_timer_s *priv)
* Description:
* Handle timer 1 and 8 interrupts.
*
- * Input parameters:
+ * Input Parameters:
* Standard NuttX interrupt inputs
*
* Returned Value:
@@ -349,7 +349,7 @@ static int timer_tim1interrupt(int irq, void *context)
* should configure and initialize the device so that it is ready for use.
* It should not, however, output pulses until the start method is called.
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -437,7 +437,7 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev)
* stop pulsed output, free any resources, disable the timer hardware, and
* put the system into the lowest possible power usage state
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half TIMER driver state structure
*
* Returned Value:
@@ -463,7 +463,7 @@ static int timer_shutdown(FAR struct pwm_lowerhalf_s *dev)
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half TIMER driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -485,7 +485,7 @@ static int timer_start(FAR struct pwm_lowerhalf_s *dev,
* Description:
* Stop the pulsed output and reset the timer resources
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half TIMER driver state structure
*
* Returned Value:
@@ -543,7 +543,7 @@ static int timer_stop(FAR struct pwm_lowerhalf_s *dev)
* Description:
* Lower-half logic may support platform-specific ioctl commands
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half TIMER driver state structure
* cmd - The ioctl command
* arg - The argument accompanying the ioctl command
diff --git a/arch/arm/src/lpc17xx/lpc17_usbhost.c b/arch/arm/src/lpc17xx/lpc17_usbhost.c
index fd51d9df2c45d3bd5f0529c0a6a9aaf90086decd..fb8abb6467be52b02081c154f3549fd1fb0d479f 100644
--- a/arch/arm/src/lpc17xx/lpc17_usbhost.c
+++ b/arch/arm/src/lpc17xx/lpc17_usbhost.c
@@ -1933,7 +1933,7 @@ static int lpc17_usbinterrupt(int irq, void *context, FAR void *arg)
* hport - The location to return the hub port descriptor that detected the
* connection related event.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success when a device in connected or
* disconnected. This function will not return until either (1) a device is
* connected or disconnect to/from any hub port or until (2) some failure
@@ -2029,7 +2029,7 @@ static int lpc17_wait(struct usbhost_connection_s *conn,
* hport - The descriptor of the hub port that has the newly connected
* device.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -2128,7 +2128,7 @@ static int lpc17_enumerate(FAR struct usbhost_connection_s *conn,
* mps (maxpacketsize) - The maximum number of bytes that can be sent to or
* received from the endpoint in a single data packet
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -2183,7 +2183,7 @@ static int lpc17_ep0configure(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -2339,7 +2339,7 @@ static int lpc17_epalloc(struct usbhost_driver_s *drvr,
* the class create() method.
* ep - The endpint to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -2422,7 +2422,7 @@ static int lpc17_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep)
* maxlen - The address of a memory location provided by the caller in which to
* return the maximum size of the allocated buffer memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -2468,7 +2468,7 @@ static int lpc17_alloc(struct usbhost_driver_s *drvr,
* the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -2508,7 +2508,7 @@ static int lpc17_free(struct usbhost_driver_s *drvr, uint8_t *buffer)
* return the allocated buffer memory address.
* buflen - The size of the buffer required.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -2553,7 +2553,7 @@ static int lpc17_ioalloc(struct usbhost_driver_s *drvr,
* the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -2600,7 +2600,7 @@ static int lpc17_iofree(struct usbhost_driver_s *drvr, uint8_t *buffer)
* NOTE: On an IN transaction, req and buffer may refer to the same allocated
* memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -2701,7 +2701,7 @@ static int lpc17_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
* (IN endpoint). buffer must have been allocated using DRVR_ALLOC
* buflen - The length of the data to be sent or received.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -2779,7 +2779,7 @@ static int lpc17_transfer_common(struct lpc17_usbhost_s *priv,
* buflen - The length of the data to be sent or received.
* alloc - The location to return the allocated DMA buffer.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -2851,7 +2851,7 @@ static int lpc17_dma_alloc(struct lpc17_usbhost_s *priv,
* buflen - The length of the data to be sent or received.
* alloc - The allocated DMA buffer to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -2913,7 +2913,7 @@ static void lpc17_dma_free(struct lpc17_usbhost_s *priv,
* (IN endpoint). buffer must have been allocated using DRVR_ALLOC
* buflen - The length of the data to be sent or received.
*
- * Returned Values:
+ * Returned Value:
* On success, a non-negative value is returned that indicates the number
* of bytes successfully transferred. On a failure, a negated errno value is
* returned that indicates the nature of the failure:
@@ -3087,7 +3087,7 @@ errout_with_sem:
* ep - The IN or OUT endpoint descriptor for the device endpoint on which the
* transfer was performed.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
@@ -3189,7 +3189,7 @@ static void lpc17_asynch_completion(struct lpc17_usbhost_s *priv,
* arg - The arbitrary parameter that will be passed to the callback function
* when the transfer completes.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3306,7 +3306,7 @@ errout_with_sem:
* ep - The IN or OUT endpoint descriptor for the device endpoint on which an
* asynchronous transfer should be transferred.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -3451,7 +3451,7 @@ static int lpc17_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
* related event
* connected - True: device connected; false: device disconnected
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -3502,7 +3502,7 @@ static int lpc17_connect(FAR struct usbhost_driver_s *drvr,
* hport - The port from which the device is being disconnected. Might be a port
* on a hub.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
@@ -3531,7 +3531,7 @@ static void lpc17_disconnect(struct usbhost_driver_s *drvr,
* Input Parameters:
* priv - private driver state instance.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/lpc214x/lpc214x_spi.h b/arch/arm/src/lpc214x/lpc214x_spi.h
index 69c94d89c0fc782290a96290d4c434e7fe0bbbb2..e4934d9d38c8b255bb0aec572850d61b6121961e 100644
--- a/arch/arm/src/lpc214x/lpc214x_spi.h
+++ b/arch/arm/src/lpc214x/lpc214x_spi.h
@@ -171,7 +171,7 @@ struct spi_dev_s; /* Forward reference */
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lpc2378/lpc23xx_i2c.c b/arch/arm/src/lpc2378/lpc23xx_i2c.c
index 00d44687ea300b5c8593993774ff4348c80293f8..2a99c2a084425a3cd133ce9fc970b686e43cf02b 100644
--- a/arch/arm/src/lpc2378/lpc23xx_i2c.c
+++ b/arch/arm/src/lpc2378/lpc23xx_i2c.c
@@ -220,7 +220,8 @@ static int lpc2378_i2c_start(struct lpc2378_i2cdev_s *priv)
priv->base + I2C_CONCLR_OFFSET);
putreg32(I2C_CONSET_STA, priv->base + I2C_CONSET_OFFSET);
- wd_start(priv->timeout, I2C_TIMEOUT, lpc2378_i2c_timeout, 1, (uint32_t)priv);
+ (void)wd_start(priv->timeout, I2C_TIMEOUT, lpc2378_i2c_timeout, 1,
+ (uint32_t)priv);
nxsem_wait(&priv->wait);
wd_cancel(priv->timeout);
diff --git a/arch/arm/src/lpc2378/lpc23xx_i2c.h b/arch/arm/src/lpc2378/lpc23xx_i2c.h
index 5658269f20ae834b3c7837825e6bee9d2a07e43d..1ae069c5f7699139937df1f3698da507f1cbae76 100644
--- a/arch/arm/src/lpc2378/lpc23xx_i2c.h
+++ b/arch/arm/src/lpc2378/lpc23xx_i2c.h
@@ -163,7 +163,7 @@
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
@@ -179,7 +179,7 @@ FAR struct i2c_master_s *lpc2378_i2cbus_initialize(int port);
* Description:
* De-initialize the selected I2C port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the lpc2378_i2cbus_initialize()
*
* Returned Value:
diff --git a/arch/arm/src/lpc2378/lpc23xx_io.c b/arch/arm/src/lpc2378/lpc23xx_io.c
index 94e7f99c548f23651f09a01c0a4ccde18a39c3c9..f871ce17f80a2133918f69aea36e08bd258afeb0 100644
--- a/arch/arm/src/lpc2378/lpc23xx_io.c
+++ b/arch/arm/src/lpc2378/lpc23xx_io.c
@@ -55,7 +55,8 @@
/****************************************************************************
* Name: IO_Init()
*
- * Descriptions: Initialize the target board before running the main()
+ * Description:
+ * Initialize the target board before running the main()
*
****************************************************************************/
diff --git a/arch/arm/src/lpc2378/lpc23xx_spi.c b/arch/arm/src/lpc2378/lpc23xx_spi.c
index bc7f46cf0727e4af83f59f24ac8925d729d9eb61..b9006f4e5ce67b9c9f4b3dde10605f6e44c684b7 100644
--- a/arch/arm/src/lpc2378/lpc23xx_spi.c
+++ b/arch/arm/src/lpc2378/lpc23xx_spi.c
@@ -525,7 +525,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lpc2378/lpc23xx_spi.h b/arch/arm/src/lpc2378/lpc23xx_spi.h
index 8b5fbda37c5b14db4acfcdad1094a32a85a106bd..280c2f44e20afee17003ccef5147f7c5111f6762 100644
--- a/arch/arm/src/lpc2378/lpc23xx_spi.h
+++ b/arch/arm/src/lpc2378/lpc23xx_spi.h
@@ -161,7 +161,7 @@ struct spi_dev_s; /* Forward reference */
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lpc31xx/lpc31.h b/arch/arm/src/lpc31xx/lpc31.h
index 00ce6b8e35c70801957df11c2a8601230bf93db3..ca3c0ad8fbd5e198c0f2c37e255e14bc46ad6d32 100644
--- a/arch/arm/src/lpc31xx/lpc31.h
+++ b/arch/arm/src/lpc31xx/lpc31.h
@@ -176,7 +176,7 @@ void lpc31_clockconfig(void);
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
@@ -315,7 +315,7 @@ void lpc31_usbhost_vbusdrive(int rhport, bool enable);
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
@@ -337,7 +337,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno);
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -355,7 +355,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is writeprotected.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/lpc31xx/lpc31_ehci.c b/arch/arm/src/lpc31xx/lpc31_ehci.c
index 26772ea81a510f7ace18e3c9efd5b0065270464a..6b90a1b2eb1ca82afc1ed9436a9d40a433be778b 100644
--- a/arch/arm/src/lpc31xx/lpc31_ehci.c
+++ b/arch/arm/src/lpc31xx/lpc31_ehci.c
@@ -2087,7 +2087,7 @@ static struct lpc31_qtd_s *lpc31_qtd_statusphase(uint32_t tokenbits)
*
* Assumption: The caller holds the EHCI exclsem.
*
- * Returned value:
+ * Returned Value:
* Zero (OK) is returned on success; a negated errno value is return on
* any failure.
*
@@ -2368,7 +2368,7 @@ errout_with_qh:
*
* Assumption: The caller holds the EHCI exclsem.
*
- * Returned value:
+ * Returned Value:
* Zero (OK) is returned on success; a negated errno value is return on
* any failure.
*
@@ -2475,7 +2475,7 @@ errout_with_qh:
* complete, but will be re-acquired when before returning. The state of
* EHCI resources could be very different upon return.
*
- * Returned value:
+ * Returned Value:
* On success, this function returns the number of bytes actually transferred.
* For control transfers, this size includes the size of the control request
* plus the size of the data (which could be short); For bulk transfers, this
@@ -2555,7 +2555,7 @@ static ssize_t lpc31_transfer_wait(struct lpc31_epinfo_s *epinfo)
* callback - The function to be called when the completes
* arg - An arbitrary argument that will be provided with the callback.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
@@ -2608,7 +2608,7 @@ static inline int lpc31_ioc_async_setup(struct lpc31_rhport_s *rhport,
* epinfo - The IN or OUT endpoint descriptor for the device endpoint on
* which the transfer was performed.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
@@ -3428,7 +3428,7 @@ static int lpc31_ehci_interrupt(int irq, FAR void *context, FAR void *arg)
* hport - The location to return the hub port descriptor that detected the
* connection related event.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success when a device in connected or
* disconnected. This function will not return until either (1) a device is
* connected or disconnect to/from any hub port or until (2) some failure
@@ -3530,7 +3530,7 @@ static int lpc31_wait(FAR struct usbhost_connection_s *conn,
* hport - The descriptor of the hub port that has the newly connected
* device.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3839,7 +3839,7 @@ static int lpc31_enumerate(FAR struct usbhost_connection_s *conn,
* maxpacketsize - The maximum number of bytes that can be sent to or
* received from the endpoint in a single data packet
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3882,7 +3882,7 @@ static int lpc31_ep0configure(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3965,7 +3965,7 @@ static int lpc31_epalloc(FAR struct usbhost_driver_s *drvr,
* the class create() method.
* ep - The endpint to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4010,7 +4010,7 @@ static int lpc31_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
* maxlen - The address of a memory location provided by the caller in which
* to return the maximum size of the allocated buffer memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4055,7 +4055,7 @@ static int lpc31_alloc(FAR struct usbhost_driver_s *drvr,
* to the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4092,7 +4092,7 @@ static int lpc31_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer)
* return the allocated buffer memory address.
* buflen - The size of the buffer required.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4131,7 +4131,7 @@ static int lpc31_ioalloc(FAR struct usbhost_driver_s *drvr, FAR uint8_t **buffer
* the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4176,7 +4176,7 @@ static int lpc31_iofree(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer)
* NOTE: On an IN transaction, req and buffer may refer to the same allocated
* memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4277,7 +4277,7 @@ static int lpc31_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
* (IN endpoint). buffer must have been allocated using DRVR_ALLOC
* buflen - The length of the data to be sent or received.
*
- * Returned Values:
+ * Returned Value:
* On success, a non-negative value is returned that indicates the number
* of bytes successfully transferred. On a failure, a negated errno value is
* returned that indicates the nature of the failure:
@@ -4387,7 +4387,7 @@ errout_with_sem:
* arg - The arbitrary parameter that will be passed to the callback function
* when the transfer completes.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4480,7 +4480,7 @@ errout_with_sem:
* ep - The IN or OUT endpoint descriptor for the device endpoint on which an
* asynchronous transfer should be transferred.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -4677,7 +4677,7 @@ errout_with_sem:
* related event
* connected - True: device connected; false: device disconnected
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -4728,7 +4728,7 @@ static int lpc31_connect(FAR struct usbhost_driver_s *drvr,
* hport - The port from which the device is being disconnected. Might be a port
* on a hub.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
diff --git a/arch/arm/src/lpc31xx/lpc31_i2c.c b/arch/arm/src/lpc31xx/lpc31_i2c.c
index c65d55c47125a0bee54cdb5cad8226b085480f14..b4ff05cd9d12229f33109f5bfe67d23f6d1a70cb 100644
--- a/arch/arm/src/lpc31xx/lpc31_i2c.c
+++ b/arch/arm/src/lpc31xx/lpc31_i2c.c
@@ -490,7 +490,7 @@ static int i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs
/* Start a watchdog to timeout the transfer if the bus is locked up... */
- wd_start(priv->timeout, I2C_TIMEOUT, i2c_timeout, 1, (uint32_t)priv);
+ (void)wd_start(priv->timeout, I2C_TIMEOUT, i2c_timeout, 1, (uint32_t)priv);
/* Wait for the transfer to complete */
diff --git a/arch/arm/src/lpc31xx/lpc31_i2c.h b/arch/arm/src/lpc31xx/lpc31_i2c.h
index 10280a577311f83d04b8875b43a37175ca793e2f..ac14998d2224a7c9bed3f6cc6b3582df68611bd4 100644
--- a/arch/arm/src/lpc31xx/lpc31_i2c.h
+++ b/arch/arm/src/lpc31xx/lpc31_i2c.h
@@ -206,7 +206,7 @@
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
@@ -222,7 +222,7 @@ FAR struct i2c_master_s *lpc31_i2cbus_initialize(int port);
* Description:
* De-initialize the selected I2C port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the lpc31_i2cbus_initialize()
*
* Returned Value:
diff --git a/arch/arm/src/lpc31xx/lpc31_spi.c b/arch/arm/src/lpc31xx/lpc31_spi.c
index d0275a502d21157f9e3048a3902551f0b1545d25..c4e18511638369831d19c6eba69a90f889d164a6 100644
--- a/arch/arm/src/lpc31xx/lpc31_spi.c
+++ b/arch/arm/src/lpc31xx/lpc31_spi.c
@@ -903,7 +903,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, size_t
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lpc43xx/Make.defs b/arch/arm/src/lpc43xx/Make.defs
index d5bd89123723dec372537e7e7dadd7e137ee7731..744768142c03909aaa28edf9f0fa24507f4fc01d 100644
--- a/arch/arm/src/lpc43xx/Make.defs
+++ b/arch/arm/src/lpc43xx/Make.defs
@@ -36,7 +36,7 @@
HEAD_ASRC =
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
-CMN_ASRCS += up_testset.S vfork.S
+CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S
CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c
CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c
diff --git a/arch/arm/src/lpc43xx/lpc43_can.c b/arch/arm/src/lpc43xx/lpc43_can.c
index 415a7b28efd163130bac8e6079c611b681dd0643..7013ffd6dd6aaafdd818c39a65e5ade3667e0c8e 100644
--- a/arch/arm/src/lpc43xx/lpc43_can.c
+++ b/arch/arm/src/lpc43xx/lpc43_can.c
@@ -1152,7 +1152,7 @@ static void can_setuprxobj(struct up_dev_s *priv)
* Where:
* Tcan is the period of the APB clock (PCLK = CCLK / CONFIG_CAN1_DIVISOR).
*
- * Input Parameter:
+ * Input Parameters:
* priv - A reference to the CAN block status
*
* Returned Value:
@@ -1210,7 +1210,7 @@ static int can_bittiming(struct up_dev_s *priv)
* Description:
* Initialize the selected can port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple can interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lpc43xx/lpc43_can.h b/arch/arm/src/lpc43xx/lpc43_can.h
index f321c9b72fa087ce403f8e48a75e92847a90b28d..37074c6df34cfd35d5389bf89d2908ae011cc5e0 100644
--- a/arch/arm/src/lpc43xx/lpc43_can.h
+++ b/arch/arm/src/lpc43xx/lpc43_can.h
@@ -64,7 +64,7 @@ extern "C"
* Description:
* Initialize the selected can port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple can interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lpc43xx/lpc43_ehci.c b/arch/arm/src/lpc43xx/lpc43_ehci.c
index 3b24b4f282e38b8a4bb32a82405aa389b262f444..3908fb1a8ee177d0c7cda2660123aff3be218e59 100644
--- a/arch/arm/src/lpc43xx/lpc43_ehci.c
+++ b/arch/arm/src/lpc43xx/lpc43_ehci.c
@@ -1971,7 +1971,7 @@ static struct lpc43_qtd_s *lpc43_qtd_statusphase(uint32_t tokenbits)
*
* Assumption: The caller holds the EHCI exclsem.
*
- * Returned value:
+ * Returned Value:
* Zero (OK) is returned on success; a negated errno value is return on
* any failure.
*
@@ -2251,7 +2251,7 @@ errout_with_qh:
*
* Assumption: The caller holds the EHCI exclsem.
*
- * Returned value:
+ * Returned Value:
* Zero (OK) is returned on success; a negated errno value is return on
* any failure.
*
@@ -2358,7 +2358,7 @@ errout_with_qh:
* complete, but will be re-acquired when before returning. The state of
* EHCI resources could be very different upon return.
*
- * Returned value:
+ * Returned Value:
* On success, this function returns the number of bytes actually transferred.
* For control transfers, this size includes the size of the control request
* plus the size of the data (which could be short); For bulk transfers, this
@@ -2420,7 +2420,7 @@ static ssize_t lpc43_transfer_wait(struct lpc43_epinfo_s *epinfo)
* callback - The function to be called when the completes
* arg - An arbitrary argument that will be provided with the callback.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
@@ -2473,7 +2473,7 @@ static inline int lpc43_ioc_async_setup(struct lpc43_rhport_s *rhport,
* epinfo - The IN or OUT endpoint descriptor for the device endpoint on
* which the transfer was performed.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
@@ -3265,7 +3265,7 @@ static int lpc43_ehci_interrupt(int irq, FAR void *context, FAR void *arg)
* hport - The location to return the hub port descriptor that detected the
* connection related event.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success when a device in connected or
* disconnected. This function will not return until either (1) a device is
* connected or disconnect to/from any hub port or until (2) some failure
@@ -3367,7 +3367,7 @@ static int lpc43_wait(FAR struct usbhost_connection_s *conn,
* hport - The descriptor of the hub port that has the newly connected
* device.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3676,7 +3676,7 @@ static int lpc43_enumerate(FAR struct usbhost_connection_s *conn,
* maxpacketsize - The maximum number of bytes that can be sent to or
* received from the endpoint in a single data packet
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3719,7 +3719,7 @@ static int lpc43_ep0configure(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3802,7 +3802,7 @@ static int lpc43_epalloc(FAR struct usbhost_driver_s *drvr,
* the class create() method.
* ep - The endpint to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3847,7 +3847,7 @@ static int lpc43_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
* maxlen - The address of a memory location provided by the caller in which
* to return the maximum size of the allocated buffer memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3889,7 +3889,7 @@ static int lpc43_alloc(FAR struct usbhost_driver_s *drvr,
* to the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3926,7 +3926,7 @@ static int lpc43_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer)
* return the allocated buffer memory address.
* buflen - The size of the buffer required.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3962,7 +3962,7 @@ static int lpc43_ioalloc(FAR struct usbhost_driver_s *drvr, FAR uint8_t **buffer
* the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4007,7 +4007,7 @@ static int lpc43_iofree(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer)
* NOTE: On an IN transaction, req and buffer may refer to the same allocated
* memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4108,7 +4108,7 @@ static int lpc43_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
* (IN endpoint). buffer must have been allocated using DRVR_ALLOC
* buflen - The length of the data to be sent or received.
*
- * Returned Values:
+ * Returned Value:
* On success, a non-negative value is returned that indicates the number
* of bytes successfully transferred. On a failure, a negated errno value is
* returned that indicates the nature of the failure:
@@ -4218,7 +4218,7 @@ errout_with_sem:
* arg - The arbitrary parameter that will be passed to the callback function
* when the transfer completes.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4311,7 +4311,7 @@ errout_with_sem:
* ep - The IN or OUT endpoint descriptor for the device endpoint on which an
* asynchronous transfer should be transferred.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -4508,7 +4508,7 @@ errout_with_sem:
* related event
* connected - True: device connected; false: device disconnected
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -4559,7 +4559,7 @@ static int lpc43_connect(FAR struct usbhost_driver_s *drvr,
* hport - The port from which the device is being disconnected. Might be a port
* on a hub.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c
index f5a9cb1e580215f2988447e8a629e9d314fafcf4..e598178811781f18b601b32594bdcbcc5d38eab2 100644
--- a/arch/arm/src/lpc43xx/lpc43_ethernet.c
+++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc43/lpc43_eth.c
*
- * Copyright (C) 2011-2015, 2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011-2015, 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -621,7 +621,7 @@ static int lpc43_addmac(struct net_driver_s *dev, FAR const uint8_t *mac);
#ifdef CONFIG_NET_IGMP
static int lpc43_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac);
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
static int lpc43_ioctl(struct net_driver_s *dev, int cmd,
unsigned long arg);
#endif
@@ -2744,16 +2744,17 @@ static void lpc43_rxdescinit(FAR struct lpc43_ethmac_s *priv)
*
****************************************************************************/
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
static int lpc43_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
{
-#ifdef CONFIG_ARCH_PHY_INTERRUPT
+#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
FAR struct lpc43_ethmac_s *priv = (FAR struct lpc43_ethmac_s *)dev->d_private;
#endif
int ret;
switch (cmd)
{
+#ifdef CONFIG_NETDEV_PHY_IOCTL
#ifdef CONFIG_ARCH_PHY_INTERRUPT
case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
@@ -2791,6 +2792,7 @@ static int lpc43_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
ret = lpc43_phywrite(req->phy_id, req->reg_num, req->val_in);
}
break;
+#endif /* ifdef CONFIG_NETDEV_PHY_IOCTL */
default:
ret = -ENOTTY;
@@ -2799,7 +2801,7 @@ static int lpc43_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
return ret;
}
-#endif /* CONFIG_NETDEV_PHY_IOCTL */
+#endif /* CONFIG_NETDEV_IOCTL */
/****************************************************************************
* Function: lpc43_phyintenable
@@ -3823,12 +3825,12 @@ static inline int lpc43_ethinitialize(void)
priv->dev.d_addmac = lpc43_addmac; /* Add multicast MAC address */
priv->dev.d_rmmac = lpc43_rmmac; /* Remove multicast MAC address */
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = lpc43_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void *)&g_lpc43ethmac; /* Used to recover private state from dev */
- /* Create a watchdog for timing polling for and timing of transmisstions */
+ /* Create a watchdog for timing polling for and timing of transmission */
priv->txpoll = wd_create(); /* Create periodic poll timer */
priv->txtimeout = wd_create(); /* Create TX timeout timer */
diff --git a/arch/arm/src/lpc43xx/lpc43_i2c.c b/arch/arm/src/lpc43xx/lpc43_i2c.c
index f613470a8f5a1313760576007e896699a4a48159..137a34f1f780a43db23418c810dae9f6173f5353 100644
--- a/arch/arm/src/lpc43xx/lpc43_i2c.c
+++ b/arch/arm/src/lpc43xx/lpc43_i2c.c
@@ -202,7 +202,8 @@ static int lpc43_i2c_start(struct lpc43_i2cdev_s *priv)
priv->base + LPC43_I2C_CONCLR_OFFSET);
putreg32(I2C_CONSET_STA, priv->base + LPC43_I2C_CONSET_OFFSET);
- wd_start(priv->timeout, I2C_TIMEOUT, lpc43_i2c_timeout, 1, (uint32_t)priv);
+ (void)wd_start(priv->timeout, I2C_TIMEOUT, lpc43_i2c_timeout, 1,
+ (uint32_t)priv);
nxsem_wait(&priv->wait);
wd_cancel(priv->timeout);
diff --git a/arch/arm/src/lpc43xx/lpc43_i2c.h b/arch/arm/src/lpc43xx/lpc43_i2c.h
index ae8d94a7f883e5f25654ebe699ab1be0379a6af8..224fbaa593e35cb07efcd12bc0b8e88a7a0d3f16 100644
--- a/arch/arm/src/lpc43xx/lpc43_i2c.h
+++ b/arch/arm/src/lpc43xx/lpc43_i2c.h
@@ -57,7 +57,7 @@
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
@@ -73,7 +73,7 @@ FAR struct i2c_master_s *lpc43_i2cbus_initialize(int port);
* Description:
* De-initialize the selected I2C port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the lpc43_i2cbus_initialize()
*
* Returned Value:
diff --git a/arch/arm/src/lpc43xx/lpc43_pinconfig.c b/arch/arm/src/lpc43xx/lpc43_pinconfig.c
index 0a274dd6a898bac27314835e74a951e71f8aaa35..738b4b8dafd2bf85924260cebf3ae1ff2f672a14 100644
--- a/arch/arm/src/lpc43xx/lpc43_pinconfig.c
+++ b/arch/arm/src/lpc43xx/lpc43_pinconfig.c
@@ -68,7 +68,7 @@
* Description:
* Configure a pin based on bit-encoded description of the pin.
*
- * Input Value:
+ * Input Parameters:
* 20-bit encoded value describing the pin.
*
* Returned Value:
diff --git a/arch/arm/src/lpc43xx/lpc43_pinconfig.h b/arch/arm/src/lpc43xx/lpc43_pinconfig.h
index d3a8a822a6a0d70e11621cfdf5bf9e78872c5bdb..6b82878981af7cfd8741cd7c1eb2cd5bd4b48048 100644
--- a/arch/arm/src/lpc43xx/lpc43_pinconfig.h
+++ b/arch/arm/src/lpc43xx/lpc43_pinconfig.h
@@ -262,7 +262,7 @@ extern "C"
* Description:
* Configure a pin based on bit-encoded description of the pin.
*
- * Input Value:
+ * Input Parameters:
* 20-bit encoded value describing the pin.
*
* Returned Value:
diff --git a/arch/arm/src/lpc43xx/lpc43_sdmmc.c b/arch/arm/src/lpc43xx/lpc43_sdmmc.c
index 5d4df400b3f00723a24d9da7dc3e03ff33cce892..a84c6b8de99e490fbebde7e7985bb52e14cecc00 100644
--- a/arch/arm/src/lpc43xx/lpc43_sdmmc.c
+++ b/arch/arm/src/lpc43xx/lpc43_sdmmc.c
@@ -2262,7 +2262,7 @@ static sdio_eventset_t lpc43_eventwait(FAR struct sdio_dev_s *dev,
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay, (wdentry_t)lpc43_eventtimeout,
1, (uint32_t)priv);
- if (ret != OK)
+ if (ret < 0)
{
mcerr("ERROR: wd_start failed: %d\n", ret);
}
@@ -2709,7 +2709,7 @@ static void lpc43_callback(struct lpc43_dev_s *priv)
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SD card interface structure. NULL is returned on failures.
*
****************************************************************************/
diff --git a/arch/arm/src/lpc43xx/lpc43_sdmmc.h b/arch/arm/src/lpc43xx/lpc43_sdmmc.h
index 7a27088415cf16f294218165fe6fc3f73b2d846d..449ee0f7a508f146eac58e8d5393e50d2ec5297e 100644
--- a/arch/arm/src/lpc43xx/lpc43_sdmmc.h
+++ b/arch/arm/src/lpc43xx/lpc43_sdmmc.h
@@ -71,7 +71,7 @@ extern "C"
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
diff --git a/arch/arm/src/lpc43xx/lpc43_spi.c b/arch/arm/src/lpc43xx/lpc43_spi.c
index a77996513bd729c3b9b5a871f9f9b4d40900deeb..2181b4fa2f0b291d31074c4e95f3842208c0a118 100644
--- a/arch/arm/src/lpc43xx/lpc43_spi.c
+++ b/arch/arm/src/lpc43xx/lpc43_spi.c
@@ -505,7 +505,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
* Description:
* Initialize the SPI port
*
- * Input Parameter:
+ * Input Parameters:
* port Port number (must be zero)
*
* Returned Value:
@@ -564,7 +564,7 @@ static FAR struct spi_dev_s *lpc43_spiport_initialize(int port)
* 1 - SSP0
* 2 - SSP1
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lpc43xx/lpc43_spi.h b/arch/arm/src/lpc43xx/lpc43_spi.h
index d0414f9af64b142f2c44317c2ebbd7e650ba5909..b642f9c49083eb967d9606357834fa9353428806 100644
--- a/arch/arm/src/lpc43xx/lpc43_spi.h
+++ b/arch/arm/src/lpc43xx/lpc43_spi.h
@@ -98,7 +98,7 @@ extern "C"
* 1 - SSP0
* 2 - SSP1
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/lpc43xx/lpc43_spifi.c b/arch/arm/src/lpc43xx/lpc43_spifi.c
index 57349370c027b401854c2703903c8f09631a79c0..ed2f01f2c90b40ac31c1d3856c618799952820fe 100644
--- a/arch/arm/src/lpc43xx/lpc43_spifi.c
+++ b/arch/arm/src/lpc43xx/lpc43_spifi.c
@@ -1132,7 +1132,7 @@ static inline int lpc43_rominit(FAR struct lpc43_dev_s *priv)
* Input Parameters:
* None
*
- * Returned value:
+ * Returned Value:
* One success, a reference to the initialized MTD device instance is
* returned; NULL is returned on any failure.
*
@@ -1220,7 +1220,7 @@ FAR struct mtd_dev_s *lpc43_spifi_initialize(void)
* Input Parameters:
* high
*
- * Returned value:
+ * Returned Value:
* None.
*
****************************************************************************/
diff --git a/arch/arm/src/lpc43xx/lpc43_spifi.h b/arch/arm/src/lpc43xx/lpc43_spifi.h
index 4445919259139dae7d863faf488338fc380666db..30f85b83282f83a33bea41d49218d72a930264bf 100644
--- a/arch/arm/src/lpc43xx/lpc43_spifi.h
+++ b/arch/arm/src/lpc43xx/lpc43_spifi.h
@@ -118,7 +118,7 @@ extern "C"
* Input Parameters:
* None
*
- * Returned value:
+ * Returned Value:
* One success, a reference to the initialized MTD device instance is
* returned; NULL is returned on any failure.
*
diff --git a/arch/arm/src/lpc43xx/lpc43_ssp.c b/arch/arm/src/lpc43xx/lpc43_ssp.c
index 2660b00654707eee749b2e10e9f843dda6d404fe..a9816b9366e92bba380fe5d35f2aeffd05b49fc8 100644
--- a/arch/arm/src/lpc43xx/lpc43_ssp.c
+++ b/arch/arm/src/lpc43xx/lpc43_ssp.c
@@ -664,7 +664,7 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
* Description:
* Initialize the SSP0
*
- * Input Parameter:
+ * Input Parameters:
* None
*
* Returned Value:
@@ -717,7 +717,7 @@ static inline FAR struct lpc43_sspdev_s *lpc43_ssp0initialize(void)
* Description:
* Initialize the SSP1
*
- * Input Parameter:
+ * Input Parameters:
* None
*
* Returned Value:
@@ -777,7 +777,7 @@ static inline FAR struct lpc43_sspdev_s *lpc43_ssp1initialize(void)
* Description:
* Initialize the selected SSP port (0=SSP0, 1=SSP1)
*
- * Input Parameter:
+ * Input Parameters:
* port - Port number (0=SSP0, 1=SSP1)
*
* Returned Value:
diff --git a/arch/arm/src/lpc43xx/lpc43_ssp.h b/arch/arm/src/lpc43xx/lpc43_ssp.h
index 5bf708859e6d54d4b416ee70ac50a73c500eaa21..27be5a5130befebad5f48cabc03948645359919b 100644
--- a/arch/arm/src/lpc43xx/lpc43_ssp.h
+++ b/arch/arm/src/lpc43xx/lpc43_ssp.h
@@ -95,7 +95,7 @@ extern "C"
* Description:
* Initialize the selected SSP port (0=SSP0, 1=SSP1)
*
- * Input Parameter:
+ * Input Parameters:
* port - Port number (0=SSP0, 1=SSP1)
*
* Returned Value:
diff --git a/arch/arm/src/lpc43xx/lpc43_timer.c b/arch/arm/src/lpc43xx/lpc43_timer.c
index decc110dd49998f13405d6b8e049fe1497d5e766..7c68ffd449a897e70bc917a5a7c6f1685bc1eb92 100644
--- a/arch/arm/src/lpc43xx/lpc43_timer.c
+++ b/arch/arm/src/lpc43xx/lpc43_timer.c
@@ -331,7 +331,7 @@ void tmr_clk_disable(uint16_t tmrid)
* Input Parameters:
* Usual interrupt callback arguments.
*
- * Returned Values:
+ * Returned Value:
* Always returns OK.
*
****************************************************************************/
@@ -401,7 +401,7 @@ static int lpc43_interrupt(int irq, FAR void *context, FAR void *arg)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -465,7 +465,7 @@ static int lpc43_start(FAR struct timer_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -509,7 +509,7 @@ static int lpc43_stop(FAR struct timer_lowerhalf_s *lower)
* half" driver state structure.
* status - The location to return the status information.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -564,7 +564,7 @@ static int lpc43_getstatus(FAR struct timer_lowerhalf_s *lower,
* half" driver state structure.
* timeout - The new timeout value in milliseconds.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -627,7 +627,7 @@ static int lpc43_settimeout(FAR struct timer_lowerhalf_s *lower,
* function pointer is NULL, then the reset-on-expiration
* behavior is restored,
*
- * Returned Values:
+ * Returned Value:
* The previous timer expiration function pointer or NULL is there was
* no previous function pointer.
*
@@ -667,7 +667,7 @@ static void lpc43_setcallback(FAR struct timer_lowerhalf_s *lower,
* interpretation of this argument depends on the particular
* command.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -700,7 +700,7 @@ static int lpc43_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd,
* devpath - The full path to the timer. This should be of the form
* /dev/tmr0
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/lpc43xx/lpc43_timer.h b/arch/arm/src/lpc43xx/lpc43_timer.h
index 194d917c3179d58837af19a93a1d6fc95043f9dd..7eed9b2dcd39cdb60e56c042a0746cad236ee54a 100644
--- a/arch/arm/src/lpc43xx/lpc43_timer.h
+++ b/arch/arm/src/lpc43xx/lpc43_timer.h
@@ -80,7 +80,7 @@ extern "C"
* devpath - The full path to the timer. This should be of the form
* /dev/timer0
* irq - irq associated with the timer
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/lpc43xx/lpc43_wdt.h b/arch/arm/src/lpc43xx/lpc43_wdt.h
index af427504e4dc53fa8c75031ea4d12165852756f7..c1d88a01e6b8ee673e66ebbe0e65719fae765d0a 100644
--- a/arch/arm/src/lpc43xx/lpc43_wdt.h
+++ b/arch/arm/src/lpc43xx/lpc43_wdt.h
@@ -78,7 +78,7 @@ extern "C"
* devpath - The full path to the watchdog. This should be of the form
* /dev/watchdog0
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/lpc43xx/lpc43_wwdt.c b/arch/arm/src/lpc43xx/lpc43_wwdt.c
index 872e8d5f3f5b063c11f0b129cabf09bc0ccd397c..fb60102d420924e3cb3c383e8753da3226b396a2 100644
--- a/arch/arm/src/lpc43xx/lpc43_wwdt.c
+++ b/arch/arm/src/lpc43xx/lpc43_wwdt.c
@@ -206,7 +206,7 @@ static void lpc43_setwarning(uint32_t warning)
* Input Parameters:
* Usual interrupt handler arguments.
*
- * Returned Values:
+ * Returned Value:
* Always returns OK.
*
****************************************************************************/
@@ -254,7 +254,7 @@ static int lpc43_interrupt(int irq, FAR void *context)
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -295,7 +295,7 @@ static int lpc43_start(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -329,7 +329,7 @@ static int lpc43_stop(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -361,7 +361,7 @@ static int lpc43_keepalive(FAR struct watchdog_lowerhalf_s *lower)
* driver state structure.
* status - The location to return the watchdog status information.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -419,7 +419,7 @@ static int lpc43_getstatus(FAR struct watchdog_lowerhalf_s *lower,
* "lower-half" driver state structure.
* timeout - The new timeout value in milliseconds.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -494,7 +494,7 @@ static int lpc43_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* function pointer is NULL, then the reset-on-expiration
* behavior is restored,
*
- * Returned Values:
+ * Returned Value:
* The previous watchdog expiration function pointer or NULL is there was
* no previous function pointer, i.e., if the previous behavior was
* reset-on-expiration (NULL is also returned if an error occurs).
@@ -563,7 +563,7 @@ static xcpt_t lpc43_capture(FAR struct watchdog_lowerhalf_s *lower,
* interpretation of this argument depends on the particular
* command.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -620,7 +620,7 @@ static int lpc43_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
* devpath - The full path to the watchdog. This should be of the form
* /dev/watchdog0
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/lpc54xx/Kconfig b/arch/arm/src/lpc54xx/Kconfig
index bc77fb071992cfa6024976919edebd97e1ddb5e3..947350c773304d33c7d51da5bc609b1eb763549e 100644
--- a/arch/arm/src/lpc54xx/Kconfig
+++ b/arch/arm/src/lpc54xx/Kconfig
@@ -667,6 +667,24 @@ endif # LPC54_EMC_DYNAMIC
endmenu # EMC Configuration
+menu "SPI Master configuration"
+ depends on LPC54_HAVE_SPI_MASTER
+
+config LPC54_SPI_WIDEDATA
+ bool "Enable wide data"
+ default n
+ ---help---
+ The LPC54xxx SPI supports data widths from 4 through 16 bits. For
+ data from 4 through 8 bits; the receive and transmit data is
+ represented with a uint8_t type. For the wider data, data is
+ represented with a uint16_t. There is duplication of logic for this
+ different widths. By default, SPI wide data is disabled since that
+ is the less frequently used data type and disabling wide data can
+ result in some size reduction. Select this option if you need wide
+ SPI data.
+
+endmenu # SPI Master configuration
+
menu "Ethernet configuration"
depends on LPC54_ETHERNET
diff --git a/arch/arm/src/lpc54xx/Make.defs b/arch/arm/src/lpc54xx/Make.defs
index 4ba8c0d6f8f3d21e02bbf01d3157ac8ee755a4a5..0df41b51b8247105fa0792012a820a9e68ae0c40 100644
--- a/arch/arm/src/lpc54xx/Make.defs
+++ b/arch/arm/src/lpc54xx/Make.defs
@@ -36,7 +36,7 @@
HEAD_ASRC =
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
-CMN_ASRCS += up_testset.S vfork.S
+CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S
CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c
CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_spi.h b/arch/arm/src/lpc54xx/chip/lpc54_spi.h
index 9ab286e18a9a02895093eafd273e5329691b9ba1..21071fbb371f0c491ebac4a379d30fc189b40098 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_spi.h
+++ b/arch/arm/src/lpc54xx/chip/lpc54_spi.h
@@ -260,38 +260,146 @@
/* Register bit definitions *************************************************************************/
/* SPI Configuration register */
-#define SPI_CFG_
+
+#define SPI_CFG_ENABLE (1 << 0) /* Bit 0: SPI enable */
+#define SPI_CFG_MASTER (1 << 2) /* Bit 2: Master mode select */
+#define SPI_CFG_LSBF (1 << 3) /* Bit 3: LSB First mode enable */
+#define SPI_CFG_CPHA (1 << 4) /* Bit 4: Clock Phase select */
+#define SPI_CFG_CPOL (1 << 5) /* Bit 5: Clock Polarity select */
+#define SPI_CFG_LOOP (1 << 7) /* Bit 7: Loopback mode enable */
+#define SPI_CFG_SPOL0 (1 << 8) /* Bit 8: SSEL0 Polarity select */
+#define SPI_CFG_SPOL1 (1 << 9) /* Bit 9: SSEL1 Polarity select */
+#define SPI_CFG_SPOL2 (1 << 10) /* Bit 10: SSEL2 Polarity select */
+#define SPI_CFG_SPOL3 (1 << 11) /* Bit 11: SSEL3 Polarity select */
+
/* SPI Delay register */
-#define SPI_DLY_
+
+#define SPI_DLY_PRE_DELAY_SHIFT (0) /* Bits 0-3: Time between SSEL assertion and data transfer */
+#define SPI_DLY_PRE_DELAY_MASK (15 << SPI_DLY_PRE_DELAY_SHIFT)
+# define SPI_DLY_PRE_DELAY(n) ((uint32_t)(n) << SPI_DLY_PRE_DELAY_SHIFT)
+#define SPI_DLY_POST_DELAY_SHIFT (4) /* Bits 4-7: Time between tdata transfer and SSEL deassertion */
+#define SPI_DLY_POST_DELAY_MASK (15 << SPI_DLY_POST_DELAY_SHIFT)
+# define SPI_DLY_POST_DELAY(n) ((uint32_t)(n) << SPI_DLY_POST_DELAY_SHIFT)
+#define SPI_DLY_FRAME_DELAY_SHIFT (8) /* Bits 8-11: Minimum amount of time between frames */
+#define SPI_DLY_FRAME_DELAY_MASK (15 << SPI_DLY_FRAME_DELAY_SHIFT)
+# define SPI_DLY_FRAME_DELAY(n) ((uint32_t)(n) << SPI_DLY_FRAME_DELAY_SHIFT)
+#define SPI_DLY_TRANSFER_DELAY_SHIFT (12) /* Bits 12-15: Time SSEL deasserted between transfers */
+#define SPI_DLY_TRANSFER_DELAY_MASK (15 << SPI_DLY_TRANSFER_DELAY_SHIFT)
+# define SPI_DLY_TRANSFER_DELAY(n) ((uint32_t)(n) << SPI_DLY_TRANSFER_DELAY_SHIFT)
+
/* SPI Status register */
-#define SPI_STAT_
-/* SPI Interrupt Enable read and set */
-#define SPI_INTENSET_
-/* SPI Interrupt Enable Clear */
-#define SPI_INTENCLR_
+
+#define SPI_STAT_SSA (1 << 4) /* Bit 4: Slave Select Assert */
+#define SPI_STAT_SSD (1 << 5) /* Bit 5: Slave Select Deassert */
+#define SPI_STAT_STALLED (1 << 6) /* Bit 6: Stalled status flag */
+#define SPI_STAT_ENDTRANSFER (1 << 7) /* Bit 7: End Transfer control bit */
+#define SPI_STAT_MSTIDLE (1 << 8) /* Bit 8: Master idle status flag */
+
+/* SPI Interrupt Enable read and set, SPI Interrupt Enable Clear, and SPI Interrupt Status */
+
+#define SPI_INT_SSA (1 << 4) /* Bit 4: Slave select assert interrupt */
+#define SPI_INT_SSD (1 << 5) /* Bit 5: Slave select deassert interrupt */
+#define SPI_INT_MSTIDLE (1 << 8) /* Bit 8: Master idle interrupt */
+
/* SPI clock Divider */
-#define SPI_DIV_
-/* SPI Interrupt Status */
-#define SPI_INTSTAT_
+
+#define SPI_DIV_SHIFT (0) /* Bits 0-15: Rate divider value */
+#define SPI_DIV_MASK (0xffff << SPI_DIV_SHIFT)
+# define SPI_DIV(n) ((uint32_t)((n)-1) << SPI_DIV_SHIFT)
+
/* FIFO configuration and enable register */
-#define SPI_FIFOCFG_
+
+#define SPI_FIFOCFG_ENABLETX (1 << 0) /* Bit 0: Enable the transmit FIFO) */
+#define SPI_FIFOCFG_ENABLERX (1 << 1) /* Bit 1: Enable the receive FIFO) */
+#define SPI_FIFOCFG_SIZE_SHIFT (4) /* Bits 4-5: FIFO size configuration (read-only) */
+#define SPI_FIFOCFG_SIZE_MASK (3 << SPI_FIFOCFG_SIZE_SHIFT)
+# define SPI_FIFOCFG_SIZE_8x16 (1 << SPI_FIFOCFG_SIZE_SHIFT) /* FIFO is configured as 8 entries of 16 bits */
+#define SPI_FIFOCFG_DMATX (1 << 12) /* Bit 12: DMA configuration for transmit */
+#define SPI_FIFOCFG_DMARX (1 << 13) /* Bit 13: DMA configuration for receive */
+#define SPI_FIFOCFG_WAKETX (1 << 14) /* Bit 14: Wake-up for transmit FIFO level */
+#define SPI_FIFOCFG_WAKERX (1 << 15) /* Bit 15: Wake-up for receive FIFO level */
+#define SPI_FIFOCFG_EMPTYTX (1 << 16) /* Bit 16: Empty command for the transmit FIFO) */
+#define SPI_FIFOCFG_EMPTYRX (1 << 17) /* Bit 17: Empty command for the receive FIFO) */
+
/* FIFO status register */
-#define SPI_FIFOSTAT_
+
+#define SPI_FIFOSTAT_TXERR (1 << 0) /* Bit 0: TX FIFO error */
+#define SPI_FIFOSTAT_RXERR (1 << 1) /* Bit 1: RX FIFO error */
+#define SPI_FIFOSTAT_PERINT (1 << 3) /* Bit 3: Peripheral interrupt */
+#define SPI_FIFOSTAT_TXEMPTY (1 << 4) /* Bit 4: Transmit FIFO empty */
+#define SPI_FIFOSTAT_TXNOTFULL (1 << 5) /* Bit 5: Transmit FIFO not full */
+#define SPI_FIFOSTAT_RXNOTEMPTY (1 << 6) /* Bit 6: Receive FIFO not empty */
+#define SPI_FIFOSTAT_RXFULL (1 << 7) /* Bit 7: Receive FIFO full */
+#define SPI_FIFOSTAT_TXLVL_SHIFT (8) /* Bits 8-12: Transmit FIFO current level */
+#define SPI_FIFOSTAT_TXLVL_MASK (31 << SPI_FIFOSTAT_TXLVL_SHIFT)
+#define SPI_FIFOSTAT_RXLVL_SHIFT (16) /* Bits 16-20: Receive FIFO current level */
+#define SPI_FIFOSTAT_RXLVL_MASK (31 << SPI_FIFOSTAT_RXLVL_SHIFT)
+
/* FIFO trigger level settings for interrupt and DMA request */
-#define SPI_FIFOTRIG_
-/* FIFO interrupt enable set (enable) and read register */
-#define SPI_FIFOINTENSET_
-/* FIFO interrupt enable clear (disable) and read register */
-#define SPI_FIFOINTENCLR_
-/* FIFO interrupt status register */
-#define SPI_FIFOINTSTAT_
+
+#define SPI_FIFOTRIG_TXLVLENA (1 << 0) /* Bit 0: Transmit FIFO level trigger enable */
+#define SPI_FIFOTRIG_RXLVLENA (1 << 1) /* Bit 1: Receive FIFO level trigger enable */
+#define SPI_FIFOTRIG_TXLVL_SHIFT (8) /* Bits 8-11: Transmit FIFO level trigger point */
+#define SPI_FIFOTRIG_TXLVL_MASK (15 << SPI_FIFOTRIG_TXLVL_SHIFT)
+# define SPI_FIFOTRIG_TXLVL(n) ((uint32_t)(n) << SPI_FIFOTRIG_TXLVL_SHIFT)
+# define SPI_FIFOTRIG_TXLVL_EMPTY (0 << SPI_FIFOTRIG_TXLVL_SHIFT)
+# define SPI_FIFOTRIG_TXLVL_NOTFULL (7 << SPI_FIFOTRIG_TXLVL_SHIFT)
+#define SPI_FIFOTRIG_RXLVL_SHIFT (16) /* Bits 16-19: Receive FIFO level trigger point */
+#define SPI_FIFOTRIG_RXLVL_MASK (15 << SPI_FIFOTRIG_RXLVL_SHIFT)
+# define SPI_FIFOTRIG_RXLVL(n) ((uint32_t)((n)-1) << SPI_FIFOTRIG_RXLVL_SHIFT)
+# define SPI_FIFOTRIG_RXLVL_NOTEMPTY (0 << SPI_FIFOTRIG_RXLVL_SHIFT)
+# define SPI_FIFOTRIG_RXLVL_FULL (7 << SPI_FIFOTRIG_RXLVL_SHIFT)
+
+/* FIFO interrupt enable set (enable) and read register, FIFO interrupt enable clear (disable)
+ * and read register, and FIFO interrupt status register
+ */
+
+#define SPI_FIFOINT_TXERR (1 << 0) /* Bit 0: Transmit error interrupt */
+#define SPI_FIFOINT_RXERR (1 << 1) /* Bit 1: Receive error interrupt */
+#define SPI_FIFOINT_TXLVL (1 << 2) /* Bit 2: Tx FIFO level reached interrupt */
+#define SPI_FIFOINT_RXLVL (1 << 3) /* Bit 3: Rx FIFO level reached interrupt */
+#define SPI_FIFOINTSTAT_PERINT (1 << 4) /* Bit 4: Peripheral interrupt (status only) */
+
/* FIFO write data */
-#define SPI_FIFOWR_
-/* FIFO read data */
-#define SPI_FIFORD_
-/* FIFO data read with no FIFO pop */
-#define SPI_FIFORDNOPOP_
+
+#define SPI_FIFOWR_TXDATA_SHIFT (0) /* Bits 0-15: Transmit data to the FIFO */
+#define SPI_FIFOWR_TXDATA_MASK (0xffff << SPI_FIFOWR_TXDATA_SHIFT)
+# define SPI_FIFOWR_TXDATA(n) ((uint32_t)(n) << SPI_FIFOWR_TXDATA_SHIFT)
+#define SPI_FIFOWR_TXSSELN_SHIFT (16) /* Bits 16-19: Transmit Slave Selects */
+#define SPI_FIFOWR_TXSSELN_MASK (15 << SPI_FIFOWR_TXSSELN_SHIFT)
+# define SPI_FIFOWR_TXSSELN_ALL (15 << SPI_FIFOWR_TXSSELN_SHIFT)
+# define SPI_FIFOWR_TXSSEL0N (1 << 16) /* Bit 16: Transmit Slave Select */
+# define SPI_FIFOWR_TXSSEL1N (1 << 17) /* Bit 17: Transmit Slave Select */
+# define SPI_FIFOWR_TXSSEL2N (1 << 18) /* Bit 18: Transmit Slave Select */
+# define SPI_FIFOWR_TXSSEL3N (1 << 19) /* Bit 19: Transmit Slave Select */
+#define SPI_FIFOWR_EOT (1 << 20) /* Bit 20: End of Transfer */
+#define SPI_FIFOWR_EOF (1 << 21) /* Bit 21: End of Frame */
+#define SPI_FIFOWR_RXIGNORE (1 << 22) /* Bit 22: Receive Ignore */
+#define SPI_FIFOWR_LEN_SHIFT (24) /* Bits 24-27: Data Length */
+#define SPI_FIFOWR_LEN_MASK (15 << SPI_FIFOWR_LEN_SHIFT)
+# define SPI_FIFOWR_LEN(n) ((uint32_t)((n)-1) << SPI_FIFOWR_LEN_SHIFT)
+
+/* FIFO read data and FIFO data read with no FIFO pop */
+
+#define SPI_FIFORD_RXDATA_SHIFT (0) /* Bits 0-15: Received data from the FIFO */
+#define SPI_FIFORD_RXDATA_MASK (0xffff << SPI_FIFORD_RXDATA_SHIFT)
+#define SPI_FIFORD_RXSSELN_SHIFT (16) /* Bits 16-19: Slave Selects for receive */
+#define SPI_FIFORD_RXSSELN_MASK (15 << SPI_FIFORD_RXSSELN_SHIFT)
+# define SPI_FIFORD_RXSSEL0N (1 << 16) /* Bit 16: Slave Select for receive */
+# define SPI_FIFORD_RXSSEL1N (1 << 17) /* Bit 17: Slave Select for receive */
+# define SPI_FIFORD_RXSSEL2N (1 << 18) /* Bit 18: Slave Select for receive */
+# define SPI_FIFORD_RXSSEL3N (1 << 19) /* Bit 19: Slave Select for receive */
+#define SPI_FIFORD_SOT (1 << 20) /* Bit 20: Start of Transfer flag */
+
/* SPI module Identification */
-#define SPI_ID_
+
+#define SPI_ID_APERTURE_SHIFT (0) /* Bits 0-7: Aperture encoded as (aperture size/4K) -1 */
+#define SPI_ID_APERTURE_MASK (0xff << SPI_ID_APERTURE_SHIFT)
+#define SPI_ID_MINORREV_SHIFT (8) /* Bits 8-11: Minor revision of module implementation */
+#define SPI_ID_MINORREV_MASK (15 << SPI_ID_MINORREV_SHIFT)
+#define SPI_ID_MAJORREV_SHIFT (12) /* Bits 12-15: Major revision of module implementation */
+#define SPI_ID_MAJORREV_MASK (15 << SPI_ID_MAJORREV_SHIFT)
+#define SPI_ID_ID_SHIFT (15) /* Bits 16-31: Unique module identifier for this IP block */
+#define SPI_ID_ID_MASK (0xffff << SPI_ID_ID_SHIFT)
#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SPI_H */
diff --git a/arch/arm/src/lpc54xx/lpc54_ethernet.c b/arch/arm/src/lpc54xx/lpc54_ethernet.c
index d89317247dc74004e777795f607c33154658059d..dde91da5c1773f3bb31118f36a30ce7bb6cb4cdd 100644
--- a/arch/arm/src/lpc54xx/lpc54_ethernet.c
+++ b/arch/arm/src/lpc54xx/lpc54_ethernet.c
@@ -2392,13 +2392,16 @@ static int lpc54_eth_rmmac(struct net_driver_s *dev, const uint8_t *mac)
static int lpc54_eth_ioctl(struct net_driver_s *dev, int cmd,
unsigned long arg)
{
+#ifdef CONFIG_NETDEV_PHY_IOCTL
struct lpc54_ethdriver_s *priv = (struct lpc54_ethdriver_s *)dev->d_private;
+#endif
int ret;
/* Decode and dispatch the driver-specific IOCTL command */
switch (cmd)
{
+#ifdef CONFIG_NETDEV_PHY_IOCTL
case SIOCGMIIPHY: /* Get MII PHY address */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
@@ -2422,6 +2425,7 @@ static int lpc54_eth_ioctl(struct net_driver_s *dev, int cmd,
ret = OK
}
break;
+#endif /* ifdef CONFIG_NETDEV_PHY_IOCTL */
default:
nerr("ERROR: Unrecognized IOCTL command: %d\n", command);
diff --git a/arch/arm/src/lpc54xx/lpc54_i2c_master.c b/arch/arm/src/lpc54xx/lpc54_i2c_master.c
index cf4981676f5267a1c352680221365cc9dca38fad..05d171a5971db2a829bb758355bd22e91d5168ba 100644
--- a/arch/arm/src/lpc54xx/lpc54_i2c_master.c
+++ b/arch/arm/src/lpc54xx/lpc54_i2c_master.c
@@ -765,10 +765,9 @@ static int lpc54_i2c_transfer(FAR struct i2c_master_s *dev,
priv->result = OK;
/* Set up the transfer timeout */
- /* wd_start(priv->timeout ...); */
- wd_start(priv->timeout, priv->nmsgs * I2C_WDOG_TIMEOUT, lpc54_i2c_timeout,
- 1, (uint32_t)priv);
+ (void)wd_start(priv->timeout, priv->nmsgs * I2C_WDOG_TIMEOUT,
+ lpc54_i2c_timeout, 1, (uint32_t)priv);
/* Initiate the transfer */
diff --git a/arch/arm/src/lpc54xx/lpc54_i2c_master.h b/arch/arm/src/lpc54xx/lpc54_i2c_master.h
index 1655d0fec5e174af6ad715ed4e683ff22a44fc58..fc9e80f662a83c5a5986302ae06b9063f6d7d472 100644
--- a/arch/arm/src/lpc54xx/lpc54_i2c_master.h
+++ b/arch/arm/src/lpc54xx/lpc54_i2c_master.h
@@ -57,7 +57,7 @@
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
@@ -73,7 +73,7 @@ FAR struct i2c_master_s *lpc54_i2cbus_initialize(int port);
* Description:
* De-initialize the selected I2C port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the lpc54_i2cbus_initialize()
*
* Returned Value:
diff --git a/arch/arm/src/lpc54xx/lpc54_lcd.c b/arch/arm/src/lpc54xx/lpc54_lcd.c
index 25cb80fc3335eae27060095864f2dd7c0591984e..2b8b5aa262cda268b03e7e3996966f2b54d1e6ee 100644
--- a/arch/arm/src/lpc54xx/lpc54_lcd.c
+++ b/arch/arm/src/lpc54xx/lpc54_lcd.c
@@ -441,7 +441,7 @@ static int lpc54_setcursor(FAR struct fb_vtable_s *vtable,
* Description:
* Initialize the framebuffer video hardware associated with the display.
*
- * Input parameters:
+ * Input Parameters:
* display - In the case of hardware with multiple displays, this
* specifies the display. Normally this is zero.
*
@@ -802,7 +802,7 @@ int up_fbinitialize(int display)
* Return a a reference to the framebuffer object for the specified video
* plane of the specified plane. Many OSDs support multiple planes of video.
*
- * Input parameters:
+ * Input Parameters:
* display - In the case of hardware with multiple displays, this
* specifies the display. Normally this is zero.
* vplane - Identifies the plane being queried.
diff --git a/arch/arm/src/lpc54xx/lpc54_sdmmc.c b/arch/arm/src/lpc54xx/lpc54_sdmmc.c
index 09cb42526777204524ddbdbcdf8da77cc000f531..292732040db4e294a422e4c944b26a1e0675a689 100644
--- a/arch/arm/src/lpc54xx/lpc54_sdmmc.c
+++ b/arch/arm/src/lpc54xx/lpc54_sdmmc.c
@@ -2262,7 +2262,7 @@ static sdio_eventset_t lpc54_eventwait(FAR struct sdio_dev_s *dev,
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay, (wdentry_t)lpc54_eventtimeout,
1, (uint32_t)priv);
- if (ret != OK)
+ if (ret < 0)
{
mcerr("ERROR: wd_start failed: %d\n", ret);
}
@@ -2709,7 +2709,7 @@ static void lpc54_callback(struct lpc54_dev_s *priv)
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SD card interface structure. NULL is returned on failures.
*
****************************************************************************/
diff --git a/arch/arm/src/lpc54xx/lpc54_sdmmc.h b/arch/arm/src/lpc54xx/lpc54_sdmmc.h
index 7eb00403c55dd833eac291f54a6e4e46f500a755..a56fe2095bc5cc4414a35bd05de257a194f2ef15 100644
--- a/arch/arm/src/lpc54xx/lpc54_sdmmc.h
+++ b/arch/arm/src/lpc54xx/lpc54_sdmmc.h
@@ -71,7 +71,7 @@ extern "C"
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
diff --git a/arch/arm/src/lpc54xx/lpc54_serial.c b/arch/arm/src/lpc54xx/lpc54_serial.c
index 7c74dec93be5935cdb4497b6b3e5cf894f6f499f..996affee4caef22105b1d138cf5ad2b425376898 100644
--- a/arch/arm/src/lpc54xx/lpc54_serial.c
+++ b/arch/arm/src/lpc54xx/lpc54_serial.c
@@ -1421,7 +1421,7 @@ void lpc54_earlyserialinit(void)
* Input Parameters:
* None
*
- * Returns Value:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/lpc54xx/lpc54_spi_master.c b/arch/arm/src/lpc54xx/lpc54_spi_master.c
index 665c1a4242dd8e244fbf76077209dfe8f64d5bd6..443bcb3333cea4e87e32197607f64fe332da0871 100644
--- a/arch/arm/src/lpc54xx/lpc54_spi_master.c
+++ b/arch/arm/src/lpc54xx/lpc54_spi_master.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc54xx/lpc54_spi.c
*
- * Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,6 +33,16 @@
*
****************************************************************************/
+/* TODO:
+ *
+ * - There are no interrupt driven transfers, only polled. I don't
+ * consider this a significant problem because of the higher rate that
+ * would be necessary for interrupt driven transfers.
+ * - Integrate DMA transfers. This is fairly important because it can
+ * a) improve the data transfer rates and b) free the CPU when the
+ * SPI driver would otherwise be stuck in a tight polling loop.
+ */
+
/****************************************************************************
* Included Files
****************************************************************************/
@@ -59,6 +69,7 @@
#include "chip/lpc54_spi.h"
#include "lpc54_config.h"
#include "lpc54_enableclk.h"
+#include "lpc54_gpio.h"
#include "lpc54_spi_master.h"
#ifdef HAVE_SPI_MASTER_DEVICE
@@ -67,74 +78,166 @@
* Pre-processor Definitions
****************************************************************************/
+#define SPI_DUMMYDATA8 0xff
+#define SPI_DUMMYDATA16 0xffff
+
+#define SPI_MINWIDTH 4
+#ifdef CONFIG_LPC54_SPI_WIDEDATA
+# define SPI_MAXWIDTH 16
+#else
+# define SPI_MAXWIDTH 8
+#endif
+
/****************************************************************************
* Private Types
****************************************************************************/
-/* This structure descibes the state of the SSP driver */
+/* This structure describes the state of the SSP driver */
struct lpc54_spidev_s
{
- struct spi_dev_s dev; /* Externally visible part of the SPI interface */
- uintptr_t base; /* Base address of Flexcomm registers */
- sem_t exclsem; /* Held while chip is selected for mutual exclusion */
- uint32_t fclock; /* Flexcomm function clock frequency */
- uint32_t frequency; /* Requested clock frequency */
- uint32_t actual; /* Actual clock frequency */
- uint16_t irq; /* Flexcomm IRQ number */
- uint8_t nbits; /* Width of word in bits (8 to 16) */
- uint8_t mode; /* Mode 0,1,2,3 */
+ struct spi_dev_s dev; /* Externally visible part of the SPI interface */
+ uintptr_t base; /* Base address of Flexcomm registers */
+ sem_t exclsem; /* Held while chip is selected for mutual exclusion */
+ uint32_t fclock; /* Flexcomm function clock frequency */
+ uint32_t frequency; /* Requested clock frequency */
+ uint32_t actual; /* Actual clock frequency */
+ uint16_t irq; /* Flexcomm IRQ number */
+ uint8_t nbits; /* Width of word in bits (SPI_MINWIDTH to SPI_MAXWIDTH) */
+ uint8_t mode; /* Mode 0,1,2,3 */
+};
+
+/* These structures describes the Rx side of an 8- or 16-bit SPI data
+ * exchange.
+ */
+
+struct lpc54_rxtransfer8_s
+{
+ FAR uint8_t *rxptr; /* Pointer into receive buffer */
+ unsigned int remaining; /* Bytes remaining in the receive buffer */
+ unsigned int expected; /* Bytes expected to be received */
+};
+
+#ifdef CONFIG_LPC54_SPI_WIDEDATA
+struct lpc54_rxtransfer16_s
+{
+ FAR uint16_t *rxptr; /* Pointer into receive buffer */
+ unsigned int remaining; /* Hwords remaining in the receive buffer */
+ unsigned int expected; /* Hwords expected to be received */
+};
+#endif
+
+/* These structures describes the Tx side of an 8- or 16-bit SPI data
+ * exchange.
+ */
+
+struct lpc54_txtransfer8_s
+{
+ uint32_t txctrl; /* Tx control bits */
+ FAR const uint8_t *txptr; /* Pointer into transmit buffer */
+ unsigned int remaining; /* Bytes remaining in the transmit buffer */
+};
+
+#ifdef CONFIG_LPC54_SPI_WIDEDATA
+struct lpc54_txtransfer16_s
+{
+ uint32_t txctrl; /* Tx control bits */
+ FAR const uint16_t *txptr; /* Pointer into transmit buffer */
+ unsigned int remaining; /* Hwords remaining in the transmit buffer */
+};
+#endif
+
+struct lpc54_txdummy_s
+{
+ uint32_t txctrl; /* Tx control bits */
+ unsigned int remaining; /* Bytes remaining in the transmit buffer */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
-static inline bool lpc54_spi_16bitmode(FAR struct lpc54_spidev_s *priv);
+/* Transfer helpers */
+
+static inline unsigned int lpc54_spi_fifodepth(FAR struct lpc54_spidev_s *priv);
+static inline bool lpc54_spi_txavailable(FAR struct lpc54_spidev_s *priv);
+static inline bool lpc54_spi_rxavailable(FAR struct lpc54_spidev_s *priv);
+
+static void lpc54_spi_resetfifos(FAR struct lpc54_spidev_s *priv);
+static void lpc54_spi_rxtransfer8(FAR struct lpc54_spidev_s *priv,
+ FAR struct lpc54_rxtransfer8_s *xfr);
+#ifdef CONFIG_LPC54_SPI_WIDEDATA
+static void lpc54_spi_rxtransfer16(FAR struct lpc54_spidev_s *priv,
+ FAR struct lpc54_rxtransfer16_s *xfr);
+#endif
+static bool lpc54_spi_txtransfer8(FAR struct lpc54_spidev_s *priv,
+ FAR struct lpc54_txtransfer8_s *xfr);
+#ifdef CONFIG_LPC54_SPI_WIDEDATA
+static bool lpc54_spi_txtransfer16(FAR struct lpc54_spidev_s *priv,
+ FAR struct lpc54_txtransfer16_s *xfr);
+#endif
+static bool lpc54_spi_txdummy(FAR struct lpc54_spidev_s *priv,
+ FAR struct lpc54_txdummy_s *xfr);
+#ifdef CONFIG_SPI_EXCHANGE
+static void lpc54_spi_exchange8(FAR struct lpc54_spidev_s *priv,
+ FAR const void *txbuffer, FAR void *rxbuffer,
+ size_t nwords);
+#ifdefCONFIG_LPC54_SPI_WIDEDATA
+static void lpc54_spi_exchange16(FAR struct lpc54_spidev_s *priv,
+ FAR const void *txbuffer, FAR void *rxbuffer,
+ size_t nwords);
+#endif
+#endif
+static void lpc54_spi_sndblock8(FAR struct lpc54_spidev_s *priv,
+ FAR const void *buffer, size_t nwords);
+#ifdef CONFIG_LPC54_SPI_WIDEDATA
+static void lpc54_spi_sndblock16(FAR struct lpc54_spidev_s *priv,
+ FAR const void *buffer, size_t nwords);
+#endif
+static void lpc54_spi_recvblock8(FAR struct lpc54_spidev_s *priv,
+ FAR void *buffer, size_t nwords);
+#ifdef CONFIG_LPC54_SPI_WIDEDATA
+static void lpc54_spi_recvblock16(FAR struct lpc54_spidev_s *priv,
+ FAR void *buffer, size_t nwords);
+#endif
/* SPI methods */
static int lpc54_spi_lock(FAR struct spi_dev_s *dev, bool lock);
-static void lpc54_spi_select(FAR struct spi_dev_s *dev, uint32_t devid,
- bool selected);
static uint32_t lpc54_spi_setfrequency(FAR struct spi_dev_s *dev,
uint32_t frequency);
static void lpc54_spi_setmode(FAR struct spi_dev_s *dev,
enum spi_mode_e mode);
static void lpc54_spi_setbits(FAR struct spi_dev_s *dev, int nbits);
static uint16_t lpc54_spi_send(FAR struct spi_dev_s *dev, uint16_t ch);
-#ifdef CONFIG_LPC54_SPI_MASTER_DMA
-static void lpc54_spi_exchange_nodma(FAR struct spi_dev_s *dev,
- FAR const void *txbuffer, FAR void *rxbuffer,
- size_t nwords)
-#endif
+#ifdef CONFIG_SPI_EXCHANGE
static void lpc54_spi_exchange(FAR struct spi_dev_s *dev,
FAR const void *txbuffer, FAR void *rxbuffer,
size_t nwords);
-#ifndef CONFIG_SPI_EXCHANGE
+#endif
static void lpc54_spi_sndblock(FAR struct spi_dev_s *dev,
FAR const void *buffer, size_t nwords);
static void lpc54_spi_recvblock(FAR struct spi_dev_s *dev,
FAR void *buffer, size_t nwords);
-#endif
/****************************************************************************
* Private Data
****************************************************************************/
-static const struct spi_ops_s g_spi_ops =
+#ifdef CONFIG_LPC54_SPI0_MASTER
+static const struct spi_ops_s g_spi0_ops =
{
.lock = lpc54_spi_lock,
- .select = lpc54_spiselect,
+ .select = lpc54_spi0_select, /* Provided externally */
.setfrequency = lpc54_spi_setfrequency,
.setmode = lpc54_spi_setmode,
.setbits = lpc54_spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
- .hwfeatures = 0, /* Not supported */
+ .hwfeatures = NULL, /* Not supported */
#endif
- .status = lpc54_spistatus,
+ .status = lpc54_spi0_status, /* Provided externally */
#ifdef CONFIG_SPI_CMDDATA
- .cmddata = lpc54_spicmddata,
+ .cmddata = lpc54_spi0_cmddata, /* Provided externally */
#endif
.send = lpc54_spi_send,
#ifdef CONFIG_SPI_EXCHANGE
@@ -144,101 +247,1003 @@ static const struct spi_ops_s g_spi_ops =
.recvblock = lpc54_spi_recvblock,
#endif
#ifdef CONFIG_SPI_CALLBACK
- .registercallback = lpc54_spiregister, /* Provided externally */
+ .registercallback = lpc54_spi0_register, /* Provided externally */
#else
- .registercallback = 0, /* Not implemented */
+ .registercallback = NULL, /* Not implemented */
#endif
};
-#ifdef CONFIG_LPC54_I2C0_MASTER
static struct lpc54_spidev_s g_spi0_dev;
#endif
-#ifdef CONFIG_LPC54_I2C1_MASTER
+
+#ifdef CONFIG_LPC54_SPI1_MASTER
+static const struct spi_ops_s g_spi1_ops =
+{
+ .lock = lpc54_spi_lock,
+ .select = lpc54_spi1_select, /* Provided externally */
+ .setfrequency = lpc54_spi_setfrequency,
+ .setmode = lpc54_spi_setmode,
+ .setbits = lpc54_spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = NULL, /* Not supported */
+#endif
+ .status = lpc54_spi1_status, /* Provided externally */
+#ifdef CONFIG_SPI_CMDDATA
+ .cmddata = lpc54_spi1_cmddata, /* Provided externally */
+#endif
+ .send = lpc54_spi_send,
+#ifdef CONFIG_SPI_EXCHANGE
+ .exchange = lpc54_spi_exchange,
+#else
+ .sndblock = lpc54_spi_sndblock,
+ .recvblock = lpc54_spi_recvblock,
+#endif
+#ifdef CONFIG_SPI_CALLBACK
+ .registercallback = lpc54_spi1_register, /* Provided externally */
+#else
+ .registercallback = NULL, /* Not implemented */
+#endif
+};
+
static struct lpc54_spidev_s g_spi1_dev;
#endif
-#ifdef CONFIG_LPC54_I2C2_MASTER
+
+#ifdef CONFIG_LPC54_SPI2_MASTER
+static const struct spi_ops_s g_spi2_ops =
+{
+ .lock = lpc54_spi_lock,
+ .select = lpc54_spi2_select, /* Provided externally */
+ .setfrequency = lpc54_spi_setfrequency,
+ .setmode = lpc54_spi_setmode,
+ .setbits = lpc54_spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = NULL, /* Not supported */
+#endif
+ .status = lpc54_spi2_status, /* Provided externally */
+#ifdef CONFIG_SPI_CMDDATA
+ .cmddata = lpc54_spi2_cmddata, /* Provided externally */
+#endif
+ .send = lpc54_spi_send,
+#ifdef CONFIG_SPI_EXCHANGE
+ .exchange = lpc54_spi_exchange,
+#else
+ .sndblock = lpc54_spi_sndblock,
+ .recvblock = lpc54_spi_recvblock,
+#endif
+#ifdef CONFIG_SPI_CALLBACK
+ .registercallback = lpc54_spi2_register, /* Provided externally */
+#else
+ .registercallback = NULL, /* Not implemented */
+#endif
+};
+
static struct lpc54_spidev_s g_spi2_dev;
#endif
-#ifdef CONFIG_LPC54_I2C3_MASTER
+
+#ifdef CONFIG_LPC54_SPI3_MASTER
+static const struct spi_ops_s g_spi3_ops =
+{
+ .lock = lpc54_spi_lock,
+ .select = lpc54_spi3_select, /* Provided externally */
+ .setfrequency = lpc54_spi_setfrequency,
+ .setmode = lpc54_spi_setmode,
+ .setbits = lpc54_spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = NULL, /* Not supported */
+#endif
+ .status = lpc54_spi3_status, /* Provided externally */
+#ifdef CONFIG_SPI_CMDDATA
+ .cmddata = lpc54_spi3_cmddata, /* Provided externally */
+#endif
+ .send = lpc54_spi_send,
+#ifdef CONFIG_SPI_EXCHANGE
+ .exchange = lpc54_spi_exchange,
+#else
+ .sndblock = lpc54_spi_sndblock,
+ .recvblock = lpc54_spi_recvblock,
+#endif
+#ifdef CONFIG_SPI_CALLBACK
+ .registercallback = lpc54_spi3_register, /* Provided externally */
+#else
+ .registercallback = NULL, /* Not implemented */
+#endif
+};
+
static struct lpc54_spidev_s g_spi3_dev;
#endif
-#ifdef CONFIG_LPC54_I2C4_MASTER
+
+#ifdef CONFIG_LPC54_SPI4_MASTER
+static const struct spi_ops_s g_spi4_ops =
+{
+ .lock = lpc54_spi_lock,
+ .select = lpc54_spi4_select, /* Provided externally */
+ .setfrequency = lpc54_spi_setfrequency,
+ .setmode = lpc54_spi_setmode,
+ .setbits = lpc54_spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = NULL, /* Not supported */
+#endif
+ .status = lpc54_spi4_status, /* Provided externally */
+#ifdef CONFIG_SPI_CMDDATA
+ .cmddata = lpc54_spi4_cmddata, /* Provided externally */
+#endif
+ .send = lpc54_spi_send,
+#ifdef CONFIG_SPI_EXCHANGE
+ .exchange = lpc54_spi_exchange,
+#else
+ .sndblock = lpc54_spi_sndblock,
+ .recvblock = lpc54_spi_recvblock,
+#endif
+#ifdef CONFIG_SPI_CALLBACK
+ .registercallback = lpc54_spi4_register, /* Provided externally */
+#else
+ .registercallback = NULL, /* Not implemented */
+#endif
+};
+
static struct lpc54_spidev_s g_spi4_dev;
#endif
-#ifdef CONFIG_LPC54_I2C5_MASTER
+
+#ifdef CONFIG_LPC54_SPI5_MASTER
+static const struct spi_ops_s g_spi5_ops =
+{
+ .lock = lpc54_spi_lock,
+ .select = lpc54_spi5_select, /* Provided externally */
+ .setfrequency = lpc54_spi_setfrequency,
+ .setmode = lpc54_spi_setmode,
+ .setbits = lpc54_spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = NULL, /* Not supported */
+#endif
+ .status = lpc54_spi5_status, /* Provided externally */
+#ifdef CONFIG_SPI_CMDDATA
+ .cmddata = lpc54_spi5_cmddata, /* Provided externally */
+#endif
+ .send = lpc54_spi_send,
+#ifdef CONFIG_SPI_EXCHANGE
+ .exchange = lpc54_spi_exchange,
+#else
+ .sndblock = lpc54_spi_sndblock,
+ .recvblock = lpc54_spi_recvblock,
+#endif
+#ifdef CONFIG_SPI_CALLBACK
+ .registercallback = lpc54_spi5_register, /* Provided externally */
+#else
+ .registercallback = NULL, /* Not implemented */
+#endif
+};
+
static struct lpc54_spidev_s g_spi5_dev;
#endif
-#ifdef CONFIG_LPC54_I2C6_MASTER
+
+#ifdef CONFIG_LPC54_SPI6_MASTER
+static const struct spi_ops_s g_spi6_ops =
+{
+ .lock = lpc54_spi_lock,
+ .select = lpc54_spi6_select, /* Provided externally */
+ .setfrequency = lpc54_spi_setfrequency,
+ .setmode = lpc54_spi_setmode,
+ .setbits = lpc54_spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = NULL, /* Not supported */
+#endif
+ .status = lpc54_spi6_status, /* Provided externally */
+#ifdef CONFIG_SPI_CMDDATA
+ .cmddata = lpc54_spi6_cmddata, /* Provided externally */
+#endif
+ .send = lpc54_spi_send,
+#ifdef CONFIG_SPI_EXCHANGE
+ .exchange = lpc54_spi_exchange,
+#else
+ .sndblock = lpc54_spi_sndblock,
+ .recvblock = lpc54_spi_recvblock,
+#endif
+#ifdef CONFIG_SPI_CALLBACK
+ .registercallback = lpc54_spi6_register, /* Provided externally */
+#else
+ .registercallback = NULL, /* Not implemented */
+#endif
+};
+
static struct lpc54_spidev_s g_spi6_dev;
#endif
-#ifdef CONFIG_LPC54_I2C7_MASTER
+
+#ifdef CONFIG_LPC54_SPI7_MASTER
+static const struct spi_ops_s g_spi7_ops =
+{
+ .lock = lpc54_spi_lock,
+ .select = lpc54_spi7_select, /* Provided externally */
+ .setfrequency = lpc54_spi_setfrequency,
+ .setmode = lpc54_spi_setmode,
+ .setbits = lpc54_spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = NULL, /* Not supported */
+#endif
+ .status = lpc54_spi7_status, /* Provided externally */
+#ifdef CONFIG_SPI_CMDDATA
+ .cmddata = lpc54_spi7_cmddata, /* Provided externally */
+#endif
+ .send = lpc54_spi_send,
+#ifdef CONFIG_SPI_EXCHANGE
+ .exchange = lpc54_spi_exchange,
+#else
+ .sndblock = lpc54_spi_sndblock,
+ .recvblock = lpc54_spi_recvblock,
+#endif
+#ifdef CONFIG_SPI_CALLBACK
+ .registercallback = lpc54_spi7_register, /* Provided externally */
+#else
+ .registercallback = NULL, /* Not implemented */
+#endif
+};
+
static struct lpc54_spidev_s g_spi7_dev;
#endif
-#ifdef CONFIG_LPC54_I2C8_MASTER
+
+#ifdef CONFIG_LPC54_SPI8_MASTER
+static const struct spi_ops_s g_spi8_ops =
+{
+ .lock = lpc54_spi_lock,
+ .select = lpc54_spi8_select, /* Provided externally */
+ .setfrequency = lpc54_spi_setfrequency,
+ .setmode = lpc54_spi_setmode,
+ .setbits = lpc54_spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = NULL, /* Not supported */
+#endif
+ .status = lpc54_spi8_status, /* Provided externally */
+#ifdef CONFIG_SPI_CMDDATA
+ .cmddata = lpc54_spi8_cmddata, /* Provided externally */
+#endif
+ .send = lpc54_spi_send,
+#ifdef CONFIG_SPI_EXCHANGE
+ .exchange = lpc54_spi_exchange,
+#else
+ .sndblock = lpc54_spi_sndblock,
+ .recvblock = lpc54_spi_recvblock,
+#endif
+#ifdef CONFIG_SPI_CALLBACK
+ .registercallback = lpc54_spi8_register, /* Provided externally */
+#else
+ .registercallback = NULL, /* Not implemented */
+#endif
+};
+
static struct lpc54_spidev_s g_spi8_dev;
#endif
-#ifdef CONFIG_LPC54_I2C9_MASTER
+
+#ifdef CONFIG_LPC54_SPI9_MASTER
+static const struct spi_ops_s g_spi9_ops =
+{
+ .lock = lpc54_spi_lock,
+ .select = lpc54_spi9_select, /* Provided externally */
+ .setfrequency = lpc54_spi_setfrequency,
+ .setmode = lpc54_spi_setmode,
+ .setbits = lpc54_spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = NULL, /* Not supported */
+#endif
+ .status = lpc54_spi9_status, /* Provided externally */
+#ifdef CONFIG_SPI_CMDDATA
+ .cmddata = lpc54_spi9_cmddata, /* Provided externally */
+#endif
+ .send = lpc54_spi_send,
+#ifdef CONFIG_SPI_EXCHANGE
+ .exchange = lpc54_spi_exchange,
+#else
+ .sndblock = lpc54_spi_sndblock,
+ .recvblock = lpc54_spi_recvblock,
+#endif
+#ifdef CONFIG_SPI_CALLBACK
+ .registercallback = lpc54_spi9_register, /* Provided externally */
+#else
+ .registercallback = NULL, /* Not implemented */
+#endif
+};
+
static struct lpc54_spidev_s g_spi9_dev;
#endif
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc54_spi_putreg
+ *
+ * Description:
+ * Write a value to a register at the offset from the Flexcomm base.
+ *
+ ****************************************************************************/
+
+static inline void lpc54_spi_putreg(struct lpc54_spidev_s *priv,
+ unsigned int regoffset, uint32_t regval)
+{
+ putreg32(regval, priv->base + regoffset);
+}
+
+/****************************************************************************
+ * Name: lpc54_spi_getreg
+ *
+ * Description:
+ * Read the content of a register at the offset from the Flexcomm base.
+ *
+ ****************************************************************************/
+
+static inline uint32_t lpc54_spi_getreg(struct lpc54_spidev_s *priv,
+ unsigned int regoffset)
+{
+ return getreg32(priv->base + regoffset);
+}
+
+/****************************************************************************
+ * Name: lpc54_spi_fifodepth
+ *
+ * Description:
+ * Return the depth of the SPI FIFOs. This is a constant value and could
+ * be hard coded.
+ *
+ * Input Parameters:
+ * priv - Device-specific state data
+ *
+ * Returned Value:
+ * The FIFO depth in words of the configured bit width.
+ *
+ ****************************************************************************/
+
+static inline unsigned int lpc54_spi_fifodepth(FAR struct lpc54_spidev_s *priv)
+{
+ uint32_t regval = lpc54_spi_getreg(priv, LPC54_SPI_FIFOCFG_OFFSET);
+ return ((regval & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3;
+}
+
+/****************************************************************************
+ * Name: lpc54_spi_txavailable
+ *
+ * Description:
+ * Return true if the Tx FIFO is not full.
+ *
+ * Input Parameters:
+ * priv - Device-specific state data
+ *
+ * Returned Value:
+ * true: Tx FIFO is not full.
+ *
+ ****************************************************************************/
+
+static inline bool lpc54_spi_txavailable(FAR struct lpc54_spidev_s *priv)
+{
+ uint32_t regval = lpc54_spi_getreg(priv, LPC54_SPI_FIFOSTAT_OFFSET);
+ return ((regval & SPI_FIFOSTAT_TXNOTFULL) != 0);
+}
+
+/****************************************************************************
+ * Name: lpc54_spi_rxavailable
+ *
+ * Description:
+ * Return true if the Rx FIFO is not empty.
+ *
+ * Input Parameters:
+ * priv - Device-specific state data
+ *
+ * Returned Value:
+ * true: Rx FIFO is not empty.
+ *
+ ****************************************************************************/
+
+static inline bool lpc54_spi_rxavailable(FAR struct lpc54_spidev_s *priv)
+{
+ uint32_t regval = lpc54_spi_getreg(priv, LPC54_SPI_FIFOSTAT_OFFSET);
+ return ((regval & SPI_FIFOSTAT_RXNOTEMPTY) != 0);
+}
+
+/****************************************************************************
+ * Name: lpc54_spi_rxdiscard
+ *
+ * Description:
+ * Read and discard the data until the Rx FIFO is empty.
+ *
+ * Input Parameters:
+ * priv - Device-specific state data
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void lpc54_spi_rxdiscard(FAR struct lpc54_spidev_s *priv)
+{
+ while (lpc54_spi_rxavailable(priv))
+ {
+ (void)lpc54_spi_getreg(priv, LPC54_SPI_FIFORD_OFFSET);
+ }
+}
+
+/****************************************************************************
+ * Name: lpc54_spi_resetfifos
+ *
+ * Description:
+ * Clear Tx/Rx errors and empty FIFOs.
+ *
+ * Input Parameters:
+ * priv - Device-specific state data
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void lpc54_spi_resetfifos(FAR struct lpc54_spidev_s *priv)
+{
+ uint32_t regval;
+
+ /* Clear Tx/Rx errors and empty FIFOs */
+
+ regval = lpc54_spi_getreg(priv, LPC54_SPI_FIFOCFG_OFFSET);
+ regval |= (SPI_FIFOCFG_EMPTYTX | SPI_FIFOCFG_EMPTYRX);
+ lpc54_spi_putreg(priv, LPC54_SPI_FIFOCFG_OFFSET, regval);
+
+ regval = lpc54_spi_getreg(priv, LPC54_SPI_FIFOSTAT_OFFSET);
+ regval |= (SPI_FIFOSTAT_TXERR | SPI_FIFOSTAT_RXERR);
+ lpc54_spi_putreg(priv, LPC54_SPI_FIFOSTAT_OFFSET, regval);
+}
+
+/****************************************************************************
+ * Name: lpc54_spi_rxtransfer8 and lpc54_spi_rxtransfer16
+ *
+ * Description:
+ * Receive one 8- or 16-bit value from the selected SPI device.
+ *
+ * Input Parameters:
+ * priv - Device-specific state data
+ * xfr - Describes the Rx transfer
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void lpc54_spi_rxtransfer8(FAR struct lpc54_spidev_s *priv,
+ FAR struct lpc54_rxtransfer8_s *xfr)
+{
+ /* Read one byte if available and expected */
+
+ if (lpc54_spi_rxavailable(priv))
+ {
+ /* There is something in the Rx FIFO to be read. Are we expecting
+ * data in the Rx FIFO? Is there space available in the Rx buffer?
+ */
+
+ if (xfr->expected == 0 || xfr->remaining == 0)
+ {
+ /* No.. then just read and discard the data until the Rx FIFO is empty */
+
+ lpc54_spi_rxdiscard(priv);
+ xfr->expected = 0;
+ }
+ else
+ {
+ /* Read and transfer one byte */
+
+ *xfr->rxptr = lpc54_spi_getreg(priv, LPC54_SPI_FIFORD_OFFSET);
+
+ /* Update pointers and counts */
+
+ xfr->rxptr++;
+ xfr->remaining--;
+ xfr->expected--;
+ }
+ }
+}
+
+#ifdef CONFIG_LPC54_SPI_WIDEDATA
+static void lpc54_spi_rxtransfer16(FAR struct lpc54_spidev_s *priv,
+ FAR struct lpc54_rxtransfer16_s *xfr)
+{
+ /* Read one HWord if available and expected */
+
+ if (lpc54_spi_rxavailable(priv))
+ {
+ /* There is something in the Rx FIFO to be read. Are we expecting
+ * data in the Rx FIFO? Is there space available in the Rx buffer?
+ */
+
+ if (xfr->expected == 0 || xfr->remaining == 0)
+ {
+ /* No.. then just read and discard the data until the Rx FIFO
+ * is empty.
+ */
+
+ lpc54_spi_rxdiscard(priv);
+ xfr->expected = 0;
+ }
+ else
+ {
+ /* Read and transfer HWord */
+
+ *xfr->rxptr = lpc54_spi_getreg(priv, LPC54_SPI_FIFORD_OFFSET);
+
+ /* Update pointers and counts */
+
+ xfr->rxptr++;
+ xfr->remaining--;
+ xfr->expected--;
+ }
+ }
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc54_spi_txtransfer8 and lpc54_spi_txtransfer16
+ *
+ * Description:
+ * Send one 8- or 16-bit value to the selected SPI device.
+ *
+ * Input Parameters:
+ * priv - Device-specific state data
+ * xfr - Describes the Tx transfer
+ *
+ * Returned Value:
+ * true: The value was added to the TxFIFO
+ *
+ ****************************************************************************/
+
+static bool lpc54_spi_txtransfer8(FAR struct lpc54_spidev_s *priv,
+ FAR struct lpc54_txtransfer8_s *xfr)
+{
+ uint32_t regval;
+
+ /* Transmit if txFIFO is not full and there is more Tx data to be sent */
+
+ if (lpc54_spi_txavailable(priv) && xfr->remaining > 0)
+ {
+ /* Get the next byte to be sent */
+
+ regval = *xfr->txptr;
+
+ /* And send it */
+
+ regval |= xfr->txctrl;
+ lpc54_spi_putreg(priv, LPC54_SPI_FIFOWR_OFFSET, regval);
+
+ /* Update pointers and counts */
+
+ xfr->txptr++;
+ xfr->remaining--;
+
+ return true;
+ }
+
+ return false;
+}
+
+#ifdef CONFIG_LPC54_SPI_WIDEDATA
+static bool lpc54_spi_txtransfer16(FAR struct lpc54_spidev_s *priv,
+ FAR struct lpc54_txtransfer16_s *xfr)
+{
+ uint32_t regval;
+
+ /* Transmit if txFIFO is not full and there is more Tx data to be sent */
+
+ if (lpc54_spi_txavailable(priv) && xfr->remaining > 0)
+ {
+ /* Get the next byte to be sent */
+
+ regval = *xfr->txptr;
+
+ /* And send it */
+
+ regval |= xfr->txctrl;
+ lpc54_spi_putreg(priv, LPC54_SPI_FIFOWR_OFFSET, regval);
+
+ /* Update pointers and counts */
+
+ xfr->txptr++;
+ xfr->remaining--;
+
+ return true;
+ }
+
+ return false;
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc54_spi_txdummy
+ *
+ * Description:
+ * Send dummy Tx data when we really only care about the Rx data.
+ *
+ * Input Parameters:
+ * priv - Device-specific state data
+ * xfr - Describes the Tx transfer
+ *
+ * Returned Value:
+ * true: The dummy value was added to the TxFIFO
+ *
+ ****************************************************************************/
+
+static bool lpc54_spi_txdummy(FAR struct lpc54_spidev_s *priv,
+ FAR struct lpc54_txdummy_s *xfr)
+{
+ /* Transmit if txFIFO is not full and there is more Tx data to be sent */
+
+ if (lpc54_spi_txavailable(priv) && xfr->remaining > 0)
+ {
+ /* Send the dummy data */
+
+ lpc54_spi_putreg(priv, LPC54_SPI_FIFOWR_OFFSET, xfr->txctrl);
+
+ /* Update counts */
+
+ xfr->remaining--;
+ return true;
+ }
+
+ return false;
+}
+
+/****************************************************************************
+ * Name: lpc54_spi_exchange8 and lpc54_spi_exchange16
+ *
+ * Description:
+ * Implements the SPI exchange method for the case of 8- and 16-bit transfers.
+ *
+ * Input Parameters:
+ * priv - Device-specific state data
+ * txbuffer - A pointer to the buffer of data to be sent
+ * rxbuffer - A pointer to a buffer in which to receive data
+ * nwords - the length of data to be exchanged in units of words.
+ * The wordsize is determined by the number of bits-per-word
+ * selected for the SPI interface. If nbits <= 8, the data is
+ * packed into uint8_t's; if nbits >8, the data is packed into
+ * uint16_t's
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_EXCHANGE
+static void lpc54_spi_exchange8(FAR struct lpc54_spidev_s *priv,
+ FAR const void *txbuffer, FAR void *rxbuffer,
+ size_t nwords)
+{
+ struct lpc54_rxtransfer8_s rxtransfer;
+ struct lpc54_txtransfer8_s txtransfer;
+ unsigned int depth;
+
+ DEBUGASSERT(rxbuffer != NULL && txbuffer != NULL);
+
+ /* Get the FIFO depth */
+
+ depth = lpc54_spi_fifodepth(priv);
+
+ /* Set up the transfer data */
+
+ txtransfer.txctrl = SPI_FIFOWR_LEN(priv->nbits) | SPI_FIFOWR_TXSSELN_ALL;
+ txtransfer.txptr = (FAR uint8_t *)txbuffer;
+ txtransfer.remaining = nwords;
+ rxtransfer.rxptr = (FAR uint8_t *)rxbuffer;
+ rxtransfer.remaining = nwords;
+ rxtransfer.expected = 0;
+
+ /* Clear Tx/Rx errors and empty FIFOs */
+
+ lpc54_spi_resetfifos(priv);
+
+ /* Loop until all Tx data has been sent and until all Rx data has been
+ * received.
+ */
+
+ while (txtransfer.remaining != 0 || rxtransfer.remaining != 0)
+ {
+ /* Transfer one byte from the Rx FIFO to the caller's Rx buffer */
+
+ lpc54_spi_rxtransfer8(priv, &rxtransfer);
+
+ /* If sending another byte would exceed the capacity of the Rx FIFO
+ * then read-only until there space freed.
+ */
+
+ if (rxtransfer.expected < depth)
+ {
+ /* Attempt to transfer one byte from the caller's Tx buffer to
+ * the Tx FIFO.
+ */
+
+ if (lpc54_spi_txtransfer8(priv, &txtransfer))
+ {
+ /* Increment the Rx expected count if successful */
+
+ rxtransfer.expected++;
+ }
+ }
+ }
+}
+#endif /* CONFIG_SPI_EXCHANGE */
+
+#if defined(CONFIG_SPI_EXCHANGE) && defined(CONFIG_LPC54_SPI_WIDEDATA)
+static void lpc54_spi_exchange16(FAR struct lpc54_spidev_s *priv,
+ FAR const void *txbuffer, FAR void *rxbuffer,
+ size_t nwords)
+{
+ struct lpc54_rxtransfer16_s rxtransfer;
+ struct lpc54_txtransfer16_s txtransfer;
+ uint32_t regval;
+ unsigned int depth;
+
+ DEBUGASSERT(rxbuffer != NULL && ((uintptr_t)rxbuffer & 1) == 0);
+ DEBUGASSERT(txbuffer != NULL && ((uintptr_t)txbuffer & 1) == 0);
+
+ /* Get the FIFO depth */
+
+ depth = lpc54_spi_fifodepth(priv);
-/****************************************************************************
- * Name: lpc54_spi_putreg
- *
- * Description:
- * Write a value to a register at the offset from the Flexcomm base.
- *
- ****************************************************************************/
+ /* Set up the transfer data */
-static inline void lpc54_spi_putreg(struct lpc54_spidev_s *priv,
- unsigned int regoffset, uint32_t regval)
-{
- putreg32(value, priv->base + regoffset);
+ txtransfer.txctrl = SPI_FIFOWR_LEN(priv->nbits) | SPI_FIFOWR_TXSSELN_ALL;
+ txtransfer.txptr = (FAR uint16_t *)txbuffer;
+ txtransfer.remaining = nwords;
+ rxtransfer.rxptr = (FAR uint16_t *)rxbuffer;
+ rxtransfer.remaining = nwords;
+ rxtransfer.expected = 0;
+
+ /* Clear Tx/Rx errors and empty FIFOs */
+
+ lpc54_spi_resetfifos(priv);
+
+ /* Loop until all Tx data has been sent and until all Rx data has been
+ * received.
+ */
+
+ while (txtransfer.remaining || rxtransfer.remaining || rxtransfer.expected)
+ {
+ /* Transfer one HWord from the Rx FIFO to the caller's Rx buffer */
+
+ lpc54_spi_rxtransfer16(priv, &rxtransfer);
+
+ /* If sending another byte would exceed the capacity of the Rx FIFO
+ * then read-only until there space freed.
+ */
+
+ if (rxtransfer.expected < depth)
+ {
+ /* Attempt to send one more byte */
+
+ if (lpc54_spi_txtransfer16(priv, &txtransfer))
+ {
+ /* Increment the Rx expected count if successful */
+
+ rxtransfer.expected++;
+ }
+ }
+ }
}
+#endif /* CONFIG_SPI_EXCHANGE && CONFIG_LPC54_SPI_WIDEDATA */
/****************************************************************************
- * Name: lpc54_spi_gettreg
+ * Name: lpc54_spi_sndblock8 and lpc54_spi_sndblock16
*
* Description:
- * Read the content of a register at the offset from the Flexcomm base.
+ * Implements the SPI sndblock method for the case of 8- and 16-bit
+ * transfers.
+ *
+ * Input Parameters:
+ * priv - Device-specific state data
+ * buffer - A pointer to the buffer of data to be sent
+ * nwords - the length of data to send from the buffer in number of words.
+ * The wordsize is determined by the number of bits-per-word
+ * selected for the SPI interface. If nbits <= 8, the data is
+ * packed into uint8_t's; if nbits >8, the data is packed into
+ * uint16_t's
+ *
+ * Returned Value:
+ * None
*
****************************************************************************/
-static inline void lpc54_spi_gettreg(struct lpc54_spidev_s *priv,
- unsigned int regoffset)
+static void lpc54_spi_sndblock8(FAR struct lpc54_spidev_s *priv,
+ FAR const void *buffer, size_t nwords)
{
- return getreg32(priv->base + regoffset);
+ struct lpc54_txtransfer8_s txtransfer;
+
+ DEBUGASSERT(buffer != NULL);
+
+ /* Set up the transfer data. NOTE that we are ignoring returned Rx data */
+
+ txtransfer.txctrl = SPI_FIFOWR_RXIGNORE | SPI_FIFOWR_LEN(priv->nbits) |
+ SPI_FIFOWR_TXSSELN_ALL;
+ txtransfer.txptr = (FAR uint8_t *)buffer;
+ txtransfer.remaining = nwords;
+
+ /* Clear Tx/Rx errors and empty FIFOs */
+
+ lpc54_spi_resetfifos(priv);
+
+ /* Loop until all Tx data has been sent */
+
+ while (txtransfer.remaining != 0)
+ {
+ /* Attempt to transfer one byte from the caller's Tx buffer to the
+ * Tx FIFO.
+ */
+
+ (void)lpc54_spi_txtransfer8(priv, &txtransfer);
+ }
+}
+
+#ifdef CONFIG_LPC54_SPI_WIDEDATA
+static void lpc54_spi_sndblock16(FAR struct lpc54_spidev_s *priv,
+ FAR const void *buffer, size_t nwords)
+{
+ struct lpc54_txtransfer16_s txtransfer;
+
+ DEBUGASSERT(buffer != NULL);
+
+ /* Set up the transfer data. NOTE that we are ignoring returned Rx data */
+
+ txtransfer.txctrl = SPI_FIFOWR_RXIGNORE | SPI_FIFOWR_LEN(priv->nbits) |
+ SPI_FIFOWR_TXSSELN_ALL;
+ txtransfer.txptr = (FAR uint16_t *)buffer;
+ txtransfer.remaining = nwords;
+
+ /* Clear Tx/Rx errors and empty FIFOs */
+
+ lpc54_spi_resetfifos(priv);
+
+ /* Loop until all Tx data has been sent and until all Rx data has been
+ * received.
+ */
+
+ while (txtransfer.remaining != 0)
+ {
+ /* Attempt to transfer one byte from the caller's Tx buffer to the
+ * Tx FIFO.
+ */
+
+ lpc54_spi_txtransfer16(priv, &txtransfer);
+ }
}
+#endif /*CONFIG_LPC54_SPI_WIDEDATA */
/****************************************************************************
- * Name: lpc54_spi_16bitmode
+ * Name: lpc54_spi_recvblock8 and lpc54_spi_recvblock16
*
* Description:
- * Check if the SPI is operating in > 8-bit mode (16-bit accesses)
+ * Implements the SPI recvblock method for the case of 8- and 16-bit
+ * transfers.
*
* Input Parameters:
- * priv - Device-specific state data
+ * priv - Device-specific state data
+ * buffer - A pointer to the buffer in which to receive data
+ * nwords - the length of data that can be received in the buffer in
+ * number of words. The wordsize is determined by the number of
+ * bits-per-word selected for the SPI interface. If nbits <= 8,
+ * the data is packed into uint8_t's; if nbits >8, the data is
+ * packed into uint16_t's
*
* Returned Value:
- * true: 16-bit mode, false: 8-bit mode
+ * None
*
****************************************************************************/
-static inline bool lpc54_spi_16bitmode(FAR struct lpc54_spidev_s *priv)
+static void lpc54_spi_recvblock8(FAR struct lpc54_spidev_s *priv,
+ FAR void *buffer, size_t nwords)
{
-#warning Missing logic
- return false;
+ struct lpc54_rxtransfer8_s rxtransfer;
+ struct lpc54_txdummy_s txtransfer;
+ unsigned int depth;
+
+ DEBUGASSERT(buffer != NULL);
+
+ /* Get the FIFO depth */
+
+ depth = lpc54_spi_fifodepth(priv);
+
+ /* Set up the transfer data */
+
+ txtransfer.txctrl = SPI_DUMMYDATA8 | SPI_FIFOWR_LEN(priv->nbits) |
+ SPI_FIFOWR_TXSSELN_ALL;
+ txtransfer.remaining = nwords;
+ rxtransfer.rxptr = (FAR uint8_t *)buffer;
+ rxtransfer.remaining = nwords;
+ rxtransfer.expected = 0;
+
+ /* Clear Tx/Rx errors and empty FIFOs */
+
+ lpc54_spi_resetfifos(priv);
+
+ /* Loop until all Tx data has been sent and until all Rx data has been
+ * received.
+ */
+
+ while (txtransfer.remaining != 0|| rxtransfer.remaining != 0)
+ {
+ /* Transfer one byte from the Rx FIFO to the caller's Rx buffer */
+
+ lpc54_spi_rxtransfer8(priv, &rxtransfer);
+
+ /* If sending another byte would exceed the capacity of the Rx FIFO
+ * then read-only until there space freed.
+ */
+
+ if (rxtransfer.expected < depth)
+ {
+ /* Attempt to transfer one dummy byte to the Tx FIFO. */
+
+ if (lpc54_spi_txdummy(priv, &txtransfer))
+ {
+ /* Increment the Rx expected count if successful */
+
+ rxtransfer.expected++;
+ }
+ }
+ }
+}
+
+#ifdef CONFIG_LPC54_SPI_WIDEDATA
+static void lpc54_spi_recvblock16(FAR struct lpc54_spidev_s *priv,
+ FAR void *buffer, size_t nwords)
+{
+ struct lpc54_rxtransfer16_s rxtransfer;
+ struct lpc54_txdummy_s txtransfer;
+ unsigned int depth;
+
+ DEBUGASSERT(buffer != NULL);
+
+ /* Get the FIFO depth */
+
+ depth = lpc54_spi_fifodepth(priv);
+
+ /* Set up the transfer data */
+
+ txtransfer.txctrl = SPI_DUMMYDATA16 | SPI_FIFOWR_LEN(priv->nbits) |
+ SPI_FIFOWR_TXSSELN_ALL;
+ txtransfer.remaining = nwords;
+ rxtransfer.rxptr = (FAR uint16_t *)rxbuffer;
+ rxtransfer.remaining = nwords;
+ rxtransfer.expected = 0;
+
+ /* Clear Tx/Rx errors and empty FIFOs */
+
+ lpc54_spi_resetfifos(priv);
+
+ /* Loop until all Tx data has been sent and until all Rx data has been
+ * received.
+ */
+
+ while (txtransfer.remaining || rxtransfer.remaining || rxtransfer.expected)
+ {
+ /* Transfer one HWord from the Rx FIFO to the caller's Rx buffer */
+
+ lpc54_spi_rxtransfer16(priv, &rxtransfer);
+
+ /* If sending another byte would exceed the capacity of the Rx FIFO
+ * then read-only until there space freed.
+ */
+
+ if (rxtransfer.expected < depth)
+ {
+ /* Attempt to transfer one dummy HWord to the Tx FIFO. */
+
+ if (lpc54_spi_txdummy(priv, &txtransfer))
+ {
+ /* Increment the Rx expected count if successful */
+
+ rxtransfer.expected++;
+ }
+ }
+ }
}
+#endif /* CONFIG_LPC54_SPI_WIDEDATA */
/****************************************************************************
* Name: lpc54_spi_lock
*
* Description:
- * On SPI busses where there are multiple devices, it will be necessary to
- * lock SPI to have exclusive access to the busses for a sequence of
+ * On SPI buses where there are multiple devices, it will be necessary to
+ * lock SPI to have exclusive access to the buses for a sequence of
* transfers. The bus should be locked before the chip is selected. After
* locking the SPI bus, the caller should then also call the setfrequency,
* setbits, and setmode methods to make sure that the SPI is properly
@@ -303,11 +1308,15 @@ static uint32_t lpc54_spi_setfrequency(FAR struct spi_dev_s *dev,
uint32_t frequency)
{
FAR struct lpc54_spidev_s *priv = (FAR struct lpc54_spidev_s *)dev;
+ uint32_t divider;
uint32_t actual;
+ uint32_t regval;
- /* Check if the requested frequence is the same as the frequency selection */
+ /* Check if the requested frequency is the same as the current frequency
+ * selection.
+ */
- DEBUGASSERT(priv && frequency <= priv->fclock / 2);
+ DEBUGASSERT(priv != NULL && frequency <= priv->fclock / 2);
if (priv->frequency == frequency)
{
@@ -317,7 +1326,21 @@ static uint32_t lpc54_spi_setfrequency(FAR struct spi_dev_s *dev,
}
/* Set the new SPI frequency */
-#warning Missing logic
+
+ divider = priv->fclock / frequency;
+ if (divider > 0x10000)
+ {
+ divider = 0x10000;
+ }
+
+ regval = lpc54_spi_getreg(priv, LPC54_SPI_DIV_OFFSET);
+ regval &= ~SPI_DIV_MASK;
+ regval |= SPI_DIV(divider);
+ lpc54_spi_putreg(priv, LPC54_SPI_DIV_OFFSET, regval);
+
+ /* Calculate the actual frequency */
+
+ actual = priv->fclock / divider;
/* Save the frequency setting */
@@ -354,24 +1377,25 @@ static void lpc54_spi_setmode(FAR struct spi_dev_s *dev,
if (mode != priv->mode)
{
/* Yes... Set the new mode */
-#warning Missing logic
+
+ regval = lpc54_spi_getreg(priv, LPC54_SPI_CFG_OFFSET);
+ regval &= ~(SPI_CFG_CPHA | SPI_CFG_CPOL);
switch (mode)
{
case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
-#warning Missing logic
break;
case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
-#warning Missing logic
+ regval |= SPI_CFG_CPHA;
break;
case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
-#warning Missing logic
+ regval |= SPI_CFG_CPOL;
break;
case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
-#warning Missing logic
+ regval |= (SPI_CFG_CPHA | SPI_CFG_CPOL);
break;
default:
@@ -379,9 +1403,9 @@ static void lpc54_spi_setmode(FAR struct spi_dev_s *dev,
return;
}
-#warning Missing logic
+ lpc54_spi_putreg(priv, LPC54_SPI_CFG_OFFSET, regval);
- /* Save the mode so that subsequent re-configuratins will be faster */
+ /* Save the mode so that subsequent re-configurations will be faster */
priv->mode = mode;
}
@@ -405,18 +1429,14 @@ static void lpc54_spi_setmode(FAR struct spi_dev_s *dev,
static void lpc54_spi_setbits(FAR struct spi_dev_s *dev, int nbits)
{
FAR struct lpc54_spidev_s *priv = (FAR struct lpc54_spidev_s *)dev;
- uint32_t regval;
- /* Has the number of bits changed? */
+ /* The valid range of bit selections is SPI_MINWIDTH through SPI_MAXWIDTH */
- DEBUGASSERT(priv && nbits > 7 && nbits < 17);
+ DEBUGASSERT(priv != NULL && nbits >= SPI_MINWIDTH && nbits <= SPI_MAXWIDTH);
- if (nbits != priv->nbits)
+ if (nbits >= SPI_MINWIDTH && nbits <= SPI_MAXWIDTH)
{
- /* Yes... Set the number word width */
-#warning Missing logic
-
- /* Save the selection so the subsequence re-configurations will be faster */
+ /* Save the selection. It will be applied when data is transferred. */
priv->nbits = nbits;
}
@@ -440,28 +1460,46 @@ static void lpc54_spi_setbits(FAR struct spi_dev_s *dev, int nbits)
static uint16_t lpc54_spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
{
- uint16_t ret;
+ FAR struct lpc54_spidev_s *priv = (FAR struct lpc54_spidev_s *)dev;
+ uint32_t regval;
- /* Write the data to transmitted to the SPI Data Register */
-#warning Missing logic
+ DEBUGASSERT(priv != NULL);
- /* Read the SPI Status Register again to clear the status bit */
-#warning Missing logic
+ /* Clear Tx/Rx errors and empty FIFOs */
- return ret;
+ lpc54_spi_resetfifos(priv);
+
+ /* Send the word. Since we just reset the FIFOs, we assume that the Tx
+ * FIFO is not full and that the Rx FIFO is empty.
+ */
+
+ DEBUGASSERT(lpc54_spi_txavailable(priv) || !lpc54_spi_rxavailable(priv));
+
+ regval = wd | SPI_FIFOWR_LEN(priv->nbits) | SPI_FIFOWR_TXSSELN_ALL;
+ lpc54_spi_putreg(priv, LPC54_SPI_FIFOWR_OFFSET, regval);
+
+ /* Wait for the Rx FIFO to become non-empty. */
+
+ while (!lpc54_spi_rxavailable(priv))
+ {
+ }
+
+ /* Then read and return the value from the Rx FIFO */
+
+ return (uint16_t)lpc54_spi_getreg(priv, LPC54_SPI_FIFORD_OFFSET);
}
/****************************************************************************
- * Name: lpc54_spi_exchange (no DMA). aka lpc54_spi_exchange_nodma
+ * Name: lpc54_spi_exchange
*
* Description:
- * Exchange a block of data on SPI without using DMA
+ * Exchange a block of data on SPI
*
* Input Parameters:
* dev - Device-specific state data
* txbuffer - A pointer to the buffer of data to be sent
* rxbuffer - A pointer to a buffer in which to receive data
- * nwords - the length of data to be exchaned in units of words.
+ * nwords - the length of data to be exchanged in units of words.
* The wordsize is determined by the number of bits-per-word
* selected for the SPI interface. If nbits <= 8, the data is
* packed into uint8_t's; if nbits >8, the data is packed into
@@ -472,125 +1510,52 @@ static uint16_t lpc54_spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
*
****************************************************************************/
-#ifndef CONFIG_LPC54_SPI_MASTER_DMA
-static void lpc54_spi_exchange(FAR struct spi_dev_s *dev,
+#ifdef CONFIG_SPI_EXCHANGE
+static void lpc54_spi_exchange(FAR struct lpc54_spidev_s *priv,
FAR const void *txbuffer, FAR void *rxbuffer,
size_t nwords)
-#else
-static void lpc54_spi_exchange_nodma(FAR struct spi_dev_s *dev,
- FAR const void *txbuffer,
- FAR void *rxbuffer, size_t nwords)
-#endif
{
FAR struct lpc54_spidev_s *priv = (FAR struct lpc54_spidev_s *)dev;
- DEBUGASSERT(priv && priv->base);
- spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n",
- txbuffer, rxbuffer, nwords);
+ DEBUGASSERT(priv != NULL);
- /* 8- or 16-bit mode? */
+ /* If there is no data sink, then handle this transfer with
+ * lpc54_spi_sndblock().
+ */
- if (lpc54_spi_16bitmode(priv))
+ if (rxbuffer == NULL)
{
- /* 16-bit mode */
-
- const uint16_t *src = (const uint16_t *)txbuffer;
- uint16_t *dest = (uint16_t *)rxbuffer;
- uint16_t word;
-
- while (nwords-- > 0)
- {
- /* Get the next word to write. Is there a source buffer? */
-
- if (src)
- {
- word = *src++;
- }
- else
- {
- word = 0xffff;
- }
-
- /* Exchange one word */
-
- word = spi_send(dev, word);
-
- /* Is there a buffer to receive the return value? */
-
- if (dest)
- {
- *dest++ = word;
- }
- }
+ lpc54_spi_sndblock(priv, txbuffer, nwords)
}
- else
- {
- /* 8-bit mode */
-
- const uint8_t *src = (const uint8_t *)txbuffer;
- uint8_t *dest = (uint8_t *)rxbuffer;
- uint8_t word;
-
- while (nwords-- > 0)
- {
- /* Get the next word to write. Is there a source buffer? */
-
- if (src)
- {
- word = *src++;
- }
- else
- {
- word = 0xff;
- }
- /* Exchange one word */
+ /* If there is no data source, then handle this transfer with
+ * lpc54_spi_recvblock().
+ */
- word = (uint8_t)spi_send(dev, (uint16_t)word);
+ else if (txbuffer == NULL)
+ {
+ lpc54_spi_recvblock(priv, rxbuffer, nwords)
+ }
- /* Is there a buffer to receive the return value? */
+#ifdef CONFIG_LPC54_SPI_WIDEDATA
+ /* If the data with is > 8-bits, then handle this transfer with
+ * lpc54_spi_exchange16().
+ */
- if (dest)
- {
- *dest++ = word;
- }
- }
+ else if (priv->nbits > 8)
+ {
+ lpc54_spi_exchange16(priv, txbuffer, rxbuffer, nwords);
}
-}
-
-/****************************************************************************
- * Name: lpc54_spi_exchange (no DMA). aka lpc54_spi_exchange_nodma
- *
- * Description:
- * Exchange a block of data on SPI without using DMA
- *
- * Input Parameters:
- * dev - Device-specific state data
- * txbuffer - A pointer to the buffer of data to be sent
- * rxbuffer - A pointer to a buffer in which to receive data
- * nwords - the length of data to be exchaned in units of words.
- * The wordsize is determined by the number of bits-per-word
- * selected for the SPI interface. If nbits <= 8, the data is
- * packed into uint8_t's; if nbits >8, the data is packed into
- * uint16_t's
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
+#endif
-#ifdef CONFIG_LPC54_SPI_MASTER_DMA
-static void lpc54_spi_exchange(FAR struct spi_dev_s *dev,
- FAR const void *txbuffer, FAR void *rxbuffer,
- size_t nwords)
-{
- /* If the transfer is small, then perform the exchange without using DMA. */
-#warning Missing logic
+ /* Otherwise, let lpc54_spi_exchange8() do the job */
- /* Otherwise, use DMA */
-#warning Missing logic
+ else if (priv->nbits > 8)
+ {
+ lpc54_spi_exchange8(priv, txbuffer, rxbuffer, nwords);
+ }
}
-#endif /* CONFIG_LPC54_SPI_MASTER_DMA */
+#endif /* CONFIG_SPI_EXCHANGE */
/****************************************************************************
* Name: lpc54_spi_sndblock
@@ -615,8 +1580,28 @@ static void lpc54_spi_exchange(FAR struct spi_dev_s *dev,
static void lpc54_spi_sndblock(FAR struct spi_dev_s *dev,
FAR const void *buffer, size_t nwords)
{
- spiinfo("txbuffer=%p nwords=%d\n", txbuffer, nwords);
- return lpc54_spi_exchange(dev, txbuffer, NULL, nwords);
+ FAR struct lpc54_spidev_s *priv = (FAR struct lpc54_spidev_s *)dev;
+
+ spiinfo("buffer=%p nwords=%d\n", buffer, nwords);
+ DEBUGASSERT(priv != NULL && buffer != NULL);
+
+#ifdef CONFIG_LPC54_SPI_WIDEDATA
+ /* If the data with is > 8-bits, then handle this transfer with
+ * lpc54_spi_sndblock16().
+ */
+
+ if (priv->nbits > 8)
+ {
+ lpc54_spi_sndblock16(priv, buffer, nwords);
+ }
+
+ /* Otherwise, let lpc54_spi_sndblock8() do the job */
+
+ else if (priv->nbits > 8)
+#endif
+ {
+ lpc54_spi_sndblock8(priv, buffer, nwords);
+ }
}
/****************************************************************************
@@ -627,7 +1612,7 @@ static void lpc54_spi_sndblock(FAR struct spi_dev_s *dev,
*
* Input Parameters:
* dev - Device-specific state data
- * buffer - A pointer to the buffer in which to recieve data
+ * buffer - A pointer to the buffer in which to receive data
* nwords - the length of data that can be received in the buffer in
* number of words. The wordsize is determined by the number of
* bits-per-word selected for the SPI interface. If nbits <= 8,
@@ -642,8 +1627,28 @@ static void lpc54_spi_sndblock(FAR struct spi_dev_s *dev,
static void lpc54_spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
size_t nwords)
{
- spiinfo("rxbuffer=%p nwords=%d\n", rxbuffer, nwords);
- return lpc54_spi_exchange(dev, NULL, rxbuffer, nwords);
+ FAR struct lpc54_spidev_s *priv = (FAR struct lpc54_spidev_s *)dev;
+
+ spiinfo("buffer=%p nwords=%d\n", buffer, nwords);
+ DEBUGASSERT(priv != NULL && buffer != NULL);
+
+#ifdef CONFIG_LPC54_SPI_WIDEDATA
+ /* If the data with is > 8-bits, then handle this transfer with
+ * lpc54_spi_recvblock16().
+ */
+
+ if (priv->nbits > 8)
+ {
+ lpc54_spi_recvblock16(priv, buffer, nwords);
+ }
+
+ /* Otherwise, let lpc54_spi_recvblock8() do the job */
+
+ else if (priv->nbits > 8)
+#endif
+ {
+ lpc54_spi_recvblock8(priv, buffer, nwords);
+ }
}
/****************************************************************************
@@ -660,7 +1665,7 @@ static void lpc54_spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
* ...
* 9 - SSP9
*
- * Input Parameter:
+ * Input Parameters:
* port - SPI peripheral number. 0..9
*
* Returned Value:
@@ -672,15 +1677,16 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
{
struct lpc54_spidev_s *priv;
irqstate_t flags;
+ uint32_t regval;
flags = enter_critical_section();
- /* Configure the requestin SPI peripheral */
+ /* Configure the requested SPI peripheral */
/* NOTE: The basic FLEXCOMM initialization was performed in
* lpc54_lowputc.c.
*/
-#ifdef CONFIG_LPC54_I2C0_MASTER
+#ifdef CONFIG_LPC54_SPI0_MASTER
if (port == 0)
{
/* Attach 12 MHz clock to FLEXCOMM0 */
@@ -698,14 +1704,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi0_dev;
priv->base = LPC54_FLEXCOMM0_BASE;
- priv->irqid = LPC54_IRQ_FLEXCOMM0;
+ priv->irq = LPC54_IRQ_FLEXCOMM0;
priv->fclock = BOARD_FLEXCOMM0_FCLK;
+ priv->dev.ops = &g_spi0_ops;
/* Configure SPI pins (defined in board.h) */
- lpc54_gpio_config(GPIO_I2C0_SCK);
- lpc54_gpio_config(GPIO_I2C0_MOSI);
- lpc54_gpio_config(GPIO_I2C0_MISO);
+ lpc54_gpio_config(GPIO_SPI0_SCK);
+ lpc54_gpio_config(GPIO_SPI0_MOSI);
+ lpc54_gpio_config(GPIO_SPI0_MISO);
/* Set up the FLEXCOMM0 function clock */
@@ -713,7 +1720,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
}
else
#endif
-#ifdef CONFIG_LPC54_I2C1_MASTER
+#ifdef CONFIG_LPC54_SPI1_MASTER
if (port == 1)
{
/* Attach 12 MHz clock to FLEXCOMM1 */
@@ -731,14 +1738,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi1_dev;
priv->base = LPC54_FLEXCOMM1_BASE;
- priv->irqid = LPC54_IRQ_FLEXCOMM1;
+ priv->irq = LPC54_IRQ_FLEXCOMM1;
priv->fclock = BOARD_FLEXCOMM1_FCLK;
+ priv->dev.ops = &g_spi1_ops;
/* Configure SPI pins (defined in board.h) */
- lpc54_gpio_config(GPIO_I2C1_SCK);
- lpc54_gpio_config(GPIO_I2C1_MOSI);
- lpc54_gpio_config(GPIO_I2C1_MISO);
+ lpc54_gpio_config(GPIO_SPI1_SCK);
+ lpc54_gpio_config(GPIO_SPI1_MOSI);
+ lpc54_gpio_config(GPIO_SPI1_MISO);
/* Set up the FLEXCOMM1 function clock */
@@ -746,7 +1754,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
}
else
#endif
-#ifdef CONFIG_LPC54_I2C2_MASTER
+#ifdef CONFIG_LPC54_SPI2_MASTER
if (port == 2)
{
/* Attach 12 MHz clock to FLEXCOMM2 */
@@ -764,14 +1772,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi2_dev;
priv->base = LPC54_FLEXCOMM2_BASE;
- priv->irqid = LPC54_IRQ_FLEXCOMM2;
+ priv->irq = LPC54_IRQ_FLEXCOMM2;
priv->fclock = BOARD_FLEXCOMM2_FCLK;
+ priv->dev.ops = &g_spi2_ops;
/* Configure SPI pins (defined in board.h) */
- lpc54_gpio_config(GPIO_I2C2_SCK);
- lpc54_gpio_config(GPIO_I2C2_MOSI);
- lpc54_gpio_config(GPIO_I2C2MISO);
+ lpc54_gpio_config(GPIO_SPI2_SCK);
+ lpc54_gpio_config(GPIO_SPI2_MOSI);
+ lpc54_gpio_config(GPIO_SPI2MISO);
/* Set up the FLEXCOMM2 function clock */
@@ -779,7 +1788,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
}
else
#endif
-#ifdef CONFIG_LPC54_I2C3_MASTER
+#ifdef CONFIG_LPC54_SPI3_MASTER
if (port == 3)
{
/* Attach 12 MHz clock to FLEXCOMM3 */
@@ -797,14 +1806,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi3_dev;
priv->base = LPC54_FLEXCOMM3_BASE;
- priv->irqid = LPC54_IRQ_FLEXCOMM3;
+ priv->irq = LPC54_IRQ_FLEXCOMM3;
priv->fclock = BOARD_FLEXCOMM3_FCLK;
+ priv->dev.ops = &g_spi3_ops;
/* Configure SPI pins (defined in board.h) */
- lpc54_gpio_config(GPIO_I2C3_SCK);
- lpc54_gpio_config(GPIO_I2C3_MOSI);
- lpc54_gpio_config(GPIO_I2C3_MISO);
+ lpc54_gpio_config(GPIO_SPI3_SCK);
+ lpc54_gpio_config(GPIO_SPI3_MOSI);
+ lpc54_gpio_config(GPIO_SPI3_MISO);
/* Set up the FLEXCOMM3 function clock */
@@ -812,7 +1822,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
}
else
#endif
-#ifdef CONFIG_LPC54_I2C4_MASTER
+#ifdef CONFIG_LPC54_SPI4_MASTER
if (port == 4)
{
/* Attach 12 MHz clock to FLEXCOMM4 */
@@ -830,14 +1840,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi4_dev;
priv->base = LPC54_FLEXCOMM4_BASE;
- priv->irqid = LPC54_IRQ_FLEXCOMM4;
+ priv->irq = LPC54_IRQ_FLEXCOMM4;
priv->fclock = BOARD_FLEXCOMM4_FCLK;
+ priv->dev.ops = &g_spi4_ops;
/* Configure SPI pins (defined in board.h) */
- lpc54_gpio_config(GPIO_I2C4_SCK);
- lpc54_gpio_config(GPIO_I2C4_MOSI);
- lpc54_gpio_config(GPIO_I2C4_MISO);
+ lpc54_gpio_config(GPIO_SPI4_SCK);
+ lpc54_gpio_config(GPIO_SPI4_MOSI);
+ lpc54_gpio_config(GPIO_SPI4_MISO);
/* Set up the FLEXCOMM4 function clock */
@@ -845,7 +1856,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
}
else
#endif
-#ifdef CONFIG_LPC54_I2C5_MASTER
+#ifdef CONFIG_LPC54_SPI5_MASTER
if (port == 5)
{
/* Attach 12 MHz clock to FLEXCOMM5 */
@@ -863,14 +1874,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi5_dev;
priv->base = LPC54_FLEXCOMM5_BASE;
- priv->irqid = LPC54_IRQ_FLEXCOMM5;
+ priv->irq = LPC54_IRQ_FLEXCOMM5;
priv->fclock = BOARD_FLEXCOMM5_FCLK;
+ priv->dev.ops = &g_spi5_ops;
/* Configure SPI pins (defined in board.h) */
- lpc54_gpio_config(GPIO_I2C5_SCK);
- lpc54_gpio_config(GPIO_I2C5_MOSI);
- lpc54_gpio_config(GPIO_I2C5_MISO);
+ lpc54_gpio_config(GPIO_SPI5_SCK);
+ lpc54_gpio_config(GPIO_SPI5_MOSI);
+ lpc54_gpio_config(GPIO_SPI5_MISO);
/* Set up the FLEXCOMM5 function clock */
@@ -878,7 +1890,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
}
else
#endif
-#ifdef CONFIG_LPC54_I2C6_MASTER
+#ifdef CONFIG_LPC54_SPI6_MASTER
if (port == 6)
{
/* Attach 12 MHz clock to FLEXCOMM6 */
@@ -896,14 +1908,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi6_dev;
priv->base = LPC54_FLEXCOMM6_BASE;
- priv->irqid = LPC54_IRQ_FLEXCOMM6;
+ priv->irq = LPC54_IRQ_FLEXCOMM6;
priv->fclock = BOARD_FLEXCOMM6_FCLK;
+ priv->dev.ops = &g_spi6_ops;
/* Configure SPI pins (defined in board.h) */
- lpc54_gpio_config(GPIO_I2C6_SCK);
- lpc54_gpio_config(GPIO_I2C6_MOSI);
- lpc54_gpio_config(GPIO_I2C6_MISO);
+ lpc54_gpio_config(GPIO_SPI6_SCK);
+ lpc54_gpio_config(GPIO_SPI6_MOSI);
+ lpc54_gpio_config(GPIO_SPI6_MISO);
/* Set up the FLEXCOMM6 function clock */
@@ -911,7 +1924,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
}
else
#endif
-#ifdef CONFIG_LPC54_I2C7_MASTER
+#ifdef CONFIG_LPC54_SPI7_MASTER
if (port == 7)
{
/* Attach 12 MHz clock to FLEXCOMM7 */
@@ -929,14 +1942,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi7_dev;
priv->base = LPC54_FLEXCOMM7_BASE;
- priv->irqid = LPC54_IRQ_FLEXCOMM7;
+ priv->irq = LPC54_IRQ_FLEXCOMM7;
priv->fclock = BOARD_FLEXCOMM7_FCLK;
+ priv->dev.ops = &g_spi7_ops;
/* Configure SPI pins (defined in board.h) */
- lpc54_gpio_config(GPIO_I2C7_SCK);
- lpc54_gpio_config(GPIO_I2C7_MOSI);
- lpc54_gpio_config(GPIO_I2C7_MISO);
+ lpc54_gpio_config(GPIO_SPI7_SCK);
+ lpc54_gpio_config(GPIO_SPI7_MOSI);
+ lpc54_gpio_config(GPIO_SPI7_MISO);
/* Set up the FLEXCOMM7 function clock */
@@ -944,7 +1958,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
}
else
#endif
-#ifdef CONFIG_LPC54_I2C8_MASTER
+#ifdef CONFIG_LPC54_SPI8_MASTER
if (port == 8)
{
/* Attach 12 MHz clock to FLEXCOMM8 */
@@ -962,14 +1976,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi8_dev;
priv->base = LPC54_FLEXCOMM8_BASE;
- priv->irqid = LPC54_IRQ_FLEXCOMM8;
+ priv->irq = LPC54_IRQ_FLEXCOMM8;
priv->fclock = BOARD_FLEXCOMM8_FCLK;
+ priv->dev.ops = &g_spi8_ops;
/* Configure SPI pins (defined in board.h) */
- lpc54_gpio_config(GPIO_I2C8_SCK);
- lpc54_gpio_config(GPIO_I2C8_MOSI);
- lpc54_gpio_config(GPIO_I2C8_MISO);
+ lpc54_gpio_config(GPIO_SPI8_SCK);
+ lpc54_gpio_config(GPIO_SPI8_MOSI);
+ lpc54_gpio_config(GPIO_SPI8_MISO);
/* Set up the FLEXCOMM8 function clock */
@@ -977,7 +1992,7 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
}
else
#endif
-#ifdef CONFIG_LPC54_I2C9_MASTER
+#ifdef CONFIG_LPC54_SPI9_MASTER
if (port == 9)
{
/* Attach 12 MHz clock to FLEXCOMM9 */
@@ -995,14 +2010,15 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
priv = &g_spi9_dev;
priv->base = LPC54_FLEXCOMM9_BASE;
- priv->irqid = LPC54_IRQ_FLEXCOMM9;
+ priv->irq = LPC54_IRQ_FLEXCOMM9;
priv->fclock = BOARD_FLEXCOMM9_FCLK;
+ priv->dev.ops = &g_spi9_ops;
/* Configure SPI pins (defined in board.h) */
- lpc54_gpio_config(GPIO_I2C9_SCK);
- lpc54_gpio_config(GPIO_I2C9_MOSI);
- lpc54_gpio_config(GPIO_I2C9_MISO);
+ lpc54_gpio_config(GPIO_SPI9_SCK);
+ lpc54_gpio_config(GPIO_SPI9_MOSI);
+ lpc54_gpio_config(GPIO_SPI9_MISO);
/* Set up the FLEXCOMM9 function clock */
@@ -1016,24 +2032,69 @@ FAR struct spi_dev_s *lpc54_spibus_initialize(int port)
leave_critical_section(flags);
- /* Enable the SPI peripheral*/
- /* Configure 8-bit SPI mode and master mode */
-#warning Missing logic
-
/* Set the initial SPI configuration */
priv->frequency = 0;
priv->nbits = 8;
priv->mode = SPIDEV_MODE0;
- priv->dev.ops = &g_spi_ops;
+
+ /* Initialize the SPI semaphore that enforces mutually exclusive access */
+
+ nxsem_init(&priv->exclsem, 0, 1);
+
+ /* Configure master mode in mode 0:
+ *
+ * ENABLE - Disabled for now (0)
+ * MASTER - Master mode (1)
+ * LSBF - MSB first (0)
+ * CPHA/CPOL - Mode 0 (0,0)
+ * LOOP - Disable loopback mode (0)
+ * SPOLn - Active low (0,0,0)
+ */
+
+ regval = lpc54_spi_getreg(priv, LPC54_SPI_CFG_OFFSET);
+ regval &= ~(SPI_CFG_ENABLE | SPI_CFG_LSBF | SPI_CFG_CPHA | SPI_CFG_CPOL |
+ SPI_CFG_LOOP | SPI_CFG_SPOL0 | SPI_CFG_SPOL1 | SPI_CFG_SPOL2 |
+ SPI_CFG_SPOL3);
+ regval |= SPI_CFG_MASTER;
+ lpc54_spi_putreg(priv, LPC54_SPI_CFG_OFFSET, regval);
+
+ /* Enable FIFOs */
+
+ regval = lpc54_spi_getreg(priv, LPC54_SPI_FIFOCFG_OFFSET);
+ regval |= (SPI_FIFOCFG_EMPTYTX | SPI_FIFOCFG_EMPTYRX);
+ lpc54_spi_putreg(priv, LPC54_SPI_FIFOCFG_OFFSET, regval);
+
+ regval |= (SPI_FIFOCFG_ENABLETX | SPI_FIFOCFG_ENABLERX);
+ lpc54_spi_putreg(priv, LPC54_SPI_FIFOCFG_OFFSET, regval);
+
+ /* Set FIFO trigger levels: Empty for Tx FIFO; 1 word for RxFIFO */
+
+ regval = lpc54_spi_getreg(priv, LPC54_SPI_FIFOCFG_OFFSET);
+ regval &= ~(SPI_FIFOTRIG_TXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK);
+ regval |= (SPI_FIFOTRIG_TXLVL_EMPTY | SPI_FIFOTRIG_RXLVL_NOTEMPTY);
+
+ /* Enable generation of interrupts for selected FIFO trigger levels */
+
+ regval |= (SPI_FIFOTRIG_TXLVLENA | SPI_FIFOTRIG_RXLVLENA);
+ lpc54_spi_putreg(priv, LPC54_SPI_FIFOCFG_OFFSET, regval);
+
+ /* Set the delay configuration (not used) */
+
+ regval = (SPI_DLY_PRE_DELAY(0) | SPI_DLY_POST_DELAY(0) | SPI_DLY_FRAME_DELAY(0) |
+ SPI_DLY_TRANSFER_DELAY(0));
+ lpc54_spi_putreg(priv, LPC54_SPI_DLY_OFFSET, regval);
/* Select a default frequency of approx. 400KHz */
lpc54_spi_setfrequency((FAR struct spi_dev_s *)priv, 400000);
- /* Initialize the SPI semaphore that enforces mutually exclusive access */
+ /* Enable the SPI peripheral */
+
+ regval = lpc54_spi_getreg(priv, LPC54_SPI_CFG_OFFSET);
+ regval |= SPI_CFG_ENABLE;
+ lpc54_spi_putreg(priv, LPC54_SPI_CFG_OFFSET, regval);
- nxsem_init(&priv->exclsem, 0, 1);
return &priv->dev;
}
diff --git a/arch/arm/src/lpc54xx/lpc54_spi_master.h b/arch/arm/src/lpc54xx/lpc54_spi_master.h
index 376c3a6e7680796629856439072abc6906d52bbb..9205dd66f45942e36fbe6c340157716739979ec9 100644
--- a/arch/arm/src/lpc54xx/lpc54_spi_master.h
+++ b/arch/arm/src/lpc54xx/lpc54_spi_master.h
@@ -98,7 +98,7 @@ extern "C"
* ...
* 9 - SPI9
*
- * Input Parameter:
+ * Input Parameters:
* port - SPI peripheral number, 0.. 9.
*
* Returned Value:
@@ -109,45 +109,111 @@ extern "C"
FAR struct spi_dev_s *lpc54_spibus_initialize(int port);
/************************************************************************************
- * Name: lpc54_spiselect, lpc54_spistatus, and lpc54_spicmddata
+ * Name: lpc54_spiN_select, lpc54_spiN_status, and lpc54_spiN_cmddata
*
* Description:
* These functions must be provided in your board-specific logic. The
- * lpc54_spiselect function will perform chip selection and the lpc54_spistatus
+ * lpc54_spiN_select function will perform chip selection and the lpc54_spiN_status
* will perform status operations using GPIOs in the way your board is configured.
*
* If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, then
- * lpc54_spicmddata must also be provided. This functions performs cmd/data
+ * lpc54_spiN_cmddata must also be provided. This functions performs cmd/data
* selection operations using GPIOs in the way your board is configured.
*
************************************************************************************/
-void lpc54_spiselect(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
-uint8_t lpc54_spistatus(FAR struct spi_dev_s *dev, uint32_t devid);
+#ifdef CONFIG_LPC54_SPI0_MASTER
+void lpc54_spi0_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi0_status(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
-int lpc54_spicmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+int lpc54_spi0_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
#endif
-/************************************************************************************
- * Name: spi_flush
- *
- * Description:
- * Flush and discard any words left in the RX fifo. This can be called from
- * spiselect after a device is deselected (if you worry about such things).
- *
- * Input Parameters:
- * dev - Device-specific state data
- *
- * Returned Value:
- * None
- *
- ************************************************************************************/
+#ifdef CONFIG_LPC54_SPI1_MASTER
+void lpc54_spi1_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi1_status(FAR struct spi_dev_s *dev, uint32_t devid);
+
+#ifdef CONFIG_SPI_CMDDATA
+int lpc54_spi1_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+#endif
+
+#ifdef CONFIG_LPC54_SPI2_MASTER
+void lpc54_spi2_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi2_status(FAR struct spi_dev_s *dev, uint32_t devid);
-void spi_flush(FAR struct spi_dev_s *dev);
+#ifdef CONFIG_SPI_CMDDATA
+int lpc54_spi2_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+#endif
+
+#ifdef CONFIG_LPC54_SPI3_MASTER
+void lpc54_spi3_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi3_status(FAR struct spi_dev_s *dev, uint32_t devid);
+
+#ifdef CONFIG_SPI_CMDDATA
+int lpc54_spi3_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+#endif
+
+#ifdef CONFIG_LPC54_SPI4_MASTER
+void lpc54_spi4_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi4_status(FAR struct spi_dev_s *dev, uint32_t devid);
+
+#ifdef CONFIG_SPI_CMDDATA
+int lpc54_spi4_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+#endif
+
+#ifdef CONFIG_LPC54_SPI5_MASTER
+void lpc54_spi5_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi5_status(FAR struct spi_dev_s *dev, uint32_t devid);
+
+#ifdef CONFIG_SPI_CMDDATA
+int lpc54_spi5_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+#endif
+
+#ifdef CONFIG_LPC54_SPI6_MASTER
+void lpc54_spi6_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi6_status(FAR struct spi_dev_s *dev, uint32_t devid);
+
+#ifdef CONFIG_SPI_CMDDATA
+int lpc54_spi6_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+#endif
+
+#ifdef CONFIG_LPC54_SPI7_MASTER
+void lpc54_spi7_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi7_status(FAR struct spi_dev_s *dev, uint32_t devid);
+
+#ifdef CONFIG_SPI_CMDDATA
+int lpc54_spi7_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+#endif
+
+#ifdef CONFIG_LPC54_SPI8_MASTER
+void lpc54_spi8_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi8_status(FAR struct spi_dev_s *dev, uint32_t devid);
+
+#ifdef CONFIG_SPI_CMDDATA
+int lpc54_spi8_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+#endif
+
+#ifdef CONFIG_LPC54_SPI9_MASTER
+void lpc54_spi9_select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
+uint8_t lpc54_spi9_status(FAR struct spi_dev_s *dev, uint32_t devid);
+
+#ifdef CONFIG_SPI_CMDDATA
+int lpc54_spi9_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+#endif
/************************************************************************************
- * Name: lpc54_spi/spiregister
+ * Name: lpc54_spiN_register
*
* Description:
* If the board supports a card detect callback to inform the SPI-based MMC/SD
@@ -167,8 +233,37 @@ void spi_flush(FAR struct spi_dev_s *dev);
************************************************************************************/
#ifdef CONFIG_SPI_CALLBACK
-int lpc54_spiregister(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#ifdef CONFIG_LPC54_SPI0_MASTER
+int lpc54_spi0_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#endif
+#ifdef CONFIG_LPC54_SPI1_MASTER
+int lpc54_spi1_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#endif
+#ifdef CONFIG_LPC54_SPI2_MASTER
+int lpc54_spi2_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#endif
+#ifdef CONFIG_LPC54_SPI3_MASTER
+int lpc54_spi3_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#endif
+#ifdef CONFIG_LPC54_SPI4_MASTER
+int lpc54_spi4_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#endif
+#ifdef CONFIG_LPC54_SPI5_MASTER
+int lpc54_spi5_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#endif
+#ifdef CONFIG_LPC54_SPI6_MASTER
+int lpc54_spi6_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#endif
+#ifdef CONFIG_LPC54_SPI7_MASTER
+int lpc54_spi7_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#endif
+#ifdef CONFIG_LPC54_SPI8_MASTER
+int lpc54_spi8_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
+#endif
+#ifdef CONFIG_LPC54_SPI9_MASTER
+int lpc54_spi9_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
#endif
+#endif /* CONFIG_SPI_CALLBACK */
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/lpc54xx/lpc54_wwdt.c b/arch/arm/src/lpc54xx/lpc54_wwdt.c
index a664d2ba99246fd2b6bf40bd1ab3ab31508200e6..c442ee318e888ccd5867b59921f57b6a8eaa4cd0 100644
--- a/arch/arm/src/lpc54xx/lpc54_wwdt.c
+++ b/arch/arm/src/lpc54xx/lpc54_wwdt.c
@@ -207,7 +207,7 @@ static void lpc54_setwarning(uint32_t warning)
* Input Parameters:
* Usual interrupt handler arguments.
*
- * Returned Values:
+ * Returned Value:
* Always returns OK.
*
****************************************************************************/
@@ -255,7 +255,7 @@ static int lpc54_wwdt_interrupt(int irq, FAR void *context)
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -296,7 +296,7 @@ static int lpc54_start(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -330,7 +330,7 @@ static int lpc54_stop(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -362,7 +362,7 @@ static int lpc54_keepalive(FAR struct watchdog_lowerhalf_s *lower)
* driver state structure.
* status - The location to return the watchdog status information.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -420,7 +420,7 @@ static int lpc54_getstatus(FAR struct watchdog_lowerhalf_s *lower,
* "lower-half" driver state structure.
* timeout - The new timeout value in milliseconds.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -495,7 +495,7 @@ static int lpc54_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* function pointer is NULL, then the reset-on-expiration
* behavior is restored,
*
- * Returned Values:
+ * Returned Value:
* The previous watchdog expiration function pointer or NULL is there was
* no previous function pointer, i.e., if the previous behavior was
* reset-on-expiration (NULL is also returned if an error occurs).
@@ -564,7 +564,7 @@ static xcpt_t lpc54_capture(FAR struct watchdog_lowerhalf_s *lower,
* interpretation of this argument depends on the particular
* command.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -621,7 +621,7 @@ static int lpc54_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
* devpath - The full path to the watchdog. This should be of the form
* /dev/watchdog0
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/lpc54xx/lpc54_wwdt.h b/arch/arm/src/lpc54xx/lpc54_wwdt.h
index db0822a48ea87fbaf877e452eeea182056b9cc4f..baffd8c167e1000195e56d08fd9a8b54b7759726 100644
--- a/arch/arm/src/lpc54xx/lpc54_wwdt.h
+++ b/arch/arm/src/lpc54xx/lpc54_wwdt.h
@@ -78,7 +78,7 @@ extern "C"
* devpath - The full path to the watchdog. This should be of the form
* /dev/watchdog0
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/nuc1xx/nuc_gpio.c b/arch/arm/src/nuc1xx/nuc_gpio.c
index 0e2b11d54c14f22cc81b67225f2a8be2491d82aa..e5c86c29347314ac50aff4461e45a6ba7e7c5b02 100644
--- a/arch/arm/src/nuc1xx/nuc_gpio.c
+++ b/arch/arm/src/nuc1xx/nuc_gpio.c
@@ -74,7 +74,7 @@
* function, it must be unconfigured with nuc_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
- * Returns:
+ * Returned Value:
* OK on success
* ERROR on invalid port, or when pin is locked as ALT function.
*
diff --git a/arch/arm/src/nuc1xx/nuc_gpio.h b/arch/arm/src/nuc1xx/nuc_gpio.h
index 1fca1dc0e50933c0ae6f6a1142c67d8f7f6cac5a..9d08dbac1ad9cd506bdca38818363ab8c794fadd 100644
--- a/arch/arm/src/nuc1xx/nuc_gpio.h
+++ b/arch/arm/src/nuc1xx/nuc_gpio.h
@@ -208,7 +208,7 @@ extern "C"
* function, it must be unconfigured with nuc_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
- * Returns:
+ * Returned Value:
* OK on success
* ERROR on invalid port, or when pin is locked as ALT function.
*
diff --git a/arch/arm/src/sam34/Kconfig b/arch/arm/src/sam34/Kconfig
index 862b381418b3b56e1a88cb94f869ad2b4dc8d0a0..692bfd062f20451f4a9c089f3c5c52e8673f156c 100644
--- a/arch/arm/src/sam34/Kconfig
+++ b/arch/arm/src/sam34/Kconfig
@@ -247,6 +247,7 @@ config ARCH_CHIP_SAM4CM
default n
select ARCH_HAVE_MULTICPU
select ARCH_HAVE_TICKLESS
+ select ARCH_GLOBAL_IRQDISABLE
config ARCH_CHIP_SAM4L
bool
diff --git a/arch/arm/src/sam34/Make.defs b/arch/arm/src/sam34/Make.defs
index 9ca94574306d696ca27d16a144a7133241852442..12a35528fb6293f80850d6b91ecb37bab118b7a4 100644
--- a/arch/arm/src/sam34/Make.defs
+++ b/arch/arm/src/sam34/Make.defs
@@ -47,7 +47,7 @@ CMN_UASRCS =
CMN_UCSRCS =
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
-CMN_ASRCS += up_testset.S vfork.S
+CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S
CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c
CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_initialize.c
diff --git a/arch/arm/src/sam34/sam4cm_cpuidlestack.c b/arch/arm/src/sam34/sam4cm_cpuidlestack.c
index 411ebfaad77efb449d82af9a9b3ac502aface7a6..1f3dd7fad8cc85ef6144d55a7d597d90aa5acea1 100644
--- a/arch/arm/src/sam34/sam4cm_cpuidlestack.c
+++ b/arch/arm/src/sam34/sam4cm_cpuidlestack.c
@@ -115,7 +115,7 @@ void up_idle(void)
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
* the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - cpu: CPU index that indicates which CPU the IDLE task is
* being created for.
* - tcb: The TCB of new CPU IDLE task
diff --git a/arch/arm/src/sam34/sam_emac.c b/arch/arm/src/sam34/sam_emac.c
index c45ea9f3838459f4552094cafb4d4255d7e80b0d..88d43258d56be27af665580ed2146a593b18a1ee 100644
--- a/arch/arm/src/sam34/sam_emac.c
+++ b/arch/arm/src/sam34/sam_emac.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/sam34/sam_emac.c
*
- * Copyright (C) 2014-2015, 2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014-2015, 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* This logic derives from the SAM34D3 Ethernet driver.
@@ -408,7 +408,7 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac);
static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac);
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg);
#endif
@@ -2309,86 +2309,90 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
*
****************************************************************************/
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
{
+#ifdef CONFIG_NETDEV_PHY_IOCTL
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
+#endif
int ret;
switch (cmd)
- {
-#ifdef CONFIG_ARCH_PHY_INTERRUPT
- case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
- struct mii_iotcl_notify_s *req = (struct mii_iotcl_notify_s *)((uintptr_t)arg);
-
- ret = phy_notify_subscribe(dev->d_ifname, req->pid, req->signo, req->arg);
- if (ret == OK)
+#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_ARCH_PHY_INTERRUPT
+ case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
- /* Enable PHY link up/down interrupts */
+ struct mii_iotcl_notify_s *req = (struct mii_iotcl_notify_s *)((uintptr_t)arg);
- ret = sam_phyintenable(priv);
+ ret = phy_notify_subscribe(dev->d_ifname, req->pid, req->signo, req->arg);
+ if (ret == OK)
+ {
+ /* Enable PHY link up/down interrupts */
+
+ ret = sam_phyintenable(priv);
+ }
}
- }
- break;
+ break;
#endif
- case SIOCGMIIPHY: /* Get MII PHY address */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- req->phy_id = priv->phyaddr;
- ret = OK;
- }
- break;
+ case SIOCGMIIPHY: /* Get MII PHY address */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ req->phy_id = priv->phyaddr;
+ ret = OK;
+ }
+ break;
- case SIOCGMIIREG: /* Get register from MII PHY */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- uint32_t regval;
+ case SIOCGMIIREG: /* Get register from MII PHY */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ uint32_t regval;
- /* Enable management port */
+ /* Enable management port */
- regval = sam_getreg(priv, SAM_EMAC_NCR);
- sam_putreg(priv, SAM_EMAC_NCR, regval | EMAC_NCR_MPE);
+ regval = sam_getreg(priv, SAM_EMAC_NCR);
+ sam_putreg(priv, SAM_EMAC_NCR, regval | EMAC_NCR_MPE);
- /* Read from the requested register */
+ /* Read from the requested register */
- ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
+ ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
- /* Disable management port (probably) */
+ /* Disable management port (probably) */
- sam_putreg(priv, SAM_EMAC_NCR, regval);
- }
- break;
+ sam_putreg(priv, SAM_EMAC_NCR, regval);
+ }
+ break;
- case SIOCSMIIREG: /* Set register in MII PHY */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- uint32_t regval;
+ case SIOCSMIIREG: /* Set register in MII PHY */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ uint32_t regval;
- /* Enable management port */
+ /* Enable management port */
- regval = sam_getreg(priv, SAM_EMAC_NCR);
- sam_putreg(priv, SAM_EMAC_NCR, regval | EMAC_NCR_MPE);
+ regval = sam_getreg(priv, SAM_EMAC_NCR);
+ sam_putreg(priv, SAM_EMAC_NCR, regval | EMAC_NCR_MPE);
- /* Write to the requested register */
+ /* Write to the requested register */
- ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
+ ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
- /* Disable management port (probably) */
+ /* Disable management port (probably) */
- sam_putreg(priv, SAM_EMAC_NCR, regval);
- }
- break;
+ sam_putreg(priv, SAM_EMAC_NCR, regval);
+ }
+ break;
+#endif /* ifdef CONFIG_NETDEV_PHY_IOCTL */
- default:
- ret = -ENOTTY;
- break;
- }
+ default:
+ ret = -ENOTTY;
+ break;
+ }
return ret;
}
-#endif /* CONFIG_NETDEV_PHY_IOCTL */
+#endif /* CONFIG_NETDEV_IOCTL */
/****************************************************************************
* Function: sam_phydump
@@ -3630,7 +3634,7 @@ void up_netinitialize(void)
priv->dev.d_addmac = sam_addmac; /* Add multicast MAC address */
priv->dev.d_rmmac = sam_rmmac; /* Remove multicast MAC address */
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = sam_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void *)&g_emac; /* Used to recover private state from dev */
diff --git a/arch/arm/src/sam34/sam_hsmci.c b/arch/arm/src/sam34/sam_hsmci.c
index 0ac187982b7e3fe2067df2d0c151ff1f12ccc643..0a1f1c2d325915fa256d816b9a4c16688c808df7 100644
--- a/arch/arm/src/sam34/sam_hsmci.c
+++ b/arch/arm/src/sam34/sam_hsmci.c
@@ -2317,7 +2317,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev,
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay, (wdentry_t)sam_eventtimeout,
1, (uint32_t)priv);
- if (ret != OK)
+ if (ret < 0)
{
mcerr("ERROR: wd_start failed: %d\n", ret);
}
@@ -2670,7 +2670,7 @@ static void sam_callback(void *arg)
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
@@ -2745,7 +2745,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -2792,7 +2792,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is writeprotected.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/sam34/sam_hsmci.h b/arch/arm/src/sam34/sam_hsmci.h
index 3339c2d2958abf25b50c903c1dd0bc8436eb7d5a..78dc02069c47ef6eddfb3051193597fb388ed583 100644
--- a/arch/arm/src/sam34/sam_hsmci.h
+++ b/arch/arm/src/sam34/sam_hsmci.h
@@ -87,7 +87,7 @@ extern "C"
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
@@ -109,7 +109,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno);
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -127,7 +127,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is writeprotected.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/sam34/sam_rtt.c b/arch/arm/src/sam34/sam_rtt.c
index 7978b01bf38467eb798dea642ecf91f37766eb12..1b945e42e8fe12b6158808e5e2d2e42ba56cda98 100644
--- a/arch/arm/src/sam34/sam_rtt.c
+++ b/arch/arm/src/sam34/sam_rtt.c
@@ -270,7 +270,7 @@ static void sam34_putreg(uint32_t val, uint32_t addr)
* Input Parameters:
* Usual interrupt handler arguments.
*
- * Returned Values:
+ * Returned Value:
* Always returns OK.
*
****************************************************************************/
@@ -354,7 +354,7 @@ static int sam34_interrupt(int irq, FAR void *context, FAR void *arg)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -417,7 +417,7 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -456,7 +456,7 @@ static int sam34_stop(FAR struct timer_lowerhalf_s *lower)
* driver state structure.
* status - The location to return the status information.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -507,7 +507,7 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower,
* driver state structure.
* timeout - The new timeout value in milliseconds.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -559,7 +559,7 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower,
* behavior is restored,
* arg - Argument that will be provided in the callback
*
- * Returned Values:
+ * Returned Value:
* The previous timer expiration function pointer or NULL is there was
* no previous function pointer.
*
@@ -599,7 +599,7 @@ static void sam34_setcallback(FAR struct timer_lowerhalf_s *lower,
* interpretation of this argument depends on the particular
* command.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -632,7 +632,7 @@ static int sam34_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd,
* devpath - The full path to the timer. This should be of the form
* /dev/rtt0
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/sam34/sam_rtt.h b/arch/arm/src/sam34/sam_rtt.h
index f300747efb3f5aff624ff55f42156273a86f878c..3a00c17fbdd5ff45ec9a562626d5a7125ea03e14 100644
--- a/arch/arm/src/sam34/sam_rtt.h
+++ b/arch/arm/src/sam34/sam_rtt.h
@@ -80,7 +80,7 @@ extern "C"
* devpath - The full path to the timer. This should be of the form
* /dev/rtt0
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/sam34/sam_spi.c b/arch/arm/src/sam34/sam_spi.c
index 0dc57e7a6c103ed53194789a74ee44d34562d35e..df2be897165826524c517c956226508a8ee8c530 100644
--- a/arch/arm/src/sam34/sam_spi.c
+++ b/arch/arm/src/sam34/sam_spi.c
@@ -79,6 +79,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* Configuration ************************************************************/
/* When SPI DMA is enabled, small DMA transfers will still be performed by
* polling logic. But we need a threshold value to determine what is small.
@@ -193,7 +194,7 @@ struct sam_spics_s
typedef void (*select_t)(uint32_t devid, bool selected);
-/* Chip select register offsetrs */
+/* Chip select register offsets */
/* The overall state of one SPI controller */
@@ -1002,7 +1003,8 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
return spics->actual;
}
- /* Configure SPI to a frequency as close as possible to the requested frequency.
+ /* Configure SPI to a frequency as close as possible to the requested
+ * frequency.
*
* SPCK frequency = SPI_CLK / SCBR, or SCBR = SPI_CLK / frequency
*/
@@ -1110,7 +1112,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
* 3 1 0
*/
- offset = (unsigned int)g_csroffset[spics->cs];
+ offset = (unsigned int)g_csroffset[spics->cs];
regval = spi_getreg(spi, offset);
regval &= ~(SPI_CSR_CPOL | SPI_CSR_NCPHA);
@@ -1184,7 +1186,9 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
spiinfo("csr[offset=%02x]=%08x\n", offset, regval);
- /* Save the selection so the subsequence re-configurations will be faster */
+ /* Save the selection so the subsequence re-configurations will be
+ * faster.
+ */
spics->nbits = nbits;
}
@@ -1233,7 +1237,7 @@ static uint16_t spi_send(struct spi_dev_s *dev, uint16_t wd)
* that performs DMA SPI transfers, but only when a larger block of
* data is being transferred. And (2) another version that does polled
* SPI transfers. When CONFIG_SAM34_SPI_DMA=n the latter is the only
- * version avaialable; when CONFIG_SAM34_SPI_DMA=y, this version is only
+ * version available; when CONFIG_SAM34_SPI_DMA=y, this version is only
* used for short SPI transfers and gets renamed as spi_exchange_nodma).
*
* Input Parameters:
@@ -1268,7 +1272,8 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
uint8_t *rxptr8;
uint8_t *txptr8;
- spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
+ spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n",
+ txbuffer, rxbuffer, nwords);
/* Set up PCS bits */
@@ -1414,7 +1419,8 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
return;
}
- spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
+ spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n",
+ txbuffer, rxbuffer, nwords);
spics = (struct sam_spics_s *)dev;
spi = spi_device(spics);
@@ -1590,7 +1596,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
ret = wd_start(spics->dmadog, DMA_TIMEOUT_TICKS,
(wdentry_t)spi_dmatimeout, 1, (uint32_t)spics);
- if (ret != OK)
+ if (ret < 0)
{
spierr("ERROR: wd_start failed: %d\n", ret);
}
@@ -1711,7 +1717,7 @@ static void spi_recvblock(struct spi_dev_s *dev, void *buffer, size_t nwords)
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* cs - Chip select number (identifying the "logical" SPI port)
*
* Returned Value:
diff --git a/arch/arm/src/sam34/sam_spi.h b/arch/arm/src/sam34/sam_spi.h
index 8cebb2f121b4864484d74c4864a3fec6baca8528..b9cbcce76df2f724b8a458b1617b9e5a5933e956 100644
--- a/arch/arm/src/sam34/sam_spi.h
+++ b/arch/arm/src/sam34/sam_spi.h
@@ -117,7 +117,7 @@ struct spi_dev_s; /* Forward reference */
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* cs - Chip select number (identifying the "logical" SPI port)
*
* Returned Value:
@@ -182,7 +182,7 @@ struct spi_dev_s *sam_spibus_initialize(int port);
* devid - Identifies the (logical) device
* selected - TRUE:Select the device, FALSE:De-select the device
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -204,7 +204,7 @@ void sam_spi1select(uint32_t devid, bool selected);
* dev - SPI device info
* devid - Identifies the (logical) device
*
- * Returned Values:
+ * Returned Value:
* Bit-encoded SPI status (see include/nuttx/spi/spi.h.
*
****************************************************************************/
@@ -235,7 +235,7 @@ uint8_t sam_spi1status(FAR struct spi_dev_s *dev, uint32_t devid);
* dev - SPI device info
* devid - Identifies the (logical) device
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno on failure.
*
****************************************************************************/
diff --git a/arch/arm/src/sam34/sam_tc.c b/arch/arm/src/sam34/sam_tc.c
index 1faab8b159f170cdff8b24429ca733d0c0c16917..3212174623864deadf897dc6ff41b3ee3fa060bf 100644
--- a/arch/arm/src/sam34/sam_tc.c
+++ b/arch/arm/src/sam34/sam_tc.c
@@ -250,7 +250,7 @@ static void sam34_putreg(uint32_t val, uint32_t addr)
* Input Parameters:
* Usual interrupt handler arguments.
*
- * Returned Values:
+ * Returned Value:
* Always returns OK.
*
****************************************************************************/
@@ -309,7 +309,7 @@ static int sam34_interrupt(int irq, FAR void *context, FAR void *arg)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -365,7 +365,7 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -401,7 +401,7 @@ static int sam34_stop(FAR struct timer_lowerhalf_s *lower)
* driver state structure.
* status - The location to return the status information.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -454,7 +454,7 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower,
* driver state structure.
* timeout - The new timeout value in milliseconds.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -507,7 +507,7 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower,
* behavior is restored,
* arg - Argument to be provided with the callback.
*
- * Returned Values:
+ * Returned Value:
* The previous timer expiration function pointer or NULL is there was
* no previous function pointer.
*
@@ -547,7 +547,7 @@ static void sam34_setcallback(FAR struct timer_lowerhalf_s *lower,
* interpretation of this argument depends on the particular
* command.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -580,7 +580,7 @@ static int sam34_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd,
* devpath - The full path to the timer. This should be of the form
* /dev/tc0
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/sam34/sam_tc.h b/arch/arm/src/sam34/sam_tc.h
index df7b3caf29011e8e006039bcd58965744577ae79..3667213d75200d75dbfe810ec84ca9f4395c846c 100644
--- a/arch/arm/src/sam34/sam_tc.h
+++ b/arch/arm/src/sam34/sam_tc.h
@@ -79,7 +79,7 @@ extern "C"
* devpath - The full path to the timer. This should be of the form
* /dev/tc0
* irq - irq associated with the timer
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/sam34/sam_twi.c b/arch/arm/src/sam34/sam_twi.c
index 18b510cbcbd0e7bae0b122ffdbbb487c7464625a..7f733790f706c6e4ac65425a13c167d0b4a451b3 100644
--- a/arch/arm/src/sam34/sam_twi.c
+++ b/arch/arm/src/sam34/sam_twi.c
@@ -386,7 +386,7 @@ static int twi_wait(struct twi_dev_s *priv)
{
/* Start a timeout to avoid hangs */
- wd_start(priv->timeout, TWI_TIMEOUT, twi_timeout, 1, (uint32_t)priv);
+ (void)wd_start(priv->timeout, TWI_TIMEOUT, twi_timeout, 1, (uint32_t)priv);
/* Wait for either the TWI transfer or the timeout to complete */
diff --git a/arch/arm/src/sam34/sam_twi.h b/arch/arm/src/sam34/sam_twi.h
index 87c31b30321b70017756d42cd83ecb15c9ce5b53..06868044b2a4552575af05aff2d16b2277f92d4e 100644
--- a/arch/arm/src/sam34/sam_twi.h
+++ b/arch/arm/src/sam34/sam_twi.h
@@ -57,7 +57,7 @@
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
@@ -73,7 +73,7 @@ FAR struct i2c_master_s *sam_i2cbus_initialize(int port);
* Description:
* De-initialize the selected I2C port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the sam_i2cbus_initialize()
*
* Returned Value:
diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c
index 908716ebb087de813c447d37b24fc7a1e97ca548..c2edada328c773fdba0ebf147fa7a37cb46b8c06 100644
--- a/arch/arm/src/sam34/sam_udp.c
+++ b/arch/arm/src/sam34/sam_udp.c
@@ -2525,7 +2525,7 @@ static void sam_resume(struct sam_usbdev_s *priv)
/****************************************************************************
* Name: sam_ep_reset
*
- * Description
+ * Description:
* Reset and disable one endpoints.
*
****************************************************************************/
@@ -2565,7 +2565,7 @@ static void sam_ep_reset(struct sam_usbdev_s *priv, uint8_t epno)
/****************************************************************************
* Name: sam_epset_reset
*
- * Description
+ * Description:
* Reset and disable a set of endpoints.
*
****************************************************************************/
diff --git a/arch/arm/src/sam34/sam_wdt.c b/arch/arm/src/sam34/sam_wdt.c
index cf88b37fec1e515a2865e2eccbc152c6ded95302..4e902f46b5ffb229825404c23813b8ead5636e2e 100644
--- a/arch/arm/src/sam34/sam_wdt.c
+++ b/arch/arm/src/sam34/sam_wdt.c
@@ -251,7 +251,7 @@ static void sam34_putreg(uint32_t val, uint32_t addr)
* Input Parameters:
* Usual interrupt handler arguments.
*
- * Returned Values:
+ * Returned Value:
* Always returns OK.
*
****************************************************************************/
@@ -294,7 +294,7 @@ static int sam34_interrupt(int irq, FAR void *context, FAR void *arg)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -338,7 +338,7 @@ static int sam34_start(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -369,7 +369,7 @@ static int sam34_stop(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -393,7 +393,7 @@ static int sam34_keepalive(FAR struct watchdog_lowerhalf_s *lower)
* driver state structure.
* status - The location to return the watchdog status information.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -449,7 +449,7 @@ static int sam34_getstatus(FAR struct watchdog_lowerhalf_s *lower,
* driver state structure.
* timeout - The new timeout value in millisecnds.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -516,7 +516,7 @@ static int sam34_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* function pointer is NULL, then the reset-on-expiration
* behavior is restored,
*
- * Returned Values:
+ * Returned Value:
* The previous watchdog expiration function pointer or NULL is there was
* no previous function pointer, i.e., if the previous behavior was
* reset-on-expiration (NULL is also returned if an error occurs).
@@ -589,7 +589,7 @@ static xcpt_t sam34_capture(FAR struct watchdog_lowerhalf_s *lower,
* interpretation of this argument depends on the particular
* command.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -649,7 +649,7 @@ static int sam34_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
* devpath - The full path to the watchdog. This should be of the form
* /dev/watchdog0
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/sam34/sam_wdt.h b/arch/arm/src/sam34/sam_wdt.h
index 77a1fbab40e3dd684031c8ab1e7a459c427cf83c..3330cc01e73349e1171b9ff89451ace27ff59396 100644
--- a/arch/arm/src/sam34/sam_wdt.h
+++ b/arch/arm/src/sam34/sam_wdt.h
@@ -79,7 +79,7 @@ extern "C"
* devpath - The full path to the watchdog. This should be of the form
* /dev/watchdog0
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/sama5/Kconfig b/arch/arm/src/sama5/Kconfig
index ae701198f1460953d4c43092c0c22005bf01e487..35f4efe98c0754dd6828817d980674df12985ba5 100644
--- a/arch/arm/src/sama5/Kconfig
+++ b/arch/arm/src/sama5/Kconfig
@@ -165,7 +165,7 @@ config SAMA5_HAVE_VDEC
bool
default n
-# Summary configuratinos
+# Summary configurations
config SAMA5_FLEXCOM
bool
diff --git a/arch/arm/src/sama5/Make.defs b/arch/arm/src/sama5/Make.defs
index 716f5581d25d17655f8e012cef89f81a459aa451..3c447aae1f0f36a1685d2385308a1f9b30ce4de5 100644
--- a/arch/arm/src/sama5/Make.defs
+++ b/arch/arm/src/sama5/Make.defs
@@ -55,7 +55,7 @@ endif
CMN_ASRCS += arm_vectors.S arm_fpuconfig.S arm_fullcontextrestore.S
CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S arm_vfork.S
-CMN_ASRCS += arm_testset.S
+CMN_ASRCS += arm_testset.S arm_fetchadd.S
CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S
diff --git a/arch/arm/src/sama5/sam_adc.c b/arch/arm/src/sama5/sam_adc.c
index c61f44a3df5aa90c32b715bc81b79d6bce93ce40..d6975391a4610a21b93ec425da3fc22e9e014d64 100644
--- a/arch/arm/src/sama5/sam_adc.c
+++ b/arch/arm/src/sama5/sam_adc.c
@@ -591,7 +591,7 @@ static bool sam_adc_checkreg(struct sam_adc_s *priv, bool wr,
* thread sets ready when it has completed processing the last sample
* data.
*
- * Input Parameters
+ * Input Parameters:
* arg - The ADC private data structure cast to (void *)
*
* Returned Value:
@@ -838,7 +838,7 @@ static int sam_adc_dmasetup(FAR struct sam_adc_s *priv, FAR uint8_t *buffer,
* sam_adc_endconversion will re-enable EOC interrupts when it completes
* processing all pending EOC events.
*
- * Input Parameters
+ * Input Parameters:
* arg - The ADC private data structure cast to (void *)
*
* Returned Value:
diff --git a/arch/arm/src/sama5/sam_boot.c b/arch/arm/src/sama5/sam_boot.c
index 0098100945f27d4a745874326748a9570404825d..609f147608092246371b80d4d23fcb2e4121f08a 100644
--- a/arch/arm/src/sama5/sam_boot.c
+++ b/arch/arm/src/sama5/sam_boot.c
@@ -84,7 +84,7 @@ extern uint32_t _vector_end; /* End+1 of vector block */
/****************************************************************************
* Name: sam_setupmappings
*
- * Description
+ * Description:
* Map all of the initial memory regions defined in g_section_mapping[]
*
****************************************************************************/
@@ -106,7 +106,7 @@ static inline void sam_setupmappings(void)
/****************************************************************************
* Name: sam_remap
*
- * Description
+ * Description:
* Map all of the final memory regions defined in g_operational_mapping[]
*
****************************************************************************/
diff --git a/arch/arm/src/sama5/sam_can.c b/arch/arm/src/sama5/sam_can.c
index 956ae680e8d5b39cbd6d233c78a33142e7d9dc1e..960c2e53467b931234f1b3c4647edafc3a31ea32 100644
--- a/arch/arm/src/sama5/sam_can.c
+++ b/arch/arm/src/sama5/sam_can.c
@@ -579,7 +579,7 @@ static void can_semtake(FAR struct sam_can_s *priv)
* Description:
* Allocate one mailbox
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN peripheral
*
* Returned Value:
@@ -626,7 +626,7 @@ static int can_mballoc(FAR struct sam_can_s *priv)
* Description:
* Free one mailbox
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN peripheral
* mbndx - Index of the mailbox to be freed
*
@@ -670,7 +670,7 @@ static void can_mbfree(FAR struct sam_can_s *priv, int mbndx)
* Description:
* Configure and enable mailbox(es) for reception
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN peripheral
*
* Returned Value:
@@ -1592,7 +1592,7 @@ static void can_interrupt(int irq, void *context, FAR void *arg)
* Tphs1 = Tq * (PHASE1 + 1)
* Tphs2 = Tq * (PHASE2 + 1)
*
- * Input Parameter:
+ * Input Parameters:
* config - A reference to the CAN constant configuration
*
* Returned Value:
@@ -1706,7 +1706,7 @@ static int can_bittiming(struct sam_can_s *priv)
* Description:
* Use the SAMA5 auto-baud feature to correct the initial timing
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN block
*
* Returned Value:
@@ -1776,7 +1776,7 @@ static int can_autobaud(struct sam_can_s *priv)
* Description:
* CAN cell initialization
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN peripheral
*
* Returned Value:
@@ -1889,7 +1889,7 @@ static int can_hwinitialize(struct sam_can_s *priv)
* Description:
* Initialize the selected CAN port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple CAN interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/sama5/sam_can.h b/arch/arm/src/sama5/sam_can.h
index 83a08f756bb59a93b5307cec0627a25dcb5c0928..bff7c1efbf007fd2fcb7d708eef27ac0ddbde513 100644
--- a/arch/arm/src/sama5/sam_can.h
+++ b/arch/arm/src/sama5/sam_can.h
@@ -125,7 +125,7 @@ extern "C"
* Description:
* Initialize the selected CAN port
*
- * Input Parameter:
+ * Input Parameters:
* Port number: 0=CAN0, 1=CAN1
*
* Returned Value:
diff --git a/arch/arm/src/sama5/sam_ehci.c b/arch/arm/src/sama5/sam_ehci.c
index 9b25316272fe95c7569e3b103657b962bf3fc4e3..bd87be9f93b252fa2d575f0db20a3e7f934919d2 100644
--- a/arch/arm/src/sama5/sam_ehci.c
+++ b/arch/arm/src/sama5/sam_ehci.c
@@ -1903,7 +1903,7 @@ static struct sam_qtd_s *sam_qtd_statusphase(uint32_t tokenbits)
*
* Assumption: The caller holds the EHCI exclsem.
*
- * Returned value:
+ * Returned Value:
* Zero (OK) is returned on success; a negated errno value is return on
* any failure.
*
@@ -2183,7 +2183,7 @@ errout_with_qh:
*
* Assumption: The caller holds the EHCI exclsem.
*
- * Returned value:
+ * Returned Value:
* Zero (OK) is returned on success; a negated errno value is return on
* any failure.
*
@@ -2290,7 +2290,7 @@ errout_with_qh:
* complete, but will be re-acquired when before returning. The state of
* EHCI resources could be very different upon return.
*
- * Returned value:
+ * Returned Value:
* On success, this function returns the number of bytes actually transferred.
* For control transfers, this size includes the size of the control request
* plus the size of the data (which could be short); For bulk transfers, this
@@ -2370,7 +2370,7 @@ static ssize_t sam_transfer_wait(struct sam_epinfo_s *epinfo)
* callback - The function to be called when the completes
* arg - An arbitrary argument that will be provided with the callback.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
@@ -2423,7 +2423,7 @@ static inline int sam_ioc_async_setup(struct sam_rhport_s *rhport,
* epinfo - The IN or OUT endpoint descriptor for the device endpoint on
* which the transfer was performed.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
@@ -3265,7 +3265,7 @@ static int sam_uhphs_interrupt(int irq, FAR void *context, FAR void *arg)
* hport - The location to return the hub port descriptor that detected the
* connection related event.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success when a device in connected or
* disconnected. This function will not return until either (1) a device is
* connected or disconnect to/from any hub port or until (2) some failure
@@ -3367,7 +3367,7 @@ static int sam_wait(FAR struct usbhost_connection_s *conn,
* hport - The descriptor of the hub port that has the newly connected
* device.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3659,7 +3659,7 @@ static int sam_enumerate(FAR struct usbhost_connection_s *conn,
* maxpacketsize - The maximum number of bytes that can be sent to or
* received from the endpoint in a single data packet
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3703,7 +3703,7 @@ static int sam_ep0configure(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3786,7 +3786,7 @@ static int sam_epalloc(FAR struct usbhost_driver_s *drvr,
* the class create() method.
* ep - The endpint to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3831,7 +3831,7 @@ static int sam_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
* maxlen - The address of a memory location provided by the caller in which
* to return the maximum size of the allocated buffer memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3876,7 +3876,7 @@ static int sam_alloc(FAR struct usbhost_driver_s *drvr,
* to the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3913,7 +3913,7 @@ static int sam_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer)
* return the allocated buffer memory address.
* buflen - The size of the buffer required.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3952,7 +3952,7 @@ static int sam_ioalloc(FAR struct usbhost_driver_s *drvr, FAR uint8_t **buffer,
* the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3996,7 +3996,7 @@ static int sam_iofree(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer)
* NOTE: On an IN transaction, req and buffer may refer to the same allocated
* memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4097,7 +4097,7 @@ static int sam_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
* (IN endpoint). buffer must have been allocated using DRVR_ALLOC
* buflen - The length of the data to be sent or received.
*
- * Returned Values:
+ * Returned Value:
* On success, a non-negative value is returned that indicates the number
* of bytes successfully transferred. On a failure, a negated errno value is
* returned that indicates the nature of the failure:
@@ -4208,7 +4208,7 @@ errout_with_sem:
* arg - The arbitrary parameter that will be passed to the callback function
* when the transfer completes.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4301,7 +4301,7 @@ errout_with_sem:
* ep - The IN or OUT endpoint descriptor for the device endpoint on which an
* asynchronous transfer should be transferred.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -4490,7 +4490,7 @@ errout_with_sem:
* related event
* connected - True: device connected; false: device disconnected
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -4541,7 +4541,7 @@ static int sam_connect(FAR struct usbhost_driver_s *drvr,
* hport - The port from which the device is being disconnected. Might be a port
* on a hub.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c
index 1648cab5258a357bd14018b7d74257bffd98afa9..3a011a5b7cbcaf10b3c6f655adbd6b35a5950cfd 100644
--- a/arch/arm/src/sama5/sam_emaca.c
+++ b/arch/arm/src/sama5/sam_emaca.c
@@ -4,7 +4,7 @@
* 10/100 Base-T Ethernet driver for the SAMA5D3. Denoted as 'A' to
* distinguish it from the SAMA5D4 EMAC driver.
*
- * Copyright (C) 2013-2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* References:
@@ -413,7 +413,7 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac);
static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac);
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg);
#endif
@@ -2345,86 +2345,90 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
*
****************************************************************************/
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
{
+#ifdef CONFIG_NETDEV_PHY_IOCTL
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
+#endif
int ret;
switch (cmd)
- {
-#ifdef CONFIG_ARCH_PHY_INTERRUPT
- case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
- struct mii_iotcl_notify_s *req = (struct mii_iotcl_notify_s *)((uintptr_t)arg);
-
- ret = phy_notify_subscribe(dev->d_ifname, req->pid, req->signo, req->arg);
- if (ret == OK)
+#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_ARCH_PHY_INTERRUPT
+ case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
- /* Enable PHY link up/down interrupts */
+ struct mii_iotcl_notify_s *req = (struct mii_iotcl_notify_s *)((uintptr_t)arg);
- ret = sam_phyintenable(priv);
+ ret = phy_notify_subscribe(dev->d_ifname, req->pid, req->signo, req->arg);
+ if (ret == OK)
+ {
+ /* Enable PHY link up/down interrupts */
+
+ ret = sam_phyintenable(priv);
+ }
}
- }
- break;
+ break;
#endif
- case SIOCGMIIPHY: /* Get MII PHY address */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- req->phy_id = priv->phyaddr;
- ret = OK;
- }
- break;
+ case SIOCGMIIPHY: /* Get MII PHY address */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ req->phy_id = priv->phyaddr;
+ ret = OK;
+ }
+ break;
- case SIOCGMIIREG: /* Get register from MII PHY */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- uint32_t regval;
+ case SIOCGMIIREG: /* Get register from MII PHY */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ uint32_t regval;
- /* Enable management port */
+ /* Enable management port */
- regval = sam_getreg(priv, SAM_EMAC_NCR);
- sam_putreg(priv, SAM_EMAC_NCR, regval | EMAC_NCR_MPE);
+ regval = sam_getreg(priv, SAM_EMAC_NCR);
+ sam_putreg(priv, SAM_EMAC_NCR, regval | EMAC_NCR_MPE);
- /* Read from the requested register */
+ /* Read from the requested register */
- ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
+ ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
- /* Disable management port (probably) */
+ /* Disable management port (probably) */
- sam_putreg(priv, SAM_EMAC_NCR, regval);
- }
- break;
+ sam_putreg(priv, SAM_EMAC_NCR, regval);
+ }
+ break;
- case SIOCSMIIREG: /* Set register in MII PHY */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- uint32_t regval;
+ case SIOCSMIIREG: /* Set register in MII PHY */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ uint32_t regval;
- /* Enable management port */
+ /* Enable management port */
- regval = sam_getreg(priv, SAM_EMAC_NCR);
- sam_putreg(priv, SAM_EMAC_NCR, regval | EMAC_NCR_MPE);
+ regval = sam_getreg(priv, SAM_EMAC_NCR);
+ sam_putreg(priv, SAM_EMAC_NCR, regval | EMAC_NCR_MPE);
- /* Write to the requested register */
+ /* Write to the requested register */
- ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
+ ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
- /* Disable management port (probably) */
+ /* Disable management port (probably) */
- sam_putreg(priv, SAM_EMAC_NCR, regval);
- }
- break;
+ sam_putreg(priv, SAM_EMAC_NCR, regval);
+ }
+ break;
+#endif /* CONFIG_NETDEV_PHY_IOCTL */
- default:
- ret = -ENOTTY;
- break;
- }
+ default:
+ ret = -ENOTTY;
+ break;
+ }
return ret;
}
-#endif /* CONFIG_NETDEV_PHY_IOCTL */
+#endif /* CONFIG_NETDEV_IOCTL */
/****************************************************************************
* Function: sam_phydump
@@ -3672,7 +3676,7 @@ int sam_emac_initialize(void)
priv->dev.d_addmac = sam_addmac; /* Add multicast MAC address */
priv->dev.d_rmmac = sam_rmmac; /* Remove multicast MAC address */
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = sam_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void *)&g_emac; /* Used to recover private state from dev */
diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c
index c9fb251acaceb37297ee9a454b8359d8968e8ac8..9f6f366e245039e5f56d0eca5a4aaa56c6bb4186 100644
--- a/arch/arm/src/sama5/sam_emacb.c
+++ b/arch/arm/src/sama5/sam_emacb.c
@@ -507,7 +507,7 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac);
static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac);
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg);
#endif
@@ -2715,79 +2715,83 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
#ifdef CONFIG_NETDEV_PHY_IOCTL
static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
{
+#ifdef CONFIG_NETDEV_PHY_IOCTL
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
+#endif
int ret;
switch (cmd)
- {
-#ifdef CONFIG_ARCH_PHY_INTERRUPT
- case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
- struct mii_iotcl_notify_s *req = (struct mii_iotcl_notify_s *)((uintptr_t)arg);
+#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_ARCH_PHY_INTERRUPT
+ case SIOCMIINOTIFY: /* Set up for PHY event notifications */
+ {
+ struct mii_iotcl_notify_s *req = (struct mii_iotcl_notify_s *)((uintptr_t)arg);
- ret = phy_notify_subscribe(dev->d_ifname, req->pid, req->signo, req->arg);
- if (ret == OK)
- {
- /* Enable PHY link up/down interrupts */
+ ret = phy_notify_subscribe(dev->d_ifname, req->pid, req->signo, req->arg);
+ if (ret == OK)
+ {
+ /* Enable PHY link up/down interrupts */
- ret = sam_phyintenable(priv);
+ ret = sam_phyintenable(priv);
+ }
}
- }
- break;
+ break;
#endif
- case SIOCGMIIPHY: /* Get MII PHY address */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- req->phy_id = priv->phyaddr;
- ret = OK;
- }
- break;
+ case SIOCGMIIPHY: /* Get MII PHY address */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ req->phy_id = priv->phyaddr;
+ ret = OK;
+ }
+ break;
- case SIOCGMIIREG: /* Get register from MII PHY */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- uint32_t regval;
+ case SIOCGMIIREG: /* Get register from MII PHY */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ uint32_t regval;
- /* Enable management port */
+ /* Enable management port */
- regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
- sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval | EMAC_NCR_MPE);
+ regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
+ sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval | EMAC_NCR_MPE);
- /* Read from the requested register */
+ /* Read from the requested register */
- ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
+ ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
- /* Disable management port (probably) */
+ /* Disable management port (probably) */
- sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
- }
- break;
+ sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
+ }
+ break;
- case SIOCSMIIREG: /* Set register in MII PHY */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- uint32_t regval;
+ case SIOCSMIIREG: /* Set register in MII PHY */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ uint32_t regval;
- /* Enable management port */
+ /* Enable management port */
- regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
- sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval | EMAC_NCR_MPE);
+ regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
+ sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval | EMAC_NCR_MPE);
- /* Write to the requested register */
+ /* Write to the requested register */
- ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
+ ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
- /* Disable management port (probably) */
+ /* Disable management port (probably) */
- sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
- }
- break;
+ sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
+ }
+ break;
+#endif /* CONFIG_NETDEV_PHY_IOCTL */
- default:
- ret = -ENOTTY;
- break;
- }
+ default:
+ ret = -ENOTTY;
+ break;
+ }
return ret;
}
@@ -4357,9 +4361,9 @@ int sam_emac_initialize(int intf)
priv->dev.d_addmac = sam_addmac; /* Add multicast MAC address */
priv->dev.d_rmmac = sam_rmmac; /* Remove multicast MAC address */
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = sam_ioctl; /* Support PHY ioctl() calls */
-#ifdef CONFIG_ARCH_PHY_INTERRUPT
+#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
priv->phytype = phytype; /* Type of PHY on port */
#endif
#endif
diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c
index d90996219062227d52f86da70a3a9a129b0227d8..d70a40c5a3376096b0f186e43ae25d35f2d7b3b1 100644
--- a/arch/arm/src/sama5/sam_gmac.c
+++ b/arch/arm/src/sama5/sam_gmac.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/sama5/sam_gmac.c
*
- * Copyright (C) 2013-2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* References:
@@ -338,7 +338,7 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac);
static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac);
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg);
#endif
@@ -2300,82 +2300,86 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
*
****************************************************************************/
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
{
+#ifdef CONFIG_NETDEV_PHY_IOCTL
struct sam_gmac_s *priv = (struct sam_gmac_s *)dev->d_private;
+#endif
int ret;
switch (cmd)
- {
-#ifdef CONFIG_ARCH_PHY_INTERRUPT
- case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
- struct mii_iotcl_notify_s *req = (struct mii_iotcl_notify_s *)((uintptr_t)arg);
-
- ret = phy_notify_subscribe(dev->d_ifname, req->pid, req->signo, req->arg);
- if (ret == OK)
+#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_ARCH_PHY_INTERRUPT
+ case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
- /* Enable PHY link up/down interrupts */
+ struct mii_iotcl_notify_s *req = (struct mii_iotcl_notify_s *)((uintptr_t)arg);
- ret = sam_phyintenable(priv);
+ ret = phy_notify_subscribe(dev->d_ifname, req->pid, req->signo, req->arg);
+ if (ret == OK)
+ {
+ /* Enable PHY link up/down interrupts */
+
+ ret = sam_phyintenable(priv);
+ }
}
- }
- break;
+ break;
#endif
- case SIOCGMIIPHY: /* Get MII PHY address */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- req->phy_id = priv->phyaddr;
- ret = OK;
- }
- break;
+ case SIOCGMIIPHY: /* Get MII PHY address */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ req->phy_id = priv->phyaddr;
+ ret = OK;
+ }
+ break;
- case SIOCGMIIREG: /* Get register from MII PHY */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ case SIOCGMIIREG: /* Get register from MII PHY */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- /* Enable the management port */
+ /* Enable the management port */
- sam_enablemdio(priv);
+ sam_enablemdio(priv);
- /* Read from the requested register */
+ /* Read from the requested register */
- ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
+ ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
- /* Disable the management port */
+ /* Disable the management port */
- sam_disablemdio(priv);
- }
- break;
+ sam_disablemdio(priv);
+ }
+ break;
- case SIOCSMIIREG: /* Set register in MII PHY */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ case SIOCSMIIREG: /* Set register in MII PHY */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- /* Enable the management port */
+ /* Enable the management port */
- sam_enablemdio(priv);
+ sam_enablemdio(priv);
- /* Write to the requested register */
+ /* Write to the requested register */
- ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
+ ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
- /* Disable the management port */
+ /* Disable the management port */
- sam_disablemdio(priv);
- }
- break;
+ sam_disablemdio(priv);
+ }
+ break;
+#endif /* CONFIG_NETDEV_PHY_IOCTL */
- default:
- ret = -ENOTTY;
- break;
- }
+ default:
+ ret = -ENOTTY;
+ break;
+ }
return ret;
}
-#endif /* CONFIG_NETDEV_PHY_IOCTL */
+#endif /* CONFIG_NETDEV_IOCTL */
/****************************************************************************
* Function: sam_phydump
@@ -3744,12 +3748,12 @@ int sam_gmac_initialize(void)
priv->dev.d_addmac = sam_addmac; /* Add multicast MAC address */
priv->dev.d_rmmac = sam_rmmac; /* Remove multicast MAC address */
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = sam_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void *)&g_gmac; /* Used to recover private state from dev */
- /* Create a watchdog for timing polling for and timing of transmisstions */
+ /* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create();
if (!priv->txpoll)
diff --git a/arch/arm/src/sama5/sam_hsmci.c b/arch/arm/src/sama5/sam_hsmci.c
index b5093d36b041f027a241cd89121e3f7f837c0a5a..3b8e48610e4e4e9738a2b4a6c5195eaae5ff0c5c 100644
--- a/arch/arm/src/sama5/sam_hsmci.c
+++ b/arch/arm/src/sama5/sam_hsmci.c
@@ -2745,7 +2745,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev,
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay, (wdentry_t)sam_eventtimeout,
1, (uint32_t)priv);
- if (ret != OK)
+ if (ret < 0)
{
lcderr("ERROR: wd_start failed: %d\n", ret);
}
@@ -3160,7 +3160,7 @@ static void sam_callback(void *arg)
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
@@ -3353,7 +3353,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
@@ -3406,7 +3406,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is write protected.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/sama5/sam_hsmci.h b/arch/arm/src/sama5/sam_hsmci.h
index c28bf89594f6c3894099cb752c7f25ee3946dde1..a3257e7d588807d65dfbcb46796cfaf4a73a137e 100644
--- a/arch/arm/src/sama5/sam_hsmci.h
+++ b/arch/arm/src/sama5/sam_hsmci.h
@@ -87,7 +87,7 @@ extern "C"
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
@@ -118,7 +118,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno);
* bootloader that brought us into SDRAM and it is that bootloader that
* has configured the clocking.
*
- * Input parameters:
+ * Input Parameters:
* target - The target SD frequency
*
* Returned Value:
@@ -143,7 +143,7 @@ uint32_t sam_hsmci_clkdiv(uint32_t target);
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -161,7 +161,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is writeprotected.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/sama5/sam_hsmci_clkdiv.c b/arch/arm/src/sama5/sam_hsmci_clkdiv.c
index 4ddba13e82b8da3b4514869a8336dddfea447c21..4a56bed140fb3d012a59b12adba992d3dbe821e7 100644
--- a/arch/arm/src/sama5/sam_hsmci_clkdiv.c
+++ b/arch/arm/src/sama5/sam_hsmci_clkdiv.c
@@ -97,7 +97,7 @@
* bootloader that brought us into SDRAM and it is that bootloader that
* has configured the clocking.
*
- * Input parameters:
+ * Input Parameters:
* target - The target SD frequency
*
* Returned Value:
diff --git a/arch/arm/src/sama5/sam_irq.c b/arch/arm/src/sama5/sam_irq.c
index fd4dfd8c5cc246f7e28df209f7212b9c13b05ae7..fbdc1eda5c564d4030c24c1d9f0e0d930a91e13a 100644
--- a/arch/arm/src/sama5/sam_irq.c
+++ b/arch/arm/src/sama5/sam_irq.c
@@ -261,7 +261,7 @@ static uint32_t *sam_fiqhandler(int irq, uint32_t *regs)
* Description:
* Return true if the peripheral secure.
*
- * Input Parameter:
+ * Input Parameters:
* PID = IRQ number
*
****************************************************************************/
@@ -576,7 +576,7 @@ void up_irqinitialize(void)
* the irq number of the interrupt and then to call arm_doirq to dispatch
* the interrupt.
*
- * Input parameters:
+ * Input Parameters:
* regs - A pointer to the register save area on the stack.
*
****************************************************************************/
diff --git a/arch/arm/src/sama5/sam_lcd.c b/arch/arm/src/sama5/sam_lcd.c
index 4e27e1ef2ab5bcf67a244c2faa1ad8ccbe58d87e..67f1ac0628de87f64c75fb0120c3b1f1d6dbbb02 100644
--- a/arch/arm/src/sama5/sam_lcd.c
+++ b/arch/arm/src/sama5/sam_lcd.c
@@ -2901,7 +2901,7 @@ static void sam_show_hcr(void)
* Description:
* Initialize the framebuffer video hardware associated with the display.
*
- * Input parameters:
+ * Input Parameters:
* display - In the case of hardware with multiple displays, this
* specifies the display. Normally this is zero.
*
@@ -3001,7 +3001,7 @@ int up_fbinitialize(int display)
* Return a a reference to the framebuffer object for the specified video
* plane of the specified plane. Many OSDs support multiple planes of video.
*
- * Input parameters:
+ * Input Parameters:
* display - In the case of hardware with multiple displays, this
* specifies the display. Normally this is zero.
* vplane - Identifies the plane being queried.
diff --git a/arch/arm/src/sama5/sam_nand.c b/arch/arm/src/sama5/sam_nand.c
index ae0c22936d4c7dde0cfb5757c53305809f0da3b1..a0fb369ce1f4b1719cfd736c56da7b4fb2abe3b4 100644
--- a/arch/arm/src/sama5/sam_nand.c
+++ b/arch/arm/src/sama5/sam_nand.c
@@ -353,10 +353,10 @@ void nand_unlock(void)
* Waiting for the completion of a page program, erase and random read
* completion.
*
- * Input parameters:
+ * Input Parameters:
* priv Pointer to a sam_nandcs_s instance.
*
- * Returned value.
+ * Returned Value:
* None
*
****************************************************************************/
@@ -376,13 +376,13 @@ static void nand_wait_ready(struct sam_nandcs_s *priv)
* Description:
* Use the HOST NAND FLASH controller to send a command to the NFC.
*
- * Input parameters:
+ * Input Parameters:
* priv - Lower-half, private NAND FLASH device state
* cmd - command to send
* acycle - address cycle when command access id decoded
* cycle0 - address at first cycle
*
- * Returned value.
+ * Returned Value:
* None
*
****************************************************************************/
@@ -414,10 +414,10 @@ static void nand_nfc_cmdsend(struct sam_nandcs_s *priv, uint32_t cmd,
* Description:
* Check if a program or erase operation completed successfully
*
- * Input parameters:
+ * Input Parameters:
* priv - Lower-half, private NAND FLASH device state
*
- * Returned value.
+ * Returned Value:
* OK on success, a negated errnor value on failure
*
****************************************************************************/
@@ -451,7 +451,7 @@ static int nand_operation_complete(struct sam_nandcs_s *priv)
* address cycles. The resulting values are stored in the provided
* variables if they are not null.
*
- * Input parameters:
+ * Input Parameters:
* priv - Lower-half, private NAND FLASH device state
* coladdr - Column address to translate.
* rowaddr - Row address to translate.
@@ -459,7 +459,7 @@ static int nand_operation_complete(struct sam_nandcs_s *priv)
* acycle1234 - Four address cycles.
* rowonly - True:Only ROW address is used.
*
- * Returned value.
+ * Returned Value:
* Number of address cycles converted.
*
****************************************************************************/
@@ -565,10 +565,10 @@ static int nand_translate_address(struct sam_nandcs_s *priv,
* Description:
* Map the number of address cycles the bit setting for the NFC command
*
- * Input parameters:
+ * Input Parameters:
* ncycles - Number of address cycles
*
- * Returned value.
+ * Returned Value:
* NFC command value
*
****************************************************************************/
@@ -602,7 +602,7 @@ static uint32_t nand_get_acycle(int ncycles)
* Description:
* Sends NAND CLE/ALE command.
*
- * Input parameters:
+ * Input Parameters:
* priv - Pointer to a sam_nandcs_s instance.
* mode - SMC ALE CLE mode parameter.
* cmd1 - First command to be sent.
@@ -610,7 +610,7 @@ static uint32_t nand_get_acycle(int ncycles)
* coladdr - Column address.
* rowaddr - Row address.
*
- * Returned value.
+ * Returned Value:
* None
*
****************************************************************************/
@@ -670,10 +670,10 @@ static void nand_nfc_cleale(struct sam_nandcs_s *priv, uint8_t mode,
* Description:
* Wait for NFC command done
*
- * Input parameters:
+ * Input Parameters:
* priv - CS state structure instance
*
- * Returned value.
+ * Returned Value:
* None
*
****************************************************************************/
@@ -716,10 +716,10 @@ static void nand_wait_cmddone(struct sam_nandcs_s *priv)
* Description:
* Setup to wait for CMDDONE event
*
- * Input parameters:
+ * Input Parameters:
* priv - CS state structure instance
*
- * Returned value.
+ * Returned Value:
* None
*
****************************************************************************/
@@ -758,10 +758,10 @@ static void nand_setup_cmddone(struct sam_nandcs_s *priv)
* Description:
* Wait for a transfer to complete
*
- * Input parameters:
+ * Input Parameters:
* priv - CS state structure instance
*
- * Returned value.
+ * Returned Value:
* None
*
****************************************************************************/
@@ -804,10 +804,10 @@ static void nand_wait_xfrdone(struct sam_nandcs_s *priv)
* Description:
* Setup to wait for XFDONE event
*
- * Input parameters:
+ * Input Parameters:
* priv - CS state structure instance
*
- * Returned value.
+ * Returned Value:
* None
*
****************************************************************************/
@@ -846,10 +846,10 @@ static void nand_setup_xfrdone(struct sam_nandcs_s *priv)
* Description:
* Wait for read/busy edge detection
*
- * Input parameters:
+ * Input Parameters:
* priv - CS state structure instance
*
- * Returned value.
+ * Returned Value:
* None
*
****************************************************************************/
@@ -892,10 +892,10 @@ static void nand_wait_rbedge(struct sam_nandcs_s *priv)
* Description:
* Setup to wait for RBEDGE0 event
*
- * Input parameters:
+ * Input Parameters:
* priv - CS state structure instance
*
- * Returned value.
+ * Returned Value:
* None
*
****************************************************************************/
@@ -934,10 +934,10 @@ static void nand_setup_rbedge(struct sam_nandcs_s *priv)
* Description:
* Wait for NFC not busy
*
- * Input parameters:
+ * Input Parameters:
* priv - CS state structure instance
*
- * Returned value.
+ * Returned Value:
* None
*
****************************************************************************/
@@ -965,10 +965,10 @@ static void nand_wait_nfcbusy(struct sam_nandcs_s *priv)
* This latching capability function is needed to prevent loss of pending
* status when sampling the HSMC_SR register.
*
- * Input parameters:
+ * Input Parameters:
* None
*
- * Returned value.
+ * Returned Value:
* Current HSMC_SR register value;
*
****************************************************************************/
@@ -1041,10 +1041,10 @@ static uint32_t nand_nfc_poll(void)
* Description:
* HSMC interrupt handler
*
- * Input parameters:
+ * Input Parameters:
* Standard interrupt arguments
*
- * Returned value.
+ * Returned Value:
* Always returns OK
*
****************************************************************************/
@@ -1203,10 +1203,10 @@ static void nand_dma_sampledone(struct sam_nandcs_s *priv, int result)
* Description:
* Wait for the completion of a DMA transfer
*
- * Input parameters:
+ * Input Parameters:
* Wait for read/busy edge detection
*
- * Returned value.
+ * Returned Value:
* The result of the DMA. OK on success; a negated ernno value on failure.
*
****************************************************************************/
@@ -1266,7 +1266,7 @@ static void nand_dmacallback(DMA_HANDLE handle, void *arg, int result)
* nbytes - The number of bytes to transfer
* dmaflags - Describes the DMA configuration
*
- * Returned Value
+ * Returned Value:
* OK on success; a negated errno value on failure.
*
****************************************************************************/
@@ -1355,7 +1355,7 @@ static int nand_dma_read(struct sam_nandcs_s *priv,
* nbytes - The number of bytes to transfer
* dmaflags - Describes the DMA configuration
*
- * Returned Value
+ * Returned Value:
* OK on success; a negated errno value on failure.
*
****************************************************************************/
@@ -1440,7 +1440,7 @@ static int nand_dma_write(struct sam_nandcs_s *priv,
* offset - If reading from NFC SRAM, this is the offset into
* the SRAM.
*
- * Returned Value
+ * Returned Value:
* OK on success; a negated errno value on failure.
*
****************************************************************************/
@@ -1506,7 +1506,7 @@ static int nand_nfcsram_read(struct sam_nandcs_s *priv, uint8_t *buffer,
* nfcsram - True: Use NFC Host SRAM
* buffer - Buffer that provides the data for the write
*
- * Returned Value
+ * Returned Value:
* OK on success; a negated errno value on failure.
*
****************************************************************************/
@@ -1590,13 +1590,13 @@ static int nand_read(struct sam_nandcs_s *priv, uint8_t *buffer,
* Description:
* Reads the data area of a page of a NAND FLASH into the provided buffer.
*
- * Input parameters:
+ * Input Parameters:
* priv - Lower-half, raw NAND FLASH interface
* block - Number of the block where the page to read resides.
* page - Number of the page to read inside the given block.
* data - Buffer where the data area will be stored.
*
- * Returned value.
+ * Returned Value:
* OK is returned in succes; a negated errno value is returned on failure.
*
****************************************************************************/
@@ -1743,7 +1743,7 @@ static int nand_read_pmecc(struct sam_nandcs_s *priv, off_t block,
* buffer - Buffer that provides the data for the write
* offset - Data offset in bytes
*
- * Returned Value
+ * Returned Value:
* OK on success; a negated errno value on failure.
*
****************************************************************************/
@@ -1806,7 +1806,7 @@ static int nand_nfcsram_write(struct sam_nandcs_s *priv, uint8_t *buffer,
* buffer - Buffer that provides the data for the write
* offset - Data offset in bytes
*
- * Returned Value
+ * Returned Value:
* OK on success; a negated errno value on failure.
*
****************************************************************************/
@@ -1891,14 +1891,14 @@ static int nand_write(struct sam_nandcs_s *priv, uint8_t *buffer,
* provided buffers. The raw NAND contents are returned with no ECC
* corrections.
*
- * Input parameters:
+ * Input Parameters:
* priv - Lower-half, private NAND FLASH device state
* block - Number of the block where the page to read resides.
* page - Number of the page to read inside the given block.
* data - Buffer where the data area will be stored.
* spare - Buffer where the spare area will be stored.
*
- * Returned value.
+ * Returned Value:
* OK is returned in succes; a negated errno value is returned on failure.
*
****************************************************************************/
@@ -2007,13 +2007,13 @@ static int nand_readpage_noecc(struct sam_nandcs_s *priv, off_t block,
* Reads the data and/or the spare areas of a page of a NAND FLASH into the
* provided buffers. PMECC is used
*
- * Input parameters:
+ * Input Parameters:
* priv - Lower-half, private NAND FLASH device state
* block - Number of the block where the page to read resides.
* page - Number of the page to read inside the given block.
* data - Buffer where the data area will be stored.
*
- * Returned value.
+ * Returned Value:
* OK is returned in succes; a negated errno value is returned on failure.
*
****************************************************************************/
@@ -2127,14 +2127,14 @@ errout:
* Writes the data and/or the spare area of a page on a NAND FLASH chip.
* No ECC calculations are performed.
*
- * Input parameters:
+ * Input Parameters:
* priv - Lower-half, private NAND FLASH device state
* block - Number of the block where the page to write resides.
* page - Number of the page to write inside the given block.
* data - Buffer containing the data to be writting
* spare - Buffer conatining the spare data to be written.
*
- * Returned value.
+ * Returned Value:
* OK is returned in succes; a negated errno value is returned on failure.
*
****************************************************************************/
@@ -2281,13 +2281,13 @@ static int nand_writepage_noecc(struct sam_nandcs_s *priv, off_t block,
* performed. The redundancy is appended to the page and written in the
* spare area.
*
- * Input parameters:
+ * Input Parameters:
* priv - Lower-half, private NAND FLASH device state
* block - Number of the block where the page to write resides.
* page - Number of the page to write inside the given block.
* data - Buffer containing the data to be writting
*
- * Returned value.
+ * Returned Value:
* OK is returned in succes; a negated errno value is returned on failure.
*
****************************************************************************/
@@ -2495,11 +2495,11 @@ errout:
* Description:
* Erases the specified block of the device.
*
- * Input parameters:
+ * Input Parameters:
* raw - Lower-half, raw NAND FLASH interface
* block - Number of the physical block to erase.
*
- * Returned value.
+ * Returned Value:
* OK is returned in succes; a negated errno value is returned on failure.
*
****************************************************************************/
@@ -2575,14 +2575,14 @@ static int nand_eraseblock(struct nand_raw_s *raw, off_t block)
* Reads the data and/or the spare areas of a page of a NAND FLASH into the
* provided buffers. This is a raw read of the flash contents.
*
- * Input parameters:
+ * Input Parameters:
* raw - Lower-half, raw NAND FLASH interface
* block - Number of the block where the page to read resides.
* page - Number of the page to read inside the given block.
* data - Buffer where the data area will be stored.
* spare - Buffer where the spare area will be stored.
*
- * Returned value.
+ * Returned Value:
* OK is returned in succes; a negated errno value is returned on failure.
*
****************************************************************************/
@@ -2612,14 +2612,14 @@ static int nand_rawread(struct nand_raw_s *raw, off_t block,
* Writes the data and/or the spare area of a page on a NAND FLASH chip.
* This is a raw write of the flash contents.
*
- * Input parameters:
+ * Input Parameters:
* raw - Lower-half, raw NAND FLASH interface
* block - Number of the block where the page to write resides.
* page - Number of the page to write inside the given block.
* data - Buffer containing the data to be writting
* spare - Buffer containing the spare data to be written.
*
- * Returned value.
+ * Returned Value:
* OK is returned in succes; a negated errno value is returned on failure.
*
****************************************************************************/
@@ -2651,14 +2651,14 @@ static int nand_rawwrite(struct nand_raw_s *raw, off_t block,
* provided buffers. Hardware ECC checking will be performed if so
* configured.
*
- * Input parameters:
+ * Input Parameters:
* raw - Lower-half, raw NAND FLASH interface
* block - Number of the block where the page to read resides.
* page - Number of the page to read inside the given block.
* data - Buffer where the data area will be stored.
* spare - Buffer where the spare area will be stored.
*
- * Returned value.
+ * Returned Value:
* OK is returned in succes; a negated errno value is returned on failure.
*
****************************************************************************/
@@ -2713,14 +2713,14 @@ static int nand_readpage(struct nand_raw_s *raw, off_t block,
* Writes the data and/or the spare area of a page on a NAND FLASH chip.
* Hardware ECC checking will be performed if so configured.
*
- * Input parameters:
+ * Input Parameters:
* raw - Lower-half, raw NAND FLASH interface
* block - Number of the block where the page to write resides.
* page - Number of the page to write inside the given block.
* data - Buffer containing the data to be writting
* spare - Buffer conatining the spare data to be written.
*
- * Returned value.
+ * Returned Value:
* OK is returned in succes; a negated errno value is returned on failure.
*
****************************************************************************/
@@ -2775,10 +2775,10 @@ static int nand_writepage(struct nand_raw_s *raw, off_t block,
* Description:
* Resets a NAND FLASH device
*
- * Input parameters:
+ * Input Parameters:
* priv - Lower-half, private NAND FLASH device state
*
- * Returned value.
+ * Returned Value:
* None
*
****************************************************************************/
@@ -2803,11 +2803,11 @@ static void nand_reset(struct sam_nandcs_s *priv)
* performed here. Those necessary NAND features are provided by common,
* higher level NAND MTD layers found in drivers/mtd.
*
- * Input parameters:
+ * Input Parameters:
* cs - Chip select number (in the event that multiple NAND devices
* are connected on-board).
*
- * Returned value.
+ * Returned Value:
* On success a non-NULL pointer to an MTD device structure is returned;
* NULL is returned on a failure.
*
diff --git a/arch/arm/src/sama5/sam_nand.h b/arch/arm/src/sama5/sam_nand.h
index 808b719aa52d3a94462fb81a64b8a56afec7e64f..69c6b729e9ed336d00d25ce2c58d6054b3712cef 100644
--- a/arch/arm/src/sama5/sam_nand.h
+++ b/arch/arm/src/sama5/sam_nand.h
@@ -397,11 +397,11 @@ EXTERN struct sam_nand_s g_nand;
* performed here. Those necessary NAND features are provided by common,
* higher level NAND MTD layers found in drivers/mtd.
*
- * Input parameters:
+ * Input Parameters:
* cs - Chip select number (in the event that multiple NAND devices
* are connected on-board).
*
- * Returned value.
+ * Returned Value:
* On success a non-NULL pointer to an MTD device structure is returned;
* NULL is returned on a failure.
*
@@ -428,7 +428,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs);
* cs - Chip select number (in the event that multiple NAND devices
* are connected on-board).
*
- * Returned Values:
+ * Returned Value:
* OK if the HSMC was successfully configured for this CS. A negated
* errno value is returned on a failure. This would fail with -ENODEV,
* for example, if the board does not support NAND FLASH on the requested
@@ -449,7 +449,7 @@ int board_nandflash_config(int cs);
* cs - Chip select number (in the event that multiple NAND devices
* are connected on-board).
*
- * Returned Values:
+ * Returned Value:
* True: NAND is busy, False: NAND is ready
*
****************************************************************************/
@@ -470,7 +470,7 @@ bool board_nand_busy(int cs);
* are connected on-board).
* enable - True: enable Chip Select, False: Disable Chip select
*
- * Returned Values:
+ * Returned Value:
* OK if the HSMC was successfully configured for this CS. A negated
* errno value is returned on a failure. This would fail with -ENODEV,
* for example, if the board does not support NAND FLASH on the requested
diff --git a/arch/arm/src/sama5/sam_ohci.c b/arch/arm/src/sama5/sam_ohci.c
index 7b87c382c6952fd6fc4d24261e9def24f55819a3..fac941d686267fa1fb2135ecfa092637b9a18674 100644
--- a/arch/arm/src/sama5/sam_ohci.c
+++ b/arch/arm/src/sama5/sam_ohci.c
@@ -1543,7 +1543,7 @@ static int sam_enqueuetd(struct sam_rhport_s *rhport, struct sam_eplist_s *eplis
* Input Parameters:
* rhpndx - Root hub port index.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -1629,7 +1629,7 @@ static int sam_ep0enqueue(struct sam_rhport_s *rhport)
* ep0 - The control endpoint to be released. May be the control endpoint for
* an attached hub.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -2319,7 +2319,7 @@ static void sam_ohci_bottomhalf(void *arg)
* hport - The location to return the hub port descriptor that detected the
* connection related event.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success when a device in connected or
* disconnected. This function will not return until either (1) a device is
* connected or disconnect to/from any hub port or until (2) some failure
@@ -2437,7 +2437,7 @@ static int sam_wait(struct usbhost_connection_s *conn,
* hport - The descriptor of the hub port that has the newly connected
* device.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -2564,7 +2564,7 @@ static int sam_enumerate(struct usbhost_connection_s *conn,
* maxpacketsize - The maximum number of bytes that can be sent to or
* received from the endpoint in a single data packet
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -2627,7 +2627,7 @@ static int sam_ep0configure(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -2832,7 +2832,7 @@ errout:
* the class create() method.
* ep - The endpoint to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -2924,7 +2924,7 @@ static int sam_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep)
* maxlen - The address of a memory location provided by the caller in which to
* return the maximum size of the allocated buffer memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -2969,7 +2969,7 @@ static int sam_alloc(struct usbhost_driver_s *drvr,
* to the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3008,7 +3008,7 @@ static int sam_free(struct usbhost_driver_s *drvr, uint8_t *buffer)
* return the allocated buffer memory address.
* buflen - The size of the buffer required.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3042,7 +3042,7 @@ static int sam_ioalloc(struct usbhost_driver_s *drvr, uint8_t **buffer,
* the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3087,7 +3087,7 @@ static int sam_iofree(struct usbhost_driver_s *drvr, uint8_t *buffer)
* NOTE: On an IN transaction, req and buffer may refer to the same allocated
* memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3206,7 +3206,7 @@ static int sam_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
* (IN endpoint). buffer must have been allocated using DRVR_ALLOC
* buflen - The length of the data to be sent or received.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -3296,7 +3296,7 @@ static int sam_transfer_common(struct sam_rhport_s *rhport,
* (IN endpoint). buffer must have been allocated using DRVR_ALLOC
* buflen - The length of the data to be sent or received.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure:
*
@@ -3445,7 +3445,7 @@ errout:
* eplist - The internal representation of the device endpoint on which
* to perform the transfer.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
@@ -3555,7 +3555,7 @@ static void sam_asynch_completion(struct sam_eplist_s *eplist)
* arg - The arbitrary parameter that will be passed to the callback function
* when the transfer completes.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3635,7 +3635,7 @@ errout:
* ep - The IN or OUT endpoint descriptor for the device endpoint on which an
* asynchronous transfer should be transferred.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -3780,7 +3780,7 @@ static int sam_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep)
* related event
* connected - True: device connected; false: device disconnected
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -3831,7 +3831,7 @@ static int sam_connect(struct usbhost_driver_s *drvr,
* hport - The port from which the device is being disconnected. Might be a port
* on a hub.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
diff --git a/arch/arm/src/sama5/sam_pwm.c b/arch/arm/src/sama5/sam_pwm.c
index 90b204eac30c03d958419e8b082d309dfb90de64..1758bee1a7940aaff5c4322f3dc572a345f3006a 100644
--- a/arch/arm/src/sama5/sam_pwm.c
+++ b/arch/arm/src/sama5/sam_pwm.c
@@ -754,7 +754,7 @@ static void pwm_chan_putreg(struct sam_pwm_chan_s *chan, int offset,
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* chan - A reference to the PWM channel instance
*
* Returned Value:
@@ -827,7 +827,7 @@ static void pwm_dumpregs(struct sam_pwm_chan_s *chan, FAR const char *msg)
* Description:
* Handle timer interrupts.
*
- * Input parameters:
+ * Input Parameters:
* Standard interrupt handler inputs
*
* Returned Value:
@@ -854,7 +854,7 @@ static int pwm_interrupt(int irq, void *context, FAR void *arg)
* use. It will not, however, output pulses until the start method is
* called.
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -897,7 +897,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
* stop pulsed output, free any resources, disable the timer hardware, and
* put the system into the lowest possible power usage state
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -927,7 +927,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -1049,7 +1049,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
* Description:
* Stop the pulsed output and reset the timer resources
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -1086,7 +1086,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
* Description:
* Lower-half logic may support platform-specific ioctl commands
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* cmd - The ioctl command
* arg - The argument accompanying the ioctl command
@@ -1145,7 +1145,7 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg
* regbits = PWM_CLK_PREB_DIV(prelog2);
* prescaler = (1 << prelog2)
*
- * Input parameters:
+ * Input Parameters:
* mck - The main clock frequency
* fclk - The desired clock A or B frequency
*
@@ -1193,7 +1193,7 @@ static unsigned int pwm_clk_prescaler_log2(uint32_t mck, uint32_t fclk)
*
* div = MCK / prescaler / frequency
*
- * Input parameters:
+ * Input Parameters:
* mck - The main clock frequency
* fclk - The desired clock A or B frequency
* prelog2 - The log2(prescaler) value previously selected by
@@ -1231,7 +1231,7 @@ static unsigned int pwm_clk_divider(uint32_t mck, uint32_t fclk,
*
* frequency = MCK / prescaler / div
*
- * Input parameters:
+ * Input Parameters:
* mck - The main clock frequency
* prelog2 - The log2(prescaler) value previously selected by
* pwm_prescale_log2().
@@ -1255,7 +1255,7 @@ static uint32_t pwm_clk_frequency(uint32_t mck, unsigned int prelog2,
* Description:
* Lower-half logic may support platform-specific ioctl commands
*
- * Input parameters:
+ * Input Parameters:
* chan - A reference to the PWM channel instance
*
* Returned Value:
diff --git a/arch/arm/src/sama5/sam_spi.c b/arch/arm/src/sama5/sam_spi.c
index ce398400f419ae72c2a3c7b59b9c22e7c295113f..eaf588202065c27cd0b6602d87b991d933d45ff9 100644
--- a/arch/arm/src/sama5/sam_spi.c
+++ b/arch/arm/src/sama5/sam_spi.c
@@ -1520,7 +1520,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
ret = wd_start(spics->dmadog, DMA_TIMEOUT_TICKS,
(wdentry_t)spi_dmatimeout, 1, (uint32_t)spics);
- if (ret != OK)
+ if (ret < 0)
{
spierr("ERROR: wd_start failed: %d\n", ret);
}
@@ -1638,7 +1638,7 @@ static void spi_recvblock(struct spi_dev_s *dev, void *buffer, size_t nwords)
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* cs - Chip select number (identifying the "logical" SPI port)
*
* Returned Value:
diff --git a/arch/arm/src/sama5/sam_spi.h b/arch/arm/src/sama5/sam_spi.h
index 705f2248e75fc9df41b9f3440e05e0603e57c126..4a8697f25ab02bab2a9d3d2cd32f9f97247f4288 100644
--- a/arch/arm/src/sama5/sam_spi.h
+++ b/arch/arm/src/sama5/sam_spi.h
@@ -111,7 +111,7 @@ struct spi_dev_s; /* Forward reference */
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* cs - Chip select number (identifying the "logical" SPI port)
*
* Returned Value:
@@ -175,7 +175,7 @@ struct spi_dev_s *sam_spibus_initialize(int port);
* devid - Identifies the (logical) device
* selected - TRUE:Select the device, FALSE:De-select the device
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -197,7 +197,7 @@ void sam_spi1select(uint32_t devid, bool selected);
* dev - SPI device info
* devid - Identifies the (logical) device
*
- * Returned Values:
+ * Returned Value:
* Bit-encoded SPI status (see include/nuttx/spi/spi.h.
*
****************************************************************************/
@@ -228,7 +228,7 @@ uint8_t sam_spi1status(FAR struct spi_dev_s *dev, uint32_t devid);
* dev - SPI device info
* devid - Identifies the (logical) device
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno on failure.
*
****************************************************************************/
diff --git a/arch/arm/src/sama5/sam_ssc.c b/arch/arm/src/sama5/sam_ssc.c
index 0c8699103084cc815bbba2cccfa195319d884505..176b2235cc0bee516cb6d22240dd3dfa524e37af 100644
--- a/arch/arm/src/sama5/sam_ssc.c
+++ b/arch/arm/src/sama5/sam_ssc.c
@@ -2786,7 +2786,7 @@ static int ssc_tx_configure(struct sam_ssc_s *priv)
* Setup the MCK/2 divider based on the currently selected data width and
* the sample rate
*
- * Input Parameter:
+ * Input Parameters:
* priv - I2C device structure (only the sample rate and data length is
* needed at this point).
*
@@ -2843,7 +2843,7 @@ static uint32_t ssc_mck2divider(struct sam_ssc_s *priv)
* Description:
* Enable and configure clocking to the SSC
*
- * Input Parameter:
+ * Input Parameters:
* priv - Partially initialized I2C device structure (only the PID is
* needed at this point).
*
@@ -3394,7 +3394,7 @@ static void ssc1_configure(struct sam_ssc_s *priv)
* Description:
* Initialize the selected SSC port
*
- * Input Parameter:
+ * Input Parameters:
* port - I2S "port" number (identifying the "logical" SSC port)
*
* Returned Value:
diff --git a/arch/arm/src/sama5/sam_ssc.h b/arch/arm/src/sama5/sam_ssc.h
index b7ecafe5a454591009f0523c484d68988a21bd2c..7ae4dafe079e0450fe03881c173e303ccbec505f 100644
--- a/arch/arm/src/sama5/sam_ssc.h
+++ b/arch/arm/src/sama5/sam_ssc.h
@@ -83,7 +83,7 @@ extern "C"
* Description:
* Initialize the selected I2S port.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple I2S interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/sama5/sam_tsd.c b/arch/arm/src/sama5/sam_tsd.c
index 4ec8d1bf04cd58666254f603a0cf67e38bf648c5..15c96f7f8a6c8181ee1270d2cadca815176167df 100644
--- a/arch/arm/src/sama5/sam_tsd.c
+++ b/arch/arm/src/sama5/sam_tsd.c
@@ -432,7 +432,7 @@ errout:
* The ADC hardware can filter the touchscreen samples by averaging. The
* function selects (or de-selects) that filtering.
*
- * Input Parameters
+ * Input Parameters:
* priv - The touchscreen private data structure
* tsav - The new (shifted) value of the TSAV field of the ADC TSMR regsiter.
*
@@ -494,7 +494,7 @@ static void sam_tsd_setaverage(struct sam_tsd_s *priv, uint32_t tsav)
* will re-enable TSD interrupts when it completes processing all pending
* TSD events.
*
- * Input Parameters
+ * Input Parameters:
* arg - The touchscreen private data structure cast to (void *)
*
* Returned Value:
@@ -597,7 +597,8 @@ static void sam_tsd_bottomhalf(void *arg)
* this case; we rely on the timer expiry to get us going again.
*/
- wd_start(priv->wdog, TSD_WDOG_DELAY, sam_tsd_expiry, 1, (uint32_t)priv);
+ (void)wd_start(priv->wdog, TSD_WDOG_DELAY, sam_tsd_expiry, 1,
+ (uint32_t)priv);
ier = 0;
goto ignored;
}
@@ -675,7 +676,8 @@ static void sam_tsd_bottomhalf(void *arg)
/* Continue to sample the position while the pen is down */
- wd_start(priv->wdog, TSD_WDOG_DELAY, sam_tsd_expiry, 1, (uint32_t)priv);
+ (void)wd_start(priv->wdog, TSD_WDOG_DELAY, sam_tsd_expiry, 1,
+ (uint32_t)priv);
/* Check the thresholds. Bail if (1) this is not the first
* measurement and (2) there is no significant difference from
@@ -1032,7 +1034,7 @@ errout:
}
/****************************************************************************
- * Name:sam_tsd_ioctl
+ * Name: sam_tsd_ioctl
****************************************************************************/
static int sam_tsd_ioctl(struct file *filep, int cmd, unsigned long arg)
@@ -1705,7 +1707,7 @@ errout_with_priv:
* Description:
* Handles ADC interrupts associated with touchscreen channels
*
- * Input parmeters:
+ * Input Parameters:
* pending - Current set of pending interrupts being handled
*
* Returned Value:
diff --git a/arch/arm/src/sama5/sam_tsd.h b/arch/arm/src/sama5/sam_tsd.h
index 3ae36434b792a21f213144a98f13694b1981b551..ff0d6a5ead826217c156ca30306c4b58d6681362 100644
--- a/arch/arm/src/sama5/sam_tsd.h
+++ b/arch/arm/src/sama5/sam_tsd.h
@@ -119,7 +119,7 @@ int sam_tsd_register(FAR struct sam_adc_s *adc, int minor);
* Description:
* Handles ADC interrupts associated with touchscreen channels
*
- * Input parmeters:
+ * Input Parameters:
* pending - Current set of pending interrupts being handled
*
* Returned Value:
diff --git a/arch/arm/src/sama5/sam_twi.c b/arch/arm/src/sama5/sam_twi.c
index 7e32dd7720789d4e15b3cfb4c37ee4cec829ba57..11f9cf8801efe78a88ec74674b627d7a611c779c 100644
--- a/arch/arm/src/sama5/sam_twi.c
+++ b/arch/arm/src/sama5/sam_twi.c
@@ -487,7 +487,7 @@ static int twi_wait(struct twi_dev_s *priv, unsigned int size)
* TWI transfer stalls.
*/
- wd_start(priv->timeout, timeout, twi_timeout, 1, (uint32_t)priv);
+ (void)wd_start(priv->timeout, timeout, twi_timeout, 1, (uint32_t)priv);
/* Wait for either the TWI transfer or the timeout to complete */
diff --git a/arch/arm/src/sama5/sam_twi.h b/arch/arm/src/sama5/sam_twi.h
index e8d75e133540ecfd66e90cda005cf6bff16832d9..f966bec8f8b5ddd9ec2af97800186f2b9434730a 100644
--- a/arch/arm/src/sama5/sam_twi.h
+++ b/arch/arm/src/sama5/sam_twi.h
@@ -57,7 +57,7 @@
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
@@ -73,7 +73,7 @@ FAR struct i2c_master_s *sam_i2cbus_initialize(int port);
* Description:
* De-initialize the selected I2C port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the sam_i2cbus_initialize()
*
* Returned Value:
diff --git a/arch/arm/src/sama5/sam_udphs.c b/arch/arm/src/sama5/sam_udphs.c
index 090e10b4d84ce1fdad192fe88d05feccbf4656d2..1c04600e1a710f4691ac5336c4240463aa197e6b 100644
--- a/arch/arm/src/sama5/sam_udphs.c
+++ b/arch/arm/src/sama5/sam_udphs.c
@@ -3048,7 +3048,7 @@ static void sam_resume(struct sam_usbdev_s *priv)
/****************************************************************************
* Name: sam_ep_reset
*
- * Description
+ * Description:
* Reset and disable a set of endpoints.
*
****************************************************************************/
@@ -3090,7 +3090,7 @@ static void sam_ep_reset(struct sam_usbdev_s *priv, uint8_t epno)
/****************************************************************************
* Name: sam_epset_reset
*
- * Description
+ * Description:
* Reset and disable a set of endpoints.
*
****************************************************************************/
diff --git a/arch/arm/src/sama5/sam_wdt.c b/arch/arm/src/sama5/sam_wdt.c
index 9d3f7dd61eaed194699b3e485a7712664a01b036..0fd0fa21ee1b3e8b8f9dbffd11b6324cdde88ae2 100644
--- a/arch/arm/src/sama5/sam_wdt.c
+++ b/arch/arm/src/sama5/sam_wdt.c
@@ -254,7 +254,7 @@ static void sam_putreg(uint32_t regval, uintptr_t regaddr)
* Input Parameters:
* Usual interrupt handler arguments.
*
- * Returned Values:
+ * Returned Value:
* Always returns OK.
*
****************************************************************************/
@@ -290,7 +290,7 @@ static int sam_interrupt(int irq, FAR void *context, FAR void *arg)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -320,7 +320,7 @@ static int sam_start(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -350,7 +350,7 @@ static int sam_stop(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -378,7 +378,7 @@ static int sam_keepalive(FAR struct watchdog_lowerhalf_s *lower)
* driver state structure.
* stawtus - The location to return the watchdog status information.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -435,7 +435,7 @@ static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower,
* driver state structure.
* timeout - The new timeout value in millisecnds.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -554,7 +554,7 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* function pointer is NULL, then the reset-on-expiration
* behavior is restored,
*
- * Returned Values:
+ * Returned Value:
* The previous watchdog expiration function pointer or NULL is there was
* no previous function pointer, i.e., if the previous behavior was
* reset-on-expiration (NULL is also returned if an error occurs).
@@ -619,7 +619,7 @@ static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower,
* interpretation of this argument depends on the particular
* command.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -649,7 +649,7 @@ static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
* Input Parameters:
* None
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/sama5/sam_wdt.h b/arch/arm/src/sama5/sam_wdt.h
index 0f9eab7b75b871c6e96f466872f916ebc5bb5def..ba3a067b1df0b5277efc4e59b58f12efef6ccc43 100644
--- a/arch/arm/src/sama5/sam_wdt.h
+++ b/arch/arm/src/sama5/sam_wdt.h
@@ -76,7 +76,7 @@ extern "C"
*
* At a minimum, this function should call watchdog_register().
*
- * Input parameters:
+ * Input Parameters:
* None
*
* Returned Value:
diff --git a/arch/arm/src/samdl/Kconfig b/arch/arm/src/samdl/Kconfig
index ec8507a048b644819aa63c96995bcabbe8aea4b9..3026bc9fcbaf7392a85a1301683bfff1d4a85ad4 100644
--- a/arch/arm/src/samdl/Kconfig
+++ b/arch/arm/src/samdl/Kconfig
@@ -572,6 +572,10 @@ config SAMDL_USB
default n
depends on SAMDL_HAVE_USB
+config SAMDL_EIC
+ bool "External Interrupt Controller"
+ default n
+
config SAMDL_WDT
bool "Watchdog Timer"
default n
@@ -716,7 +720,15 @@ config SAMDL_HAVE_SPI
bool
select SPI
-if SAMDL_HAVE_SPI
+menu "SPI options"
+ depends on SAMDL_HAVE_SPI
+
+config SAMDL_SPI_DMA
+ bool "SPI DMA"
+ default n
+ depends on SAMDL_DMAC && EXPERIMENTAL
+ ---help---
+ Use DMA for SPI SERCOM peripherals.
config SAMDL_SPI_REGDEBUG
bool "SPI register-Level Debug"
@@ -725,13 +737,14 @@ config SAMDL_SPI_REGDEBUG
---help---
Enable very low-level register access debug. Depends on DEBUG_SPI.
-endif # SAMDL_HAVE_SPI
+endmenu # SPI options
config SAMDL_HAVE_I2C
bool
select I2C
-if SAMDL_HAVE_I2C
+menu "I2C options"
+ depends on SAMDL_HAVE_I2C
config SAMDL_I2C_REGDEBUG
bool "I2C register-Level Debug"
@@ -740,9 +753,10 @@ config SAMDL_I2C_REGDEBUG
---help---
Enable very low-level register access debug. Depends on DEBUG_I2C.
-endif # SAMDL_HAVE_I2C
+endmenu # I2C options
-if SAMDL_HAVE_USB
+menu "USB options"
+ depends on SAMDL_HAVE_USB
config SAMDL_USB_ENABLE_PPEP
bool "Enable Ping-Pong Endpoints"
@@ -762,4 +776,5 @@ config SAMDL_USB_REGDEBUG
Enable very low-level register access debug. Depends on
CONFIG_DEBUG_USB_INFO.
-endif # SAMDL_HAVE_USB
+endmenu # USB options
+
diff --git a/arch/arm/src/samdl/Make.defs b/arch/arm/src/samdl/Make.defs
index 71b156c6c774f7a8a656af27f8e6cee0c30d0dac..e62eba81f3b982efe7b141f7869293fa04210447 100644
--- a/arch/arm/src/samdl/Make.defs
+++ b/arch/arm/src/samdl/Make.defs
@@ -102,3 +102,11 @@ endif
ifeq ($(CONFIG_SAMDL_USB),y)
CHIP_CSRCS += sam_usb.c
endif
+
+ifeq ($(CONFIG_SAMDL_EIC),y)
+CHIP_CSRCS += sam_eic.c
+endif
+
+ifeq ($(CONFIG_SAMDL_AC),y)
+CHIP_CSRCS += sam_ac.c
+endif
diff --git a/arch/arm/src/samdl/chip/samd_ac.h b/arch/arm/src/samdl/chip/samd_ac.h
new file mode 100644
index 0000000000000000000000000000000000000000..31c896402021e63c2236c5d9b6db811dd4a8975c
--- /dev/null
+++ b/arch/arm/src/samdl/chip/samd_ac.h
@@ -0,0 +1,209 @@
+/********************************************************************************************
+ * arch/arm/src/samdl/chip/samd_ac.h
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Matt Thompson
+ *
+ * References:
+ * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
+ * Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_AC_H
+#define __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_AC_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+#ifdef CONFIG_ARCH_FAMILY_SAMD21
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+/* AC register offsets **********************************************************************/
+
+#define SAM_AC_CTRLA_OFFSET 0x0000 /* Control A Register */
+#define SAM_AC_CTRLB_OFFSET 0x0001 /* Control B Register */
+#define SAM_AC_EVCTRL_OFFSET 0x0002 /* Event Control Register */
+#define SAM_AC_INTENCLR_OFFSET 0x0004 /* Interrupt Enable Clear Register */
+#define SAM_AC_INTENSET_OFFSET 0x0005 /* Interrupt Enable Set Register */
+#define SAM_AC_INTFLAG_OFFSET 0x0006 /* Interrupt Flag Status and Clear Register */
+#define SAM_AC_STATUSA_OFFSET 0x0008 /* Status A Register */
+#define SAM_AC_STATUSB_OFFSET 0x0009 /* Status B Register */
+#define SAM_AC_STATUSC_OFFSET 0x000A /* Status C Register */
+#define SAM_AC_WINCTRL_OFFSET 0x000C /* Window Control Register */
+#define SAM_AC_COMPCTRL0_OFFSET 0x0010 /* Comparator 0 Control Register */
+#define SAM_AC_COMPCTRL1_OFFSET 0x0014 /* Comparator 1 Control Register */
+#define SAM_AC_SCALER0_OFFSET 0x0020 /* Scaler 0 Register */
+#define SAM_AC_SCALER1_OFFSET 0x0021 /* Scaler 1 Register */
+
+/* AC register addresses *******************************************************************/
+
+#define SAM_AC_CTRLA (SAM_AC_BASE+SAM_AC_CTRLA_OFFSET)
+#define SAM_AC_CTRLB (SAM_AC_BASE+SAM_AC_CTRLB_OFFSET)
+#define SAM_AC_EVCTRL (SAM_AC_BASE+SAM_AC_EVCTRL_OFFSET)
+#define SAM_AC_INTENCLR (SAM_AC_BASE+SAM_AC_INTENCLR_OFFSET)
+#define SAM_AC_INTENSET (SAM_AC_BASE+SAM_AC_INTENSET_OFFSET)
+#define SAM_AC_INTFLAG (SAM_AC_BASE+SAM_AC_INTFLAG_OFFSET)
+#define SAM_AC_STATUSA (SAM_AC_BASE+SAM_AC_STATUSA_OFFSET)
+#define SAM_AC_STATUSB (SAM_AC_BASE+SAM_AC_STATUSB_OFFSET)
+#define SAM_AC_STATUSC (SAM_AC_BASE+SAM_AC_STATUSC_OFFSET)
+#define SAM_AC_WINCTRL (SAM_AC_BASE+SAM_AC_WINCTRL_OFFSET)
+#define SAM_AC_COMPCTRL0 (SAM_AC_BASE+SAM_AC_COMPCTRL0_OFFSET)
+#define SAM_AC_COMPCTRL1 (SAM_AC_BASE+SAM_AC_COMPCTRL1_OFFSET)
+#define SAM_AC_SCALER0 (SAM_AC_BASE+SAM_AC_SCALER0_OFFSET)
+#define SAM_AC_SCALER1 (SAM_AC_BASE+SAM_AC_SCALER1_OFFSET)
+
+/* AC register bit definitions ************************************************************/
+
+/* Control A Register */
+
+#define AC_CTRLA_SWRTS (1 << 0) /* Bit 0: Software reset */
+#define AC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable AC */
+#define AC_CTRLA_RUNSTDBY (1 << 2) /* Bit 2: Run in standby */
+#define AC_CTRLA_LPMUX (1 << 7) /* Bit 7: Low-Power Mux */
+
+/* Control B Register */
+
+#define AC_CTRLB_START0 (1 << 0) /* Bit 0: Comparator 0 start */
+#define AC_CTRLB_START1 (1 << 1) /* Bit 1: Comparator 1 start */
+
+/* Event Control Register */
+
+#define AC_EVCTRL_COMPEO0 (1 << 0) /* Bit 0: Comparator 0 Event Output enable */
+#define AC_EVCTRL_COMPEO1 (1 << 1) /* Bit 1: Comparator 1 Event Output enable */
+#define AC_EVCTRL_WINEO0 (1 << 4) /* Bit 4: Window 0 Event Output enable */
+#define AC_EVCTRL_COMPEI0 (1 << 8) /* Bit 8: Comparator 0 Event Input enable */
+#define AC_EVCTRL_COMPEI1 (1 << 9) /* Bit 9: Comparator 1 Event Input enable */
+
+/* Common bit definitions for Interrupt Enable Clear Register, Interrupt Enable Set
+ * Register, and Interrupt Flag Status and Clear Register
+ */
+
+#define AC_INT_COMP0 (1 << 0) /* Bit 0: Comparator 0 */
+#define AC_INT_COMP1 (1 << 1) /* Bit 1: Comparator 1 */
+#define AC_INT_WIN0 (1 << 4) /* Bit 4: Window 0 */
+#define AC_INT_ALL 0x13
+
+/* Status A Register */
+
+#define AC_STATUSA_STATE0 (1 << 0) /* Bit 0: State 0 - Output state of comparator 0 */
+#define AC_STATUSA_STATE1 (1 << 1) /* Bit 1: State 1 - Output state of comparator 1 */
+#define AC_STATUSA_WSTATE_SHIFT (4)
+#define AC_STATUSA_WSTATE_MASK (3 << AC_STATUSA_WSTATE_SHIFT)
+# define AC_STATUSA_WSTATE_ABOVE (0 << AC_STATUSA_WSTATE_SHIFT)
+# define AC_STATUSA_WSTATE_INSIDE (1 << AC_STATUSA_WSTATE_SHIFT)
+# define AC_STATUSA_WSTATE_BELOW (2 << AC_STATUSA_WSTATE_SHIFT)
+
+/* Status B Register */
+
+#define AC_STATUSB_READY0 (1 << 0) /* Bit 0: Ready 0 - Comparator 0 ready status */
+#define AC_STATUSB_READY1 (1 << 1) /* Bit 1: Ready 1 - Comparator 1 ready status */
+#define AC_STATUSB_SYNCBUSY (1 << 7) /* Bit 7: Synchronoziation ready */
+
+/* Status C Register */
+
+/* Window Control Register */
+
+#define AC_WINCTRL_WEN0 (1 << 0) /* Bit 0: Window enable (both comparators) */
+#define AC_WINCTRL_WINTSEL_SHIFT (1)
+#define AC_WINCTRL_WINTSEL_MASK (3 << AC_WINCTRL_WINTSEL_SHIFT)
+# define AC_WINCTRL_WINTSEL_ABOVE (0 << AC_WINCTRL_WINTSEL_SHIFT)
+# define AC_WINCTRL_WINTSEL_INSIDE (1 << AC_WINCTRL_WINTSEL_SHIFT)
+# define AC_WINCTRL_WINTSEL_BELOW (2 << AC_WINCTRL_WINTSEL_SHIFT)
+# define AC_WINCTRL_WINTSEL_OUTSIDE (3 << AC_WINCTRL_WINTSEL_SHIFT)
+
+/* Comparator Control Registers */
+
+#define AC_COMPCTRL_ENABLE (1 << 0) /* Bit 0: Enable Comparator */
+#define AC_COMPCTRL_SINGLE (1 << 1) /* Bit 1: Single Shot Mode */
+#define AC_COMPCTRL_SPEED_SHIFT (2)
+#define AC_COMPCTRL_SPEED_MASK (3 << AC_COMPCTRL_SPEED_SHIFT)
+# define AC_COMPCTRL_SPEED_LOW (0 << AC_COMPCTRL_SPEED_SHIFT)
+# define AC_COMPCTRL_SPEED_HIGH (1 << AC_COMPCTRL_SPEED_SHIFT)
+#define AC_COMPCTRL_INTSEL_SHIFT (5)
+#define AC_COMPCTRL_INTSEL_MASK (3 << AC_COMPCTRL_INTSEL_SHIFT)
+# define AC_COMPCTRL_INTSEL_TOGGLE (0 << AC_COMPCTRL_INTSEL_SHIFT)
+# define AC_COMPCTRL_INTSEL_RISING (1 << AC_COMPCTRL_INTSEL_SHIFT)
+# define AC_COMPCTRL_INTSEL_FALLING (2 << AC_COMPCTRL_INTSEL_SHIFT)
+# define AC_COMPCTRL_INTSEL_EOC (3 << AC_COMPCTRL_INTSEL_SHIFT)
+#define AC_COMPCTRL_MUXNEG_SHIFT (8)
+#define AC_COMPCTRL_MUXNEG_MASK (7 << AC_COMPCTRL_MUXNEG_SHIFT)
+# define AC_COMPCTRL_MUXNEG_PIN0 (0 << AC_COMPCTRL_MUXNEG_SHIFT)
+# define AC_COMPCTRL_MUXNEG_PIN1 (1 << AC_COMPCTRL_MUXNEG_SHIFT)
+# define AC_COMPCTRL_MUXNEG_PIN2 (2 << AC_COMPCTRL_MUXNEG_SHIFT)
+# define AC_COMPCTRL_MUXNEG_PIN3 (3 << AC_COMPCTRL_MUXNEG_SHIFT)
+# define AC_COMPCTRL_MUXNEG_GND (4 << AC_COMPCTRL_MUXNEG_SHIFT)
+# define AC_COMPCTRL_MUXNEG_VSCALE (5 << AC_COMPCTRL_MUXNEG_SHIFT)
+# define AC_COMPCTRL_MUXNEG_BANDGAP (6 << AC_COMPCTRL_MUXNEG_SHIFT)
+# define AC_COMPCTRL_MUXNEG_DAC (7 << AC_COMPCTRL_MUXNEG_SHIFT)
+#define AC_COMPCTRL_MUXPOS_SHIFT (12)
+#define AC_COMPCTRL_MUXPOS_MASK (3 << AC_COMPCTRL_MUXPOS_SHIFT)
+# define AC_COMPCTRL_MUXPOS_PIN0 (0 << AC_COMPCTRL_MUXPOS_SHIFT)
+# define AC_COMPCTRL_MUXPOS_PIN1 (1 << AC_COMPCTRL_MUXPOS_SHIFT)
+# define AC_COMPCTRL_MUXPOS_PIN2 (2 << AC_COMPCTRL_MUXPOS_SHIFT)
+# define AC_COMPCTRL_MUXPOS_PIN3 (3 << AC_COMPCTRL_MUXPOS_SHIFT)
+#define AC_COMPCTRL_SWAP (1 << 13) /* Bit 13: Swap Inputs and Invert */
+#define AC_COMPCTRL_OUT_SHIFT (16)
+#define AC_COMPCTRL_OUT_MASK (3 << AC_COMPCTRL_OUT_SHIFT)
+# define AC_COMPCTRL_OUT_OFF (0 << AC_COMPCTRL_OUT_SHIFT)
+# define AC_COMPCTRL_OUT_ASYNC (1 << AC_COMPCTRL_OUT_SHIFT)
+# define AC_COMPCTRL_OUT_SYNC (2 << AC_COMPCTRL_OUT_SHIFT)
+#define AC_COMPCTRL_HYST (1 << 19) /* Bit 19: Hysteresis Enable */
+#define AC_COMPCTRL_FLEN_SHIFT (24)
+#define AC_COMPCTRL_FLEN_MASK (7 << AC_COMPCTRL_FLEN_SHIFT)
+# define AC_COMPCTRL_FLEN_OFF (0 << AC_COMPCTRL_FLEN_SHIFT)
+# define AC_COMPCTRL_FLEN_MAJ3 (1 << AC_COMPCTRL_FLEN_SHIFT)
+# define AC_COMPCTRL_FLEN_MAJ5 (2 << AC_COMPCTRL_FLEN_SHIFT)
+
+/* Scaler Registers */
+
+#define AC_COMPCTRL_SCALER_MASK (0x3f)
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
+#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_AC_H */
diff --git a/arch/arm/src/samdl/chip/samd_dac.h b/arch/arm/src/samdl/chip/samd_dac.h
new file mode 100644
index 0000000000000000000000000000000000000000..274cab701efad1975e8866108e8445b169417f1b
--- /dev/null
+++ b/arch/arm/src/samdl/chip/samd_dac.h
@@ -0,0 +1,136 @@
+/********************************************************************************************
+ * arch/arm/src/samdl/chip/saml_dac.h
+ *
+ * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * References:
+ * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
+ * Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_DAC_H
+#define __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_DAC_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+#ifdef CONFIG_ARCH_FAMILY_SAMD21
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+/* DAC register offsets ********************************************************************/
+
+#define SAM_DAC_CTRLA_OFFSET 0x0000 /* Control A Register */
+#define SAM_DAC_CTRLB_OFFSET 0x0001 /* Control B Register */
+#define SAM_DAC_EVCTRL_OFFSET 0x0002 /* Event Control Register */
+#define SAM_DAC_INTENCLR_OFFSET 0x0004 /* Interrupt Enable Clear Register */
+#define SAM_DAC_INTENSET_OFFSET 0x0005 /* Interrupt Enable Set Register */
+#define SAM_DAC_INTFLAG_OFFSET 0x0006 /* Interrupt Flag Status and Clear Register */
+#define SAM_DAC_STATUS_OFFSET 0x0007 /* Status Register */
+#define SAM_DAC_DATA0_OFFSET 0x0008 /* Data DAC0 Register */
+#define SAM_DAC_DATA1_OFFSET 0x0009 /* Data DAC1 Register */
+#define SAM_DAC_DATABUF0_OFFSET 0x000C /* Data Buffer DAC0 Register */
+#define SAM_DAC_DATABUF1_OFFSET 0x000D /* Data Buffer DAC1 Register */
+
+/* DAC register addresses ******************************************************************/
+
+#define SAM_DAC_CTRLA (SAM_DAC_BASE+SAM_DAC_CTRLA_OFFSET)
+#define SAM_DAC_CTRLB (SAM_DAC_BASE+SAM_DAC_CTRLB_OFFSET)
+#define SAM_DAC_EVCTRL (SAM_DAC_BASE+SAM_DAC_EVCTRL_OFFSET)
+#define SAM_DAC_INTENCLR (SAM_DAC_BASE+SAM_DAC_INTENCLR_OFFSET)
+#define SAM_DAC_INTENSET (SAM_DAC_BASE+SAM_DAC_INTENSET_OFFSET)
+#define SAM_DAC_INTFLAG (SAM_DAC_BASE+SAM_DAC_INTFLAG_OFFSET)
+#define SAM_DAC_STATUS (SAM_DAC_BASE+SAM_DAC_STATUS_OFFSET)
+#define SAM_DAC_DATA0 (SAM_DAC_BASE+SAM_DAC_DATA0_OFFSET)
+#define SAM_DAC_DATA1 (SAM_DAC_BASE+SAM_DAC_DATA1_OFFSET)
+#define SAM_DAC_DATABUF0 (SAM_DAC_BASE+SAM_DAC_DATABUF0_OFFSET)
+#define SAM_DAC_DATABUF1 (SAM_DAC_BASE+SAM_DAC_DATABUF1_OFFSET)
+
+/* DAC register bit definitions ************************************************************/
+
+/* Control A Register */
+
+#define DAC_CTRLA_SWRTS (1 << 0) /* Bit 0: Software reset */
+#define DAC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable DAC controller */
+#define DAC_CTRLA_RUNSTDBY (1 << 2) /* Bit 1: Run in standby */
+
+/* Control B Register */
+
+#define DAC_CTRLB_EOEN (1 << 0) /* Bit 0: External Output Enable (to Vout) */
+#define DAC_CTRLB_IOEN (1 << 1) /* Bit 1: Internal Output Enable (to analog comparator) */
+#define DAC_CTRLB_LEFTADJ (1 << 2) /* Bit 2: Left-Adjusted Data */
+#define DAC_CTRLB_VPD (1 << 3) /* Bit 3: Voltage Pump Disabled */
+#define DAC_CTRLB_BDWP (1 << 4) /* Bit 4: Bypass DATABUF Write protection */
+#define DAC_CTRLB_REFSEL_SHIFT (6) /* Bit 7:6: Reference selection */
+#define DAC_CTRLB_REFSEL_MASK (3 << DAC_CTRLB_REFSEL_SHIFT)
+# define DAC_CTRLB_REFSEL_INTREF (0 << DAC_CTRLB_REFSEL_SHIFT) /* Internal voltage reference */
+# define DAC_CTRLB_REFSEL_VDDANA (1 << DAC_CTRLB_REFSEL_SHIFT) /* Analog voltage supply */
+# define DAC_CTRLB_REFSEL_VREFA (2 << DAC_CTRLB_REFSEL_SHIFT) /* External voltage reference */
+
+/* Event Control Register */
+
+#define DAC_EVCTRL_STARTEI (1 << 0) /* Bit 0: Start conversion event input */
+#define DAC_EVCTRL_EMPTYEO (1 << 1) /* Bit 1: Data buffer empty event output */
+
+/* Common bit definitions for Interrupt Enable Clear Register, Interrupt Enable Set
+ * Register, and Interrupt Flag Status and Clear Register
+ */
+
+#define DAC_INT_UNDERRUN (1 << 0) /* Bit 0: Underrun interrupt */
+#define DAC_INT_EMPTY (1 << 1) /* Bit 1: Data buffer empty interrupt */
+#define DAC_INT_SYNCRDY (1 << 2) /* Bit 2: Sync ready */
+#define DAC_INT_ALL 0x07
+
+/* Status Register */
+
+#define DAC_STATUS_SYNCBUSY (1 << 7) /* Bit 0: Sync busy */
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
+#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_DAC_H */
diff --git a/arch/arm/src/samdl/chip/samd_dmac.h b/arch/arm/src/samdl/chip/samd_dmac.h
new file mode 100644
index 0000000000000000000000000000000000000000..318fc38a42bb8d20813dda7835a2991f586af786
--- /dev/null
+++ b/arch/arm/src/samdl/chip/samd_dmac.h
@@ -0,0 +1,399 @@
+/********************************************************************************************
+ * arch/arm/src/samdl/chip/samd_dmac.h
+ *
+ * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ * Matt Thompson
+ *
+ * References:
+ * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
+ * Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_DMAC_H
+#define __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_DMAC_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+/* DMAC register offsets ********************************************************************/
+
+#define SAM_DMAC_CTRL_OFFSET 0x0000 /* Control Register */
+#define SAM_DMAC_CRCCTRL_OFFSET 0x0002 /* CRC Control Register */
+#define SAM_DMAC_CRCDATAIN_OFFSET 0x0004 /* CRC Data Input Register */
+#define SAM_DMAC_CRCCHKSUM_OFFSET 0x0008 /* CRC Checksum Register */
+#define SAM_DMAC_CRCSTATUS_OFFSET 0x000c /* CRC Status Register */
+#define SAM_DMAC_DBGCTRL_OFFSET 0x000d /* Debug Control Register */
+#define SAM_DMAC_QOSCTRL_OFFSET 0x000e /* Quality of Service Control Register */
+#define SAM_DMAC_SWTRIGCTRL_OFFSET 0x0010 /* Software Trigger Control Register */
+#define SAM_DMAC_PRICTRL0_OFFSET 0x0014 /* Priority Control 0 Register */
+#define SAM_DMAC_INTPEND_OFFSET 0x0020 /* Interrupt Pending Register */
+#define SAM_DMAC_INTSTATUS_OFFSET 0x0024 /* Interrupt Status Register */
+#define SAM_DMAC_BUSYCH_OFFSET 0x0028 /* Busy Channels Register */
+#define SAM_DMAC_PENDCH_OFFSET 0x002c /* Pending Channels Register */
+#define SAM_DMAC_ACTIVE_OFFSET 0x0030 /* Active Channels and Levels Register */
+#define SAM_DMAC_BASEADDR_OFFSET 0x0034 /* Descriptor Memory Section Base Address Register */
+#define SAM_DMAC_WRBADDR_OFFSET 0x0038 /* Write-Back Memory Section Base Address Register */
+#define SAM_DMAC_CHID_OFFSET 0x003f /* Channel ID Register */
+#define SAM_DMAC_CHCTRLA_OFFSET 0x0040 /* Channel Control A Register */
+#define SAM_DMAC_CHCTRLB_OFFSET 0x0044 /* Channel Control B Register */
+#define SAM_DMAC_CHINTENCLR_OFFSET 0x004c /* Channel Interrupt Enable Clear Register */
+#define SAM_DMAC_CHINTENSET_OFFSET 0x004d /* Channel Interrupt Enable Set Register */
+#define SAM_DMAC_CHINTFLAG_OFFSET 0x004e /* Channel Interrupt Flag Status and Clear Register */
+#define SAM_DMAC_CHSTATUS_OFFSET 0x004f /* Channel Status Register */
+
+/* LPSRAM Registers Relative to BASEADDR or WRBADDR */
+
+#define SAM_LPSRAM_BTCTRL_OFFSET 0x0000 /* Block Transfer Control Register */
+#define SAM_LPSRAM_BTCNT_OFFSET 0x0002 /* Block Transfer Count Register */
+#define SAM_LPSRAM_SRCADDR_OFFSET 0x0004 /* Block Transfer Source Address Register */
+#define SAM_LPSRAM_DSTADDR_OFFSET 0x0008 /* Block Transfer Destination Address Register */
+#define SAM_LPSRAM_DESCADDR_OFFSET 0x000c /* Next Address Descriptor Register */
+
+/* DMAC register addresses ******************************************************************/
+
+#define SAM_DMAC_CTRL (SAM_DMAC_BASE+SAM_DMAC_CTRL_OFFSET)
+#define SAM_DMAC_CRCCTRL (SAM_DMAC_BASE+SAM_DMAC_CRCCTRL_OFFSET)
+#define SAM_DMAC_CRCDATAIN (SAM_DMAC_BASE+SAM_DMAC_CRCDATAIN_OFFSET)
+#define SAM_DMAC_CRCCHKSUM (SAM_DMAC_BASE+SAM_DMAC_CRCCHKSUM_OFFSET)
+#define SAM_DMAC_CRCSTATUS (SAM_DMAC_BASE+SAM_DMAC_CRCSTATUS_OFFSET)
+#define SAM_DMAC_DBGCTRL (SAM_DMAC_BASE+SAM_DMAC_DBGCTRL_OFFSET)
+#define SAM_DMAC_QOSCTRL (SAM_DMAC_BASE+SAM_DMAC_QOSCTRL_OFFSET)
+#define SAM_DMAC_SWTRIGCTRL (SAM_DMAC_BASE+SAM_DMAC_SWTRIGCTRL_OFFSET)
+#define SAM_DMAC_PRICTRL0 (SAM_DMAC_BASE+SAM_DMAC_PRICTRL0_OFFSET)
+#define SAM_DMAC_INTPEND (SAM_DMAC_BASE+SAM_DMAC_INTPEND_OFFSET)
+#define SAM_DMAC_INTSTATUS (SAM_DMAC_BASE+SAM_DMAC_INTSTATUS_OFFSET)
+#define SAM_DMAC_BUSYCH (SAM_DMAC_BASE+SAM_DMAC_BUSYCH_OFFSET)
+#define SAM_DMAC_PENDCH (SAM_DMAC_BASE+SAM_DMAC_PENDCH_OFFSET)
+#define SAM_DMAC_ACTIVE (SAM_DMAC_BASE+SAM_DMAC_ACTIVE_OFFSET)
+#define SAM_DMAC_BASEADDR (SAM_DMAC_BASE+SAM_DMAC_BASEADDR_OFFSET)
+#define SAM_DMAC_WRBADDR (SAM_DMAC_BASE+SAM_DMAC_WRBADDR_OFFSET)
+#define SAM_DMAC_CHID (SAM_DMAC_BASE+SAM_DMAC_CHID_OFFSET)
+#define SAM_DMAC_CHCTRLA (SAM_DMAC_BASE+SAM_DMAC_CHCTRLA_OFFSET)
+#define SAM_DMAC_CHCTRLB (SAM_DMAC_BASE+SAM_DMAC_CHCTRLB_OFFSET)
+#define SAM_DMAC_CHINTENCLR (SAM_DMAC_BASE+SAM_DMAC_CHINTENCLR_OFFSET)
+#define SAM_DMAC_CHINTENSET (SAM_DMAC_BASE+SAM_DMAC_CHINTENSET_OFFSET)
+#define SAM_DMAC_CHINTFLAG (SAM_DMAC_BASE+SAM_DMAC_CHINTFLAG_OFFSET)
+#define SAM_DMAC_CHSTATUS (SAM_DMAC_BASE+SAM_DMAC_CHSTATUS_OFFSET)
+
+/* DMAC register bit definitions ************************************************************/
+
+/* Control Register */
+
+#define DMAC_CTRL_SWRST (1 << 0) /* Bit 0: Software Reset */
+#define DMAC_CTRL_DMAENABLE (1 << 1) /* Bit 1: DMA Enable */
+#define DMAC_CTRL_CRCENABLE (1 << 2) /* Bit 2: CRC Enable */
+#define DMAC_CTRL_LVLEN0 (1 << 8) /* Bit 8: Priority level 0 Enable */
+#define DMAC_CTRL_LVLEN1 (1 << 9) /* Bit 9: Priority level 1 Enable */
+#define DMAC_CTRL_LVLEN2 (1 << 10) /* Bit 10: Priority level 2 Enable */
+#define DMAC_CTRL_LVLEN3 (1 << 11) /* Bit 10: Priority level 2 Enable */
+
+/* CRC Control Register */
+
+#define DMAC_CRCCTRL_CRCBEATSIZE_SHIFT (0) /* Bits 0-1: CRC beat size */
+#define DMAC_CRCCTRL_CRCBEATSIZE_MASK (3 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT)
+# define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (0 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 8-bit bus transfer */
+# define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (1 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 16-bit bus transfer */
+# define DMAC_CRCCTRL_CRCBEATSIZE_WORD (2 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 32-bit bus transfer */
+#define DMAC_CRCCTRL_CRCPOLY_SHIFT (2) /* Bits 2-3: CRC polynomial type */
+#define DMAC_CRCCTRL_CRCPOLY_MASK (3 < DMAC_CRCCTRL_CRCPOLY_SHIFT)
+# define DMAC_CRCCTRL_CRCPOLY_CRC16 (0 < DMAC_CRCCTRL_CRCPOLY_SHIFT) /* CRC-16 (CRC-CCITT) */
+# define DMAC_CRCCTRL_CRCPOLY_CRC32 (1 < DMAC_CRCCTRL_CRCPOLY_SHIFT) /* CRC32 (IEEE 802.3) */
+#define DMAC_CRCCTRL_CRCSRC_SHIFT (8) /* Bits 8-13: CRC Input Source */
+#define DMAC_CRCCTRL_CRCSRC_MASK (0x3f < DMAC_CRCCTRL_CRCSRC_SHIFT)
+# define DMAC_CRCCTRL_CRCSRC_NOACTION (0 < DMAC_CRCCTRL_CRCSRC_SHIFT) /* No action */
+# define DMAC_CRCCTRL_CRCSRC_IO (1 < DMAC_CRCCTRL_CRCSRC_SHIFT) /* I/O interface */
+# define DMAC_CRCCTRL_CRCSRC_CHAN(n) (((uint32_t)(n) + 0x20) < DMAC_CRCCTRL_CRCSRC_SHIFT)
+
+/* CRC Data Input Register (32-bit value) */
+/* CRC Checksum Register (32-bit value) */
+
+/* CRC Status Register */
+
+#define DMAC_CRCSTATUS_CRCBUSY (1 << 0) /* Bit 0: CRC module busy */
+#define DMAC_CRCSTATUS_CRCZERO (1 << 1) /* Bit 1: CRC zero */
+
+/* Debug Control Register */
+
+#define DMAC_DBGCTRL_DBGRUN (1 << 0) /* Bit 0: Debug run */
+
+/* Quality of Service Control Register */
+
+#define DMAC_QOSCTRL_WRBQOS_SHIFT (0) /* Bits 0-1: Write back quality of service */
+#define DMAC_QOSCTRL_WRBQOS_MASK (3 << DMAC_QOSCTRL_WRBQOS_SHIFT)
+# define DMAC_QOSCTRL_WRBQOS_DISABLE (0 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Background */
+# define DMAC_QOSCTRL_WRBQOS_LOW (1 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Sensitive bandwidth */
+# define DMAC_QOSCTRL_WRBQOS_MEDIUM (2 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Sensitive latency */
+# define DMAC_QOSCTRL_WRBQOS_HIGH (3 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Critical latency */
+#define DMAC_QOSCTRL_FQOS_SHIFT (2) /* Bits 2-3: Fetch quality of service */
+#define DMAC_QOSCTRL_FQOS_MASK (3 << DMAC_QOSCTRL_FQOS_SHIFT)
+# define DMAC_QOSCTRL_FQOS_DISABLE (0 << DMAC_QOSCTRL_FQOS_SHIFT) /* Background */
+# define DMAC_QOSCTRL_FQOS_LOW (1 << DMAC_QOSCTRL_FQOS_SHIFT) /* Sensitive bandwidth */
+# define DMAC_QOSCTRL_FQOS_MEDIUM (2 << DMAC_QOSCTRL_FQOS_SHIFT) /* Sensitive latency */
+# define DMAC_QOSCTRL_FQOS_HIGH (3 << DMAC_QOSCTRL_FQOS_SHIFT) /* Critical latency */
+#define DMAC_QOSCTRL_DQOS_SHIFT (4) /* Bits 4-5: Data transfer quality of service */
+#define DMAC_QOSCTRL_DQOS_MASK (3 << DMAC_QOSCTRL_DQOS_SHIFT)
+# define DMAC_QOSCTRL_DQOS_DISABLE (0 << DMAC_QOSCTRL_DQOS_SHIFT) /* Background */
+# define DMAC_QOSCTRL_DQOS_LOW (1 << DMAC_QOSCTRL_DQOS_SHIFT) /* Sensitive bandwidth */
+# define DMAC_QOSCTRL_DQOS_MEDIUM (2 << DMAC_QOSCTRL_DQOS_SHIFT) /* Sensitive latency */
+# define DMAC_QOSCTRL_DQOS_HIGH (3 << DMAC_QOSCTRL_DQOS_SHIFT) /* Critical latency */
+
+/* Common bit definitions for: Software Trigger Control Register, Interrupt Status Register,
+ * Busy Channels Register, and Pending Channels Register
+ */
+
+#define DMAC_CHAN(n) (1 << (n)) /* DMAC Channel n, n=0-11 */
+
+/* Priority Control 0 Register */
+
+#define DMAC_PRICTRL0_LVLPRI0_SHIFT (0) /* Bits 0-3: Level 0 channel priority number */
+#define DMAC_PRICTRL0_LVLPRI0_MASK (15 << DMAC_PRICTRL0_LVLPRI0_SHIFT)
+# define DMAC_PRICTRL0_LVLPRI0(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI0_SHIFT)
+#define DMAC_PRICTRL0_RRLVLEN0 (1 << 7) /* Bit 7: Level 0 round-robin arbitrarion enable */
+#define DMAC_PRICTRL0_LVLPRI1_SHIFT (8) /* Bits 8-11: Level 1 channel priority number */
+#define DMAC_PRICTRL0_LVLPRI1_MASK (15 << DMAC_PRICTRL0_LVLPRI1_SHIFT)
+# define DMAC_PRICTRL0_LVLPRI1(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI1_SHIFT)
+#define DMAC_PRICTRL0_RRLVLEN1 (1 << 15) /* Bit 15: Level 1 round-robin arbitrarion enable */
+#define DMAC_PRICTRL0_LVLPRI2_SHIFT (16) /* Bits 16-18: Level 2 channel priority number */
+#define DMAC_PRICTRL0_LVLPRI2_MASK (7 << DMAC_PRICTRL0_LVLPRI2_SHIFT)
+# define DMAC_PRICTRL0_LVLPRI2(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI2_SHIFT)
+#define DMAC_PRICTRL0_RRLVLEN2 (1 << 23) /* Bit 23: Level 2 round-robin arbitrarion enable */
+#define DMAC_PRICTRL0_LVLPRI3_SHIFT (24) /* Bits 24-27: Level 3 channel priority number */
+#define DMAC_PRICTRL0_LVLPRI3_MASK (7 << DMAC_PRICTRL0_LVLPRI3_SHIFT)
+# define DMAC_PRICTRL0_LVLPRI3(n) ((uint32_t)(n) << DMAC_PRICTRL0_LVLPRI3_SHIFT)
+#define DMAC_PRICTRL0_RRLVLEN3 (1 << 31) /* Bit 23: Level 3 round-robin arbitrarion enable */
+
+/* Interrupt Pending Register */
+
+#define DMAC_INTPEND_ID_SHIFT (0) /* Bit 0-3: Channel ID */
+#define DMAC_INTPEND_ID_MASK (15 << DMAC_INTPEND_ID_SHIFT)
+#define DMAC_INTPEND_TERR (1 << 8) /* Bit 8: Transfer error */
+#define DMAC_INTPEND_TCMPL (1 << 9) /* Bit 9: Transfer complete */
+#define DMAC_INTPEND_SUSP (1 << 10) /* Bit 10: Channel suspend */
+#define DMAC_INTPEND_FERR (1 << 13) /* Bit 13: Fetch error */
+#define DMAC_INTPEND_BUSY (1 << 14) /* Bit 14: Busy */
+#define DMAC_INTPEND_PEND (1 << 15) /* Bit 15: Pending */
+
+/* Interrupt Status Register */
+/* Busy Channels Register */
+/* Pending Channels Register */
+
+/* Active Channels and Levels Register */
+
+#define DMAC_ACTIVE_LVLEX0 (1 << 0) /* Bit 0: Level 0 channel trigger request executing */
+#define DMAC_ACTIVE_LVLEX1 (1 << 1) /* Bit 1: Level 1 channel trigger request executing */
+#define DMAC_ACTIVE_LVLEX2 (1 << 2) /* Bit 2: Level 2 channel trigger request executing */
+#define DMAC_ACTIVE_LVLEX3 (1 << 3) /* Bit 3: Level 3 channel trigger request executing */
+#define DMAC_ACTIVE_ID_SHIFT (8) /* Bits 8-11: Active channel ID */
+#define DMAC_ACTIVE_ID_MASK (15 << DMAC_ACTIVE_ID_SHIFT)
+#define DMAC_ACTIVE_ABUSY (1 << 15) /* Bit 15: Active channel busy */
+#define DMAC_ACTIVE_BTCNT_SHIFT (16) /* Bit 16-31: Active channel block transfer count */
+#define DMAC_ACTIVE_BTCNT_MASK (0xffff << DMAC_ACTIVE_BTCNT_SHIFT)
+
+/* Descriptor Memory Section Base Address Register (32-bit address) */
+/* Write-Back Memory Section Base Address Register (31-bit address) */
+
+/* Channel ID Register */
+
+#define DMAC_CHID_MASK 0x0f /* Bits 0-3: Channel ID */
+
+/* Channel Control A Register */
+
+#define DMAC_CHCTRLA_SWRST (1 << 0) /* Bit 0: Channel software reset */
+#define DMAC_CHCTRLA_ENABLE (1 << 1) /* Bit 1: Channel enable */
+
+/* Channel Control B Register */
+
+#define DMAC_CHCTRLB_EVACT_SHIFT (0) /* Bits 0-2: Event input action */
+#define DMAC_CHCTRLB_EVACT_MASK (7 << DMAC_CHCTRLB_EVACT_SHIFT)
+# define DMAC_CHCTRLB_EVACT_NOACT (0 << DMAC_CHCTRLB_EVACT_SHIFT) /* No action */
+# define DMAC_CHCTRLB_EVACT_TRIG (1 << DMAC_CHCTRLB_EVACT_SHIFT) /* Normal Transfer and Conditional Transfer on Strobe
+trigger */
+# define DMAC_CHCTRLB_EVACT_CTRIG (2 << DMAC_CHCTRLB_EVACT_SHIFT) /* Conditional transfer trigger */
+# define DMAC_CHCTRLB_EVACT_CBLOCK (3 << DMAC_CHCTRLB_EVACT_SHIFT) /* Conditional block transfer */
+# define DMAC_CHCTRLB_EVACT_SUSPEND (4 << DMAC_CHCTRLB_EVACT_SHIFT) /* Channel suspend operation */
+# define DMAC_CHCTRLB_EVACT_RESUME (5 << DMAC_CHCTRLB_EVACT_SHIFT) /* Channel resume operation */
+# define DMAC_CHCTRLB_EVACT_SSKIP (6 << DMAC_CHCTRLB_EVACT_SHIFT) /* Skip next block suspend action */
+#define DMAC_CHCTRLB_EVIE (1 << 3) /* Bit 3: Channel event input enable */
+#define DMAC_CHCTRLB_EVOE (1 << 4) /* Bit 4: Channel event output enable */
+#define DMAC_CHCTRLB_LVL_SHIFT (5) /* Bits 5-6: Channel arbitration level */
+#define DMAC_CHCTRLB_LVL_MASK (3 << DMAC_CHCTRLB_LVL_SHIFT)
+# define DMAC_CHCTRLB_LVL(n) ((uint32_t)(n) << DMAC_CHCTRLB_LVL_SHIFT)
+# define DMAC_CHCTRLB_LVL_LVL0 (0 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 0 */
+# define DMAC_CHCTRLB_LVL_LVL1 (1 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 1 */
+# define DMAC_CHCTRLB_LVL_LVL2 (2 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 2 */
+# define DMAC_CHCTRLB_LVL_LVL3 (3 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 3 */
+#define DMAC_CHCTRLB_TRIGSRC_SHIFT (8) /* Bits 8-13: Trigger source */
+#define DMAC_CHCTRLB_TRIGSRC_MASK (0x3f << DMAC_CHCTRLB_TRIGSRC_SHIFT)
+ #define DMAC_CHCTRLB_TRIGSRC(n) ((uint32_t)(n) << DMAC_CHCTRLB_TRIGSRC_SHIFT)
+#define DMAC_CHCTRLB_TRIGACT_SHIFT (22) /* Bits 22-23: Trigger action */
+#define DMAC_CHCTRLB_TRIGACT_MASK (3 << DMAC_CHCTRLB_TRIGACT_SHIFT)
+# define DMAC_CHCTRLB_TRIGACT_BLOCK (0 << DMAC_CHCTRLB_TRIGACT_SHIFT) /* One trigger required for each action */
+# define DMAC_CHCTRLB_TRIGACT_BEAT (2 << DMAC_CHCTRLB_TRIGACT_SHIFT) /* One trigger required for beat transfer */
+# define DMAC_CHCTRLB_TRIGACT_TRANSACT (3 << DMAC_CHCTRLB_TRIGACT_SHIFT) /* One trigger required for each transaction */
+#define DMAC_CHCTRLB_CMD_SHIFT (24) /* Bits 24-25: Software command */
+#define DMAC_CHCTRLB_CMD_MASK (3 << DMAC_CHCTRLB_CMD_SHIFT)
+# define DMAC_CHCTRLB_CMD_NOACTION (0 << DMAC_CHCTRLB_CMD_SHIFT) /* No action */
+# define DMAC_CHCTRLB_CMD_SUSPEND (1 << DMAC_CHCTRLB_CMD_SHIFT) /* Channel suspend operation */
+# define DMAC_CHCTRLB_CMD_RESUME (2 << DMAC_CHCTRLB_CMD_SHIFT) /* Channel resume operation */
+
+/* Values for use with the DMAC_CHCTRLB_TRIGSRC(n) macro: */
+
+#define DMAC_TRIGSRC_DISABLE (0) /* Only software/event triggers */
+#define DMAC_TRIGSRC_SERCOM0_RX (1) /* SERCOM0 RX Trigger */
+#define DMAC_TRIGSRC_SERCOM0_TX (2) /* SERCOM0 TX Trigger */
+#define DMAC_TRIGSRC_SERCOM1_RX (3) /* SERCOM1 RX Trigger */
+#define DMAC_TRIGSRC_SERCOM1_TX (4) /* SERCOM1 TX Trigger */
+#define DMAC_TRIGSRC_SERCOM2_RX (5) /* SERCOM2 RX Trigger */
+#define DMAC_TRIGSRC_SERCOM2_TX (6) /* SERCOM2 TX Trigger */
+#define DMAC_TRIGSRC_SERCOM3_RX (7) /* SERCOM3 RX Trigger */
+#define DMAC_TRIGSRC_SERCOM3_TX (8) /* SERCOM3 TX Trigger */
+#define DMAC_TRIGSRC_SERCOM4_RX (9) /* SERCOM4 RX Trigger */
+#define DMAC_TRIGSRC_SERCOM4_TX (10) /* SERCOM4 TX Trigger */
+#define DMAC_TRIGSRC_SERCOM5_RX (11) /* SERCOM4 RX Trigger */
+#define DMAC_TRIGSRC_SERCOM5_TX (12) /* SERCOM4 TX Trigger */
+#define DMAC_TRIGSRC_TCC0_OVF (13) /* TCC0 Overflow Trigger */
+#define DMAC_TRIGSRC_TCC0_MC0 (14) /* TCC0 Match/Compare 0 Trigger */
+#define DMAC_TRIGSRC_TCC0_MC1 (15) /* TCC0 Match/Compare 1 Trigger */
+#define DMAC_TRIGSRC_TCC0_MC2 (16) /* TCC0 Match/Compare 2 Trigger */
+#define DMAC_TRIGSRC_TCC0_MC3 (17) /* TCC0 Match/Compare 3 Trigger */
+#define DMAC_TRIGSRC_TCC1_OVF (18) /* TCC1 Overflow Trigger */
+#define DMAC_TRIGSRC_TCC1_MC0 (19) /* TCC1 Match/Compare 0 Trigger */
+#define DMAC_TRIGSRC_TCC1_MC1 (20) /* TCC1 Match/Compare 1 Trigger */
+#define DMAC_TRIGSRC_TCC2_OVF (21) /* TCC2 Overflow Trigger */
+#define DMAC_TRIGSRC_TCC2_MC0 (22) /* TCC2 Match/Compare 0 Trigger */
+#define DMAC_TRIGSRC_TCC2_MC1 (23) /* TCC2 Match/Compare 1 Trigger */
+#define DMAC_TRIGSRC_TC0_OVF (24) /* TC0 Overflow Trigger */
+#define DMAC_TRIGSRC_TC0_MC0 (25) /* TC0 Match/Compare 0 Trigger */
+#define DMAC_TRIGSRC_TC0 MC1 (26) /* TC0 Match/Compare 1 Trigger */
+#define DMAC_TRIGSRC_TC1_OVF (27) /* TC1 Overflow Trigger */
+#define DMAC_TRIGSRC_TC1_MC0 (28) /* TC1 Match/Compare 0 Trigger */
+#define DMAC_TRIGSRC_TC1_MC1 (29) /* TC1 Match/Compare 1 Trigger */
+#define DMAC_TRIGSRC_TC2_OVF (30) /* TC2 Overflow Trigger */
+#define DMAC_TRIGSRC_TC2_MC0 (31) /* TC2 Match/Compare 0 Trigger */
+#define DMAC_TRIGSRC_TC2_MC1 (32) /* TC2 Match/Compare 1 Trigger */
+#define DMAC_TRIGSRC_TC3_OVF (33) /* TC3 Overflow Trigger */
+#define DMAC_TRIGSRC_TC3_MC0 (34) /* TC3 Match/Compare 0 Trigger */
+#define DMAC_TRIGSRC_TC3_MC1 (35) /* TC3 Match/Compare 1 Trigger */
+#define DMAC_TRIGSRC_TC4_OVF (36) /* TC4 Overflow Trigger */
+#define DMAC_TRIGSRC_TC4_MC0 (37) /* TC4 Match/Compare 0 Trigger */
+#define DMAC_TRIGSRC_TC4_MC1 (38) /* TC4 Match/Compare 1 Trigger */
+#define DMAC_TRIGSRC_ADC_RESRDY (39) /* ADC Result Ready Trigger */
+#define DMAC_TRIGSRC_DAC_EMPTY (40) /* DAC0 Empty Trigger */
+#define DMAC_TRIGSRC_I2S0_RX (41) /* I2S0 RX Trigger */
+#define DMAC_TRIGSRC_I2S1_RX (42) /* I2S1 RX Trigger */
+#define DMAC_TRIGSRC_I2S0_TX (43) /* I2S0 TX Trigger */
+#define DMAC_TRIGSRC_I2S1_TX (44) /* I2S1 TX Trigger */
+
+/* Common register bit definitions: Channel Interrupt Enable Clear Register, Channel Interrupt
+ * Enable Set Register, and Channel Interrupt Flag Status and Clear Register
+ */
+
+#define DMAC_INT_TERR (1 << 0) /* Bit 0: Transfer error interrupt */
+#define DMAC_INT_TCMPL (1 << 1) /* Bit 1: Channel transfer complete interrupt */
+#define DMAC_INT_SUSP (1 << 2) /* Bit 2: Channel suspend interrupt */
+#define DMAC_INT_ALL (0x07)
+
+/* Channel Status Register */
+
+#define DMAC_CHSTATUS_PEND (1 << 0) /* Bit 0: Chennel pending */
+#define DMAC_CHSTATUS_BUSY (1 << 1) /* Bit 1: Channel busy */
+#define DMAC_CHSTATUS_FERR (1 << 2) /* Bit 2: Channel fetch error */
+
+/* Block Transfer Control Register */
+
+#define LPSRAM_BTCTRL_VALID (1 << 0) /* Bit 0: Descriptor valid */
+#define LPSRAM_BTCTRL_EVOSEL_SHIFT (1) /* Bits 1-2: Event output selection */
+#define LPSRAM_BTCTRL_EVOSEL_MASK (3 << LPSRAM_BTCTRL_EVOSEL_SHIFT)
+# define LPSRAM_BTCTRL_EVOSEL_DISABLE (0 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event generation disabled */
+# define LPSRAM_BTCTRL_EVOSEL_BLOCK (1 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event strobe when block transfer complete */
+# define LPSRAM_BTCTRL_EVOSEL_BEAT (3 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event strobe when beat transfer complete */
+#define LPSRAM_BTCTRL_BLOCKACT_SHIFT (3) /* Bits 3-4: Block action */
+#define LPSRAM_BTCTRL_BLOCKACT_MASK (3 << LPSRAM_BTCTRL_BLOCKACT_SHIFT)
+# define LPSRAM_BTCTRL_BLOCKACT_NOACT (0 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel disabled if last block transfer */
+# define LPSRAM_BTCTRL_BLOCKACT_INT (1 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel disabled if last block transfer + block int */
+# define LPSRAM_BTCTRL_BLOCKACT_SUSPEND (2 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel suspend operation is completed */
+# define LPSRAM_BTCTRL_BLOCKACT_BOTH (3 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Both channel suspend operation + block int */
+#define LPSRAM_BTCTRL_BEATSIZE_SHIFT (8) /* Bits 8-9: Beat size */
+#define LPSRAM_BTCTRL_BEATSIZE_MASK (3 << LPSRAM_BTCTRL_BEATSIZE_SHIFT)
+# define LPSRAM_BTCTRL_BEATSIZE_BYTE (0 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 8-bit bus transfer */
+# define LPSRAM_BTCTRL_BEATSIZE_HWORD (1 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 16-bit bus transfer */
+# define LPSRAM_BTCTRL_BEATSIZE_WORD (2 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 32-bit bus transfer */
+#define LPSRAM_BTCTRL_SRCINC (1 << 10) /* Bit 10: Source address increment enable */
+#define LPSRAM_BTCTRL_DSTINC (1 << 11) /* Bit 11: Destination address increment enable */
+#define LPSRAM_BTCTRL_STEPSEL (1 << 12) /* Bit 12: Step selection */
+#define LPSRAM_BTCTRL_STEPSIZE_SHIFT (13) /* Bits 13-15: Address increment step */
+#define LPSRAM_BTCTRL_STEPSIZE_MASK (7 << LPSRAM_BTCTRL_STEPSIZE_SHIFT)
+# define LPSRAM_BTCTRL_STEPSIZE_X1 (0 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 1 */
+# define LPSRAM_BTCTRL_STEPSIZE_X2 (1 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 2 */
+# define LPSRAM_BTCTRL_STEPSIZE_X4 (2 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 4 */
+# define LPSRAM_BTCTRL_STEPSIZE_X8 (3 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 8 */
+# define LPSRAM_BTCTRL_STEPSIZE_X16 (4 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 16 */
+# define LPSRAM_BTCTRL_STEPSIZE_X32 (5 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 32 */
+# define LPSRAM_BTCTRL_STEPSIZE_X64 (6 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 64 */
+# define LPSRAM_BTCTRL_STEPSIZE_X128 (7 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 128 */
+
+/* Block Transfer Count Register (16-bit count) */
+/* Block Transfer Source Address Register (32-bit address) */
+/* Block Transfer Destination Address Register (32-bit address) */
+/* Next Address Descriptor Register (32-bit address) */
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+/* DMA descriptor */
+
+struct dma_desc_s
+{
+ uint16_t btctrl; /* Block Transfer Control Register */
+ uint16_t btcnt; /* Block Transfer Count Register */
+ uint32_t srcaddr; /* Block Transfer Source Address Register */
+ uint32_t dstaddr; /* Block Transfer Destination Address Register */
+ uint32_t descaddr; /* Next Address Descriptor Register */
+};
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_DMAC_H */
diff --git a/arch/arm/src/samdl/chip/samd_eic.h b/arch/arm/src/samdl/chip/samd_eic.h
new file mode 100644
index 0000000000000000000000000000000000000000..adc898212446e94557199fd26bbcc984556d3058
--- /dev/null
+++ b/arch/arm/src/samdl/chip/samd_eic.h
@@ -0,0 +1,190 @@
+/********************************************************************************************
+ * arch/arm/src/samdl/chip/samd_eic.h
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ * Matt Thompson
+ *
+ * References:
+ * "Microchip SAMD21 datasheet"
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_EIC_H
+#define __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_EIC_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+#ifdef CONFIG_ARCH_FAMILY_SAMD21
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+/* EIC register offsets *********************************************************************/
+
+#define SAM_EIC_CTRLA_OFFSET 0x0000 /* Control A register */
+#define SAM_EIC_STATUS_OFFSET 0x0001 /* Status register */
+#define SAM_EIC_NMICTRL_OFFSET 0x0002 /* Non-maskable interrupt control register */
+#define SAM_EIC_NMIFLAG_OFFSET 0x0003 /* Non-maskable interrupt flag register */
+#define SAM_EIC_EVCTRL_OFFSET 0x0004 /* Event control register */
+#define SAM_EIC_INTENCLR_OFFSET 0x0008 /* Interrupt enable clear register */
+#define SAM_EIC_INTENSET_OFFSET 0x000c /* Interrupt enable set register */
+#define SAM_EIC_INTFLAG_OFFSET 0x0010 /* Interrupt flag and status clear register */
+#define SAM_EIC_WAKEUP_OFFSET 0x0014 /* Wakeup register */
+#define SAM_EIC_CONFIG0_OFFSET 0x0018 /* Configuration 0 register */
+#define SAM_EIC_CONFIG1_OFFSET 0x001c /* Configuration 1 register */
+#define SAM_EIC_CONFIG2_OFFSET 0x0020 /* Configuration 2 register */
+
+/* EIC register addresses *******************************************************************/
+
+#define SAM_EIC_CTRLA (SAM_EIC_BASE+SAM_EIC_CTRLA_OFFSET)
+#define SAM_EIC_STATUS (SAM_EIC_BASE+SAM_EIC_STATUS_OFFSET)
+#define SAM_EIC_NMICTRL (SAM_EIC_BASE+SAM_EIC_NMICTRL_OFFSET)
+#define SAM_EIC_NMIFLAG (SAM_EIC_BASE+SAM_EIC_NMIFLAG_OFFSET)
+#define SAM_EIC_EVCTRL (SAM_EIC_BASE+SAM_EIC_EVCTRL_OFFSET)
+#define SAM_EIC_INTENCLR (SAM_EIC_BASE+SAM_EIC_INTENCLR_OFFSET)
+#define SAM_EIC_INTENSET (SAM_EIC_BASE+SAM_EIC_INTENSET_OFFSET)
+#define SAM_EIC_INTFLAG (SAM_EIC_BASE+SAM_EIC_INTFLAG_OFFSET)
+#define SAM_EIC_WAKEUP (SAM_EIC_BASE+SAM_EIC_WAKEUP_OFFSET)
+#define SAM_EIC_CONFIG0 (SAM_EIC_BASE+SAM_EIC_CONFIG0_OFFSET)
+#define SAM_EIC_CONFIG1 (SAM_EIC_BASE+SAM_EIC_CONFIG1_OFFSET)
+#define SAM_EIC_CONFIG2 (SAM_EIC_BASE+SAM_EIC_CONFIG2_OFFSET)
+
+/* EIC register bit definitions *************************************************************/
+
+/* Control A register */
+
+#define EIC_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
+#define EIC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
+
+/* Status register */
+
+#define EIC_STATUS_SYNCBUSY (1 << 7) /* Bit 7: Syncronization busy */
+
+/* Non-maskable interrupt control register */
+
+#define EIC_NMICTRL_NMISENSE_SHIFT (0) /* Bits 0-2: Non-maskable interrupt sense */
+#define EIC_NMICTRL_NMISENSE_MASK (7 << EIC_NVMICTRL_NMISENSE_SHIFT)
+# define EIC_NMICTRL_NMISENSE_NONE (0 << EIC_NVMICTRL_NMISENSE_SHIFT) /* No detection */
+# define EIC_NMICTRL_NMISENSE_RISE (1 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Rising edge detection */
+# define EIC_NMICTRL_NMISENSE_FALL (2 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Falling edge detection */
+# define EIC_NMICTRL_NMISENSE_BOTH (3 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Both edge detection */
+# define EIC_NMICTRL_NMISENSE_HIGH (4 << EIC_NVMICTRL_NMISENSE_SHIFT) /* High level detection */
+# define EIC_NMICTRL_NMISENSE_LOW (5 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Low level detection */
+#define EIC_NMICTRL_NMIFLTEN (1 << 3) /* Bit 3: Non-maskable interrupt filter enable */
+
+/* Non-maskable interrupt flas status and clear register */
+
+#define EIC_NMIFLAG_NMI (1 << 0) /* Non-maskable interrupt */
+
+/* Event control, Interrupt enable clear, interrupt enable set register, interrupt flag
+ * status and clear, and external interrupt wakeup registers.
+ */
+
+#define EIC_EXTINT_SHIFT (0) /* Bits 0-15: External interrupt n */
+#define EIC_EXTINT_MASK (0x3ffff << EIC_EXTINT_SHIFT)
+# define EIC_EXTINT(n) (1 << (n))
+# define EIC_EXTINT_0 (1 << 0) /* Bit 0: External interrupt 0 */
+# define EIC_EXTINT_1 (1 << 1) /* Bit 1: External interrupt 1 */
+# define EIC_EXTINT_2 (1 << 2) /* Bit 2: External interrupt 2 */
+# define EIC_EXTINT_3 (1 << 3) /* Bit 3: External interrupt 3 */
+# define EIC_EXTINT_4 (1 << 4) /* Bit 4: External interrupt 4 */
+# define EIC_EXTINT_5 (1 << 5) /* Bit 5: External interrupt 5 */
+# define EIC_EXTINT_6 (1 << 6) /* Bit 6: External interrupt 6 */
+# define EIC_EXTINT_7 (1 << 7) /* Bit 7: External interrupt 7 */
+# define EIC_EXTINT_8 (1 << 8) /* Bit 8: External interrupt 8 */
+# define EIC_EXTINT_9 (1 << 9) /* Bit 9: External interrupt 9 */
+# define EIC_EXTINT_10 (1 << 10) /* Bit 10: External interrupt 10 */
+# define EIC_EXTINT_11 (1 << 11) /* Bit 11: External interrupt 11 */
+# define EIC_EXTINT_12 (1 << 12) /* Bit 12: External interrupt 12 */
+# define EIC_EXTINT_13 (1 << 13) /* Bit 13: External interrupt 13 */
+# define EIC_EXTINT_14 (1 << 14) /* Bit 14: External interrupt 14 */
+# define EIC_EXTINT_15 (1 << 15) /* Bit 15: External interrupt 15 */
+# define EIC_EXTINT_16 (1 << 16) /* Bit 16: External interrupt 16 */
+# define EIC_EXTINT_17 (1 << 17) /* Bit 17: External interrupt 17 */
+
+#define EIC_EXTINT_ALL EIC_EXTINT_MASK
+
+/* Configuration 0 register */
+
+#define EIC_CONFIG0_FILTEN(n) (0x8 << ((n) << 2)) /* Filter n enable, n=0-7 */
+#define EIC_CONFIG0_SENSE_SHIFT(n) ((n) << 2) /* Filter n input sense, n=0-7 */
+#define EIC_CONFIG0_SENSE_MASK(n) (7 << EIC_CONFIG0_SENSE_SHIFT(n))
+# define EIC_CONFIG0_SENSE_NONE(n) (0 << EIC_CONFIG0_SENSE_SHIFT(n)) /* No detection */
+# define EIC_CONFIG0_SENSE_RISE(n) (1 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Rising edge detection */
+# define EIC_CONFIG0_SENSE_FALL(n) (2 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Falling edge detection */
+# define EIC_CONFIG0_SENSE_BOTH(n) (3 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Both edge detection */
+# define EIC_CONFIG0_SENSE_HIGH(n) (4 << EIC_CONFIG0_SENSE_SHIFT(n)) /* High level detection */
+# define EIC_CONFIG0_SENSE_LOW(n) (5 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Low level detection */
+
+/* Configuration 1 register */
+
+#define EIC_CONFIG1_FILTEN(n) (0x8 << (((n) - 8) << 2)) /* Filter n enable, n=8-15 */
+#define EIC_CONFIG1_SENSE_SHIFT(n) (((n) - 8) << 2) /* Filter n input sense, n=8-17 */
+#define EIC_CONFIG1_SENSE_MASK(n) (7 << EIC_CONFIG1_SENSE_SHIFT(n))
+# define EIC_CONFIG1_SENSE_NONE(n) (0 << EIC_CONFIG1_SENSE_SHIFT(n)) /* No detection */
+# define EIC_CONFIG1_SENSE_RISE(n) (1 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Rising edge detection */
+# define EIC_CONFIG1_SENSE_FALL(n) (2 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Falling edge detection */
+# define EIC_CONFIG1_SENSE_BOTH(n) (3 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Both edge detection */
+# define EIC_CONFIG1_SENSE_HIGH(n) (4 << EIC_CONFIG1_SENSE_SHIFT(n)) /* High level detection */
+# define EIC_CONFIG1_SENSE_LOW(n) (5 << EIC_CONFIG1_SENSE_SHIFT(n)) /* Low level detection */
+
+/* Configuration 2 register */
+
+#define EIC_CONFIG2_FILTEN(n) (0x8 << (((n) - 16) << 2)) /* Filter n enable, n=16-23 */
+#define EIC_CONFIG2_SENSE_SHIFT(n) (((n) - 16) << 2) /* Filter n input sense, n=16-23 */
+#define EIC_CONFIG2_SENSE_MASK(n) (7 << EIC_CONFIG2_SENSE_SHIFT(n))
+# define EIC_CONFIG2_SENSE_NONE(n) (0 << EIC_CONFIG2_SENSE_SHIFT(n)) /* No detection */
+# define EIC_CONFIG2_SENSE_RISE(n) (1 << EIC_CONFIG2_SENSE_SHIFT(n)) /* Rising edge detection */
+# define EIC_CONFIG2_SENSE_FALL(n) (2 << EIC_CONFIG2_SENSE_SHIFT(n)) /* Falling edge detection */
+# define EIC_CONFIG2_SENSE_BOTH(n) (3 << EIC_CONFIG2_SENSE_SHIFT(n)) /* Both edge detection */
+# define EIC_CONFIG2_SENSE_HIGH(n) (4 << EIC_CONFIG2_SENSE_SHIFT(n)) /* High level detection */
+# define EIC_CONFIG2_SENSE_LOW(n) (5 << EIC_CONFIG2_SENSE_SHIFT(n)) /* Low level detection */
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
+#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_EIC_H */
diff --git a/arch/arm/src/samdl/chip/samd_evsys.h b/arch/arm/src/samdl/chip/samd_evsys.h
index e1489a2622b62554fcc9f5b13ba6c446c0702f3e..84ea384f09294516cf1147c5237829a8da347697 100644
--- a/arch/arm/src/samdl/chip/samd_evsys.h
+++ b/arch/arm/src/samdl/chip/samd_evsys.h
@@ -68,9 +68,9 @@
#define SAM_EVSYS_CTRL (SAM_EVSYS_BASE+SAM_EVSYS_CTRL_OFFSET)
#define SAM_EVSYS_CHANNEL (SAM_EVSYS_BASE+SAM_EVSYS_CHANNEL_OFFSET)
#define SAM_EVSYS_USER (SAM_EVSYS_BASE+SAM_EVSYS_USER_OFFSET)
-#define SAM_EVSYS_CHSTATUS (SAM_EVSYS_BASE+SAM_EVSYS_CHSTATUS_OFFSET
-#define SAM_EVSYS_INTENCLR (SAM_EVSYS_BASE+SAM_EVSYS_INTENCLR_OFFSET
-#define SAM_EVSYS_INTENSET (SAM_EVSYS_BASE+SAM_EVSYS_INTENSET_OFFSET
+#define SAM_EVSYS_CHSTATUS (SAM_EVSYS_BASE+SAM_EVSYS_CHSTATUS_OFFSET)
+#define SAM_EVSYS_INTENCLR (SAM_EVSYS_BASE+SAM_EVSYS_INTENCLR_OFFSET)
+#define SAM_EVSYS_INTENSET (SAM_EVSYS_BASE+SAM_EVSYS_INTENSET_OFFSET)
#define SAM_EVSYS_INTFLAG (SAM_EVSYS_BASE+SAM_EVSYS_INTFLAG_OFFSET)
/* EVSYS register bit definitions ***********************************************************/
@@ -302,12 +302,14 @@
/* Channel status register */
-#define EVSYS_CHSTATUS_USRRDY_SHIFT (0) /* Bits 0-7: User Ready for Channel n, n=0-7 */
-#define EVSYS_CHSTATUS_USRRDY_MASK (0xff << EVSYS_CHSTATUS_USRRDY_SHIFT)
-# define EVSYS_CHSTATUS_USRRDY(n) (1 << (n))
-#define EVSYS_CHSTATUS_CHBUSY_SHIFT (8) /* Bits 8-15: Channel Busy n, n=0-7 */
-#define EVSYS_CHSTATUS_CHBUSY_MASK (0xff << EVSYS_CHSTATUS_CHBUSY_SHIFT)
-# define EVSYS_CHSTATUS_CHBUSY(n) (1 << ((n) + 8))
+#ifdef CONFIG_ARCH_FAMILY_SAMD20
+# define EVSYS_CHSTATUS_USRRDY_SHIFT (0) /* Bits 0-7: User Ready for Channel n, n=0-7 */
+# define EVSYS_CHSTATUS_USRRDY_MASK (0xff << EVSYS_CHSTATUS_USRRDY_SHIFT)
+# define EVSYS_CHSTATUS_USRRDY(n) (1 << (n))
+# define EVSYS_CHSTATUS_CHBUSY_SHIFT (8) /* Bits 8-15: Channel Busy n, n=0-7 */
+# define EVSYS_CHSTATUS_CHBUSY_MASK (0xff << EVSYS_CHSTATUS_CHBUSY_SHIFT)
+# define EVSYS_CHSTATUS_CHBUSY(n) (1 << ((n) + 8))
+#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define EVSYS_CHSTATUS_USRRDYH_SHIFT (16) /* Bits 16-19: User Ready for Channel n, n=8-11 */
@@ -320,12 +322,14 @@
/* Interrupt enable clear, interrupt enable set, and interrupt flag status and clear registers */
-#define EVSYS_INT_OVR_SHIFT (0) /* Bits 0-7: Overrun channel n interrupt, n=0-7 */
-#define EVSYS_INT_OVR_MASK (0xff << EVSYS_INT_OVR_SHIFT)
-# define EVSYS_INT_OVR(n) (1 << (n))
-#define EVSYS_INT_EVD_SHIFT (8) /* Bits 8-15: Event detected channel n interrupt, n=0-7 */
-#define EVSYS_INT_EVD_MASK (0xff << EVSYS_INT_EVD_SHIFT)
-# define EVSYS_INT_EVD(n) (1 << ((n) + 8))
+#ifdef CONFIG_ARCH_FAMILY_SAMD20
+# define EVSYS_INT_OVR_SHIFT (0) /* Bits 0-7: Overrun channel n interrupt, n=0-7 */
+# define EVSYS_INT_OVR_MASK (0xff << EVSYS_INT_OVR_SHIFT)
+# define EVSYS_INT_OVR(n) (1 << (n))
+# define EVSYS_INT_EVD_SHIFT (8) /* Bits 8-15: Event detected channel n interrupt, n=0-7 */
+# define EVSYS_INT_EVD_MASK (0xff << EVSYS_INT_EVD_SHIFT)
+# define EVSYS_INT_EVD(n) (1 << ((n) + 8))
+#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define EVSYS_INT_OVR_SHIFT (16) /* Bits 16-19: Overrun channel n interrupt, n=8-11 */
diff --git a/arch/arm/src/samdl/chip/samd_gclk.h b/arch/arm/src/samdl/chip/samd_gclk.h
index 5426dc394d3bed1f4e0398f9dde2830393a7d58b..56ec14f2f6e471d191851d99a170fec05c1bc8dd 100644
--- a/arch/arm/src/samdl/chip/samd_gclk.h
+++ b/arch/arm/src/samdl/chip/samd_gclk.h
@@ -158,8 +158,8 @@
# define GCLK_CLKCTRL_ID_ACANA (32 << GCLK_CLKCTRL_ID_SHIFT) /* AC_ANA */
# define GCLK_CLKCTRL_ID_DAC (33 << GCLK_CLKCTRL_ID_SHIFT) /* DAC */
# define GCLK_CLKCTRL_ID_PTC (34 << GCLK_CLKCTRL_ID_SHIFT) /* PTC */
-# define GCLK_CLKCTRL_I2S0_PTC (35 << GCLK_CLKCTRL_ID_SHIFT) /* I2S0 */
-# define GCLK_CLKCTRL_I2S1_PTC (36 << GCLK_CLKCTRL_ID_SHIFT) /* I2S1 */
+# define GCLK_CLKCTRL_ID_I2S0 (35 << GCLK_CLKCTRL_ID_SHIFT) /* I2S0 */
+# define GCLK_CLKCTRL_ID_I2S1 (36 << GCLK_CLKCTRL_ID_SHIFT) /* I2S1 */
#endif
#define GCLK_CLKCTRL_GEN_SHIFT (8) /* Bits 8-11: Generic Clock Generator */
diff --git a/arch/arm/src/samdl/chip/samd_i2s.h b/arch/arm/src/samdl/chip/samd_i2s.h
new file mode 100644
index 0000000000000000000000000000000000000000..87a4cf7daf380c59d8348837268b10add35b6dd9
--- /dev/null
+++ b/arch/arm/src/samdl/chip/samd_i2s.h
@@ -0,0 +1,203 @@
+/********************************************************************************************
+ * arch/arm/src/samdl/chip/samd_i2s.h
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Matt Thompson
+ *
+ * References:
+ * "Microchip SAMD21 datasheet"
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_I2S_H
+#define __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_I2S_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+#ifdef CONFIG_ARCH_FAMILY_SAMD21
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+/* I2S register offsets *********************************************************************/
+
+#define SAM_I2S_CTRLA_OFFSET 0x0000 /* Control A register */
+#define SAM_I2S_CLKCTRL0_OFFSET 0x0004 /* Clock Control 0 register */
+#define SAM_I2S_CLKCTRL1_OFFSET 0x0008 /* Clock Control 1 register */
+#define SAM_I2S_INTENCLR_OFFSET 0x000C /* Interrupt enable clear register */
+#define SAM_I2S_INTENSET_OFFSET 0x0010 /* Interrupt enable set register */
+#define SAM_I2S_INTFLAG_OFFSET 0x0014 /* Interrupt flag register */
+#define SAM_I2S_SYNCBUSY_OFFSET 0x0018 /* Sync Busy register */
+#define SAM_I2S_SERCTRL0_OFFSET 0x0020 /* Serializer 0 Control register */
+#define SAM_I2S_SERCTRL1_OFFSET 0x0024 /* Serializer 1 Control register */
+#define SAM_I2S_DATA0_OFFSET 0x0030 /* Data 0 register */
+#define SAM_I2S_DATA1_OFFSET 0x0034 /* Data 1 register */
+
+/* I2S register addresses ******************************************************************/
+
+#define SAM_I2S_CTRLA (SAM_I2S_BASE+SAM_I2S_CTRLA_OFFSET)
+#define SAM_I2S_CLKCTRL0 (SAM_I2S_BASE+SAM_I2S_CLKCTRL0_OFFSET)
+#define SAM_I2S_CLKCTRL1 (SAM_I2S_BASE+SAM_I2S_CLKCTRL1_OFFSET)
+#define SAM_I2S_INTENCLR (SAM_I2S_BASE+SAM_I2S_INTENCLR_OFFSET)
+#define SAM_I2S_INTENSET (SAM_I2S_BASE+SAM_I2S_INTENSET_OFFSET)
+#define SAM_I2S_INTFLAG (SAM_I2S_BASE+SAM_I2S_INTFLAG_OFFSET)
+#define SAM_I2S_SYNCBUSY (SAM_I2S_BASE+SAM_I2S_SYNCBUSY_OFFSET)
+#define SAM_I2S_SERCTRL0 (SAM_I2S_BASE+SAM_I2S_SERCTRL0_OFFSET)
+#define SAM_I2S_SERCTRL1 (SAM_I2S_BASE+SAM_I2S_SERCTRL1_OFFSET)
+#define SAM_I2S_DATA0 (SAM_I2S_BASE+SAM_I2S_DATA0_OFFSET)
+#define SAM_I2S_DATA1 (SAM_I2S_BASE+SAM_I2S_DATA1_OFFSET)
+
+/* I2S register bit definitions ************************************************************/
+
+/* Control A register */
+
+#define I2S_CTRLA_SWRST (1 << 0) /* Bit 0: Software Reset */
+#define I2S_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
+#define I2S_CTRLA_CKEN0 (1 << 2) /* Bit 2: Clock Unit 0 Enable */
+#define I2S_CTRLA_CKEN1 (1 << 3) /* Bit 3: Clock Unit 1 Enable */
+#define I2S_CTRLA_SEREN0 (1 << 4) /* Bit 4: Serializer 0 Enable */
+#define I2S_CTRLA_SEREN1 (1 << 5) /* Bit 5: Seriailier 1 Enable */
+
+/* Clock Unit Control Register */
+
+#define I2S_CLKCTRL_SLOTSIZE_SHIFT (0) /* Bits [1:0]: Slot Size */
+#define I2S_CLKCTRL_SLOTSIZE_MASK (3 << I2S_CLKCTRL_SLOTSIZE_SHIFT)
+# define I2S_CLKCTRL_SLOTSIZE_8 (0 << I2S_CLKCTRL_SLOTSIZE_SHIFT)
+# define I2S_CLKCTRL_SLOTSIZE_16 (1 << I2S_CLKCTRL_SLOTSIZE_SHIFT)
+# define I2S_CLKCTRL_SLOTSIZE_24 (2 << I2S_CLKCTRL_SLOTSIZE_SHIFT)
+# define I2S_CLKCTRL_SLOTSIZE_32 (3 << I2S_CLKCTRL_SLOTSIZE_SHIFT)
+#define I2S_CLKCTRL_NBSLOTS_SHIFT (2) /* Bit 2: Number of Slots in Frame */
+#define I2S_CLKCTRL_NBSLOTS_MASK (7 << I2S_CLKCTRL_NBSLOTS_SHIFT)
+#define I2S_CLKCTRL_NBSLOTS(n) (((n) & 0x7) << I2S_CLKCTRL_NBSLOTS_SHIFT)
+#define I2S_CLKCTRL_FSWIDTH_SHIFT (5) /* Bits [6:5]: Frame Sync Width */
+#define I2S_CLKCTRL_FSWIDTH_MASK (3 << I2S_CLKCTRL_FSWIDTH_SHIFT)
+# define I2S_CLKCTRL_FSWIDTH_SLOT (0 << I2S_CLKCTRL_FSWIDTH_SHIFT)
+# define I2S_CLKCTRL_FSWIDTH_HALF (1 << I2S_CLKCTRL_FSWIDTH_SHIFT)
+# define I2S_CLKCTRL_FSWIDTH_BIT (2 << I2S_CLKCTRL_FSWIDTH_SHIFT)
+# define I2S_CLKCTRL_FSWIDTH_BURST (3 << I2S_CLKCTRL_FSWIDTH_SHIFT)
+#define I2S_CLKCTRL_BITDELAY (1 << 7) /* Bit 7: Data Delay from Frame Sync */
+#define I2S_CLKCTRL_FSSEL (1 << 8) /* Bit 8: Frame Sync Select */
+#define I2S_CLKCTRL_FSINV (1 << 11) /* Bit 11: Frame Sync Invert */
+#define I2S_CLKCTRL_SCKSEL (1 << 12) /* Bit 12: Serial Clock Select. 0: Divided Master clock, 1: SCKn input pin */
+#define I2S_CLKCTRL_MCKSEL (1 << 16) /* Bit 16: Master Clock Select. 0: GCLK, 1: MCKn input pin */
+#define I2S_CLKCTRL_MCKEN (1 << 18) /* Bit 18: Master Clock Enable */
+#define I2S_CLKCTRL_MCKDIV_SHIFT (19) /* Bits [23:19]: Master Clock Division Factor */
+#define I2S_CLKCTRL_MCKDIV_MASK (0x1f << I2S_CLKCTRL_MCKDIV_SHIFT)
+#define I2S_CLKCTRL_MCKDIV(n) (((n) & 0x1f) << I2S_CLKCTRL_MCKDIV_SHIFT)
+#define I2S_CLKCTRL_MCKOUTDIV_SHIFT (24) /* Bits [28:24]: Master Clock Output Division Factor */
+#define I2S_CLKCTRL_MCKOUTDIV_MASK (0x1f << I2S_CLKCTRL_MCKOUTDIV_SHIFT)
+#define I2S_CLKCTRL_MCKOUTDIV(n) (((n) & 0x1f) << I2S_CLKCTRL_MCKOUTDIV_SHIFT)
+#define I2S_CLKCTRL_FSOUTINV (1 << 29) /* Bit 29: Frame Sync Output Invert */
+#define I2S_CLKCTRL_SCKOUTINV (1 << 30) /* Bit 30: Serial Clock Output Invert */
+#define I2S_CLKCTRL_MCKOUTINV (1 << 31) /* Bit 31: Master Clock Output Invert */
+
+/* Interrupt register bits */
+
+#define I2S_INT_RXRDY0 (1 << 0) /* Bit 0: Receive Ready 0 */
+#define I2S_INT_RXRDY1 (1 << 1) /* Bit 1: Receive Ready 1 */
+#define I2S_INT_RXOR0 (1 << 4) /* Bit 4: Receive Overrun 0 */
+#define I2S_INT_RXOR1 (1 << 5) /* Bit 5: Receive Overrun 1 */
+#define I2S_INT_TXRDY0 (1 << 8) /* Bit 8: Transmit Ready 0 */
+#define I2S_INT_TXRDY1 (1 << 9) /* Bit 9: Transmit Ready 1 */
+#define I2S_INT_TXUR0 (1 << 12) /* Bit 12: Transmit Underrun 0 */
+#define I2S_INT_TXUR1 (1 << 13) /* Bit 13: Transmit Underrun 1 */
+#define I2S_INT_ALL (0x3333)
+
+/* Sync Busy register bits */
+
+#define I2S_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software Reset Sync Status */
+#define I2S_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: Enable Sync Status */
+#define I2S_SYNCBUSY_CKEN0 (1 << 2) /* Bit 2: Clock Unit 0 Sync Status */
+#define I2S_SYNCBUSY_CKEN1 (1 << 3) /* Bit 3: Clock Unit 1 Sync Status */
+#define I2S_SYNCBUSY_SEREN0 (1 << 4) /* Bit 4: Serializer 0 Enable Sync Status */
+#define I2S_SYNCBUSY_SEREN1 (1 << 5) /* Bit 5: Seriaiizer 1 Enable Sync Status */
+#define I2S_SYNCBUSY_DATA0 (1 << 8) /* Bit 8: Data 0 Sync Status */
+#define I2S_SYNCBUSY_DATA1 (1 << 9) /* Bit 9: Data 1 Sync Status */
+
+/* Serializer Control register bits */
+
+#define I2S_SERCTRL_SERMODE_SHIFT (0) /* Bits [1:0]: Seriailizer Mode */
+#define I2S_SERCTRL_SERMODE_MASK (3 << I2S_SERCTRL_SERMODE_SHIFT)
+# define I2S_SERCTRL_SERMODE_RX (0 << I2S_SERCTRL_SERMODE_SHIFT)
+# define I2S_SERCTRL_SERMODE_TX (1 << I2S_SERCTRL_SERMODE_SHIFT)
+# define I2S_SERCTRL_SERMODE_PDM2 (2 << I2S_SERCTRL_SERMODE_SHIFT)
+#define I2S_SERCTRL_TXDEFAULT_SHIFT (2) /* Bits [3:2]: Line Default when Slot Disabled */
+#define I2S_SERCTRL_TXDEFAULT_MASK (3 << I2S_SERCTRL_TXDEFAULT_SHIFT)
+# define I2S_SERCTRL_TXDEFAULT_ZERO (0 << I2S_SERCTRL_TXDEFAULT_SHIFT)
+# define I2S_SERCTRL_TXDEFAULT_ONE (1 << I2S_SERCTRL_TXDEFAULT_SHIFT)
+# define I2S_SERCTRL_TXDEFAULT_HIZ (3 << I2S_SERCTRL_TXDEFAULT_SHIFT)
+#define I2S_SERCTRL_TXSAME (1 << 4) /* Bit 4: Transmit last data when Underrun */
+#define I2S_SERCTRL_CLKSEL (1 << 5) /* Bit 5: Clock Unit Selection. 0: Use Clock 0, 1: Use Clock 1 */
+#define I2S_SERCTRL_SLOTADJ (1 << 7) /* Bit 7: Data slot formatting. 0: Right justified, 1: Left justified */
+#define I2S_SERCTRL_DATASIZE_SHIFT (8) /* Bits [10:8]: Data Word Size */
+#define I2S_SERCTRL_DATASIZE_MASK (7 << I2S_SERCTRL_DATASIZE_SHIFT)
+# define I2S_SERCTRL_DATASIZE_32 (0 << I2S_SERCTRL_DATASIZE_SHIFT)
+# define I2S_SERCTRL_DATASIZE_24 (1 << I2S_SERCTRL_DATASIZE_SHIFT)
+# define I2S_SERCTRL_DATASIZE_20 (2 << I2S_SERCTRL_DATASIZE_SHIFT)
+# define I2S_SERCTRL_DATASIZE_18 (3 << I2S_SERCTRL_DATASIZE_SHIFT)
+# define I2S_SERCTRL_DATASIZE_16 (4 << I2S_SERCTRL_DATASIZE_SHIFT)
+# define I2S_SERCTRL_DATASIZE_16C (5 << I2S_SERCTRL_DATASIZE_SHIFT)
+# define I2S_SERCTRL_DATASIZE_8 (6 << I2S_SERCTRL_DATASIZE_SHIFT)
+# define I2S_SERCTRL_DATASIZE_8C (7 << I2S_SERCTRL_DATASIZE_SHIFT)
+#define I2S_SERCTRL_WORDADJ (1 << 12) /* Bit 12: Data word formatting. 0: Right justified, 1: Left justified */
+#define I2S_SERCTRL_EXTEND_SHIFT (13) /* Bits [14:13]: Data formatting bit extension */
+#define I2S_SERCTRL_EXTEND_MASK (3 << I2S_SERCTRL_EXTEND_SHIFT)
+# define I2S_SERCTRL_EXTEND_ZERO (0 << I2S_SERCTRL_EXTEND_SHIFT)
+# define I2S_SERCTRL_EXTEND_ONE (1 << I2S_SERCTRL_EXTEND_SHIFT)
+# define I2S_SERCTRL_EXTEND_MSBIT (2 << I2S_SERCTRL_EXTEND_SHIFT)
+# define I2S_SERCTRL_EXTEND_LSBIT (3 << I2S_SERCTRL_EXTEND_SHIFT)
+#define I2S_SERCTRL_BITREV (1 << 15) /* Bit 15: Data formatting bit reverse */
+#define I2S_SERCTRL_SLOTDIS_SHIFT (16) /* Bits [23:16]: Slot x Disabled */
+#define I2S_SERCTRL_SLOTDIS_MASK (0xff << I2S_SERCTRL_SLOTDIS_SHIFT)
+#define I2S_SERCTRL_SLOTDIS(n) (((n) & 0xff) << I2C_SERCTRL_SLOTDIS_SHIFT)
+#define I2S_SERCTRL_MONO (1 << 24) /* Bit 24: Mono Mode */
+#define I2S_SERCTRL_DMA (1 << 25) /* Bit 25: Single or Multiple DMA channels */
+#define I2S_SERCTRL_RXLOOP (1 << 26) /* Bit 26: RX Loopback Test Mode */
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
+#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_I2S_H */
diff --git a/arch/arm/src/samdl/chip/samd_pm.h b/arch/arm/src/samdl/chip/samd_pm.h
index 7c3e7f08724ef7fbf8e6ac956e052ecbd7704308..50f8551d31b64159b5caf6e745f4e22aaeb7af98 100644
--- a/arch/arm/src/samdl/chip/samd_pm.h
+++ b/arch/arm/src/samdl/chip/samd_pm.h
@@ -228,7 +228,7 @@
#define PM_APBCMASK_PTC (1 << 19) /* Bit 19: PTC */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
-# define PM_APBBMASK_I2S (1 << 20) /* Bit 20: Inter IC Sound */
+# define PM_APBCMASK_I2S (1 << 20) /* Bit 20: Inter IC Sound */
#endif
/* Interrupt enable clear, Interrupt enable set, and Interrupt flag status and clear registers */
diff --git a/arch/arm/src/samdl/chip/samd_spi.h b/arch/arm/src/samdl/chip/samd_spi.h
index 8bdcc9e21ee2400db743dea1733e997c8ea32c66..b045c32c4077ae6085c605f9b00c1de44046a7dd 100644
--- a/arch/arm/src/samdl/chip/samd_spi.h
+++ b/arch/arm/src/samdl/chip/samd_spi.h
@@ -247,8 +247,8 @@
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD21
-# define SPI_INT_ SSL (1 << 3) /* Bit 3: Slave select low interrupt */
-# define SPI_INT_ ERROR (1 << 7) /* Bit 7: Error interrupt */
+# define SPI_INT_SSL (1 << 3) /* Bit 3: Slave select low interrupt */
+# define SPI_INT_ERROR (1 << 7) /* Bit 7: Error interrupt */
# define SPI_INT_ALL (0x8f)
#endif
diff --git a/arch/arm/src/samdl/chip/samd_tc.h b/arch/arm/src/samdl/chip/samd_tc.h
new file mode 100644
index 0000000000000000000000000000000000000000..fe3d2c40592fc6a51cefff4d7672fba6c1113774
--- /dev/null
+++ b/arch/arm/src/samdl/chip/samd_tc.h
@@ -0,0 +1,254 @@
+/********************************************************************************************
+ * arch/arm/src/samdl/chip/samd_tc.h
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Matt Thompson
+ *
+ * References:
+ * "Microchip SAMD21 datasheet"
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_TC_H
+#define __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_TC_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+#ifdef CONFIG_ARCH_FAMILY_SAMD21
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+/* TC register offsets *********************************************************************/
+
+#define SAM_TC_CTRLA_OFFSET 0x0000 /* Control A register */
+#define SAM_TC_READREQ_OFFSET 0x0002 /* Read request register */
+#define SAM_TC_CTRLBCLR_OFFSET 0x0004 /* Control B clear register */
+#define SAM_TC_CTRLBSET_OFFSET 0x0005 /* Control B clear register */
+#define SAM_TC_CTRLC_OFFSET 0x0006 /* Control C register */
+#define SAM_TC_DBGCTRL_OFFSET 0x0008 /* Debug control register */
+#define SAM_TC_EVCTRL_OFFSET 0x000A /* Event control register */
+#define SAM_TC_INTENCLR_OFFSET 0x000C /* Interrupt enable clear register */
+#define SAM_TC_INTENSET_OFFSET 0x000D /* Interrupt enable set register */
+#define SAM_TC_INTFLAG_OFFSET 0x000E /* Interrupt flag register */
+#define SAM_TC_STATUS_OFFSET 0x000F /* Status register */
+#define SAM_TC_COUNT_OFFSET 0x0010 /* Count register */
+#define SAM_TC_CC0_OFFSET 0x0018 /* Capture Compare 0 register */
+#define SAM_TC_CC1_OFFSET 0x001C /* Capture Compare 1 register */
+
+/* TC register addresses *******************************************************************/
+
+#define SAM_TC3_CTRLA (SAM_TC3_BASE+SAM_TC_CTRLA_OFFSET)
+#define SAM_TC3_READREQ (SAM_TC3_BASE+SAM_TC_READREQ_OFFSET)
+#define SAM_TC3_CTRLBCLR (SAM_TC3_BASE+SAM_TC_CTRLBCLR_OFFSET)
+#define SAM_TC3_CTRLBSET (SAM_TC3_BASE+SAM_TC_CTRLBSET_OFFSET)
+#define SAM_TC3_CTRLC (SAM_TC3_BASE+SAM_TC_CTRLC_OFFSET)
+#define SAM_TC3_DBGCTRL (SAM_TC3_BASE+SAM_TC_DBGCTRL_OFFSET)
+#define SAM_TC3_EVCTRL (SAM_TC3_BASE+SAM_TC_EVCTRL_OFFSET)
+#define SAM_TC3_INTENCLR (SAM_TC3_BASE+SAM_TC_INTENCLR_OFFSET)
+#define SAM_TC3_INTENSET (SAM_TC3_BASE+SAM_TC_INTENSET_OFFSET)
+#define SAM_TC3_INTFLAG (SAM_TC3_BASE+SAM_TC_INTFLAG_OFFSET)
+#define SAM_TC3_STATUS (SAM_TC3_BASE+SAM_TC_STATUS_OFFSET)
+#define SAM_TC3_COUNT (SAM_TC3_BASE+SAM_TC_COUNT_OFFSET)
+#define SAM_TC3_CC0 (SAM_TC3_BASE+SAM_TC_CC0_OFFSET)
+#define SAM_TC3_CC1 (SAM_TC3_BASE+SAM_TC_CC1_OFFSET)
+
+#define SAM_TC4_CTRLA (SAM_TC4_BASE+SAM_TC_CTRLA_OFFSET)
+#define SAM_TC4_READREQ (SAM_TC4_BASE+SAM_TC_READREQ_OFFSET)
+#define SAM_TC4_CTRLBCLR (SAM_TC4_BASE+SAM_TC_CTRLBCLR_OFFSET)
+#define SAM_TC4_CTRLBSET (SAM_TC4_BASE+SAM_TC_CTRLBSET_OFFSET)
+#define SAM_TC4_CTRLC (SAM_TC4_BASE+SAM_TC_CTRLC_OFFSET)
+#define SAM_TC4_DBGCTRL (SAM_TC4_BASE+SAM_TC_DBGCTRL_OFFSET)
+#define SAM_TC4_EVCTRL (SAM_TC4_BASE+SAM_TC_EVCTRL_OFFSET)
+#define SAM_TC4_INTENCLR (SAM_TC4_BASE+SAM_TC_INTENCLR_OFFSET)
+#define SAM_TC4_INTENSET (SAM_TC4_BASE+SAM_TC_INTENSET_OFFSET)
+#define SAM_TC4_INTFLAG (SAM_TC4_BASE+SAM_TC_INTFLAG_OFFSET)
+#define SAM_TC4_STATUS (SAM_TC4_BASE+SAM_TC_STATUS_OFFSET)
+#define SAM_TC4_COUNT (SAM_TC4_BASE+SAM_TC_COUNT_OFFSET)
+#define SAM_TC4_CC0 (SAM_TC4_BASE+SAM_TC_CC0_OFFSET)
+#define SAM_TC4_CC1 (SAM_TC4_BASE+SAM_TC_CC1_OFFSET)
+
+#define SAM_TC5_CTRLA (SAM_TC5_BASE+SAM_TC_CTRLA_OFFSET)
+#define SAM_TC5_READREQ (SAM_TC5_BASE+SAM_TC_READREQ_OFFSET)
+#define SAM_TC5_CTRLBCLR (SAM_TC5_BASE+SAM_TC_CTRLBCLR_OFFSET)
+#define SAM_TC5_CTRLBSET (SAM_TC5_BASE+SAM_TC_CTRLBSET_OFFSET)
+#define SAM_TC5_CTRLC (SAM_TC5_BASE+SAM_TC_CTRLC_OFFSET)
+#define SAM_TC5_DBGCTRL (SAM_TC5_BASE+SAM_TC_DBGCTRL_OFFSET)
+#define SAM_TC5_EVCTRL (SAM_TC5_BASE+SAM_TC_EVCTRL_OFFSET)
+#define SAM_TC5_INTENCLR (SAM_TC5_BASE+SAM_TC_INTENCLR_OFFSET)
+#define SAM_TC5_INTENSET (SAM_TC5_BASE+SAM_TC_INTENSET_OFFSET)
+#define SAM_TC5_INTFLAG (SAM_TC5_BASE+SAM_TC_INTFLAG_OFFSET)
+#define SAM_TC5_STATUS (SAM_TC5_BASE+SAM_TC_STATUS_OFFSET)
+#define SAM_TC5_COUNT (SAM_TC5_BASE+SAM_TC_COUNT_OFFSET)
+#define SAM_TC5_CC0 (SAM_TC5_BASE+SAM_TC_CC0_OFFSET)
+#define SAM_TC5_CC1 (SAM_TC5_BASE+SAM_TC_CC1_OFFSET)
+
+#define SAM_TC6_CTRLA (SAM_TC6_BASE+SAM_TC_CTRLA_OFFSET)
+#define SAM_TC6_READREQ (SAM_TC6_BASE+SAM_TC_READREQ_OFFSET)
+#define SAM_TC6_CTRLBCLR (SAM_TC6_BASE+SAM_TC_CTRLBCLR_OFFSET)
+#define SAM_TC6_CTRLBSET (SAM_TC6_BASE+SAM_TC_CTRLBSET_OFFSET)
+#define SAM_TC6_CTRLC (SAM_TC6_BASE+SAM_TC_CTRLC_OFFSET)
+#define SAM_TC6_DBGCTRL (SAM_TC6_BASE+SAM_TC_DBGCTRL_OFFSET)
+#define SAM_TC6_EVCTRL (SAM_TC6_BASE+SAM_TC_EVCTRL_OFFSET)
+#define SAM_TC6_INTENCLR (SAM_TC6_BASE+SAM_TC_INTENCLR_OFFSET)
+#define SAM_TC6_INTENSET (SAM_TC6_BASE+SAM_TC_INTENSET_OFFSET)
+#define SAM_TC6_INTFLAG (SAM_TC6_BASE+SAM_TC_INTFLAG_OFFSET)
+#define SAM_TC6_STATUS (SAM_TC6_BASE+SAM_TC_STATUS_OFFSET)
+#define SAM_TC6_COUNT (SAM_TC6_BASE+SAM_TC_COUNT_OFFSET)
+#define SAM_TC6_CC0 (SAM_TC6_BASE+SAM_TC_CC0_OFFSET)
+#define SAM_TC6_CC1 (SAM_TC6_BASE+SAM_TC_CC1_OFFSET)
+
+#define SAM_TC7_CTRLA (SAM_TC7_BASE+SAM_TC_CTRLA_OFFSET)
+#define SAM_TC7_READREQ (SAM_TC7_BASE+SAM_TC_READREQ_OFFSET)
+#define SAM_TC7_CTRLBCLR (SAM_TC7_BASE+SAM_TC_CTRLBCLR_OFFSET)
+#define SAM_TC7_CTRLBSET (SAM_TC7_BASE+SAM_TC_CTRLBSET_OFFSET)
+#define SAM_TC7_CTRLC (SAM_TC7_BASE+SAM_TC_CTRLC_OFFSET)
+#define SAM_TC7_DBGCTRL (SAM_TC7_BASE+SAM_TC_DBGCTRL_OFFSET)
+#define SAM_TC7_EVCTRL (SAM_TC7_BASE+SAM_TC_EVCTRL_OFFSET)
+#define SAM_TC7_INTENCLR (SAM_TC7_BASE+SAM_TC_INTENCLR_OFFSET)
+#define SAM_TC7_INTENSET (SAM_TC7_BASE+SAM_TC_INTENSET_OFFSET)
+#define SAM_TC7_INTFLAG (SAM_TC7_BASE+SAM_TC_INTFLAG_OFFSET)
+#define SAM_TC7_STATUS (SAM_TC7_BASE+SAM_TC_STATUS_OFFSET)
+#define SAM_TC7_COUNT (SAM_TC7_BASE+SAM_TC_COUNT_OFFSET)
+#define SAM_TC7_CC0 (SAM_TC7_BASE+SAM_TC_CC0_OFFSET)
+#define SAM_TC7_CC1 (SAM_TC7_BASE+SAM_TC_CC1_OFFSET)
+
+/* TC register bit definitions *************************************************************/
+
+/* Control A register */
+
+#define TC_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
+#define TC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
+#define TC_CTRLA_MODE_SHIFT (2)
+#define TC_CTRLA_MODE_MASK (3 << TC_CTRLA_MODE_SHIFT)
+# define TC_CTRLA_MODE_COUNT16 (0 << TC_CTRLA_MODE_SHIFT)
+# define TC_CTRLA_MODE_COUNT8 (1 << TC_CTRLA_MODE_SHIFT)
+# define TC_CTRLA_MODE_COUNT32 (2 << TC_CTRLA_MODE_SHIFT)
+#define TC_CTRLA_WAVEGEN_SHIFT (5)
+#define TC_CTRLA_WAVEGEN_MASK (3 << TC_CTRLA_WAVEGEN_SHIFT)
+# define TC_CTRLA_WAVEGEN_NFRQ (0 << TC_CTRLA_WAVEGEN_SHIFT)
+# define TC_CTRLA_WAVEGEN_MFRQ (1 << TC_CTRLA_WAVEGEN_SHIFT)
+# define TC_CTRLA_WAVEGEN_NPWM (2 << TC_CTRLA_WAVEGEN_SHIFT)
+# define TC_CTRLA_WAVEGEN_MPWM (3 << TC_CTRLA_WAVEGEN_SHIFT)
+#define TC_CTRLA_PRESCALER_SHIFT (8)
+#define TC_CTRLA_PRESCALER_MASK (7 << TC_CTRLA_PRESCALER_SHIFT)
+# define TC_CTRLA_PRESCALER_DIV1 (0 << TC_CTRLA_PRESCALER_SHIFT)
+# define TC_CTRLA_PRESCALER_DIV2 (1 << TC_CTRLA_PRESCALER_SHIFT)
+# define TC_CTRLA_PRESCALER_DIV4 (2 << TC_CTRLA_PRESCALER_SHIFT)
+# define TC_CTRLA_PRESCALER_DIV8 (3 << TC_CTRLA_PRESCALER_SHIFT)
+# define TC_CTRLA_PRESCALER_DIV16 (4 << TC_CTRLA_PRESCALER_SHIFT)
+# define TC_CTRLA_PRESCALER_DIV64 (5 << TC_CTRLA_PRESCALER_SHIFT)
+# define TC_CTRLA_PRESCALER_DIV256 (6 << TC_CTRLA_PRESCALER_SHIFT)
+# define TC_CTRLA_PRESCALER_DIV1024 (7 << TC_CTRLA_PRESCALER_SHIFT)
+#define TC_CTRLA_RUNSTDBY (1 << 11)
+#define TC_CTRLA_PRESCSYNC_SHIFT (12)
+#define TC_CTRLA_PRESCSYNC_MASK (3 << TC_CTRLA_PRESCSYNC_SHIFT)
+# define TC_CTRLA_PRESCSYNC_GCLK (0 << TC_CTRLA_PRESCSYNC_SHIFT)
+# define TC_CTRLA_PRESCSYNC_PRESC (1 << TC_CTRLA_PRESCSYNC_SHIFT)
+# define TC_CTRLA_PRESCSYNC_RESYNC (2 << TC_CTRLA_PRESCSYNC_SHIFT)
+
+/* Read Request register */
+
+#define TC_READREQ_ADDR_SHIFT (0)
+#define TC_READREQ_ADDR_MASK (0x1F << TC_READREQ_ADDR_SHIFT)
+#define TC_READREQ_RCONT (1 << 14)
+#define TC_READREQ_RREQ (1 << 15)
+
+/* Control B Set/Clear register */
+
+#define TC_CTRLB_DIR (1 << 0)
+#define TC_CTRLB_ONESHOT (1 << 2)
+#define TC_CTRLB_CMD_SHIFT (6)
+#define TC_CTRLB_CMD_MASK (3 << TC_CTRLBCLR_CMD_SHIFT)
+# define TC_CTRLB_CMD_NONE (0 << TC_CTRLBCLR_CMD_SHIFT)
+# define TC_CTRLB_CMD_RETRIGGER (1 << TC_CTRLBCLR_CMD_SHIFT)
+# define TC_CTRLB_CMD_STOP (2 << TC_CTRLBCLR_CMD_SHIFT)
+
+/* Control C register */
+
+#define TC_CTRLC_INVEN0 (1 << 0)
+#define TC_CTRLC_INVEN1 (1 << 1)
+#define TC_CTRLC_CPTEN0 (1 << 4)
+#define TC_CTRLC_CPTEN1 (1 << 5)
+
+/* Debug control register */
+
+#define TC_DBGCTRL_DBGRUN (1 << 0)
+
+/* Event control register */
+
+#define TC_EVCTRL_EVACT_SHIFT (0)
+#define TC_EVCTRL_EVACT_MASK (7 << TC_EVCTRL_EVACT_SHIFT)
+# define TC_EVCTRL_EVACT_OFF (0 << TC_EVCTRL_EVACT_SHIFT)
+# define TC_EVCTRL_EVACT_RETRIGGER (1 << TC_EVCTRL_EVACT_SHIFT)
+# define TC_EVCTRL_EVACT_COUNT (2 << TC_EVCTRL_EVACT_SHIFT)
+# define TC_EVCTRL_EVACT_START (3 << TC_EVCTRL_EVACT_SHIFT)
+# define TC_EVCTRL_EVACT_PPW (5 << TC_EVCTRL_EVACT_SHIFT)
+# define TC_EVCTRL_EVACT_PWP (6 << TC_EVCTRL_EVACT_SHIFT)
+#define TC_EVCTRL_TCINV (1 << 4)
+#define TC_EVCTRL_TCEI (1 << 5)
+#define TC_EVCTRL_OVFEO (1 << 8)
+#define TC_EVCTRL_MCEO0 (1 << 12)
+#define TC_EVCTRL_MCEO1 (1 << 13)
+
+/* Interrupt register bits */
+
+#define TC_INT_OVF (1 << 0)
+#define TC_INT_ERR (1 << 1)
+#define TC_INT_SYNCRDY (1 << 3)
+#define TC_INT_MC0 (1 << 4)
+#define TC_INT_MC1 (1 << 5)
+
+/* Status register */
+
+#define TC_STATUS_STOP (1 << 3)
+#define TC_STATUS_SLAVE (1 << 4)
+#define TC_STATUS_SYNCBUSY (1 << 7)
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
+#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_TC_H */
diff --git a/arch/arm/src/samdl/chip/samd_tcc.h b/arch/arm/src/samdl/chip/samd_tcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..f7274f992e60c13ffb686993fc35cc8b96bcfbc8
--- /dev/null
+++ b/arch/arm/src/samdl/chip/samd_tcc.h
@@ -0,0 +1,463 @@
+/********************************************************************************************
+ * arch/arm/src/samdl/chip/samd_tcc.h
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Matt Thompson
+ *
+ * References:
+ * "Microchip SAMD21 datasheet"
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_TCC_H
+#define __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_TCC_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+#ifdef CONFIG_ARCH_FAMILY_SAMD21
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+/* TCC register offsets *********************************************************************/
+
+#define SAM_TCC_CTRLA_OFFSET 0x0000 /* Control A register */
+#define SAM_TCC_CTRLBCLR_OFFSET 0x0004 /* Control B clear register */
+#define SAM_TCC_CTRLBSET_OFFSET 0x0005 /* Control B clear register */
+#define SAM_TCC_SYNCBUSY_OFFSET 0x0008 /* Sync Busy register */
+#define SAM_TCC_FCTRLA_OFFSET 0x000C /* Fault control A register */
+#define SAM_TCC_FCTRLB_OFFSET 0x0010 /* Fault control B register */
+#define SAM_TCC_WEXCTRL_OFFSET 0x0014 /* Waveform extension control register */
+#define SAM_TCC_DRVCTRL_OFFSET 0x0018 /* Event control register */
+#define SAM_TCC_DBGCTRL_OFFSET 0x001E /* Debug control register */
+#define SAM_TCC_EVCTRL_OFFSET 0x0020 /* Event control register */
+#define SAM_TCC_INTENCLR_OFFSET 0x0024 /* Interrupt enable clear register */
+#define SAM_TCC_INTENSET_OFFSET 0x0028 /* Interrupt enable set register */
+#define SAM_TCC_INTFLAG_OFFSET 0x002C /* Interrupt flag register */
+#define SAM_TCC_STATUS_OFFSET 0x0030 /* Status register */
+#define SAM_TCC_COUNT_OFFSET 0x0034 /* Count register */
+#define SAM_TCC_PATT_OFFSET 0x0038 /* Pattern register */
+#define SAM_TCC_WAVE_OFFSET 0x003C /* Waveform register */
+#define SAM_TCC_PER_OFFSET 0x0040 /* Period register */
+#define SAM_TCC_CC0_OFFSET 0x0044 /* Capture Compare 0 register */
+#define SAM_TCC_CC1_OFFSET 0x0048 /* Capture Compare 1 register */
+#define SAM_TCC_CC2_OFFSET 0x004C /* Capture Compare 2 register */
+#define SAM_TCC_CC3_OFFSET 0x0050 /* Capture Compare 3 register */
+#define SAM_TCC_PATTB_OFFSET 0x0064 /* Capture Compare 3 register */
+#define SAM_TCC_WAVEB_OFFSET 0x0068 /* Capture Compare 3 register */
+#define SAM_TCC_PERB_OFFSET 0x006C /* Capture Compare 3 register */
+#define SAM_TCC_CCB0_OFFSET 0x0070 /* Capture Compare B0 register */
+#define SAM_TCC_CCB1_OFFSET 0x0074 /* Capture Compare B0 register */
+#define SAM_TCC_CCB2_OFFSET 0x0078 /* Capture Compare B0 register */
+#define SAM_TCC_CCB3_OFFSET 0x007C /* Capture Compare B0 register */
+
+/* TC register addresses *******************************************************************/
+
+#define SAM_TCC0_CTRLA (SAM_TCC0_BASE+SAM_TCC_CTRLA_OFFSET)
+#define SAM_TCC0_CTRLBCLR (SAM_TCC0_BASE+SAM_TCC_CTRLBCLR_OFFSET)
+#define SAM_TCC0_CTRLBSET (SAM_TCC0_BASE+SAM_TCC_CTRLBSET_OFFSET)
+#define SAM_TCC0_SYNCBUSY (SAM_TCC0_BASE+SAM_TCC_SYNCBUSY_OFFSET)
+#define SAM_TCC0_FCTRLA (SAM_TCC0_BASE+SAM_TCC_FCTRLA_OFFSET)
+#define SAM_TCC0_FCTRLB (SAM_TCC0_BASE+SAM_TCC_FCTRLB_OFFSET)
+#define SAM_TCC0_WEXCTRL (SAM_TCC0_BASE+SAM_TCC_WEXCTRL_OFFSET)
+#define SAM_TCC0_DRVCTRL (SAM_TCC0_BASE+SAM_TCC_DRVCTRL_OFFSET)
+#define SAM_TCC0_DBGCTRL (SAM_TCC0_BASE+SAM_TCC_DBGCTRL_OFFSET)
+#define SAM_TCC0_EVCTRL (SAM_TCC0_BASE+SAM_TCC_EVCTRL_OFFSET)
+#define SAM_TCC0_INTENCLR (SAM_TCC0_BASE+SAM_TCC_INTENCLR_OFFSET)
+#define SAM_TCC0_INTENSET (SAM_TCC0_BASE+SAM_TCC_INTENSET_OFFSET)
+#define SAM_TCC0_INTFLAG (SAM_TCC0_BASE+SAM_TCC_INTFLAG_OFFSET)
+#define SAM_TCC0_STATUS (SAM_TCC0_BASE+SAM_TCC_STATUS_OFFSET)
+#define SAM_TCC0_COUNT (SAM_TCC0_BASE+SAM_TCC_COUNT_OFFSET)
+#define SAM_TCC0_PATT (SAM_TCC0_BASE+SAM_TCC_PATT_OFFSET)
+#define SAM_TCC0_WAVE (SAM_TCC0_BASE+SAM_TCC_WAVE_OFFSET)
+#define SAM_TCC0_PER (SAM_TCC0_BASE+SAM_TCC_PER_OFFSET)
+#define SAM_TCC0_CC0 (SAM_TCC0_BASE+SAM_TCC_CC0_OFFSET)
+#define SAM_TCC0_CC1 (SAM_TCC0_BASE+SAM_TCC_CC1_OFFSET)
+#define SAM_TCC0_CC2 (SAM_TCC0_BASE+SAM_TCC_CC2_OFFSET)
+#define SAM_TCC0_CC3 (SAM_TCC0_BASE+SAM_TCC_CC3_OFFSET)
+#define SAM_TCC0_PATTB (SAM_TCC0_BASE+SAM_TCC_PATTB_OFFSET)
+#define SAM_TCC0_WAVEB (SAM_TCC0_BASE+SAM_TCC_WAVEB_OFFSET)
+#define SAM_TCC0_PERB (SAM_TCC0_BASE+SAM_TCC_PERB_OFFSET)
+#define SAM_TCC0_CCB0 (SAM_TCC0_BASE+SAM_TCC_CCB0_OFFSET)
+#define SAM_TCC0_CCB1 (SAM_TCC0_BASE+SAM_TCC_CCB1_OFFSET)
+#define SAM_TCC0_CCB2 (SAM_TCC0_BASE+SAM_TCC_CCB2_OFFSET)
+#define SAM_TCC0_CCB3 (SAM_TCC0_BASE+SAM_TCC_CCB3_OFFSET)
+
+#define SAM_TCC1_CTRLA (SAM_TCC1_BASE+SAM_TCC_CTRLA_OFFSET)
+#define SAM_TCC1_CTRLBCLR (SAM_TCC1_BASE+SAM_TCC_CTRLBCLR_OFFSET)
+#define SAM_TCC1_CTRLBSET (SAM_TCC1_BASE+SAM_TCC_CTRLBSET_OFFSET)
+#define SAM_TCC1_SYNCBUSY (SAM_TCC1_BASE+SAM_TCC_SYNCBUSY_OFFSET)
+#define SAM_TCC1_FCTRLA (SAM_TCC1_BASE+SAM_TCC_FCTRLA_OFFSET)
+#define SAM_TCC1_FCTRLB (SAM_TCC1_BASE+SAM_TCC_FCTRLB_OFFSET)
+#define SAM_TCC1_WEXCTRL (SAM_TCC1_BASE+SAM_TCC_WEXCTRL_OFFSET)
+#define SAM_TCC1_DRVCTRL (SAM_TCC1_BASE+SAM_TCC_DRVCTRL_OFFSET)
+#define SAM_TCC1_DBGCTRL (SAM_TCC1_BASE+SAM_TCC_DBGCTRL_OFFSET)
+#define SAM_TCC1_EVCTRL (SAM_TCC1_BASE+SAM_TCC_EVCTRL_OFFSET)
+#define SAM_TCC1_INTENCLR (SAM_TCC1_BASE+SAM_TCC_INTENCLR_OFFSET)
+#define SAM_TCC1_INTENSET (SAM_TCC1_BASE+SAM_TCC_INTENSET_OFFSET)
+#define SAM_TCC1_INTFLAG (SAM_TCC1_BASE+SAM_TCC_INTFLAG_OFFSET)
+#define SAM_TCC1_STATUS (SAM_TCC1_BASE+SAM_TCC_STATUS_OFFSET)
+#define SAM_TCC1_COUNT (SAM_TCC1_BASE+SAM_TCC_COUNT_OFFSET)
+#define SAM_TCC1_PATT (SAM_TCC1_BASE+SAM_TCC_PATT_OFFSET)
+#define SAM_TCC1_WAVE (SAM_TCC1_BASE+SAM_TCC_WAVE_OFFSET)
+#define SAM_TCC1_PER (SAM_TCC1_BASE+SAM_TCC_PER_OFFSET)
+#define SAM_TCC1_CC0 (SAM_TCC1_BASE+SAM_TCC_CC0_OFFSET)
+#define SAM_TCC1_CC1 (SAM_TCC1_BASE+SAM_TCC_CC1_OFFSET)
+#define SAM_TCC1_CC2 (SAM_TCC1_BASE+SAM_TCC_CC2_OFFSET)
+#define SAM_TCC1_CC3 (SAM_TCC1_BASE+SAM_TCC_CC3_OFFSET)
+#define SAM_TCC1_PATTB (SAM_TCC1_BASE+SAM_TCC_PATTB_OFFSET)
+#define SAM_TCC1_WAVEB (SAM_TCC1_BASE+SAM_TCC_WAVEB_OFFSET)
+#define SAM_TCC1_PERB (SAM_TCC1_BASE+SAM_TCC_PERB_OFFSET)
+#define SAM_TCC1_CCB0 (SAM_TCC1_BASE+SAM_TCC_CCB0_OFFSET)
+#define SAM_TCC1_CCB1 (SAM_TCC1_BASE+SAM_TCC_CCB1_OFFSET)
+#define SAM_TCC1_CCB2 (SAM_TCC1_BASE+SAM_TCC_CCB2_OFFSET)
+#define SAM_TCC1_CCB3 (SAM_TCC1_BASE+SAM_TCC_CCB3_OFFSET)
+
+#define SAM_TCC2_CTRLA (SAM_TCC2_BASE+SAM_TCC_CTRLA_OFFSET)
+#define SAM_TCC2_CTRLBCLR (SAM_TCC2_BASE+SAM_TCC_CTRLBCLR_OFFSET)
+#define SAM_TCC2_CTRLBSET (SAM_TCC2_BASE+SAM_TCC_CTRLBSET_OFFSET)
+#define SAM_TCC2_SYNCBUSY (SAM_TCC2_BASE+SAM_TCC_SYNCBUSY_OFFSET)
+#define SAM_TCC2_FCTRLA (SAM_TCC2_BASE+SAM_TCC_FCTRLA_OFFSET)
+#define SAM_TCC2_FCTRLB (SAM_TCC2_BASE+SAM_TCC_FCTRLB_OFFSET)
+#define SAM_TCC2_WEXCTRL (SAM_TCC2_BASE+SAM_TCC_WEXCTRL_OFFSET)
+#define SAM_TCC2_DRVCTRL (SAM_TCC2_BASE+SAM_TCC_DRVCTRL_OFFSET)
+#define SAM_TCC2_DBGCTRL (SAM_TCC2_BASE+SAM_TCC_DBGCTRL_OFFSET)
+#define SAM_TCC2_EVCTRL (SAM_TCC2_BASE+SAM_TCC_EVCTRL_OFFSET)
+#define SAM_TCC2_INTENCLR (SAM_TCC2_BASE+SAM_TCC_INTENCLR_OFFSET)
+#define SAM_TCC2_INTENSET (SAM_TCC2_BASE+SAM_TCC_INTENSET_OFFSET)
+#define SAM_TCC2_INTFLAG (SAM_TCC2_BASE+SAM_TCC_INTFLAG_OFFSET)
+#define SAM_TCC2_STATUS (SAM_TCC2_BASE+SAM_TCC_STATUS_OFFSET)
+#define SAM_TCC2_COUNT (SAM_TCC2_BASE+SAM_TCC_COUNT_OFFSET)
+#define SAM_TCC2_PATT (SAM_TCC2_BASE+SAM_TCC_PATT_OFFSET)
+#define SAM_TCC2_WAVE (SAM_TCC2_BASE+SAM_TCC_WAVE_OFFSET)
+#define SAM_TCC2_PER (SAM_TCC2_BASE+SAM_TCC_PER_OFFSET)
+#define SAM_TCC2_CC0 (SAM_TCC2_BASE+SAM_TCC_CC0_OFFSET)
+#define SAM_TCC2_CC1 (SAM_TCC2_BASE+SAM_TCC_CC1_OFFSET)
+#define SAM_TCC2_CC2 (SAM_TCC2_BASE+SAM_TCC_CC2_OFFSET)
+#define SAM_TCC2_CC3 (SAM_TCC2_BASE+SAM_TCC_CC3_OFFSET)
+#define SAM_TCC2_PATTB (SAM_TCC2_BASE+SAM_TCC_PATTB_OFFSET)
+#define SAM_TCC2_WAVEB (SAM_TCC2_BASE+SAM_TCC_WAVEB_OFFSET)
+#define SAM_TCC2_PERB (SAM_TCC2_BASE+SAM_TCC_PERB_OFFSET)
+#define SAM_TCC2_CCB0 (SAM_TCC2_BASE+SAM_TCC_CCB0_OFFSET)
+#define SAM_TCC2_CCB1 (SAM_TCC2_BASE+SAM_TCC_CCB1_OFFSET)
+#define SAM_TCC2_CCB2 (SAM_TCC2_BASE+SAM_TCC_CCB2_OFFSET)
+#define SAM_TCC2_CCB3 (SAM_TCC2_BASE+SAM_TCC_CCB3_OFFSET)
+
+/* TC register bit definitions *************************************************************/
+
+/* Control A register */
+
+#define TCC_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
+#define TCC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
+#define TCC_CTRLA_RES_SHIFT (5)
+#define TCC_CTRLA_RES_MASK (3 << TCC_CTRLA_RES_SHIFT)
+# define TCC_CTRLA_RES_NONE (0 << TCC_CTRLA_RES_SHIFT)
+# define TCC_CTRLA_RES_DITH4 (1 << TCC_CTRLA_RES_SHIFT)
+# define TCC_CTRLA_RES_DITH5 (2 << TCC_CTRLA_RES_SHIFT)
+# define TCC_CTRLA_RES_DITH6 (3 << TCC_CTRLA_RES_SHIFT)
+#define TCC_CTRLA_PRESCALER_SHIFT (8)
+#define TCC_CTRLA_PRESCALER_MASK (7 << TCC_CTRLA_PRESCALER_SHIFT)
+# define TCC_CTRLA_PRESCALER_DIV1 (0 << TCC_CTRLA_PRESCALER_SHIFT)
+# define TCC_CTRLA_PRESCALER_DIV2 (1 << TCC_CTRLA_PRESCALER_SHIFT)
+# define TCC_CTRLA_PRESCALER_DIV4 (2 << TCC_CTRLA_PRESCALER_SHIFT)
+# define TCC_CTRLA_PRESCALER_DIV8 (3 << TCC_CTRLA_PRESCALER_SHIFT)
+# define TCC_CTRLA_PRESCALER_DIV16 (4 << TCC_CTRLA_PRESCALER_SHIFT)
+# define TCC_CTRLA_PRESCALER_DIV64 (5 << TCC_CTRLA_PRESCALER_SHIFT)
+# define TCC_CTRLA_PRESCALER_DIV256 (6 << TCC_CTRLA_PRESCALER_SHIFT)
+# define TCC_CTRLA_PRESCALER_DIV1024 (7 << TCC_CTRLA_PRESCALER_SHIFT)
+#define TCC_CTRLA_RUNSTDBY (1 << 11)
+#define TCC_CTRLA_PRESCSYNC_SHIFT (12)
+#define TCC_CTRLA_PRESCSYNC_MASK (3 << TCC_CTRLA_PRESCSYNC_SHIFT)
+# define TCC_CTRLA_PRESCSYNC_GCLK (0 << TCC_CTRLA_PRESCSYNC_SHIFT)
+# define TCC_CTRLA_PRESCSYNC_PRESC (1 << TCC_CTRLA_PRESCSYNC_SHIFT)
+# define TCC_CTRLA_PRESCSYNC_RESYNC (2 << TCC_CTRLA_PRESCSYNC_SHIFT)
+#define TCC_CTRLA_ALOCK (1 << 14)
+#define TCC_CTRLA_CPTEN0 (1 << 24)
+#define TCC_CTRLA_CPTEN1 (1 << 25)
+#define TCC_CTRLA_CPTEN2 (1 << 26)
+#define TCC_CTRLA_CPTEN3 (1 << 27)
+
+/* Control B Set/Clear register */
+
+#define TCC_CTRLB_DIR (1 << 0)
+#define TCC_CTRLB_LUPD (1 << 1)
+#define TCC_CTRLB_ONESHOT (1 << 2)
+#define TCC_CTRLB_IDXCMD_SHIFT (3)
+#define TCC_CTRLB_IDXCMD_MASK (3 << TCC_CTRLB_IDXCMD_SHIFT)
+# define TCC_CTRLB_IDXCMD_DISABLE (0 << TCC_CTRLB_IDXCMD_SHIFT)
+# define TCC_CTRLB_IDXCMD_SET (1 << TCC_CTRLB_IDXCMD_SHIFT)
+# define TCC_CTRLB_IDXCMD_CLEAR (2 << TCC_CTRLB_IDXCMD_SHIFT)
+# define TCC_CTRLB_IDXCMD_HOLD (3 << TCC_CTRLB_IDXCMD_SHIFT)
+#define TCC_CTRLB_CMD_SHIFT (6)
+#define TCC_CTRLB_CMD_MASK (7 << TCC_CTRLB_CMD_SHIFT)
+# define TCC_CTRLB_CMD_NONE (0 << TCC_CTRLB_CMD_SHIFT)
+# define TCC_CTRLB_CMD_RETRIGGER (1 << TCC_CTRLB_CMD_SHIFT)
+# define TCC_CTRLB_CMD_STOP (2 << TCC_CTRLB_CMD_SHIFT)
+# define TCC_CTRLB_CMD_UPDATE (3 << TCC_CTRLB_CMD_SHIFT)
+# define TCC_CTRLB_CMD_READSYNC (4 << TCC_CTRLB_CMD_SHIFT)
+
+/* Sync Busy register */
+
+#define TCC_SYNCBUSY_SWRST (1 << 0)
+#define TCC_SYNCBUSY_ENABLE (1 << 1)
+#define TCC_SYNCBUSY_CTRLB (1 << 2)
+#define TCC_SYNCBUSY_STATUS (1 << 3)
+#define TCC_SYNCBUSY_COUNT (1 << 4)
+#define TCC_SYNCBUSY_PATT (1 << 5)
+#define TCC_SYNCBUSY_WAVE (1 << 6)
+#define TCC_SYNCBUSY_PER (1 << 7)
+#define TCC_SYNCBUSY_CC0 (1 << 8)
+#define TCC_SYNCBUSY_CC1 (1 << 9)
+#define TCC_SYNCBUSY_CC2 (1 << 10)
+#define TCC_SYNCBUSY_CC3 (1 << 11)
+#define TCC_SYNCBUSY_PATTB (1 << 16)
+#define TCC_SYNCBUSY_WAVEB (1 << 17)
+#define TCC_SYNCBUSY_PERB (1 << 18)
+#define TCC_SYNCBUSY_CCB0 (1 << 19)
+#define TCC_SYNCBUSY_CCB1 (1 << 20)
+#define TCC_SYNCBUSY_CCB2 (1 << 21)
+#define TCC_SYNCBUSY_CCB3 (1 << 22)
+
+/* Fault Control A and B */
+
+#define TCC_FCTRL_SRC_SHIFT (0)
+#define TCC_FCTRL_SRC_MASK (3 << TCC_FCTRL_SRC_SHIFT)
+# define TCC_FCTRL_SRC_DISABLE (0 << TCC_FCTRL_SRC_SHIFT)
+# define TCC_FCTRL_SRC_ENABLE (1 << TCC_FCTRL_SRC_SHIFT)
+# define TCC_FCTRL_SRC_INVERT (2 << TCC_FCTRL_SRC_SHIFT)
+# define TCC_FCTRL_SRC_ALTFAULT (3 << TCC_FCTRL_SRC_SHIFT)
+#define TCC_FCTRL_KEEP (1 << 3)
+#define TCC_FCTRL_QUAL (1 << 4)
+#define TCC_FCTRL_BLANK_SHIFT (5)
+#define TCC_FCTRL_BLANK_MASK (3 << TCC_FCTRL_BLANK_SHIFT)
+# define TCC_FCTRL_BLANK_START (0 << TCC_FCTRL_BLANK_SHIFT)
+# define TCC_FCTRL_BLANK_RISE (1 << TCC_FCTRL_BLANK_SHIFT)
+# define TCC_FCTRL_BLANK_FALL (2 << TCC_FCTRL_BLANK_SHIFT)
+# define TCC_FCTRL_BLANK_BOTH (3 << TCC_FCTRL_BLANK_SHIFT)
+#define TCC_FCTRL_RESTART (1 << 7)
+#define TCC_FCTRL_HALT_SHIFT (8)
+#define TCC_FCTRL_HALT_MASK (3 << TCC_FCTRL_HALT_SHIFT)
+# define TCC_FCTRL_HALT_DISABLE (0 << TCC_FCTRL_HALT_SHIFT)
+# define TCC_FCTRL_HALT_HW (1 << TCC_FCTRL_HALT_SHIFT)
+# define TCC_FCTRL_HALT_SW (2 << TCC_FCTRL_HALT_SHIFT)
+# define TCC_FCTRL_HALT_NR (3 << TCC_FCTRL_HALT_SHIFT)
+#define TCC_FCTRL_CHSEL_SHIFT (10)
+#define TCC_FCTRL_CHSEL_MASK (3 << TCC_FCTRL_CHSEL_SHIFT)
+# define TCC_FCTRL_CHSEL_CC0 (0 << TCC_FCTRL_CHSEL_SHIFT)
+# define TCC_FCTRL_CHSEL_CC1 (1 << TCC_FCTRL_CHSEL_SHIFT)
+# define TCC_FCTRL_CHSEL_CC2 (2 << TCC_FCTRL_CHSEL_SHIFT)
+# define TCC_FCTRL_CHSEL_CC3 (3 << TCC_FCTRL_CHSEL_SHIFT)
+#define TCC_FCTRL_CAPTURE_SHIFT (12)
+#define TCC_FCTRL_CAPTURE_MASK (7 << TCC_FCTRL_CAPTURE_SHIFT)
+# define TCC_FCTRL_CAPTURE_DISABLE (0 << TCC_FCTRL_CAPTURE_SHIFT)
+# define TCC_FCTRL_CAPTURE_CAPT (1 << TCC_FCTRL_CAPTURE_SHIFT)
+# define TCC_FCTRL_CAPTURE_CAPTMIN (2 << TCC_FCTRL_CAPTURE_SHIFT)
+# define TCC_FCTRL_CAPTURE_CAPTMAX (3 << TCC_FCTRL_CAPTURE_SHIFT)
+# define TCC_FCTRL_CAPTURE_LOCMIN (4 << TCC_FCTRL_CAPTURE_SHIFT)
+# define TCC_FCTRL_CAPTURE_LOCMAX (5 << TCC_FCTRL_CAPTURE_SHIFT)
+# define TCC_FCTRL_CAPTURE_DERIV0 (6 << TCC_FCTRL_CAPTURE_SHIFT)
+#define TCC_FCTRL_BLANKVAL_SHIFT (16)
+#define TCC_FCTRL_BLANKVAL_MASK (0xff << TCC_FCTRL_BLANKVAL_SHIFT)
+#define TCC_FCTRL_FILTERVAL_SHIFT (24)
+#define TCC_FCTRL_FILTERVAL_MASK (0xf << TCC_FCTRL_FILTERVAL_SHIFT)
+
+/* Waveform Extension Control register */
+
+#define TCC_WEXCTRL_OTMX_SHIFT (0)
+#define TCC_WEXCTRL_OTMX_MASK (3 << TCC_WEXCTRL_OTMX_SHIFT)
+#define TCC_WEXCTRL_DTIEN0 (1 << 8)
+#define TCC_WEXCTRL_DTIEN1 (1 << 9)
+#define TCC_WEXCTRL_DTIEN2 (1 << 10)
+#define TCC_WEXCTRL_DTIEN3 (1 << 11)
+#define TCC_WEXCTRL_DTLS_SHIFT (16)
+#define TCC_WEXCTRL_DTLS_MASK (0xff << TCC_WEXCTRL_DTLS_SHIFT)
+#define TCC_WEXCTRL_DTHS_SHIFT (24)
+#define TCC_WEXCTRL_DTHS_MASK (0xff << TCC_WEXCTRL_DTHS_SHIFT)
+
+/* Driver Control register */
+
+#define TCC_DRVCTRL_NRE(n) (1 << n)
+#define TCC_DRVCTRL_NRV(n) (1 << (8+n))
+#define TCC_DRVCTRL_INVEN(n) (1 << (16+n))
+#define TCC_DRVCTRL_FILTERVAL0_SHIFT (24)
+#define TCC_DRVCTRL_FILTERVAL0_MASK (0xf << TCC_DRVCTRL_FILTERVAL0_SHIFT)
+#define TCC_DRVCTRL_FILTERVAL1_SHIFT (28)
+#define TCC_DRVCTRL_FILTERVAL1_MASK (0xf << TCC_DRVCTRL_FILTERVAL1_SHIFT)
+
+/* Debug control register */
+
+#define TCC_DBGCTRL_DBGRUN (1 << 0)
+#define TCC_DBGCTRL_FDDBD (1 << 2)
+
+/* Event control register */
+
+#define TCC_EVCTRL_EVACT0_SHIFT (0)
+#define TCC_EVCTRL_EVACT0_MASK (7 << TCC_EVCTRL_EVACT0_SHIFT)
+# define TCC_EVCTRL_EVACT0_OFF (0 << TCC_EVCTRL_EVACT0_SHIFT)
+# define TCC_EVCTRL_EVACT0_RETRIGGER (1 << TCC_EVCTRL_EVACT0_SHIFT)
+# define TCC_EVCTRL_EVACT0_COUNTEV (2 << TCC_EVCTRL_EVACT0_SHIFT)
+# define TCC_EVCTRL_EVACT0_START (3 << TCC_EVCTRL_EVACT0_SHIFT)
+# define TCC_EVCTRL_EVACT0_INC (4 << TCC_EVCTRL_EVACT0_SHIFT)
+# define TCC_EVCTRL_EVACT0_COUNT (5 << TCC_EVCTRL_EVACT0_SHIFT)
+# define TCC_EVCTRL_EVACT0_FAULT (7 << TCC_EVCTRL_EVACT0_SHIFT)
+#define TCC_EVCTRL_EVACT1_SHIFT (3)
+#define TCC_EVCTRL_EVACT1_MASK (7 << TCC_EVCTRL_EVACT1_SHIFT)
+# define TCC_EVCTRL_EVACT1_OFF (0 << TCC_EVCTRL_EVACT1_SHIFT)
+# define TCC_EVCTRL_EVACT1_RETRIGGER (1 << TCC_EVCTRL_EVACT1_SHIFT)
+# define TCC_EVCTRL_EVACT1_DIR (2 << TCC_EVCTRL_EVACT1_SHIFT)
+# define TCC_EVCTRL_EVACT1_STOP (3 << TCC_EVCTRL_EVACT1_SHIFT)
+# define TCC_EVCTRL_EVACT1_DEC (4 << TCC_EVCTRL_EVACT1_SHIFT)
+# define TCC_EVCTRL_EVACT1_PPW (5 << TCC_EVCTRL_EVACT1_SHIFT)
+# define TCC_EVCTRL_EVACT1_PWP (6 << TCC_EVCTRL_EVACT1_SHIFT)
+# define TCC_EVCTRL_EVACT1_FAULT (7 << TCC_EVCTRL_EVACT1_SHIFT)
+#define TCC_EVCTRL_CNTSEL_SHIFT (6)
+#define TCC_EVCTRL_CNTSEL_MASK (3 << TCC_EVCTRL_CNTSEL_SHIFT)
+# define TCC_EVCTRL_CNTSEL_BEGIN (0 << TCC_EVCTRL_CNTSEL_SHIFT)
+# define TCC_EVCTRL_CNTSEL_END (1 << TCC_EVCTRL_CNTSEL_SHIFT)
+# define TCC_EVCTRL_CNTSEL_BETWEEN (2 << TCC_EVCTRL_CNTSEL_SHIFT)
+# define TCC_EVCTRL_CNTSEL_BOUNDARY (3 << TCC_EVCTRL_CNTSEL_SHIFT)
+#define TCC_EVCTRL_OVFEO (1 << 8)
+#define TCC_EVCTRL_TRGEO (1 << 9)
+#define TCC_EVCTRL_CNTEO (1 << 10)
+#define TCC_EVCTRL_TCINV0 (1 << 12)
+#define TCC_EVCTRL_TCINV1 (1 << 13)
+#define TCC_EVCTRL_TCEI0 (1 << 14)
+#define TCC_EVCTRL_TCEI1 (1 << 15)
+#define TCC_EVCTRL_MCEI0 (1 << 16)
+#define TCC_EVCTRL_MCEI1 (1 << 17)
+#define TCC_EVCTRL_MCEI2 (1 << 18)
+#define TCC_EVCTRL_MCEI3 (1 << 19)
+#define TCC_EVCTRL_MCEO0 (1 << 24)
+#define TCC_EVCTRL_MCEO1 (1 << 25)
+#define TCC_EVCTRL_MCEO2 (1 << 26)
+#define TCC_EVCTRL_MCEO3 (1 << 27)
+
+/* Interrupt register bits */
+
+#define TCC_INT_OVF (1 << 0)
+#define TCC_INT_TRG (1 << 1)
+#define TCC_INT_CNT (1 << 2)
+#define TCC_INT_ERR (1 << 3)
+#define TCC_INT_DFS (1 << 11)
+#define TCC_INT_FAULTA (1 << 12)
+#define TCC_INT_FAULTB (1 << 13)
+#define TCC_INT_FAULT0 (1 << 14)
+#define TCC_INT_FAULT1 (1 << 15)
+#define TCC_INT_MC0 (1 << 16)
+#define TCC_INT_MC1 (1 << 17)
+#define TCC_INT_MC2 (1 << 18)
+#define TCC_INT_MC3 (1 << 19)
+
+/* Status register */
+
+#define TCC_STATUS_STOP (1 << 0)
+#define TCC_STATUS_IDX (1 << 1)
+#define TCC_STATUS_DFS (1 << 3)
+#define TCC_STATUS_PATTBV (1 << 5)
+#define TCC_STATUS_WAVEBV (1 << 6)
+#define TCC_STATUS_PERBV (1 << 7)
+#define TCC_STATUS_FAULTAIN (1 << 8)
+#define TCC_STATUS_FAULTBIN (1 << 9)
+#define TCC_STATUS_FAULT0IN (1 << 10)
+#define TCC_STATUS_FAULT1IN (1 << 11)
+#define TCC_STATUS_FAULTA (1 << 12)
+#define TCC_STATUS_FAULTB (1 << 13)
+#define TCC_STATUS_FAULT0 (1 << 14)
+#define TCC_STATUS_FAULT1 (1 << 15)
+#define TCC_STATUS_CCBV0 (1 << 16)
+#define TCC_STATUS_CCBV1 (1 << 17)
+#define TCC_STATUS_CCBV2 (1 << 18)
+#define TCC_STATUS_CCBV3 (1 << 19)
+#define TCC_STATUS_CMP0 (1 << 24)
+#define TCC_STATUS_CMP1 (1 << 25)
+#define TCC_STATUS_CMP2 (1 << 26)
+#define TCC_STATUS_CMP3 (1 << 27)
+
+/* Waveform register */
+
+#define TCC_WAVE_WAVEGEN_SHIFT (0)
+#define TCC_WAVE_WAVEGEN_MASK (7 << TCC_WAVE_WAVEGEN_SHIFT)
+# define TCC_WAVE_WAVEGEN_NFRQ (0 << TCC_WAVE_WAVEGEN_SHIFT)
+# define TCC_WAVE_WAVEGEN_MFRQ (1 << TCC_WAVE_WAVEGEN_SHIFT)
+# define TCC_WAVE_WAVEGEN_NPWM (2 << TCC_WAVE_WAVEGEN_SHIFT)
+# define TCC_WAVE_WAVEGEN_DSCRITICAL (4 << TCC_WAVE_WAVEGEN_SHIFT)
+# define TCC_WAVE_WAVEGEN_DSBOTTOM (5 << TCC_WAVE_WAVEGEN_SHIFT)
+# define TCC_WAVE_WAVEGEN_DSBOTH (6 << TCC_WAVE_WAVEGEN_SHIFT)
+# define TCC_WAVE_WAVEGEN_DSTOP (7 << TCC_WAVE_WAVEGEN_SHIFT)
+#define TCC_WAVE_RAMP_SHIFT (4)
+#define TCC_WAVE_RAMP_MASK (3 << TCC_WAVE_RAMP_SHIFT)
+# define TCC_WAVE_RAMP_RAMP1 (0 << TCC_WAVE_RAMP_SHIFT)
+# define TCC_WAVE_RAMP_RAMP2A (1 << TCC_WAVE_RAMP_SHIFT)
+# define TCC_WAVE_RAMP_RAMP2 (2 << TCC_WAVE_RAMP_SHIFT)
+#define TCC_WAVE_CIPEREN (1 << 7)
+#define TCC_WAVE_CICCEN0 (1 << 8)
+#define TCC_WAVE_CICCEN1 (1 << 9)
+#define TCC_WAVE_CICCEN2 (1 << 10)
+#define TCC_WAVE_CICCEN3 (1 << 11)
+#define TCC_WAVE_POL0 (1 << 16)
+#define TCC_WAVE_POL1 (1 << 17)
+#define TCC_WAVE_POL2 (1 << 18)
+#define TCC_WAVE_POL3 (1 << 19)
+#define TCC_WAVE_SWAP0 (1 << 24)
+#define TCC_WAVE_SWAP1 (1 << 25)
+#define TCC_WAVE_SWAP2 (1 << 26)
+#define TCC_WAVE_SWAP3 (1 << 27)
+
+/* Period, CCx, PERB, CCBx register */
+
+#define TCC_DITHER_SHIFT (0)
+#define TCC_DITHER_MASK (0x3f << TCC_PER_DITHER_SHIFT)
+# define TCC_DITHER_NONE (0 << TCC_DITHER_SHIFT)
+# define TCC_DITHER_DITH4 (1 << TCC_DITHER_SHIFT)
+# define TCC_DITHER_DITH5 (2 << TCC_DITHER_SHIFT)
+# define TCC_DITHER_DITH6 (3 << TCC_DITHER_SHIFT)
+#define TCC_VALUE_SHIFT (6)
+#define TCC_VALUE_MASK (0x3ff << TCC_VALUE_SHIFT)
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
+#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_TCC_H */
diff --git a/arch/arm/src/samdl/chip/saml_eic.h b/arch/arm/src/samdl/chip/saml_eic.h
index e6bb167e2ebd022381815e5a4d44edd597f57f4e..56d91824ec401b5629bd99ddf158b644984f3249 100644
--- a/arch/arm/src/samdl/chip/saml_eic.h
+++ b/arch/arm/src/samdl/chip/saml_eic.h
@@ -123,7 +123,7 @@
#define EIC_EXTINT_SHIFT (0) /* Bits 0-15: External interrupt n */
#define EIC_EXTINT_MASK (0xffff << EIC_EXTINT_SHIFT)
-# define EIC_EXTINT(n) ((uint32_t)(n) << EIC_EXTINT_SHIFT)
+# define EIC_EXTINT(n) (1 << (n))
# define EIC_EXTINT_0 (1 << 0) /* Bit 0: External interrupt 0 */
# define EIC_EXTINT_1 (1 << 1) /* Bit 1: External interrupt 1 */
# define EIC_EXTINT_2 (1 << 2) /* Bit 2: External interrupt 2 */
diff --git a/arch/arm/src/samdl/sam_ac.c b/arch/arm/src/samdl/sam_ac.c
new file mode 100644
index 0000000000000000000000000000000000000000..62872da31d94d669328f3a84b17cc945e0636762
--- /dev/null
+++ b/arch/arm/src/samdl/sam_ac.c
@@ -0,0 +1,177 @@
+/****************************************************************************
+ * arch/arm/src/samdl/sam_ac.c
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Matt Thompson
+ *
+ * References:
+ * 1. "Microchip SAM D21E / SAM D21G / SAM D21J Datasheet"
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+
+#include "up_arch.h"
+
+#include "sam_config.h"
+
+#include "sam_pm.h"
+#include "sam_gclk.h"
+#include "sam_periphclks.h"
+#include "sam_ac.h"
+#include "sam_port.h"
+
+#include
+#include
+#include
+
+#include
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static int sam_ac_isr(int irq, FAR void *context, FAR void *arg)
+{
+ return OK;
+}
+
+static void sam_ac_syncwait(void)
+{
+ while ((getreg8(SAM_AC_STATUSB) & AC_STATUSB_SYNCBUSY) != 0);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_ac_initialize
+ *
+ * Description:
+ * Initialize the Analog Comparator (AC).
+ *
+ * Input Parameters:
+ * gclkgen - GCLK Generator
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+int sam_ac_initialize(uint8_t gclkgen)
+{
+ uint16_t regval;
+
+ sam_ac_enableperiph();
+
+ /* The Analog Comparators use two GCLKs */
+
+ /* Enable comparator digital GCLK which provides the sampling rate */
+
+ regval = GCLK_CLKCTRL_ID_ACDIG | GCLK_CLKCTRL_GEN(gclkgen) | GCLK_CLKCTRL_CLKEN;
+ putreg16(regval, SAM_GCLK_CLKCTRL);
+
+ /* Enable comparator analog GCLK */
+
+ regval = GCLK_CLKCTRL_ID_ACANA | GCLK_CLKCTRL_GEN(gclkgen) | GCLK_CLKCTRL_CLKEN;
+ putreg16(regval, SAM_GCLK_CLKCTRL);
+
+ putreg8(AC_CTRLA_ENABLE, SAM_AC_CTRLA);
+ sam_ac_syncwait();
+
+ irq_attach(SAM_IRQ_AC, sam_ac_isr, NULL);
+
+ up_enable_irq(SAM_IRQ_AC);
+
+ return OK;
+}
+
+int sam_ac_config(uint8_t channel, uint32_t compctrl)
+{
+ switch(channel)
+ {
+ case 0:
+ putreg32(compctrl, SAM_AC_COMPCTRL0);
+ break;
+ case 1:
+ putreg32(compctrl, SAM_AC_COMPCTRL1);
+ break;
+ default:
+ return -ENODEV;
+ }
+
+ sam_ac_syncwait();
+
+ return OK;
+}
+
+int sam_ac_enable(uint8_t channel, bool enable)
+{
+ uint32_t regval;
+ switch(channel)
+ {
+ case 0:
+ regval = getreg32(SAM_AC_COMPCTRL0);
+ if(enable == true)
+ regval |= AC_COMPCTRL_ENABLE;
+ else
+ regval &= ~AC_COMPCTRL_ENABLE;
+ putreg32(regval, SAM_AC_COMPCTRL0);
+ break;
+ case 1:
+ regval = getreg32(SAM_AC_COMPCTRL1);
+ if(enable == true)
+ regval |= AC_COMPCTRL_ENABLE;
+ else
+ regval &= ~AC_COMPCTRL_ENABLE;
+ putreg32(regval, SAM_AC_COMPCTRL1);
+ break;
+ default:
+ return -ENODEV;
+ }
+
+ sam_ac_syncwait();
+
+ return OK;
+}
diff --git a/arch/arm/src/samdl/sam_ac.h b/arch/arm/src/samdl/sam_ac.h
new file mode 100644
index 0000000000000000000000000000000000000000..bdf4b5928dd1897fe08927b5146b62720d568070
--- /dev/null
+++ b/arch/arm/src/samdl/sam_ac.h
@@ -0,0 +1,81 @@
+/****************************************************************************
+ * arch/arm/src/samdl/sam_ac.h
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Matt Thompson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMDL_SAM_AC_H
+#define __ARCH_ARM_SRC_SAMDL_SAM_AC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+
+#include "sam_config.h"
+#include "sam_port.h"
+
+#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
+# include "chip/samd_ac.h"
+#elif defined(CONFIG_ARCH_FAMILY_SAML21)
+# include "chip/saml_ac.h"
+#else
+# error Unrecognized SAMD/L architecture
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+int sam_ac_initialize(uint8_t gclkgen);
+int sam_ac_config(uint8_t channel, uint32_t compctrl);
+int sam_ac_enable(uint8_t channel, bool enable);
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+#endif /* __ARCH_ARM_SRC_SAMDL_SAM_AC_H */
diff --git a/arch/arm/src/samdl/sam_dac.h b/arch/arm/src/samdl/sam_dac.h
new file mode 100644
index 0000000000000000000000000000000000000000..b78afd36c1d222b6ed3d8a34a81f8d9fca730e69
--- /dev/null
+++ b/arch/arm/src/samdl/sam_dac.h
@@ -0,0 +1,77 @@
+/****************************************************************************
+ * arch/arm/src/samdl/sam_dac.h
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Matt Thompson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMDL_SAM_DAC_H
+#define __ARCH_ARM_SRC_SAMDL_SAM_DAC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+
+#include "sam_config.h"
+#include "sam_port.h"
+
+#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
+# include "chip/samd_dac.h"
+#elif defined(CONFIG_ARCH_FAMILY_SAML21)
+# include "chip/saml_dac.h"
+#else
+# error Unrecognized SAMD/L architecture
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+#endif /* __ARCH_ARM_SRC_SAMDL_SAM_DAC_H */
diff --git a/arch/arm/src/samdl/sam_dmac.c b/arch/arm/src/samdl/sam_dmac.c
index 5ca812ea4f8ddb36281bbab272917915dc86116e..0b354a03906d8f6b1609927e905dd913447dbed4 100644
--- a/arch/arm/src/samdl/sam_dmac.c
+++ b/arch/arm/src/samdl/sam_dmac.c
@@ -145,15 +145,18 @@ static sem_t g_dsem;
static struct sam_dmach_s g_dmach[SAMDL_NDMACHAN];
-/* DMA descriptor tables positioned in LPRAM. In this use case, it is
- * acceptable for the writeback descriptors to overlap the base
- * descriptors since the base descriptors are always initialized prior
- * to starting each DMA transaction.
+/* NOTE: Using the same address as the base descriptors for writeback descriptors
+ * causes TERR and FERR interrupts to be raised immediately after starting DMA.
+ * This was tested on SAMD21G18A, and it would appear that the writeback
+ * buffer must be located at a different memory address.
+ *
+ * - Matt Thompson
*/
static struct dma_desc_s g_base_desc[SAMDL_NDMACHAN]
__attribute__ ((section(".lpram"), aligned(16)));
-#define g_writeback_desc g_base_desc
+static struct dma_desc_s g_writeback_desc[SAMDL_NDMACHAN]
+ __attribute__ ((section(".lpram"), aligned(16)));
#if CONFIG_SAMDL_DMAC_NDESC > 0
/* Additional DMA descriptors for (optional) multi-block transfer support.
@@ -293,7 +296,7 @@ static int sam_dmainterrupt(int irq, void *context, FAR void *arg)
/* Process all pending channel interrupts */
- while (((intpend = getreg16(SAM_DMAC_INTPEND)) & DMAC_INTPEND_PEND) != 0)
+ while ((intpend = getreg16(SAM_DMAC_INTPEND)) != 0)
{
/* Get the channel that generated the interrupt */
@@ -322,10 +325,17 @@ static int sam_dmainterrupt(int irq, void *context, FAR void *arg)
sam_dmaterminate(dmach, OK);
}
+ else if ((intpend & DMAC_INTPEND_TERR) != 0)
+ {
+ dmaerr("Invalid descriptor. Channel %d\n", chndx);
+ sam_dmaterminate(dmach, -EIO);
+ }
+
/* Check for channel suspend interrupt */
else if ((intpend & DMAC_INTPEND_SUSP) != 0)
{
+ dmaerr("Channel suspended. Channel %d\n", chndx);
/* REVISIT: Do we want to do anything here? */
}
}
@@ -472,7 +482,7 @@ static struct dma_desc_s *sam_append_desc(struct sam_dmach_s *dmach,
/* Allocate a DMA descriptor */
desc = sam_alloc_desc(dmach);
- if (desc == NULL)
+ if (desc != NULL)
{
/* We have it. Initialize the new descriptor list entry */
@@ -500,7 +510,7 @@ static struct dma_desc_s *sam_append_desc(struct sam_dmach_s *dmach,
{
/* There is no previous link. This is the new head of the list */
- DEBUGASSERT(desc == g_base_desc[dmach->dc_chan]);
+ DEBUGASSERT(desc == &g_base_desc[dmach->dc_chan]);
}
#if CONFIG_SAMDL_DMAC_NDESC > 0
@@ -509,6 +519,10 @@ static struct dma_desc_s *sam_append_desc(struct sam_dmach_s *dmach,
dmach->dc_tail = desc;
#endif
}
+ else
+ {
+ dmaerr("Failed to allocate descriptor\n");
+ }
return desc;
}
@@ -604,7 +618,7 @@ static uint16_t sam_bytes2beats(struct sam_dmach_s *dmach, size_t nbytes)
/* The number of beats is then the ceiling of the division */
- mask = (1 < beatsize) - 1;
+ mask = (1 << beatsize) - 1;
nbeats = (nbytes + mask) >> beatsize;
DEBUGASSERT(nbeats <= UINT16_MAX);
return (uint16_t)nbeats;
@@ -627,7 +641,7 @@ static int sam_txbuffer(struct sam_dmach_s *dmach, uint32_t paddr,
uint16_t btcnt;
uint16_t tmp;
- DEBUGASSERT(dmac->dc_dir == DMADIR_UNKOWN || dmac->dc_dir == DMADIR_TX);
+ DEBUGASSERT(dmach->dc_dir == DMADIR_UNKOWN || dmach->dc_dir == DMADIR_TX);
/* Set up the Block Transfer Control Register configuration:
*
@@ -653,14 +667,25 @@ static int sam_txbuffer(struct sam_dmach_s *dmach, uint32_t paddr,
tmp = (dmach->dc_flags & DMACH_FLAG_BEATSIZE_MASK) >> DMACH_FLAG_BEATSIZE_SHIFT;
btctrl |= tmp << LPSRAM_BTCTRL_BEATSIZE_SHIFT;
+ /* See Addressing on page 264 of the datasheet.
+ * When increment is used, we have to adjust the address in the descriptor
+ * based on the beat count remaining in the block
+ */
+
+ /* Set up the Block Transfer Count Register configuration */
+
+ btcnt = sam_bytes2beats(dmach, nbytes);
+
if ((dmach->dc_flags & DMACH_FLAG_MEM_INCREMENT) != 0)
{
btctrl |= LPSRAM_BTCTRL_SRCINC;
+ maddr += nbytes;
}
if ((dmach->dc_flags & DMACH_FLAG_PERIPH_INCREMENT) != 0)
{
btctrl |= LPSRAM_BTCTRL_DSTINC;
+ paddr += nbytes;
}
if ((dmach->dc_flags & DMACH_FLAG_STEPSEL) == DMACH_FLAG_STEPSEL_PERIPH)
@@ -671,10 +696,6 @@ static int sam_txbuffer(struct sam_dmach_s *dmach, uint32_t paddr,
tmp = (dmach->dc_flags & DMACH_FLAG_STEPSIZE_MASK) >> LPSRAM_BTCTRL_STEPSIZE_SHIFT;
btctrl |= tmp << LPSRAM_BTCTRL_STEPSIZE_SHIFT;
- /* Set up the Block Transfer Count Register configuration */
-
- btcnt = sam_bytes2beats(dmach, nbytes);
-
/* Add the new descriptor list entry */
if (!sam_append_desc(dmach, btctrl, btcnt, maddr, paddr))
@@ -703,7 +724,7 @@ static int sam_rxbuffer(struct sam_dmach_s *dmach, uint32_t paddr,
uint16_t btcnt;
uint16_t tmp;
- DEBUGASSERT(dmac->dc_dir == DMADIR_UNKOWN || dmac->dc_dir == DMADIR_RX);
+ DEBUGASSERT(dmach->dc_dir == DMADIR_UNKOWN || dmach->dc_dir == DMADIR_RX);
/* Set up the Block Transfer Control Register configuration:
*
@@ -729,14 +750,20 @@ static int sam_rxbuffer(struct sam_dmach_s *dmach, uint32_t paddr,
tmp = (dmach->dc_flags & DMACH_FLAG_BEATSIZE_MASK) >> DMACH_FLAG_BEATSIZE_SHIFT;
btctrl |= tmp << LPSRAM_BTCTRL_BEATSIZE_SHIFT;
+ /* Set up the Block Transfer Count Register configuration */
+
+ btcnt = sam_bytes2beats(dmach, nbytes);
+
if ((dmach->dc_flags & DMACH_FLAG_PERIPH_INCREMENT) != 0)
{
btctrl |= LPSRAM_BTCTRL_SRCINC;
+ paddr += nbytes;
}
if ((dmach->dc_flags & DMACH_FLAG_MEM_INCREMENT) != 0)
{
btctrl |= LPSRAM_BTCTRL_DSTINC;
+ maddr += nbytes;
}
if ((dmach->dc_flags & DMACH_FLAG_STEPSEL) == DMACH_FLAG_STEPSEL_MEM)
@@ -747,10 +774,6 @@ static int sam_rxbuffer(struct sam_dmach_s *dmach, uint32_t paddr,
tmp = (dmach->dc_flags & DMACH_FLAG_STEPSIZE_MASK) >> LPSRAM_BTCTRL_STEPSIZE_SHIFT;
btctrl |= tmp << LPSRAM_BTCTRL_STEPSIZE_SHIFT;
- /* Set up the Block Transfer Count Register configuration */
-
- btcnt = sam_bytes2beats(dmach, nbytes);
-
/* Add the new descriptor list entry */
if (!sam_append_desc(dmach, btctrl, btcnt, paddr, maddr))
@@ -1183,7 +1206,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
}
chctrlb |= tmp << DMAC_CHCTRLB_TRIGSRC_SHIFT;
- putreg8(chctrlb, SAM_DMAC_CHCTRLB);
+ putreg32(chctrlb, SAM_DMAC_CHCTRLB);
/* Setup the Quality of Service Control Register
*
@@ -1218,10 +1241,13 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
/* Enable the channel */
ctrla = DMAC_CHCTRLA_ENABLE;
+
+#ifdef CONFIG_ARCH_FAMILY_SAML21
if (dmach->dc_flags & DMACH_FLAG_RUNINSTDBY)
{
ctrla |= DMAC_CHCTRLA_RUNSTDBY;
}
+#endif
putreg8(ctrla, SAM_DMAC_CHCTRLA);
@@ -1272,19 +1298,18 @@ void sam_dmastop(DMA_HANDLE handle)
#ifdef CONFIG_DEBUG_DMA_INFO
void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
{
- struct sam_dmach_s *dmach = (struct sam_dmach_s *)handle;
- uintptr_t base;
irqstate_t flags;
/* Sample DMAC registers. */
flags = enter_critical_section();
+
regs->ctrl = getreg16(SAM_DMAC_CTRL); /* Control Register */
regs->crcctrl = getreg16(SAM_DMAC_CRCCTRL); /* CRC Control Register */
regs->crcdatain = getreg32(SAM_DMAC_CRCDATAIN); /* CRC Data Input Register */
regs->crcchksum = getreg32(SAM_DMAC_CRCCHKSUM); /* CRC Checksum Register */
regs->crcstatus = getreg8(SAM_DMAC_CRCSTATUS); /* CRC Status Register */
- regs->errctrl = getreg8(SAM_DMAC_DBGCTRL); /* Debug Control Register */
+ regs->dbgctrl = getreg8(SAM_DMAC_DBGCTRL); /* Debug Control Register */
regs->qosctrl = getreg8(SAM_DMAC_QOSCTRL); /* Quality of Service Control Register */
regs->swtrigctrl = getreg32(SAM_DMAC_SWTRIGCTRL); /* Software Trigger Control Register */
regs->prictrl0 = getreg32(SAM_DMAC_PRICTRL0); /* Priority Control 0 Register */
@@ -1300,6 +1325,8 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
regs->chctrlb = getreg32(SAM_DMAC_CHCTRLB); /* Channel Control B Register */
regs->chintflag = getreg8(SAM_DMAC_CHINTFLAG); /* Channel Interrupt Flag Status and Clear Register */
regs->chstatus = getreg8(SAM_DMAC_CHSTATUS); /* Channel Status Register */
+
+ leave_critical_section(flags);
}
#endif /* CONFIG_DEBUG_DMA_INFO */
@@ -1325,13 +1352,13 @@ void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
dmainfo(" CTRL: %04x CRCCTRL: %04x CRCDATAIN: %08x CRCCHKSUM: %08x\n",
regs->ctrl, regs->crcctrl, regs->crcdatain, regs->crcchksum);
dmainfo(" CRCSTATUS: %02x DBGCTRL: %02x QOSCTRL: %02x SWTRIGCTRL: %08x\n",
- regs->crcstatus, regs->errctrl, regs->qosctrl, regs->swtrigctrl);
- dmainfo(" PRICTRL0: %08x INTPEND: %04x INSTSTATUS: %08x BUSYCH: %08x\n",
+ regs->crcstatus, regs->dbgctrl, regs->qosctrl, regs->swtrigctrl);
+ dmainfo(" PRICTRL0: %08x INTPEND: %04x INTSTATUS: %08x BUSYCH: %08x\n",
regs->prictrl0, regs->intpend, regs->intstatus, regs->busych);
dmainfo(" PENDCH: %08x ACTIVE: %08x BASEADDR: %08x WRBADDR: %08x\n",
regs->pendch, regs->active, regs->baseaddr, regs->wrbaddr);
dmainfo(" CHID: %02x CHCRTRLA: %02x CHCRTRLB: %08x CHINFLAG: %02x\n",
- regs->chid, regs->chctrla, regs->chctrlb, regs->chintflag,
+ regs->chid, regs->chctrla, regs->chctrlb, regs->chintflag);
dmainfo(" CHSTATUS: %02x\n",
regs->chstatus);
}
diff --git a/arch/arm/src/samdl/sam_dmac.h b/arch/arm/src/samdl/sam_dmac.h
index 2a6937dd6820014c626c3a88d8c86b2655b26471..f7b7a18b7bb67a32fd3053a5f10468e182d35b15 100644
--- a/arch/arm/src/samdl/sam_dmac.h
+++ b/arch/arm/src/samdl/sam_dmac.h
@@ -50,8 +50,8 @@
#ifdef CONFIG_SAMDL_DMAC
-#if defined(CONFIG_ARCH_FAMILY_SAMD20)
-# error Missing support for the SAMD20 architecture
+#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
+# include "chip/samd_dmac.h"
#elif defined(CONFIG_ARCH_FAMILY_SAML21)
# include "chip/saml_dmac.h"
#else
diff --git a/arch/arm/src/samdl/sam_eic.c b/arch/arm/src/samdl/sam_eic.c
new file mode 100644
index 0000000000000000000000000000000000000000..95a20504cb9ff0b60cce44925111de1a4ac324fb
--- /dev/null
+++ b/arch/arm/src/samdl/sam_eic.c
@@ -0,0 +1,275 @@
+/****************************************************************************
+ * arch/arm/src/samdl/sam_eic.c
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Matt Thompson
+ *
+ * References:
+ * 1. "Microchip SAM D21E / SAM D21G / SAM D21J Datasheet"
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+
+#include "up_arch.h"
+
+#include "sam_config.h"
+
+#include "sam_pm.h"
+#include "sam_gclk.h"
+#include "sam_periphclks.h"
+#include "sam_eic.h"
+#include "sam_port.h"
+
+#include
+#include
+#include
+
+#include
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static int sam_eic_isr(int irq, FAR void *context, FAR void *arg)
+{
+ uint32_t intflag;
+ int bit;
+
+ /* Get the pending interrupt flag register */
+
+ intflag = getreg32(SAM_EIC_INTFLAG);
+
+ /* Dispatch the IRQ to the SAM_IRQ_EXTINTn handlers */
+
+ for(bit=0;bit> bit & 0x1)
+ {
+ irq_dispatch(SAM_IRQ_EXTINT0 + bit, context);
+ }
+ }
+
+ /* Clear the pending interrupt flags */
+
+ putreg32(EIC_EXTINT_ALL, SAM_EIC_INTFLAG);
+
+ return 0;
+}
+
+static void sam_eic_syncwait(void)
+{
+ while ((getreg8(SAM_EIC_STATUS) & EIC_STATUS_SYNCBUSY) != 0);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void sam_eic_dumpregs(void)
+{
+ irqinfo("EIC:\n");
+ irqinfo(" CTRLA: %02x\n", getreg8(SAM_EIC_CTRLA));
+ irqinfo(" STATUS: %02x\n", getreg8(SAM_EIC_STATUS));
+ irqinfo(" NMICTRL: %02x\n", getreg8(SAM_EIC_NMICTRL));
+ irqinfo(" NMIFLAG: %02x\n", getreg8(SAM_EIC_NMIFLAG));
+ irqinfo(" EVCTRL: %08x\n", getreg32(SAM_EIC_EVCTRL));
+ irqinfo(" INTENCLR: %08x\n", getreg32(SAM_EIC_INTENCLR));
+ irqinfo(" INTENSET: %08x\n", getreg32(SAM_EIC_INTENSET));
+ irqinfo(" INTFLAG: %08x\n", getreg32(SAM_EIC_INTFLAG));
+ irqinfo(" WAKEUP: %08x\n", getreg32(SAM_EIC_WAKEUP));
+ irqinfo(" CONFIG0: %08x\n", getreg32(SAM_EIC_CONFIG0));
+ irqinfo(" CONFIG1: %08x\n", getreg32(SAM_EIC_CONFIG1));
+ irqinfo(" CONFIG2: %08x\n", getreg32(SAM_EIC_CONFIG2));
+}
+
+/****************************************************************************
+ * Name: sam_eic_initialize
+ *
+ * Description:
+ * Initialize the external interrupt controller (EIC).
+ *
+ * Input Parameters:
+ * gclkgen - GCLK Generator
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+int sam_eic_initialize(uint8_t gclkgen)
+{
+ uint16_t regval;
+
+ sam_eic_enableperiph();
+
+ regval = GCLK_CLKCTRL_ID_EIC | GCLK_CLKCTRL_GEN(gclkgen) | GCLK_CLKCTRL_CLKEN;
+ putreg16(regval, SAM_GCLK_CLKCTRL);
+
+ putreg8(EIC_CTRLA_ENABLE, SAM_EIC_CTRLA);
+ sam_eic_syncwait();
+
+ irq_attach(SAM_IRQ_EIC, sam_eic_isr, NULL);
+
+ sam_eic_dumpregs();
+
+ up_enable_irq(SAM_IRQ_EIC);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: sam_eic_initialize
+ *
+ * Description:
+ * Enable a external interrupt.
+ *
+ * Input Parameters:
+ * irq - SAM_IRQ_EXTINTn IRQ to be enabled
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+int sam_eic_irq_enable(int irq)
+{
+ uint32_t config;
+ int eirq = irq - SAM_IRQ_EXTINT0;
+
+ config = getreg32(SAM_EIC_CONFIG0);
+ config |= EIC_CONFIG0_FILTEN(eirq) | EIC_CONFIG0_SENSE_FALL(eirq);
+ putreg32(config, SAM_EIC_CONFIG0);
+
+ putreg32(EIC_EXTINT(eirq), SAM_EIC_INTENSET);
+ sam_eic_dumpregs();
+ return OK;
+}
+
+/****************************************************************************
+ * Name: sam_eic_config
+ *
+ * Description:
+ * Configure the interrupt edge sensitivity in CONFIGn register of the EIC
+ *
+ * Input Parameters:
+ * eirq - Pin to be configured
+ * pinset - Configuration of the pin
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+int sam_eic_config(uint8_t eirq, port_pinset_t pinset)
+{
+ uint32_t reg;
+ uint32_t val;
+ uint32_t config;
+
+ /* Determine which of the CONFIG[0:2] registers to write to */
+
+ if (eirq < 8)
+ {
+ reg = SAM_EIC_CONFIG0;
+
+ val = EIC_CONFIG0_SENSE_BOTH(eirq);
+ if (pinset & PORT_INT_RISING)
+ {
+ val = EIC_CONFIG0_SENSE_RISE(eirq);
+ }
+
+ if (pinset & PORT_INT_FALLING)
+ {
+ val = EIC_CONFIG0_SENSE_FALL(eirq);
+ }
+
+ val |= EIC_CONFIG0_FILTEN(eirq);
+ }
+ else if (eirq < 16)
+ {
+ reg = SAM_EIC_CONFIG1;
+
+ val = EIC_CONFIG1_SENSE_BOTH(eirq);
+ if (pinset & PORT_INT_RISING)
+ {
+ val = EIC_CONFIG1_SENSE_RISE(eirq);
+ }
+
+ if (pinset & PORT_INT_FALLING)
+ {
+ val = EIC_CONFIG1_SENSE_FALL(eirq);
+ }
+
+ val |= EIC_CONFIG1_FILTEN(eirq);
+ }
+ else
+ {
+ reg = SAM_EIC_CONFIG2;
+
+ val = EIC_CONFIG2_SENSE_BOTH(eirq);
+ if (pinset & PORT_INT_RISING)
+ {
+ val = EIC_CONFIG2_SENSE_RISE(eirq);
+ }
+
+ if (pinset & PORT_INT_FALLING)
+ {
+ val = EIC_CONFIG2_SENSE_FALL(eirq);
+ }
+
+ val |= EIC_CONFIG2_FILTEN(eirq);
+ }
+
+ /* Write the new config to the CONFIGn register */
+
+ config = getreg32(reg);
+ config |= val;
+ putreg32(config, reg);
+
+ /* Enable interrupt generation for this pin */
+
+ putreg32(EIC_EXTINT(eirq), SAM_EIC_INTENSET);
+
+ sam_eic_dumpregs();
+ return OK;
+}
diff --git a/arch/arm/src/samdl/sam_eic.h b/arch/arm/src/samdl/sam_eic.h
new file mode 100644
index 0000000000000000000000000000000000000000..d60c936cef5193f7531b570fc07d96b6da478ae4
--- /dev/null
+++ b/arch/arm/src/samdl/sam_eic.h
@@ -0,0 +1,125 @@
+/****************************************************************************
+ * arch/arm/src/samdl/sam_eic.h
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Matt Thompson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMDL_SAM_EIC_H
+#define __ARCH_ARM_SRC_SAMDL_SAM_EIC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+
+#include "sam_config.h"
+#include "sam_port.h"
+
+#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
+# include "chip/samd_eic.h"
+#elif defined(CONFIG_ARCH_FAMILY_SAML21)
+# include "chip/saml_eic.h"
+#else
+# error Unrecognized SAMD/L architecture
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: sam_eic_initialize
+ *
+ * Description:
+ * Initialize the EIC
+ *
+ * Input Parameters:
+ * gclkgen - GCLK Generator
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+int sam_eic_initialize(uint8_t gclkgen);
+
+/****************************************************************************
+ * Name: sam_eic_initialize
+ *
+ * Description:
+ * Enable a external interrupt.
+ *
+ * Input Parameters:
+ * irq - SAM_IRQ_EXTINTn IRQ to be enabled
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+int sam_eic_irq_enable(int irq);
+
+/****************************************************************************
+ * Name: sam_eic_config
+ *
+ * Description:
+ * Configure the interrupt edge sensitivity in CONFIGn register of the EIC
+ *
+ * Input Parameters:
+ * eirq - Pin to be configured
+ * pinset - Configuration of the pin
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+int sam_eic_config(uint8_t eirq, port_pinset_t pinset);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+#endif /* __ARCH_ARM_SRC_SAMDL_SAM_EIC_H */
diff --git a/arch/arm/src/samdl/sam_evsys.h b/arch/arm/src/samdl/sam_evsys.h
new file mode 100644
index 0000000000000000000000000000000000000000..13b41fa3e5563f0a1f2b78f4178333f7f945e464
--- /dev/null
+++ b/arch/arm/src/samdl/sam_evsys.h
@@ -0,0 +1,76 @@
+/****************************************************************************
+ * arch/arm/src/samdl/sam_evsys.h
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Matt Thompson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMDL_SAM_EVSYS_H
+#define __ARCH_ARM_SRC_SAMDL_SAM_EVSYS_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+
+#include "sam_config.h"
+#include "sam_port.h"
+
+#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
+# include "chip/samd_evsys.h"
+#elif defined(CONFIG_ARCH_FAMILY_SAML21)
+# include "chip/saml_evsys.h"
+#else
+# error Unrecognized SAMD/L architecture
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+#endif /* __ARCH_ARM_SRC_SAMDL_SAM_EVSYS_H */
diff --git a/arch/arm/src/samdl/sam_port.c b/arch/arm/src/samdl/sam_port.c
index b757de5c581bd63193f19574b43fcf0970e6e209..df35aae65a7aa3e59c4993b4cd1907dbf94b83dc 100644
--- a/arch/arm/src/samdl/sam_port.c
+++ b/arch/arm/src/samdl/sam_port.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/samdl/sam_port.c
*
- * Copyright (C) 2014-2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014-2016, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* References:
@@ -57,6 +57,7 @@
#include "chip.h"
#include "sam_port.h"
+#include "sam_eic.h"
/****************************************************************************
* Private Data
@@ -189,7 +190,30 @@ static inline void sam_configinput(uintptr_t base, port_pinset_t pinset)
static inline void sam_configinterrupt(uintptr_t base, port_pinset_t pinset)
{
-#warning Missing logic
+#ifdef CONFIG_SAMDL_EIC
+ uint32_t func;
+ uint32_t regval;
+ int pin;
+
+ pin = (pinset & PORT_PIN_MASK) >> PORT_PIN_SHIFT;
+
+ regval = (PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_WRPMUX |
+ PORT_WRCONFIG_PMUXEN | PORT_WRCONFIG_INEN);
+ regval |= PORT_WRCONFIG_PINMASK(pin);
+
+ func = (pinset & PORT_FUNC_MASK) >> PORT_FUNC_SHIFT;
+ regval |= (func << PORT_WRCONFIG_PMUX_SHIFT);
+
+ putreg32(regval, base + SAM_PORT_WRCONFIG_OFFSET);
+
+ /* Configure the interrupt edge sensitivity in CONFIGn register of the EIC */
+
+ sam_eic_config(pin, pinset);
+
+#ifdef CONFIG_DEBUG_GPIO_INFO
+ sam_dumpport(pinset, "extint");
+#endif
+#endif /* CONFIG_SAMDL_EIC */
}
/****************************************************************************
@@ -531,7 +555,7 @@ int sam_dumpport(uint32_t pinset, const char *msg)
/* Get the base address associated with the PIO port */
- pin = sam_portpin(pinset);
+ pin = (pinset & PORT_PIN_MASK) >> PORT_PIN_SHIFT;
port = (pinset & PORT_MASK) >> PORT_SHIFT;
base = SAM_PORTN_BASE(port);
diff --git a/arch/arm/src/samdl/sam_port.h b/arch/arm/src/samdl/sam_port.h
index c03edcbcb5d38494b4be3e9beb3c2a622a9043fa..3227c5480381eaed2efab21bbe291d6366a97396 100644
--- a/arch/arm/src/samdl/sam_port.h
+++ b/arch/arm/src/samdl/sam_port.h
@@ -343,7 +343,7 @@ extern "C"
* Description:
* Configure a PORT pin based on bit-encoded description of the pin.
*
- * Returns:
+ * Returned Value:
* OK (always)
*
****************************************************************************/
diff --git a/arch/arm/src/samdl/sam_serial.c b/arch/arm/src/samdl/sam_serial.c
index aab2d81d23d3d86712257b7377c1cc5b3df17c10..6f00639df84c17feb26e621d7f9877920f6ea9c1 100644
--- a/arch/arm/src/samdl/sam_serial.c
+++ b/arch/arm/src/samdl/sam_serial.c
@@ -524,7 +524,7 @@ static void sam_disableallints(struct sam_dev_s *priv)
* interrupt received on the 'irq' It should call uart_transmitchars or
* uart_receivechar to perform the appropriate data transfers. The
* interrupt handling logic must be able to map the 'irq' number into the
- * approprite uart_dev_s structure in order to call these functions.
+ * appropriate uart_dev_s structure in order to call these functions.
*
****************************************************************************/
@@ -1010,4 +1010,3 @@ int up_putc(int ch)
#endif /* USE_SERIALDRIVER */
#endif /* SAMDL_HAVE_USART */
-
diff --git a/arch/arm/src/samdl/sam_spi.c b/arch/arm/src/samdl/sam_spi.c
index 1f945b765932d5839d6d9337ad4b39e976d01af1..ab75f1f4b349665c11233850da9e9d8e0f61080a 100644
--- a/arch/arm/src/samdl/sam_spi.c
+++ b/arch/arm/src/samdl/sam_spi.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/samdl/sam_spi.c
*
- * Copyright (C) 2014-2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014-2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt
*
* References:
@@ -69,6 +69,10 @@
#include "sam_sercom.h"
#include "sam_spi.h"
+#ifdef CONFIG_SAMDL_SPI_DMA
+# include "sam_dmac.h"
+#endif
+
#include
#ifdef SAMDL_HAVE_SPI
@@ -118,6 +122,16 @@ struct sam_spidev_s
uint8_t mode; /* Mode 0,1,2,3 */
uint8_t nbits; /* Width of word in bits (8 to 16) */
+#ifdef CONFIG_SAMDL_SPI_DMA
+ /* DMA */
+
+ uint8_t dma_tx_trig; /* DMA TX trigger source to use */
+ uint8_t dma_rx_trig; /* DMA RX trigger source to use */
+ DMA_HANDLE dma_tx; /* DMA TX channel handle */
+ DMA_HANDLE dma_rx; /* DMA RX channel handle */
+ sem_t dmasem; /* Transfer wait semaphore */
+#endif
+
/* Debug stuff */
#ifdef CONFIG_SAMDL_SPI_REGDEBUG
@@ -154,6 +168,10 @@ static uint32_t spi_getreg32(struct sam_spidev_s *priv,
static void spi_putreg32(struct sam_spidev_s *priv, uint32_t regval,
unsigned int offset);
+#ifdef CONFIG_SAMDL_SPI_DMA
+static void spi_dma_setup(struct sam_spidev_s *priv);
+#endif
+
#ifdef CONFIG_DEBUG_SPI_INFO
static void spi_dumpregs(struct sam_spidev_s *priv, const char *msg);
#else
@@ -163,7 +181,7 @@ static void spi_dumpregs(struct sam_spidev_s *priv, const char *msg);
/* Interrupt handling */
#if 0 /* Not used */
-static int spi_interrupt(int irq, void *context, FAR void *arg);
+static int spi_interrupt(int irq, void *context, FAR void *arg);
#endif
/* SPI methods */
@@ -222,21 +240,25 @@ static const struct spi_ops_s g_spi0ops =
static struct sam_spidev_s g_spi0dev =
{
- .ops = &g_spi0ops,
- .sercom = 0,
+ .ops = &g_spi0ops,
+ .sercom = 0,
#if 0 /* Not used */
- .irq = SAM_IRQ_SERCOM0,
-#endif
- .gclkgen = BOARD_SERCOM0_GCLKGEN,
- .slowgen = BOARD_SERCOM0_SLOW_GCLKGEN,
- .pad0 = BOARD_SERCOM0_PINMAP_PAD0,
- .pad1 = BOARD_SERCOM0_PINMAP_PAD1,
- .pad2 = BOARD_SERCOM0_PINMAP_PAD2,
- .pad3 = BOARD_SERCOM0_PINMAP_PAD3,
- .muxconfig = BOARD_SERCOM0_MUXCONFIG,
- .srcfreq = BOARD_SERCOM0_FREQUENCY,
- .base = SAM_SERCOM0_BASE,
- .spilock = SEM_INITIALIZER(1),
+ .irq = SAM_IRQ_SERCOM0,
+#endif
+ .gclkgen = BOARD_SERCOM0_GCLKGEN,
+ .slowgen = BOARD_SERCOM0_SLOW_GCLKGEN,
+ .pad0 = BOARD_SERCOM0_PINMAP_PAD0,
+ .pad1 = BOARD_SERCOM0_PINMAP_PAD1,
+ .pad2 = BOARD_SERCOM0_PINMAP_PAD2,
+ .pad3 = BOARD_SERCOM0_PINMAP_PAD3,
+ .muxconfig = BOARD_SERCOM0_MUXCONFIG,
+ .srcfreq = BOARD_SERCOM0_FREQUENCY,
+ .base = SAM_SERCOM0_BASE,
+ .spilock = SEM_INITIALIZER(1),
+#ifdef CONFIG_SAMDL_SPI_DMA
+ .dma_tx_trig = DMAC_TRIGSRC_SERCOM0_TX,
+ .dma_rx_trig = DMAC_TRIGSRC_SERCOM0_RX,
+#endif
};
#endif
@@ -268,21 +290,25 @@ static const struct spi_ops_s g_spi1ops =
static struct sam_spidev_s g_spi1dev =
{
- .ops = &g_spi1ops,
- .sercom = 1,
+ .ops = &g_spi1ops,
+ .sercom = 1,
#if 0 /* Not used */
- .irq = SAM_IRQ_SERCOM1,
-#endif
- .gclkgen = BOARD_SERCOM1_GCLKGEN,
- .slowgen = BOARD_SERCOM1_SLOW_GCLKGEN,
- .pad0 = BOARD_SERCOM1_PINMAP_PAD0,
- .pad1 = BOARD_SERCOM1_PINMAP_PAD1,
- .pad2 = BOARD_SERCOM1_PINMAP_PAD2,
- .pad3 = BOARD_SERCOM1_PINMAP_PAD3,
- .muxconfig = BOARD_SERCOM1_MUXCONFIG,
- .srcfreq = BOARD_SERCOM1_FREQUENCY,
- .base = SAM_SERCOM1_BASE,
- .spilock = SEM_INITIALIZER(1),
+ .irq = SAM_IRQ_SERCOM1,
+#endif
+ .gclkgen = BOARD_SERCOM1_GCLKGEN,
+ .slowgen = BOARD_SERCOM1_SLOW_GCLKGEN,
+ .pad0 = BOARD_SERCOM1_PINMAP_PAD0,
+ .pad1 = BOARD_SERCOM1_PINMAP_PAD1,
+ .pad2 = BOARD_SERCOM1_PINMAP_PAD2,
+ .pad3 = BOARD_SERCOM1_PINMAP_PAD3,
+ .muxconfig = BOARD_SERCOM1_MUXCONFIG,
+ .srcfreq = BOARD_SERCOM1_FREQUENCY,
+ .base = SAM_SERCOM1_BASE,
+ .spilock = SEM_INITIALIZER(1),
+#ifdef CONFIG_SAMDL_SPI_DMA
+ .dma_tx_trig = DMAC_TRIGSRC_SERCOM1_TX,
+ .dma_rx_trig = DMAC_TRIGSRC_SERCOM1_RX,
+#endif
};
#endif
@@ -292,13 +318,13 @@ static struct sam_spidev_s g_spi1dev =
static const struct spi_ops_s g_spi2ops =
{
.lock = spi_lock,
- .select = sam_spi0select,
+ .select = sam_spi2select,
.setfrequency = spi_setfrequency,
.setmode = spi_setmode,
.setbits = spi_setbits,
- .status = sam_spi0status,
+ .status = sam_spi2status,
#ifdef CONFIG_SPI_CMDDATA
- .cmddata = sam_spi0cmddata,
+ .cmddata = sam_spi2cmddata,
#endif
.send = spi_send,
#ifdef CONFIG_SPI_EXCHANGE
@@ -314,21 +340,25 @@ static const struct spi_ops_s g_spi2ops =
static struct sam_spidev_s g_spi2dev =
{
- .ops = &g_spi1ops,
- .sercom = 2,
+ .ops = &g_spi2ops,
+ .sercom = 2,
#if 0 /* Not used */
- .irq = SAM_IRQ_SERCOM2,
-#endif
- .gclkgen = BOARD_SERCOM2_GCLKGEN,
- .slowgen = BOARD_SERCOM2_SLOW_GCLKGEN,
- .pad0 = BOARD_SERCOM2_PINMAP_PAD0,
- .pad1 = BOARD_SERCOM2_PINMAP_PAD1,
- .pad2 = BOARD_SERCOM2_PINMAP_PAD2,
- .pad3 = BOARD_SERCOM2_PINMAP_PAD3,
- .muxconfig = BOARD_SERCOM2_MUXCONFIG,
- .srcfreq = BOARD_SERCOM2_FREQUENCY,
- .base = SAM_SERCOM2_BASE,
- .spilock = SEM_INITIALIZER(1),
+ .irq = SAM_IRQ_SERCOM2,
+#endif
+ .gclkgen = BOARD_SERCOM2_GCLKGEN,
+ .slowgen = BOARD_SERCOM2_SLOW_GCLKGEN,
+ .pad0 = BOARD_SERCOM2_PINMAP_PAD0,
+ .pad1 = BOARD_SERCOM2_PINMAP_PAD1,
+ .pad2 = BOARD_SERCOM2_PINMAP_PAD2,
+ .pad3 = BOARD_SERCOM2_PINMAP_PAD3,
+ .muxconfig = BOARD_SERCOM2_MUXCONFIG,
+ .srcfreq = BOARD_SERCOM2_FREQUENCY,
+ .base = SAM_SERCOM2_BASE,
+ .spilock = SEM_INITIALIZER(1),
+#ifdef CONFIG_SAMDL_SPI_DMA
+ .dma_tx_trig = DMAC_TRIGSRC_SERCOM2_TX,
+ .dma_rx_trig = DMAC_TRIGSRC_SERCOM2_RX,
+#endif
};
#endif
@@ -360,21 +390,25 @@ static const struct spi_ops_s g_spi3ops =
static struct sam_spidev_s g_spi3dev =
{
- .ops = &g_spi3ops,
- .sercom = 3,
+ .ops = &g_spi3ops,
+ .sercom = 3,
#if 0 /* Not used */
- .irq = SAM_IRQ_SERCOM3,
-#endif
- .gclkgen = BOARD_SERCOM3_GCLKGEN,
- .slowgen = BOARD_SERCOM3_SLOW_GCLKGEN,
- .pad0 = BOARD_SERCOM3_PINMAP_PAD0,
- .pad1 = BOARD_SERCOM3_PINMAP_PAD1,
- .pad2 = BOARD_SERCOM3_PINMAP_PAD2,
- .pad3 = BOARD_SERCOM3_PINMAP_PAD3,
- .muxconfig = BOARD_SERCOM3_MUXCONFIG,
- .srcfreq = BOARD_SERCOM3_FREQUENCY,
- .base = SAM_SERCOM3_BASE,
- .spilock = SEM_INITIALIZER(1),
+ .irq = SAM_IRQ_SERCOM3,
+#endif
+ .gclkgen = BOARD_SERCOM3_GCLKGEN,
+ .slowgen = BOARD_SERCOM3_SLOW_GCLKGEN,
+ .pad0 = BOARD_SERCOM3_PINMAP_PAD0,
+ .pad1 = BOARD_SERCOM3_PINMAP_PAD1,
+ .pad2 = BOARD_SERCOM3_PINMAP_PAD2,
+ .pad3 = BOARD_SERCOM3_PINMAP_PAD3,
+ .muxconfig = BOARD_SERCOM3_MUXCONFIG,
+ .srcfreq = BOARD_SERCOM3_FREQUENCY,
+ .base = SAM_SERCOM3_BASE,
+ .spilock = SEM_INITIALIZER(1),
+#ifdef CONFIG_SAMDL_SPI_DMA
+ .dma_tx_trig = DMAC_TRIGSRC_SERCOM3_TX,
+ .dma_rx_trig = DMAC_TRIGSRC_SERCOM3_RX,
+#endif
};
#endif
@@ -406,21 +440,25 @@ static const struct spi_ops_s g_spi4ops =
static struct sam_spidev_s g_spi4dev =
{
- .ops = &g_spi4ops,
- .sercom = 4,
+ .ops = &g_spi4ops,
+ .sercom = 4,
#if 0 /* Not used */
- .irq = SAM_IRQ_SERCOM4,
-#endif
- .gclkgen = BOARD_SERCOM4_GCLKGEN,
- .slowgen = BOARD_SERCOM4_SLOW_GCLKGEN,
- .pad0 = BOARD_SERCOM4_PINMAP_PAD0,
- .pad1 = BOARD_SERCOM4_PINMAP_PAD1,
- .pad2 = BOARD_SERCOM4_PINMAP_PAD2,
- .pad3 = BOARD_SERCOM4_PINMAP_PAD3,
- .muxconfig = BOARD_SERCOM4_MUXCONFIG,
- .srcfreq = BOARD_SERCOM4_FREQUENCY,
- .base = SAM_SERCOM4_BASE,
- .spilock = SEM_INITIALIZER(1),
+ .irq = SAM_IRQ_SERCOM4,
+#endif
+ .gclkgen = BOARD_SERCOM4_GCLKGEN,
+ .slowgen = BOARD_SERCOM4_SLOW_GCLKGEN,
+ .pad0 = BOARD_SERCOM4_PINMAP_PAD0,
+ .pad1 = BOARD_SERCOM4_PINMAP_PAD1,
+ .pad2 = BOARD_SERCOM4_PINMAP_PAD2,
+ .pad3 = BOARD_SERCOM4_PINMAP_PAD3,
+ .muxconfig = BOARD_SERCOM4_MUXCONFIG,
+ .srcfreq = BOARD_SERCOM4_FREQUENCY,
+ .base = SAM_SERCOM4_BASE,
+ .spilock = SEM_INITIALIZER(1),
+#ifdef CONFIG_SAMDL_SPI_DMA
+ .dma_tx_trig = DMAC_TRIGSRC_SERCOM4_TX,
+ .dma_rx_trig = DMAC_TRIGSRC_SERCOM4_RX,
+#endif
};
#endif
@@ -452,21 +490,25 @@ static const struct spi_ops_s g_spi5ops =
static struct sam_spidev_s g_spi5dev =
{
- .ops = &g_spi5ops,
- .sercom = 5,
+ .ops = &g_spi5ops,
+ .sercom = 5,
#if 0 /* Not used */
- .irq = SAM_IRQ_SERCOM5,
-#endif
- .gclkgen = BOARD_SERCOM5_GCLKGEN,
- .slowgen = BOARD_SERCOM5_SLOW_GCLKGEN,
- .pad0 = BOARD_SERCOM5_PINMAP_PAD0,
- .pad1 = BOARD_SERCOM5_PINMAP_PAD1,
- .pad2 = BOARD_SERCOM5_PINMAP_PAD2,
- .pad3 = BOARD_SERCOM5_PINMAP_PAD3,
- .muxconfig = BOARD_SERCOM5_MUXCONFIG,
- .srcfreq = BOARD_SERCOM5_FREQUENCY,
- .base = SAM_SERCOM5_BASE,
- .spilock = SEM_INITIALIZER(1),
+ .irq = SAM_IRQ_SERCOM5,
+#endif
+ .gclkgen = BOARD_SERCOM5_GCLKGEN,
+ .slowgen = BOARD_SERCOM5_SLOW_GCLKGEN,
+ .pad0 = BOARD_SERCOM5_PINMAP_PAD0,
+ .pad1 = BOARD_SERCOM5_PINMAP_PAD1,
+ .pad2 = BOARD_SERCOM5_PINMAP_PAD2,
+ .pad3 = BOARD_SERCOM5_PINMAP_PAD3,
+ .muxconfig = BOARD_SERCOM5_MUXCONFIG,
+ .srcfreq = BOARD_SERCOM5_FREQUENCY,
+ .base = SAM_SERCOM5_BASE,
+ .spilock = SEM_INITIALIZER(1),
+#ifdef CONFIG_SAMDL_SPI_DMA
+ .dma_tx_trig = DMAC_TRIGSRC_SERCOM5_TX,
+ .dma_rx_trig = DMAC_TRIGSRC_SERCOM5_RX,
+#endif
};
#endif
@@ -944,7 +986,12 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
{
/* Yes... Set the mode appropriately */
+ /* First we need to disable SPI while we change the mode */
+
regval = spi_getreg32(priv, SAM_SPI_CTRLA_OFFSET);
+ spi_putreg32(priv, regval & ~SPI_CTRLA_ENABLE, SAM_SPI_CTRLA_OFFSET);
+ spi_wait_synchronization(priv);
+
regval &= ~(SPI_CTRLA_CPOL | SPI_CTRLA_CPHA);
switch (mode)
@@ -969,7 +1016,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
return;
}
- spi_putreg32(priv, regval, SAM_SPI_CTRLA_OFFSET);
+ spi_putreg32(priv, regval | SPI_CTRLA_ENABLE, SAM_SPI_CTRLA_OFFSET);
/* Save the mode so that subsequent re-configurations will be faster */
@@ -1056,6 +1103,45 @@ static uint16_t spi_send(struct spi_dev_s *dev, uint16_t wd)
return (uint16_t)rxbyte;
}
+/****************************************************************************
+ * Name: spi_dma_callback
+ *
+ * Description:
+ * DMA completion callback
+ *
+ * Input Parameters:
+ * dma - Allocate DMA handle
+ * arg - User argument provided with callback
+ * result - The result of the DMA operation
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAMDL_SPI_DMA
+static void spi_dma_callback(DMA_HANDLE dma, void *arg, int result)
+{
+ struct sam_spidev_s *priv = (struct sam_spidev_s *)arg;
+
+ if (dma == priv->dma_rx)
+ {
+ /* Notify the blocked spi_exchange() call that the transaction
+ * has completed by posting to the semaphore
+ */
+
+ nxsem_post(&priv->dmasem);
+ }
+ else if (dma == priv->dma_tx)
+ {
+ if (result != OK)
+ {
+ spierr("ERROR: DMA transmission failed: %d\n", result);
+ }
+ }
+}
+#endif
+
/****************************************************************************
* Name: spi_exchange
*
@@ -1084,6 +1170,47 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
void *rxbuffer, size_t nwords)
{
struct sam_spidev_s *priv = (struct sam_spidev_s *)dev;
+
+#ifdef CONFIG_SAMDL_SPI_DMA
+ uint32_t regval;
+ int ret;
+
+ spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
+
+ /* Disable SPI while we configure new DMA descriptors */
+
+ regval = spi_getreg32(priv, SAM_SPI_CTRLA_OFFSET);
+ regval &= ~SPI_CTRLA_ENABLE;
+ spi_putreg32(priv, regval, SAM_SPI_CTRLA_OFFSET);
+ spi_wait_synchronization(priv);
+
+ /* Setup RX and TX DMA channels */
+
+ sam_dmatxsetup(priv->dma_tx, priv->base + SAM_SPI_DATA_OFFSET,
+ (uint32_t)txbuffer, nwords);
+ sam_dmarxsetup(priv->dma_rx, priv->base + SAM_SPI_DATA_OFFSET,
+ (uint32_t)rxbuffer, nwords);
+
+ /* Start RX and TX DMA channels */
+
+ sam_dmastart(priv->dma_tx, spi_dma_callback, (void *)priv);
+ sam_dmastart(priv->dma_rx, spi_dma_callback, (void *)priv);
+
+ /* Enable SPI to trigger the TX DMA channel */
+
+ regval = spi_getreg32(priv, SAM_SPI_CTRLA_OFFSET);
+ regval |= SPI_CTRLA_ENABLE;
+ spi_putreg32(priv, regval, SAM_SPI_CTRLA_OFFSET);
+ spi_wait_synchronization(priv);
+
+ do
+ {
+ /* Wait for the DMA callback to notify us that the transfer is complete */
+
+ ret = nxsem_wait(&priv->dmasem);
+ }
+ while (ret < 0 && ret == -EINTR);
+#else
const uint16_t *ptx16;
const uint8_t *ptx8;
uint16_t *prx16;
@@ -1198,6 +1325,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
*prx16++ = (uint16_t)data;
}
}
+#endif
}
/****************************************************************************
@@ -1307,6 +1435,34 @@ static void spi_pad_configure(struct sam_spidev_s *priv)
}
}
+/****************************************************************************
+ * Name: spi_dma_setup
+ *
+ * Description:
+ * Configure the SPI DMA operation.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAMDL_SPI_DMA
+static void spi_dma_setup(struct sam_spidev_s *priv)
+{
+ /* Allocate a pair of DMA channels */
+
+ priv->dma_rx = sam_dmachannel(DMACH_FLAG_BEATSIZE_BYTE |
+ DMACH_FLAG_MEM_INCREMENT |
+ DMACH_FLAG_PERIPH_RXTRIG(priv->dma_rx_trig));
+
+ priv->dma_tx = sam_dmachannel(DMACH_FLAG_BEATSIZE_BYTE |
+ DMACH_FLAG_MEM_INCREMENT |
+ DMACH_FLAG_PERIPH_TXTRIG(priv->dma_tx_trig));
+
+ /* Initialize the semaphore used to notify when DMA is complete */
+
+ nxsem_init(&priv->dmasem, 0, 0);
+ nxsem_setprotocol(&priv->dmasem, SEM_PRIO_NONE);
+}
+#endif
+
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -1317,7 +1473,7 @@ static void spi_pad_configure(struct sam_spidev_s *priv)
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* port - SPI "port" number (i.e., SERCOM number)
*
* Returned Value:
@@ -1393,6 +1549,10 @@ struct spi_dev_s *sam_spibus_initialize(int port)
return NULL;
}
+#ifdef CONFIG_SAMDL_SPI_DMA
+ spi_dma_setup(priv);
+#endif
+
/* Enable clocking to the SERCOM module in PM */
flags = enter_critical_section();
@@ -1421,7 +1581,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
/* Set the SERCOM in SPI master mode (no address) */
regval = spi_getreg32(priv, SAM_SPI_CTRLA_OFFSET);
- regval &= ~SPI_CTRLA_MODE_MASK;
+ regval &= ~(SPI_CTRLA_MODE_MASK | SPI_CTRLA_FORM_MASK);
regval |= (SPI_CTRLA_MODE_MASTER | SPI_CTRLA_FORM_SPI);
spi_putreg32(priv, regval, SAM_SPI_CTRLA_OFFSET);
@@ -1435,11 +1595,13 @@ struct spi_dev_s *sam_spibus_initialize(int port)
(void)spi_setfrequency((struct spi_dev_s *)priv, 400000);
- /* Set MSB first data order and the configured pad mux setting,
- * Note that SPI mode 0 is assumed initially (CPOL=0 and CPHA=0).
+ /* Set MSB first data order and the configured pad mux setting.
+ * SPI mode 0 is assumed initially (CPOL=0 and CPHA=0).
*/
- regval = (SPI_CTRLA_MSBFIRST | priv->muxconfig);
+ regval &= ~(SPI_CTRLA_DOPO_MASK | SPI_CTRLA_DIPO_MASK);
+ regval &= ~(SPI_CTRLA_CPHA | SPI_CTRLA_CPOL);
+ regval |= (SPI_CTRLA_MSBFIRST | priv->muxconfig);
spi_putreg32(priv, regval, SAM_SPI_CTRLA_OFFSET);
/* Enable the receiver. Note that 8-bit data width is assumed initially */
diff --git a/arch/arm/src/samdl/sam_spi.h b/arch/arm/src/samdl/sam_spi.h
index 7e0cbfa9e08d53a0167294d39bd9b3230b622b65..d4044ab19cd820f282e662c23ba129c1fd9462a3 100644
--- a/arch/arm/src/samdl/sam_spi.h
+++ b/arch/arm/src/samdl/sam_spi.h
@@ -94,7 +94,7 @@ struct spi_dev_s; /* Forward reference */
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* port - SPI "port" number (i.e., SERCOM number)
*
* Returned Value:
@@ -161,7 +161,7 @@ struct spi_dev_s *sam_spibus_initialize(int port);
* devid - Identifies the (logical) device
* selected - TRUE:Select the device, FALSE:De-select the device
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -206,7 +206,7 @@ void sam_spi5select(FAR struct spi_dev_s *dev, uint32_t devid,
* dev - SPI device info
* devid - Identifies the (logical) device
*
- * Returned Values:
+ * Returned Value:
* Bit-encoded SPI status (see include/nuttx/spi/spi.h.
*
****************************************************************************/
@@ -254,7 +254,7 @@ uint8_t sam_spi5status(FAR struct spi_dev_s *dev, uint32_t devid);
* dev - SPI device info
* devid - Identifies the (logical) device
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno on failure.
*
****************************************************************************/
diff --git a/arch/arm/src/samdl/sam_usb.c b/arch/arm/src/samdl/sam_usb.c
index 02521250738660b96e16f7aa4eca7ebf1fa05ce8..2132fec4b70d3397b4f8f25640682f92e169807c 100644
--- a/arch/arm/src/samdl/sam_usb.c
+++ b/arch/arm/src/samdl/sam_usb.c
@@ -107,17 +107,13 @@
#include "up_arch.h"
#include "up_internal.h"
-#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
- #include "samd_periphclks.h"
-#elif defined(CONFIG_ARCH_FAMILY_SAML21)
- #include "saml_periphclks.h"
-#endif
-
#include "sam_gclk.h"
#include "chip.h"
#include "sam_port.h"
#include "sam_pinmap.h"
#include "sam_usb.h"
+#include "sam_fuses.h"
+#include "sam_periphclks.h"
#if defined(CONFIG_USBHOST) && defined(CONFIG_SAMDL_USB)
# error USBHOST mode not yet implemented!
@@ -321,7 +317,6 @@ struct sam_rqhead_s
struct sam_req_s *tail; /* Requests are removed from the tail of the list */
};
-
/* This is the internal representation of an endpoint */
struct sam_ep_s
@@ -2476,8 +2471,6 @@ static void sam_ep0_dispatch(struct sam_usbdev_s *priv)
static void sam_setdevaddr(struct sam_usbdev_s *priv, uint8_t address)
{
- uint32_t regval;
-
DEBUGASSERT(address <= 0x7f);
if (address)
{
@@ -3435,6 +3428,8 @@ static int sam_usb_interrupt(int irq, void *context, void *arg)
uwarn("WARNING: Unhandled_EP:0x%X\n", pendingep);
}
#endif
+
+ return OK;
}
void up_usbuninitialize(void)
@@ -3491,7 +3486,7 @@ errout:
/****************************************************************************
* Name: sam_ep_reset
*
- * Description
+ * Description:
* Reset and disable one endpoints.
*
****************************************************************************/
@@ -3528,7 +3523,7 @@ static void sam_ep_reset(struct sam_usbdev_s *priv, uint8_t epno)
/****************************************************************************
* Name: sam_epset_reset
*
- * Description
+ * Description:
* Reset and disable a set of endpoints.
*
****************************************************************************/
@@ -3782,6 +3777,10 @@ static void sam_hw_setup(struct sam_usbdev_s *priv)
uint16_t regval;
uint32_t padcalib;
+ uint8_t calib_transn;
+ uint8_t calib_transp;
+ uint8_t calib_trim;
+
/* To use the USB, the programmer must first configure the USB clock
* input,
*/
@@ -3792,11 +3791,21 @@ static void sam_hw_setup(struct sam_usbdev_s *priv)
sam_ctrla_write(USB_CTRLA_SWRST);
- /* TODO: load PAD calibration from NVM or ...
- * now using default values
- */
+ /* Load USB factory calibration values from NVRAM */
+
+ calib_transn = getreg32(SYSCTRL_FUSES_USBTRANSN_ADDR) &
+ SYSCTRL_FUSES_USBTRANSN_MASK >> SYSCTRL_FUSES_USBTRANSN_SHIFT;
+
+ calib_transp = getreg32(SYSCTRL_FUSES_USBTRANSP_ADDR) &
+ SYSCTRL_FUSES_USBTRANSP_MASK >> SYSCTRL_FUSES_USBTRANSP_SHIFT;
+
+ calib_trim = getreg32(SYSCTRL_FUSES_USBTRIM_ADDR) &
+ SYSCTRL_FUSES_USBTRIM_MASK >> SYSCTRL_FUSES_USBTRIM_SHIFT;
+
+ padcalib = USB_PADCAL_TRANSP(calib_transp) |
+ USB_PADCAL_TRANSN(calib_transn) |
+ USB_PADCAL_TRIM(calib_trim);
- padcalib = USB_PADCAL_TRANSP(29) | USB_PADCAL_TRANSN(5) | USB_PADCAL_TRIM(3);
sam_putreg32(padcalib, SAM_USB_PADCAL);
/* set config
@@ -3866,8 +3875,6 @@ static void sam_hw_setup(struct sam_usbdev_s *priv)
static void sam_hw_shutdown(struct sam_usbdev_s *priv)
{
- uint16_t regval;
-
priv->usbdev.speed = USB_SPEED_UNKNOWN;
/* Disable all interrupts */
diff --git a/arch/arm/src/samdl/samd_clockconfig.c b/arch/arm/src/samdl/samd_clockconfig.c
index a17c30235c8b0397dd5dd8342cb2a9717fb3dfd7..87f9bfd0d99cf4f2fe9174f988859c4c7713d234 100644
--- a/arch/arm/src/samdl/samd_clockconfig.c
+++ b/arch/arm/src/samdl/samd_clockconfig.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/samdl/samd_clockconfig.c
*
- * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014-2015, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* References:
@@ -453,11 +453,10 @@ static inline void sam_osc32k_config(void)
regval = getreg32(SYSCTRL_FUSES_OSC32KCAL_ADDR);
calib = (regval & SYSCTRL_FUSES_OSC32KCAL_MASK) >> SYSCTRL_FUSES_OSC32KCAL_SHIFT;
- regval = calib << SYSCTRL_OSC32K_CALIB_SHIFT;
/* Configure OSC32K */
- regval |= BOARD_OSC32K_STARTUPTIME;
+ regval = BOARD_OSC32K_STARTUPTIME;
#ifdef BOARD_OSC32K_EN1KHZ
regval |= SYSCTRL_OSC32K_EN1K;
@@ -481,6 +480,18 @@ static inline void sam_osc32k_config(void)
regval |= SYSCTRL_OSC32K_ENABLE;
putreg32(regval, SAM_SYSCTRL_OSC32K);
+
+ /* From the datasheet on page 157:
+ * "When writing to the Calibration bits, the user must wait for the
+ * PCLKSR.OSC32KRDY bit to go high before the value is committed
+ * to the oscillator."
+ */
+
+ while ((getreg32(SAM_SYSCTRL_PCLKSR) & SYSCTRL_INT_OSC32KRDY) == 0);
+
+ regval = getreg32(SAM_SYSCTRL_OSC32K);
+ regval |= calib << SYSCTRL_OSC32K_CALIB_SHIFT;
+ putreg32(regval, SAM_SYSCTRL_OSC32K);
}
#else
# define sam_osc32k_config()
@@ -556,6 +567,91 @@ static inline void sam_osc8m_config(void)
putreg32(regval, SAM_SYSCTRL_OSC8M);
}
+#ifdef BOARD_DPLL_ENABLE
+static inline void sam_dpll_config(void)
+{
+ uint8_t ctrla;
+ uint32_t ctrlb;
+ uint32_t ratio;
+
+ ctrla = SYSCTRL_DPLLCTRLA_ENABLE; /* Enable the FDPLL */
+ ctrlb = 0;
+ ratio = 0;
+
+#ifdef BOARD_DPLL_RUNINSTANDBY
+ ctrla |= SYSCTRL_DPLLCTRLA_RUNSTDBY; /* Run in standby */
+#endif
+
+#ifdef BOARD_DPLL_ONDEMAND
+ ctrla |= SYSCTRL_DPLLCTRLA_ONDEMAND; /* On demand mode */
+#endif
+
+#ifdef BOARD_DPLL_DIV
+ ctrlb |= SYSCTRL_DPLLCTRLB_DIV(BOARD_DPLL_DIV);
+#endif
+
+#ifdef BOARD_DPLL_LBYPASS
+ ctrlb |= SYSCTRL_DPLLCTRLB_LBYPASS;
+#endif
+
+#ifdef BOARD_DPLL_LTIME
+ ctrlb |= BOARD_DPLL_LTIME;
+#endif
+
+#ifdef BOARD_DPLL_REFCLK
+ ctrlb |= BOARD_DPLL_REFCLK;
+ ratio = SYSCTRL_DPLLRATIO_LDR(BOARD_DPLL_LDR);
+#ifdef BOARD_DPLL_LDRFRAC
+ ratio |= SYSCTRL_DPLLRATIO_LDRFRAC(BOARD_DPLL_LDRFRAC);
+#endif
+
+ /* If a GCLK reference was requested, we must initialize the GCLK first */
+
+ if (BOARD_DPLL_REFCLK == SYSCTRL_DPLLCTRLB_REFCLK_GCLKDPLL)
+ {
+ putreg16(GCLK_CLKCTRL_ID_DPLL | GCLK_CLKCTRL_GEN(2) | GCLK_CLKCTRL_CLKEN, SAM_GCLK_CLKCTRL);
+ }
+
+ putreg32(ratio, SAM_SYSCTRL_DPLLRATIO);
+#else
+
+ /* If no reference clock was specified, default to using
+ * the external 32KHz crystal and output of 96MHz
+ */
+
+ ctrlb |= SYSCTRL_DPLLCTRLB_REFCLK_XOSC32;
+ ratio = SYSCTRL_DPLLRATIO_LDR(3000);
+ putreg32(ratio, SAM_SYSCTRL_DPLLRATIO);
+#endif
+
+#ifdef BOARD_DPLL_WUF
+ ctrlb |= BOARD_DPLL_WUF;
+#endif
+
+#ifdef BOARD_DPLL_LPEN
+ ctrlb |= BOARD_DPLL_LPEN;
+#endif
+
+#ifdef BOARD_DPLL_FILTER
+ ctrlb |= BOARD_DPLL_FILTER;
+#endif
+
+ /* Write Control B register */
+
+ putreg32(ctrlb, SAM_SYSCTRL_DPLLCTRLB);
+
+ /* Write Control A register */
+
+ putreg8(ctrla, SAM_SYSCTRL_DPLLCTRLA);
+
+ /* Wait for the DPLL to synchronize */
+
+ while ((getreg8(SAM_SYSCTRL_DPLLSTATUS) & SYSCTRL_DPLLSTATUS_CLKRDY) == 0);
+}
+#else
+# define sam_dpll_config()
+#endif
+
/****************************************************************************
* Name: sam_dfll_config
*
@@ -866,10 +962,12 @@ void sam_clockconfig(void)
/* Configure XOSC */
+ putreg16(0, SAM_SYSCTRL_XOSC);
sam_xosc_config();
/* Configure XOSC32K */
+ putreg16(0, SAM_SYSCTRL_XOSC32K);
sam_xosc32k_config();
/* Configure OSCK32K */
@@ -884,6 +982,10 @@ void sam_clockconfig(void)
sam_osc8m_config();
+ /* Configure DPLL */
+
+ sam_dpll_config();
+
/* Configure GCLK(s) */
sam_config_gclks();
diff --git a/arch/arm/src/samdl/samd_periphclks.h b/arch/arm/src/samdl/samd_periphclks.h
index 0ba3df0f879d10e4c79dc50a1e4c97bc5103dd4d..0130cb6372cf61c94d5a71314ca4c0f6c3879a6c 100644
--- a/arch/arm/src/samdl/samd_periphclks.h
+++ b/arch/arm/src/samdl/samd_periphclks.h
@@ -75,7 +75,7 @@
#define sam_apbc_enableperiph(s) modifyreg32(SAM_PM_APBCMASK,0,s)
#define sam_pac2_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_PAC2)
-#define sam_devsys_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_EVSYS)
+#define sam_evsys_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_EVSYS)
#define sam_sercom_enableperiph(n) sam_apbc_enableperiph(PM_APBCMASK_SERCOM(n))
#define sam_sercom0_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_SERCOM0)
#define sam_sercom1_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_SERCOM1)
@@ -107,7 +107,7 @@
#define sam_ptc_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_PTC)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
-# define sam_i2s_enableperiph() sam_apbc_enableperiph(PM_APBBMASK_I2S)
+# define sam_i2s_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_I2S)
#endif
#define sam_apba_disableperiph(s) modifyreg32(SAM_PM_APBAMASK,s,0)
@@ -135,7 +135,7 @@
#define sam_apbc_disableperiph(s) modifyreg32(SAM_PM_APBCMASK,s,0)
#define sam_pac2_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_PAC2)
-#define sam_devsys_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_EVSYS)
+#define sam_evsys_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_EVSYS)
#define sam_sercom_disableperiph(n) sam_apbc_disableperiph(PM_APBCMASK_SERCOM(n))
#define sam_sercom0_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_SERCOM0)
#define sam_sercom1_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_SERCOM1)
@@ -167,7 +167,7 @@
#define sam_ptc_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_PTC)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
-# define sam_i2s_disableperiph() sam_apbc_disableperiph(PM_APBBMASK_I2S)
+# define sam_i2s_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_I2S)
#endif
#define sam_apba_isenabled(s) (getreg32(SAM_PM_APBAMASK) & (s)) != 0)
@@ -195,7 +195,7 @@
#define sam_apbc_isenabled(s) (getreg32(SAM_PM_APBCMASK) & (s)) != 0)
#define sam_pac2_isenabled() sam_apbc_isenabled(PM_APBCMASK_PAC2)
-#define sam_devsys_isenabled() sam_apbc_isenabled(PM_APBCMASK_EVSYS)
+#define sam_evsys_isenabled() sam_apbc_isenabled(PM_APBCMASK_EVSYS)
#define sam_sercom_isenabled(n) sam_apbc_isenabled(PM_APBCMASK_SERCOM(n))
#define sam_sercom0_isenabled() sam_apbc_isenabled(PM_APBCMASK_SERCOM0)
#define sam_sercom1_isenabled() sam_apbc_isenabled(PM_APBCMASK_SERCOM1)
@@ -227,7 +227,7 @@
#define sam_ptc_isenabled() sam_apbc_isenabled(PM_APBCMASK_PTC)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
-# define sam_i2s_isenabled() sam_apbc_isenabled(PM_APBBMASK_I2S)
+# define sam_i2s_isenabled() sam_apbc_isenabled(PM_APBCMASK_I2S)
#endif
/****************************************************************************
diff --git a/arch/arm/src/samdl/saml_clockconfig.c b/arch/arm/src/samdl/saml_clockconfig.c
index 364933501d5a5269d1349111dabdc56352a1e9c2..f32166ee49b0b2e0b5d06afb8c21d415253aa602 100644
--- a/arch/arm/src/samdl/saml_clockconfig.c
+++ b/arch/arm/src/samdl/saml_clockconfig.c
@@ -74,6 +74,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* BOARD_GCLK_ENABLE looks optional, but it is not */
#ifndef BOARD_GCLK_ENABLE
@@ -140,6 +141,7 @@ static inline void sam_periph_clocks(void);
/****************************************************************************
* Private Data
****************************************************************************/
+
/* This structure describes the configuration of every enabled GCLK */
#ifdef BOARD_GCLK_ENABLE
diff --git a/arch/arm/src/samv7/Make.defs b/arch/arm/src/samv7/Make.defs
index fe5ab20b2c6d69e2dbe483b61d9c7908766b7540..f7d4f3fb6b051d83e95a4df4fc2d34a9b40ac46f 100644
--- a/arch/arm/src/samv7/Make.defs
+++ b/arch/arm/src/samv7/Make.defs
@@ -44,7 +44,7 @@ CMN_UASRCS =
CMN_UCSRCS =
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
-CMN_ASRCS += up_testset.S vfork.S
+CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S
CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c
CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_idle.c up_initialize.c
CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_memfault.c up_modifyreg8.c
diff --git a/arch/arm/src/samv7/sam_config.h b/arch/arm/src/samv7/sam_config.h
index 05e6db84f1182e710e090c3ab61c54543fe350da..f9e37ac3f377eaf01a97295330bc443fed69d393 100644
--- a/arch/arm/src/samv7/sam_config.h
+++ b/arch/arm/src/samv7/sam_config.h
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/samv7/sam-config.h
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -144,7 +144,11 @@
# undef CONFIG_SAMV7_USART2
#endif
-/* Are any USARTs enabled? */
+/* Are any USARTs enabled?
+ *
+ * REVISIT: Setting HAVE_UART_DEVICE only makes sense of the USART is being
+ * used as a UART.
+ */
#if defined(CONFIG_SAMV7_USART0) || defined(CONFIG_SAMV7_USART1) || \
defined(CONFIG_SAMV7_USART2)
diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c
index 3496331898c0bc293b6209cbba1edee8c5d05684..94c5956b2bd199a5be8822c012f0e5f27468fddb 100644
--- a/arch/arm/src/samv7/sam_emac.c
+++ b/arch/arm/src/samv7/sam_emac.c
@@ -2,7 +2,7 @@
* arch/arm/src/samv7/sam_emac.c
* 10/100 Base-T Ethernet driver for the SAMV71.
*
- * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015, 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* This logic derives from the SAMA5 Ethernet driver which, in turn, derived
@@ -622,7 +622,7 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac);
static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac);
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg);
#endif
@@ -3196,86 +3196,90 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
*
****************************************************************************/
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
{
+#ifdef CONFIG_NETDEV_PHY_IOCTL
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
+#endif
int ret;
switch (cmd)
- {
+ {
+#ifdef CONFIG_NETDEV_PHY_IOCTL
#ifdef CONFIG_ARCH_PHY_INTERRUPT
case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
- struct mii_iotcl_notify_s *req = (struct mii_iotcl_notify_s *)((uintptr_t)arg);
+ struct mii_iotcl_notify_s *req = (struct mii_iotcl_notify_s *)((uintptr_t)arg);
- ret = phy_notify_subscribe(dev->d_ifname, req->pid, req->signo, req->arg);
- if (ret == OK)
- {
- /* Enable PHY link up/down interrupts */
+ ret = phy_notify_subscribe(dev->d_ifname, req->pid, req->signo, req->arg);
+ if (ret == OK)
+ {
+ /* Enable PHY link up/down interrupts */
- ret = sam_phyintenable(priv);
+ ret = sam_phyintenable(priv);
+ }
}
- }
- break;
+ break;
#endif
- case SIOCGMIIPHY: /* Get MII PHY address */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- req->phy_id = priv->phyaddr;
- ret = OK;
- }
- break;
+ case SIOCGMIIPHY: /* Get MII PHY address */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ req->phy_id = priv->phyaddr;
+ ret = OK;
+ }
+ break;
- case SIOCGMIIREG: /* Get register from MII PHY */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- uint32_t regval;
+ case SIOCGMIIREG: /* Get register from MII PHY */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ uint32_t regval;
- /* Enable management port */
+ /* Enable management port */
- regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
- sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval | EMAC_NCR_MPE);
+ regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
+ sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval | EMAC_NCR_MPE);
- /* Read from the requested register */
+ /* Read from the requested register */
- ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
+ ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
- /* Disable management port (probably) */
+ /* Disable management port (probably) */
- sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
- }
- break;
+ sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
+ }
+ break;
- case SIOCSMIIREG: /* Set register in MII PHY */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- uint32_t regval;
+ case SIOCSMIIREG: /* Set register in MII PHY */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ uint32_t regval;
- /* Enable management port */
+ /* Enable management port */
- regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
- sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval | EMAC_NCR_MPE);
+ regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
+ sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval | EMAC_NCR_MPE);
- /* Write to the requested register */
+ /* Write to the requested register */
- ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
+ ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
- /* Disable management port (probably) */
+ /* Disable management port (probably) */
- sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
- }
- break;
+ sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
+ }
+ break;
+#endif /* CONFIG_NETDEV_PHY_IOCTL */
- default:
- ret = -ENOTTY;
- break;
- }
+ default:
+ ret = -ENOTTY;
+ break;
+ }
return ret;
}
-#endif /* CONFIG_NETDEV_PHY_IOCTL */
+#endif /* CONFIG_NETDEV_IOCTL */
/****************************************************************************
* Function: sam_phydump
@@ -5017,9 +5021,9 @@ int sam_emac_initialize(int intf)
priv->dev.d_addmac = sam_addmac; /* Add multicast MAC address */
priv->dev.d_rmmac = sam_rmmac; /* Remove multicast MAC address */
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = sam_ioctl; /* Support PHY ioctl() calls */
-#ifdef CONFIG_ARCH_PHY_INTERRUPT
+#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
priv->phytype = phytype; /* Type of PHY on port */
#endif
#endif
diff --git a/arch/arm/src/samv7/sam_hsmci.c b/arch/arm/src/samv7/sam_hsmci.c
index b6df58bc1818ca18168cfb99a6d95d3d1926c38e..213be4f878649dd8b6be4002eddfe1d5282aeea8 100644
--- a/arch/arm/src/samv7/sam_hsmci.c
+++ b/arch/arm/src/samv7/sam_hsmci.c
@@ -2791,7 +2791,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev,
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay, (wdentry_t)sam_eventtimeout,
1, (uint32_t)priv);
- if (ret != OK)
+ if (ret < 0)
{
mcerr("ERROR: wd_start failed: %d\n", ret);
}
@@ -3234,7 +3234,7 @@ static void sam_callback(void *arg)
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
@@ -3385,7 +3385,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
@@ -3438,7 +3438,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is write protected.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/samv7/sam_hsmci.h b/arch/arm/src/samv7/sam_hsmci.h
index fa5992082dacfc7bc58f3334ec5d05371440a315..990ce462d5f6cf968d092fbc2f9b2d25103d13eb 100644
--- a/arch/arm/src/samv7/sam_hsmci.h
+++ b/arch/arm/src/samv7/sam_hsmci.h
@@ -85,7 +85,7 @@ extern "C"
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
@@ -116,7 +116,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno);
* bootloader that brought us into SDRAM and it is that bootloader that
* has configured the clocking.
*
- * Input parameters:
+ * Input Parameters:
* target - The target SD frequency
*
* Returned Value:
@@ -141,7 +141,7 @@ uint32_t sam_hsmci_clkdiv(uint32_t target);
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -159,7 +159,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is writeprotected.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/samv7/sam_hsmci_clkdiv.c b/arch/arm/src/samv7/sam_hsmci_clkdiv.c
index 83b85b6cb691eb54288cac59909168177000356b..0da38726216a29be83e057670f927bdff92d004f 100644
--- a/arch/arm/src/samv7/sam_hsmci_clkdiv.c
+++ b/arch/arm/src/samv7/sam_hsmci_clkdiv.c
@@ -96,7 +96,7 @@
* bootloader that brought us into SDRAM and it is that bootloader that
* has configured the clocking.
*
- * Input parameters:
+ * Input Parameters:
* target - The target SD frequency
*
* Returned Value:
diff --git a/arch/arm/src/samv7/sam_lowputc.c b/arch/arm/src/samv7/sam_lowputc.c
index c9d4b6e9ce5d541a3b273f85d8475437dbfe5dd6..614a9defd9ca6ec9d3cea56985b8f6eed2d6ffa5 100644
--- a/arch/arm/src/samv7/sam_lowputc.c
+++ b/arch/arm/src/samv7/sam_lowputc.c
@@ -172,26 +172,6 @@
#endif /* HAVE_SERIAL_CONSOLE */
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -277,6 +257,9 @@ void sam_lowsetup(void)
uint64_t divb3;
uint32_t intpart;
uint32_t fracpart;
+#endif
+#if (defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)) || \
+ defined(CONFIG_SAMV7_USART1)
uint32_t regval;
#endif
diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c
index e72d089dc73b5bad66367532dda5a48769575ffd..5be48501d1b8d015ad744d0b1c2e8327725cff9c 100644
--- a/arch/arm/src/samv7/sam_mcan.c
+++ b/arch/arm/src/samv7/sam_mcan.c
@@ -1609,7 +1609,7 @@ static void mcan_buffer_release(FAR struct sam_mcan_s *priv)
* standard CAN. In CAN FD mode, the values 9 to 15 are encoded to values
* in the range 12 to 64.
*
- * Input Parameter:
+ * Input Parameters:
* dlc - the DLC value to convert to a byte count
*
* Returned Value:
@@ -1665,7 +1665,7 @@ static uint8_t mcan_dlc2bytes(FAR struct sam_mcan_s *priv, uint8_t dlc)
* standard CAN. In CAN FD mode, the values 9 to 15 are encoded to values
* in the range 12 to 64.
*
- * Input Parameter:
+ * Input Parameters:
* nbytes - the byte count to convert to a DLC value
*
* Returned Value:
@@ -3649,7 +3649,7 @@ static int mcan_interrupt(int irq, void *context, FAR void *arg)
* Description:
* MCAN hardware initialization
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this MCAN peripheral
*
* Returned Value:
@@ -3924,7 +3924,7 @@ static int mcan_hw_initialize(struct sam_mcan_s *priv)
* Description:
* Initialize the selected MCAN port
*
- * Input Parameter:
+ * Input Parameters:
* port - Port number (for hardware that has multiple MCAN interfaces),
* 0=MCAN0, 1=MCAN1
*
diff --git a/arch/arm/src/samv7/sam_mcan.h b/arch/arm/src/samv7/sam_mcan.h
index 3672547788ac9fdfc7b7a757f38eb46f253d30eb..0c5dc6c7260093c1c99c5f26580407061f727907 100644
--- a/arch/arm/src/samv7/sam_mcan.h
+++ b/arch/arm/src/samv7/sam_mcan.h
@@ -88,7 +88,7 @@ extern "C"
* Description:
* Initialize the selected MCAN port
*
- * Input Parameter:
+ * Input Parameters:
* port - Port number (for hardware that has multiple CAN interfaces),
* 0=MCAN0, 1=NCAN1
*
diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c
index e2ff6dea79485ba253ed420c81f24a104d7a0040..6e39c7f8e3ead114f98712705383e9a67aec2832 100644
--- a/arch/arm/src/samv7/sam_qspi.c
+++ b/arch/arm/src/samv7/sam_qspi.c
@@ -885,7 +885,7 @@ static int qspi_memory_dma(struct sam_qspidev_s *priv,
ret = wd_start(priv->dmadog, DMA_TIMEOUT_TICKS,
(wdentry_t)qspi_dma_timeout, 1, (uint32_t)priv);
- if (ret != OK)
+ if (ret < 0)
{
spierr("ERROR: wd_start failed: %d\n", ret);
}
@@ -1714,7 +1714,7 @@ static int qspi_hw_initialize(struct sam_qspidev_s *priv)
* Description:
* Initialize the selected QSPI port in master mode
*
- * Input Parameter:
+ * Input Parameters:
* intf - Interface number(must be zero)
*
* Returned Value:
@@ -1737,7 +1737,7 @@ struct qspi_dev_s *sam_qspi_initialize(int intf)
#ifdef CONFIG_SAMV7_QSPI
if (intf == 0)
{
- /* If this function is called multiple times, the following operatinos
+ /* If this function is called multiple times, the following operations
* will be performed multiple times.
*/
diff --git a/arch/arm/src/samv7/sam_qspi.h b/arch/arm/src/samv7/sam_qspi.h
index 85d2e57d6594a7a4984d1b14b3337b2e11e659b3..9b64f0531cb454e41e1363188b49b03c365e58e0 100644
--- a/arch/arm/src/samv7/sam_qspi.h
+++ b/arch/arm/src/samv7/sam_qspi.h
@@ -87,7 +87,7 @@ extern "C"
* Description:
* Initialize the selected QSPI port in master mode
*
- * Input Parameter:
+ * Input Parameters:
* intf - Interface number(must be zero)
*
* Returned Value:
diff --git a/arch/arm/src/samv7/sam_rswdt.c b/arch/arm/src/samv7/sam_rswdt.c
index 6d5add03a23ac158e16eb569deb6ed4c4e1b885b..5651e612ee4eabc69c4ba399fec537478ab991ba 100644
--- a/arch/arm/src/samv7/sam_rswdt.c
+++ b/arch/arm/src/samv7/sam_rswdt.c
@@ -254,7 +254,7 @@ static void sam_putreg(uint32_t regval, uintptr_t regaddr)
* Input Parameters:
* Usual interrupt handler arguments.
*
- * Returned Values:
+ * Returned Value:
* Always returns OK.
*
****************************************************************************/
@@ -290,7 +290,7 @@ static int sam_interrupt(int irq, FAR void *context, FAR void *arg)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -320,7 +320,7 @@ static int sam_start(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -350,7 +350,7 @@ static int sam_stop(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -378,7 +378,7 @@ static int sam_keepalive(FAR struct watchdog_lowerhalf_s *lower)
* driver state structure.
* stawtus - The location to return the watchdog status information.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -435,7 +435,7 @@ static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower,
* driver state structure.
* timeout - The new timeout value in millisecnds.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -554,7 +554,7 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* function pointer is NULL, then the reset-on-expiration
* behavior is restored,
*
- * Returned Values:
+ * Returned Value:
* The previous watchdog expiration function pointer or NULL is there was
* no previous function pointer, i.e., if the previous behavior was
* reset-on-expiration (NULL is also returned if an error occurs).
@@ -619,7 +619,7 @@ static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower,
* interpretation of this argument depends on the particular
* command.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -649,7 +649,7 @@ static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
* Input Parameters:
* None
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c
index e45fac7d000cdce30a345b71313e11b715dffcfb..0f4a52c90434484d9d1492fe8fb376c56d0f4e63 100644
--- a/arch/arm/src/samv7/sam_spi.c
+++ b/arch/arm/src/samv7/sam_spi.c
@@ -1864,7 +1864,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
ret = wd_start(spics->dmadog, DMA_TIMEOUT_TICKS,
(wdentry_t)spi_dmatimeout, 1, (uint32_t)spics);
- if (ret != OK)
+ if (ret < 0)
{
spierr("ERROR: wd_start failed: %d\n", ret);
}
@@ -1985,7 +1985,7 @@ static void spi_recvblock(struct spi_dev_s *dev, void *buffer, size_t nwords)
* Description:
* Initialize the selected SPI port in master mode
*
- * Input Parameter:
+ * Input Parameters:
* cs - Chip select number (identifying the "logical" SPI port)
*
* Returned Value:
diff --git a/arch/arm/src/samv7/sam_spi.h b/arch/arm/src/samv7/sam_spi.h
index 6e5a76e9ef6276dee67e52080a161f03a72a5e13..e7e715fd38a04b6d902a95de141a4766d845f854 100644
--- a/arch/arm/src/samv7/sam_spi.h
+++ b/arch/arm/src/samv7/sam_spi.h
@@ -166,7 +166,7 @@ struct spi_sctrlr_s; /* Forward reference */
* Description:
* Initialize the selected SPI port in master mode
*
- * Input Parameter:
+ * Input Parameters:
* cs - Chip select number (identifying the "logical" SPI port)
*
* Returned Value:
@@ -182,7 +182,7 @@ FAR struct spi_dev_s *sam_spibus_initialize(int port);
* Description:
* Initialize the selected SPI port in slave mode.
*
- * Input Parameter:
+ * Input Parameters:
* port - Chip select number identifying the "logical" SPI port. Includes
* encoded port and chip select information.
*
@@ -248,7 +248,7 @@ FAR struct spi_sctrlr_s *sam_spi_slave_initialize(int port);
* devid - Identifies the (logical) device
* selected - TRUE:Select the device, FALSE:De-select the device
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -270,7 +270,7 @@ void sam_spi1select(uint32_t devid, bool selected);
* dev - SPI device info
* devid - Identifies the (logical) device
*
- * Returned Values:
+ * Returned Value:
* Bit-encoded SPI status (see include/nuttx/spi/spi.h.
*
****************************************************************************/
@@ -301,7 +301,7 @@ uint8_t sam_spi1status(FAR struct spi_dev_s *dev, uint32_t devid);
* dev - SPI device info
* devid - Identifies the (logical) device
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno on failure.
*
****************************************************************************/
diff --git a/arch/arm/src/samv7/sam_spi_slave.c b/arch/arm/src/samv7/sam_spi_slave.c
index 19473aa05c553be46c34fbf85506ef5e4dfa0bea..77a2cf67326b67533e458f1230d023a28ea7940c 100644
--- a/arch/arm/src/samv7/sam_spi_slave.c
+++ b/arch/arm/src/samv7/sam_spi_slave.c
@@ -1059,7 +1059,7 @@ static void spi_qflush(struct spi_sctrlr_s *sctrlr)
* Description:
* Initialize the selected SPI port in slave mode.
*
- * Input Parameter:
+ * Input Parameters:
* port - Chip select number identifying the "logical" SPI port. Includes
* encoded port and chip select information.
*
diff --git a/arch/arm/src/samv7/sam_ssc.c b/arch/arm/src/samv7/sam_ssc.c
index bb1114c44493d94a9811017ff85659cb4930715b..8d56ff8f383b69d7df6d1f849d795bf9221679c0 100644
--- a/arch/arm/src/samv7/sam_ssc.c
+++ b/arch/arm/src/samv7/sam_ssc.c
@@ -2765,7 +2765,7 @@ static int ssc_tx_configure(struct sam_ssc_s *priv)
* Setup the MCK/2 divider based on the currently selected data width and
* the sample rate
*
- * Input Parameter:
+ * Input Parameters:
* priv - I2C device structure (only the sample rate and data length is
* needed at this point).
*
@@ -2822,7 +2822,7 @@ static uint32_t ssc_mck2divider(struct sam_ssc_s *priv)
* Description:
* Enable and configure clocking to the SSC
*
- * Input Parameter:
+ * Input Parameters:
* priv - Partially initialized I2C device structure (only the PID is
* needed at this point).
*
@@ -3370,7 +3370,7 @@ static void ssc1_configure(struct sam_ssc_s *priv)
* Description:
* Initialize the selected SSC port
*
- * Input Parameter:
+ * Input Parameters:
* port - I2S "port" number (identifying the "logical" SSC port)
*
* Returned Value:
diff --git a/arch/arm/src/samv7/sam_ssc.h b/arch/arm/src/samv7/sam_ssc.h
index 567b655c3629a7bf11d8675f67abc83157d5f7af..0db57fe3615de9a14d1b7c0a902eb931f5a03d3f 100644
--- a/arch/arm/src/samv7/sam_ssc.h
+++ b/arch/arm/src/samv7/sam_ssc.h
@@ -82,7 +82,7 @@ extern "C"
* Description:
* Initialize the selected I2S port.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple I2S interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/samv7/sam_twihs.c b/arch/arm/src/samv7/sam_twihs.c
index 261357c618df9f641c81d2ad56a77101f21bf8d9..6c2d36b291ed16fa663ee230cc52930aa5365e97 100644
--- a/arch/arm/src/samv7/sam_twihs.c
+++ b/arch/arm/src/samv7/sam_twihs.c
@@ -491,7 +491,8 @@ static int twi_wait(struct twi_dev_s *priv, unsigned int size)
* TWIHS transfer stalls.
*/
- wd_start(priv->timeout, (timeout * size), twi_timeout, 1, (uint32_t)priv);
+ (void)wd_start(priv->timeout, (timeout * size), twi_timeout, 1,
+ (uint32_t)priv);
/* Wait for either the TWIHS transfer or the timeout to complete */
diff --git a/arch/arm/src/samv7/sam_twihs.h b/arch/arm/src/samv7/sam_twihs.h
index 79f85a70e3894e6ddfc9afe708b496d90905b493..abcaba9b7d27b22b1d36dded9ba2b4cec399d299 100644
--- a/arch/arm/src/samv7/sam_twihs.h
+++ b/arch/arm/src/samv7/sam_twihs.h
@@ -57,7 +57,7 @@
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
@@ -73,7 +73,7 @@ FAR struct i2c_master_s *sam_i2cbus_initialize(int port);
* Description:
* De-initialize the selected I2C port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the sam_i2cbus_initialize()
*
* Returned Value:
diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c
index d27dafd5cc8b733103a5945a61a85486b281b7fd..5959cde64a0e81aae14b85e5d66dc95f440128ad 100644
--- a/arch/arm/src/samv7/sam_usbdevhs.c
+++ b/arch/arm/src/samv7/sam_usbdevhs.c
@@ -3319,7 +3319,7 @@ static void sam_resume(struct sam_usbdev_s *priv)
/****************************************************************************
* Name: sam_ep_reset
*
- * Description
+ * Description:
* Reset and disable a set of endpoints.
*
****************************************************************************/
@@ -3377,7 +3377,7 @@ static void sam_ep_reset(struct sam_usbdev_s *priv, uint8_t epno)
/****************************************************************************
* Name: sam_epset_reset
*
- * Description
+ * Description:
* Reset and disable a set of endpoints.
*
****************************************************************************/
diff --git a/arch/arm/src/samv7/sam_wdt.c b/arch/arm/src/samv7/sam_wdt.c
index 4ce21303c33122abc65501edd8292d4ef1a9a528..b6990b9370a07037780cf18323aafbc5a3c13e74 100644
--- a/arch/arm/src/samv7/sam_wdt.c
+++ b/arch/arm/src/samv7/sam_wdt.c
@@ -254,7 +254,7 @@ static void sam_putreg(uint32_t regval, uintptr_t regaddr)
* Input Parameters:
* Usual interrupt handler arguments.
*
- * Returned Values:
+ * Returned Value:
* Always returns OK.
*
****************************************************************************/
@@ -290,7 +290,7 @@ static int sam_interrupt(int irq, FAR void *context, FAR void *arg)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -320,7 +320,7 @@ static int sam_start(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -350,7 +350,7 @@ static int sam_stop(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -378,7 +378,7 @@ static int sam_keepalive(FAR struct watchdog_lowerhalf_s *lower)
* driver state structure.
* stawtus - The location to return the watchdog status information.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -435,7 +435,7 @@ static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower,
* driver state structure.
* timeout - The new timeout value in millisecnds.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -567,7 +567,7 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* function pointer is NULL, then the reset-on-expiration
* behavior is restored,
*
- * Returned Values:
+ * Returned Value:
* The previous watchdog expiration function pointer or NULL is there was
* no previous function pointer, i.e., if the previous behavior was
* reset-on-expiration (NULL is also returned if an error occurs).
@@ -632,7 +632,7 @@ static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower,
* interpretation of this argument depends on the particular
* command.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -662,7 +662,7 @@ static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
* Input Parameters:
* None
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/samv7/sam_wdt.h b/arch/arm/src/samv7/sam_wdt.h
index f5ee97a2479e8e84457628b88864daf89818e148..3fe31686caf299ad106c0977b589a7411432b184 100644
--- a/arch/arm/src/samv7/sam_wdt.h
+++ b/arch/arm/src/samv7/sam_wdt.h
@@ -76,7 +76,7 @@ extern "C"
*
* At a minimum, this function should call watchdog_register().
*
- * Input parameters:
+ * Input Parameters:
* None
*
* Returned Value:
@@ -96,7 +96,7 @@ int sam_wdt_initialize(void);
*
* At a minimum, this function should call watchdog_register().
*
- * Input parameters:
+ * Input Parameters:
* None
*
* Returned Value:
diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig
index 141058ece8bb899c44beae7984d1467fa9ee821d..02441b567d012c564d3a01c42d46b6944d0315ec 100644
--- a/arch/arm/src/stm32/Kconfig
+++ b/arch/arm/src/stm32/Kconfig
@@ -2195,7 +2195,7 @@ config STM32_COMP6
config STM32_COMP7
bool "COMP7"
default n
- depends on STM32_HAVE_COMP6
+ depends on STM32_HAVE_COMP7
config STM32_BKP
bool "BKP"
@@ -5864,6 +5864,11 @@ config STM32_HRTIM_DEADTIME
depends on STM32_HRTIM_PWM
default n
+config STM32_HRTIM_PUSHPULL
+ bool "HRTIM push-pull mode"
+ depends on STM32_HRTIM_PWM
+ default n
+
config STM32_HRTIM_DMA
bool "HRTIM DMA"
default n
@@ -6041,6 +6046,11 @@ config STM32_HRTIM_TIMA_DT
default n
depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMA_PWM)
+config STM32_HRTIM_TIMA_PSHPLL
+ bool "HRTIM TIMA PWM Push-pull mode"
+ default n
+ depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMA_PWM)
+
endmenu # "HRTIM Timer A Configuration"
menu "HRTIM Timer B Configuration"
@@ -6106,6 +6116,11 @@ config STM32_HRTIM_TIMB_DT
default n
depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMB_PWM)
+config STM32_HRTIM_TIMB_PSHPLL
+ bool "HRTIM TIMB PWM Push-pull mode"
+ default n
+ depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMB_PWM)
+
endmenu # "HRTIM Timer B Configuration"
menu "HRTIM Timer C Configuration"
@@ -6171,6 +6186,11 @@ config STM32_HRTIM_TIMC_DT
default n
depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMC_PWM)
+config STM32_HRTIM_TIMC_PSHPLL
+ bool "HRTIM TIMC PWM Push-pull mode"
+ default n
+ depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMC_PWM)
+
endmenu # "HRTIM Timer C Configuration"
menu "HRTIM Timer D Configuration"
@@ -6236,6 +6256,11 @@ config STM32_HRTIM_TIMD_DT
default n
depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMD_PWM)
+config STM32_HRTIM_TIMD_PSHPLL
+ bool "HRTIM TIMD PWM Push-pull mode"
+ default n
+ depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMD_PWM)
+
endmenu # "HRTIM Timer D Configuration"
menu "HRTIM Timer E Configuration"
@@ -6301,6 +6326,11 @@ config STM32_HRTIM_TIME_DT
default n
depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIME_PWM)
+config STM32_HRTIM_TIME_PSHPLL
+ bool "HRTIM TIME PWM Push-pull mode"
+ default n
+ depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIME_PWM)
+
endmenu # "HRTIM Timer E Configuration"
endif # STM32_HRTIM1
diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs
index e4402d0bfb1a8f061fc3e099b15db42e090915c9..898a6986b18ca2f4d7d16bf8b45285f4f46ef0f1 100644
--- a/arch/arm/src/stm32/Make.defs
+++ b/arch/arm/src/stm32/Make.defs
@@ -43,7 +43,7 @@ CMN_UASRCS =
CMN_UCSRCS =
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
-CMN_ASRCS += up_testset.S vfork.S
+CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S
CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c
CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c
diff --git a/arch/arm/src/stm32/chip/stm32f20xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f20xxx_memorymap.h
index 9c64929a0b06c2114bfd14b3e4367f2c71fd8d36..b1b4f41c34be06deeb3040f2b4c6afa0a8a3ac58 100644
--- a/arch/arm/src/stm32/chip/stm32f20xxx_memorymap.h
+++ b/arch/arm/src/stm32/chip/stm32f20xxx_memorymap.h
@@ -129,7 +129,6 @@
#define STM32_TIM13_BASE 0x40001c00 /* 0x40001c00-0x40001fff: TIM13 timer */
#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff: TIM14 timer */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP registers */
-#define STM32_BKP_BASE 0x40002850
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: Window watchdog (WWDG) */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: Independent watchdog (IWDG) */
#define STM32_I2S2EXT_BASE 0x40003400 /* 0x40003400-0x400037ff: I2S2ext */
diff --git a/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h
index a7cbc46117d9e8ee258a8cd0b9cdb30dd1defd0e..30308dd93bdc7a0323ecd065d98ed3068c373661 100644
--- a/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h
+++ b/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h
@@ -92,8 +92,7 @@
#define STM32_TIM4_BASE 0x40000800 /* 0x40000800-0x40000bff TIM4 */
#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */
#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */
-#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */
-#define STM32_BKP_BASE 0x40002850 /* 0x40002850-0x4000288c BKP */
+#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC and BKP */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */
#define STM32_I2S2EXT_BASE 0x40003400 /* 0x40003400-0x400037ff I2S2ext */
diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h b/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h
index 0e962104f9171d22e54f37571c8fdb04314cf4b6..0e8a707e8bc1b777d9c65bd82306e62deab76e25 100644
--- a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h
+++ b/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h
@@ -447,8 +447,8 @@
# define HRTIM_TIMDT_DTPRSC_110 (6 << HRTIM_TIMDT_DTPRSC_SHIFT)
# define HRTIM_TIMDT_DTPRSC_111 (7 << HRTIM_TIMDT_DTPRSC_SHIFT)
#define HRTIM_TIMDT_DTRSLK (1 << 14) /* Bit 14: Deadtime Rising Sign Lock */
-#define HRTIM_TIMDT_DTRLK (1 << 14) /* Bit 15: Deadtime Rising Lock */
-#define HRTIM_TIMDT_DTF_SHIFT 0 /* Bits 16-24: Deadtime Falling Value */
+#define HRTIM_TIMDT_DTRLK (1 << 15) /* Bit 15: Deadtime Rising Lock */
+#define HRTIM_TIMDT_DTF_SHIFT 16 /* Bits 16-24: Deadtime Falling Value */
#define HRTIM_TIMDT_DTF_MASK (0x1ff << HRTIM_TIMDT_DTF_SHIFT)
#define HRTIM_TIMDT_SDTF (1 << 25) /* Bit 25: Sign Deadtime Falling Value */
#define HRTIM_TIMDT_DTFSLK (1 << 30) /* Bit 30: Deadtime Falling Sign Lock */
@@ -818,7 +818,7 @@
#define HRTIM_TIMARST_TIMCCMP4 (1 << 24) /* Bit 24 */
#define HRTIM_TIMARST_TIMDCMP1 (1 << 25) /* Bit 25 */
#define HRTIM_TIMARST_TIMDCMP2 (1 << 26) /* Bit 26 */
-#define HRTIM_TIMARST_TIMDCMP3 (1 << 27) /* Bit 27 */
+#define HRTIM_TIMARST_TIMDCMP4 (1 << 27) /* Bit 27 */
#define HRTIM_TIMARST_TIMECMP1 (1 << 28) /* Bit 28 */
#define HRTIM_TIMARST_TIMECMP2 (1 << 29) /* Bit 29 */
#define HRTIM_TIMARST_TIMECMP4 (1 << 30) /* Bit 30 */
@@ -849,7 +849,7 @@
#define HRTIM_TIMBRST_TIMCCMP4 (1 << 24) /* Bit 24 */
#define HRTIM_TIMBRST_TIMDCMP1 (1 << 25) /* Bit 25 */
#define HRTIM_TIMBRST_TIMDCMP2 (1 << 26) /* Bit 26 */
-#define HRTIM_TIMBRST_TIMDCMP3 (1 << 27) /* Bit 27 */
+#define HRTIM_TIMBRST_TIMDCMP4 (1 << 27) /* Bit 27 */
#define HRTIM_TIMBRST_TIMECMP1 (1 << 28) /* Bit 28 */
#define HRTIM_TIMBRST_TIMECMP2 (1 << 29) /* Bit 29 */
#define HRTIM_TIMBRST_TIMECMP4 (1 << 30) /* Bit 30 */
@@ -880,7 +880,7 @@
#define HRTIM_TIMCRST_TIMBCMP4 (1 << 24) /* Bit 24 */
#define HRTIM_TIMCRST_TIMDCMP1 (1 << 25) /* Bit 25 */
#define HRTIM_TIMCRST_TIMDCMP2 (1 << 26) /* Bit 26 */
-#define HRTIM_TIMCRST_TIMDCMP3 (1 << 27) /* Bit 27 */
+#define HRTIM_TIMCRST_TIMDCMP4 (1 << 27) /* Bit 27 */
#define HRTIM_TIMCRST_TIMECMP1 (1 << 28) /* Bit 28 */
#define HRTIM_TIMCRST_TIMECMP2 (1 << 29) /* Bit 29 */
#define HRTIM_TIMCRST_TIMECMP4 (1 << 30) /* Bit 30 */
@@ -911,7 +911,7 @@
#define HRTIM_TIMDRST_TIMBCMP4 (1 << 24) /* Bit 24 */
#define HRTIM_TIMDRST_TIMCCMP1 (1 << 25) /* Bit 25 */
#define HRTIM_TIMDRST_TIMCCMP2 (1 << 26) /* Bit 26 */
-#define HRTIM_TIMDRST_TIMCCMP3 (1 << 27) /* Bit 27 */
+#define HRTIM_TIMDRST_TIMCCMP4 (1 << 27) /* Bit 27 */
#define HRTIM_TIMDRST_TIMECMP1 (1 << 28) /* Bit 28 */
#define HRTIM_TIMDRST_TIMECMP2 (1 << 29) /* Bit 29 */
#define HRTIM_TIMDRST_TIMECMP4 (1 << 30) /* Bit 30 */
@@ -942,7 +942,7 @@
#define HRTIM_TIMERST_TIMBCMP4 (1 << 24) /* Bit 24 */
#define HRTIM_TIMERST_TIMCCMP1 (1 << 25) /* Bit 25 */
#define HRTIM_TIMERST_TIMCCMP2 (1 << 26) /* Bit 26 */
-#define HRTIM_TIMERST_TIMCCMP3 (1 << 27) /* Bit 27 */
+#define HRTIM_TIMERST_TIMCCMP4 (1 << 27) /* Bit 27 */
#define HRTIM_TIMERST_TIMDCMP1 (1 << 28) /* Bit 28 */
#define HRTIM_TIMERST_TIMDCMP2 (1 << 29) /* Bit 29 */
#define HRTIM_TIMERST_TIMDCMP4 (1 << 30) /* Bit 30 */
diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h
index 85e5ce175d615d44e0c5eabc06269bf225e962ae..90af97f03681065dd450352dbd7580174f14f860 100644
--- a/arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h
+++ b/arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h
@@ -93,8 +93,7 @@
#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */
#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */
#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */
-#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */
-#define STM32_BKP_BASE 0x40002850 /* 0x40002850-0x400028cc BKP */
+#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC and BKP */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */
#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff USART2 */
diff --git a/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h
index 49bfa2ecf2ea9f9d9ecfcaa09ebc36721b343fdf..2089ad0be898a8564b763e909fca3fddec75ef29 100644
--- a/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h
+++ b/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h
@@ -93,8 +93,7 @@
#define STM32_TIM12_BASE 0x40001800 /* 0x40001800-0x40001bff TIM12 */
#define STM32_TIM13_BASE 0x40001c00 /* 0x40001c00-0x40001fff TIM13 */
#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff TIM14 */
-#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */
-#define STM32_BKP_BASE 0x40002850 /* 0x40002850-0x400028cc BKP */
+#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC and BKP */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */
#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2, or */
diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h
index 8b493e916ca806a938348a84fc0f65a650dd1b01..8bd7d5e16afeb87f4c876c9b112212a0bd43e396 100644
--- a/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h
+++ b/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h
@@ -129,7 +129,6 @@
#define STM32_TIM13_BASE 0x40001c00 /* 0x40001c00-0x40001fff: TIM13 timer */
#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff: TIM14 timer */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP registers */
-#define STM32_BKP_BASE 0x40002850
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: Window watchdog (WWDG) */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: Independent watchdog (IWDG) */
#define STM32_I2S2EXT_BASE 0x40003400 /* 0x40003400-0x400037ff: I2S2ext */
diff --git a/arch/arm/src/stm32/stm32.h b/arch/arm/src/stm32/stm32.h
index 56225ee211d4932f59e09604b3ebc1a8ac233972..fe61cd4811d2ff8867124538798791788818e0be 100644
--- a/arch/arm/src/stm32/stm32.h
+++ b/arch/arm/src/stm32/stm32.h
@@ -57,7 +57,6 @@
#include "chip.h"
#include "stm32_adc.h"
-//#include "stm32_bkp.h"
#include "stm32_can.h"
#include "stm32_comp.h"
#include "stm32_dbgmcu.h"
diff --git a/arch/arm/src/stm32/stm32_1wire.c b/arch/arm/src/stm32/stm32_1wire.c
index a4157006a62f18976383b8cccd354769c78e1dae..93ab8000eed79ebede7e6b1f0e529a2379844bb8 100644
--- a/arch/arm/src/stm32/stm32_1wire.c
+++ b/arch/arm/src/stm32/stm32_1wire.c
@@ -500,7 +500,7 @@ static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv)
* Description:
* Enable or disable APB clock for the USART peripheral
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the 1-Wire driver state structure
* on - Enable clock if 'on' is 'true' and disable if 'false'
*
@@ -1149,7 +1149,7 @@ static int stm32_1wire_exchange(FAR struct onewire_dev_s *dev, bool reset,
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple 1-Wire interfaces)
*
* Returned Value:
@@ -1245,7 +1245,7 @@ FAR struct onewire_dev_s *stm32_1wireinitialize(int port)
* Description:
* De-initialize the selected 1-Wire port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the stm32_1wireinitialize()
*
* Returned Value:
diff --git a/arch/arm/src/stm32/stm32_1wire.h b/arch/arm/src/stm32/stm32_1wire.h
index 24cfe45592f604a2d85d4595e6ac738c49e77399..7606c8f4610bd598b456ce2ce3dee2b2948ae5eb 100644
--- a/arch/arm/src/stm32/stm32_1wire.h
+++ b/arch/arm/src/stm32/stm32_1wire.h
@@ -57,7 +57,7 @@
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple 1-Wire interfaces)
*
* Returned Value:
@@ -73,7 +73,7 @@ FAR struct onewire_dev_s *stm32_1wireinitialize(int port);
* Description:
* De-initialize the selected 1-Wire port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the stm32_1wireinitialize()
*
* Returned Value:
diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c
index 7ec37927bd5ee01c8e8f63fa4e91715f7d14771c..a1a3d5523c669afd1a629aad217a1c3a5e6af9ad 100644
--- a/arch/arm/src/stm32/stm32_adc.c
+++ b/arch/arm/src/stm32/stm32_adc.c
@@ -757,7 +757,7 @@ static void tim_modifyreg(FAR struct stm32_dev_s *priv, int offset,
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the ADC block status
*
* Returned Value:
@@ -1366,7 +1366,8 @@ static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset)
/****************************************************************************
* Name: adc_power_down_idle
*
- * Description : Enables or disables power down during the idle phase.
+ * Description:
+ * Enables or disables power down during the idle phase.
*
* Input Parameters:
*
@@ -1407,7 +1408,8 @@ static void adc_power_down_idle(FAR struct stm32_dev_s *priv, bool pdi_high)
/****************************************************************************
* Name: adc_power_down_delay
*
- * Description : Enables or disables power down during the delay phase.
+ * Description:
+ * Enables or disables power down during the delay phase.
*
* Input Parameters:
*
@@ -1448,8 +1450,9 @@ static void adc_power_down_delay(FAR struct stm32_dev_s *priv, bool pdd_high)
/****************************************************************************
* Name: adc_dels_after_conversion
*
- * Description : Defines the length of the delay which is applied
- * after a conversion or a sequence of conversions.
+ * Description:
+ * Defines the length of the delay which is applied after a conversion or
+ * a sequence of conversions.
*
* Input Parameters:
*
@@ -1474,7 +1477,8 @@ static void adc_dels_after_conversion(FAR struct stm32_dev_s *priv,
/****************************************************************************
* Name: adc_select_ch_bank
*
- * Description : Selects the bank of channels to be converted
+ * Description:
+ * Selects the bank of channels to be converted
* (! Must be modified only when no conversion is on going !)
*
* Input Parameters:
@@ -1507,9 +1511,9 @@ static void adc_select_ch_bank(FAR struct stm32_dev_s *priv,
/****************************************************************************
* Name: adc_enable
*
- * Description : Enables or disables the specified ADC peripheral.
- * Also, starts a conversion when the ADC is not
- * triggered by timers
+ * Description:
+ * Enables or disables the specified ADC peripheral. Also, starts a
+ * conversion when the ADC is not triggered by timers
*
* Input Parameters:
*
diff --git a/arch/arm/src/stm32/stm32_bkp.h b/arch/arm/src/stm32/stm32_bkp.h
index 21399c38bd291a99ca6e744ccef03f51d8f161d7..4478ffd63357836059777f89f22836ca3b5169a4 100644
--- a/arch/arm/src/stm32/stm32_bkp.h
+++ b/arch/arm/src/stm32/stm32_bkp.h
@@ -42,8 +42,18 @@
#include
+/* Only the STM32 F1 family has a dedicated address region for BKP memory. For F2,
+ * F3, and F4 parts, the bKP registers lie in the same address region as the RTCC
+ * and the definitions in chip/stm32_rtcc.h should be used to access backup
+ * registers. NOTE: These definitions are not interchangeable!
+ */
+
#include "chip.h"
-#include "chip/stm32_bkp.h"
+#ifdef CONFIG_STM32_STM32F10XX
+# include "chip/stm32_bkp.h"
+#else
+# include "chip/stm32_rtcc.h"
+#endif
/************************************************************************************
* Pre-processor Definitions
diff --git a/arch/arm/src/stm32/stm32_can.c b/arch/arm/src/stm32/stm32_can.c
index a2fc3fac1dfaf2bfae0d013248a910c7fe7a6d0c..2625c9123c51caf8750ef873ddb35dd2174d009b 100644
--- a/arch/arm/src/stm32/stm32_can.c
+++ b/arch/arm/src/stm32/stm32_can.c
@@ -1644,7 +1644,7 @@ static int stm32can_txinterrupt(int irq, FAR void *context, FAR void *arg)
* Where:
* Tpclk1 is the period of the APB1 clock (PCLK1).
*
- * Input Parameter:
+ * Input Parameters:
* priv - A reference to the CAN block status
*
* Returned Value:
@@ -1743,7 +1743,7 @@ static int stm32can_bittiming(FAR struct stm32_can_s *priv)
* peripheral, no registers are changed. The initialization mode is
* required to change the baud rate.
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN block
*
* Returned Value:
@@ -1794,7 +1794,7 @@ static int stm32can_enterinitmode(FAR struct stm32_can_s *priv)
* Description:
* Put the CAN cell out of the Initialization mode (to Normal mode)
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN block
*
* Returned Value:
@@ -1844,7 +1844,7 @@ static int stm32can_exitinitmode(FAR struct stm32_can_s *priv)
* Description:
* CAN cell initialization
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN block
*
* Returned Value:
@@ -1927,7 +1927,7 @@ static int stm32can_cellinit(FAR struct stm32_can_s *priv)
* are set to zero thus supressing all filtering because anything masked
* with zero matches zero.
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN block
*
* Returned Value:
@@ -2014,7 +2014,7 @@ static int stm32can_filterinit(FAR struct stm32_can_s *priv)
* Description:
* Add a filter for extended CAN IDs
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN block
* arg - A pointer to a structure describing the filter
*
@@ -2039,7 +2039,7 @@ static int stm32can_addextfilter(FAR struct stm32_can_s *priv,
* Description:
* Remove a filter for extended CAN IDs
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN block
* arg - The filter index previously returned by the
* CANIOC_ADD_EXTFILTER command
@@ -2064,7 +2064,7 @@ static int stm32can_delextfilter(FAR struct stm32_can_s *priv, int arg)
* Description:
* Add a filter for standard CAN IDs
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN block
* arg - A pointer to a structure describing the filter
*
@@ -2087,7 +2087,7 @@ static int stm32can_addstdfilter(FAR struct stm32_can_s *priv,
* Description:
* Remove a filter for standard CAN IDs
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN block
* arg - The filter index previously returned by the
* CANIOC_ADD_STDFILTER command
@@ -2107,7 +2107,7 @@ static int stm32can_delstdfilter(FAR struct stm32_can_s *priv, int arg)
/****************************************************************************
* Name: stm32can_txmb0empty
*
- * Input Parameter:
+ * Input Parameters:
* tsr_regval - value of CAN transmit status register
*
* Returned Value:
@@ -2124,7 +2124,7 @@ static bool stm32can_txmb0empty(uint32_t tsr_regval)
/****************************************************************************
* Name: stm32can_txmb1empty
*
- * Input Parameter:
+ * Input Parameters:
* tsr_regval - value of CAN transmit status register
*
* Returned Value:
@@ -2141,7 +2141,7 @@ static bool stm32can_txmb1empty(uint32_t tsr_regval)
/****************************************************************************
* Name: stm32can_txmb2empty
*
- * Input Parameter:
+ * Input Parameters:
* tsr_regval - value of CAN transmit status register
*
* Returned Value:
@@ -2165,7 +2165,7 @@ static bool stm32can_txmb2empty(uint32_t tsr_regval)
* Description:
* Initialize the selected CAN port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple CAN interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/stm32/stm32_can.h b/arch/arm/src/stm32/stm32_can.h
index f06231ab60a49fc50e24d8dbf233b0732838cfe0..078e6b2a124d9b70345086ac307f1b27640275ee 100644
--- a/arch/arm/src/stm32/stm32_can.h
+++ b/arch/arm/src/stm32/stm32_can.h
@@ -125,7 +125,7 @@ extern "C"
* Description:
* Initialize the selected CAN port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple CAN interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/stm32/stm32_comp.c b/arch/arm/src/stm32/stm32_comp.c
index ada260042107bacddd60d4a92d805a474fe660e3..b46b678f94e5fd0149ff288414bde683fef180f7 100644
--- a/arch/arm/src/stm32/stm32_comp.c
+++ b/arch/arm/src/stm32/stm32_comp.c
@@ -1069,7 +1069,6 @@ FAR struct comp_dev_s* stm32_compinitialize(int intf)
if (ret < 0)
{
aerr("ERROR: Failed to initialize COMP%d: %d\n", intf, ret);
- errno = -ret;
return NULL;
}
diff --git a/arch/arm/src/stm32/stm32_dma.h b/arch/arm/src/stm32/stm32_dma.h
index 965fd6f30fe865c4532d268515ba8d127c8b1342..e9878d1157224d77741d1b9689c9686ab8a79a44 100644
--- a/arch/arm/src/stm32/stm32_dma.h
+++ b/arch/arm/src/stm32/stm32_dma.h
@@ -175,7 +175,7 @@ extern "C"
* Hmm.. I suppose this interface could be extended to make a non-blocking
* version. Feel free to do that if that is what you need.
*
- * Input parameter:
+ * Input Parameters:
* chan - Identifies the stream/channel resource
* For the STM32 F1, this is simply the channel number as provided by
* the DMACHAN_* definitions in chip/stm32f10xxx_dma.h.
@@ -281,7 +281,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle);
* only applies to memory addresses, it will return false for any peripheral
* address.
*
- * Returned value:
+ * Returned Value:
* True, if transfer is possible.
*
****************************************************************************/
diff --git a/arch/arm/src/stm32/stm32_dma2d.c b/arch/arm/src/stm32/stm32_dma2d.c
index a70ed7508580006f1e1da0552113a2ecd198c790..c9e2a0e54c4275d1c73fcb12829ce3bbaaa5ec15 100644
--- a/arch/arm/src/stm32/stm32_dma2d.c
+++ b/arch/arm/src/stm32/stm32_dma2d.c
@@ -486,7 +486,7 @@ static int stm32_dma2dirq(int irq, void *context, FAR void *arg)
* loading or dma transfer was completed.
* Note! The caller must use this function within a critical section.
*
- * Return:
+ * Returned Value:
* On success OK otherwise ERROR
*
****************************************************************************/
@@ -532,7 +532,7 @@ static int stm32_dma2d_waitforirq(void)
* Parameter:
* pfcreg - PFC control Register
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -620,7 +620,7 @@ static int stm32_dma2d_start(void)
* Parameter:
* layer - Reference to the common layer state structure
*
- * Return:
+ * Returned Value:
* memory address
*
****************************************************************************/
@@ -646,7 +646,7 @@ static uint32_t stm32_dma2d_memaddress(FAR const struct stm32_dma2d_s *layer,
* Parameter:
* layer - Reference to the common layer state structure
*
- * Return:
+ * Returned Value:
* line offset
*
****************************************************************************/
@@ -670,7 +670,7 @@ static fb_coord_t stm32_dma2d_lineoffset(FAR const struct stm32_dma2d_s *layer,
* layer - Reference to the common layer state structure
* fmt - Reference to the location to store the pixel format
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -729,7 +729,7 @@ static int stm32_dma2d_pixelformat(uint8_t fmt, uint8_t *fmtmap)
* layer - Reference to the common layer state structure
* bpp - Reference to the location to store the pixel format
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -770,7 +770,7 @@ static int stm32_dma2d_bpp(uint8_t fmt, uint8_t *bpp)
* Description:
* Get a free layer id
*
- * Return:
+ * Returned Value:
* The number of the free layer
* -1 if no free layer is available
*
@@ -797,7 +797,7 @@ static int stm32_dma2d_lfreelid(void)
* Description:
* Allocate a new layer structure
*
- * Return:
+ * Returned Value:
* A new allocated layer structure or NULL on error.
*
****************************************************************************/
@@ -886,7 +886,7 @@ static void stm32_dma2d_llayerscleanup(void)
* Description:
* Helper to validate if the layer is valid
*
- * Return:
+ * Returned Value:
* true if validates otherwise false
*
****************************************************************************/
@@ -908,7 +908,7 @@ static inline bool stm32_dma2d_lvalidate(FAR const struct stm32_dma2d_s *layer)
* ypos - The y position inside the whole layer
* area - the area inside the whole layer
*
- * Return:
+ * Returned Value:
* true if area is inside the whole layer otherwise false
*
****************************************************************************/
@@ -1162,7 +1162,7 @@ static void stm32_dma2d_lpfc(FAR const struct stm32_dma2d_s *layer,
* layer - Reference to the layer control structure
* vinfo - Reference to the video info structure
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1199,7 +1199,7 @@ static int stm32_dma2dgetvideoinfo(FAR struct dma2d_layer_s *layer,
* planeno - Number of the plane
* pinfo - Reference to the plane info structure
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1235,7 +1235,7 @@ static int stm32_dma2dgetplaneinfo(FAR struct dma2d_layer_s *layer, int planeno,
* layer - Reference to the layer structure
* lid - Reference to store the layer id
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1271,7 +1271,7 @@ static int stm32_dma2dgetlid(FAR struct dma2d_layer_s *layer, int *lid)
* layer - Reference to the layer structure
* cmap - color lookup table with up the 256 entries
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1390,7 +1390,7 @@ static int stm32_dma2dsetclut(FAR struct dma2d_layer_s *layer,
* cmap - Reference to valid color lookup table accept up the 256 color
* entries
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1482,7 +1482,7 @@ static int stm32_dma2dgetclut(FAR struct dma2d_layer_s *layer,
* layer - Reference to the layer structure
* alpha - Alpha value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1517,7 +1517,7 @@ static int stm32_dma2dsetalpha(FAR struct dma2d_layer_s *layer, uint8_t alpha)
* layer - Reference to the layer structure
* alpha - Reference to store the alpha value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1554,7 +1554,7 @@ static int stm32_dma2dgetalpha(FAR struct dma2d_layer_s *layer, uint8_t *alpha)
* layer - Reference to the layer structure
* mode - Blend mode (see DMA2D_BLEND_*)
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1603,7 +1603,7 @@ static int stm32_dma2dsetblendmode(FAR struct dma2d_layer_s *layer,
* layer - Reference to the layer structure
* mode - Reference to store the blend mode
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1643,7 +1643,7 @@ static int stm32_dma2dgetblendmode(FAR struct dma2d_layer_s *layer,
* src - Valid reference to the source layer
* srcarea - Valid reference to the selected area of the source layer
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* source area outside the visible area of the destination layer.
@@ -1752,7 +1752,7 @@ static int stm32_dma2dblit(FAR struct dma2d_layer_s *dest,
* back - Reference to the background layer
* backarea - Reference to the selected area of the background layer
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* source area outside the visible area of the destination layer.
@@ -1859,7 +1859,7 @@ static int stm32_dma2dblend(FAR struct dma2d_layer_s *dest,
* color - Color to fill the selected area. Color must be formatted
* according to the layer pixel format.
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* area outside the visible area of the layer.
@@ -1935,7 +1935,7 @@ static int stm32_dma2dfillarea(FAR struct dma2d_layer_s *layer,
* Parameter:
* lid - Layer identifier
*
- * Return:
+ * Returned Value:
* Reference to the dma2d layer control structure on success or Null if no
* related exist.
*
@@ -1968,7 +1968,7 @@ FAR struct dma2d_layer_s *up_dma2dgetlayer(int lid)
* height - Layer height
* fmt - Pixel format of the layer
*
- * Return:
+ * Returned Value:
* On success - A valid dma2d layer reference
* On error - NULL
*
@@ -2090,7 +2090,7 @@ FAR struct dma2d_layer_s *up_dma2dcreatelayer(fb_coord_t width,
* Parameter:
* layer - Reference to the layer to remove
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2132,7 +2132,7 @@ int up_dma2dremovelayer(FAR struct dma2d_layer_s *layer)
* Description:
* Initialize the dma2d controller
*
- * Return:
+ * Returned Value:
* OK - On success
* An error if initializing failed.
*
@@ -2248,7 +2248,7 @@ void up_dma2duninitialize(void)
* layer - a valid reference to the low level ltdc layer structure
* clut - a pointer to a valid memory region to hold 256 clut colors
*
- * Return:
+ * Returned Value:
* On success - A valid dma2d layer reference
* On error - NULL
*
diff --git a/arch/arm/src/stm32/stm32_dma2d.h b/arch/arm/src/stm32/stm32_dma2d.h
index a62d16f7af1416b9d294cf5c03f1b11b90f9d5fb..258ae695317d4cb17ae381154f015d2791cd35d4 100644
--- a/arch/arm/src/stm32/stm32_dma2d.h
+++ b/arch/arm/src/stm32/stm32_dma2d.h
@@ -74,7 +74,7 @@ struct dma2d_layer_s
* layer - Reference to the layer control structure
* vinfo - Reference to the video info structure
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -92,7 +92,7 @@ struct dma2d_layer_s
* planeno - Number of the plane
* pinfo - Reference to the plane info structure
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -109,7 +109,7 @@ struct dma2d_layer_s
* layer - Reference to the layer structure
* lid - Reference to store the layer id
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -127,7 +127,7 @@ struct dma2d_layer_s
* layer - Reference to the layer structure
* cmap - color lookup table with up the 256 entries
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -145,7 +145,7 @@ struct dma2d_layer_s
* cmap - Reference to valid color lookup table accept up the 256 color
* entries
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -167,7 +167,7 @@ struct dma2d_layer_s
* layer - Reference to the layer structure
* alpha - Alpha value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -183,7 +183,7 @@ struct dma2d_layer_s
* layer - Reference to the layer structure
* alpha - Reference to store the alpha value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -201,7 +201,7 @@ struct dma2d_layer_s
* layer - Reference to the layer structure
* mode - Blend mode (see DMA2D_BLEND_*)
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -230,7 +230,7 @@ struct dma2d_layer_s
* layer - Reference to the layer structure
* mode - Reference to store the blend mode
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -250,7 +250,7 @@ struct dma2d_layer_s
* src - Reference to the source layer
* srcarea - Reference to the selected area of the source layer
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the
* selected source area outside the visible area of the
@@ -281,7 +281,7 @@ struct dma2d_layer_s
* back - Reference to the background layer
* backarea - Reference to the selected area of the background layer
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the
* selected source area outside the visible area of the
@@ -308,7 +308,7 @@ struct dma2d_layer_s
* color - Color to fill the selected area. Color must be formatted
* according to the layer pixel format.
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the
* selected area outside the visible area of the layer.
@@ -340,7 +340,7 @@ struct stm32_ltdc_s; /* Forward declaration */
* Parameter:
* layer - a valid reference to the low level ltdc layer structure
*
- * Return:
+ * Returned Value:
* On success - A valid dma2d layer reference
* On error - NULL and errno is set to
* -EINVAL if one of the parameter is invalid
@@ -358,7 +358,7 @@ FAR struct dma2d_layer_s *stm32_dma2dinitltdc(FAR struct stm32_ltdc_s *layer);
* Parameter:
* lid - Layer identifier
*
- * Return:
+ * Returned Value:
* Reference to the dma2d layer control structure on success or Null if no
* related exist.
*
@@ -377,7 +377,7 @@ FAR struct dma2d_layer_s *up_dma2dgetlayer(int lid);
* height - Layer height
* fmt - Pixel format of the layer
*
- * Return:
+ * Returned Value:
* On success - A valid dma2d layer reference
* On error - NULL and errno is set to
* -EINVAL if one of the parameter is invalid
@@ -399,7 +399,7 @@ FAR struct dma2d_layer_s *up_dma2dcreatelayer(fb_coord_t width,
* Parameter:
* layer - Reference to the layer to remove
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -413,7 +413,7 @@ int up_dma2dremovelayer(FAR struct dma2d_layer_s *layer);
* Description:
* Initialize the dma2d controller
*
- * Return:
+ * Returned Value:
* OK - On success
* An error if initializing failed.
*
diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c
index 62e44a0ff234631ded40df95d3b2ed0940624019..0c2aac13116d4d5fcf7c4864b1db9ac9c2e56c84 100644
--- a/arch/arm/src/stm32/stm32_eth.c
+++ b/arch/arm/src/stm32/stm32_eth.c
@@ -721,7 +721,7 @@ static int stm32_addmac(struct net_driver_s *dev, FAR const uint8_t *mac);
#ifdef CONFIG_NET_IGMP
static int stm32_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac);
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
static int stm32_ioctl(struct net_driver_s *dev, int cmd,
unsigned long arg);
#endif
@@ -2847,62 +2847,64 @@ static void stm32_rxdescinit(FAR struct stm32_ethmac_s *priv)
*
****************************************************************************/
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
{
-#ifdef CONFIG_ARCH_PHY_INTERRUPT
+#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)dev->d_private;
#endif
int ret;
switch (cmd)
- {
-#ifdef CONFIG_ARCH_PHY_INTERRUPT
- case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
- struct mii_iotcl_notify_s *req = (struct mii_iotcl_notify_s *)((uintptr_t)arg);
-
- ret = phy_notify_subscribe(dev->d_ifname, req->pid, req->signo, req->arg);
- if (ret == OK)
+#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_ARCH_PHY_INTERRUPT
+ case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
- /* Enable PHY link up/down interrupts */
+ struct mii_iotcl_notify_s *req = (struct mii_iotcl_notify_s *)((uintptr_t)arg);
- ret = stm32_phyintenable(priv);
+ ret = phy_notify_subscribe(dev->d_ifname, req->pid, req->signo, req->arg);
+ if (ret == OK)
+ {
+ /* Enable PHY link up/down interrupts */
+
+ ret = stm32_phyintenable(priv);
+ }
}
- }
- break;
+ break;
#endif
- case SIOCGMIIPHY: /* Get MII PHY address */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- req->phy_id = CONFIG_STM32_PHYADDR;
- ret = OK;
- }
- break;
+ case SIOCGMIIPHY: /* Get MII PHY address */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ req->phy_id = CONFIG_STM32_PHYADDR;
+ ret = OK;
+ }
+ break;
- case SIOCGMIIREG: /* Get register from MII PHY */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- ret = stm32_phyread(req->phy_id, req->reg_num, &req->val_out);
- }
- break;
+ case SIOCGMIIREG: /* Get register from MII PHY */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ ret = stm32_phyread(req->phy_id, req->reg_num, &req->val_out);
+ }
+ break;
- case SIOCSMIIREG: /* Set register in MII PHY */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- ret = stm32_phywrite(req->phy_id, req->reg_num, req->val_in);
- }
- break;
+ case SIOCSMIIREG: /* Set register in MII PHY */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ ret = stm32_phywrite(req->phy_id, req->reg_num, req->val_in);
+ }
+ break;
+#endif /* CONFIG_NETDEV_PHY_IOCTL */
- default:
- ret = -ENOTTY;
- break;
- }
+ default:
+ ret = -ENOTTY;
+ break;
+ }
return ret;
}
-#endif /* CONFIG_NETDEV_PHY_IOCTL */
+#endif /* CONFIG_NETDEV_IOCTL */
/****************************************************************************
* Function: stm32_phyintenable
@@ -4014,12 +4016,12 @@ int stm32_ethinitialize(int intf)
priv->dev.d_addmac = stm32_addmac; /* Add multicast MAC address */
priv->dev.d_rmmac = stm32_rmmac; /* Remove multicast MAC address */
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = stm32_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void *)g_stm32ethmac; /* Used to recover private state from dev */
- /* Create a watchdog for timing polling for and timing of transmisstions */
+ /* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create(); /* Create periodic poll timer */
priv->txtimeout = wd_create(); /* Create TX timeout timer */
diff --git a/arch/arm/src/stm32/stm32_exti.h b/arch/arm/src/stm32/stm32_exti.h
index 8e46e239da27adb3cbc056442dd10553b612eda2..376d65f774aa2dae66c54c5255f7b346fcbbda18 100644
--- a/arch/arm/src/stm32/stm32_exti.h
+++ b/arch/arm/src/stm32/stm32_exti.h
@@ -123,7 +123,7 @@ int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func,
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
- * Returns:
+ * Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
diff --git a/arch/arm/src/stm32/stm32_exti_alarm.c b/arch/arm/src/stm32/stm32_exti_alarm.c
index 414817a6b84f1ec35767c4e8d0aee3b1d4fd532c..77de848e9f7502f2767caac0e89e6447d254143c 100644
--- a/arch/arm/src/stm32/stm32_exti_alarm.c
+++ b/arch/arm/src/stm32/stm32_exti_alarm.c
@@ -108,7 +108,7 @@ static int stm32_exti_alarm_isr(int irq, void *context, FAR void *arg)
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
- * Returns:
+ * Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
diff --git a/arch/arm/src/stm32/stm32_exti_pwr.c b/arch/arm/src/stm32/stm32_exti_pwr.c
index 5ab6138ac4bb345729b20edcb879a27804266816..36d2167283bed458a8d024ede3c8ab8f3592ebfc 100644
--- a/arch/arm/src/stm32/stm32_exti_pwr.c
+++ b/arch/arm/src/stm32/stm32_exti_pwr.c
@@ -114,7 +114,7 @@ static int stm32_exti_pvd_isr(int irq, void *context, FAR void *arg)
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
- * Returns:
+ * Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on
* failure.
*
diff --git a/arch/arm/src/stm32/stm32_exti_pwr.h b/arch/arm/src/stm32/stm32_exti_pwr.h
index c4841dffebe9d14c3445458e03774644a3baef27..e48ca3f2eed0adaebe3f4bfea111ed23f798c196 100644
--- a/arch/arm/src/stm32/stm32_exti_pwr.h
+++ b/arch/arm/src/stm32/stm32_exti_pwr.h
@@ -59,7 +59,7 @@
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
- * Returns:
+ * Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on
* failure.
*
diff --git a/arch/arm/src/stm32/stm32_exti_wakeup.c b/arch/arm/src/stm32/stm32_exti_wakeup.c
index 9dd9ad7d99a4f2cdfe13c49bb263f7cdce0841bb..d265361f87195073bddd52e852c7a352a3d04b14 100644
--- a/arch/arm/src/stm32/stm32_exti_wakeup.c
+++ b/arch/arm/src/stm32/stm32_exti_wakeup.c
@@ -107,7 +107,7 @@ static int stm32_exti_wakeup_isr(int irq, void *context, FAR void *arg)
* - event: generate event when set
* - func: when non-NULL, generate interrupt
*
- * Returns:
+ * Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
diff --git a/arch/arm/src/stm32/stm32_flash.h b/arch/arm/src/stm32/stm32_flash.h
index 6da1b0b70343096d86ca20bcf1e400ccfdf32638..4d5003b056764106dab8763096a27b6fa5831f14 100644
--- a/arch/arm/src/stm32/stm32_flash.h
+++ b/arch/arm/src/stm32/stm32_flash.h
@@ -56,7 +56,7 @@
* Description:
* Get EEPROM data memory size
*
- * Returns:
+ * Returned Value:
* Length of EEPROM memory region
*
************************************************************************************/
@@ -69,7 +69,7 @@ size_t stm32_eeprom_size(void);
* Description:
* Get EEPROM data memory address
*
- * Returns:
+ * Returned Value:
* Address of EEPROM memory region
*
************************************************************************************/
@@ -82,7 +82,7 @@ size_t stm32_eeprom_getaddress(void);
* Description:
* Write buffer to EEPROM data memory address
*
- * Returns:
+ * Returned Value:
* Number of written bytes or error code.
*
************************************************************************************/
@@ -95,7 +95,7 @@ ssize_t stm32_eeprom_write(size_t addr, const void *buf, size_t buflen);
* Description:
* Erase memory on EEPROM data memory address
*
- * Returns:
+ * Returned Value:
* Number of erased bytes or error code.
*
************************************************************************************/
diff --git a/arch/arm/src/stm32/stm32_gpio.c b/arch/arm/src/stm32/stm32_gpio.c
index 727f0c943a56ac9f6f794db9c62b0a85bc4e4e87..7a1d7800c4d109698a34af7b60f7d8a0cbe9d034 100644
--- a/arch/arm/src/stm32/stm32_gpio.c
+++ b/arch/arm/src/stm32/stm32_gpio.c
@@ -261,7 +261,7 @@ void stm32_gpioinit(void)
* function, it must be unconfigured with stm32_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
- * Returns:
+ * Returned Value:
* OK on success
* A negated errono valu on invalid port, or when pin is locked as ALT
* function.
@@ -667,7 +667,7 @@ int stm32_configgpio(uint32_t cfgset)
* operate in PWM mode could produce excessive on-board currents and trigger
* over-current/alarm function.
*
- * Returns:
+ * Returned Value:
* OK on success
* A negated errno value on invalid port
*
diff --git a/arch/arm/src/stm32/stm32_hrtim.c b/arch/arm/src/stm32/stm32_hrtim.c
index d064c8e1d3b4b4a43aece55a4f696c53e040bb85..3f40ca0e8e1038105b0a856bd5cad99336d3c530 100644
--- a/arch/arm/src/stm32/stm32_hrtim.c
+++ b/arch/arm/src/stm32/stm32_hrtim.c
@@ -117,9 +117,10 @@
# endif
#endif
#if defined(CONFIG_STM32_HRTIM_INTERRUPTS)
-#if !defined(CONFIG_STM32_HRTIM_TIMA_IRQ) && !defined(CONFIG_STM32_HRTIM_TIMB_IRQ) && \
- !defined(CONFIG_STM32_HRTIM_TIMC_IRQ) && !defined(CONFIG_STM32_HRTIM_TIMD_IRQ) && \
- !defined(CONFIG_STM32_HRTIM_TIME_IRQ)
+#if !defined(CONFIG_STM32_HRTIM_MASTER_IRQ) && !defined(CONFIG_STM32_HRTIM_TIMA_IRQ) && \
+ !defined(CONFIG_STM32_HRTIM_TIMB_IRQ) && !defined(CONFIG_STM32_HRTIM_TIMC_IRQ) && \
+ !defined(CONFIG_STM32_HRTIM_TIMD_IRQ) && !defined(CONFIG_STM32_HRTIM_TIME_IRQ) && \
+ !defined(CONFIG_STM32_HRTIM_COMMON_IRQ)
# warning "CONFIG_STM32_HRTIM_INTERRUPTS enabled but no timer selected"
# endif
#endif
@@ -180,6 +181,29 @@
# error "CONFIG_STM32_HRTIM_CHOPPER must be set"
# endif
#endif
+#if defined(CONFIG_STM32_HRTIM_TIMA_PSHPLL) || defined(CONFIG_STM32_HRTIM_TIMB_PSHPLL) || \
+ defined(CONFIG_STM32_HRTIM_TIMC_PSHPLL) || defined(CONFIG_STM32_HRTIM_TIMD_PSHPLL) || \
+ defined(CONFIG_STM32_HRTIM_TIME_PSHPLL)
+# ifndef CONFIG_STM32_HRTIM_PUSHPULL
+# error "CONFIG_STM32_HRTIM_PUSHPULL must be set"
+# endif
+#endif
+
+#if defined(CONFIG_STM32_HRTIM_TIMA_DT) && defined(CONFIG_STM32_HRTIM_TIMA_PSHPLL)
+# error "The deadtime cannot be used simultaneously with the push-pull mode"
+#endif
+#if defined(CONFIG_STM32_HRTIM_TIMB_DT) && defined(CONFIG_STM32_HRTIM_TIMB_PSHPLL)
+# error "The deadtime cannot be used simultaneously with the push-pull mode"
+#endif
+#if defined(CONFIG_STM32_HRTIM_TIMC_DT) && defined(CONFIG_STM32_HRTIM_TIMC_PSHPLL)
+# error "The deadtime cannot be used simultaneously with the push-pull mode"
+#endif
+#if defined(CONFIG_STM32_HRTIM_TIMD_DT) && defined(CONFIG_STM32_HRTIM_TIMD_PSHPLL)
+# error "The deadtime cannot be used simultaneously with the push-pull mode"
+#endif
+#if defined(CONFIG_STM32_HRTIM_TIME_DT) && defined(CONFIG_STM32_HRTIM_TIME_PSHPLL)
+# error "The deadtime cannot be used simultaneously with the push-pull mode"
+#endif
#if defined(CONFIG_STM32_HRTIM_ADC1_TRG1) || defined(CONFIG_STM32_HRTIM_ADC1_TRG2) || \
defined(CONFIG_STM32_HRTIM_ADC1_TRG3) || defined(CONFIG_STM32_HRTIM_ADC1_TRG4) || \
@@ -201,17 +225,13 @@
# define HRTIM_HAVE_ADC_TRG4
#endif
-#ifdef CONFIG_STM32_HRTIM_INTERRUPTS
-# error HRTIM Interrupts not supported yet
-#endif
-
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* HRTIM default configuration **********************************************/
-#ifndef HRTIM_TIMER_MASTER
+#ifndef HRTIM_MASTER_PRESCALER
# warning "HRTIM_MASTER_PRESCALER is not set. Set the default value HRTIM_PRESCALER_2"
# define HRTIM_MASTER_PRESCALER HRTIM_PRESCALER_2
#endif
@@ -305,7 +325,7 @@ struct stm32_hrtim_timout_s
#ifdef CONFIG_STM32_HRTIM_CHOPPER
struct stm32_hrtim_chopper_s
{
- uint16_t start:4; /* Chopper start pulsewidth */
+ uint16_t start_pulse:4; /* Chopper start pulsewidth */
uint16_t freq:4; /* Chopper carrier frequency value */
uint16_t duty:3; /* Chopper duty cycle */
uint16_t _res:5; /* Reserved */
@@ -317,10 +337,11 @@ struct stm32_hrtim_chopper_s
#ifdef CONFIG_STM32_HRTIM_DEADTIME
struct stm32_hrtim_deadtime_s
{
+ uint8_t en:1; /* Enable deadtime for timer */
uint8_t fsign_lock:1; /* Deadtime falling sing lock */
uint8_t rsign_lock:1; /* Deadtime rising sing lock */
- uint8_t rising_lock:1; /* Deadtime rising value lock */
uint8_t falling_lock:1; /* Deadtime falling value lock */
+ uint8_t rising_lock:1; /* Deadtime rising value lock */
uint8_t fsign:1; /* Deadtime falling sign */
uint8_t rsign:1; /* Deadtime rising sign */
uint8_t prescaler:3; /* Deadtime prescaler */
@@ -344,6 +365,8 @@ struct stm32_hrtim_tim_burst_s
struct stm32_hrtim_pwm_s
{
+ uint8_t pushpull:1;
+ uint8_t res:7;
struct stm32_hrtim_timout_s ch1; /* Channel 1 Set/Reset configuration*/
struct stm32_hrtim_timout_s ch2; /* Channel 2 Set/Reset configuration */
@@ -374,12 +397,13 @@ struct stm32_hrtim_capture_s
struct stm32_hrtim_timcmn_s
{
uint32_t base; /* The base adress of the timer */
- uint32_t pclk; /* The frequency of the peripheral clock
+ uint64_t fclk; /* The frequency of the peripheral clock
* that drives the timer module.
*/
+ uint8_t prescaler:3; /* Prescaler */
uint8_t mode; /* Timer mode */
uint8_t dac:2; /* DAC triggering */
- uint8_t reserved:6;
+ uint8_t reserved:3;
#ifdef CONFIG_STM32_HRTIM_INTERRUPTS
uint16_t irq; /* interrupts configuration */
#endif
@@ -420,7 +444,7 @@ struct stm32_hrtim_slave_priv_s
#endif
#endif
uint16_t update; /* Update configuration */
- uint32_t reset; /* Timer reset events */
+ uint64_t reset; /* Timer reset events */
#ifdef CONFIG_STM32_HRTIM_PWM
struct stm32_hrtim_pwm_s pwm; /* PWM configuration */
#endif
@@ -609,7 +633,7 @@ static void hrtim_tim_putreg(FAR struct stm32_hrtim_s *priv, uint8_t timer,
static void hrtim_tim_modifyreg(FAR struct stm32_hrtim_s *priv, uint8_t timer,
uint32_t offset, uint32_t clrbits, uint32_t setbits);
-#ifdef CONFIG_DEBUG_POWER_INFO
+#ifdef CONFIG_DEBUG_TIMER_INFO
static void hrtim_dumpregs(FAR struct stm32_hrtim_s *priv, uint8_t timer,
FAR const char *msg);
#else
@@ -622,6 +646,8 @@ static uint32_t hrtim_tim_getreg(FAR struct stm32_hrtim_s *priv, uint8_t timer,
uint32_t offset);
static FAR struct stm32_hrtim_tim_s *hrtim_tim_get(FAR struct stm32_hrtim_s *priv,
uint8_t timer);
+static FAR struct stm32_hrtim_slave_priv_s *hrtim_slave_get(FAR struct stm32_hrtim_s *priv,
+ uint8_t timer);
static uint32_t hrtim_base_get(FAR struct stm32_hrtim_s *priv, uint8_t timer);
/* Configuration */
@@ -645,6 +671,10 @@ static int hrtim_synch_config(FAR struct stm32_hrtim_s *priv);
static int hrtim_outputs_config(FAR struct stm32_hrtim_s *priv);
static int hrtim_outputs_enable(FAR struct hrtim_dev_s *dev, uint16_t outputs,
bool state);
+static int hrtim_output_set_set(FAR struct hrtim_dev_s *dev, uint16_t output,
+ uint32_t set);
+static int hrtim_output_rst_set(FAR struct hrtim_dev_s *dev, uint16_t output,
+ uint32_t rst);
#endif
#ifdef HRTIM_HAVE_ADC
static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv);
@@ -658,13 +688,15 @@ static int hrtim_tim_dma_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer,
uint16_t dma);
#endif
#ifdef CONFIG_STM32_HRTIM_DEADTIME
-static int hrtim_deadtime_update(FAR struct stm32_dev_s *dev, uint8_t dt,
- uint16_t value)
-static uint16_t hrtim_deadtime_get(FAR struct stm32_dev_s *dev, uint8_t dt);
+static int hrtim_deadtime_update(FAR struct hrtim_dev_s *dev, uint8_t timer,
+ uint8_t dt, uint16_t value);
+static uint16_t hrtim_deadtime_get(FAR struct hrtim_dev_s *dev, uint8_t timer,
+ uint8_t dt);
+static int hrtim_tim_deadtime_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer);
static int hrtim_deadtime_config(FAR struct stm32_hrtim_s *priv);
#endif
#ifdef CONFIG_STM32_HRTIM_CHOPPER
-static int hrtim_chopper_enable(FAR struct stm32_dev_s *dev, uint8_t timer,
+static int hrtim_chopper_enable(FAR struct hrtim_dev_s *dev, uint8_t timer,
uint8_t chan, bool state);
static int hrtim_tim_chopper_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer);
static int hrtim_chopper_config(FAR struct stm32_hrtim_s *priv);
@@ -690,7 +722,8 @@ static int hrtim_eev_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index);
#endif
#ifdef CONFIG_STM32_HRTIM_INTERRUPTS
static int hrtim_irq_config(FAR struct stm32_hrtim_s *priv);
-static void hrtim_irq_ack(FAR struct hrtim_dev_s *dev, uint8_t timer, int source);
+static uint16_t hrtim_irq_get(FAR struct hrtim_dev_s *dev, uint8_t timer);
+static int hrtim_irq_ack(FAR struct hrtim_dev_s *dev, uint8_t timer, int source);
#endif
static int hrtim_cmp_update(FAR struct hrtim_dev_s *dev, uint8_t timer,
uint8_t index, uint16_t cmp);
@@ -699,11 +732,15 @@ static int hrtim_per_update(FAR struct hrtim_dev_s *dev, uint8_t timer,
static uint16_t hrtim_per_get(FAR struct hrtim_dev_s *dev, uint8_t timer);
static uint16_t hrtim_cmp_get(FAR struct hrtim_dev_s *dev, uint8_t timer,
uint8_t index);
+static uint64_t hrtim_fclk_get(FAR struct hrtim_dev_s *dev, uint8_t timer);
+static int hrtim_soft_update(FAR struct hrtim_dev_s *dev, uint8_t timer);
+static int hrtim_tim_freq_set(FAR struct hrtim_dev_s *hrtim, uint8_t timer,
+ uint64_t freq);
static int hrtim_tim_reset_set(FAR struct stm32_hrtim_s *priv, uint8_t timer,
- uint32_t reset);
+ uint64_t reset);
static int hrtim_reset_config(FAR struct stm32_hrtim_s *priv);
static int hrtim_tim_update_set(FAR struct stm32_hrtim_s *priv, uint8_t timer,
- uint32_t update);
+ uint16_t update);
static int hrtim_update_config(FAR struct stm32_hrtim_s *priv);
static void hrtim_tim_mode_set(FAR struct stm32_hrtim_s *priv, uint8_t timer,
@@ -747,20 +784,21 @@ static struct stm32_hrtim_tim_s g_master =
/* If MASTER is disabled, we need only MASTER base */
#ifdef CONFIG_STM32_HRTIM_MASTER
- .pclk = HRTIM_CLOCK/(HRTIM_MASTER_PRESCALER+1),
- .mode = HRTIM_MASTER_MODE,
+ .fclk = HRTIM_CLOCK/(1<priv;
+
+errout:
+ return slave;
+}
+
/****************************************************************************
* Name: hrtim_base_get
*
@@ -1873,32 +1989,32 @@ static void hrtim_tim_modifyreg(FAR struct stm32_hrtim_s *priv, uint8_t timer,
(hrtim_tim_getreg(priv, timer, offset) & ~clrbits) | setbits);
}
-#ifdef CONFIG_DEBUG_POWER_INFO
+#ifdef CONFIG_DEBUG_TIMER_INFO
static void hrtim_dumpregs(FAR struct stm32_hrtim_s *priv, uint8_t timer,
FAR const char *msg)
{
- pwrinfo("%s:\n", msg);
+ tmrinfo("%s:\n", msg);
switch (timer)
{
case HRTIM_TIMER_MASTER:
{
- pwrinfo("\tCR:\t0x%08x\tISR:\t0x%08x\tICR:\t0x%08x\n",
+ tmrinfo("\tCR:\t0x%08x\tISR:\t0x%08x\tICR:\t0x%08x\n",
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ISR_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ICR_OFFSET));
- pwrinfo("\tDIER:\t0x%08x\tCNTR:\t0x%08x\tPER:\t0x%08x\n",
+ tmrinfo("\tDIER:\t0x%08x\tCNTR:\t0x%08x\tPER:\t0x%08x\n",
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_DIER_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CNTR_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_PER_OFFSET));
- pwrinfo("\tREP:\t0x%08x\tCMP1:\t0x%08x\tCMP2:\t0x%08x\n",
+ tmrinfo("\tREP:\t0x%08x\tCMP1:\t0x%08x\tCMP2:\t0x%08x\n",
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_REPR_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CMP1R_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CMP2R_OFFSET));
- pwrinfo("\tCMP3:\t0x%08x\tCMP4:\t0x%08x\n",
+ tmrinfo("\tCMP3:\t0x%08x\tCMP4:\t0x%08x\n",
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CMP3R_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CMP4R_OFFSET));
break;
@@ -1920,47 +2036,47 @@ static void hrtim_dumpregs(FAR struct stm32_hrtim_s *priv, uint8_t timer,
case HRTIM_TIMER_TIME:
#endif
{
- pwrinfo("\tCR:\t0x%08x\tISR:\t0x%08x\tICR:\t0x%08x\n",
+ tmrinfo("\tCR:\t0x%08x\tISR:\t0x%08x\tICR:\t0x%08x\n",
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ISR_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ICR_OFFSET));
- pwrinfo("\tDIER:\t0x%08x\tCNTR:\t0x%08x\tPER:\t0x%08x\n",
+ tmrinfo("\tDIER:\t0x%08x\tCNTR:\t0x%08x\tPER:\t0x%08x\n",
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_DIER_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CNTR_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_PER_OFFSET));
- pwrinfo("\tREP:\t0x%08x\tCMP1:\t0x%08x\tCMP1C:\t0x%08x\n",
+ tmrinfo("\tREP:\t0x%08x\tCMP1:\t0x%08x\tCMP1C:\t0x%08x\n",
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_REPR_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CMP1R_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CMP1CR_OFFSET));
- pwrinfo("\tCMP2:\t0x%08x\tCMP3:\t0x%08x\tCMP4:\t0x%08x\n",
+ tmrinfo("\tCMP2:\t0x%08x\tCMP3:\t0x%08x\tCMP4:\t0x%08x\n",
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CMP2R_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CMP3R_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CMP4R_OFFSET));
- pwrinfo("\tCPT1:\t0x%08x\tCPT2:\t0x%08x\tDTR:\t0x%08x\n",
+ tmrinfo("\tCPT1:\t0x%08x\tCPT2:\t0x%08x\tDTR:\t0x%08x\n",
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CPT1R_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CPT2R_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_DTR_OFFSET));
- pwrinfo("\tSET1:\t0x%08x\tRST1:\t0x%08x\tSET2:\t0x%08x\n",
+ tmrinfo("\tSET1:\t0x%08x\tRST1:\t0x%08x\tSET2:\t0x%08x\n",
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_SET1R_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_RST1R_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_SET2R_OFFSET));
- pwrinfo("\tRST2:\t0x%08x\tEEF1:\t0x%08x\tEEF2:\t0x%08x\n",
+ tmrinfo("\tRST2:\t0x%08x\tEEF1:\t0x%08x\tEEF2:\t0x%08x\n",
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_RST2R_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_EEFR1_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_EEFR2_OFFSET));
- pwrinfo("\tRSTR:\t0x%08x\tCHPR:\t0x%08x\tCPT1C:\t0x%08x\n",
+ tmrinfo("\tRSTR:\t0x%08x\tCHPR:\t0x%08x\tCPT1C:\t0x%08x\n",
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_RSTR_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CHPR_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CPT1CR_OFFSET));
- pwrinfo("\tCPT2C:\t0x%08x\tOUT:\t0x%08x\tFLT:\t0x%08x\n",
+ tmrinfo("\tCPT2C:\t0x%08x\tOUT:\t0x%08x\tFLT:\t0x%08x\n",
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CPT2CR_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET),
hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_FLTR_OFFSET));
@@ -1970,47 +2086,47 @@ static void hrtim_dumpregs(FAR struct stm32_hrtim_s *priv, uint8_t timer,
case HRTIM_TIMER_COMMON:
{
- pwrinfo("\tCR1:\t0x%08x\tCR2:\t0x%08x\tISR:\t0x%08x\n",
+ tmrinfo("\tCR1:\t0x%08x\tCR2:\t0x%08x\tISR:\t0x%08x\n",
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_CR1_OFFSET),
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_CR2_OFFSET),
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ISR_OFFSET));
- pwrinfo("\tICR:\t0x%08x\tIER:\t0x%08x\tOENR:\t0x%08x\n",
+ tmrinfo("\tICR:\t0x%08x\tIER:\t0x%08x\tOENR:\t0x%08x\n",
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ICR_OFFSET),
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_IER_OFFSET),
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_OENR_OFFSET));
- pwrinfo("\tODISR:\t0x%08x\tODSR:\t0x%08x\tBMCR:\t0x%08x\n",
+ tmrinfo("\tODISR:\t0x%08x\tODSR:\t0x%08x\tBMCR:\t0x%08x\n",
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ODISR_OFFSET),
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ODSR_OFFSET),
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET));
- pwrinfo("\tBMTRG:\t0x%08x\tBMCMPR:\t0x%08x\tBMPER:\t0x%08x\n",
+ tmrinfo("\tBMTRG:\t0x%08x\tBMCMPR:\t0x%08x\tBMPER:\t0x%08x\n",
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMTRGR_OFFSET),
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMCMPR_OFFSET),
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMPER_OFFSET));
- pwrinfo("\tADC1R:\t0x%08x\tADC2R:\t0x%08x\tADC3R:\t0x%08x\n",
+ tmrinfo("\tADC1R:\t0x%08x\tADC2R:\t0x%08x\tADC3R:\t0x%08x\n",
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC1R_OFFSET),
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC2R_OFFSET),
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC3R_OFFSET));
- pwrinfo("\tADC4R:\t0x%08x\tDLLCR:\t0x%08x\tFLTIN1:\t0x%08x\n",
+ tmrinfo("\tADC4R:\t0x%08x\tDLLCR:\t0x%08x\tFLTIN1:\t0x%08x\n",
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC4R_OFFSET),
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_DLLCR_OFFSET),
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_FLTINR1_OFFSET));
- pwrinfo("\tFLTIN2:\t0x%08x\tBDMUPD:\t0x%08x\tBDTAUP:\t0x%08x\n",
+ tmrinfo("\tFLTIN2:\t0x%08x\tBDMUPD:\t0x%08x\tBDTAUP:\t0x%08x\n",
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET),
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDMUPDR_OFFSET),
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTAUPR_OFFSET));
- pwrinfo("\tBDTBUP: 0x%08x\tBDTCUP:\t0x%08x\tBDTDUP:\t0x%08x\n",
+ tmrinfo("\tBDTBUP: 0x%08x\tBDTCUP:\t0x%08x\tBDTDUP:\t0x%08x\n",
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTBUPR_OFFSET),
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTCUPR_OFFSET),
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTDUPR_OFFSET));
- pwrinfo("\tBDTEUP:\t0x%08x\tBDMAD:\t0x%08x\n",
+ tmrinfo("\tBDTEUP:\t0x%08x\tBDMAD:\t0x%08x\n",
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTEUPR_OFFSET),
hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDMADR_OFFSET));
@@ -2036,7 +2152,7 @@ static void hrtim_dumpregs(FAR struct stm32_hrtim_s *priv, uint8_t timer,
* priv - A reference to the HRTIM structure
*
* Returned Value:
- * 0 on success, a negated errno value on failure
+ * 0 on success, a negated errno value on failure
*
****************************************************************************/
@@ -2080,7 +2196,7 @@ static int hrtim_dll_cal(FAR struct stm32_hrtim_s *priv)
* timer - An HRTIM Timer index
*
* Returned Value:
- * 0 on success, a negated errno value on failure
+ * 0 on success, a negated errno value on failure
*
****************************************************************************/
@@ -2151,6 +2267,10 @@ static int hrtim_tim_clock_config(FAR struct stm32_hrtim_s *priv,
}
}
+ /* Write prescaler configuration */
+
+ hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, regval);
+
errout:
return ret;
}
@@ -2165,7 +2285,7 @@ errout:
* priv - A reference to the HRTIM structure
*
* Returned Value:
- * 0 on success, a negated errno value on failure
+ * 0 on success, a negated errno value on failure
*
****************************************************************************/
@@ -2247,7 +2367,7 @@ errout:
* priv - A reference to the HRTIM structure
*
* Returned Value:
- * 0 on success, a negated errno value on failure
+ * 0 on success, a negated errno value on failure
*
****************************************************************************/
@@ -2444,13 +2564,13 @@ static int hrtim_gpios_config(FAR struct stm32_hrtim_s *priv)
* Description:
* Configure HRTIM Captures
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the HRTIM block
* timer - HRTIM Timer index
* capture - capture trigers configuration
*
* Returned Value:
- * None
+ * 0 on success, a negated errno value on failure
*
****************************************************************************/
@@ -2461,7 +2581,9 @@ static int hrtim_tim_capture_cfg(FAR struct stm32_hrtim_s *priv,
int ret = OK;
uint32_t offset = 0;
- if (timer == HRTIM_TIMER_MASTER)
+ /* Sanity checking */
+
+ if (timer == HRTIM_TIMER_MASTER || timer == HRTIM_TIMER_COMMON)
{
ret = -EINVAL;
goto errout;
@@ -2500,11 +2622,11 @@ errout:
* Description:
* Configure HRTIM Captures
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the HRTIM block
*
* Returned Value:
- * None
+ * 0 on success, a negated errno value on failure
*
****************************************************************************/
@@ -2551,13 +2673,13 @@ static int hrtim_capture_config(FAR struct stm32_hrtim_s *priv)
* Description:
* Get HRTIM Timer Capture register
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the HRTIM block
* timer - HRTIM Timer index
* index - Capture register index
*
* Returned Value:
- * None
+ * Timer Capture value on success, 0 on failure
*
****************************************************************************/
@@ -2606,7 +2728,7 @@ errout:
* priv - A reference to the HRTIM structure
*
* Returned Value:
- * 0 on success, a negated errno value on failure
+ * 0 on success, a negated errno value on failure
*
****************************************************************************/
@@ -2628,38 +2750,26 @@ static int hrtim_synch_config(FAR struct stm32_hrtim_s *priv)
* priv - A reference to the HRTIM structure
*
* Returned Value:
- * 0 on success, a negated errno value on failure
+ * 0 on success, a negated errno value on failure
*
****************************************************************************/
#if defined(CONFIG_STM32_HRTIM_PWM)
static int hrtim_tim_outputs_config(FAR struct stm32_hrtim_s *priv, uint8_t timer)
{
- FAR struct stm32_hrtim_tim_s* tim;
FAR struct stm32_hrtim_slave_priv_s* slave;
-
- int ret = OK;
uint32_t regval = 0;
+ int ret = OK;
- /* Master Timer has no outputs */
-
- if (timer == HRTIM_TIMER_MASTER)
- {
- ret = -EINVAL;
- goto errout;
- }
-
- /* Get Timer data strucutre */
+ /* Get Slave Timer data structure */
- tim = hrtim_tim_get(priv, timer);
- if (tim == NULL)
+ slave = hrtim_slave_get(priv, timer);
+ if (slave == NULL)
{
ret = -EINVAL;
goto errout;
}
- slave = (struct stm32_hrtim_slave_priv_s*)tim->priv;
-
/* Configure CH1 SET events */
regval = slave->pwm.ch1.set;
@@ -2724,6 +2834,33 @@ static int hrtim_tim_outputs_config(FAR struct stm32_hrtim_s *priv, uint8_t time
}
#endif
+#ifdef CONFIG_STM32_HRTIM_DEADTIME
+ if (slave->pwm.dt.en == 1)
+ {
+ regval = 0;
+
+ /* Set deadtime enable */
+
+ regval |= HRTIM_TIMOUT_DTEN;
+
+ /* TODO: deadtime upon burst mode Idle entry */
+
+ /* Write register */
+
+ hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET, 0,
+ regval);
+ }
+#endif
+
+#ifdef CONFIG_STM32_HRTIM_PUSHPULL
+ if (slave->pwm.pushpull == 1)
+ {
+ /* Enable push-pull mode */
+
+ hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, 0, HRTIM_TIMCR_PSHPLL);
+ }
+#endif
+
errout:
return ret;
}
@@ -2739,7 +2876,7 @@ errout:
* priv - A reference to the HRTIM structure
*
* Returned Value:
- * 0 on success, a negated errno value on failure
+ * 0 on success, a negated errno value on failure
*
****************************************************************************/
@@ -2814,7 +2951,7 @@ errout:
* state - Enable/disable operation
*
* Returned Value:
- * 0 on success, a negated errno value on failure
+ * 0 on success, a negated errno value on failure
*
****************************************************************************/
@@ -2841,123 +2978,354 @@ static int hrtim_outputs_enable(FAR struct hrtim_dev_s *dev,
return OK;
}
-#endif
/****************************************************************************
- * Name: hrtim_adc_config
- *
- * Description:
- * Configure HRTIM ADC triggers
- *
- * Input Parameters:
- * priv - A reference to the HRTIM structure
- *
- * Returned Value:
- * 0 on success, a negated errno value on failure
- *
+ * Name: output_tim_index_get
****************************************************************************/
-#ifdef HRTIM_HAVE_ADC
-static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv)
+static uint8_t output_tim_index_get(uint16_t output)
{
- /* Configure ADC Trigger 1 */
+ uint8_t timer = 0;
-#ifdef HRTIM_HAVE_ADC_TRG1
- hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC1R_OFFSET, priv->adc->trg1);
+ switch(output)
+ {
+#ifdef CONFIG_STM32_HRTIM_TIMA
+ case HRTIM_OUT_TIMA_CH1:
+ case HRTIM_OUT_TIMA_CH2:
+ {
+ timer = HRTIM_TIMER_TIMA;
+ break;
+ }
#endif
- /* Configure ADC Trigger 2 */
-
-#ifdef HRTIM_HAVE_ADC_TRG2
- hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC2R_OFFSET, priv->adc->trg2);
+#ifdef CONFIG_STM32_HRTIM_TIMB
+ case HRTIM_OUT_TIMB_CH1:
+ case HRTIM_OUT_TIMB_CH2:
+ {
+ timer = HRTIM_TIMER_TIMB;
+ break;
+ }
#endif
- /* Configure ADC Trigger 3 */
-
-#ifdef HRTIM_HAVE_ADC_TRG3
- hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC3R_OFFSET, priv->adc->trg3);
+#ifdef CONFIG_STM32_HRTIM_TIMC
+ case HRTIM_OUT_TIMC_CH1:
+ case HRTIM_OUT_TIMC_CH2:
+ {
+ timer = HRTIM_TIMER_TIMC;
+ break;
+ }
#endif
- /* Configure ADC Trigger 4 */
+#ifdef CONFIG_STM32_HRTIM_TIMD
+ case HRTIM_OUT_TIMD_CH1:
+ case HRTIM_OUT_TIMD_CH2:
+ {
+ timer = HRTIM_TIMER_TIMD;
+ break;
+ }
+#endif
-#ifdef HRTIM_HAVE_ADC_TRG4
- hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC4R_OFFSET, priv->adc->trg4);
+#ifdef CONFIG_STM32_HRTIM_TIME
+ case HRTIM_OUT_TIME_CH1:
+ case HRTIM_OUT_TIME_CH2:
+ {
+ timer = HRTIM_TIMER_TIME;
+ break;
+ }
#endif
- return OK;
+ default:
+ {
+ timer = 0;
+ break;
+ }
+ }
+
+ return timer;
}
-#endif
-#ifdef CONFIG_STM32_HRTIM_DAC
/****************************************************************************
- * Name: hrtim_tim_dac_cfg
- *
- * Description:
- * Configure single HRTIM Timer DAC synchronization event
- *
- * Input Parameters:
- * priv - A reference to the HRTIM structure
- * timer - Timer index
- * dac - DAC synchronisation event configuration
- *
- * Returned Value:
- * 0 on success, a negated errno value on failure
- *
+ * Name: output_tim_ch_get
****************************************************************************/
-static int hrtim_tim_dac_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer,
- uint8_t dac)
+static uint8_t output_tim_ch_get(uint16_t output)
{
- FAR struct stm32_hrtim_tim_s *tim;
- uint32_t regval = 0;
-
- tim = hrtim_tim_get(priv, timer);
+ uint8_t ch = 0;
- regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET);
+ switch (output)
+ {
+#ifdef CONFIG_STM32_HRTIM_TIMA
+ case HRTIM_OUT_TIMA_CH1:
+#endif
+#ifdef CONFIG_STM32_HRTIM_TIMB
+ case HRTIM_OUT_TIMB_CH1:
+#endif
+#ifdef CONFIG_STM32_HRTIM_TIMC
+ case HRTIM_OUT_TIMC_CH1:
+#endif
+#ifdef CONFIG_STM32_HRTIM_TIMD
+ case HRTIM_OUT_TIMD_CH1:
+#endif
+#ifdef CONFIG_STM32_HRTIM_TIME
+ case HRTIM_OUT_TIME_CH1:
+#endif
+ {
+ ch = HRTIM_OUT_CH1;
+ break;
+ }
- regval |= (dac << HRTIM_CMNCR_DACSYNC_SHIFT);
+#ifdef CONFIG_STM32_HRTIM_TIMA
+ case HRTIM_OUT_TIMA_CH2:
+#endif
+#ifdef CONFIG_STM32_HRTIM_TIMB
+ case HRTIM_OUT_TIMB_CH2:
+#endif
+#ifdef CONFIG_STM32_HRTIM_TIMC
+ case HRTIM_OUT_TIMC_CH2:
+#endif
+#ifdef CONFIG_STM32_HRTIM_TIMD
+ case HRTIM_OUT_TIMD_CH2:
+#endif
+#ifdef CONFIG_STM32_HRTIM_TIME
+ case HRTIM_OUT_TIME_CH2:
+#endif
+ {
+ ch = HRTIM_OUT_CH2;
+ break;
+ }
- hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, regval);
+ default:
+ {
+ ch = 0;
+ break;
+ }
+ }
- return OK;
+ return ch;
}
/****************************************************************************
- * Name: hrtim_dac_config
- *
- * Description:
- * Configure HRTIM DAC synchronization
- *
- * Input Parameters:
- * priv - A reference to the HRTIM structure
- *
- * Returned Value:
- * 0 on success, a negated errno value on failure
- *
+ * Name: hrtim_output_set_set
****************************************************************************/
-static int hrtim_dac_config(FAR struct stm32_hrtim_s *priv)
+static int hrtim_output_set_set(FAR struct hrtim_dev_s *dev, uint16_t output,
+ uint32_t set)
{
- FAR struct stm32_hrtim_timcmn_s *tim;
+ FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv;
+ FAR struct stm32_hrtim_slave_priv_s* slave;
+ uint8_t timer = 0;
+ int ret = OK;
- /* Configure DAC synchronization for Master Timer */
+ /* Get timer index from output */
-#ifdef CONFIG_STM32_HRTIM_MASTER_DAC
- tim = (struct stm32_hrtim_timcmn_s*)priv->master;
- hrtim_tim_dac_cfg(priv, HRTIM_TIMER_MASTER, tim->dac);
-#endif
+ timer = output_tim_index_get(output);
- /* Configure DAC synchronization for Timer A */
+ /* Get Slave Timer data strucutre */
-#ifdef CONFIG_STM32_HRTIM_TIMA_DAC
- tim = (struct stm32_hrtim_timcmn_s*)priv->tima;
- hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMA, tim->dac);
-#endif
+ slave = hrtim_slave_get(priv, timer);
+ if (slave == NULL)
+ {
+ ret = -EINVAL;
+ goto errout;
+ }
- /* Configure DAC synchronization for Timer B */
+ /* Set new SET value */
-#ifdef CONFIG_STM32_HRTIM_TIMB_DAC
- tim = (struct stm32_hrtim_timcmn_s*)priv->timb;
+ switch (output_tim_ch_get(output))
+ {
+ case HRTIM_OUT_CH1:
+ {
+ slave->pwm.ch1.set = set;
+ hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_SET1R_OFFSET, set);
+ break;
+ }
+
+ case HRTIM_OUT_CH2:
+ {
+ slave->pwm.ch2.set = set;
+ hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_SET2R_OFFSET, set);
+ break;
+ }
+
+ default:
+ {
+ ret = -EINVAL;
+ goto errout;
+ }
+ }
+
+errout:
+ return ret;
+}
+
+/****************************************************************************
+ * Name: hrtim_output_rst_set
+ ****************************************************************************/
+static int hrtim_output_rst_set(FAR struct hrtim_dev_s *dev, uint16_t output,
+ uint32_t rst)
+{
+ FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv;
+ FAR struct stm32_hrtim_slave_priv_s* slave;
+ uint8_t timer = 0;
+ int ret = OK;
+
+ /* Get timer index from output */
+
+ timer = output_tim_index_get(output);
+
+ /* Get Salve Timer data strucutre */
+
+ slave = hrtim_slave_get(priv, timer);
+ if (slave == NULL)
+ {
+ ret = -EINVAL;
+ goto errout;
+ }
+
+ /* Set new RST value */
+
+ switch (output_tim_ch_get(output))
+ {
+ case HRTIM_OUT_CH1:
+ {
+ slave->pwm.ch1.rst = rst;
+ hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RST1R_OFFSET, rst);
+ }
+
+ case HRTIM_OUT_CH2:
+ {
+ slave->pwm.ch2.rst = rst;
+ hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RST2R_OFFSET, rst);
+ }
+
+ default:
+ {
+ ret = -EINVAL;
+ goto errout;
+ }
+ }
+
+errout:
+ return ret;
+}
+
+#endif
+
+/****************************************************************************
+ * Name: hrtim_adc_config
+ *
+ * Description:
+ * Configure HRTIM ADC triggers
+ *
+ * Input Parameters:
+ * priv - A reference to the HRTIM structure
+ *
+ * Returned Value:
+ * 0 on success, a negated errno value on failure
+ *
+ ****************************************************************************/
+
+#ifdef HRTIM_HAVE_ADC
+static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv)
+{
+ /* Configure ADC Trigger 1 */
+
+#ifdef HRTIM_HAVE_ADC_TRG1
+ hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC1R_OFFSET, priv->adc->trg1);
+#endif
+
+ /* Configure ADC Trigger 2 */
+
+#ifdef HRTIM_HAVE_ADC_TRG2
+ hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC2R_OFFSET, priv->adc->trg2);
+#endif
+
+ /* Configure ADC Trigger 3 */
+
+#ifdef HRTIM_HAVE_ADC_TRG3
+ hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC3R_OFFSET, priv->adc->trg3);
+#endif
+
+ /* Configure ADC Trigger 4 */
+
+#ifdef HRTIM_HAVE_ADC_TRG4
+ hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC4R_OFFSET, priv->adc->trg4);
+#endif
+
+ return OK;
+}
+#endif
+
+#ifdef CONFIG_STM32_HRTIM_DAC
+/****************************************************************************
+ * Name: hrtim_tim_dac_cfg
+ *
+ * Description:
+ * Configure single HRTIM Timer DAC synchronization event
+ *
+ * Input Parameters:
+ * priv - A reference to the HRTIM structure
+ * timer - Timer index
+ * dac - DAC synchronisation event configuration
+ *
+ * Returned Value:
+ * 0 on success, a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int hrtim_tim_dac_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer,
+ uint8_t dac)
+{
+ FAR struct stm32_hrtim_tim_s *tim;
+ uint32_t regval = 0;
+
+ tim = hrtim_tim_get(priv, timer);
+
+ regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET);
+
+ regval |= (dac << HRTIM_CMNCR_DACSYNC_SHIFT);
+
+ hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, regval);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: hrtim_dac_config
+ *
+ * Description:
+ * Configure HRTIM DAC synchronization
+ *
+ * Input Parameters:
+ * priv - A reference to the HRTIM structure
+ *
+ * Returned Value:
+ * 0 on success, a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int hrtim_dac_config(FAR struct stm32_hrtim_s *priv)
+{
+ FAR struct stm32_hrtim_timcmn_s *tim;
+
+ /* Configure DAC synchronization for Master Timer */
+
+#ifdef CONFIG_STM32_HRTIM_MASTER_DAC
+ tim = (struct stm32_hrtim_timcmn_s*)priv->master;
+ hrtim_tim_dac_cfg(priv, HRTIM_TIMER_MASTER, tim->dac);
+#endif
+
+ /* Configure DAC synchronization for Timer A */
+
+#ifdef CONFIG_STM32_HRTIM_TIMA_DAC
+ tim = (struct stm32_hrtim_timcmn_s*)priv->tima;
+ hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMA, tim->dac);
+#endif
+
+ /* Configure DAC synchronization for Timer B */
+
+#ifdef CONFIG_STM32_HRTIM_TIMB_DAC
+ tim = (struct stm32_hrtim_timcmn_s*)priv->timb;
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMB, tim->dac);
#endif
@@ -2997,6 +3365,14 @@ static int hrtim_tim_dma_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer,
int ret = OK;
uint32_t regval = 0;
+ /* Sanity checking */
+
+ if (timer == HRTIM_TIMER_COMMON)
+ {
+ ret = -EINVAL;
+ goto errout;
+ }
+
if (timer == HRTIM_TIMER_MASTER)
{
/* Master support first 7 DMA requests */
@@ -3069,7 +3445,7 @@ static int hrtim_dma_cfg(FAR struct stm32_hrtim_s *priv)
* Name: hrtim_deadtime_update
****************************************************************************/
-static int hrtim_deadtime_update(FAR struct stm32_dev_s *dev, uint8_t timer,
+static int hrtim_deadtime_update(FAR struct hrtim_dev_s *dev, uint8_t timer,
uint8_t dt, uint16_t value)
{
FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv;
@@ -3078,17 +3454,18 @@ static int hrtim_deadtime_update(FAR struct stm32_dev_s *dev, uint8_t timer,
uint32_t shift = 0;
uint32_t mask = 0;
- /* Sanity check */
+ /* For safety reasons we saturate deadtime value if it exceeds
+ * the acceptable range.
+ */
if (value > 0x1FF)
{
- ret = -EINVAL;
- goto errout;
+ value = 0x1FF;
}
/* Get shift value */
- switch (index)
+ switch (dt)
{
case HRTIM_DT_EDGE_RISING:
{
@@ -3115,7 +3492,7 @@ static int hrtim_deadtime_update(FAR struct stm32_dev_s *dev, uint8_t timer,
/* Update register */
- hrtim_tim_modify(priv, timer, STM32_HRTIM_TIM_DTR_OFFSET, mask, regval);
+ hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_DTR_OFFSET, mask, regval);
errout:
return ret;
@@ -3125,7 +3502,8 @@ errout:
* Name: hrtim_deadtime_get
****************************************************************************/
-static uint16_t hrtim_deadtime_get(FAR struct stm32_dev_s *dev, uint8_t dt)
+static uint16_t hrtim_deadtime_get(FAR struct hrtim_dev_s *dev, uint8_t timer,
+ uint8_t dt)
{
#warning missing logic
}
@@ -3134,19 +3512,32 @@ static uint16_t hrtim_deadtime_get(FAR struct stm32_dev_s *dev, uint8_t dt)
* Name: hrtim_tim_deadtime_cfg
****************************************************************************/
-static int hrtim_tim_deadtime_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index)
+static int hrtim_tim_deadtime_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer)
{
FAR struct stm32_hrtim_slave_priv_s* slave;
uint32_t regval = 0;
int ret = OK;
- if (timer == HRTIM_TIMER_MASTER)
+ /* Sanity checking */
+
+ if (timer == HRTIM_TIMER_MASTER || timer == HRTIM_TIMER_COMMON)
{
ret = -EINVAL;
goto errout;
}
- slave = (struct stm32_hrtim_slave_priv_s*)tim->priv;
+ /* Get Slave Timer data strucutre */
+
+ slave = hrtim_slave_get(priv, timer);
+ if (slave == NULL)
+ {
+ ret = -EINVAL;
+ goto errout;
+ }
+
+ /* Configure deadtime prescaler */
+
+ regval |= slave->pwm.dt.prescaler << HRTIM_TIMDT_DTPRSC_SHIFT;
/* Configure rising deadtime */
@@ -3158,14 +3549,14 @@ static int hrtim_tim_deadtime_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index)
/* Configure falling deadtime sign */
- if (slave->pwm.dt.fsign == HRTIM_DT_SIGN_POSITIVE)
+ if (slave->pwm.dt.fsign == HRTIM_DT_SIGN_NEGATIVE)
{
regval |= HRTIM_TIMDT_SDTF;
}
/* Configure risign deadtime sign */
- if (slave->pwm.dt.rsign == HRTIM_DT_SIGN_POSITIVE)
+ if (slave->pwm.dt.rsign == HRTIM_DT_SIGN_NEGATIVE)
{
regval |= HRTIM_TIMDT_SDTR;
}
@@ -3198,6 +3589,12 @@ static int hrtim_tim_deadtime_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index)
regval |= HRTIM_TIMDT_DTFLK;
}
+ /* TODO: configure default deadtime values */
+
+ /* Write register */
+
+ hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_DTR_OFFSET, regval);
+
errout:
return ret;
}
@@ -3210,31 +3607,31 @@ static int hrtim_deadtime_config(FAR struct stm32_hrtim_s *priv)
{
/* Configure Timer A deadtime */
-#ifdef CONFIG_STM32_HRTIM_TIMA
+#ifdef CONFIG_STM32_HRTIM_TIMA_DT
hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIMA);
#endif
/* Configure Timer B deadtime */
-#ifdef CONFIG_STM32_HRTIM_TIMB
+#ifdef CONFIG_STM32_HRTIM_TIMB_DT
hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIMB);
#endif
/* Configure Timer C deadtime */
-#ifdef CONFIG_STM32_HRTIM_TIMC
+#ifdef CONFIG_STM32_HRTIM_TIMC_DT
hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIMC);
#endif
/* Configure Timer D deadtime */
-#ifdef CONFIG_STM32_HRTIM_TIMD
+#ifdef CONFIG_STM32_HRTIM_TIMD_DT
hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIMD);
#endif
/* Configure Timer E deadtime */
-#ifdef CONFIG_STM32_HRTIM_TIME
+#ifdef CONFIG_STM32_HRTIM_TIME_DT
hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIME);
#endif
@@ -3256,11 +3653,11 @@ static int hrtim_deadtime_config(FAR struct stm32_hrtim_s *priv)
* state - Enable/disable operation
*
* Returned Value:
- * 0 on success, a negated errno value on failure
+ * 0 on success, a negated errno value on failure
*
****************************************************************************/
-static int hrtim_chopper_enable(FAR struct stm32_dev_s *dev, uint8_t timer,
+static int hrtim_chopper_enable(FAR struct hrtim_dev_s *dev, uint8_t timer,
uint8_t chan, bool state)
{
FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv;
@@ -3296,13 +3693,13 @@ static int hrtim_chopper_enable(FAR struct stm32_dev_s *dev, uint8_t timer,
{
/* Set enable bit */
- hrtim_tim_modifyreg(priv, index, STM32_HRTIM_TIM_OUTR_OFFSET, 0, val);
+ hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET, 0, val);
}
else
{
/* Clear enable bit */
- hrtim_tim_modifyreg(priv, index, STM32_HRTIM_TIM_OUTR_OFFSET, val, 0);
+ hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET, val, 0);
}
errout:
@@ -3316,31 +3713,28 @@ errout:
static int hrtim_tim_chopper_cfg(FAR struct stm32_hrtim_s *priv,
uint8_t timer)
{
- FAR struct stm32_hrtim_tim_s* tim;
FAR struct stm32_hrtim_slave_priv_s* slave;
int ret = OK;
uint32_t regval = 0;
- /* Master Timer has no outputs */
+ /* Sanity checking */
- if (timer == HRTIM_TIMER_MASTER)
+ if (timer == HRTIM_TIMER_MASTER || timer == HRTIM_TIMER_COMMON)
{
ret = -EINVAL;
goto errout;
}
- /* Get Timer data strucutre */
+ /* Get Slave Timer data strucutre */
- tim = hrtim_tim_get(priv, timer);
- if (tim == NULL)
+ slave = hrtim_slave_get(priv, timer);
+ if (slave == NULL)
{
ret = -EINVAL;
goto errout;
}
- slave = (struct stm32_hrtim_slave_priv_s*)tim->priv;
-
/* Configure start pulsewidth */
regval |= slave->pwm.chp.start_pulse << HRTIM_TIMCHP_STRTPW_SHIFT;
@@ -3357,6 +3751,7 @@ static int hrtim_tim_chopper_cfg(FAR struct stm32_hrtim_s *priv,
hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CHPR_OFFSET, regval);
+errout:
return OK;
}
@@ -3597,19 +3992,22 @@ static int hrtim_burst_config(FAR struct stm32_hrtim_s *priv)
* timer - timer index
*
* Returned Value:
- * 0 on success, a negated errno value on failure
+ * 0 on success, a negated errno value on failure
*
****************************************************************************/
static int hrtim_tim_faults_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer)
{
- FAR struct stm32_hrtim_tim_s *tim;
FAR struct stm32_hrtim_slave_priv_s *slave;
uint32_t regval = 0;
+ int ret = OK;
- tim = hrtim_tim_get(priv, timer);
-
- slave = tim->priv;
+ slave = hrtim_slave_get(priv, timer);
+ if (slave == NULL)
+ {
+ ret = -EINVAL;
+ goto errout;
+ }
/* Get lock configuration */
@@ -3623,7 +4021,8 @@ static int hrtim_tim_faults_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer)
hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_FLTR_OFFSET, regval);
- return OK;
+errout:
+ return ret;
}
/****************************************************************************
@@ -3637,7 +4036,7 @@ static int hrtim_tim_faults_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer)
* index - Fault index
*
* Returned Value:
- * 0 on success, a negated errno value on failure
+ * 0 on success, a negated errno value on failure
*
****************************************************************************/
@@ -3779,7 +4178,7 @@ errout:
* priv - A reference to the HRTIM structure
*
* Returned Value:
- * 0 on success, a negated errno value on failure
+ * 0 on success, a negated errno value on failure
*
****************************************************************************/
@@ -3853,7 +4252,7 @@ static int hrtim_faults_config(FAR struct stm32_hrtim_s *priv)
* index - External Event index
*
* Returned Value:
- * 0 on success, a negated errno value on failure
+ * 0 on success, a negated errno value on failure
*
****************************************************************************/
@@ -4028,7 +4427,7 @@ errout:
* priv - A reference to the HRTIM structure
*
* Returned Value:
- * 0 on success, a negated errno value on failure
+ * 0 on success, a negated errno value on failure
*
****************************************************************************/
@@ -4088,6 +4487,30 @@ static int hrtim_events_config(FAR struct stm32_hrtim_s *priv)
}
#endif /* CONFIG_STM32_HRTIM_FAULTS */
+
+#ifdef CONFIG_STM32_HRTIM_INTERRUPTS
+
+/****************************************************************************
+ * Name: hrtim_irq_cfg
+ ****************************************************************************/
+
+static int hrtim_irq_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint16_t irq)
+{
+ int ret = OK;
+
+ if (timer == HRTIM_TIMER_COMMON)
+ {
+ hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_IER_OFFSET, irq);
+ }
+ else
+ {
+ hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_DIER_OFFSET, irq);
+ }
+
+errout:
+ return ret;
+}
+
/****************************************************************************
* Name: hrtim_irq_config
*
@@ -4098,30 +4521,100 @@ static int hrtim_events_config(FAR struct stm32_hrtim_s *priv)
* priv - A reference to the HRTIM structure
*
* Returned Value:
- * 0 on success, a negated errno value on failure
+ * 0 on success, a negated errno value on failure
*
****************************************************************************/
-#ifdef CONFIG_STM32_HRTIM_INTERRUPTS
static int hrtim_irq_config(FAR struct stm32_hrtim_s *priv)
{
-#warning "hrtim_irq_config: missing logic"
- return OK;
-}
+#ifdef CONFIG_STM32_HRTIM_MASTER_IRQ
+ hrtim_irq_cfg(priv, HRTIM_TIMER_MASTER, priv->master->tim.irq);
+#endif
-void hrtim_irq_ack(FAR struct hrtim_dev_s *dev, uint8_t timer, int source);
-{
-#warning "hrtim_irq_ack: missing logic"
-}
-#endif /* CONFIG_STM32_HRTIM_INTERRUPTS */
+#ifdef CONFIG_STM32_HRTIM_TIMA_IRQ
+ hrtim_irq_cfg(priv, HRTIM_TIMER_TIMA, priv->tima->tim.irq);
+#endif
-/****************************************************************************
+#ifdef CONFIG_STM32_HRTIM_TIMB_IRQ
+ hrtim_irq_cfg(priv, HRTIM_TIMER_TIMB, priv->timb->tim.irq);
+#endif
+
+#ifdef CONFIG_STM32_HRTIM_TIMB_IRQ
+ hrtim_irq_cfg(priv, HRTIM_TIMER_TIMB, priv->timc->tim.irq);
+#endif
+
+#ifdef CONFIG_STM32_HRTIM_TIMB_IRQ
+ hrtim_irq_cfg(priv, HRTIM_TIMER_TIMB, priv->timd->tim.irq);
+#endif
+
+#ifdef CONFIG_STM32_HRTIM_TIMB_IRQ
+ hrtim_irq_cfg(priv, HRTIM_TIMER_TIMB, priv->time->tim.irq);
+#endif
+
+#ifdef CONFIG_STM32_HRTIM_COMMON_IRQ
+ hrtim_irq_cfg(priv, HRTIM_TIMER_COMMON, priv->irq);
+#endif
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: hrtim_irq_ack
+ ****************************************************************************/
+
+static int hrtim_irq_ack(FAR struct hrtim_dev_s *dev, uint8_t timer, int source)
+{
+ FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv;
+
+ if (timer == HRTIM_TIMER_COMMON)
+ {
+ /* Write to the HRTIM common clear interrupt register */
+
+ hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ICR_OFFSET, source);
+ }
+ else
+ {
+ /* Each timer has its own ICR register */
+
+ hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_ICR_OFFSET, source);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: hrtim_irq_get
+ ****************************************************************************/
+
+static uint16_t hrtim_irq_get(FAR struct hrtim_dev_s *dev, uint8_t timer)
+{
+ FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv;
+ uint32_t regval = 0;
+
+ if (timer == HRTIM_TIMER_COMMON)
+ {
+ /* Get HRTIM common status interrupt register */
+
+ regval = hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ISR_OFFSET);
+ }
+ else
+ {
+ /* Each timer has its own ISR register */
+
+ regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ISR_OFFSET);
+ }
+
+ return (uint16_t)regval;
+}
+#endif /* CONFIG_STM32_HRTIM_INTERRUPTS */
+
+/****************************************************************************
* Name: hrtim_tim_mode_set
*
* Description:
* Set HRTIM Timer mode
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the HRTIM block
* timer - HRTIM Timer index
* mode - Timer mode configuration
@@ -4166,17 +4659,9 @@ static void hrtim_tim_mode_set(FAR struct stm32_hrtim_s *priv, uint8_t timer,
regval |= HRTIM_CMNCR_CONT;
}
- /* Configure push-pull mode. Only Slaves */
-
- if (mode & HRTIM_MODE_PSHPLL && timer != HRTIM_TIMER_MASTER)
- {
- regval |= HRTIM_TIMCR_PSHPLL;
- }
-
/* Write register */
hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, regval);
-
}
/****************************************************************************
@@ -4189,7 +4674,7 @@ static void hrtim_tim_mode_set(FAR struct stm32_hrtim_s *priv, uint8_t timer,
* priv - A reference to the HRTIM structure
*
* Returned Value:
- * None
+ * None
*
****************************************************************************/
@@ -4220,20 +4705,91 @@ static void hrtim_mode_config(FAR struct stm32_hrtim_s *priv)
#endif
}
+/****************************************************************************
+ * Name: hrtim_cmpcap_mask_get
+ *
+ * Description:
+ * This function returns not significant bits in counter/capture
+ * regsiters for given HRTIM Timer index.
+ *
+ * Input Parameters:
+ * priv - A reference to the HRTIM structure
+ * timer - HRTIM Timer index
+ *
+ * Returned Value:
+ * Not significant bits for counter/capture registers
+ *
+ ****************************************************************************/
+
+static uint8_t hrtim_cmpcap_mask_get(FAR struct stm32_hrtim_s *priv,
+ uint8_t timer)
+{
+ FAR struct stm32_hrtim_tim_s* tim;
+ uint8_t mask = 0;
+
+ /* Get Timer data strucutre */
+
+ tim = hrtim_tim_get(priv, timer);
+ if (tim == NULL)
+ {
+ mask = 0;
+ goto errout;
+ }
+
+ /* Not significant bits depens on timer prescaler */
+
+ switch(tim->tim.prescaler)
+ {
+ case HRTIM_PRESCALER_1:
+ {
+ mask = 0b11111;
+ break;
+ }
+ case HRTIM_PRESCALER_2:
+ {
+ mask = 0b1111;
+ break;
+ }
+ case HRTIM_PRESCALER_4:
+ {
+ mask = 0b111;
+ break;
+ }
+ case HRTIM_PRESCALER_8:
+ {
+ mask = 0b11;
+ break;
+ }
+ case HRTIM_PRESCALER_16:
+ {
+ mask = 0b1;
+ break;
+ }
+ default:
+ {
+ mask = 0;
+ break;
+ }
+ }
+
+errout:
+ return mask;
+}
+
/****************************************************************************
* Name: hrtim_cmp_update
*
* Description:
* Try update HRTIM Timer compare register.
*
- * Input parameters:
+ * Input Parameters:
* dev - HRTIM device structure
* timer - HRTIM Timer index
* index - Compare register timer
* cmp - New compare register value
*
* Returned Value:
- * Zero on success; a negated errno value on failure
+ * 0 on success, a negated errno value on failure
*
****************************************************************************/
@@ -4243,6 +4799,7 @@ static int hrtim_cmp_update(FAR struct hrtim_dev_s *dev, uint8_t timer,
FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv;
int ret = OK;
uint32_t offset = 0;
+ uint8_t mask = 0;
switch (index)
{
@@ -4277,6 +4834,16 @@ static int hrtim_cmp_update(FAR struct hrtim_dev_s *dev, uint8_t timer,
}
}
+ /* REVISIT: what should we do if cmp value is not significant ?
+ * At this moment we set compare register to the nearest significant value.
+ */
+
+ mask = hrtim_cmpcap_mask_get(priv, timer);
+ if (cmp <= mask)
+ {
+ cmp = mask + 1;
+ }
+
hrtim_tim_putreg(priv, timer, offset, cmp);
errout:
@@ -4289,13 +4856,13 @@ errout:
* Description:
* Try update HRTIM Timer period register.
*
- * Input parameters:
+ * Input Parameters:
* dev - HRTIM device structure
* timer - HRTIM Timer index
* per - New period register value
*
* Returned Value:
- * Zero on success; a negated errno value on failure
+ * 0 on success; a negated errno value on failure
*
****************************************************************************/
@@ -4314,12 +4881,12 @@ static int hrtim_per_update(FAR struct hrtim_dev_s *dev, uint8_t timer,
* Description:
* Get HRTIM Timer period value
*
- * Input parameters:
+ * Input Parameters:
* dev - HRTIM device structure
* timer - HRTIM Timer index
*
* Returned Value:
- * Zero on success; a negated errno value on failure
+ * Timer period value
*
****************************************************************************/
@@ -4336,13 +4903,13 @@ static uint16_t hrtim_per_get(FAR struct hrtim_dev_s *dev, uint8_t timer)
* Description:
* Get HRTIM Timer compare register
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the HRTIM block
* timer - HRTIM Timer index
* index - Compare register timer
*
* Returned Value:
- * Zero on success; a negated errno value on failure
+ * Timer compare value
*
****************************************************************************/
@@ -4392,13 +4959,134 @@ errout:
return cmpx;
}
+/****************************************************************************
+ * Name: hrtim_fclk_get
+ *
+ * Description:
+ * Get HRTIM Timer clock value
+ *
+ * Input Parameters:
+ * dev - HRTIM device structure
+ * timer - HRTIM Timer index
+ *
+ * Returned Value:
+ * Timer clock value
+ *
+ ****************************************************************************/
+
+static uint64_t hrtim_fclk_get(FAR struct hrtim_dev_s *dev, uint8_t timer)
+{
+ FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv;
+ FAR struct stm32_hrtim_tim_s *tim;
+ uint64_t fclk = 0;
+
+ /* Get Timer data structure */
+
+ tim = hrtim_tim_get(priv, timer);
+ if (tim == NULL)
+ {
+ fclk = 0;
+ goto errout;
+ }
+
+ fclk = tim->tim.fclk;
+
+errout:
+ return fclk;
+}
+
+/****************************************************************************
+ * Name: hrtim_soft_update
+ *
+ * Description:
+ * HRTIM Timer software update.
+ * This is bulk operation, so we can update many registers at the same time.
+ *
+ * Input Parameters:
+ * dev - HRTIM device structure
+ * timer - HRTIM Timer indexes
+ *
+ * Returned Value:
+ * 0 on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int hrtim_soft_update(FAR struct hrtim_dev_s *dev, uint8_t timer)
+{
+ FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv;
+ uint32_t regval = 0;
+
+ regval |= (timer & HRTIM_TIMER_MASTER ? HRTIM_CR2_MSWU : 0);
+#ifdef CONFIG_STM32_HRTIM_TIMA
+ regval |= (timer & HRTIM_TIMER_TIMA ? HRTIM_CR2_TASWU : 0);
+#endif
+#ifdef CONFIG_STM32_HRTIM_TIMB
+ regval |= (timer & HRTIM_TIMER_TIMB ? HRTIM_CR2_TBSWU : 0);
+#endif
+#ifdef CONFIG_STM32_HRTIM_TIMC
+ regval |= (timer & HRTIM_TIMER_TIMC ? HRTIM_CR2_TCSWU : 0);
+#endif
+#ifdef CONFIG_STM32_HRTIM_TIMD
+ regval |= (timer & HRTIM_TIMER_TIMD ? HRTIM_CR2_TDSWU : 0);
+#endif
+#ifdef CONFIG_STM32_HRTIM_TIME
+ regval |= (timer & HRTIM_TIMER_TIME ? HRTIM_CR2_TESWU : 0);
+#endif
+
+ /* Bits in HRTIM CR2 common register are automatically reset,
+ * so we can just write to it.
+ */
+
+ hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_CR2_OFFSET, regval);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: hrtim_tim_freq_set
+ *
+ * Description:
+ * Set HRTIM Timer frequency
+ *
+ * Returned Value:
+ * 0 on success, a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int hrtim_tim_freq_set(FAR struct hrtim_dev_s *hrtim, uint8_t timer,
+ uint64_t freq)
+{
+ uint64_t per = 0;
+ uint64_t fclk = 0;
+ int ret = OK;
+
+ /* Get Timer period value for given frequency */
+
+ fclk = HRTIM_FCLK_GET(hrtim, timer);
+ per = fclk/freq;
+ if (per > HRTIM_PER_MAX)
+ {
+ tmrerr("ERROR: can not achieve timer pwm freq=%u if fclk=%llu\n",
+ (uint32_t)freq, (uint64_t)fclk);
+ ret = -EINVAL;
+ goto errout;
+ }
+
+ /* Set Timer period value */
+
+ HRTIM_PER_SET(hrtim, timer, (uint16_t)per);
+
+ errout:
+ return ret;
+}
+
/****************************************************************************
* Name: hrtim_tim_reset_set
*
* Description:
* Set HRTIM Timer Reset events
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the HRTIM block
* timer - HRTIM Timer index
* reset - Reset configuration
@@ -4409,17 +5097,135 @@ errout:
****************************************************************************/
static int hrtim_tim_reset_set(FAR struct stm32_hrtim_s *priv, uint8_t timer,
- uint32_t reset)
+ uint64_t reset)
{
int ret = OK;
+ uint32_t regval = 0;
- if (timer == HRTIM_TIMER_MASTER)
+ /* Sanity checking */
+
+ if (timer == HRTIM_TIMER_MASTER || timer == HRTIM_TIMER_COMMON)
{
ret = -EINVAL;
goto errout;
}
- hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RSTR_OFFSET, reset);
+ /* First 18 bits can be written directly */
+
+ regval |= (reset & 0x3FFFF);
+
+ /* TimerX reset events differ for individual timers */
+
+ switch(timer)
+ {
+#ifdef CONFIG_STM32_HRTIM_TIMA
+ case HRTIM_TIMER_TIMA:
+ {
+ regval |= ((reset & HRTIM_RST_TBCMP1) ? HRTIM_TIMARST_TIMBCMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TBCMP2) ? HRTIM_TIMARST_TIMBCMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TBCMP4) ? HRTIM_TIMARST_TIMBCMP4 : 0);
+ regval |= ((reset & HRTIM_RST_TCCMP1) ? HRTIM_TIMARST_TIMCCMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TCCMP2) ? HRTIM_TIMARST_TIMCCMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TCCMP4) ? HRTIM_TIMARST_TIMCCMP4 : 0);
+ regval |= ((reset & HRTIM_RST_TDCMP1) ? HRTIM_TIMARST_TIMDCMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TDCMP2) ? HRTIM_TIMARST_TIMDCMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TDCMP4) ? HRTIM_TIMARST_TIMDCMP4 : 0);
+ regval |= ((reset & HRTIM_RST_TECMP1) ? HRTIM_TIMARST_TIMECMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TECMP2) ? HRTIM_TIMARST_TIMECMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TECMP4) ? HRTIM_TIMARST_TIMECMP4 : 0);
+
+ break;
+ }
+#endif
+
+#ifdef CONFIG_STM32_HRTIM_TIMB
+ case HRTIM_TIMER_TIMB:
+ {
+ regval |= ((reset & HRTIM_RST_TACMP1) ? HRTIM_TIMBRST_TIMACMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TACMP2) ? HRTIM_TIMBRST_TIMACMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TACMP4) ? HRTIM_TIMBRST_TIMACMP4 : 0);
+ regval |= ((reset & HRTIM_RST_TCCMP1) ? HRTIM_TIMBRST_TIMCCMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TCCMP2) ? HRTIM_TIMBRST_TIMCCMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TCCMP4) ? HRTIM_TIMBRST_TIMCCMP4 : 0);
+ regval |= ((reset & HRTIM_RST_TDCMP1) ? HRTIM_TIMBRST_TIMDCMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TDCMP2) ? HRTIM_TIMBRST_TIMDCMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TDCMP4) ? HRTIM_TIMBRST_TIMDCMP4 : 0);
+ regval |= ((reset & HRTIM_RST_TECMP1) ? HRTIM_TIMBRST_TIMECMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TECMP2) ? HRTIM_TIMBRST_TIMECMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TECMP4) ? HRTIM_TIMBRST_TIMECMP4 : 0);
+
+ break;
+ }
+#endif
+
+#ifdef CONFIG_STM32_HRTIM_TIMC
+ case HRTIM_TIMER_TIMC:
+ {
+ regval |= ((reset & HRTIM_RST_TACMP1) ? HRTIM_TIMCRST_TIMACMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TACMP2) ? HRTIM_TIMCRST_TIMACMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TACMP4) ? HRTIM_TIMCRST_TIMACMP4 : 0);
+ regval |= ((reset & HRTIM_RST_TBCMP1) ? HRTIM_TIMCRST_TIMBCMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TBCMP2) ? HRTIM_TIMCRST_TIMBCMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TBCMP4) ? HRTIM_TIMCRST_TIMBCMP4 : 0);
+ regval |= ((reset & HRTIM_RST_TDCMP1) ? HRTIM_TIMCRST_TIMDCMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TDCMP2) ? HRTIM_TIMCRST_TIMDCMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TDCMP4) ? HRTIM_TIMCRST_TIMDCMP4 : 0);
+ regval |= ((reset & HRTIM_RST_TECMP1) ? HRTIM_TIMCRST_TIMECMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TECMP2) ? HRTIM_TIMCRST_TIMECMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TECMP4) ? HRTIM_TIMCRST_TIMECMP4 : 0);
+
+ break;
+ }
+#endif
+
+#ifdef CONFIG_STM32_HRTIM_TIMD
+ case HRTIM_TIMER_TIMD:
+ {
+ regval |= ((reset & HRTIM_RST_TACMP1) ? HRTIM_TIMDRST_TIMACMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TACMP2) ? HRTIM_TIMDRST_TIMACMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TACMP4) ? HRTIM_TIMDRST_TIMACMP4 : 0);
+ regval |= ((reset & HRTIM_RST_TBCMP1) ? HRTIM_TIMDRST_TIMBCMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TBCMP2) ? HRTIM_TIMDRST_TIMBCMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TBCMP4) ? HRTIM_TIMDRST_TIMBCMP4 : 0);
+ regval |= ((reset & HRTIM_RST_TCCMP1) ? HRTIM_TIMDRST_TIMCCMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TCCMP2) ? HRTIM_TIMDRST_TIMCCMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TCCMP4) ? HRTIM_TIMDRST_TIMCCMP4 : 0);
+ regval |= ((reset & HRTIM_RST_TECMP1) ? HRTIM_TIMDRST_TIMECMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TECMP2) ? HRTIM_TIMDRST_TIMECMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TECMP4) ? HRTIM_TIMDRST_TIMECMP4 : 0);
+
+ break;
+ }
+#endif
+
+#ifdef CONFIG_STM32_HRTIM_TIME
+ case HRTIM_TIMER_TIME:
+ {
+ regval |= ((reset & HRTIM_RST_TACMP1) ? HRTIM_TIMERST_TIMACMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TACMP2) ? HRTIM_TIMERST_TIMACMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TACMP4) ? HRTIM_TIMERST_TIMACMP4 : 0);
+ regval |= ((reset & HRTIM_RST_TBCMP1) ? HRTIM_TIMERST_TIMBCMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TBCMP2) ? HRTIM_TIMERST_TIMBCMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TBCMP4) ? HRTIM_TIMERST_TIMBCMP4 : 0);
+ regval |= ((reset & HRTIM_RST_TCCMP1) ? HRTIM_TIMERST_TIMCCMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TCCMP2) ? HRTIM_TIMERST_TIMCCMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TCCMP4) ? HRTIM_TIMERST_TIMCCMP4 : 0);
+ regval |= ((reset & HRTIM_RST_TDCMP1) ? HRTIM_TIMERST_TIMDCMP1 : 0);
+ regval |= ((reset & HRTIM_RST_TDCMP2) ? HRTIM_TIMERST_TIMDCMP2 : 0);
+ regval |= ((reset & HRTIM_RST_TDCMP4) ? HRTIM_TIMERST_TIMDCMP4 : 0);
+
+ break;
+ }
+#endif
+
+ default:
+ {
+ ret = -EINVAL;
+ goto errout;
+ }
+ }
+
+ hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RSTR_OFFSET, regval);
errout:
return ret;
@@ -4458,13 +5264,37 @@ static int hrtim_reset_config(FAR struct stm32_hrtim_s *priv)
}
static int hrtim_tim_update_set(FAR struct stm32_hrtim_s *priv, uint8_t timer,
- uint32_t update)
+ uint16_t update)
{
uint32_t regval = 0;
regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET);
- /* TODO: Configure update events */
+ /* Configure update events */
+
+ regval |= (update & HRTIM_UPDATE_MSTU ? HRTIM_TIMCR_MSTU : 0);
+ regval |= (update & HRTIM_UPDATE_RSTU ? HRTIM_TIMCR_RSTU : 0);
+ regval |= (update & HRTIM_UPDATE_REPU ? HRTIM_TIMCR_REPU : 0);
+
+#ifdef CONFIG_STM32_HRTIM_TIMA
+ regval |= (update & HRTIM_UPDATE_TAU ? HRTIM_TIMCR_TAU : 0);
+#endif
+
+#ifdef CONFIG_STM32_HRTIM_TIMB
+ regval |= (update & HRTIM_UPDATE_TBU ? HRTIM_TIMCR_TBU : 0);
+#endif
+
+#ifdef CONFIG_STM32_HRTIM_TIMC
+ regval |= (update & HRTIM_UPDATE_TCU ? HRTIM_TIMCR_TCU : 0);
+#endif
+
+#ifdef CONFIG_STM32_HRTIM_TIMD
+ regval |= (update & HRTIM_UPDATE_TDU ? HRTIM_TIMCR_TDU : 0);
+#endif
+
+#ifdef CONFIG_STM32_HRTIM_TIME
+ regval |= (update & HRTIM_UPDATE_TEU ? HRTIM_TIMCR_TEU : 0);
+#endif
/* TODO: Configure update gating */
@@ -4517,7 +5347,7 @@ static int hrtim_update_config(FAR struct stm32_hrtim_s *priv)
* priv - A reference to the HRTIM structure
*
* Returned Value:
- * 0 on success, a negated errno value on failure
+ * 0 on success, a negated errno value on failure
*
****************************************************************************/
@@ -4595,6 +5425,17 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv)
}
#endif
+ /* Configure HRTIM outputs deadtime */
+
+#if defined(CONFIG_STM32_HRTIM_DEADTIME)
+ ret = hrtim_deadtime_config(priv);
+ if (ret != OK)
+ {
+ tmrerr("ERROR: HRTIM deadtime configuration failed!\n");
+ goto errout;
+ }
+#endif
+
/* Configure HRTIM outputs GPIOs */
#if defined(CONFIG_STM32_HRTIM_PWM)
@@ -4652,7 +5493,7 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv)
/* Configure interrupts */
-#ifdef CONFIG_STM32_HRTIM_INTERRUTPS
+#ifdef CONFIG_STM32_HRTIM_INTERRUPTS
ret = hrtim_irq_config(priv);
if (ret != OK)
{
@@ -4794,7 +5635,6 @@ FAR struct hrtim_dev_s* stm32_hrtiminitialize(void)
if (ret < 0)
{
tmrerr("ERROR: Failed to initialize HRTIM1: %d\n", ret);
- errno = -ret;
return NULL;
}
diff --git a/arch/arm/src/stm32/stm32_hrtim.h b/arch/arm/src/stm32/stm32_hrtim.h
index 1085951fb9049690e94bcf7a7d8e66cb3aebe442..323488ae3023cae204ae7a8eb65381f179ad6994 100644
--- a/arch/arm/src/stm32/stm32_hrtim.h
+++ b/arch/arm/src/stm32/stm32_hrtim.h
@@ -187,7 +187,7 @@
# error "APB2 prescaler factor can not be greater than 2"
# else
# define HRTIM_HAVE_CLK_FROM_PLL 1
-# define HRTIM_CLOCK 2*STM32_PLL_FREQUENCY
+# define HRTIM_MAIN_CLOCK 2*STM32_PLL_FREQUENCY
# endif
# else
# error "Clock system must be set to PLL"
@@ -195,23 +195,41 @@
#else
# error "Not supported yet: system freezes when no PLL selected."
# define HRTIM_HAVE_CLK_FROM_APB2 1
-# if STM32_RCC_CFGR_PPRE2 == RCC_CFGR_PPRE2_HCLK
-# define HRTIM_CLOCK STM32_PCLK2_FREQUENCY
+# if STM32_RCC_CFGR_PPRE2 == RCC_CFGR_PPRE2_HCLK
+# define HRTIM_MAIN_CLOCK STM32_PCLK2_FREQUENCY
# else
-# define HRTIM_CLOCK 2*STM32_PCLK2_FREQUENCY
+# define HRTIM_MAIN_CLOCK 2*STM32_PCLK2_FREQUENCY
# endif
#endif
+/* High-resolution equivalent clock */
+
+#define HRTIM_CLOCK (HRTIM_MAIN_CLOCK*32ull)
+
/* Helpers **************************************************************************/
#define HRTIM_CMP_SET(hrtim, tim, index, cmp) \
(hrtim)->hd_ops->cmp_update(hrtim, tim, index, cmp)
#define HRTIM_PER_SET(hrtim, tim, per) \
(hrtim)->hd_ops->per_update(hrtim, tim, per)
-#define HRTIM_OUTPUTS_ENABLE(hrtim, tim, state) \
- (hrtim)->hd_ops->outputs_enable(hrtim, tim, state)
-#define HRTIM_OUTPUTS_ENABLE(hrtim, tim, state) \
- (hrtim)->hd_ops->outputs_enable(hrtim, tim, state)
+#define HRTIM_PER_GET(hrtim, tim) \
+ (hrtim)->hd_ops->per_get(hrtim, tim)
+#define HRTIM_FCLK_GET(hrtim, tim) \
+ (hrtim)->hd_ops->fclk_get(hrtim, tim)
+#define HRTIM_IRQ_GET(hrtim, irq) \
+ (hrtim)->hd_ops->irq_get(hrtim, irq)
+#define HRTIM_IRQ_ACK(hrtim, irq, ack) \
+ (hrtim)->hd_ops->irq_ack(hrtim, irq, ack)
+#define HRTIM_SOFT_UPDATE(hrtim, timer) \
+ (hrtim)->hd_ops->soft_update(hrtim, timer)
+#define HRTIM_FREQ_SET(hrtim, timer,freq) \
+ (hrtim)->hd_ops->freq_set(hrtim, timer, freq)
+#define HRTIM_OUTPUTS_ENABLE(hrtim, outputs, state) \
+ (hrtim)->hd_ops->outputs_enable(hrtim, outputs, state)
+#define HRTIM_OUTPUT_SET_SET(hrtim, output, set) \
+ (hrtim)->hd_ops->output_set_set(hrtim, output, set)
+#define HRTIM_OUTPUT_RST_SET(hrtim, output, rst) \
+ (hrtim)->hd_ops->output_rst_set(hrtim, output, rst)
#define HRTIM_BURST_CMP_SET(hrtim, cmp) \
(hrtim)->hd_ops->burst_cmp_set(hrtim, cmp)
#define HRTIM_BURST_PER_SET(hrtim, per) \
@@ -220,6 +238,13 @@
(hrtim)->hd_ops->burst_pre_set(hrtim, pre)
#define HRTIM_BURST_ENABLE(hrtim, state) \
(hrtim)->hd_ops->burst_enable(hrtim, state)
+#define HRTIM_DEADTIME_UPDATE(hrtim, tim, dt, val) \
+ (hrtim)->hd_ops->deadtime_update(hrtim, tim, dt, val)
+
+#define HRTIM_PER_MAX 0xFFFF
+#define HRTIM_CMP_MAX 0xFFFF
+#define HRTIM_CPT_MAX 0xFFFF
+#define HRTIM_REP_MAX 0xFF
/************************************************************************************
* Public Types
@@ -229,23 +254,23 @@
enum stm32_hrtim_tim_e
{
- HRTIM_TIMER_MASTER = 0,
+ HRTIM_TIMER_MASTER = (1<<0),
#ifdef CONFIG_STM32_HRTIM_TIMA
- HRTIM_TIMER_TIMA = 1,
+ HRTIM_TIMER_TIMA = (1<<1),
#endif
#ifdef CONFIG_STM32_HRTIM_TIMB
- HRTIM_TIMER_TIMB = 2,
+ HRTIM_TIMER_TIMB = (1<<2),
#endif
#ifdef CONFIG_STM32_HRTIM_TIMC
- HRTIM_TIMER_TIMC = 3,
+ HRTIM_TIMER_TIMC = (1<<3),
#endif
#ifdef CONFIG_STM32_HRTIM_TIMD
- HRTIM_TIMER_TIMD = 4,
+ HRTIM_TIMER_TIMD = (1<<4),
#endif
#ifdef CONFIG_STM32_HRTIM_TIME
- HRTIM_TIMER_TIME = 5,
+ HRTIM_TIMER_TIME = (1<<5),
#endif
- HRTIM_TIMER_COMMON = 6
+ HRTIM_TIMER_COMMON = (1<<6)
};
/* Source which can force the Tx1/Tx2 output to its inactive state */
@@ -332,62 +357,62 @@ enum stm32_hrtim_tim_rst_e
{
/* Timer owns events */
- HRTIM_RST_UPDT,
- HRTIM_RST_CMP4,
- HRTIM_RST_CMP2,
+ HRTIM_RST_UPDT = (1<<1),
+ HRTIM_RST_CMP4 = (1<<2),
+ HRTIM_RST_CMP2 = (1<<3),
/* Master Timer Events */
- HRTIM_RST_MSTCMP4,
- HRTIM_RST_MSTCMP3,
- HRTIM_RST_MSTCMP2,
- HRTIM_RST_MSTCMP1,
- HRTIM_RST_MSTPER,
+ HRTIM_RST_MSTPER = (1<<4),
+ HRTIM_RST_MSTCMP1 = (1<<5),
+ HRTIM_RST_MSTCMP2 = (1<<6),
+ HRTIM_RST_MSTCMP3 = (1<<7),
+ HRTIM_RST_MSTCMP4 = (1<<8),
- /* TimerX events */
+ /* External Events */
- HRTIM_RST_TECMP4,
- HRTIM_RST_TECMP2,
- HRTIM_RST_TECMP1,
- HRTIM_RST_TDCMP4,
- HRTIM_RST_TDCMP2,
- HRTIM_RST_TDCMP1,
- HRTIM_RST_TCCMP4,
- HRTIM_RST_TCCMP2,
- HRTIM_RST_TCCMP1,
- HRTIM_RST_TBCMP4,
- HRTIM_RST_TBCMP2,
- HRTIM_RST_TBCMP1,
- HRTIM_RST_TACMP4,
- HRTIM_RST_TACMP2,
- HRTIM_RST_TACMP1,
+ HRTIM_RST_EXTEVNT1 = (1<<9),
+ HRTIM_RST_EXTEVNT2 = (1<<10),
+ HRTIM_RST_EXTEVNT3 = (1<<11),
+ HRTIM_RST_EXTEVNT4 = (1<<12),
+ HRTIM_RST_EXTEVNT5 = (1<<13),
+ HRTIM_RST_EXTEVNT6 = (1<<14),
+ HRTIM_RST_EXTEVNT7 = (1<<15),
+ HRTIM_RST_EXTEVNT8 = (1<<16),
+ HRTIM_RST_EXTEVNT9 = (1<<17),
+ HRTIM_RST_EXTEVNT10 = (1<<18),
- /* External Events */
+ /* TimerX events */
- HRTIM_RST_EXTEVNT10,
- HRTIM_RST_EXTEVNT9,
- HRTIM_RST_EXTEVNT8,
- HRTIM_RST_EXTEVNT7,
- HRTIM_RST_EXTEVNT6,
- HRTIM_RST_EXTEVNT5,
- HRTIM_RST_EXTEVNT4,
- HRTIM_RST_EXTEVNT3,
- HRTIM_RST_EXTEVNT2,
- HRTIM_RST_EXTEVNT1
+ HRTIM_RST_TACMP1 = (1<<19),
+ HRTIM_RST_TACMP2 = (1<<20),
+ HRTIM_RST_TACMP4 = (1<<21),
+ HRTIM_RST_TBCMP1 = (1<<22),
+ HRTIM_RST_TBCMP2 = (1<<23),
+ HRTIM_RST_TBCMP4 = (1<<24),
+ HRTIM_RST_TCCMP1 = (1<<25),
+ HRTIM_RST_TCCMP2 = (1<<26),
+ HRTIM_RST_TCCMP4 = (1<<27),
+ HRTIM_RST_TDCMP1 = (1<<28),
+ HRTIM_RST_TDCMP2 = (1<<29),
+ HRTIM_RST_TDCMP4 = (1<<30),
+ HRTIM_RST_TECMP1 = (1<<31),
+ HRTIM_RST_TECMP2 = (1<<32),
+ HRTIM_RST_TECMP4 = (1<<33),
};
/* HRTIM Timer X prescaler */
enum stm32_hrtim_tim_prescaler_e
{
- HRTIM_PRESCALER_1,
- HRTIM_PRESCALER_2,
- HRTIM_PRESCALER_4,
- HRTIM_PRESCALER_8,
- HRTIM_PRESCALER_16,
- HRTIM_PRESCALER_32,
- HRTIM_PRESCALER_64,
- HRTIM_PRESCALER_128
+ HRTIM_PRESCALER_1, /* CKPSC = 0 */
+ HRTIM_PRESCALER_2, /* CKPSC = 1 */
+ HRTIM_PRESCALER_4, /* CKPSC = 2 */
+ HRTIM_PRESCALER_8, /* CKPSC = 3 */
+ HRTIM_PRESCALER_16, /* CKPSC = 4 */
+ HRTIM_PRESCALER_32, /* CKPSC = 5 */
+ HRTIM_PRESCALER_64, /* CKPSC = 6 */
+ HRTIM_PRESCALER_128 /* CKPSC = 7 */
};
/* HRTIM Timer Master/Slave mode */
@@ -398,10 +423,6 @@ enum stm32_hrtim_mode_e
HRTIM_MODE_HALF = (1 << 1), /* Half mode */
HRTIM_MODE_RETRIG = (1 << 2), /* Re-triggerable mode */
HRTIM_MODE_CONT = (1 << 3), /* Continuous mode */
-
- /* Only slave Timers */
-
- HRTIM_MODE_PSHPLL = (1 << 7), /* Push-Pull mode */
};
/* HRTIM Slave Timer auto-delayed mode
@@ -571,7 +592,7 @@ enum stm32_outputs_e
enum stm32_hrtim_deadtime_sign_e
{
HRTIM_DT_SIGN_POSITIVE = 0,
- HRTIM_DT_DIGN_NEGATIVE = 1
+ HRTIM_DT_SIGN_NEGATIVE = 1
};
/* HRTIM Deadtime types */
@@ -759,6 +780,21 @@ enum stm32_hrtim_dac_e
HRTIM_DAC_TRIG3 = 3
};
+/* HRTIM Timer update events */
+
+enum stm32_tim_update_e
+{
+ HRTIM_UPDATE_NONE = 0,
+ HRTIM_UPDATE_MSTU = (1 << 0),
+ HRTIM_UPDATE_TAU = (1 << 2),
+ HRTIM_UPDATE_TBU = (1 << 3),
+ HRTIM_UPDATE_TCU = (1 << 4),
+ HRTIM_UPDATE_TDU = (1 << 5),
+ HRTIM_UPDATE_TEU = (1 << 6),
+ HRTIM_UPDATE_RSTU = (1 << 7),
+ HRTIM_UPDATE_REPU = (1 << 8),
+};
+
/* HRTIM Master Timer interrupts */
enum stm32_irq_master_e
@@ -967,12 +1003,22 @@ struct stm32_hrtim_ops_s
uint16_t (*per_get)(FAR struct hrtim_dev_s *dev, uint8_t timer);
uint16_t (*cmp_get)(FAR struct hrtim_dev_s *dev, uint8_t timer,
uint8_t index);
+ uint64_t (*fclk_get)(FAR struct hrtim_dev_s *dev, uint8_t timer);
+ int (*soft_update)(FAR struct hrtim_dev_s *dev, uint8_t timer);
+ int (*freq_set)(FAR struct hrtim_dev_s *hrtim, uint8_t timer,
+ uint64_t freq);
+
#ifdef CONFIG_STM32_HRTIM_INTERRUPTS
- void (*irq_ack)(FAR struct hrtim_dev_s *dev, uint8_t timer, int source);
+ int (*irq_ack)(FAR struct hrtim_dev_s *dev, uint8_t timer, int source);
+ uint16_t (*irq_get)(FAR struct hrtim_dev_s *dev, uint8_t timer);
#endif
#ifdef CONFIG_STM32_HRTIM_PWM
int (*outputs_enable)(FAR struct hrtim_dev_s *dev, uint16_t outputs,
bool state);
+ int (*output_set_set)(FAR struct hrtim_dev_s *dev, uint16_t output,
+ uint32_t set);
+ int (*output_rst_set)(FAR struct hrtim_dev_s *dev, uint16_t output,
+ uint32_t rst);
#endif
#ifdef CONFIG_STM32_HRTIM_BURST
int (*burst_enable)(FAR struct hrtim_dev_s *dev, bool state);
@@ -988,8 +1034,10 @@ struct stm32_hrtim_ops_s
uint8_t chan, bool state);
#endif
#ifdef CONFIG_STM32_HRTIM_DEADTIME
- int (*deadtime_update)(FAR struct hrtim_dev_s *dev, uint8_t dt, uint16_t value);
- uint16_t (*deadtime_get)(FAR struct hrtim_dev_s *dev, uint8_t dt);
+ int (*deadtime_update)(FAR struct hrtim_dev_s *dev, uint8_t timer,
+ uint8_t dt, uint16_t value);
+ uint16_t (*deadtime_get)(FAR struct hrtim_dev_s *dev, uint8_t timer,
+ uint8_t dt);
#endif
#ifdef CONFIG_STM32_HRTIM_CAPTURE
uint16_t (*capture_get)(FAR struct hrtim_dev_s *dev, uint8_t timer,
diff --git a/arch/arm/src/stm32/stm32_i2c.h b/arch/arm/src/stm32/stm32_i2c.h
index f36ee952f55178cff12bc2a13fb95a6fb85a5182..c61f17332bda21440dcc8332569b40711d874124 100644
--- a/arch/arm/src/stm32/stm32_i2c.h
+++ b/arch/arm/src/stm32/stm32_i2c.h
@@ -79,7 +79,7 @@
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
@@ -95,7 +95,7 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port);
* Description:
* De-initialize the selected I2C port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the stm32_i2cbus_initialize()
*
* Returned Value:
diff --git a/arch/arm/src/stm32/stm32_i2s.c b/arch/arm/src/stm32/stm32_i2s.c
index 46ac8f6eec3c7b0821baa4701a484193953be931..f68eb8683da8249c0a19f6dce4153fdd913f0fb0 100644
--- a/arch/arm/src/stm32/stm32_i2s.c
+++ b/arch/arm/src/stm32/stm32_i2s.c
@@ -2160,7 +2160,7 @@ errout_with_exclsem:
* Setup the MCK divider based on the currently selected data width and
* the sample rate
*
- * Input Parameter:
+ * Input Parameters:
* priv - I2C device structure (only the sample rate and data length is
* needed at this point).
*
@@ -2562,7 +2562,7 @@ static void i2s3_configure(struct stm32_i2s_s *priv)
* Description:
* Initialize the selected i2S port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple I2S interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/stm32/stm32_i2s.h b/arch/arm/src/stm32/stm32_i2s.h
index 5e6d51b817f27a51b50c628663b149d6d56cb420..fc7a702b7e5f0424adc99149c6cb98a7ea4ba453 100644
--- a/arch/arm/src/stm32/stm32_i2s.h
+++ b/arch/arm/src/stm32/stm32_i2s.h
@@ -71,7 +71,7 @@ extern "C"
* Description:
* Initialize the selected I2S port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple I2S interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/stm32/stm32_irq.c
index 98adf74f36c234c450c0566af39ff950e5eee81b..402351aafa264b10bd62efa25408c43b8eebd890 100644
--- a/arch/arm/src/stm32/stm32_irq.c
+++ b/arch/arm/src/stm32/stm32_irq.c
@@ -387,7 +387,7 @@ void up_irqinitialize(void)
up_enable_irq(STM32_IRQ_MEMFAULT);
#endif
-#ifdef CONFIG_RTC
+#if defined(CONFIG_RTC) && !defined(CONFIG_RTC_EXTERNAL)
/* RTC was initialized earlier but IRQs weren't ready at that time */
stm32_rtc_irqinitialize();
diff --git a/arch/arm/src/stm32/stm32_iwdg.c b/arch/arm/src/stm32/stm32_iwdg.c
index d26ec9f71a375f6c211c1e6c0a87f1c50b15b1e1..2ceaf9bd4bbf2327b59e95022a64016e510fbb32 100644
--- a/arch/arm/src/stm32/stm32_iwdg.c
+++ b/arch/arm/src/stm32/stm32_iwdg.c
@@ -315,7 +315,7 @@ static inline void stm32_setprescaler(FAR struct stm32_lowerhalf_s *priv)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -371,7 +371,7 @@ static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -396,7 +396,7 @@ static int stm32_stop(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -429,7 +429,7 @@ static int stm32_keepalive(FAR struct watchdog_lowerhalf_s *lower)
* driver state structure.
* status - The location to return the watchdog status information.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -488,7 +488,7 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
* driver state structure.
* timeout - The new timeout value in milliseconds.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -639,7 +639,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* /dev/watchdog0
* lsifreq - The calibrated LSI clock frequency
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/stm32/stm32_ltdc.c b/arch/arm/src/stm32/stm32_ltdc.c
index 5b794d17dd4ac2b2773c8886d5414705f0e7f454..9c798d1ab5c5ad7bddf8602763a1ec57f8138988 100644
--- a/arch/arm/src/stm32/stm32_ltdc.c
+++ b/arch/arm/src/stm32/stm32_ltdc.c
@@ -1162,7 +1162,7 @@ static int stm32_ltdcirq(int irq, void *context, FAR void *arg)
* that a register reload was been completed.
* Note! The caller must use this function within a critical section.
*
- * Return:
+ * Returned Value:
* OK - On success otherwise ERROR
*
****************************************************************************/
@@ -1457,7 +1457,7 @@ static inline uint8_t stm32_ltdc_lgetopac(FAR struct stm32_layer_s *layer)
* Parameter:
* layer - Reference to the layer control structure
*
- * Return:
+ * Returned Value:
* true - layer valid
* false - layer invalid
*
@@ -1487,7 +1487,7 @@ static inline bool stm32_ltdc_lvalidate(FAR const struct stm32_layer_s *layer)
* srcxpos - Top left x position from where data visible in the active area
* srcypos - Top left y position from where data visible in the active area
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1949,7 +1949,7 @@ static void stm32_ltdc_lenable(FAR struct stm32_layer_s *layer)
}
/****************************************************************************
- * Name stm32_ltdc_lclear
+ * Name: stm32_ltdc_lclear
*
* Description:
* Clear the whole layer
@@ -1958,7 +1958,7 @@ static void stm32_ltdc_lenable(FAR struct stm32_layer_s *layer)
* layer - Reference to the layer control structure
* color - The color to clear
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid
*
@@ -2172,7 +2172,7 @@ static void stm32_ltdc_linit(int lid)
* vtable - The framebuffer driver object
* vinfo - the videoinfo object
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2207,7 +2207,7 @@ static int stm32_getvideoinfo(struct fb_vtable_s *vtable,
* vtable - The framebuffer driver object
* pinfo - the planeinfo object
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2242,7 +2242,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno,
* vtable - The framebuffer driver object
* cmap - the color table
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2269,7 +2269,7 @@ static int stm32_getcmap(struct fb_vtable_s *vtable,
* vtable - The framebuffer driver object
* cmap - the color table
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2296,7 +2296,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable,
* layer - Reference to the layer control structure
* vinfo - Reference to the video info structure
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2330,7 +2330,7 @@ static int stm32_lgetvideoinfo(struct ltdc_layer_s *layer,
* planeno - Number of the plane
* pinfo - Reference to the plane info structure
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2364,7 +2364,7 @@ static int stm32_lgetplaneinfo(struct ltdc_layer_s *layer, int planeno,
* layer - Reference to the layer structure
* cmap - color lookup table with up the 256 entries
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2424,7 +2424,7 @@ static int stm32_setclut(struct ltdc_layer_s *layer,
* cmap - Reference to valid color lookup table accept up the 256 color
* entries
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2523,7 +2523,7 @@ static int stm32_getclut(struct ltdc_layer_s *layer,
* e.g. get the current active or inactive layer.
* See LTDC_LAYER_* for possible values
*
- * Return:
+ * Returned Value:
* OK - On success
* Null if invalid flag
*
@@ -2600,7 +2600,7 @@ static int stm32_getlid(FAR struct ltdc_layer_s *layer, int *lid,
* layer - Reference to the layer structure
* argb - ARGB8888 color value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2636,7 +2636,7 @@ static int stm32_setcolor(FAR struct ltdc_layer_s *layer, uint32_t argb)
* layer - Reference to the layer structure
* argb - Reference to store the ARGB8888 color value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2673,7 +2673,7 @@ static int stm32_getcolor(FAR struct ltdc_layer_s *layer, uint32_t *argb)
* layer - Reference to the layer structure
* rgb - RGB888 color value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2709,7 +2709,7 @@ static int stm32_setcolorkey(FAR struct ltdc_layer_s *layer, uint32_t rgb)
* layer - Reference to the layer structure
* rgb - Reference to store the RGB888 color key
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2750,7 +2750,7 @@ static int stm32_getcolorkey(FAR struct ltdc_layer_s *layer, uint32_t *rgb)
* layer - Reference to the layer structure
* alpha - Alpha value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2786,7 +2786,7 @@ static int stm32_setalpha(FAR struct ltdc_layer_s *layer, uint8_t alpha)
* layer - Reference to the layer structure
* alpha - Reference to store the alpha value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2823,7 +2823,7 @@ static int stm32_getalpha(FAR struct ltdc_layer_s *layer, uint8_t *alpha)
* layer - Reference to the layer structure
* mode - Blend mode (see LTDC_BLEND_*)
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2955,7 +2955,7 @@ static int stm32_setblendmode(FAR struct ltdc_layer_s *layer, uint32_t mode)
* layer - Reference to the layer structure
* mode - Reference to store the blend mode
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
****************************************************************************/
@@ -2994,7 +2994,7 @@ static int stm32_getblendmode(FAR struct ltdc_layer_s *layer, uint32_t *mode)
* srcxpos - x position of the visible pixel of the whole layer
* srcypos - y position of the visible pixel of the whole layer
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -3056,7 +3056,7 @@ static int stm32_setarea(FAR struct ltdc_layer_s *layer,
* srcxpos - Reference to store the referenced x position of the whole layer
* srcypos - Reference to store the reterenced y position of the whole layer
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -3096,7 +3096,7 @@ static int stm32_getarea(FAR struct ltdc_layer_s *layer,
* layer - Reference to the layer structure
* mode - operation mode
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid
* -ECANCELED - Operation cancelled, something goes wrong
@@ -3259,7 +3259,7 @@ static int stm32_update(FAR struct ltdc_layer_s *layer, uint32_t mode)
* src - Reference to the source layer
* srcarea - Reference to the selected area of the source layer
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* source area outside the visible area of the destination layer.
@@ -3310,7 +3310,7 @@ static int stm32_blit(FAR struct ltdc_layer_s *dest,
* back - Reference to the background layer
* backarea - Reference to the selected area of the background layer
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* source area outside the visible area of the destination layer.
@@ -3360,7 +3360,7 @@ static int stm32_blend(FAR struct ltdc_layer_s *dest,
* color - Color to fill the selected area. Color must be formatted
* according to the layer pixel format.
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* area outside the visible area of the layer.
@@ -3402,7 +3402,7 @@ static int stm32_fillarea(FAR struct ltdc_layer_s *layer,
* Parameter:
* lid - Layer identifier
*
- * Return:
+ * Returned Value:
* Reference to the layer control structure on success or Null if lid
* is invalid.
*
@@ -3428,7 +3428,7 @@ FAR struct ltdc_layer_s *stm32_ltdcgetlayer(int lid)
* Description:
* Initialize the ltdc controller
*
- * Return:
+ * Returned Value:
* OK
*
****************************************************************************/
@@ -3517,10 +3517,10 @@ int stm32_ltdcinitialize(void)
* Return a a reference to the framebuffer object for the specified video
* plane.
*
- * Input parameters:
+ * Input Parameters:
* None
*
- * Returned value:
+ * Returned Value:
* Reference to the framebuffer object (NULL on failure)
*
****************************************************************************/
diff --git a/arch/arm/src/stm32/stm32_ltdc.h b/arch/arm/src/stm32/stm32_ltdc.h
index 33ebc3e5580e995df514c57c0381701d9205d9c4..7c73de31fe482d396f68b2081280eb74411888af 100644
--- a/arch/arm/src/stm32/stm32_ltdc.h
+++ b/arch/arm/src/stm32/stm32_ltdc.h
@@ -133,7 +133,7 @@ struct ltdc_layer_s
* layer - Reference to the layer control structure
* vinfo - Reference to the video info structure
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -151,7 +151,7 @@ struct ltdc_layer_s
* planeno - Number of the plane
* pinfo - Reference to the plane info structure
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -171,7 +171,7 @@ struct ltdc_layer_s
* e.g. get the current active or inactive layer.
* See LTDC_LAYER_* for possible values
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -192,7 +192,7 @@ struct ltdc_layer_s
* enable - Enable or disable clut support (if false cmap is ignored and can
* be NULL)
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -210,7 +210,7 @@ struct ltdc_layer_s
* cmap - Reference to valid color lookup table accept up the 256 color
* entries
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -229,7 +229,7 @@ struct ltdc_layer_s
* layer - Reference to the layer structure
* argb - ARGB8888 color value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -245,7 +245,7 @@ struct ltdc_layer_s
* layer - Reference to the layer structure
* argb - Reference to store the ARGB8888 color value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -263,7 +263,7 @@ struct ltdc_layer_s
* layer - Reference to the layer structure
* rgb - RGB888 color key
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -279,7 +279,7 @@ struct ltdc_layer_s
* layer - Reference to the layer structure
* rgb - Reference to store the RGB888 color key
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -301,7 +301,7 @@ struct ltdc_layer_s
* layer - Reference to the layer structure
* alpha - Alpha value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -317,7 +317,7 @@ struct ltdc_layer_s
* layer - Reference to the layer structure
* alpha - Reference to store the alpha value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -335,7 +335,7 @@ struct ltdc_layer_s
* layer - Reference to the layer structure
* mode - Blend mode (see LTDC_BLEND_*)
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -373,7 +373,7 @@ struct ltdc_layer_s
* layer - Reference to the layer structure
* mode - Reference to store the blend mode
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -400,7 +400,7 @@ struct ltdc_layer_s
* srcxpos - x position of the visible pixel of the whole layer
* srcypos - y position of the visible pixel of the whole layer
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -426,7 +426,7 @@ struct ltdc_layer_s
* srcxpos - Reference to store the referenced x position of the whole layer
* srcypos - Reference to store the reterenced y position of the whole layer
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -445,7 +445,7 @@ struct ltdc_layer_s
* layer - Reference to the layer structure
* mode - operation mode (see LTDC_UPDATE_*)
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid
* -ECANCELED - Operation cancelled, something goes wrong
@@ -489,7 +489,7 @@ struct ltdc_layer_s
* src - Reference to the source layer
* srcarea - Reference to the selected area of the source layer
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* source area outside the visible area of the destination layer.
@@ -518,7 +518,7 @@ struct ltdc_layer_s
* back - Reference to the background layer
* backarea - Reference to the selected area of the background layer
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* source area outside the visible area of the destination layer.
@@ -543,7 +543,7 @@ struct ltdc_layer_s
* color - Color to fill the selected area. Color must be formatted
* according to the layer pixel format.
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* area outside the visible area of the layer.
@@ -607,7 +607,7 @@ struct stm32_ltdc_s
* Description:
* Initialize the ltdc controller
*
- * Return:
+ * Returned Value:
* OK
*
************************************************************************************/
@@ -625,7 +625,7 @@ void stm32_ltdcuninitialize(void);
* Parameter:
* lid - Layer identifier
*
- * Return:
+ * Returned Value:
* Reference to the layer control structure on success or Null if parameter
* invalid.
*
diff --git a/arch/arm/src/stm32/stm32_opamp.c b/arch/arm/src/stm32/stm32_opamp.c
index e79e8ed8068845ea906423062e4e591446921173..e839bba863d452f5100c46177751baccb9d23311 100644
--- a/arch/arm/src/stm32/stm32_opamp.c
+++ b/arch/arm/src/stm32/stm32_opamp.c
@@ -1402,7 +1402,6 @@ FAR struct opamp_dev_s* stm32_opampinitialize(int intf)
if (ret < 0)
{
aerr("ERROR: Failed to initialize OPAMP%d: %d\n", intf, ret);
- errno = -ret;
return NULL;
}
diff --git a/arch/arm/src/stm32/stm32_otgfshost.c b/arch/arm/src/stm32/stm32_otgfshost.c
index 8a6382d345b0bac1274828f69fc4ef199722c731..1b29ae09e5e66cfbcda18e69c37c70745546c5ed 100644
--- a/arch/arm/src/stm32/stm32_otgfshost.c
+++ b/arch/arm/src/stm32/stm32_otgfshost.c
@@ -1265,7 +1265,7 @@ static int stm32_ctrlchan_alloc(FAR struct stm32_usbhost_s *priv,
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -1327,7 +1327,7 @@ static int stm32_ctrlep_alloc(FAR struct stm32_usbhost_s *priv,
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3820,7 +3820,7 @@ static void stm32_txfe_enable(FAR struct stm32_usbhost_s *priv, int chidx)
* hport - The location to return the hub port descriptor that detected the
* connection related event.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success when a device in connected or
* disconnected. This function will not return until either (1) a device is
* connected or disconnect to/from any hub port or until (2) some failure
@@ -3911,7 +3911,7 @@ static int stm32_wait(FAR struct usbhost_connection_s *conn,
* hport - The descriptor of the hub port that has the newly connected
* device.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4041,7 +4041,7 @@ static int stm32_enumerate(FAR struct usbhost_connection_s *conn,
* maxpacketsize - The maximum number of bytes that can be sent to or
* received from the endpoint in a single data packet
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4100,7 +4100,7 @@ static int stm32_ep0configure(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4156,7 +4156,7 @@ static int stm32_epalloc(FAR struct usbhost_driver_s *drvr,
* the class create() method.
* ep - The endpoint to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4224,7 +4224,7 @@ static int stm32_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
* maxlen - The address of a memory location provided by the caller in which to
* return the maximum size of the allocated buffer memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4270,7 +4270,7 @@ static int stm32_alloc(FAR struct usbhost_driver_s *drvr,
* the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4306,7 +4306,7 @@ static int stm32_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer)
* return the allocated buffer memory address.
* buflen - The size of the buffer required.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4350,7 +4350,7 @@ static int stm32_ioalloc(FAR struct usbhost_driver_s *drvr,
* the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4393,7 +4393,7 @@ static int stm32_iofree(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer)
* NOTE: On an IN transaction, req and buffer may refer to the same allocated
* memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4596,7 +4596,7 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
* (IN endpoint). buffer must have been allocated using DRVR_ALLOC
* buflen - The length of the data to be sent or received.
*
- * Returned Values:
+ * Returned Value:
* On success, a non-negative value is returned that indicates the number
* of bytes successfully transferred. On a failure, a negated errno value is
* returned that indicates the nature of the failure:
@@ -4668,7 +4668,7 @@ static ssize_t stm32_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep
* arg - The arbitrary parameter that will be passed to the callback function
* when the transfer completes.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4724,7 +4724,7 @@ static int stm32_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
* ep - The IN or OUT endpoint descriptor for the device endpoint on which an
* asynchronous transfer should be transferred.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -4813,7 +4813,7 @@ static int stm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
* related event
* connected - True: device connected; false: device disconnected
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -4865,7 +4865,7 @@ static int stm32_connect(FAR struct usbhost_driver_s *drvr,
* hport - The port from which the device is being disconnected. Might be a port
* on a hub.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
diff --git a/arch/arm/src/stm32/stm32_otghshost.c b/arch/arm/src/stm32/stm32_otghshost.c
index ad1091d02f76de61f65b18e9c77825710ea571db..c276742ab7e0dc39fe339628f57c405f3b8f8144 100644
--- a/arch/arm/src/stm32/stm32_otghshost.c
+++ b/arch/arm/src/stm32/stm32_otghshost.c
@@ -1270,7 +1270,7 @@ static int stm32_ctrlchan_alloc(FAR struct stm32_usbhost_s *priv,
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -1332,7 +1332,7 @@ static int stm32_ctrlep_alloc(FAR struct stm32_usbhost_s *priv,
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3825,7 +3825,7 @@ static void stm32_txfe_enable(FAR struct stm32_usbhost_s *priv, int chidx)
* hport - The location to return the hub port descriptor that detected the
* connection related event.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success when a device in connected or
* disconnected. This function will not return until either (1) a device is
* connected or disconnect to/from any hub port or until (2) some failure
@@ -3916,7 +3916,7 @@ static int stm32_wait(FAR struct usbhost_connection_s *conn,
* hport - The descriptor of the hub port that has the newly connected
* device.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4046,7 +4046,7 @@ static int stm32_enumerate(FAR struct usbhost_connection_s *conn,
* maxpacketsize - The maximum number of bytes that can be sent to or
* received from the endpoint in a single data packet
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4105,7 +4105,7 @@ static int stm32_ep0configure(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4161,7 +4161,7 @@ static int stm32_epalloc(FAR struct usbhost_driver_s *drvr,
* the class create() method.
* ep - The endpoint to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4229,7 +4229,7 @@ static int stm32_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
* maxlen - The address of a memory location provided by the caller in which to
* return the maximum size of the allocated buffer memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4275,7 +4275,7 @@ static int stm32_alloc(FAR struct usbhost_driver_s *drvr,
* the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4311,7 +4311,7 @@ static int stm32_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer)
* return the allocated buffer memory address.
* buflen - The size of the buffer required.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4355,7 +4355,7 @@ static int stm32_ioalloc(FAR struct usbhost_driver_s *drvr,
* the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4398,7 +4398,7 @@ static int stm32_iofree(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer)
* NOTE: On an IN transaction, req and buffer may refer to the same allocated
* memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4601,7 +4601,7 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
* (IN endpoint). buffer must have been allocated using DRVR_ALLOC
* buflen - The length of the data to be sent or received.
*
- * Returned Values:
+ * Returned Value:
* On success, a non-negative value is returned that indicates the number
* of bytes successfully transferred. On a failure, a negated errno value is
* returned that indicates the nature of the failure:
@@ -4673,7 +4673,7 @@ static ssize_t stm32_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep
* arg - The arbitrary parameter that will be passed to the callback function
* when the transfer completes.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4729,7 +4729,7 @@ static int stm32_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
* ep - The IN or OUT endpoint descriptor for the device endpoint on which an
* asynchronous transfer should be transferred.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -4818,7 +4818,7 @@ static int stm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
* related event
* connected - True: device connected; false: device disconnected
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -4870,7 +4870,7 @@ static int stm32_connect(FAR struct usbhost_driver_s *drvr,
* hport - The port from which the device is being disconnected. Might be a port
* on a hub.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
diff --git a/arch/arm/src/stm32/stm32_pm.h b/arch/arm/src/stm32/stm32_pm.h
index 7fc93ba688f9d324dfc550b647f217c550ffcb0d..8feee1f5666fc1ee29b618fc05475b1f01571b08 100644
--- a/arch/arm/src/stm32/stm32_pm.h
+++ b/arch/arm/src/stm32/stm32_pm.h
@@ -102,7 +102,7 @@ int stm32_pmstop(bool lpds);
* Input Parameters:
* None
*
- * Returned Value.
+ * Returned Value:
* On success, this function will not return (STANDBY mode can only be
* terminated with a reset event). Otherwise, STANDBY mode did not occur
* and a negated errno value is returned to indicate the cause of the
diff --git a/arch/arm/src/stm32/stm32_pminitialize.c b/arch/arm/src/stm32/stm32_pminitialize.c
index e9b6d4780cb43c27cead52ed1293ac5866134e4d..243bc53aa4e7bce92750c80d3aabe4ed5e2839a2 100644
--- a/arch/arm/src/stm32/stm32_pminitialize.c
+++ b/arch/arm/src/stm32/stm32_pminitialize.c
@@ -76,10 +76,10 @@
* *before* any other device drivers are initialized (since they may
* attempt to register with the power management subsystem).
*
- * Input parameters:
+ * Input Parameters:
* None.
*
- * Returned value:
+ * Returned Value:
* None.
*
****************************************************************************/
diff --git a/arch/arm/src/stm32/stm32_pmstandby.c b/arch/arm/src/stm32/stm32_pmstandby.c
index 2b4de6a6f0ec407160bd8f8761b1e2da06c4f00a..952e14317fcd76f6a42b6df9d5de1435c1792003 100644
--- a/arch/arm/src/stm32/stm32_pmstandby.c
+++ b/arch/arm/src/stm32/stm32_pmstandby.c
@@ -71,7 +71,7 @@
* Input Parameters:
* None
*
- * Returned Value.
+ * Returned Value:
* On success, this function will not return (STANDBY mode can only be
* terminated with a reset event). Otherwise, STANDBY mode did not occur
* and a negated errno value is returned to indicate the cause of the
diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c
index 0e9db5005947119a375cdffe2e31745a5498f9e3..7aadb98ae7278d4560483fff54e297ead1bb309e 100644
--- a/arch/arm/src/stm32/stm32_pwm.c
+++ b/arch/arm/src/stm32/stm32_pwm.c
@@ -1095,7 +1095,7 @@ static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, uint16_t value
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the PWM block status
*
* Returned Value:
@@ -1182,7 +1182,7 @@ static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg)
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -1815,7 +1815,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
* Description:
* Try to change only channel duty.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the lower half PWM driver state structure
* channel - Channel to by updated
* duty - New duty.
@@ -1897,7 +1897,7 @@ static int pwm_update_duty(FAR struct stm32_pwmtimer_s *priv, uint8_t channel,
* Description:
* Handle timer interrupts.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -1980,7 +1980,7 @@ static int pwm_interrupt(struct stm32_pwmtimer_s *priv)
* Description:
* Handle timer 1 and 8 interrupts.
*
- * Input parameters:
+ * Input Parameters:
* Standard NuttX interrupt inputs
*
* Returned Value:
@@ -2008,7 +2008,7 @@ static int pwm_tim8interrupt(int irq, void *context, FAR void *arg)
* Description:
* Pick an optimal pulse count to program the RCR.
*
- * Input parameters:
+ * Input Parameters:
* count - The total count remaining
*
* Returned Value:
@@ -2055,7 +2055,7 @@ static uint8_t pwm_pulsecount(uint32_t count)
* Description:
* Enable or disable APB clock for the timer peripheral
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* on - Enable clock if 'on' is 'true' and disable if 'false'
*
@@ -2188,7 +2188,7 @@ static void pwm_set_apb_clock(FAR struct stm32_pwmtimer_s *priv, bool on)
* should configure and initialize the device so that it is ready for use.
* It should not, however, output pulses until the start method is called.
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -2241,7 +2241,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
* stop pulsed output, free any resources, disable the timer hardware, and
* put the system into the lowest possible power usage state
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -2303,7 +2303,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -2390,7 +2390,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
* Description:
* Stop the pulsed output and reset the timer resources
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -2549,7 +2549,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
* Description:
* Lower-half logic may support platform-specific ioctl commands
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* cmd - The ioctl command
* arg - The argument accompanying the ioctl command
diff --git a/arch/arm/src/stm32/stm32_pwr.c b/arch/arm/src/stm32/stm32_pwr.c
index 04cf7e9387cb0efe3991a5571a15db67efb1467a..5a4b863b55db64a3eb018782ed9e251bb6e8864c 100644
--- a/arch/arm/src/stm32/stm32_pwr.c
+++ b/arch/arm/src/stm32/stm32_pwr.c
@@ -263,7 +263,7 @@ void stm32_pwr_enablebkp(bool writable)
* wupin - Selects the WKUP pin to enable/disable
* wupon - state to set it to
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned on any
* failure. The only cause of failure is if the selected MCU does not support
* the requested wakeup pin.
@@ -359,7 +359,7 @@ bool stm32_pwr_getwuf(void)
* Input Parameters:
* regon - state to set it to
*
- * Returned Values:
+ * Returned Value:
* None
*
************************************************************************************/
@@ -390,7 +390,7 @@ void stm32_pwr_enablebreg(bool regon)
* Input Parameters:
* vos - Properly aligned voltage scaling select bits for the PWR_CR register.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
@@ -432,7 +432,7 @@ void stm32_pwr_setvos(uint16_t vos)
* Input Parameters:
* pls - PVD level
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
diff --git a/arch/arm/src/stm32/stm32_pwr.h b/arch/arm/src/stm32/stm32_pwr.h
index b93b34108cd66ec652549f5a0a3700b94fcf1268..ee56a40d18e5d8aca5f8cd3d6e465fdb481d8165 100644
--- a/arch/arm/src/stm32/stm32_pwr.h
+++ b/arch/arm/src/stm32/stm32_pwr.h
@@ -152,7 +152,7 @@ void stm32_pwr_enablebkp(bool writable);
* wupin - Selects the WKUP pin to enable/disable
* wupon - state to set it to
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned on any
* failure. The only cause of failure is if the selected MCU does not support
* the requested wakeup pin.
@@ -195,7 +195,7 @@ bool stm32_pwr_getwuf(void);
* Input Parameters:
* regon - state to set it to
*
- * Returned Values:
+ * Returned Value:
* None
*
************************************************************************************/
@@ -215,7 +215,7 @@ void stm32_pwr_enablebreg(bool regon);
* Input Parameters:
* vos - Properly aligned voltage scaling select bits for the PWR_CR register.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
@@ -237,7 +237,7 @@ void stm32_pwr_setvos(uint16_t vos);
* Input Parameters:
* pls - PVD level
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
diff --git a/arch/arm/src/stm32/stm32_qencoder.c b/arch/arm/src/stm32/stm32_qencoder.c
index 5bc98ad32296f5b7b40ed6f1003608a6cbbfe595..661e737f8a8e736f01a779109ee6a091255fb132 100644
--- a/arch/arm/src/stm32/stm32_qencoder.c
+++ b/arch/arm/src/stm32/stm32_qencoder.c
@@ -574,7 +574,7 @@ static void stm32_putreg32(FAR struct stm32_lowerhalf_s *priv, int offset, uint3
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the QENCODER block status
*
* Returned Value:
@@ -1173,7 +1173,7 @@ static int stm32_ioctl(FAR struct qe_lowerhalf_s *lower, int cmd, unsigned long
* devpath - The full path to the driver to register. E.g., "/dev/qe0"
* tim - The timer number to used. 'tim' must be an element of {1,2,3,4,5,8}
*
- * Returned Values:
+ * Returned Value:
* Zero on success; A negated errno value is returned on failure.
*
************************************************************************************/
diff --git a/arch/arm/src/stm32/stm32_qencoder.h b/arch/arm/src/stm32/stm32_qencoder.h
index bea28531b6722f1a9ae9dc81ad54f98027a2994e..98c5b25f11c7bcdaf0e1a6958c746be3a8dbbae2 100644
--- a/arch/arm/src/stm32/stm32_qencoder.h
+++ b/arch/arm/src/stm32/stm32_qencoder.h
@@ -130,7 +130,7 @@
* devpath - The full path to the driver to register. E.g., "/dev/qe0"
* tim - The timer number to used. 'tim' must be an element of {1,2,3,4,5,8}
*
- * Returned Values:
+ * Returned Value:
* Zero on success; A negated errno value is returned on failure.
*
************************************************************************************/
diff --git a/arch/arm/src/stm32/stm32_sdadc.c b/arch/arm/src/stm32/stm32_sdadc.c
index e8236a05f93cb247eec7aee1b48dfb2929bc7823..67e348c81d05dc04d3e4e775298441624516785b 100644
--- a/arch/arm/src/stm32/stm32_sdadc.c
+++ b/arch/arm/src/stm32/stm32_sdadc.c
@@ -456,7 +456,7 @@ static void tim_modifyreg(FAR struct stm32_dev_s *priv, int offset,
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the SDADC block state
*
* Returned Value:
@@ -629,7 +629,8 @@ static void sdadc_rccreset(FAR struct stm32_dev_s *priv, bool reset)
/****************************************************************************
* Name: sdadc_power_down_idle
*
- * Description : Enables or disables power down during the idle phase.
+ * Description:
+ * Enables or disables power down during the idle phase.
*
* Input Parameters:
* priv - A reference to the SDADC block state
@@ -670,7 +671,8 @@ static void sdadc_power_down_idle(FAR struct stm32_dev_s *priv, bool pdi_high)
/****************************************************************************
* Name: sdadc_enable
*
- * Description : Enables or disables the specified SDADC peripheral.
+ * Description:
+ * Enables or disables the specified SDADC peripheral.
* Does not start conversion unless the SDADC is
* triggered by timer
*
diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/stm32/stm32_sdio.c
index 31ecd08604c3c5d4fd4d731cc789f8f09d45d2c2..1d9f99e72b2996366c3463ad440fdbb41552c4f7 100644
--- a/arch/arm/src/stm32/stm32_sdio.c
+++ b/arch/arm/src/stm32/stm32_sdio.c
@@ -2500,7 +2500,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay, (wdentry_t)stm32_eventtimeout,
1, (uint32_t)priv);
- if (ret != OK)
+ if (ret < 0)
{
mcerr("ERROR: wd_start failed: %d\n", ret);
}
@@ -2954,7 +2954,7 @@ static void stm32_default(void)
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
@@ -3028,7 +3028,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -3075,7 +3075,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is writeprotected.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/stm32/stm32_sdio.h b/arch/arm/src/stm32/stm32_sdio.h
index 04c65ba00f975b35761ef391016503ecb9e5c22d..4fc477a0e44d2cf5e81839d24377cb525f6ccf9a 100644
--- a/arch/arm/src/stm32/stm32_sdio.h
+++ b/arch/arm/src/stm32/stm32_sdio.h
@@ -71,7 +71,7 @@ extern "C"
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
@@ -93,7 +93,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno);
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -111,7 +111,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is writeprotected.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c
index 74b70ffd0617aaa5c2b73b50f575bd0844c52a8f..a14404835b9899127329d50204790779592d3229 100644
--- a/arch/arm/src/stm32/stm32_serial.c
+++ b/arch/arm/src/stm32/stm32_serial.c
@@ -1381,7 +1381,7 @@ static void up_set_format(struct uart_dev_s *dev)
* Description:
* Enable or disable APB clock for the USART peripheral
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the UART driver state structure
* on - Enable clock if 'on' is 'true' and disable if 'false'
*
@@ -2274,7 +2274,7 @@ static bool up_rxavailable(struct uart_dev_s *dev)
* Return true if UART activated RX flow control to block more incoming
* data
*
- * Input parameters:
+ * Input Parameters:
* dev - UART device instance
* nbuffered - the number of characters currently buffered
* (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is
diff --git a/arch/arm/src/stm32/stm32_spi.c b/arch/arm/src/stm32/stm32_spi.c
index 71f6dbfb3a5796e3352f1c11d08df7403f2fd4ca..585a3e9231cd626533916ee60f946c4687d3ec5a 100644
--- a/arch/arm/src/stm32/stm32_spi.c
+++ b/arch/arm/src/stm32/stm32_spi.c
@@ -1122,13 +1122,6 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
uint16_t setbits;
uint32_t actual;
- /* Limit to max possible (if STM32_SPI_CLK_MAX is defined in board.h) */
-
- if (frequency > STM32_SPI_CLK_MAX)
- {
- frequency = STM32_SPI_CLK_MAX;
- }
-
/* Has the frequency changed? */
if (frequency != priv->frequency)
@@ -1677,7 +1670,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, size_t
* Description:
* Initialize the selected SPI bus in its default state (Master, 8-bit, mode 0, etc.)
*
- * Input Parameter:
+ * Input Parameters:
* priv - private SPI device structure
*
* Returned Value:
@@ -1782,7 +1775,7 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv)
* Description:
* Initialize the selected SPI bus
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/stm32/stm32_spi.h b/arch/arm/src/stm32/stm32_spi.h
index ee99808c6abbee3f0eb8baa843f150ca327ede21..bcc2f0e14bb68c8aa17407b7f781a37c138359cc 100644
--- a/arch/arm/src/stm32/stm32_spi.h
+++ b/arch/arm/src/stm32/stm32_spi.h
@@ -78,7 +78,7 @@ struct spi_dev_s;
* Description:
* Initialize the selected SPI bus
*
- * Input Parameter:
+ * Input Parameters:
* bus number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/stm32/stm32_tim.h b/arch/arm/src/stm32/stm32_tim.h
index bc6ef090c62a94740aefbdb0dabfe131250fe744..2e0828fafa27326e18d4991d07cb18e6cd0dcfd5 100644
--- a/arch/arm/src/stm32/stm32_tim.h
+++ b/arch/arm/src/stm32/stm32_tim.h
@@ -208,7 +208,7 @@ int stm32_tim_deinit(FAR struct stm32_tim_dev_s *dev);
* devpath - The full path to the timer device. This should be of the form /dev/timer0
* timer - the timer number.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
diff --git a/arch/arm/src/stm32/stm32_tim_lowerhalf.c b/arch/arm/src/stm32/stm32_tim_lowerhalf.c
index d8415ac040569c34c9c50eb6d20ae0af1cc7e009..d0a9619517e2e6d2fb9c7ec7d48cfe6375ed1fa1 100644
--- a/arch/arm/src/stm32/stm32_tim_lowerhalf.c
+++ b/arch/arm/src/stm32/stm32_tim_lowerhalf.c
@@ -261,7 +261,7 @@ static struct stm32_lowerhalf_s g_tim14_lowerhalf =
*
* Input Parameters:
*
- * Returned Values:
+ * Returned Value:
*
****************************************************************************/
@@ -297,7 +297,7 @@ static int stm32_timer_handler(int irq, void * context, void * arg)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -335,7 +335,7 @@ static int stm32_start(FAR struct timer_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -369,7 +369,7 @@ static int stm32_stop(struct timer_lowerhalf_s *lower)
* driver state structure.
* timeout - The new timeout value in microseconds.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -414,7 +414,7 @@ static int stm32_settimeout(FAR struct timer_lowerhalf_s *lower, uint32_t timeou
* behavior is restored,
* arg - Argument that will be provided in the callback
*
- * Returned Values:
+ * Returned Value:
* The previous timer expiration function pointer or NULL is there was
* no previous function pointer.
*
@@ -462,7 +462,7 @@ static void stm32_setcallback(FAR struct timer_lowerhalf_s *lower,
* form /dev/timer0
* timer - the timer's number.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
diff --git a/arch/arm/src/stm32/stm32_wdg.h b/arch/arm/src/stm32/stm32_wdg.h
index 64815bfe908dc66576aa95528550a7406d05a07e..264734b9f53bcdc63f5829188fc56bb78f666ea3 100644
--- a/arch/arm/src/stm32/stm32_wdg.h
+++ b/arch/arm/src/stm32/stm32_wdg.h
@@ -79,7 +79,7 @@ extern "C"
* /dev/watchdog0
* lsifreq - The calibrated LSI clock frequency
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -100,7 +100,7 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq);
* devpath - The full path to the watchdog. This should be of the form
* /dev/watchdog0
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/stm32/stm32_wwdg.c b/arch/arm/src/stm32/stm32_wwdg.c
index 79d34656dae29aeb710c5aaed5fe0769ef242d03..ba2b994fa40840b8c47b354042ad56af4f977d92 100644
--- a/arch/arm/src/stm32/stm32_wwdg.c
+++ b/arch/arm/src/stm32/stm32_wwdg.c
@@ -281,7 +281,7 @@ static void stm32_setwindow(FAR struct stm32_lowerhalf_s *priv, uint8_t window)
* Input Parameters:
* Usual interrupt handler arguments.
*
- * Returned Values:
+ * Returned Value:
* Always returns OK.
*
****************************************************************************/
@@ -329,7 +329,7 @@ static int stm32_interrupt(int irq, FAR void *context, FAR void *arg)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -361,7 +361,7 @@ static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -395,7 +395,7 @@ static int stm32_stop(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -426,7 +426,7 @@ static int stm32_keepalive(FAR struct watchdog_lowerhalf_s *lower)
* driver state structure.
* status - The location to return the watchdog status information.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -482,7 +482,7 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
* "lower-half" driver state structure.
* timeout - The new timeout value in milliseconds.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -618,7 +618,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* function pointer is NULL, then the reset-on-expiration
* behavior is restored,
*
- * Returned Values:
+ * Returned Value:
* The previous watchdog expiration function pointer or NULL is there was
* no previous function pointer, i.e., if the previous behavior was
* reset-on-expiration (NULL is also returned if an error occurs).
@@ -686,7 +686,7 @@ static xcpt_t stm32_capture(FAR struct watchdog_lowerhalf_s *lower,
* interpretation of this argument depends on the particular
* command.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -742,7 +742,7 @@ static int stm32_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
* devpath - The full path to the watchdog. This should be of the form
* /dev/watchdog0
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/stm32/stm32f10xxx_dma.c b/arch/arm/src/stm32/stm32f10xxx_dma.c
index c3c666e937b5a4deced4a2dc36b7f92f83819de9..72da836ad1b561c0abf4d4ab38b91351d8c022b9 100644
--- a/arch/arm/src/stm32/stm32f10xxx_dma.c
+++ b/arch/arm/src/stm32/stm32f10xxx_dma.c
@@ -395,7 +395,7 @@ void weak_function up_dmainitialize(void)
* Hmm.. I suppose this interface could be extended to make a non-blocking
* version. Feel free to do that if that is what you need.
*
- * Input parameter:
+ * Input Parameters:
* chndx - Identifies the stream/channel resource. For the STM32 F1, this
* is simply the channel number as provided by the DMACHAN_* definitions
* in chip/stm32f10xxx_dma.h.
@@ -626,7 +626,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle)
* of the processor. Note that this only applies to memory addresses, it
* will return false for any peripheral address.
*
- * Returned value:
+ * Returned Value:
* True, if transfer is possible.
*
****************************************************************************/
diff --git a/arch/arm/src/stm32/stm32f20xxx_dma.c b/arch/arm/src/stm32/stm32f20xxx_dma.c
index 8c06819f7a5db56e83bf8f605713d501a2225245..86b95f7f1379c2244d51fb385c73d466d583488b 100644
--- a/arch/arm/src/stm32/stm32f20xxx_dma.c
+++ b/arch/arm/src/stm32/stm32f20xxx_dma.c
@@ -525,7 +525,7 @@ void weak_function up_dmainitialize(void)
* Hmm.. I suppose this interface could be extended to make a non-blocking
* version. Feel free to do that if that is what you need.
*
- * Input parameter:
+ * Input Parameters:
* dmamap - Identifies the stream/channel resource. For the STM32 F2, this
* is a bit-encoded value as provided by the DMAMAP_* definitions
* in chip/stm32f20xxx_dma.h
@@ -856,7 +856,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle)
* of the processor. Note that this only applies to memory addresses, it
* will return false for any peripheral address.
*
- * Returned value:
+ * Returned Value:
* True, if transfer is possible.
*
****************************************************************************/
diff --git a/arch/arm/src/stm32/stm32f33xxx_adc.c b/arch/arm/src/stm32/stm32f33xxx_adc.c
index 4eb887e1484a97afea75710a57901079269086e6..b75641c27af4025af20198ce85d57ebb63179c6b 100644
--- a/arch/arm/src/stm32/stm32f33xxx_adc.c
+++ b/arch/arm/src/stm32/stm32f33xxx_adc.c
@@ -804,7 +804,7 @@ static void tim_modifyreg(FAR struct stm32_dev_s *priv, int offset,
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the ADC block status
*
* Returned Value:
@@ -1350,9 +1350,9 @@ static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset)
/****************************************************************************
* Name: adc_enable
*
- * Description : Enables or disables the specified ADC peripheral.
- * Also, starts a conversion when the ADC is not
- * triggered by timers
+ * Description:
+ * Enables or disables the specified ADC peripheral. Also, starts a
+ * conversion when the ADC is not triggered by timers
*
* Input Parameters:
*
diff --git a/arch/arm/src/stm32/stm32f33xxx_dma.c b/arch/arm/src/stm32/stm32f33xxx_dma.c
index af091e2fec6c4278df7634e10673432878589627..1c0c626e601abab15c1fb1f7666f2d188c22f966 100644
--- a/arch/arm/src/stm32/stm32f33xxx_dma.c
+++ b/arch/arm/src/stm32/stm32f33xxx_dma.c
@@ -343,7 +343,7 @@ void weak_function up_dmainitialize(void)
* Hmm.. I suppose this interface could be extended to make a non-blocking
* version. Feel free to do that if that is what you need.
*
- * Input parameter:
+ * Input Parameters:
* chndx - Identifies the stream/channel resource. For the STM32 F1, this
* is simply the channel number as provided by the DMACHAN_* definitions
* in chip/stm32f10xxx_dma.h.
@@ -574,7 +574,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle)
* of the processor. Note that this only applies to memory addresses, it
* will return false for any peripheral address.
*
- * Returned value:
+ * Returned Value:
* True, if transfer is possible.
*
****************************************************************************/
diff --git a/arch/arm/src/stm32/stm32f40xxx_dma.c b/arch/arm/src/stm32/stm32f40xxx_dma.c
index 6dedd5a337de43551eb6624533eca765e8a5adb3..7f528f1a330e471eb1e0bd22f5126cd9dc3a42d8 100644
--- a/arch/arm/src/stm32/stm32f40xxx_dma.c
+++ b/arch/arm/src/stm32/stm32f40xxx_dma.c
@@ -524,7 +524,7 @@ void weak_function up_dmainitialize(void)
* Hmm.. I suppose this interface could be extended to make a non-blocking
* version. Feel free to do that if that is what you need.
*
- * Input parameter:
+ * Input Parameters:
* dmamap - Identifies the stream/channel resource. For the STM32 F4, this
* is a bit-encoded value as provided by the DMAMAP_* definitions
* in chip/stm32f40xxx_dma.h
@@ -863,7 +863,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle)
* of the processor. Note that this only applies to memory addresses, it
* will return false for any peripheral address.
*
- * Returned value:
+ * Returned Value:
* True, if transfer is possible.
*
****************************************************************************/
diff --git a/arch/arm/src/stm32/stm32f40xxx_i2c.c b/arch/arm/src/stm32/stm32f40xxx_i2c.c
index 86de66e7f56ccc3967845e01fe2c3b1ef8ed7e52..ac3c85adc00bbd08968cc2de39356c89eae3719a 100644
--- a/arch/arm/src/stm32/stm32f40xxx_i2c.c
+++ b/arch/arm/src/stm32/stm32f40xxx_i2c.c
@@ -270,7 +270,6 @@ struct stm32_i2c_priv_s
volatile int dcnt; /* Current message length */
uint16_t flags; /* Current message flags */
bool check_addr_ACK; /* Flag to signal if on next interrupt address has ACKed */
- uint8_t total_msg_len; /* Flag to signal a short read sequence */
/* I2C trace support */
@@ -1260,27 +1259,6 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
priv->status = status;
- /* Any new message should begin with "Start" condition
- * However there were 2 situations where that was not true
- * Situation 1: priv->msgc == 0 came from DMA RX handler and should
- * be managed
- *
- * Situation 2: If an error is injected that looks like a STOP the
- * interrupt will be reentered with some status that will be incorrect. This
- * will ensure that the error handler will clear the interrupt enables and
- * return the error to the waiting task.
- */
-
- if (priv->dcnt == -1 && priv->msgc != 0 && (status & I2C_SR1_SB) == 0)
- {
-#ifdef CONFIG_STM32_I2C_DMA
- return OK;
-#else
- priv->status |= I2C_SR1_TIMEOUT;
- goto state_error;
-#endif
- }
-
/* Check if this is a new transmission so to set up the
* trace table accordingly.
*/
@@ -1327,13 +1305,33 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
if (priv->dcnt == -1 && priv->msgc > 0)
{
+ /* Any new message should begin with "Start" condition
+ * However there were 2 situations where that was not true
+ * Situation 1: Next message continue transmission sequence of previous message
+ *
+ * Situation 2: If an error is injected that looks like a STOP the
+ * interrupt will be reentered with some status that will be incorrect. This
+ * will ensure that the error handler will clear the interrupt enables and
+ * return the error to the waiting task.
+ */
+
+ if (((priv->msgv[0].flags & I2C_M_NORESTART) != 0 && (status & I2C_SR1_TXE) == 0) ||
+ ((priv->msgv[0].flags & I2C_M_NORESTART) == 0 && (status & I2C_SR1_SB) == 0))
+ {
+#if defined(CONFIG_STM32_I2C_DMA) || defined(CONFIG_I2C_POLLED)
+ return OK;
+#else
+ priv->status |= I2C_SR1_TIMEOUT;
+ goto state_error;
+#endif
+ }
+
i2cinfo("Switch to new message\n");
/* Get current message to process data and copy to private structure */
priv->ptr = priv->msgv->buffer; /* Copy buffer to private struct */
priv->dcnt = priv->msgv->length; /* Set counter of current msg length */
- priv->total_msg_len = priv->msgv->length; /* Set total msg length */
priv->flags = priv->msgv->flags; /* Copy flags to private struct */
i2cinfo("Current flags %i\n", priv->flags);
@@ -1435,9 +1433,11 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
priv->dcnt = -1;
+#ifndef CONFIG_I2C_POLLED
/* Restart ISR by setting an interrupt buffer bit */
stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN);
+#endif
}
}
@@ -1504,10 +1504,6 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
priv->check_addr_ACK = false;
- /* Enable RxNE and TxE buffers in order to receive one or multiple bytes */
-
- stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN);
-
/* Note:
*
* When reading a single byte the stop condition has to be set
@@ -1518,7 +1514,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
* after the clearing of the address.
*/
- if (priv->dcnt == 1 && priv->total_msg_len == 1)
+ if (priv->dcnt == 1)
{
/* this should only happen when receiving a message of length 1 */
@@ -1532,6 +1528,12 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0);
+#ifndef CONFIG_I2C_POLLED
+ /* Enable RxNE and TxE buffers in order to receive one or multiple bytes */
+
+ stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN);
+#endif
+
/* Clear ADDR flag by reading SR2 and adding it to status */
status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16);
@@ -1554,7 +1556,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED_READ_1, 0);
}
- else if (priv->dcnt == 2 && priv->total_msg_len == 2)
+ else if (priv->dcnt == 2)
{
/* This should only happen when receiving a message of length 2 */
@@ -1627,6 +1629,15 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
stm32_dmastart(priv->rxdma, stm32_i2c_dmarxcallback, priv, false);
stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_DMAEN);
+#else
+#ifndef CONFIG_I2C_POLLED
+ if (priv->dcnt > 3)
+ {
+ /* Don't enable I2C_CR2_ITBUFEN for messages longer than 3 bytes */
+
+ stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN);
+ }
+#endif
#endif
}
}
@@ -1638,8 +1649,60 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
* begin immediately after.
*/
- else if ((priv->flags & (I2C_M_READ)) == 0 &&
- (status & (I2C_SR1_ADDR | I2C_SR1_TXE)) != 0)
+ else if ((priv->flags & I2C_M_READ) == 0 &&
+ (status & I2C_SR1_BTF) != 0 &&
+ priv->dcnt == 0)
+ {
+ /* After last byte, check what to do based on next message flags */
+
+ if (priv->msgc == 0)
+ {
+ /* If last message send stop bit */
+
+ stm32_i2c_sendstop(priv);
+ i2cinfo("Stop sent dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc);
+
+ /* Decrease counter to get to next message */
+
+ priv->dcnt--;
+ i2cinfo("dcnt %i\n", priv->dcnt);
+ stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, priv->dcnt);
+ }
+
+ /* If there is a next message with no flags or the read flag
+ * a restart sequence has to be sent.
+ * Note msgv already points to the next message.
+ */
+
+ else if (priv->msgc > 0 &&
+ (priv->msgv->flags == 0 || (priv->msgv[0].flags & I2C_M_READ) != 0))
+ {
+ /* Send start */
+
+ stm32_i2c_sendstart(priv);
+
+ stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET);
+
+ i2cinfo("Restart detected!\n");
+ i2cinfo("Nextflag %i\n", priv->msgv[0].flags);
+
+ /* Decrease counter to get to next message */
+
+ priv->dcnt--;
+ i2cinfo("dcnt %i\n", priv->dcnt);
+ stm32_i2c_traceevent(priv, I2CEVENT_WRITE_RESTART, priv->dcnt);
+ }
+ else
+ {
+ i2cinfo("Write mode: next message has an unrecognized flag.\n");
+ stm32_i2c_traceevent(priv, I2CEVENT_WRITE_FLAG_ERROR, priv->msgv->flags);
+ }
+
+ status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16);
+ }
+ else if ((priv->flags & I2C_M_READ) == 0 &&
+ (status & (I2C_SR1_ADDR | I2C_SR1_TXE)) != 0 &&
+ priv->dcnt != 0)
{
/* The has cleared(ADDR is set, ACK was received after the address)
* or the transmit buffer is empty flag has been set(TxE) then we can
@@ -1662,134 +1725,101 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
* msg flags) has to be set.
*/
- if (priv->dcnt >= 1)
- {
#ifdef CONFIG_STM32_I2C_DMA
- /* if DMA is enabled, only makes sense to make use of it for longer
- than 1 B transfers.. */
+ /* if DMA is enabled, only makes sense to make use of it for longer
+ * than 1 B transfers.
+ */
- if (priv->dcnt > 1)
- {
- i2cinfo("Starting dma transfer and disabling interrupts\n");
+ if (priv->dcnt > 1)
+ {
+ i2cinfo("Starting DMA transfer and disabling interrupts\n");
- /* The DMA must be initialized and enabled before the I2C data transfer.
- * The DMAEN bit must be set in the I2C_CR2 register before the ADDR event.
- */
+ /* The DMA must be initialized and enabled before the I2C data
+ * transfer. The DMAEN bit must be set in the I2C_CR2 register
+ * before the ADDR event.
+ */
- stm32_dmasetup(priv->txdma, priv->config->base+STM32_I2C_DR_OFFSET,
- (uint32_t) priv->ptr, priv->dcnt,
- DMA_SCR_DIR_M2P |
- DMA_SCR_MSIZE_8BITS |
- DMA_SCR_PSIZE_8BITS |
- DMA_SCR_MINC |
- I2C_DMA_PRIO );
+ stm32_dmasetup(priv->txdma, priv->config->base+STM32_I2C_DR_OFFSET,
+ (uint32_t) priv->ptr, priv->dcnt,
+ DMA_SCR_DIR_M2P |
+ DMA_SCR_MSIZE_8BITS |
+ DMA_SCR_PSIZE_8BITS |
+ DMA_SCR_MINC |
+ I2C_DMA_PRIO );
- /* Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is
- * used.
- */
+ /* Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is
+ * used.
+ */
- stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_ITBUFEN, 0);
+ stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_ITBUFEN, 0);
#ifndef CONFIG_I2C_POLLED
- /* Now let DMA do all the work, disable i2c interrupts */
+ /* Now let DMA do all the work, disable i2c interrupts */
- regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET);
- regval &= ~I2C_CR2_ALLINTS;
- stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval);
+ regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET);
+ regval &= ~I2C_CR2_ALLINTS;
+ stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval);
#endif
- /* In the interrupt routine after the EOT interrupt, disable DMA
- * requests then wait for a BTF event before programming the Stop
- * condition. To do this, we'll just call the ISR again in
- * dma tx callback, in which point we fall into the msgc==0 case
- * which ultimately sends the stop..TODO: but we don't explicitly
- * wait for BTF bit being set...
- * Start DMA.
- */
-
- stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_DMAEN);
- stm32_dmastart(priv->txdma, stm32_i2c_dmatxcallback, priv, false);
- }
- else
-#endif /* CONFIG_STM32_I2C_DMA */
- {
- /* Transmitting message. Send byte == write data into write register */
-
- stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, *priv->ptr++);
-
- /* Decrease current message length */
+ /* In the interrupt routine after the EOT interrupt, disable DMA
+ * requests then wait for a BTF event before programming the Stop
+ * condition. To do this, we'll just call the ISR again in
+ * DMA tx callback, in which point we fall into the msgc==0 case
+ * which ultimately sends the stop..TODO: but we don't explicitly
+ * wait for BTF bit being set...
+ * Start DMA.
+ */
- stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt);
- priv->dcnt--;
- }
+ stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_DMAEN);
+ stm32_dmastart(priv->txdma, stm32_i2c_dmatxcallback, priv, false);
}
- else if (priv->dcnt == 0)
+ else
+#endif /* CONFIG_STM32_I2C_DMA */
{
- /* After last byte, check what to do based on next message flags */
-
- if (priv->msgc == 0)
+#ifndef CONFIG_I2C_POLLED
+ if (priv->dcnt == 1 &&
+ (priv->msgc == 0 || (priv->msgv->flags & I2C_M_NORESTART) == 0))
{
- /* If last message send stop bit */
-
- stm32_i2c_sendstop(priv);
- i2cinfo("Stop sent dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc);
-
- /* Decrease counter to get to next message */
-
- priv->dcnt--;
- i2cinfo("dcnt %i\n", priv->dcnt);
- stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, priv->dcnt);
+ stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_ITBUFEN, 0);
}
+#endif
- /* If there is a next message with no flags or the read flag
- * a restart sequence has to be sent.
- * Note msgv already points to the next message.
- */
+ /* Transmitting message. Send byte == write data into write register */
- else if (priv->msgc > 0 &&
- (priv->msgv->flags == 0 || (priv->msgv[0].flags & I2C_M_READ) != 0))
- {
- /* ACK ISR (for some reason this is necessary even though the
- * sendstart should clear the BTF).
- */
+ stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, *priv->ptr++);
- stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET);
+ /* Decrease current message length */
- /* Send start */
+ stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt);
+ priv->dcnt--;
- stm32_i2c_sendstart(priv);
+ if ((status & I2C_SR1_ADDR) != 0 && priv->dcnt > 0)
+ {
+ /* Transmitting message. ADDR -> BTF & TXE - Send one more byte */
- i2cinfo("Restart detected!\n");
- i2cinfo("Nextflag %i\n", priv->msgv[0].flags);
+ stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, *priv->ptr++);
- /* Decrease counter to get to next message */
+ /* Decrease current message length */
+ stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt);
priv->dcnt--;
- i2cinfo("dcnt %i\n", priv->dcnt);
- stm32_i2c_traceevent(priv, I2CEVENT_WRITE_RESTART, priv->dcnt);
}
- /* If there is a next message with the NO_RESTART flag
- * do nothing.
- */
-
- else if (priv->msgc > 0 && ((priv->msgv->flags & I2C_M_NORESTART) != 0))
+#ifndef CONFIG_I2C_POLLED
+ if (((status & I2C_SR1_ADDR) != 0 && priv->dcnt > 0) ||
+ (priv->msgc > 0 && (priv->msgv->flags & I2C_M_NORESTART) != 0))
+ {
+ stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN);
+ }
+#endif
+ if (priv->dcnt == 0 &&
+ priv->msgc > 0 && (priv->msgv->flags & I2C_M_NORESTART) != 0)
{
/* Set condition to get to next message */
priv->dcnt =- 1;
stm32_i2c_traceevent(priv, I2CEVENT_WRITE_NO_RESTART, priv->dcnt);
}
- else
- {
- i2cinfo("Write mode: next message has an unrecognized flag.\n");
- stm32_i2c_traceevent(priv, I2CEVENT_WRITE_FLAG_ERROR, priv->msgv->flags);
- }
- }
- else
- {
- i2cerr("Write mode error.\n");
- stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0);
}
}
@@ -1798,6 +1828,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
* Handles all read related I2C protocol logic.
*
* * * * * * * WARNING STM32F1xx HARDWARE ERRATA * * * * * * *
+ *
* source: https://github.com/hikob/openlab/blob/master/drivers/stm32/i2c.c
*
* RXNE-only events should not be handled since it sometimes
@@ -1820,172 +1851,67 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
* -> the i2c transfer was B1 B2 B3 B4 B5(B6 is not sent)
*/
- else if ((priv->flags & (I2C_M_READ)) != 0 && (status & I2C_SR1_RXNE) != 0)
+ else if ((priv->flags & (I2C_M_READ)) != 0 &&
+ (status & (I2C_SR1_RXNE | I2C_SR1_BTF)) != 0)
{
/* When read flag is set and the receive buffer is not empty
*(RXNE is set) then the driver can read from the data register.
*/
- i2cinfo("Entering read mode dcnt = %i msgc = %i, status %i\n",
+ status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16);
+
+ i2cinfo("Entering read mode dcnt = %i msgc = %i, status 0x%04x\n",
priv->dcnt, priv->msgc, status);
- /* Implementation of method 2 for receiving data following
- * the stm32f1xx reference manual.
+ /* Byte #N-3W, we don't want to manage RxNE interrupt anymore, bytes
+ * N, N-1, N-2 will be read with BTF:
*/
- /* Case total message length = 1 */
-
- if (priv->dcnt == 1 && priv->total_msg_len == 1)
+#ifndef CONFIG_I2C_POLLED
+ if (priv->dcnt < 5)
{
- i2cinfo("short read N=1: Read data from data register(DR)\n");
-
- *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET);
- priv->dcnt = -1;
- stm32_i2c_traceevent(priv, I2CEVENT_READ, 0);
- }
-
- /* Case total message length = 2 */
-
- else if (priv->dcnt == 2 && priv->total_msg_len == 2 && !(status & I2C_SR1_BTF))
- {
- i2cinfo("short read N=2: DR full, SR empty. Waiting for more bytes.\n");
- stm32_i2c_traceevent(priv, I2CEVENT_READ_SR_EMPTY, 0);
+ stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_ITBUFEN, 0);
}
- else if (priv->dcnt == 2 && priv->total_msg_len == 2 && (status & I2C_SR1_BTF))
+#else
+ if (priv->dcnt == 1 || priv->dcnt > 3 || (status & I2C_SR1_BTF) != 0)
+#endif
{
- i2cinfo("short read N=2: DR and SR full setting stop bit and reading twice\n");
-
- /* Send Stop/Restart */
+ /* BTF: N-2/N-1, set NACK, read N-2 */
- if (priv->msgc > 0)
- {
- stm32_i2c_sendstart(priv);
- }
- else
+ if (priv->dcnt == 3)
{
- stm32_i2c_sendstop(priv);
+ stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0);
}
- *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET);
- priv->dcnt--;
- *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET);
- priv->dcnt--;
-
- /* Stop request already programmed so set dcnt for next message */
-
- priv->dcnt--;
-
- /* Set trace */
-
- stm32_i2c_traceevent(priv, I2CEVENT_READ_2, 0);
- }
+ /* BTF: N-1/N, STOP/START, read N-1, N */
-#ifndef CONFIG_STM32_I2C_DMA
- /* Case total message length >= 3 */
-
- else if (priv->dcnt >= 4 && priv->total_msg_len >= 3)
- {
- /* Read data from data register(DR). Note this clears the
- * RXNE(receive buffer not empty) flag.
- */
-
- i2cinfo("Read data from data register(DR)\n");
- *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET);
-
- /* Decrease current message length */
-
- priv->dcnt--;
- stm32_i2c_traceevent(priv, I2CEVENT_READ, 0);
- }
- else if (priv->dcnt == 3 && priv->total_msg_len >= 3 && !(status & I2C_SR1_BTF))
- {
- i2cinfo("short read N=3: DR full, SR empty. Waiting for more bytes.\n");
- stm32_i2c_traceevent(priv, I2CEVENT_READ_SR_EMPTY, 0);
- }
- else if (priv->dcnt == 3 && (status & I2C_SR1_BTF) && priv->total_msg_len >= 3)
- {
- /* This means that we are reading dcnt 3 and there is already dcnt 2 in
- * the shift register.
- * This coincides with EV7_1 in the reference manual.
- */
-
- i2cinfo("Program NACK\n");
- i2cinfo("Read data from data register(DR) dcnt=3\n");
-
- stm32_i2c_traceevent(priv, I2CEVENT_READ_3, priv->dcnt);
-
- /* Program NACK */
-
- stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0);
+ else if (priv->dcnt == 2)
+ {
+ if (priv->msgc > 0)
+ {
+ stm32_i2c_sendstart(priv);
+ }
+ else
+ {
+ stm32_i2c_sendstop(priv);
+ }
+
+ /* Read byte #N-1 */
+
+ *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET);
+ priv->dcnt--;
+ }
- /* Read dcnt = 3, to ensure a BTF event after having recieved
- * in the shift register.
- */
+ /* Read last or current byte */
*priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET);
-
- /* Decrease current message length */
-
priv->dcnt--;
- }
- else if (priv->dcnt == 2 && priv->total_msg_len >= 3 && !(status & I2C_SR1_BTF))
- {
- i2cinfo("short read N=3: DR full, SR empty. Waiting for more bytes.\n");
- stm32_i2c_traceevent(priv, I2CEVENT_READ_SR_EMPTY, 0);
- }
- else if (priv->dcnt == 2 && (status & I2C_SR1_BTF) && priv->total_msg_len >= 3)
- {
- i2cinfo("Program stop\n");
- i2cinfo("Read data from data register(DR) dcnt=2\n");
- i2cinfo("Read data from data register(SR) dcnt=1\n");
- i2cinfo("Setting condition to stop ISR dcnt = -1\n");
-
- stm32_i2c_traceevent(priv, I2CEVENT_READ_3, priv->dcnt);
- /* Program Stop/Restart */
-
- if (priv->msgc > 0)
+ if (priv->dcnt == 0)
{
- stm32_i2c_sendstart(priv);
+ priv->dcnt = -1;
}
- else
- {
- stm32_i2c_sendstop(priv);
- }
-
- /* read dcnt = 2 */
-
- *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET);
-
- /* read last byte dcnt=1 */
-
- *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET);
-
- /* Stop already sent will not get another interrupt set
- * condition to stop ISR
- */
-
- priv->dcnt = -1;
- }
-#endif /* CONFIG_STM32_I2C_DMA */
-
- /* Error handling for read mode */
-
- else
- {
- i2cinfo("I2C read mode no correct state detected\n");
- i2cinfo(" state %i, dcnt=%i\n", status, priv->dcnt);
-
- /* Set condition to terminate ISR and wake waiting thread */
-
- priv->dcnt = -1;
- priv->msgc = 0;
- stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0);
}
-
- /* Read rest of the state */
-
- status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16);
}
/* Empty call handler
@@ -2023,6 +1949,15 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16);
+ /* No any error bit is set, but driver is in incorrect state, signal
+ * it with "Bus error" bit.
+ */
+
+ if ((status & I2C_SR1_ERRORMASK) != 0)
+ {
+ priv->status |= I2C_SR1_BERR;
+ }
+
i2cinfo(" No correct state detected(start bit, read or write) \n");
i2cinfo(" state %i\n", status);
@@ -2049,7 +1984,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
/* Clear interrupt flags */
-#ifndef CONFIG_STM32_I2C_DMA
+#if !defined(CONFIG_STM32_I2C_DMA) && !defined(CONFIG_I2C_POLLED)
state_error:
#endif
stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0);
diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
index 8657d6e166728cb16b35cb25e43c89c2db167fff..460a3872d8729e6bcd9b06b48cb0801667bd05e2 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c
@@ -58,7 +58,7 @@
#include
-#ifdef CONFIG_RTC
+#if defined(CONFIG_RTC) && !defined(CONFIG_RTC_EXTERNAL)
/****************************************************************************
* Pre-processor Definitions
@@ -1659,4 +1659,5 @@ int stm32_rtc_rdalarm(FAR struct alm_rdalarm_s *alminfo)
}
#endif
-#endif /* CONFIG_RTC */
+#endif /* CONFIG_RTC && !CONFIG_RTC_EXTERNAL */
+
diff --git a/arch/arm/src/stm32f0/stm32f0_gpio.c b/arch/arm/src/stm32f0/stm32f0_gpio.c
index ffa77a43ecc7c7dcd7488760b7ce7b2f2a49d306..d6ee49b6e92aaba84cf22072dfade5db677204db 100644
--- a/arch/arm/src/stm32f0/stm32f0_gpio.c
+++ b/arch/arm/src/stm32f0/stm32f0_gpio.c
@@ -115,7 +115,7 @@ void stm32f0_gpioinit(void)
* function, it must be unconfigured with stm32f0_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
- * Returns:
+ * Returned Value:
* OK on success
* A negated errono valu on invalid port, or when pin is locked as ALT
* function.
@@ -336,7 +336,7 @@ int stm32f0_configgpio(uint32_t cfgset)
* operate in PWM mode could produce excessive on-board currents and trigger
* over-current/alarm function.
*
- * Returns:
+ * Returned Value:
* OK on success
* A negated errno value on invalid port
*
diff --git a/arch/arm/src/stm32f0/stm32f0_gpio.h b/arch/arm/src/stm32f0/stm32f0_gpio.h
index 4cbe0a40dff1058dc404b790d466f1af6e35f87d..14c95cce3f6d3bbf97055e2df1d2c6dd760f6b58 100644
--- a/arch/arm/src/stm32f0/stm32f0_gpio.h
+++ b/arch/arm/src/stm32f0/stm32f0_gpio.h
@@ -256,7 +256,7 @@ EXTERN const uint32_t g_gpiobase[STM32F0_NPORTS];
* function, it must be unconfigured with stm32f0_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
- * Returns:
+ * Returned Value:
* OK on success
* ERROR on invalid port, or when pin is locked as ALT function.
*
@@ -277,7 +277,7 @@ int stm32f0_configgpio(uint32_t cfgset);
* operate in PWM mode could produce excessive on-board currents and trigger
* over-current/alarm function.
*
- * Returns:
+ * Returned Value:
* OK on success
* ERROR on invalid port
*
diff --git a/arch/arm/src/stm32f0/stm32f0_i2c.h b/arch/arm/src/stm32f0/stm32f0_i2c.h
index 29bcbdccd1d920f4d89c8aad5bd7cf59c05f7b3f..dd127b788acf7bcc01733d8f3d333febc58703e4 100644
--- a/arch/arm/src/stm32f0/stm32f0_i2c.h
+++ b/arch/arm/src/stm32f0/stm32f0_i2c.h
@@ -74,7 +74,7 @@
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
@@ -90,7 +90,7 @@ FAR struct i2c_master_s *stm32f0_i2cbus_initialize(int port);
* Description:
* De-initialize the selected I2C port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the stm32f0_i2cbus_initialize()
*
* Returned Value:
diff --git a/arch/arm/src/stm32f0/stm32f0_serial.c b/arch/arm/src/stm32f0/stm32f0_serial.c
index 91d6cc9828b9469faeb0339f7d92108ba3a465ef..3231ebdf6de485bc6f46c760ef8057b9a5f6bd47 100644
--- a/arch/arm/src/stm32f0/stm32f0_serial.c
+++ b/arch/arm/src/stm32f0/stm32f0_serial.c
@@ -1033,7 +1033,7 @@ static void stm32f0serial_setformat(FAR struct uart_dev_s *dev)
* Description:
* Enable or disable APB clock for the USART peripheral
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the USART driver state structure
* on - Enable clock if 'on' is 'true' and disable if 'false'
*
@@ -1907,7 +1907,7 @@ static bool stm32f0serial_rxavailable(FAR struct uart_dev_s *dev)
* Return true if USART activated RX flow control to block more incoming
* data
*
- * Input parameters:
+ * Input Parameters:
* dev - USART device instance
* nbuffered - the number of characters currently buffered
* (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is
diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig
index 9e80a64934b48cf3070b84721cffe06a35735234..4f07188d09781fc28154483d036831990a6747b6 100644
--- a/arch/arm/src/stm32f7/Kconfig
+++ b/arch/arm/src/stm32f7/Kconfig
@@ -1430,6 +1430,7 @@ config STM32F7_SDMMC1
select ARCH_HAVE_SDIO
select ARCH_HAVE_SDIOWAIT_WRCOMPLETE
select SDIO_PREFLIGHT
+ select SDIO_BLOCKSETUP
config STM32F7_SDMMC2
bool "SDMMC2"
@@ -1439,6 +1440,7 @@ config STM32F7_SDMMC2
select ARCH_HAVE_SDIO
select ARCH_HAVE_SDIOWAIT_WRCOMPLETE
select SDIO_PREFLIGHT
+ select SDIO_BLOCKSETUP
config STM32F7_SPDIFRX
bool "SPDIFRX"
diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs
index ccb0fe66549f1d9f2fcba3e5e35de444c0ce983d..fb05fecf339a0498364acc7e53f0aa2c7b9dfdee 100644
--- a/arch/arm/src/stm32f7/Make.defs
+++ b/arch/arm/src/stm32f7/Make.defs
@@ -44,7 +44,7 @@ CMN_UASRCS =
CMN_UCSRCS =
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
-CMN_ASRCS += up_testset.S vfork.S
+CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S
CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c
CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_initialize.c
diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_memorymap.h b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_memorymap.h
index 669fd36abdb47a5baa6a8c32943192f099d65fda..c786506f768cbc62d706a2f5459f25416e9cb438 100644
--- a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_memorymap.h
+++ b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_memorymap.h
@@ -112,7 +112,6 @@
#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff: TIM14 */
#define STM32_LPTIM1_BASE 0x40002400 /* 0x40002400-0x400027ff: LPTIM1 */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
-#define STM32_BKP_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: IWDG */
#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff: SPI2 / I2S2 */
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h
index 89d5223845b90b011bb72eb2cf98ae685df73596..55b8481512b1bf2d861a16e372cc97fae09db45e 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h
+++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h
@@ -113,7 +113,6 @@
#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff: TIM14 */
#define STM32_LPTIM1_BASE 0x40002400 /* 0x40002400-0x400027ff: LPTIM1 */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
-#define STM32_BKP_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: IWDG */
#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff: SPI2 / I2S2 */
diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h
index 0c27a36e93cf8323cf2032bf812d1b9e9272bad8..6d988895e0d3ec8283416e0defd0ff8b1b912a87 100644
--- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h
+++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h
@@ -113,7 +113,6 @@
#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff: TIM14 */
#define STM32_LPTIM1_BASE 0x40002400 /* 0x40002400-0x400027ff: LPTIM1 */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
-#define STM32_BKP_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: IWDG */
#define STM32_CAN3_BASE 0x40003400 /* 0x40003400-0x400037ff: CAN3 */
diff --git a/arch/arm/src/stm32f7/stm32_adc.c b/arch/arm/src/stm32f7/stm32_adc.c
index 0d226ab46a3e462830b359bf2e52fa329af9a7e2..710209a2bf1558ffb98c97090d7e7dd213b9e708 100644
--- a/arch/arm/src/stm32f7/stm32_adc.c
+++ b/arch/arm/src/stm32f7/stm32_adc.c
@@ -568,7 +568,7 @@ static void tim_modifyreg(FAR struct stm32_dev_s *priv, int offset,
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the ADC block status
*
* Returned Value:
@@ -1082,9 +1082,9 @@ static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset)
/****************************************************************************
* Name: adc_enable
*
- * Description : Enables or disables the specified ADC peripheral.
- * Also, starts a conversion when the ADC is not
- * triggered by timers
+ * Description:
+ * Enables or disables the specified ADC peripheral. Also, starts a
+ * conversion when the ADC is not triggered by timers
*
* Input Parameters:
*
diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c
index a5d185944d547b5728037d867f7913287c5c4427..7a083e3239c7ca772ff7fc5002babad9f6b0dbf7 100644
--- a/arch/arm/src/stm32f7/stm32_dma.c
+++ b/arch/arm/src/stm32f7/stm32_dma.c
@@ -527,7 +527,7 @@ void weak_function up_dmainitialize(void)
* Hmm.. I suppose this interface could be extended to make a non-blocking
* version. Feel free to do that if that is what you need.
*
- * Input parameter:
+ * Input Parameters:
* dmamap - Identifies the stream/channel resource. For the STM32 F7, this
* is a bit-encoded value as provided by the DMAMAP_* definitions
* in chip/stm32f7xxxxxxx_dma.h
@@ -874,7 +874,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle)
* ccr.
* ccr - DMA stream configuration register
*
- * Returned value:
+ * Returned Value:
* True, if transfer is possible.
*
****************************************************************************/
diff --git a/arch/arm/src/stm32f7/stm32_dma.h b/arch/arm/src/stm32f7/stm32_dma.h
index e0494d538129693a0a9d1649ef97f67f486e9f5f..567e2330647a9ff517b9f94ebc370bed128befbe 100644
--- a/arch/arm/src/stm32f7/stm32_dma.h
+++ b/arch/arm/src/stm32f7/stm32_dma.h
@@ -135,7 +135,7 @@ extern "C"
* Hmm.. I suppose this interface could be extended to make a non-blocking
* version. Feel free to do that if that is what you need.
*
- * Input parameter:
+ * Input Parameters:
* chan - Identifies the stream/channel resource
* For the STM32 F7, this is a bit encoded value as provided by the
* the DMAMAP_* definitions in chip/stm32f7xxxxxxx_dma.h
@@ -248,7 +248,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle);
* ccr.
* ccr - DMA stream configuration register
*
- * Returned value:
+ * Returned Value:
* True, if transfer is possible.
*
****************************************************************************/
diff --git a/arch/arm/src/stm32f7/stm32_dma2d.c b/arch/arm/src/stm32f7/stm32_dma2d.c
index f0ec2123395195801555101cd0d75d126f4cd237..9e952d2ead31c401ca4421fff941f489f1885946 100644
--- a/arch/arm/src/stm32f7/stm32_dma2d.c
+++ b/arch/arm/src/stm32f7/stm32_dma2d.c
@@ -481,7 +481,7 @@ static int stm32_dma2dirq(int irq, void *context, FAR void *arg)
* loading or dma transfer was completed.
* Note! The caller must use this function within a critical section.
*
- * Return:
+ * Returned Value:
* On success OK otherwise ERROR
*
****************************************************************************/
@@ -526,7 +526,7 @@ static int stm32_dma2d_waitforirq(void)
* Parameter:
* pfcreg - PFC control Register
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -614,7 +614,7 @@ static int stm32_dma2d_start(void)
* Parameter:
* layer - Reference to the common layer state structure
*
- * Return:
+ * Returned Value:
* memory address
*
****************************************************************************/
@@ -640,7 +640,7 @@ static uint32_t stm32_dma2d_memaddress(FAR const struct stm32_dma2d_s *layer,
* Parameter:
* layer - Reference to the common layer state structure
*
- * Return:
+ * Returned Value:
* line offset
*
****************************************************************************/
@@ -664,7 +664,7 @@ static fb_coord_t stm32_dma2d_lineoffset(FAR const struct stm32_dma2d_s *layer,
* layer - Reference to the common layer state structure
* fmt - Reference to the location to store the pixel format
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -723,7 +723,7 @@ static int stm32_dma2d_pixelformat(uint8_t fmt, uint8_t *fmtmap)
* layer - Reference to the common layer state structure
* bpp - Reference to the location to store the pixel format
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -764,7 +764,7 @@ static int stm32_dma2d_bpp(uint8_t fmt, uint8_t *bpp)
* Description:
* Get a free layer id
*
- * Return:
+ * Returned Value:
* The number of the free layer
* -1 if no free layer is available
*
@@ -791,7 +791,7 @@ static int stm32_dma2d_lfreelid(void)
* Description:
* Allocate a new layer structure
*
- * Return:
+ * Returned Value:
* A new allocated layer structure or NULL on error.
*
****************************************************************************/
@@ -880,7 +880,7 @@ static void stm32_dma2d_llayerscleanup(void)
* Description:
* Helper to validate if the layer is valid
*
- * Return:
+ * Returned Value:
* true if validates otherwise false
*
****************************************************************************/
@@ -902,7 +902,7 @@ static inline bool stm32_dma2d_lvalidate(FAR const struct stm32_dma2d_s *layer)
* ypos - The y position inside the whole layer
* area - the area inside the whole layer
*
- * Return:
+ * Returned Value:
* true if area is inside the whole layer otherwise false
*
****************************************************************************/
@@ -1156,7 +1156,7 @@ static void stm32_dma2d_lpfc(FAR const struct stm32_dma2d_s *layer,
* layer - Reference to the layer control structure
* vinfo - Reference to the video info structure
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1193,7 +1193,7 @@ static int stm32_dma2dgetvideoinfo(FAR struct dma2d_layer_s *layer,
* planeno - Number of the plane
* pinfo - Reference to the plane info structure
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1229,7 +1229,7 @@ static int stm32_dma2dgetplaneinfo(FAR struct dma2d_layer_s *layer, int planeno,
* layer - Reference to the layer structure
* lid - Reference to store the layer id
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1265,7 +1265,7 @@ static int stm32_dma2dgetlid(FAR struct dma2d_layer_s *layer, int *lid)
* layer - Reference to the layer structure
* cmap - color lookup table with up the 256 entries
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1384,7 +1384,7 @@ static int stm32_dma2dsetclut(FAR struct dma2d_layer_s *layer,
* cmap - Reference to valid color lookup table accept up the 256 color
* entries
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1476,7 +1476,7 @@ static int stm32_dma2dgetclut(FAR struct dma2d_layer_s *layer,
* layer - Reference to the layer structure
* alpha - Alpha value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1511,7 +1511,7 @@ static int stm32_dma2dsetalpha(FAR struct dma2d_layer_s *layer, uint8_t alpha)
* layer - Reference to the layer structure
* alpha - Reference to store the alpha value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1548,7 +1548,7 @@ static int stm32_dma2dgetalpha(FAR struct dma2d_layer_s *layer, uint8_t *alpha)
* layer - Reference to the layer structure
* mode - Blend mode (see DMA2D_BLEND_*)
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1597,7 +1597,7 @@ static int stm32_dma2dsetblendmode(FAR struct dma2d_layer_s *layer,
* layer - Reference to the layer structure
* mode - Reference to store the blend mode
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1637,7 +1637,7 @@ static int stm32_dma2dgetblendmode(FAR struct dma2d_layer_s *layer,
* src - Valid reference to the source layer
* srcarea - Valid reference to the selected area of the source layer
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* source area outside the visible area of the destination layer.
@@ -1746,7 +1746,7 @@ static int stm32_dma2dblit(FAR struct dma2d_layer_s *dest,
* back - Reference to the background layer
* backarea - Reference to the selected area of the background layer
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* source area outside the visible area of the destination layer.
@@ -1853,7 +1853,7 @@ static int stm32_dma2dblend(FAR struct dma2d_layer_s *dest,
* color - Color to fill the selected area. Color must be formatted
* according to the layer pixel format.
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* area outside the visible area of the layer.
@@ -1929,7 +1929,7 @@ static int stm32_dma2dfillarea(FAR struct dma2d_layer_s *layer,
* Parameter:
* lid - Layer identifier
*
- * Return:
+ * Returned Value:
* Reference to the dma2d layer control structure on success or Null if no
* related exist.
*
@@ -1962,7 +1962,7 @@ FAR struct dma2d_layer_s *up_dma2dgetlayer(int lid)
* height - Layer height
* fmt - Pixel format of the layer
*
- * Return:
+ * Returned Value:
* On success - A valid dma2d layer reference
* On error - NULL
*
@@ -2082,7 +2082,7 @@ FAR struct dma2d_layer_s *up_dma2dcreatelayer(fb_coord_t width,
* Parameter:
* layer - Reference to the layer to remove
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2124,7 +2124,7 @@ int up_dma2dremovelayer(FAR struct dma2d_layer_s *layer)
* Description:
* Initialize the dma2d controller
*
- * Return:
+ * Returned Value:
* OK - On success
* An error if initializing failed.
*
@@ -2240,7 +2240,7 @@ void up_dma2duninitialize(void)
* layer - a valid reference to the low level ltdc layer structure
* clut - a pointer to a valid memory region to hold 256 clut colors
*
- * Return:
+ * Returned Value:
* On success - A valid dma2d layer reference
* On error - NULL
*
@@ -2261,7 +2261,6 @@ FAR struct dma2d_layer_s *stm32_dma2dinitltdc(FAR struct stm32_ltdc_s *layer)
{
lcderr("ERROR: Returning -EINVAL, unsupported pixel format: %d\n",
layer->vinfo.fmt);
- errno = -EINVAL;
return NULL;
}
diff --git a/arch/arm/src/stm32f7/stm32_dma2d.h b/arch/arm/src/stm32f7/stm32_dma2d.h
index 26d9f0faa8b63722de20fd70a05699b984d507f2..9ffc8289cd7f50531e70346b09ebde86a24c3155 100644
--- a/arch/arm/src/stm32f7/stm32_dma2d.h
+++ b/arch/arm/src/stm32f7/stm32_dma2d.h
@@ -74,7 +74,7 @@ struct dma2d_layer_s
* layer - Reference to the layer control structure
* vinfo - Reference to the video info structure
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -92,7 +92,7 @@ struct dma2d_layer_s
* planeno - Number of the plane
* pinfo - Reference to the plane info structure
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -109,7 +109,7 @@ struct dma2d_layer_s
* layer - Reference to the layer structure
* lid - Reference to store the layer id
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -127,7 +127,7 @@ struct dma2d_layer_s
* layer - Reference to the layer structure
* cmap - color lookup table with up the 256 entries
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -145,7 +145,7 @@ struct dma2d_layer_s
* cmap - Reference to valid color lookup table accept up the 256 color
* entries
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -167,7 +167,7 @@ struct dma2d_layer_s
* layer - Reference to the layer structure
* alpha - Alpha value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -183,7 +183,7 @@ struct dma2d_layer_s
* layer - Reference to the layer structure
* alpha - Reference to store the alpha value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -201,7 +201,7 @@ struct dma2d_layer_s
* layer - Reference to the layer structure
* mode - Blend mode (see DMA2D_BLEND_*)
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -230,7 +230,7 @@ struct dma2d_layer_s
* layer - Reference to the layer structure
* mode - Reference to store the blend mode
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -250,7 +250,7 @@ struct dma2d_layer_s
* src - Reference to the source layer
* srcarea - Reference to the selected area of the source layer
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the
* selected source area outside the visible area of the
@@ -281,7 +281,7 @@ struct dma2d_layer_s
* back - Reference to the background layer
* backarea - Reference to the selected area of the background layer
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the
* selected source area outside the visible area of the
@@ -308,7 +308,7 @@ struct dma2d_layer_s
* color - Color to fill the selected area. Color must be formatted
* according to the layer pixel format.
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the
* selected area outside the visible area of the layer.
@@ -340,7 +340,7 @@ struct stm32_ltdc_s; /* Forward declaration */
* Parameter:
* layer - a valid reference to the low level ltdc layer structure
*
- * Return:
+ * Returned Value:
* On success - A valid dma2d layer reference
* On error - NULL and errno is set to
* -EINVAL if one of the parameter is invalid
@@ -358,7 +358,7 @@ FAR struct dma2d_layer_s *stm32_dma2dinitltdc(FAR struct stm32_ltdc_s *layer);
* Parameter:
* lid - Layer identifier
*
- * Return:
+ * Returned Value:
* Reference to the dma2d layer control structure on success or Null if no
* related exist.
*
@@ -377,7 +377,7 @@ FAR struct dma2d_layer_s *up_dma2dgetlayer(int lid);
* height - Layer height
* fmt - Pixel format of the layer
*
- * Return:
+ * Returned Value:
* On success - A valid dma2d layer reference
* On error - NULL and errno is set to
* -EINVAL if one of the parameter is invalid
@@ -399,7 +399,7 @@ FAR struct dma2d_layer_s *up_dma2dcreatelayer(fb_coord_t width,
* Parameter:
* layer - Reference to the layer to remove
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -413,7 +413,7 @@ int up_dma2dremovelayer(FAR struct dma2d_layer_s *layer);
* Description:
* Initialize the dma2d controller
*
- * Return:
+ * Returned Value:
* OK - On success
* An error if initializing failed.
*
diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c
index 8c0eddd847ee3fefca621ef2be1000becf0def0e..d5337d8f48c86ad27a757348f7a163a6022b1614 100644
--- a/arch/arm/src/stm32f7/stm32_ethernet.c
+++ b/arch/arm/src/stm32f7/stm32_ethernet.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_ethernet.c
*
- * Copyright (C) 2015-2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -732,7 +732,7 @@ static int stm32_addmac(struct net_driver_s *dev, const uint8_t *mac);
#ifdef CONFIG_NET_IGMP
static int stm32_rmmac(struct net_driver_s *dev, const uint8_t *mac);
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
static int stm32_ioctl(struct net_driver_s *dev, int cmd,
unsigned long arg);
#endif
@@ -2958,16 +2958,17 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv,
*
****************************************************************************/
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
{
-#ifdef CONFIG_ARCH_PHY_INTERRUPT
+#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)dev->d_private;
#endif
int ret;
switch (cmd)
{
+#ifdef CONFIG_NETDEV_PHY_IOCTL
#ifdef CONFIG_ARCH_PHY_INTERRUPT
case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
@@ -3005,6 +3006,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
ret = stm32_phywrite(req->phy_id, req->reg_num, req->val_in);
}
break;
+#endif /* CONFIG_NETDEV_PHY_IOCTL */
default:
ret = -ENOTTY;
@@ -3013,7 +3015,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
return ret;
}
-#endif /* CONFIG_NETDEV_PHY_IOCTL */
+#endif /* CONFIG_NETDEV_IOCTL */
/****************************************************************************
* Function: stm32_phyintenable
@@ -4095,7 +4097,7 @@ int stm32_ethinitialize(int intf)
priv->dev.d_addmac = stm32_addmac; /* Add multicast MAC address */
priv->dev.d_rmmac = stm32_rmmac; /* Remove multicast MAC address */
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = stm32_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void *)g_stm32ethmac; /* Used to recover private state from dev */
diff --git a/arch/arm/src/stm32f7/stm32_exti_alarm.c b/arch/arm/src/stm32f7/stm32_exti_alarm.c
index 8fba01b53a4361a2ba34db6728b48e3a29009c92..552241b4907ce2366b9266cc8ad7593f3bf6d1d3 100644
--- a/arch/arm/src/stm32f7/stm32_exti_alarm.c
+++ b/arch/arm/src/stm32f7/stm32_exti_alarm.c
@@ -116,7 +116,7 @@ static int stm32_exti_alarm_isr(int irq, void *context, FAR void *arg)
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
- * Returns:
+ * Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
diff --git a/arch/arm/src/stm32f7/stm32_exti_pwr.c b/arch/arm/src/stm32f7/stm32_exti_pwr.c
index 3c4f2d07a3be4107326520c4e25a76a0bf0ef5f9..f521aaff24ebf9ae3a50bb42e30569177a64aa65 100644
--- a/arch/arm/src/stm32f7/stm32_exti_pwr.c
+++ b/arch/arm/src/stm32f7/stm32_exti_pwr.c
@@ -122,7 +122,7 @@ static int stm32_exti_pvd_isr(int irq, void *context, void *arg)
* - event: generate event when set
* - func: when non-NULL, generate interrupt
*
- * Returns:
+ * Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on
* failure.
*
diff --git a/arch/arm/src/stm32f7/stm32_exti_pwr.h b/arch/arm/src/stm32f7/stm32_exti_pwr.h
index 67e22d05ff8400fb6b14f351c19f09f9a724e7f8..90b0185d594f5f5e64189a55709295de91e51fa9 100644
--- a/arch/arm/src/stm32f7/stm32_exti_pwr.h
+++ b/arch/arm/src/stm32f7/stm32_exti_pwr.h
@@ -60,7 +60,7 @@
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
- * Returns:
+ * Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on
* failure.
*
diff --git a/arch/arm/src/stm32f7/stm32_gpio.c b/arch/arm/src/stm32f7/stm32_gpio.c
index e9b3f0d8a9ad0d5d4a3c387b6665b6614954f3d5..cf153dd48207fba5e0441271ff441903b47d892f 100644
--- a/arch/arm/src/stm32f7/stm32_gpio.c
+++ b/arch/arm/src/stm32f7/stm32_gpio.c
@@ -136,7 +136,7 @@ void stm32_gpioinit(void)
* function, it must be unconfigured with stm32_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
- * Returns:
+ * Returned Value:
* OK on success
* A negated errono value on invalid port, or when pin is locked as ALT
* function.
@@ -359,7 +359,7 @@ int stm32_configgpio(uint32_t cfgset)
* operate in PWM mode could produce excessive on-board currents and trigger
* over-current/alarm function.
*
- * Returns:
+ * Returned Value:
* OK on success
* A negated errno value on invalid port
*
diff --git a/arch/arm/src/stm32f7/stm32_i2c.h b/arch/arm/src/stm32f7/stm32_i2c.h
index c5608176387158c74c643c7d56f6c2606c1af5e6..e2223f53c8f16a7441a313287308d953858008dc 100644
--- a/arch/arm/src/stm32f7/stm32_i2c.h
+++ b/arch/arm/src/stm32f7/stm32_i2c.h
@@ -74,7 +74,7 @@
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
@@ -90,7 +90,7 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port);
* Description:
* De-initialize the selected I2C port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the stm32_i2cbus_initialize()
*
* Returned Value:
diff --git a/arch/arm/src/stm32f7/stm32_ltdc.c b/arch/arm/src/stm32f7/stm32_ltdc.c
index 3a992d928fad6ff71e94b686e2454a71390f4ec6..185a6ade19a9f35a550197c2e75ab43b1879b224 100644
--- a/arch/arm/src/stm32f7/stm32_ltdc.c
+++ b/arch/arm/src/stm32f7/stm32_ltdc.c
@@ -1168,7 +1168,7 @@ static int stm32_ltdcirq(int irq, void *context, FAR void *arg)
* that a register reload was been completed.
* Note! The caller must use this function within a critical section.
*
- * Return:
+ * Returned Value:
* OK - On success otherwise ERROR
*
****************************************************************************/
@@ -1467,7 +1467,7 @@ static inline uint8_t stm32_ltdc_lgetopac(FAR struct stm32_layer_s *layer)
* Parameter:
* layer - Reference to the layer control structure
*
- * Return:
+ * Returned Value:
* true - layer valid
* false - layer invalid
*
@@ -1497,7 +1497,7 @@ static inline bool stm32_ltdc_lvalidate(FAR const struct stm32_layer_s *layer)
* srcxpos - Top left x position from where data visible in the active area
* srcypos - Top left y position from where data visible in the active area
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -1959,7 +1959,7 @@ static void stm32_ltdc_lenable(FAR struct stm32_layer_s *layer)
}
/****************************************************************************
- * Name stm32_ltdc_lclear
+ * Name: stm32_ltdc_lclear
*
* Description:
* Clear the whole layer
@@ -1968,7 +1968,7 @@ static void stm32_ltdc_lenable(FAR struct stm32_layer_s *layer)
* layer - Reference to the layer control structure
* color - The color to clear
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid
*
@@ -2182,7 +2182,7 @@ static void stm32_ltdc_linit(int lid)
* vtable - The framebuffer driver object
* vinfo - the videoinfo object
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2217,7 +2217,7 @@ static int stm32_getvideoinfo(struct fb_vtable_s *vtable,
* vtable - The framebuffer driver object
* pinfo - the planeinfo object
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2252,7 +2252,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno,
* vtable - The framebuffer driver object
* cmap - the color table
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2279,7 +2279,7 @@ static int stm32_getcmap(struct fb_vtable_s *vtable,
* vtable - The framebuffer driver object
* cmap - the color table
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2306,7 +2306,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable,
* layer - Reference to the layer control structure
* vinfo - Reference to the video info structure
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2340,7 +2340,7 @@ static int stm32_lgetvideoinfo(struct ltdc_layer_s *layer,
* planeno - Number of the plane
* pinfo - Reference to the plane info structure
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2374,7 +2374,7 @@ static int stm32_lgetplaneinfo(struct ltdc_layer_s *layer, int planeno,
* layer - Reference to the layer structure
* cmap - color lookup table with up the 256 entries
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2434,7 +2434,7 @@ static int stm32_setclut(struct ltdc_layer_s *layer,
* cmap - Reference to valid color lookup table accept up the 256 color
* entries
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2533,7 +2533,7 @@ static int stm32_getclut(struct ltdc_layer_s *layer,
* e.g. get the current active or inactive layer.
* See LTDC_LAYER_* for possible values
*
- * Return:
+ * Returned Value:
* OK - On success
* Null if invalid flag
*
@@ -2610,7 +2610,7 @@ static int stm32_getlid(FAR struct ltdc_layer_s *layer, int *lid,
* layer - Reference to the layer structure
* argb - ARGB8888 color value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2646,7 +2646,7 @@ static int stm32_setcolor(FAR struct ltdc_layer_s *layer, uint32_t argb)
* layer - Reference to the layer structure
* argb - Reference to store the ARGB8888 color value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2683,7 +2683,7 @@ static int stm32_getcolor(FAR struct ltdc_layer_s *layer, uint32_t *argb)
* layer - Reference to the layer structure
* rgb - RGB888 color value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2719,7 +2719,7 @@ static int stm32_setcolorkey(FAR struct ltdc_layer_s *layer, uint32_t rgb)
* layer - Reference to the layer structure
* rgb - Reference to store the RGB888 color key
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2760,7 +2760,7 @@ static int stm32_getcolorkey(FAR struct ltdc_layer_s *layer, uint32_t *rgb)
* layer - Reference to the layer structure
* alpha - Alpha value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2796,7 +2796,7 @@ static int stm32_setalpha(FAR struct ltdc_layer_s *layer, uint8_t alpha)
* layer - Reference to the layer structure
* alpha - Reference to store the alpha value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2833,7 +2833,7 @@ static int stm32_getalpha(FAR struct ltdc_layer_s *layer, uint8_t *alpha)
* layer - Reference to the layer structure
* mode - Blend mode (see LTDC_BLEND_*)
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -2965,7 +2965,7 @@ static int stm32_setblendmode(FAR struct ltdc_layer_s *layer, uint32_t mode)
* layer - Reference to the layer structure
* mode - Reference to store the blend mode
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
****************************************************************************/
@@ -3004,7 +3004,7 @@ static int stm32_getblendmode(FAR struct ltdc_layer_s *layer, uint32_t *mode)
* srcxpos - x position of the visible pixel of the whole layer
* srcypos - y position of the visible pixel of the whole layer
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -3066,7 +3066,7 @@ static int stm32_setarea(FAR struct ltdc_layer_s *layer,
* srcxpos - Reference to store the referenced x position of the whole layer
* srcypos - Reference to store the reterenced y position of the whole layer
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -3106,7 +3106,7 @@ static int stm32_getarea(FAR struct ltdc_layer_s *layer,
* layer - Reference to the layer structure
* mode - operation mode
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid
* -ECANCELED - Operation cancelled, something goes wrong
@@ -3269,7 +3269,7 @@ static int stm32_update(FAR struct ltdc_layer_s *layer, uint32_t mode)
* src - Reference to the source layer
* srcarea - Reference to the selected area of the source layer
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* source area outside the visible area of the destination layer.
@@ -3320,7 +3320,7 @@ static int stm32_blit(FAR struct ltdc_layer_s *dest,
* back - Reference to the background layer
* backarea - Reference to the selected area of the background layer
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* source area outside the visible area of the destination layer.
@@ -3370,7 +3370,7 @@ static int stm32_blend(FAR struct ltdc_layer_s *dest,
* color - Color to fill the selected area. Color must be formatted
* according to the layer pixel format.
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* area outside the visible area of the layer.
@@ -3412,7 +3412,7 @@ static int stm32_fillarea(FAR struct ltdc_layer_s *layer,
* Parameter:
* lid - Layer identifier
*
- * Return:
+ * Returned Value:
* Reference to the layer control structure on success or Null if lid
* is invalid.
*
@@ -3452,7 +3452,7 @@ void stm32_ltdcreset(void)
* Description:
* Initialize the ltdc controller
*
- * Return:
+ * Returned Value:
* OK
*
****************************************************************************/
@@ -3541,10 +3541,10 @@ int stm32_ltdcinitialize(void)
* Return a a reference to the framebuffer object for the specified video
* plane.
*
- * Input parameters:
+ * Input Parameters:
* None
*
- * Returned value:
+ * Returned Value:
* Reference to the framebuffer object (NULL on failure)
*
****************************************************************************/
diff --git a/arch/arm/src/stm32f7/stm32_ltdc.h b/arch/arm/src/stm32f7/stm32_ltdc.h
index 8b3593e86da3e41f81cf289861d4b805301dafcb..c2226ec43ef3a9a84e5b0db8678ab3a44b07142f 100644
--- a/arch/arm/src/stm32f7/stm32_ltdc.h
+++ b/arch/arm/src/stm32f7/stm32_ltdc.h
@@ -125,7 +125,7 @@ struct ltdc_layer_s
* layer - Reference to the layer control structure
* vinfo - Reference to the video info structure
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -143,7 +143,7 @@ struct ltdc_layer_s
* planeno - Number of the plane
* pinfo - Reference to the plane info structure
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -163,7 +163,7 @@ struct ltdc_layer_s
* e.g. get the current active or inactive layer.
* See LTDC_LAYER_* for possible values
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -184,7 +184,7 @@ struct ltdc_layer_s
* enable - Enable or disable clut support (if false cmap is ignored and can
* be NULL)
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -202,7 +202,7 @@ struct ltdc_layer_s
* cmap - Reference to valid color lookup table accept up the 256 color
* entries
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -221,7 +221,7 @@ struct ltdc_layer_s
* layer - Reference to the layer structure
* argb - ARGB8888 color value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -237,7 +237,7 @@ struct ltdc_layer_s
* layer - Reference to the layer structure
* argb - Reference to store the ARGB8888 color value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -255,7 +255,7 @@ struct ltdc_layer_s
* layer - Reference to the layer structure
* rgb - RGB888 color key
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -271,7 +271,7 @@ struct ltdc_layer_s
* layer - Reference to the layer structure
* rgb - Reference to store the RGB888 color key
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -293,7 +293,7 @@ struct ltdc_layer_s
* layer - Reference to the layer structure
* alpha - Alpha value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -309,7 +309,7 @@ struct ltdc_layer_s
* layer - Reference to the layer structure
* alpha - Reference to store the alpha value
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -327,7 +327,7 @@ struct ltdc_layer_s
* layer - Reference to the layer structure
* mode - Blend mode (see LTDC_BLEND_*)
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -365,7 +365,7 @@ struct ltdc_layer_s
* layer - Reference to the layer structure
* mode - Reference to store the blend mode
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -392,7 +392,7 @@ struct ltdc_layer_s
* srcxpos - x position of the visible pixel of the whole layer
* srcypos - y position of the visible pixel of the whole layer
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*
@@ -418,7 +418,7 @@ struct ltdc_layer_s
* srcxpos - Reference to store the referenced x position of the whole layer
* srcypos - Reference to store the reterenced y position of the whole layer
*
- * Return:
+ * Returned Value:
* On success - OK
* On error - -EINVAL
*/
@@ -437,7 +437,7 @@ struct ltdc_layer_s
* layer - Reference to the layer structure
* mode - operation mode (see LTDC_UPDATE_*)
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid
* -ECANCELED - Operation cancelled, something goes wrong
@@ -481,7 +481,7 @@ struct ltdc_layer_s
* src - Reference to the source layer
* srcarea - Reference to the selected area of the source layer
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* source area outside the visible area of the destination layer.
@@ -510,7 +510,7 @@ struct ltdc_layer_s
* back - Reference to the background layer
* backarea - Reference to the selected area of the background layer
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* source area outside the visible area of the destination layer.
@@ -535,7 +535,7 @@ struct ltdc_layer_s
* color - Color to fill the selected area. Color must be formatted
* according to the layer pixel format.
*
- * Return:
+ * Returned Value:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* area outside the visible area of the layer.
@@ -609,7 +609,7 @@ struct stm32_ltdc_s
* Description:
* Initialize the ltdc controller
*
- * Return:
+ * Returned Value:
* OK
*
************************************************************************************/
@@ -627,7 +627,7 @@ void stm32_ltdcuninitialize(void);
* Parameter:
* lid - Layer identifier
*
- * Return:
+ * Returned Value:
* Reference to the layer control structure on success or Null if parameter
* invalid.
*
diff --git a/arch/arm/src/stm32f7/stm32_otghost.c b/arch/arm/src/stm32f7/stm32_otghost.c
index 548a6f393de2f17754528ee12af09d06024919c5..1a9b8c1feac796e1aa21a129dc81688f8ae8b983 100644
--- a/arch/arm/src/stm32f7/stm32_otghost.c
+++ b/arch/arm/src/stm32f7/stm32_otghost.c
@@ -1265,7 +1265,7 @@ static int stm32_ctrlchan_alloc(FAR struct stm32_usbhost_s *priv,
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value
* is returned indicating the nature of the failure
*
@@ -1327,7 +1327,7 @@ static int stm32_ctrlep_alloc(FAR struct stm32_usbhost_s *priv,
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value
* is returned indicating the nature of the failure
*
@@ -3819,7 +3819,7 @@ static void stm32_txfe_enable(FAR struct stm32_usbhost_s *priv, int chidx)
* hport - The location to return the hub port descriptor that detected the
* connection related event.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success when a device in connected or
* disconnected. This function will not return until either (1) a device is
* connected or disconnect to/from any hub port or until (2) some failure
@@ -3910,7 +3910,7 @@ static int stm32_wait(FAR struct usbhost_connection_s *conn,
* hport - The descriptor of the hub port that has the newly connected
* device.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4040,7 +4040,7 @@ static int stm32_enumerate(FAR struct usbhost_connection_s *conn,
* maxpacketsize - The maximum number of bytes that can be sent to or
* received from the endpoint in a single data packet
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4099,7 +4099,7 @@ static int stm32_ep0configure(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4155,7 +4155,7 @@ static int stm32_epalloc(FAR struct usbhost_driver_s *drvr,
* the class create() method.
* ep - The endpoint to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4223,7 +4223,7 @@ static int stm32_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
* maxlen - The address of a memory location provided by the caller in which to
* return the maximum size of the allocated buffer memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4269,7 +4269,7 @@ static int stm32_alloc(FAR struct usbhost_driver_s *drvr,
* the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4305,7 +4305,7 @@ static int stm32_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer)
* return the allocated buffer memory address.
* buflen - The size of the buffer required.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4349,7 +4349,7 @@ static int stm32_ioalloc(FAR struct usbhost_driver_s *drvr,
* the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4392,7 +4392,7 @@ static int stm32_iofree(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer)
* NOTE: On an IN transaction, req and buffer may refer to the same allocated
* memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4595,7 +4595,7 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
* (IN endpoint). buffer must have been allocated using DRVR_ALLOC
* buflen - The length of the data to be sent or received.
*
- * Returned Values:
+ * Returned Value:
* On success, a non-negative value is returned that indicates the number
* of bytes successfully transferred. On a failure, a negated errno value is
* returned that indicates the nature of the failure:
@@ -4667,7 +4667,7 @@ static ssize_t stm32_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep
* arg - The arbitrary parameter that will be passed to the callback function
* when the transfer completes.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4723,7 +4723,7 @@ static int stm32_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
* ep - The IN or OUT endpoint descriptor for the device endpoint on which an
* asynchronous transfer should be transferred.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -4812,7 +4812,7 @@ static int stm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
* related event
* connected - True: device connected; false: device disconnected
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -4864,7 +4864,7 @@ static int stm32_connect(FAR struct usbhost_driver_s *drvr,
* hport - The port from which the device is being disconnected. Might be a port
* on a hub.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
diff --git a/arch/arm/src/stm32f7/stm32_pwr.c b/arch/arm/src/stm32f7/stm32_pwr.c
index c9d2d5dae44159523fb02e629f6873d56350c284..573796a78805d24bb062c841d8be1cf5fe26bad0 100644
--- a/arch/arm/src/stm32f7/stm32_pwr.c
+++ b/arch/arm/src/stm32f7/stm32_pwr.c
@@ -200,7 +200,7 @@ void stm32_pwr_enablebkp(bool writable)
* Input Parameters:
* regon - state to set it to
*
- * Returned Values:
+ * Returned Value:
* None
*
************************************************************************************/
@@ -229,7 +229,7 @@ void stm32_pwr_enablebreg(bool regon)
* Input Parameters:
* vos - Properly aligned voltage scaling select bits for the PWR_CR register.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
@@ -264,7 +264,7 @@ void stm32_pwr_setvos(uint16_t vos)
* Input Parameters:
* pls - PVD level
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
diff --git a/arch/arm/src/stm32f7/stm32_pwr.h b/arch/arm/src/stm32f7/stm32_pwr.h
index c80de12ae1707689cd498cd13275af2dda22edd2..b332e424a0deb2cd595c6f4fb936511245a707bb 100644
--- a/arch/arm/src/stm32f7/stm32_pwr.h
+++ b/arch/arm/src/stm32f7/stm32_pwr.h
@@ -119,7 +119,7 @@ void stm32_pwr_enablebkp(bool writable);
* Input Parameters:
* regon - state to set it to
*
- * Returned Values:
+ * Returned Value:
* None
*
************************************************************************************/
diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c
index e6168ad6631e788c5025279f33eb108bf01fd421..86481dd42fb4d593d77778c5b3e4b677a09737bc 100644
--- a/arch/arm/src/stm32f7/stm32_sdmmc.c
+++ b/arch/arm/src/stm32f7/stm32_sdmmc.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_sdmmc.c
*
- * Copyright (C) 2009, 2011-2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009, 2011-2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt
* David Sidrane
*
@@ -388,6 +388,10 @@ struct stm32_dev_s
bool dmamode; /* true: DMA mode transfer */
DMA_HANDLE dma; /* Handle for DMA channel */
#endif
+
+ /* Misc */
+
+ uint32_t blocksize; /* Current block size */
};
/* Register logging support */
@@ -421,8 +425,8 @@ struct stm32_sampleregs_s
/* Low-level helpers ********************************************************/
-static inline void sdmmc_putreg32(struct stm32_dev_s *priv, uint32_t value,\
- int offset);
+static inline void sdmmc_putreg32(struct stm32_dev_s *priv, uint32_t value,
+ int offset);
static inline uint32_t sdmmc_getreg32(struct stm32_dev_s *priv, int offset);
static void stm32_takesem(struct stm32_dev_s *priv);
#define stm32_givesem(priv) (nxsem_post(&priv->waitsem))
@@ -438,7 +442,7 @@ static inline uint32_t stm32_getpwrctrl(struct stm32_dev_s *priv);
#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG
static void stm32_sampleinit(void);
static void stm32_sdiosample(struct stm32_dev_s *priv,
- struct stm32_sdioregs_s *regs);
+ struct stm32_sdioregs_s *regs);
static void stm32_sample(struct stm32_dev_s *priv, int index);
static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg);
static void stm32_dumpsample(struct stm32_dev_s *priv,
@@ -458,13 +462,15 @@ static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg);
static uint8_t stm32_log2(uint16_t value);
static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout,
- uint32_t dlen, uint32_t dctrl);
+ uint32_t dlen, uint32_t dctrl);
static void stm32_datadisable(struct stm32_dev_s *priv);
static void stm32_sendfifo(struct stm32_dev_s *priv);
static void stm32_recvfifo(struct stm32_dev_s *priv);
static void stm32_eventtimeout(int argc, uint32_t arg);
-static void stm32_endwait(struct stm32_dev_s *priv, sdio_eventset_t wkupevent);
-static void stm32_endtransfer(struct stm32_dev_s *priv, sdio_eventset_t wkupevent);
+static void stm32_endwait(struct stm32_dev_s *priv,
+ sdio_eventset_t wkupevent);
+static void stm32_endtransfer(struct stm32_dev_s *priv,
+ sdio_eventset_t wkupevent);
/* Interrupt Handling *******************************************************/
@@ -495,6 +501,8 @@ static int stm32_attach(FAR struct sdio_dev_s *dev);
static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd,
uint32_t arg);
+static void stm32_blocksetup(FAR struct sdio_dev_s *dev,
+ unsigned int blocksize, unsigned int nblocks);
static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
size_t nbytes);
static int stm32_sendsetup(FAR struct sdio_dev_s *dev,
@@ -543,6 +551,7 @@ static void stm32_default(struct stm32_dev_s *priv);
/****************************************************************************
* Private Data
****************************************************************************/
+
#ifdef CONFIG_STM32F7_SDMMC1
struct stm32_dev_s g_sdmmcdev1 =
{
@@ -558,9 +567,7 @@ struct stm32_dev_s g_sdmmcdev1 =
.clock = stm32_clock,
.attach = stm32_attach,
.sendcmd = stm32_sendcmd,
-#ifdef CONFIG_SDIO_BLOCKSETUP
- .blocksetup = stm32_blocksetup, /* Not implemented yet */
-#endif
+ .blocksetup = stm32_blocksetup,
.recvsetup = stm32_recvsetup,
.sendsetup = stm32_sendsetup,
.cancel = stm32_cancel,
@@ -620,9 +627,7 @@ struct stm32_dev_s g_sdmmcdev2 =
.clock = stm32_clock,
.attach = stm32_attach,
.sendcmd = stm32_sendcmd,
-#ifdef CONFIG_SDIO_BLOCKSETUP
- .blocksetup = stm32_blocksetup, /* Not implemented yet */
-#endif
+ .blocksetup = stm32_blocksetup,
.recvsetup = stm32_recvsetup,
.sendsetup = stm32_sendsetup,
.cancel = stm32_cancel,
@@ -1433,6 +1438,19 @@ static void stm32_endwait(struct stm32_dev_s *priv, sdio_eventset_t wkupevent)
static void stm32_endtransfer(struct stm32_dev_s *priv,
sdio_eventset_t wkupevent)
{
+ /* Disable the DTEN bit (it should not be left set after previous read when
+ * the next write initialization starts).
+ */
+
+#if 1
+ sdmmc_putreg32(priv,
+ sdmmc_getreg32(priv, STM32_SDMMC_DCTRL_OFFSET) &
+ ~STM32_SDMMC_DCTRL_DTEN,
+ STM32_SDMMC_DCTRL_OFFSET);
+#else
+ stm32_datadisable(priv);
+#endif
+
/* Disable all transfer related interrupts */
stm32_configxfrints(priv, 0);
@@ -2057,6 +2075,30 @@ static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg)
return OK;
}
+/****************************************************************************
+ * Name: stm32_blocksetup
+ *
+ * Description:
+ * Configure block size and the number of blocks for next transfer.
+ *
+ * Input Parameters:
+ * dev - An instance of the SDIO device interface.
+ * blocksize - The selected block size.
+ * nblocks - The number of blocks to transfer.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void stm32_blocksetup(FAR struct sdio_dev_s *dev, unsigned int blocksize,
+ unsigned int nblocks)
+{
+ struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+
+ priv->blocksize = blocksize;
+}
+
/****************************************************************************
* Name: stm32_recvsetup
*
@@ -2103,7 +2145,7 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
/* Then set up the SDIO data path */
- dblocksize = stm32_log2(nbytes) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT;
+ dblocksize = stm32_log2(priv->blocksize) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT;
stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT, nbytes, dblocksize |
STM32_SDMMC_DCTRL_DTDIR);
@@ -2158,7 +2200,7 @@ static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const
/* Then set up the SDIO data path */
- dblocksize = stm32_log2(nbytes) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT;
+ dblocksize = stm32_log2(priv->blocksize) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT;
stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT, nbytes, dblocksize);
/* Enable TX interrupts */
@@ -2649,7 +2691,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay, (wdentry_t)stm32_eventtimeout,
1, (uint32_t)priv);
- if (ret != OK)
+ if (ret < 0)
{
mcerr("ERROR: wd_start failed: %d\n", ret);
}
@@ -2882,7 +2924,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
/* Then set up the SDIO data path */
- dblocksize = stm32_log2(buflen) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT;
+ dblocksize = stm32_log2(priv->blocksize) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT;
stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT, buflen, dblocksize |
STM32_SDMMC_DCTRL_DTDIR);
@@ -2975,7 +3017,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
/* Then set up the SDIO data path */
- dblocksize = stm32_log2(buflen) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT;
+ dblocksize = stm32_log2(priv->blocksize) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT;
stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT, buflen, dblocksize);
/* Configure the TX DMA */
@@ -3115,7 +3157,7 @@ static void stm32_default(struct stm32_dev_s *priv)
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
@@ -3251,7 +3293,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -3298,7 +3340,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is writeprotected.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.h b/arch/arm/src/stm32f7/stm32_sdmmc.h
index 8e722497c5f296141a7fd40b87f4c581c0806c5a..095af548052f433d5f9f6f70f393f4d0de9c3ec2 100644
--- a/arch/arm/src/stm32f7/stm32_sdmmc.h
+++ b/arch/arm/src/stm32f7/stm32_sdmmc.h
@@ -72,7 +72,7 @@ extern "C"
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
@@ -94,7 +94,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno);
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -112,7 +112,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is writeprotected.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c
index 3f639e178ef302d4e824be6427490285c20515a1..ba6edead3016e2f3ef828ed96f25b1b5f4d68ef1 100644
--- a/arch/arm/src/stm32f7/stm32_serial.c
+++ b/arch/arm/src/stm32f7/stm32_serial.c
@@ -1369,7 +1369,7 @@ static void up_set_format(struct uart_dev_s *dev)
* Description:
* Enable or disable APB clock for the USART peripheral
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the UART driver state structure
* on - Enable clock if 'on' is 'true' and disable if 'false'
*
@@ -2235,7 +2235,7 @@ static bool up_rxavailable(struct uart_dev_s *dev)
* Return true if UART activated RX flow control to block more incoming
* data
*
- * Input parameters:
+ * Input Parameters:
* dev - UART device instance
* nbuffered - the number of characters currently buffered
* (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is
diff --git a/arch/arm/src/stm32f7/stm32_spi.c b/arch/arm/src/stm32f7/stm32_spi.c
index 8ddf22bd3a004b54ea7e7947ac9b3e4873cd8403..cd1dc679893c6159f57090205a3df5cdbb405389 100644
--- a/arch/arm/src/stm32f7/stm32_spi.c
+++ b/arch/arm/src/stm32f7/stm32_spi.c
@@ -36,7 +36,7 @@
/************************************************************************************
* The external functions, stm32_spi1/2/3/4/5/6select and stm32_spi1/2/3/4/5/6status
- * must be * provided by board-specific logic. They are implementations of the select
+ * must be provided by board-specific logic. They are implementations of the select
* and status methods of the SPI interface defined by struct spi_ops_s (see
* include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize())
* are provided by common STM32 logic. To use this common SPI logic on your
@@ -1190,6 +1190,9 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev;
uint16_t setbits;
uint16_t clrbits;
+#ifdef CONFIG_STM32F7_SPI_DMA
+ uint16_t cr2bits;
+#endif
spiinfo("mode=%d\n", mode);
@@ -1225,9 +1228,39 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
return;
}
+ /* Disable SPI then change mode */
+
spi_modifycr1(priv, 0, SPI_CR1_SPE);
spi_modifycr1(priv, setbits, clrbits);
+
+#ifdef CONFIG_STM32F7_SPI_DMA
+ /* Enabling SPI causes a spurious received character indication
+ * which confuse the DMA controller so we disable DMA during that
+ * enabling; and flush the SPI RX FIFO before re-enabling DMA.
+ */
+
+ cr2bits = spi_getreg(priv, STM32_SPI_CR2_OFFSET);
+ spi_modifycr2(priv, 0, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN);
+#endif
+
+ /* Re-enable SPI */
+
+ spi_modifycr1(priv, SPI_CR1_SPE, 0);
+ while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_FRLVL_MASK) != 0)
+ {
+ /* Flush SPI read FIFO */
+
+ spi_getreg(priv, STM32_SPI_DR_OFFSET);
+ }
+
+#ifdef CONFIG_STM32F7_SPI_DMA
+
+ /* Re-enable DMA (with SPI disabled) */
+
+ spi_modifycr1(priv, 0, SPI_CR1_SPE);
+ spi_modifycr2(priv, cr2bits & (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN), 0);
spi_modifycr1(priv, SPI_CR1_SPE, 0);
+#endif
/* Save the mode so that subsequent re-configurations will be faster */
@@ -1666,7 +1699,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, size_t
* Description:
* Initialize the selected SPI bus in its default state (Master, 8-bit, mode 0, etc.)
*
- * Input Parameter:
+ * Input Parameters:
* priv - private SPI device structure
*
* Returned Value:
@@ -1755,7 +1788,7 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv)
* Description:
* Initialize the selected SPI bus
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/stm32f7/stm32_spi.h b/arch/arm/src/stm32f7/stm32_spi.h
index 27751073564b3364ffe6cb15bb1ed9df2ad7f26e..f8c1ee9a1fc2dd644b2cc189aa24eb8a5974576e 100644
--- a/arch/arm/src/stm32f7/stm32_spi.h
+++ b/arch/arm/src/stm32f7/stm32_spi.h
@@ -71,7 +71,7 @@ struct spi_dev_s; /* Forward reference */
* Description:
* Initialize the selected SPI bus
*
- * Input Parameter:
+ * Input Parameters:
* bus number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/stm32f7/stm32_tim.h b/arch/arm/src/stm32f7/stm32_tim.h
index 5f3bf82c1002d61ccb4f46768ba84259f0a0262b..06d7fe8e841035adaab4c793af900871783f49e8 100644
--- a/arch/arm/src/stm32f7/stm32_tim.h
+++ b/arch/arm/src/stm32f7/stm32_tim.h
@@ -196,7 +196,7 @@ int stm32_tim_deinit(FAR struct stm32_tim_dev_s *dev);
* devpath - The full path to the timer device. This should be of the form /dev/timer0
* timer - the timer number.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
diff --git a/arch/arm/src/stm32l4/stm32l4_adc.c b/arch/arm/src/stm32l4/stm32l4_adc.c
index 56a9ae81d769756417303db54d56d21a63b5174a..ada9f4d8791639036a11b66359417ec50d4cdd05 100644
--- a/arch/arm/src/stm32l4/stm32l4_adc.c
+++ b/arch/arm/src/stm32l4/stm32l4_adc.c
@@ -592,7 +592,7 @@ static void tim_modifyreg(FAR struct stm32_dev_s *priv, int offset,
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the ADC block status
*
* Returned Value:
@@ -1145,7 +1145,8 @@ static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset)
/****************************************************************************
* Name: adc_enable
*
- * Description : Enables the specified ADC peripheral.
+ * Description:
+ * Enables the specified ADC peripheral.
*
* Input Parameters:
* priv - A reference to the ADC block status
diff --git a/arch/arm/src/stm32l4/stm32l4_can.c b/arch/arm/src/stm32l4/stm32l4_can.c
index 7667481c6cd31c982f8725ffaa211474c219ecb8..2bc5dcd2e6062cc00953548c8d155770aa782a48 100644
--- a/arch/arm/src/stm32l4/stm32l4_can.c
+++ b/arch/arm/src/stm32l4/stm32l4_can.c
@@ -1627,7 +1627,7 @@ static int stm32l4can_txinterrupt(int irq, FAR void *context, FAR void *arg)
* Where:
* Tpclk1 is the period of the APB1 clock (PCLK1).
*
- * Input Parameter:
+ * Input Parameters:
* priv - A reference to the CAN block status
*
* Returned Value:
@@ -1726,7 +1726,7 @@ static int stm32l4can_bittiming(FAR struct stm32l4_can_s *priv)
* peripheral, no registers are changed. The initialization mode is
* required to change the baud rate.
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN block
*
* Returned Value:
@@ -1777,7 +1777,7 @@ static int stm32l4can_enterinitmode(FAR struct stm32l4_can_s *priv)
* Description:
* Put the CAN cell out of the Initialization mode (to Normal mode)
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN block
*
* Returned Value:
@@ -1827,7 +1827,7 @@ static int stm32l4can_exitinitmode(FAR struct stm32l4_can_s *priv)
* Description:
* CAN cell initialization
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN block
*
* Returned Value:
@@ -1905,7 +1905,7 @@ static int stm32l4can_cellinit(FAR struct stm32l4_can_s *priv)
* are set to zero thus supressing all filtering because anything masked
* with zero matches zero.
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN block
*
* Returned Value:
@@ -1981,7 +1981,7 @@ static int stm32l4can_filterinit(FAR struct stm32l4_can_s *priv)
* Description:
* Add a filter for extended CAN IDs
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN block
* arg - A pointer to a structure describing the filter
*
@@ -2006,7 +2006,7 @@ static int stm32l4can_addextfilter(FAR struct stm32l4_can_s *priv,
* Description:
* Remove a filter for extended CAN IDs
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN block
* arg - The filter index previously returned by the
* CANIOC_ADD_EXTFILTER command
@@ -2031,7 +2031,7 @@ static int stm32l4can_delextfilter(FAR struct stm32l4_can_s *priv, int arg)
* Description:
* Add a filter for standard CAN IDs
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN block
* arg - A pointer to a structure describing the filter
*
@@ -2054,7 +2054,7 @@ static int stm32l4can_addstdfilter(FAR struct stm32l4_can_s *priv,
* Description:
* Remove a filter for standard CAN IDs
*
- * Input Parameter:
+ * Input Parameters:
* priv - A pointer to the private data structure for this CAN block
* arg - The filter index previously returned by the
* CANIOC_ADD_STDFILTER command
@@ -2081,7 +2081,7 @@ static int stm32l4can_delstdfilter(FAR struct stm32l4_can_s *priv, int arg)
* Description:
* Initialize the selected CAN port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple CAN interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/stm32l4/stm32l4_can.h b/arch/arm/src/stm32l4/stm32l4_can.h
index ded35c173ba2eb7c461f0869afea606deced54b4..c7ff34733d576ae07013c4e46e22548ee72220ff 100644
--- a/arch/arm/src/stm32l4/stm32l4_can.h
+++ b/arch/arm/src/stm32l4/stm32l4_can.h
@@ -122,7 +122,7 @@ extern "C"
* Description:
* Initialize the selected CAN port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple CAN interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/stm32l4/stm32l4_comp.c b/arch/arm/src/stm32l4/stm32l4_comp.c
index 8e2f4ff90868690c01f53b246b6a8326a8536411..0c954c7c8be82b0a6ac6642cb037af705b191862 100644
--- a/arch/arm/src/stm32l4/stm32l4_comp.c
+++ b/arch/arm/src/stm32l4/stm32l4_comp.c
@@ -342,7 +342,7 @@ static int stm32l4_exti_comp_isr(int irq, void *context, FAR void *arg)
* Parameters:
* cfg - configuration
*
- * Returns:
+ * Returned Value:
* 0 on success, a negated errno value on failure
*
****************************************************************************/
diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.c b/arch/arm/src/stm32l4/stm32l4_dfsdm.c
index 89a57ea86ec2d229940418e2d7f8639edee76fbe..a52ad71df0346a2844778f3a5cb3ab3416011b92 100644
--- a/arch/arm/src/stm32l4/stm32l4_dfsdm.c
+++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.c
@@ -545,7 +545,7 @@ static void tim_modifyreg(FAR struct stm32_dev_s *priv, int offset,
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the DFSDM block status
*
* Returned Value:
@@ -1070,7 +1070,8 @@ static void dfsdm_rccreset(FAR struct stm32_dev_s *priv, bool reset)
/****************************************************************************
* Name: dfsdm_enable
*
- * Description : Enables the DFSDM peripheral.
+ * Description:
+ * Enables the DFSDM peripheral.
*
* Input Parameters:
* priv - A reference to the DFSDM block status
diff --git a/arch/arm/src/stm32l4/stm32l4_dma.h b/arch/arm/src/stm32l4/stm32l4_dma.h
index 5eb679be70bf4c9e8eb70ce75e3ee317f3d60736..c31246526767e3b94301e4bb1a30c5040da938c2 100644
--- a/arch/arm/src/stm32l4/stm32l4_dma.h
+++ b/arch/arm/src/stm32l4/stm32l4_dma.h
@@ -145,7 +145,7 @@ extern "C"
* Hmm.. I suppose this interface could be extended to make a non-blocking
* version. Feel free to do that if that is what you need.
*
- * Input parameter:
+ * Input Parameters:
* chan - Identifies the stream/channel resource
* This is a bit encoded value as provided by the DMACHAN_* definitions
* in chip/stm32l4x6xx_dma.h
@@ -249,7 +249,7 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle);
* only applies to memory addresses, it will return false for any peripheral
* address.
*
- * Returned value:
+ * Returned Value:
* True, if transfer is possible.
*
****************************************************************************/
diff --git a/arch/arm/src/stm32l4/stm32l4_exti.h b/arch/arm/src/stm32l4/stm32l4_exti.h
index 14d2e7100ae47454d1b6b9bd23516e985acaa48f..098ac6e720a7d35388d52d38bfcf13b53a40fc16 100644
--- a/arch/arm/src/stm32l4/stm32l4_exti.h
+++ b/arch/arm/src/stm32l4/stm32l4_exti.h
@@ -101,7 +101,7 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
- * Returns:
+ * Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
@@ -124,7 +124,7 @@ int stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event,
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
- * Returns:
+ * Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
@@ -148,7 +148,7 @@ int stm32l4_exti_wakeup(bool risingedge, bool fallingedge, bool event,
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
- * Returns:
+ * Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on
* failure.
*
diff --git a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c
index 2a0b3fbb0ef469f0762c88c1e2897b9041b82b45..e0016e063768d1540d45541cd2609a163a605d78 100644
--- a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c
+++ b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c
@@ -108,7 +108,7 @@ static int stm32l4_exti_alarm_isr(int irq, void *context, FAR void *arg)
* - event: generate event when set
* - func: when non-NULL, generate interrupt
*
- * Returns:
+ * Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
diff --git a/arch/arm/src/stm32l4/stm32l4_exti_comp.c b/arch/arm/src/stm32l4/stm32l4_exti_comp.c
index 147eb3f4b48e7ef294e9c72b78da29e4c46166e2..44d029e0b3e572dea69cdfe63c17ebca0710b246 100644
--- a/arch/arm/src/stm32l4/stm32l4_exti_comp.c
+++ b/arch/arm/src/stm32l4/stm32l4_exti_comp.c
@@ -129,7 +129,7 @@ static int stm32l4_exti_comp_isr(int irq, void *context, FAR void *arg)
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
- * Returns:
+ * Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on
* failure.
*
diff --git a/arch/arm/src/stm32l4/stm32l4_exti_pwr.c b/arch/arm/src/stm32l4/stm32l4_exti_pwr.c
index ab19f6f3cb95384a0c35b84400d606c01fda2f8c..7d5df6709802dce39b672bf11b7b503898953be7 100644
--- a/arch/arm/src/stm32l4/stm32l4_exti_pwr.c
+++ b/arch/arm/src/stm32l4/stm32l4_exti_pwr.c
@@ -113,7 +113,7 @@ static int stm32l4_exti_pvd_isr(int irq, void *context, FAR void *arg)
* - event: generate event when set
* - func: when non-NULL, generate interrupt
*
- * Returns:
+ * Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on
* failure.
*
diff --git a/arch/arm/src/stm32l4/stm32l4_exti_pwr.h b/arch/arm/src/stm32l4/stm32l4_exti_pwr.h
index 27e584779b9fe981ce6fc93a9f2c7b86a764b3de..c6e10a0fa759b9392a275a05e3a8700992e76b48 100644
--- a/arch/arm/src/stm32l4/stm32l4_exti_pwr.h
+++ b/arch/arm/src/stm32l4/stm32l4_exti_pwr.h
@@ -59,7 +59,7 @@
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
- * Returns:
+ * Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on
* failure.
*
diff --git a/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c b/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c
index 195cf2c1ac0d9f116e7517e3fcb3cc2d88eac0e7..ddac94add35a412ab67c42fd2ae407577182fbb3 100644
--- a/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c
+++ b/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c
@@ -107,7 +107,7 @@ static int stm32l4_exti_wakeup_isr(int irq, void *context, FAR void *arg)
* - event: generate event when set
* - func: when non-NULL, generate interrupt
*
- * Returns:
+ * Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.c b/arch/arm/src/stm32l4/stm32l4_gpio.c
index f46f341662c932c26bee5f1ef467d2f7b9d43a05..a33b88c08fe0eb14742d69db2361d0159ae8aeb6 100644
--- a/arch/arm/src/stm32l4/stm32l4_gpio.c
+++ b/arch/arm/src/stm32l4/stm32l4_gpio.c
@@ -129,7 +129,7 @@ void stm32l4_gpioinit(void)
* function, it must be unconfigured with stm32l4_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
- * Returns:
+ * Returned Value:
* OK on success
* A negated errono valu on invalid port, or when pin is locked as ALT
* function.
@@ -351,7 +351,7 @@ int stm32l4_configgpio(uint32_t cfgset)
* operate in PWM mode could produce excessive on-board currents and trigger
* over-current/alarm function.
*
- * Returns:
+ * Returned Value:
* OK on success
* A negated errno value on invalid port
*
diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.h b/arch/arm/src/stm32l4/stm32l4_gpio.h
index 3c7b615c4e878aee72cbcf2a696e64f64b7b69b7..56fb77a6bbe5ff43268b2432188ef3fe3826007e 100644
--- a/arch/arm/src/stm32l4/stm32l4_gpio.h
+++ b/arch/arm/src/stm32l4/stm32l4_gpio.h
@@ -273,7 +273,7 @@ EXTERN const uint32_t g_gpiobase[STM32L4_NPORTS];
* function, it must be unconfigured with stm32l4_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
- * Returns:
+ * Returned Value:
* OK on success
* ERROR on invalid port, or when pin is locked as ALT function.
*
@@ -294,7 +294,7 @@ int stm32l4_configgpio(uint32_t cfgset);
* operate in PWM mode could produce excessive on-board currents and trigger
* over-current/alarm function.
*
- * Returns:
+ * Returned Value:
* OK on success
* ERROR on invalid port
*
diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.h b/arch/arm/src/stm32l4/stm32l4_i2c.h
index 267ee1d6640509d57d63137356fdaabf784306fb..3a38cc14bdca451a3428e3014e4acb5f5462a3e4 100644
--- a/arch/arm/src/stm32l4/stm32l4_i2c.h
+++ b/arch/arm/src/stm32l4/stm32l4_i2c.h
@@ -74,7 +74,7 @@
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
@@ -90,7 +90,7 @@ FAR struct i2c_master_s *stm32l4_i2cbus_initialize(int port);
* Description:
* De-initialize the selected I2C port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the stm32l4_i2cbus_initialize()
*
* Returned Value:
diff --git a/arch/arm/src/stm32l4/stm32l4_iwdg.c b/arch/arm/src/stm32l4/stm32l4_iwdg.c
index 9977e4d727d5c8d886940994754f658c8bb81e00..bf0b1392bb9f7be6e9bbc06b8c24ab07967d5fbd 100644
--- a/arch/arm/src/stm32l4/stm32l4_iwdg.c
+++ b/arch/arm/src/stm32l4/stm32l4_iwdg.c
@@ -312,7 +312,7 @@ static inline void stm32l4_setprescaler(FAR struct stm32l4_lowerhalf_s *priv)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -360,7 +360,7 @@ static int stm32l4_start(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -385,7 +385,7 @@ static int stm32l4_stop(FAR struct watchdog_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -418,7 +418,7 @@ static int stm32l4_keepalive(FAR struct watchdog_lowerhalf_s *lower)
* driver state structure.
* status - The location to return the watchdog status information.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -477,7 +477,7 @@ static int stm32l4_getstatus(FAR struct watchdog_lowerhalf_s *lower,
* driver state structure.
* timeout - The new timeout value in milliseconds.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -602,7 +602,7 @@ static int stm32l4_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* /dev/watchdog0
* lsifreq - The calibrated LSI clock frequency
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/stm32l4/stm32l4_otgfshost.c b/arch/arm/src/stm32l4/stm32l4_otgfshost.c
index b7e952d23171da1305254c61a83f0b3442e5b08e..e676d9504f2cd052439c44bc4d1ed5c6461e8c0a 100644
--- a/arch/arm/src/stm32l4/stm32l4_otgfshost.c
+++ b/arch/arm/src/stm32l4/stm32l4_otgfshost.c
@@ -1267,7 +1267,7 @@ static int stm32l4_ctrlchan_alloc(FAR struct stm32l4_usbhost_s *priv,
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -1329,7 +1329,7 @@ static int stm32l4_ctrlep_alloc(FAR struct stm32l4_usbhost_s *priv,
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -3825,7 +3825,7 @@ static void stm32l4_txfe_enable(FAR struct stm32l4_usbhost_s *priv, int chidx)
* hport - The location to return the hub port descriptor that detected the
* connection related event.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success when a device in connected or
* disconnected. This function will not return until either (1) a device is
* connected or disconnect to/from any hub port or until (2) some failure
@@ -3916,7 +3916,7 @@ static int stm32l4_wait(FAR struct usbhost_connection_s *conn,
* hport - The descriptor of the hub port that has the newly connected
* device.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4046,7 +4046,7 @@ static int stm32l4_enumerate(FAR struct usbhost_connection_s *conn,
* maxpacketsize - The maximum number of bytes that can be sent to or
* received from the endpoint in a single data packet
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4105,7 +4105,7 @@ static int stm32l4_ep0configure(FAR struct usbhost_driver_s *drvr,
* ep - A memory location provided by the caller in which to receive the
* allocated endpoint descriptor.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4161,7 +4161,7 @@ static int stm32l4_epalloc(FAR struct usbhost_driver_s *drvr,
* the class create() method.
* ep - The endpoint to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4229,7 +4229,7 @@ static int stm32l4_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
* maxlen - The address of a memory location provided by the caller in which to
* return the maximum size of the allocated buffer memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4275,7 +4275,7 @@ static int stm32l4_alloc(FAR struct usbhost_driver_s *drvr,
* the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4311,7 +4311,7 @@ static int stm32l4_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer)
* return the allocated buffer memory address.
* buflen - The size of the buffer required.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4355,7 +4355,7 @@ static int stm32l4_ioalloc(FAR struct usbhost_driver_s *drvr,
* the class create() method.
* buffer - The address of the allocated buffer memory to be freed.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4398,7 +4398,7 @@ static int stm32l4_iofree(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer
* NOTE: On an IN transaction, req and buffer may refer to the same allocated
* memory.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4601,7 +4601,7 @@ static int stm32l4_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
* (IN endpoint). buffer must have been allocated using DRVR_ALLOC
* buflen - The length of the data to be sent or received.
*
- * Returned Values:
+ * Returned Value:
* On success, a non-negative value is returned that indicates the number
* of bytes successfully transferred. On a failure, a negated errno value is
* returned that indicates the nature of the failure:
@@ -4673,7 +4673,7 @@ static ssize_t stm32l4_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t
* arg - The arbitrary parameter that will be passed to the callback function
* when the transfer completes.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure
*
@@ -4729,7 +4729,7 @@ static int stm32l4_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
* ep - The IN or OUT endpoint descriptor for the device endpoint on which an
* asynchronous transfer should be transferred.
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -4818,7 +4818,7 @@ static int stm32l4_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
* related event
* connected - True: device connected; false: device disconnected
*
- * Returned Values:
+ * Returned Value:
* On success, zero (OK) is returned. On a failure, a negated errno value is
* returned indicating the nature of the failure.
*
@@ -4870,7 +4870,7 @@ static int stm32l4_connect(FAR struct usbhost_driver_s *drvr,
* hport - The port from which the device is being disconnected. Might be a port
* on a hub.
*
- * Returned Values:
+ * Returned Value:
* None
*
* Assumptions:
diff --git a/arch/arm/src/stm32l4/stm32l4_pm.h b/arch/arm/src/stm32l4/stm32l4_pm.h
index fd94299389c910afcafb9f8d6773fbdb1fd91731..530be06fcb4c7a398038fb20d3e8dcbb5cece397 100644
--- a/arch/arm/src/stm32l4/stm32l4_pm.h
+++ b/arch/arm/src/stm32l4/stm32l4_pm.h
@@ -108,7 +108,7 @@ int stm32l4_pmstop2(void);
* Input Parameters:
* None
*
- * Returned Value.
+ * Returned Value:
* On success, this function will not return (STANDBY mode can only be
* terminated with a reset event). Otherwise, STANDBY mode did not occur
* and a negated errno value is returned to indicate the cause of the
diff --git a/arch/arm/src/stm32l4/stm32l4_pminitialize.c b/arch/arm/src/stm32l4/stm32l4_pminitialize.c
index 05988f21bf5723da1df9944580531b9fbf187c56..89a8547a58601b51bebf2e75601afe516f1a0436 100644
--- a/arch/arm/src/stm32l4/stm32l4_pminitialize.c
+++ b/arch/arm/src/stm32l4/stm32l4_pminitialize.c
@@ -60,10 +60,10 @@
* *before* any other device drivers are initialized (since they may
* attempt to register with the power management subsystem).
*
- * Input parameters:
+ * Input Parameters:
* None.
*
- * Returned value:
+ * Returned Value:
* None.
*
****************************************************************************/
diff --git a/arch/arm/src/stm32l4/stm32l4_pmstandby.c b/arch/arm/src/stm32l4/stm32l4_pmstandby.c
index c8730c14f9dcff17cd1eb28c887b40462d5f8c68..331d8446f32a558a1c55e88728f6510d97533a21 100644
--- a/arch/arm/src/stm32l4/stm32l4_pmstandby.c
+++ b/arch/arm/src/stm32l4/stm32l4_pmstandby.c
@@ -60,7 +60,7 @@
* Input Parameters:
* None
*
- * Returned Value.
+ * Returned Value:
* On success, this function will not return (STANDBY mode can only be
* terminated with a reset event). Otherwise, STANDBY mode did not occur
* and a negated errno value is returned to indicate the cause of the
diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c
index 10531d20a8ccc334f37a9689c88ee2a34f84fc84..03639445845b372a86a85f98462a977a2c2eab48 100644
--- a/arch/arm/src/stm32l4/stm32l4_pwm.c
+++ b/arch/arm/src/stm32l4/stm32l4_pwm.c
@@ -676,7 +676,7 @@ static void stm32l4pwm_putreg(struct stm32l4_pwmtimer_s *priv, int offset,
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the PWM block status
*
* Returned Value:
@@ -734,7 +734,7 @@ static void stm32l4pwm_dumpregs(struct stm32l4_pwmtimer_s *priv,
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -1360,7 +1360,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
* Description:
* Try to change only channel duty.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the lower half PWM driver state structure
* channel - Channel to by updated
* duty - New duty.
@@ -1442,7 +1442,7 @@ static int stm32l4pwm_update_duty(FAR struct stm32l4_pwmtimer_s *priv,
* Description:
* Handle timer interrupts.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -1525,7 +1525,7 @@ static int stm32l4pwm_interrupt(struct stm32l4_pwmtimer_s *priv)
* Description:
* Handle timer 1 and 8 interrupts.
*
- * Input parameters:
+ * Input Parameters:
* Standard NuttX interrupt inputs
*
* Returned Value:
@@ -1553,7 +1553,7 @@ static int stm32l4pwm_tim8interrupt(int irq, void *context, FAR void *arg)
* Description:
* Pick an optimal pulse count to program the RCR.
*
- * Input parameters:
+ * Input Parameters:
* count - The total count remaining
*
* Returned Value:
@@ -1600,7 +1600,7 @@ static uint8_t stm32l4pwm_pulsecount(uint32_t count)
* Description:
* Enable or disable APB clock for the timer peripheral
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* on - Enable clock if 'on' is 'true' and disable if 'false'
*
@@ -1693,7 +1693,7 @@ static void stm32l4pwm_setapbclock(FAR struct stm32l4_pwmtimer_s *priv, bool on)
* should configure and initialize the device so that it is ready for use.
* It should not, however, output pulses until the start method is called.
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -1755,7 +1755,7 @@ static int stm32l4pwm_setup(FAR struct pwm_lowerhalf_s *dev)
* stop pulsed output, free any resources, disable the timer hardware, and
* put the system into the lowest possible power usage state
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -1816,7 +1816,7 @@ static int stm32l4pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -1903,7 +1903,7 @@ static int stm32l4pwm_start(FAR struct pwm_lowerhalf_s *dev,
* Description:
* Stop the pulsed output and reset the timer resources
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -2020,7 +2020,7 @@ static int stm32l4pwm_stop(FAR struct pwm_lowerhalf_s *dev)
* Description:
* Lower-half logic may support platform-specific ioctl commands
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* cmd - The ioctl command
* arg - The argument accompanying the ioctl command
diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c
index 9f8a20fc9f83c381fd5df9a2612e6f68fe644e80..683b2f62639e993920d700247057ce7aaea8aac5 100644
--- a/arch/arm/src/stm32l4/stm32l4_qencoder.c
+++ b/arch/arm/src/stm32l4/stm32l4_qencoder.c
@@ -504,7 +504,7 @@ static void stm32l4_putreg32(FAR struct stm32l4_lowerhalf_s *priv, int offset,
* Description:
* Dump all timer registers.
*
- * Input parameters:
+ * Input Parameters:
* priv - A reference to the QENCODER block status
*
* Returned Value:
@@ -1108,7 +1108,7 @@ static int stm32l4_ioctl(FAR struct qe_lowerhalf_s *lower, int cmd, unsigned lon
* devpath - The full path to the driver to register. E.g., "/dev/qe0"
* tim - The timer number to used. 'tim' must be an element of {1,2,3,4,5,8}
*
- * Returned Values:
+ * Returned Value:
* Zero on success; A negated errno value is returned on failure.
*
************************************************************************************/
diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.h b/arch/arm/src/stm32l4/stm32l4_qencoder.h
index 7fccca772b36b5ccd677ab4f95d5c635b9dde563..b2d2b445c6ab9250b748d76d76916be2f2bfd5ba 100644
--- a/arch/arm/src/stm32l4/stm32l4_qencoder.h
+++ b/arch/arm/src/stm32l4/stm32l4_qencoder.h
@@ -129,7 +129,7 @@
* devpath - The full path to the driver to register. E.g., "/dev/qe0"
* tim - The timer number to used. 'tim' must be an element of {1,2,3,4,5,8}
*
- * Returned Values:
+ * Returned Value:
* Zero on success; A negated errno value is returned on failure.
*
************************************************************************************/
diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c
index 793fbb7ffaf21028c204d5423d7799802752d7b5..cf303e71b430e52978a3489d90766661563e73fa 100644
--- a/arch/arm/src/stm32l4/stm32l4_qspi.c
+++ b/arch/arm/src/stm32l4/stm32l4_qspi.c
@@ -1447,7 +1447,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv,
ret = wd_start(priv->dmadog, DMA_TIMEOUT_TICKS,
(wdentry_t)qspi_dma_timeout, 1, (uint32_t)priv);
- if (ret != OK)
+ if (ret < 0)
{
spierr("ERROR: wd_start failed: %d\n", ret);
}
@@ -2421,7 +2421,7 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv)
* Description:
* Initialize the selected QSPI port in master mode
*
- * Input Parameter:
+ * Input Parameters:
* intf - Interface number(must be zero)
*
* Returned Value:
@@ -2594,7 +2594,7 @@ errout_with_dmahandles:
* Description:
* Put the QSPI device into memory mapped mode
*
- * Input Parameter:
+ * Input Parameters:
* dev - QSPI device
* meminfo - parameters like for a memory transfer used for reading
*
@@ -2686,7 +2686,7 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s* dev,
* Description:
* Take the QSPI device out of memory mapped mode
*
- * Input Parameter:
+ * Input Parameters:
* dev - QSPI device
*
* Returned Value:
diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.h b/arch/arm/src/stm32l4/stm32l4_qspi.h
index ed65850fc56e69e0e043a761d1f81574f336abd8..c9c87638ee2c7d5293349b1149c997543fd4315a 100644
--- a/arch/arm/src/stm32l4/stm32l4_qspi.h
+++ b/arch/arm/src/stm32l4/stm32l4_qspi.h
@@ -86,7 +86,7 @@ extern "C"
* Description:
* Initialize the selected QSPI port in master mode
*
- * Input Parameter:
+ * Input Parameters:
* intf - Interface number(must be zero)
*
* Returned Value:
@@ -103,7 +103,7 @@ FAR struct qspi_dev_s *stm32l4_qspi_initialize(int intf);
* Description:
* Put the QSPI device into memory mapped mode
*
- * Input Parameter:
+ * Input Parameters:
* dev - QSPI device
* meminfo - parameters like for a memory transfer used for reading
* lpto - number of cycles to wait to automatically de-assert CS
@@ -123,7 +123,7 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s* dev,
* Description:
* Take the QSPI device out of memory mapped mode
*
- * Input Parameter:
+ * Input Parameters:
* dev - QSPI device
*
* Returned Value:
diff --git a/arch/arm/src/stm32l4/stm32l4_sai.c b/arch/arm/src/stm32l4/stm32l4_sai.c
index 80d07f024f37b217a9db77eed4d69ca00d069580..21892409d531e8e953f2abefc8542070535a3b37 100644
--- a/arch/arm/src/stm32l4/stm32l4_sai.c
+++ b/arch/arm/src/stm32l4/stm32l4_sai.c
@@ -479,7 +479,7 @@ static void sai_exclsem_take(struct stm32l4_sai_s *priv)
* Setup the master clock divider based on the currently selected data width
* and the sample rate
*
- * Input Parameter:
+ * Input Parameters:
* priv - SAI device structure (only the sample rate and frequency are
* needed at this point).
*
@@ -1288,7 +1288,7 @@ static void sai_buf_initialize(struct stm32l4_sai_s *priv)
* Description:
* Initialize the selected SAI port in its default state
*
- * Input Parameter:
+ * Input Parameters:
* priv - private SAI device structure
*
* Returned Value:
@@ -1353,7 +1353,7 @@ static void sai_portinitialize(struct stm32l4_sai_s *priv)
* Description:
* Initialize the selected SAI block
*
- * Input Parameter:
+ * Input Parameters:
* intf - I2S interface number (identifying the "logical" SAI interface)
*
* Returned Value:
diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.c b/arch/arm/src/stm32l4/stm32l4_sdmmc.c
index 6da267d2d026ad70d7673833c7eedd7fc89a7109..38a7077d079066f03c500d7369a64395e0a24932 100644
--- a/arch/arm/src/stm32l4/stm32l4_sdmmc.c
+++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.c
@@ -2637,7 +2637,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay, (wdentry_t)stm32_eventtimeout,
1, (uint32_t)priv);
- if (ret != OK)
+ if (ret < 0)
{
mcerr("ERROR: wd_start failed: %d\n", ret);
}
@@ -3099,7 +3099,7 @@ static void stm32_default(struct stm32_dev_s *priv)
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
@@ -3234,7 +3234,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -3281,7 +3281,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is writeprotected.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.h b/arch/arm/src/stm32l4/stm32l4_sdmmc.h
index 155cf209f1f29cc4a29e220448b178400a602a79..0882acbb74ed844134742ba087ca86cbeec4ec30 100644
--- a/arch/arm/src/stm32l4/stm32l4_sdmmc.h
+++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.h
@@ -73,7 +73,7 @@ extern "C"
* Input Parameters:
* slotno - Not used.
*
- * Returned Values:
+ * Returned Value:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
@@ -95,7 +95,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno);
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -113,7 +113,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is writeprotected.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c
index 67602e3c16909467c7a246bb0efc6dae47a97bfe..1cc67bb148f548095ddbb1f566559e208dfb570c 100644
--- a/arch/arm/src/stm32l4/stm32l4_serial.c
+++ b/arch/arm/src/stm32l4/stm32l4_serial.c
@@ -1218,7 +1218,7 @@ void stm32l4serial_pm_setsuspend(bool suspend)
* Description:
* Enable or disable APB clock for the USART peripheral
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the UART driver state structure
* on - Enable clock if 'on' is 'true' and disable if 'false'
*
@@ -2100,7 +2100,7 @@ static bool stm32l4serial_rxavailable(FAR struct uart_dev_s *dev)
* Return true if UART activated RX flow control to block more incoming
* data
*
- * Input parameters:
+ * Input Parameters:
* dev - UART device instance
* nbuffered - the number of characters currently buffered
* (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is
diff --git a/arch/arm/src/stm32l4/stm32l4_spi.c b/arch/arm/src/stm32l4/stm32l4_spi.c
index 7f5d1543a1c7c0191a3cc1fb6e0d95ca5bb10a17..b98bd793e299b389ce49533f06dfba994d1bda04 100644
--- a/arch/arm/src/stm32l4/stm32l4_spi.c
+++ b/arch/arm/src/stm32l4/stm32l4_spi.c
@@ -1481,7 +1481,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, size_t
* Description:
* Initialize the selected SPI bus in its default state (Master, 8-bit, mode 0, etc.)
*
- * Input Parameter:
+ * Input Parameters:
* priv - private SPI device structure
*
* Returned Value:
@@ -1571,7 +1571,7 @@ static void spi_bus_initialize(FAR struct stm32l4_spidev_s *priv)
* Description:
* Initialize the selected SPI bus
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/stm32l4/stm32l4_spi.h b/arch/arm/src/stm32l4/stm32l4_spi.h
index 7f5390f34778aa5636688698f0307cefa948de92..5d9f74db704f63e42b8b86a44da5deec156179f2 100644
--- a/arch/arm/src/stm32l4/stm32l4_spi.h
+++ b/arch/arm/src/stm32l4/stm32l4_spi.h
@@ -76,7 +76,7 @@ struct spi_dev_s;
* Description:
* Initialize the selected SPI bus
*
- * Input Parameter:
+ * Input Parameters:
* bus number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/stm32l4/stm32l4_tim.h b/arch/arm/src/stm32l4/stm32l4_tim.h
index 8362ef13875d1abe30384886dd8777065dcc7111..fa88892d3ad0006e4a5cccdca8a5fc9df5b9906a 100644
--- a/arch/arm/src/stm32l4/stm32l4_tim.h
+++ b/arch/arm/src/stm32l4/stm32l4_tim.h
@@ -204,7 +204,7 @@ int stm32l4_tim_deinit(FAR struct stm32l4_tim_dev_s *dev);
* devpath - The full path to the timer device. This should be of the form /dev/timer0
* timer - the timer number.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
diff --git a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c
index 59918c81ba9292ad26e2fa9e6ea98d336dc26af4..76f5bff364807f9d395e85d1bbe08809dc642fc7 100644
--- a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c
+++ b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c
@@ -231,7 +231,7 @@ static struct stm32l4_lowerhalf_s g_tim17_lowerhalf =
*
* Input Parameters:
*
- * Returned Values:
+ * Returned Value:
*
****************************************************************************/
@@ -267,7 +267,7 @@ static int stm32l4_timer_handler(int irq, void *context, void *arg)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -305,7 +305,7 @@ static int stm32l4_start(FAR struct timer_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -339,7 +339,7 @@ static int stm32l4_stop(FAR struct timer_lowerhalf_s *lower)
* driver state structure.
* timeout - The new timeout value in microseconds.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -385,7 +385,7 @@ static int stm32l4_settimeout(FAR struct timer_lowerhalf_s *lower,
* behavior is restored,
* arg - Argument that will be provided in the callback
*
- * Returned Values:
+ * Returned Value:
* The previous timer expiration function pointer or NULL is there was
* no previous function pointer.
*
@@ -432,7 +432,7 @@ static void stm32l4_setcallback(FAR struct timer_lowerhalf_s *lower,
* form /dev/timer0
* timer - the timer's number.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
diff --git a/arch/arm/src/stm32l4/stm32l4_wdg.h b/arch/arm/src/stm32l4/stm32l4_wdg.h
index 794c5e2aef83e3f4a73233171a47a4e93989c33c..0d2b0032538257bad6685d2a0feed1c6a42ccb6e 100644
--- a/arch/arm/src/stm32l4/stm32l4_wdg.h
+++ b/arch/arm/src/stm32l4/stm32l4_wdg.h
@@ -79,7 +79,7 @@ extern "C"
* /dev/watchdog0
* lsifreq - The calibrated LSI clock frequency
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -100,7 +100,7 @@ void stm32l4_iwdginitialize(FAR const char *devpath, uint32_t lsifreq);
* devpath - The full path to the watchdog. This should be of the form
* /dev/watchdog0
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c
index cd194b2cba0b362c3f7a7773d7b404948ecf97b5..d727be752b8bd0deac4500a7d96afea6c53e03f4 100644
--- a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c
+++ b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c
@@ -394,7 +394,7 @@ void weak_function up_dmainitialize(void)
* Hmm.. I suppose this interface could be extended to make a non-blocking
* version. Feel free to do that if that is what you need.
*
- * Input parameter:
+ * Input Parameters:
* chan - Identifies the stream/channel resource
* This is a bit encoded value as provided by the DMACHAN_* definitions
* in chip/stm32l4x6xx_dma.h
@@ -642,7 +642,7 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle)
* of the processor. Note that this only applies to memory addresses, it
* will return false for any peripheral address.
*
- * Returned value:
+ * Returned Value:
* True, if transfer is possible.
*
****************************************************************************/
diff --git a/arch/arm/src/str71x/str71x.h b/arch/arm/src/str71x/str71x.h
index 7b3bedf1df34e28e851cdd6044d976859cf4d7af..aea504fe89b7f867976f9135051977e2da53483f 100644
--- a/arch/arm/src/str71x/str71x.h
+++ b/arch/arm/src/str71x/str71x.h
@@ -162,7 +162,7 @@ struct spi_dev_s; /* Forward reference */
* Initialize the selected SPI port. This function could get called
* multiple times for each STR7 devices that needs an SPI reference.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/str71x/str71x_head.S b/arch/arm/src/str71x/str71x_head.S
index c35715e02d21e5010ca74a170e2a5b8803573420..934fd7fdfd181080e5723eb50b32013bcef1fe5d 100644
--- a/arch/arm/src/str71x/str71x_head.S
+++ b/arch/arm/src/str71x/str71x_head.S
@@ -346,7 +346,7 @@ eicloop:
/*****************************************************************************
* Name: periphinit
*
- * Description"
+ * Description:
* Disable all perfipherals (except EIC)
*
*****************************************************************************/
diff --git a/arch/arm/src/tiva/Make.defs b/arch/arm/src/tiva/Make.defs
index d65294d6c51984cac4bf41096183eb6a86c3f2b5..6e5c862d96e6136d1e19059d0cd73ab5fb15e751 100644
--- a/arch/arm/src/tiva/Make.defs
+++ b/arch/arm/src/tiva/Make.defs
@@ -36,7 +36,7 @@
HEAD_ASRC = tiva_vectors.S
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
-CMN_ASRCS += up_testset.S vfork.S
+CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S
CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c
CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_idle.c up_initialize.c
diff --git a/arch/arm/src/tiva/tiva_adc.h b/arch/arm/src/tiva/tiva_adc.h
index 7f6edd4f9d8b741146a22623f2c3f6fe06c3d9d3..a717ad72f12fbe5a9b8a7d41e3976dfeb3ee03a1 100644
--- a/arch/arm/src/tiva/tiva_adc.h
+++ b/arch/arm/src/tiva/tiva_adc.h
@@ -405,7 +405,7 @@ void tiva_adc_sample_rate(uint8_t rate);
* to the FIFO. This is only required when the trigger source is set to the
* processor.
*
- * Input parameters:
+ * Input Parameters:
* adc - which ADC peripherals' sample sequencers to trigger
* sse_mask - sample sequencer bitmask, each sse is 1 shifted by the sse
* number. e.g.
@@ -424,7 +424,7 @@ void tiva_adc_proc_trig(uint8_t adc, uint8_t sse_mask);
* Description:
* Returns raw interrupt status for the input ADC
*
- * Input parameters:
+ * Input Parameters:
* adc - which ADC peripherals' interrupt status to retrieve
*
****************************************************************************/
@@ -440,12 +440,12 @@ uint32_t tiva_adc_int_status(uint8_t adc);
* Sets the operation state of an ADC's sample sequencer (SSE). SSEs must
* be configured before being enabled.
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* state - sample sequencer enable/disable state
*
- * Return value:
+ * Returned Value:
* Actual state of the ACTSS register.
*
****************************************************************************/
@@ -466,7 +466,7 @@ uint8_t tiva_adc_sse_enable(uint8_t adc, uint8_t sse, bool state);
* - Always
* - !!UNSUPPORTED: Comparators
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* trigger - interrupt trigger
@@ -482,7 +482,7 @@ void tiva_adc_sse_trigger(uint8_t adc, uint8_t sse, uint32_t trigger);
* Additional triggering configuration for PWM. Sets which PWM and which
* generator.
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* cfg - which PWM modulator and generator to use, use TIVA_ADC_PWM_TRIG
@@ -501,7 +501,7 @@ void tiva_adc_sse_pwm_trig(uint8_t adc, uint8_t sse, uint32_t cfg);
* Sets the interrupt state of an ADC's sample sequencer (SSE). SSEs must
* be enabled before setting interrupt state.
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* state - sample sequencer enable/disable interrupt state
@@ -516,7 +516,7 @@ void tiva_adc_sse_int_enable(uint8_t adc, uint8_t sse, bool state);
* Description:
* Returns interrupt status for the specificed SSE
*
- * Input parameters:
+ * Input Parameters:
* adc - which ADC peripherals' interrupt status to retrieve
* sse - which SSE interrupt status to retrieve
*
@@ -530,7 +530,7 @@ bool tiva_adc_sse_int_status(uint8_t adc, uint8_t sse);
* Description:
* Clears the interrupt bit for the SSE.
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* state - sample sequencer
@@ -547,11 +547,11 @@ void tiva_adc_sse_clear_int(uint8_t adc, uint8_t sse);
* The input data buffer MUST be as large or larger than the sample sequencer.
* otherwise
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
*
- * Return value:
+ * Returned Value:
* number of steps read from FIFO.
*
****************************************************************************/
@@ -566,7 +566,7 @@ uint8_t tiva_adc_sse_data(uint8_t adc, uint8_t sse, int32_t *buf);
* priority value ranges from 0 to 3, 0 being the highest priority, 3 being
* the lowest. There can be no duplicate values.
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* priority - conversion priority
@@ -585,7 +585,7 @@ void tiva_adc_sse_priority(uint8_t adc, uint8_t sse, uint8_t priority);
*
* *SSEMUX only supported on TM4C129 devices
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* chn - sample sequencer step
@@ -601,7 +601,7 @@ void tiva_adc_sse_register_chn(uint8_t adc, uint8_t sse, uint8_t chn, uint32_t a
* Description:
* Sets the differential capability for a SSE. !! UNSUPPORTED
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* chn - sample sequencer channel
@@ -620,7 +620,7 @@ void tiva_adc_sse_differential(uint8_t adc, uint8_t sse, uint8_t chn, uint32_t d
* This is not available on all devices, however on devices that do not
* support this feature these reserved bits are ignored on write access.
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* chn - sample sequencer channel
@@ -652,7 +652,7 @@ void tiva_adc_sse_sample_hold_time(uint8_t adc, uint8_t sse, uint8_t chn, uint32
*
* *Comparator/Differential functionality is unsupported and ignored.
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* chn - sample sequencer channel
@@ -669,7 +669,7 @@ void tiva_adc_sse_step_cfg(uint8_t adc, uint8_t sse, uint8_t chn, uint8_t cfg);
* Dump all configured registers for the given ADC and SSE. This should
* only be used to verify that configuration routines were accurate.
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
*
diff --git a/arch/arm/src/tiva/tiva_adclib.c b/arch/arm/src/tiva/tiva_adclib.c
index dc2768fc16300c4b831e15e2bff9a01cef62afc1..8d55333a026950c355446c007c2b4822f668c929 100644
--- a/arch/arm/src/tiva/tiva_adclib.c
+++ b/arch/arm/src/tiva/tiva_adclib.c
@@ -624,7 +624,7 @@ void tiva_adc_sample_rate(uint8_t rate)
* to the FIFO. This is only required when the trigger source is set to the
* processor.
*
- * Input parameters:
+ * Input Parameters:
* adc - which ADC peripherals' sample sequencers to trigger
* sse_mask - sample sequencer bitmask, each sse is 1 shifted by the sse
* number. e.g.
@@ -650,7 +650,7 @@ void tiva_adc_proc_trig(uint8_t adc, uint8_t sse_mask)
* Description:
* Returns raw interrupt status for the input ADC
*
- * Input parameters:
+ * Input Parameters:
* adc - which ADC peripherals' interrupt status to retrieve
*
****************************************************************************/
@@ -670,12 +670,12 @@ uint32_t tiva_adc_int_status(uint8_t adc)
* Sets the operation state of an ADC's sample sequencer (SSE). SSEs must
* be configured before being enabled.
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* state - sample sequencer enable/disable state
*
- * Return value:
+ * Returned Value:
* Actual state of the ACTSS register.
*
****************************************************************************/
@@ -711,7 +711,7 @@ uint8_t tiva_adc_sse_enable(uint8_t adc, uint8_t sse, bool state)
* - Always
* - !!UNSUPPORTED: Comparators
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* trigger - interrupt trigger
@@ -736,7 +736,7 @@ void tiva_adc_sse_trigger(uint8_t adc, uint8_t sse, uint32_t trigger)
* Additional triggering configuration for PWM. Sets which PWM and which
* generator.
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* cfg - which PWM modulator and generator to use, use TIVA_ADC_PWM_TRIG
@@ -762,7 +762,7 @@ void tiva_adc_sse_pwm_trig(uint8_t adc, uint8_t sse, uint32_t cfg)
* Sets the interrupt state of an ADC's sample sequencer (SSE). SSEs must
* be enabled before setting interrupt state.
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* state - sample sequencer enable/disable interrupt state
@@ -799,7 +799,7 @@ void tiva_adc_sse_int_enable(uint8_t adc, uint8_t sse, bool state)
* Description:
* Returns interrupt status for the specificed SSE
*
- * Input parameters:
+ * Input Parameters:
* adc - which ADC peripherals' interrupt status to retrieve
* sse - which SSE interrupt status to retrieve
*
@@ -818,7 +818,7 @@ bool tiva_adc_sse_int_status(uint8_t adc, uint8_t sse)
* Description:
* Clears the interrupt bit for the SSE.
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* state - sample sequencer
@@ -839,11 +839,11 @@ void tiva_adc_sse_clear_int(uint8_t adc, uint8_t sse)
* The input data buffer MUST be as large or larger than the sample sequencer.
* otherwise
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
*
- * Return value:
+ * Returned Value:
* number of steps read from FIFO.
*
****************************************************************************/
@@ -880,7 +880,7 @@ uint8_t tiva_adc_sse_data(uint8_t adc, uint8_t sse, int32_t *buf)
* priority value ranges from 0 to 3, 0 being the highest priority, 3 being
* the lowest. There can be no duplicate values.
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* priority - conversion priority
@@ -906,7 +906,7 @@ void tiva_adc_sse_priority(uint8_t adc, uint8_t sse, uint8_t priority)
*
* *SSEMUX only supported on TM4C129 devices
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* chn - sample sequencer step
@@ -940,7 +940,7 @@ void tiva_adc_sse_register_chn(uint8_t adc, uint8_t sse, uint8_t chn,
* Description:
* Sets the differential capability for a SSE. !! UNSUPPORTED
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* chn - sample sequencer channel
@@ -970,7 +970,7 @@ void tiva_adc_sse_differential(uint8_t adc, uint8_t sse, uint8_t chn, uint32_t d
* This is not available on all devices, however on devices that do not
* support this feature these reserved bits are ignored on write access.
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* chn - sample sequencer channel
@@ -1007,7 +1007,7 @@ void tiva_adc_sse_sample_hold_time(uint8_t adc, uint8_t sse,
*
* *Comparator/Differential functionality is unsupported and ignored.
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
* chn - sample sequencer channel
@@ -1029,7 +1029,7 @@ void tiva_adc_sse_step_cfg(uint8_t adc, uint8_t sse, uint8_t chn, uint8_t cfg)
* Dump all configured registers for the given ADC and SSE. This should
* only be used to verify that configuration routines were accurate.
*
- * Input parameters:
+ * Input Parameters:
* adc - peripheral state
* sse - sample sequencer
*
diff --git a/arch/arm/src/tiva/tiva_adclow.c b/arch/arm/src/tiva/tiva_adclow.c
index 577a430d2f59103922cf151946322917e6837a43..3d7262b0153c62b1855f698f227698807aa20c3c 100644
--- a/arch/arm/src/tiva/tiva_adclow.c
+++ b/arch/arm/src/tiva/tiva_adclow.c
@@ -655,7 +655,7 @@ static int tiva_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
* are disabled when this function runs. tiva_adc_read will
* re-enable interrupts when it completes processing all pending events.
*
- * Input Parameters
+ * Input Parameters:
* arg - The ADC SSE data structure cast to (void *)
*
* Returned Value:
diff --git a/arch/arm/src/tiva/tiva_gpioirq.c b/arch/arm/src/tiva/tiva_gpioirq.c
index 112887f8bf4bd049717188c797c68affeb835871..a5d0e3dbe3edd6b21de1d1c0216052c157e0824f 100644
--- a/arch/arm/src/tiva/tiva_gpioirq.c
+++ b/arch/arm/src/tiva/tiva_gpioirq.c
@@ -672,7 +672,7 @@ int tiva_gpioirqinitialize(void)
* disabled to stop further interrupts. Otherwise, the new isr is linked
* and the pin's interrupt mask is set.
*
- * Returns:
+ * Returned Value:
* Zero (OK) is returned on success. Otherwise a negated errno value is
* return to indicate the nature of the failure.
*
diff --git a/arch/arm/src/tiva/tiva_i2c.h b/arch/arm/src/tiva/tiva_i2c.h
index 33acca1116ca53075dce38f3b3c4a923d53560af..c43e167f8688fe078b2feea51e1591e491303888 100644
--- a/arch/arm/src/tiva/tiva_i2c.h
+++ b/arch/arm/src/tiva/tiva_i2c.h
@@ -59,7 +59,7 @@
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
@@ -75,7 +75,7 @@ FAR struct i2c_master_s *tiva_i2cbus_initialize(int port);
* Description:
* De-initialize the selected I2C port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the tiva_i2cbus_initialize()
*
* Returned Value:
diff --git a/arch/arm/src/tiva/tiva_pwm.c b/arch/arm/src/tiva/tiva_pwm.c
index 0e882f0f7c11ccfff7b3564d7ebd4babd1a2f1ec..b25e27225560f9a3db2fbf3efeeab9ba8299146d 100644
--- a/arch/arm/src/tiva/tiva_pwm.c
+++ b/arch/arm/src/tiva/tiva_pwm.c
@@ -421,7 +421,7 @@ static inline void tiva_pwm_putreg(struct tiva_pwm_chan_s *chan,
* use. It will not, however, output pulses until the start method is
* called.
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -457,7 +457,7 @@ static int tiva_pwm_setup(FAR struct pwm_lowerhalf_s *dev)
* stop pulsed output, free any resources, disable the timer hardware, and
* put the system into the lowest possible power usage state
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -487,7 +487,7 @@ static int tiva_pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
* handle - This is the handle that was provided to the lower-half
@@ -569,7 +569,7 @@ static int tiva_pwm_start(FAR struct pwm_lowerhalf_s *dev,
* Description:
* Configure PWM registers and start the PWM timer
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
*
@@ -659,7 +659,7 @@ static inline int tiva_pwm_timer(FAR struct tiva_pwm_chan_s *chan,
* Description:
* Stop the pulsed output and reset the timer resources
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
@@ -692,7 +692,7 @@ static int tiva_pwm_stop(FAR struct pwm_lowerhalf_s *dev)
* Description:
* Lower-half logic may support platform-specific ioctl commands
*
- * Input parameters:
+ * Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* cmd - The ioctl command
* arg - The argument accompanying the ioctl command
diff --git a/arch/arm/src/tiva/tiva_qencoder.c b/arch/arm/src/tiva/tiva_qencoder.c
index b25f6dce183f4c4896a9edb1b91bdcefde73aa44..a10eb6577d1a93c19dc120d8196e32bec45ca1ea 100644
--- a/arch/arm/src/tiva/tiva_qencoder.c
+++ b/arch/arm/src/tiva/tiva_qencoder.c
@@ -177,7 +177,7 @@ static inline void tiva_qe_putreg(struct tiva_qe_s *qe, unsigned int offset,
* use. It will not, however, output pulses until the start method is
* called.
*
- * Input parameters:
+ * Input Parameters:
* lower - A reference to the lower half QEI driver state structure
*
* Returned Value:
@@ -260,7 +260,7 @@ static int tiva_qe_setup(FAR struct qe_lowerhalf_s *lower)
* stop data collection, free any resources, disable the timer hardware, and
* put the system into the lowest possible power usage state
*
- * Input parameters:
+ * Input Parameters:
* lower - A reference to the lower half QEI driver state structure
*
* Returned Value:
@@ -287,7 +287,7 @@ static int tiva_qe_shutdown(FAR struct qe_lowerhalf_s *lower)
* Description:
* Reset the position measurement to zero.
*
- * Input parameters:
+ * Input Parameters:
* lower - A reference to the lower half QEI driver state structure
*
* Returned Value:
@@ -312,7 +312,7 @@ static int tiva_qe_reset(FAR struct qe_lowerhalf_s *lower)
* Description:
* Return the position mesaured by QEI.
*
- * Input parameters:
+ * Input Parameters:
* lower - A reference to the lower half QEI driver state structure
* pos - pointer to the position returned
*
@@ -338,7 +338,7 @@ static int tiva_qe_position(FAR struct qe_lowerhalf_s *lower, FAR int32_t *pos)
* Description:
* Lower-half logic may support platform-specific ioctl commands
*
- * Input parameters:
+ * Input Parameters:
* lower - A reference to the lower half QEI driver state structure
* cmd - The ioctl command
* arg - The argument accompanying the ioctl command
@@ -383,7 +383,7 @@ static int tiva_qe_ioctl(FAR struct qe_lowerhalf_s *lower, int cmd,
* Description:
* Return the direction mesaured by QEI.
*
- * Input parameters:
+ * Input Parameters:
* qe - A reference to the TIVA QEI structure
* dir - pointer to the direction returned
*
@@ -414,7 +414,7 @@ static int tiva_qe_direction(FAR struct tiva_qe_s *qe, unsigned long *dir)
* Description:
* Return the velocity (A/B pulses per second) mesaured by QEI.
*
- * Input parameters:
+ * Input Parameters:
* qe - A reference to the TIVA QEI structure
*
* Returned Value:
@@ -437,7 +437,7 @@ static int tiva_qe_velocity(FAR struct tiva_qe_s *qe, unsigned long *vel)
* Description:
* Set reset mode as MAXPOS and also set maxpos value
*
- * Input parameters:
+ * Input Parameters:
* qe - A reference to the TIVA QEI structure
* ppr - pulses per round of encoder
*
diff --git a/arch/arm/src/tiva/tiva_ssi.c b/arch/arm/src/tiva/tiva_ssi.c
index bd224363b07fa25a4aee39f00f62e319e1f835bb..d64e4dccddf3a14bfe18bdc7326bdf6add73a225 100644
--- a/arch/arm/src/tiva/tiva_ssi.c
+++ b/arch/arm/src/tiva/tiva_ssi.c
@@ -1495,7 +1495,7 @@ static void ssi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
* required. Theregore, all GPIO chip management is deferred to board-
* specific logic.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SSI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/tiva/tiva_ssi.h b/arch/arm/src/tiva/tiva_ssi.h
index d0976c2aee965aa4cb141ff6d018cd24cebd4242..8027ae33664124fb1e1661e4b841e51585fa2369 100644
--- a/arch/arm/src/tiva/tiva_ssi.h
+++ b/arch/arm/src/tiva/tiva_ssi.h
@@ -70,7 +70,7 @@ extern "C"
* required. Theregore, all GPIO chip management is deferred to board-
* specific logic.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SSI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/tiva/tiva_timer.h b/arch/arm/src/tiva/tiva_timer.h
index 547cd117041737a23e8d420c81cf5226d1638c3a..f5d9c6f9fe1c0b1b70efbcf4202d6c591e08dc0e 100644
--- a/arch/arm/src/tiva/tiva_timer.h
+++ b/arch/arm/src/tiva/tiva_timer.h
@@ -835,7 +835,7 @@ static inline void tiva_gptm0_synchronize(uint32_t sync)
* form /dev/timer0
* config - 32-bit timer configuration values.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
diff --git a/arch/arm/src/tiva/tiva_timerlow32.c b/arch/arm/src/tiva/tiva_timerlow32.c
index 91f44618b00f2d3408d6d3def8ae3c3e98192481..9807588ec265518ed79624b49a50196d71c5f629 100644
--- a/arch/arm/src/tiva/tiva_timerlow32.c
+++ b/arch/arm/src/tiva/tiva_timerlow32.c
@@ -133,7 +133,7 @@ static const struct timer_ops_s g_timer_ops =
* priv - A pointer to a private timer driver lower half instance
* usecs - The number of usecs to convert
*
- * Returned Values:
+ * Returned Value:
* The time converted to clock ticks.
*
****************************************************************************/
@@ -161,7 +161,7 @@ static uint32_t tiva_usec2ticks(struct tiva_lowerhalf_s *priv, uint32_t usecs)
* priv - A pointer to a private timer driver lower half instance
* usecs - The number of ticks to convert
*
- * Returned Values:
+ * Returned Value:
* The time converted to microseconds.
*
****************************************************************************/
@@ -189,7 +189,7 @@ static uint32_t tiva_ticks2usec(struct tiva_lowerhalf_s *priv, uint32_t ticks)
* priv - A pointer to a private timer driver lower half instance
* timeout - The new timeout value in microseconds.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -224,7 +224,7 @@ static void tiva_timeout(struct tiva_lowerhalf_s *priv, uint32_t timeout)
* Input Parameters:
* Usual 32-bit timer interrupt handler arguments.
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -287,7 +287,7 @@ static void tiva_timer_handler(TIMER_HANDLE handle, void *arg, uint32_t status)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -324,7 +324,7 @@ static int tiva_start(struct timer_lowerhalf_s *lower)
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -362,7 +362,7 @@ static int tiva_stop(struct timer_lowerhalf_s *lower)
* driver state structure.
* status - The location to return the status information.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -415,7 +415,7 @@ static int tiva_getstatus(struct timer_lowerhalf_s *lower,
* driver state structure.
* timeout - The new timeout value in microseconds.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -456,7 +456,7 @@ static int tiva_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout)
* function pointer is NULL, then the reset-on-expiration
* behavior is restored,
*
- * Returned Values:
+ * Returned Value:
* The previous timer expiration function pointer or NULL is there was
* no previous function pointer.
*
@@ -496,7 +496,7 @@ static void tiva_setcallback(struct timer_lowerhalf_s *lower,
* interpretation of this argument depends on the particular
* command.
*
- * Returned Values:
+ * Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
@@ -535,7 +535,7 @@ static int tiva_ioctl(struct timer_lowerhalf_s *lower, int cmd,
* form /dev/timer0
* config - 32-bit timer configuration values.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
diff --git a/arch/arm/src/tiva/tm4c_ethernet.c b/arch/arm/src/tiva/tm4c_ethernet.c
index 3458db363cda53c93fafa766c9eb98be8c5a9ca5..be2dd123502b0d194e60f1e47faedc1431d136b3 100644
--- a/arch/arm/src/tiva/tm4c_ethernet.c
+++ b/arch/arm/src/tiva/tm4c_ethernet.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/tiva/tm4c_ethernet.c
*
- * Copyright (C) 2014-2015, 2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014-2015, 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -733,7 +733,7 @@ static int tiva_addmac(struct net_driver_s *dev, FAR const uint8_t *mac);
#ifdef CONFIG_NET_IGMP
static int tiva_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac);
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
static int tiva_ioctl(struct net_driver_s *dev, int cmd,
unsigned long arg);
#endif
@@ -2860,59 +2860,61 @@ static void tiva_rxdescinit(FAR struct tiva_ethmac_s *priv)
*
****************************************************************************/
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
static int tiva_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
{
int ret;
switch (cmd)
- {
-#ifdef CONFIG_TIVA_PHY_INTERRUPTS
- case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
- struct mii_iotcl_notify_s *req = (struct mii_iotcl_notify_s *)((uintptr_t)arg);
-
- ret = phy_notify_subscribe(dev->d_ifname, req->pid, req->signo, req->arg);
- if (ret == OK)
+#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_TIVA_PHY_INTERRUPTS
+ case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
- /* Enable PHY link up/down interrupts */
+ struct mii_iotcl_notify_s *req = (struct mii_iotcl_notify_s *)((uintptr_t)arg);
- tiva_phy_intenable(true);
+ ret = phy_notify_subscribe(dev->d_ifname, req->pid, req->signo, req->arg);
+ if (ret == OK)
+ {
+ /* Enable PHY link up/down interrupts */
+
+ tiva_phy_intenable(true);
+ }
}
- }
- break;
+ break;
#endif
- case SIOCGMIIPHY: /* Get MII PHY address */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- req->phy_id = CONFIG_TIVA_PHYADDR;
- ret = OK;
- }
- break;
+ case SIOCGMIIPHY: /* Get MII PHY address */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ req->phy_id = CONFIG_TIVA_PHYADDR;
+ ret = OK;
+ }
+ break;
- case SIOCGMIIREG: /* Get register from MII PHY */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- ret = tiva_phyread(req->phy_id, req->reg_num, &req->val_out);
- }
- break;
+ case SIOCGMIIREG: /* Get register from MII PHY */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ ret = tiva_phyread(req->phy_id, req->reg_num, &req->val_out);
+ }
+ break;
- case SIOCSMIIREG: /* Set register in MII PHY */
- {
- struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
- ret = tiva_phywrite(req->phy_id, req->reg_num, req->val_in);
- }
- break;
+ case SIOCSMIIREG: /* Set register in MII PHY */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ ret = tiva_phywrite(req->phy_id, req->reg_num, req->val_in);
+ }
+ break;
+#endif /* CONFIG_NETDEV_PHY_IOCTL */
- default:
- ret = -ENOTTY;
- break;
- }
+ default:
+ ret = -ENOTTY;
+ break;
+ }
return ret;
}
-#endif /* CONFIG_NETDEV_PHY_IOCTL */
+#endif /* CONFIG_NETDEV_IOCTL */
/****************************************************************************
* Function: tiva_phy_intenable
@@ -4040,7 +4042,7 @@ int tiva_ethinitialize(int intf)
priv->dev.d_addmac = tiva_addmac; /* Add multicast MAC address */
priv->dev.d_rmmac = tiva_rmmac; /* Remove multicast MAC address */
#endif
-#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = tiva_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void *)g_tiva_ethmac; /* Used to recover private state from dev */
diff --git a/arch/arm/src/tms570/Make.defs b/arch/arm/src/tms570/Make.defs
index 9d1d32f627bcbae1f7cedee949733e3f7f60b49a..c1103a2f012ae7d7ab581e44ccd4aebdf21784b7 100644
--- a/arch/arm/src/tms570/Make.defs
+++ b/arch/arm/src/tms570/Make.defs
@@ -42,7 +42,7 @@ HEAD_ASRC = arm_vectortab.S
CMN_ASRCS += arm_vectors.S arm_head.S arm_fullcontextrestore.S
CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S arm_vfork.S
-CMN_ASRCS += arm_testset.S
+CMN_ASRCS += arm_testset.S arm_fetchadd.S
CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S
CMN_ASRCS += cp15_invalidate_dcache_all.S
diff --git a/arch/arm/src/tms570/tms570_irq.c b/arch/arm/src/tms570/tms570_irq.c
index 11d606d637e5cc6a5c26d5cda365e8d9d9e8bd72..33f2890b749f7762d3621921b6fc7f05b02a674b 100644
--- a/arch/arm/src/tms570/tms570_irq.c
+++ b/arch/arm/src/tms570/tms570_irq.c
@@ -198,7 +198,7 @@ void up_irqinitialize(void)
* the irq number of the interrupt and then to call arm_doirq to dispatch
* the interrupt.
*
- * Input parameters:
+ * Input Parameters:
* regs - A pointer to the register save area on the stack.
*
****************************************************************************/
@@ -240,7 +240,7 @@ uint32_t *arm_decodeirq(uint32_t *regs)
* the irq number of the interrupt and then to call arm_doirq to dispatch
* the interrupt.
*
- * Input parameters:
+ * Input Parameters:
* regs - A pointer to the register save area on the stack.
*
****************************************************************************/
diff --git a/arch/arm/src/tms570/tms570_selftest.h b/arch/arm/src/tms570/tms570_selftest.h
index 696bc54fe3b1382d3b95321b9fc1f873fe16ad2f..727510fe329c6e1825a5fb8ce8fbd1e0fc19a864 100644
--- a/arch/arm/src/tms570/tms570_selftest.h
+++ b/arch/arm/src/tms570/tms570_selftest.h
@@ -90,7 +90,7 @@ void tms570_memtest_selftest(void);
* Description:
* Start the memory test on the selected set of RAMs.
*
- * Input Paramters:
+ * Input Parameters:
* rinfol - The OR of each RAM grouping bit. See the PBIST_RINFOL*
* definitions in chip/tms570_pbist.h
*
diff --git a/arch/arm/src/xmc4/Make.defs b/arch/arm/src/xmc4/Make.defs
index 76ddb95391e3abc6aaeea5b0e97cd213e783a977..2b6fb0c62c3570aab259fdf893eafc5b80efe9a9 100644
--- a/arch/arm/src/xmc4/Make.defs
+++ b/arch/arm/src/xmc4/Make.defs
@@ -43,7 +43,7 @@ CMN_UASRCS =
CMN_UCSRCS =
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
-CMN_ASRCS += up_testset.S vfork.S
+CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S
CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c
CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_initialize.c up_memfault.c
diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h
index 2d22084252de1c253174777c9ad478bf12b2f7ae..afa4d0f8a7f37d3e0ac7b0b7034776c21d8b6bfd 100644
--- a/arch/arm/src/xmc4/chip/xmc4_scu.h
+++ b/arch/arm/src/xmc4/chip/xmc4_scu.h
@@ -938,7 +938,7 @@
#define SCU_SLEEPCR_SYSSEL (1 << 0) /* Bit 0: System Clock Selection Value */
# define SCU_SLEEPCR_SYSSEL_OFI (0) /* 0=fOFI */
-# define SCU_SLEEPCR_SYSSEL_ PLL (1 << 0) /* 1=fPLL */
+# define SCU_SLEEPCR_SYSSEL_FPLL (1 << 0) /* 1=fPLL */
#define SCU_SLEEPCR_USBCR (1 << 16) /* Bit 6: USB Clock Control in Sleep Mode */
#define SCU_SLEEPCR_MMCCR (1 << 17) /* Bit 17: MMC Clock Control in Sleep Mode */
#define SCU_SLEEPCR_ETH0CR (1 << 18) /* Bit 18: Ethernet Clock Control in Sleep Mode */
diff --git a/arch/arm/src/xmc4/chip/xmc4_usic.h b/arch/arm/src/xmc4/chip/xmc4_usic.h
index 0ca992d548f2ca56b7e5f2be40906ba30b7c1319..af43e11f9000661e610466ab07f75eea86e36d03 100644
--- a/arch/arm/src/xmc4/chip/xmc4_usic.h
+++ b/arch/arm/src/xmc4/chip/xmc4_usic.h
@@ -465,7 +465,12 @@
# define USIC_BRG_PDIV(n) ((uint32_t)(n) << USIC_BRG_PDIV_SHIFT)
#define USIC_BRG_SCLKOSEL (1 << 28) /* Bit 28: Shift Clock Output Select */
#define USIC_BRG_MCLKCFG (1 << 29) /* Bit 29: Master Clock Configuration */
-#define USIC_BRG_SCLKCFG (1 << 30) /* Bit 30: Shift Clock Output Configuration */
+#define USIC_BRG_SCLKCFG_SHIFT 30 /* Bits 30-31: Shift Clock Output Configuration */
+#define USIC_BRG_SCLKCFG_MASK (3 << USIC_BRG_SCLKCFG_SHIFT)
+# define USIC_BRG_SCLKCFG_NOINVNODLY (0 << USIC_BRG_SCLKCFG_SHIFT) /* No inverted signal and no delay */
+# define USIC_BRG_SCLKCFG_INVNODLY (1 << USIC_BRG_SCLKCFG_SHIFT) /* Inverted signal and no delay */
+# define USIC_BRG_SCLKCFG_NOINVDLY (2 << USIC_BRG_SCLKCFG_SHIFT) /* No inverted signal and 1/2 delay */
+# define USIC_BRG_SCLKCFG_INVDLY (3 << USIC_BRG_SCLKCFG_SHIFT) /* Inverted signal and 1/2 delay */
/* Interrupt Node Pointer Register */
diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c
index eeb71dbe0b476adb8e31ca1c5f268aea7c991cac..9d6cc0621eb93a7a3a31faf7cf04c6466bb82d01 100644
--- a/arch/arm/src/xmc4/xmc4_clockconfig.c
+++ b/arch/arm/src/xmc4/xmc4_clockconfig.c
@@ -58,6 +58,7 @@
#include "up_arch.h"
#include "chip/xmc4_scu.h"
#include "xmc4_clockconfig.h"
+#include "chip/xmc4_ports.h"
#include
@@ -105,7 +106,7 @@
#define CLKSET_VALUE (0x00000000)
#define USBCLKCR_VALUE (0x00010000)
-#if BOARD_PBDIV == 1
+#if BOARD_PLL_PBDIV == 1
# define PBCLKCR_VALUE SCU_PBCLKCR_PBDIV_FCPU
#else /* BOARD_PBDIV == 2 */
# define PBCLKCR_VALUE SCU_PBCLKCR_PBDIV_DIV2
@@ -387,8 +388,8 @@ void xmc4_clock_configure(void)
/* Setup fSYS clock */
- regval = (BOARD_ENABLE_PLL << SCU_SYSCLKCR_SYSSEL);
- regval |= SCU_SYSCLKCR_SYSDIV(BOARD_SYSDIV);
+ regval = (BOARD_ENABLE_PLL ? SCU_SYSCLKCR_SYSSEL : 0);
+ regval |= SCU_SYSCLKCR_SYSDIV(BOARD_PLL_SYSDIV);
putreg32(regval, XMC4_SCU_SYSCLKCR);
/* Setup peripheral clock divider */
@@ -411,7 +412,7 @@ void xmc4_clock_configure(void)
/* Setup EBU clock */
- regval = SCU_EBUCLKCR_EBUDIV(BOARD_EBUDIV);
+ regval = SCU_EBUCLKCR_EBUDIV(BOARD_PLL_EBUDIV);
putreg32(regval, XMC4_SCU_EBUCLKCR);
#ifdef BOARD_ENABLE_USBPLL
@@ -423,7 +424,7 @@ void xmc4_clock_configure(void)
/* Setup EXT */
regval = (BOARD_EXT_SOURCE << SCU_EXTCLKCR_ECKSEL_SHIFT);
- regval |= SCU_EXTCLKCR_ECKDIV(BOARD_EXTDIV);
+ regval |= SCU_EXTCLKCR_ECKDIV(BOARD_PLL_ECKDIV);
putreg32(regval, XMC4_SCU_EXTCLKCR);
#if BOARD_ENABLE_PLL
@@ -561,4 +562,30 @@ void xmc4_clock_configure(void)
/* Enable selected clocks */
putreg32(CLKSET_VALUE, XMC4_SCU_CLKSET);
+
+#if BOARD_PLL_CLOCKSRC_XTAL == 1
+ regval = SCU_SLEEPCR_SYSSEL_FPLL;
+ putreg32(regval, XMC4_SCU_SLEEPCR);
+#endif /* BOARD_PLL_CLOCKSRC_XTAL == 1 */
+
+#if BOARD_EXTCKL_ENABLE
+#if BOARD_EXTCLK_PIN == EXTCLK_PIN_P0_8
+ /* enable EXTCLK output on P0.8 */
+ regval = getreg32(XMC4_PORT0_HWSEL);
+ regval &= ~PORT_HWSEL_HW8_MASK;
+ putreg32(regval, XMC4_PORT0_HWSEL);
+
+ regval = getreg32(XMC4_PORT0_PDR1);
+ regval &= ~PORT_PDR1_PD8_MASK;
+ putreg32(regval, XMC4_PORT0_PDR1);
+
+ regval = getreg32(XMC4_PORT0_IOCR8);
+ regval &= ~PORT_IOCR8_PC8_MASK;
+ regval |= PORT_IOCR8_PC8(0x11); /* push-pull output, alt func 1 */
+ putreg32(regval, XMC4_PORT0_IOCR8);
+#else
+ /* enable EXTCLK output on P1.15 */
+# warn "Not yet implemented"
+#endif
+#endif
}
diff --git a/arch/arm/src/xmc4/xmc4_i2c.h b/arch/arm/src/xmc4/xmc4_i2c.h
index f4a167b713da70f745271b81cd65db2ad073c256..74f8acb1684b8a0280772a6af4f523a3c7ec3834 100644
--- a/arch/arm/src/xmc4/xmc4_i2c.h
+++ b/arch/arm/src/xmc4/xmc4_i2c.h
@@ -57,7 +57,7 @@
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
@@ -73,7 +73,7 @@ FAR struct i2c_master_s *xmc4_i2cbus_initialize(int port);
* Description:
* De-initialize the selected I2C port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the lpc43_i2cbus_initialize()
*
* Returned Value:
diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c
index fef3ac077343de3e9ec41c502ed8034652afbdf9..36a23e91d768d4f8632d1a5fd129820eed1f98bd 100644
--- a/arch/arm/src/xmc4/xmc4_serial.c
+++ b/arch/arm/src/xmc4/xmc4_serial.c
@@ -1073,7 +1073,7 @@ void xmc4_earlyserialinit(void)
* Input Parameters:
* None
*
- * Returns Value:
+ * Returned Value:
* None
*
****************************************************************************/
diff --git a/arch/arm/src/xmc4/xmc4_spi.h b/arch/arm/src/xmc4/xmc4_spi.h
index 5113665eda26e05fd911db8e65c08b63efad90c6..73f4d69d4d92d84da1d6903a4f64238c8c534310 100644
--- a/arch/arm/src/xmc4/xmc4_spi.h
+++ b/arch/arm/src/xmc4/xmc4_spi.h
@@ -75,7 +75,7 @@ struct spi_dev_s;
* Description:
* Initialize the selected SPI bus
*
- * Input Parameter:
+ * Input Parameters:
* bus number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/arm/src/xmc4/xmc4_start.c b/arch/arm/src/xmc4/xmc4_start.c
index d1a1b4a1c3f79c6a866ffe67c2794481ec6c4836..5e65aecaac7ca80afe719ddf4b62427cde9627ad 100644
--- a/arch/arm/src/xmc4/xmc4_start.c
+++ b/arch/arm/src/xmc4/xmc4_start.c
@@ -396,9 +396,17 @@ void __start(void)
/* Then start NuttX */
+#ifdef CONFIG_STACK_COLORATION
+ /* Set the IDLE stack to the coloration value and jump into os_start() */
+
+ go_os_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE);
+#else
+ /* Call os_start() */
+
os_start();
/* Shouldn't get here */
for (; ; );
+#endif
}
diff --git a/arch/avr/src/at32uc3/at32uc3_gpioirq.c b/arch/avr/src/at32uc3/at32uc3_gpioirq.c
index 66e82476554a7ddedcc92b2e395b74a059a30276..03b704e08adf11ca0f70c10b81c2498ddb36c2f7 100644
--- a/arch/avr/src/at32uc3/at32uc3_gpioirq.c
+++ b/arch/avr/src/at32uc3/at32uc3_gpioirq.c
@@ -81,7 +81,7 @@ static struct g_gpiohandler_s g_gpiohandler[NR_GPIO_IRQS];
/****************************************************************************
* Name: gpio_baseaddress
*
- * Input:
+ * Input Parameters:
* irq - A IRQ number in the range of 0 to NR_GPIO_IRQS.
*
* Description:
@@ -114,7 +114,7 @@ static inline uint32_t gpio_baseaddress(unsigned int irq)
/****************************************************************************
* Name: gpio_pin
*
- * Input:
+ * Input Parameters:
* irq - A IRQ number in the range of 0 to NR_GPIO_IRQS.
*
* Description:
diff --git a/arch/avr/src/avr/avr.h b/arch/avr/src/avr/avr.h
index 0326d6d8488af3b8cf03c68d63afcb6fdae19bda..2e0c72ee38f9dafa6673b8742f6e51994050f764 100644
--- a/arch/avr/src/avr/avr.h
+++ b/arch/avr/src/avr/avr.h
@@ -144,7 +144,7 @@ uint8_t *up_doirq(uint8_t irq, uint8_t *regs);
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/avr/src/avr/up_blocktask.c b/arch/avr/src/avr/up_blocktask.c
index b03b967badadebafc3e5fb5ef845bb3d238e5730..868a517b404cfaef7fb4620b31ecd6e9dbcb1f62 100644
--- a/arch/avr/src/avr/up_blocktask.c
+++ b/arch/avr/src/avr/up_blocktask.c
@@ -61,7 +61,7 @@
* the ready to run list must be stopped. Save its context
* and move it to the inactive list specified by task_state.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to a task in the ready-to-run list (normally
* the task at the head of the list). It most be
* stopped, its context saved and moved into one of the
diff --git a/arch/avr/src/avr/up_checkstack.c b/arch/avr/src/avr/up_checkstack.c
index 725a234d1a3f482626d927192f4fbf2aa533911d..96152af0d6bb53027d5ae0f5f9b32be5cc15be17 100644
--- a/arch/avr/src/avr/up_checkstack.c
+++ b/arch/avr/src/avr/up_checkstack.c
@@ -74,7 +74,7 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size);
* alloc - Allocation base address of the stack
* size - The size of the stack in bytes
*
- * Returned value:
+ * Returned Value:
* The estimated amount of stack space used.
*
****************************************************************************/
@@ -154,7 +154,7 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size)
* Input Parameters:
* None
*
- * Returned value:
+ * Returned Value:
* The estimated amount of stack space used.
*
****************************************************************************/
diff --git a/arch/avr/src/avr/up_createstack.c b/arch/avr/src/avr/up_createstack.c
index 54efb1a3fb53f917fb55ac1b18116eda1d513715..d54b2049fe63e4008b2903ca820bf376a08118df 100644
--- a/arch/avr/src/avr/up_createstack.c
+++ b/arch/avr/src/avr/up_createstack.c
@@ -81,7 +81,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
* the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The requested stack size. At least this much
* must be allocated.
diff --git a/arch/avr/src/avr/up_reprioritizertr.c b/arch/avr/src/avr/up_reprioritizertr.c
index 846b59becf62f3f90196124d25eae4a734d899d8..28323ffbb73f606706f08f400e2982633a39cf44 100644
--- a/arch/avr/src/avr/up_reprioritizertr.c
+++ b/arch/avr/src/avr/up_reprioritizertr.c
@@ -67,7 +67,7 @@
* the priority of the current, running task and it now has the
* priority.
*
- * Inputs:
+ * Input Parameters:
* tcb: The TCB of the task that has been reprioritized
* priority: The new task priority
*
diff --git a/arch/avr/src/avr/up_spi.c b/arch/avr/src/avr/up_spi.c
index 24a4f377cbd09f2932a90e03951ef49adaaf7da7..98742cf4e20a185776a72e12946ae2dcc16311ab 100644
--- a/arch/avr/src/avr/up_spi.c
+++ b/arch/avr/src/avr/up_spi.c
@@ -440,7 +440,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/avr/src/avr/up_stackframe.c b/arch/avr/src/avr/up_stackframe.c
index 0f7d3a87463e1148abbd400b557edd8843fc142f..71c38c8aa441291da17fe40405040771db4f7223 100644
--- a/arch/avr/src/avr/up_stackframe.c
+++ b/arch/avr/src/avr/up_stackframe.c
@@ -86,7 +86,7 @@
* been removed from the stack. This will still be the initial value
* of the stack pointer when the task is started.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - frame_size: The size of the stack frame to allocate.
*
diff --git a/arch/avr/src/avr/up_switchcontext.S b/arch/avr/src/avr/up_switchcontext.S
index 3fc1b6ae42e83418d6d2fc069c9f1066530276bb..c5613b9814eda7c59c2d44955c638fe7e37e4bd7 100644
--- a/arch/avr/src/avr/up_switchcontext.S
+++ b/arch/avr/src/avr/up_switchcontext.S
@@ -74,7 +74,7 @@
* r24-r25: savregs
* r22-r23: restoreregs
*
- * Return:
+ * Returned Value:
* up_switchcontext forces a context switch to the task "canned" in restoreregs.
* It does not 'return' in the normal sense, rather, it will context switch back
* to the function point. When it does 'return,' it is because the blocked
@@ -106,7 +106,7 @@ up_switchcontext:
/****************************************************************************
* Name: up_fullcontextrestore
*
- * Descripion:
+ * Description:
* Restore the full-running context of a thread.
*
* Input Parameters:
diff --git a/arch/avr/src/avr/up_unblocktask.c b/arch/avr/src/avr/up_unblocktask.c
index d70b65405cd2af723ba9e307ab329776c5f5b120..cea4c6df79c1c7c68eb4bea6c5af3d5e212fa3e1 100644
--- a/arch/avr/src/avr/up_unblocktask.c
+++ b/arch/avr/src/avr/up_unblocktask.c
@@ -60,7 +60,7 @@
* but has been prepped to execute. Move the TCB to the
* ready-to-run list, restore its context, and start execution.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to the tcb to be unblocked. This tcb is
* in one of the waiting tasks lists. It must be moved to
* the ready-to-run list and, if it is the highest priority
diff --git a/arch/avr/src/avr/up_usestack.c b/arch/avr/src/avr/up_usestack.c
index 0546d8c770ad85b02b724717dfb79d93919349f0..1e451d883c24fa3a425411b5ca3d38684c6ba868 100644
--- a/arch/avr/src/avr/up_usestack.c
+++ b/arch/avr/src/avr/up_usestack.c
@@ -79,7 +79,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The
* initial value of the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The allocated stack size.
*
diff --git a/arch/avr/src/avr32/up_blocktask.c b/arch/avr/src/avr32/up_blocktask.c
index 8449d82cbe0e49331f09abae60b32b7530dcffe0..3e9304be28e2961922665ea7ed3e6d7c99efbf8b 100644
--- a/arch/avr/src/avr32/up_blocktask.c
+++ b/arch/avr/src/avr32/up_blocktask.c
@@ -62,7 +62,7 @@
* the ready to run list must be stopped. Save its context
* and move it to the inactive list specified by task_state.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to a task in the ready-to-run list (normally
* the task at the head of the list). It most be
* stopped, its context saved and moved into one of the
diff --git a/arch/avr/src/avr32/up_createstack.c b/arch/avr/src/avr32/up_createstack.c
index 6bc17519bc26127bace92f63bb728a02f03f1971..2244e9ba4e4860ca716a3789b5ad5546b207f7dd 100644
--- a/arch/avr/src/avr32/up_createstack.c
+++ b/arch/avr/src/avr32/up_createstack.c
@@ -81,7 +81,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
* the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The requested stack size. At least this much
* must be allocated.
diff --git a/arch/avr/src/avr32/up_fullcontextrestore.S b/arch/avr/src/avr32/up_fullcontextrestore.S
index 8b0910998347d03e07e228a86879143577ddf3c5..45019c424bf8ff5fb2b62adce55c63d1a4dcb1dc 100644
--- a/arch/avr/src/avr32/up_fullcontextrestore.S
+++ b/arch/avr/src/avr32/up_fullcontextrestore.S
@@ -53,7 +53,7 @@
/****************************************************************************
* Name: up_fullcontextrestore
*
- * Descripion:
+ * Description:
* Restore the full-running contex of a thread.
*
* NOTE: Thus function must handle one very strange case. That is when
diff --git a/arch/avr/src/avr32/up_reprioritizertr.c b/arch/avr/src/avr32/up_reprioritizertr.c
index 1ce7a4c406e1a9c8e2ee83dcf4ff0d760169bd49..eb8023d72082f8929d97c9fc0cabe39f7aab6de7 100644
--- a/arch/avr/src/avr32/up_reprioritizertr.c
+++ b/arch/avr/src/avr32/up_reprioritizertr.c
@@ -68,7 +68,7 @@
* the priority of the current, running task and it now has the
* priority.
*
- * Inputs:
+ * Input Parameters:
* tcb: The TCB of the task that has been reprioritized
* priority: The new task priority
*
diff --git a/arch/avr/src/avr32/up_stackframe.c b/arch/avr/src/avr32/up_stackframe.c
index acd10d9216f658b7fcab260564d8fc01f6bb7c57..dfcf12800184d97fcc498ad22e521f2c57c730ef 100644
--- a/arch/avr/src/avr32/up_stackframe.c
+++ b/arch/avr/src/avr32/up_stackframe.c
@@ -98,7 +98,7 @@
* been removed from the stack. This will still be the initial value
* of the stack pointer when the task is started.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - frame_size: The size of the stack frame to allocate.
*
diff --git a/arch/avr/src/avr32/up_switchcontext.S b/arch/avr/src/avr32/up_switchcontext.S
index 8820427e69ba999e7464345e88633e981d5271a2..1542a645784a698d68f41386b7e19d7b7daa4684 100644
--- a/arch/avr/src/avr32/up_switchcontext.S
+++ b/arch/avr/src/avr32/up_switchcontext.S
@@ -68,7 +68,7 @@
*
* void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs);
*
- * Return:
+ * Returned Value:
* up_switchcontext forces a context switch to the task "canned" in restoreregs.
* It does not 'return' in the normal sense, rather, it will context switch back
* to the function point. When it does 'return,' it is because the blocked
diff --git a/arch/avr/src/avr32/up_unblocktask.c b/arch/avr/src/avr32/up_unblocktask.c
index d8181344fdd56291cc6839f0a3766c6af357e6e5..c77c5dbdbb2dce8869701b2cc407a36717a5fafd 100644
--- a/arch/avr/src/avr32/up_unblocktask.c
+++ b/arch/avr/src/avr32/up_unblocktask.c
@@ -61,7 +61,7 @@
* but has been prepped to execute. Move the TCB to the
* ready-to-run list, restore its context, and start execution.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to the tcb to be unblocked. This tcb is
* in one of the waiting tasks lists. It must be moved to
* the ready-to-run list and, if it is the highest priority
diff --git a/arch/avr/src/avr32/up_usestack.c b/arch/avr/src/avr32/up_usestack.c
index 533c82a16ca887849b6563fccf87bd328697d4d0..4e6de52de83b55abd776bf3a2835891f249b0266 100644
--- a/arch/avr/src/avr32/up_usestack.c
+++ b/arch/avr/src/avr32/up_usestack.c
@@ -78,7 +78,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The
* initial value of the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The allocated stack size.
*
diff --git a/arch/avr/src/common/up_releasestack.c b/arch/avr/src/common/up_releasestack.c
index 9cda128cabf0d7ebe85e959e80e7d89af68046c7..f1abcd15d90c93469a20eb4846a4138c5946569a 100644
--- a/arch/avr/src/common/up_releasestack.c
+++ b/arch/avr/src/common/up_releasestack.c
@@ -66,7 +66,7 @@
* A task has been stopped. Free all stack related resources retained in
* the defunct TCB.
*
- * Input Parmeters
+ * Input Parameters:
* - dtcb: The TCB containing information about the stack to be released
* - ttype: The thread type. This may be one of following (defined in
* include/nuttx/sched.h):
diff --git a/arch/hc/src/common/up_blocktask.c b/arch/hc/src/common/up_blocktask.c
index f6308cb729056e30f3eae9666ef392e2e4f968fa..9c69ac43db0f410fc7f42e6712861e1f99e54bb5 100644
--- a/arch/hc/src/common/up_blocktask.c
+++ b/arch/hc/src/common/up_blocktask.c
@@ -62,7 +62,7 @@
* the ready to run list must be stopped. Save its context
* and move it to the inactive list specified by task_state.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to a task in the ready-to-run list (normally
* the task at the head of the list). It most be
* stopped, its context saved and moved into one of the
diff --git a/arch/hc/src/common/up_createstack.c b/arch/hc/src/common/up_createstack.c
index f09b98a87a20ad4e710e60609c96a882c2b89e23..5f954588f3cad51f7dd829375706310ad63be86e 100644
--- a/arch/hc/src/common/up_createstack.c
+++ b/arch/hc/src/common/up_createstack.c
@@ -78,7 +78,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
* the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The requested stack size. At least this much
* must be allocated.
diff --git a/arch/hc/src/common/up_releasestack.c b/arch/hc/src/common/up_releasestack.c
index 03d50098e12dd80ebc952bbb4d952600b22314a2..5280674c99a524f31e877510a86bba6dbb2a88a3 100644
--- a/arch/hc/src/common/up_releasestack.c
+++ b/arch/hc/src/common/up_releasestack.c
@@ -66,7 +66,7 @@
* A task has been stopped. Free all stack related resources retained in
* the defunct TCB.
*
- * Input Parmeters
+ * Input Parameters:
* - dtcb: The TCB containing information about the stack to be released
* - ttype: The thread type. This may be one of following (defined in
* include/nuttx/sched.h):
diff --git a/arch/hc/src/common/up_reprioritizertr.c b/arch/hc/src/common/up_reprioritizertr.c
index 0b0d400d9a536692f9d7b23e657b9e221cc7d2bc..757f2ad05cdfde526768ee63afa89c8ac7c4be7a 100644
--- a/arch/hc/src/common/up_reprioritizertr.c
+++ b/arch/hc/src/common/up_reprioritizertr.c
@@ -68,7 +68,7 @@
* the priority of the current, running task and it now has the
* priority.
*
- * Inputs:
+ * Input Parameters:
* tcb: The TCB of the task that has been reprioritized
* priority: The new task priority
*
diff --git a/arch/hc/src/common/up_stackframe.c b/arch/hc/src/common/up_stackframe.c
index d712bb7d3b473ef1ade1db3ffa5e602906c0dc09..57d899f08e3ec786529eb1208b0c3cf1c09672a3 100644
--- a/arch/hc/src/common/up_stackframe.c
+++ b/arch/hc/src/common/up_stackframe.c
@@ -98,7 +98,7 @@
* been removed from the stack. This will still be the initial value
* of the stack pointer when the task is started.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - frame_size: The size of the stack frame to allocate.
*
diff --git a/arch/hc/src/common/up_unblocktask.c b/arch/hc/src/common/up_unblocktask.c
index c2ed818ac3092f90c73d7e605b5d6cafb5abea86..6ab177ecf1969700211a6bccbc2b8f05f16063cb 100644
--- a/arch/hc/src/common/up_unblocktask.c
+++ b/arch/hc/src/common/up_unblocktask.c
@@ -61,7 +61,7 @@
* but has been prepped to execute. Move the TCB to the
* ready-to-run list, restore its context, and start execution.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to the tcb to be unblocked. This tcb is
* in one of the waiting tasks lists. It must be moved to
* the ready-to-run list and, if it is the highest priority
diff --git a/arch/hc/src/common/up_usestack.c b/arch/hc/src/common/up_usestack.c
index 6160e92b5eb1d2ce6cb23d393347c9c22582a7c2..4ecf5351f7ba07b5875fa9dec384d72cff247c23 100644
--- a/arch/hc/src/common/up_usestack.c
+++ b/arch/hc/src/common/up_usestack.c
@@ -77,7 +77,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The
* initial value of the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The allocated stack size.
*
diff --git a/arch/hc/src/m9s12/m9s12.h b/arch/hc/src/m9s12/m9s12.h
index 53da6a772679331310bea74b06696e18e26e5931..48a09dde8863a1775a0879913995b8fa7dd52163 100644
--- a/arch/hc/src/m9s12/m9s12.h
+++ b/arch/hc/src/m9s12/m9s12.h
@@ -329,7 +329,7 @@ int hcs12_ethinitialize(int intf);
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/hc/src/m9s12/m9s12_ethernet.c b/arch/hc/src/m9s12/m9s12_ethernet.c
index 3b3fcf0d74180e4d230f4e02e11cfba7b0b89740..a56a267c9104e8351185a719ab1cbf9d622c3992 100644
--- a/arch/hc/src/m9s12/m9s12_ethernet.c
+++ b/arch/hc/src/m9s12/m9s12_ethernet.c
@@ -772,7 +772,7 @@ int emac_initialize(int intf)
#endif
priv->d_dev.d_private = (void*)g_emac; /* Used to recover private state from dev */
- /* Create a watchdog for timing polling for and timing of transmisstions */
+ /* Create a watchdog for timing polling for and timing of transmissions */
priv->d_txpoll = wd_create(); /* Create periodic poll timer */
priv->d_txtimeout = wd_create(); /* Create TX timeout timer */
diff --git a/arch/mips/src/common/up_createstack.c b/arch/mips/src/common/up_createstack.c
index 69d5ff04869639cda3aa6e90a9ee77f871a2ef7a..715bf8151e3b01c28cd69e78e1dde5a2bde7daf6 100644
--- a/arch/mips/src/common/up_createstack.c
+++ b/arch/mips/src/common/up_createstack.c
@@ -99,7 +99,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
* the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The requested stack size. At least this much
* must be allocated.
diff --git a/arch/mips/src/common/up_idle.c b/arch/mips/src/common/up_idle.c
index bee134392f85ca6953786c5766daddd268bf86c3..601a0cd5e3a2dd4d1b30d93b2014550e029c8b9d 100644
--- a/arch/mips/src/common/up_idle.c
+++ b/arch/mips/src/common/up_idle.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/mips/src/common/up_idle.c
*
- * Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011-2012, 2016, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -69,27 +69,23 @@ void up_idle(void)
sched_process_timer();
#else
+ irqstate_t flags;
/* This would be an appropriate place to put some MCU-specific logic to
* sleep in a reduced power mode until an interrupt occurs to save power
*/
- /* This is a kludge that I still don't understand. The call to kmm_trysemaphore()
- * in the os_start.c IDLE loop seems necessary for the good health of the IDLE
- * loop. When the work queue is enabled, this logic is removed from the IDLE
- * loop and it appears that we are somehow left idling with interrupts non-
- * functional. The following should be no-op, it just disables then re-enables
- * interrupts. But it fixes the problem and will stay here until I understand
- * the problem/fix better.
+ /* This is a kludge that I still don't understand. It appears that we are
+ * somehow left idling with interrupts non-functional. The following should
+ * be no-op, it just disables then re-enables interrupts. But it fixes the
+ * problem and will stay here until I understand the problem/fix better.
*
- * And no, the contents of the CP0 status register are not incorrect. But for
- * some reason the status register needs to be re-written again on this thread
- * for it to take effect. This might be a PIC32-only issue?
+ * And no, the contents of the CP0 status register are not incorrect. But
+ * for some reason the status register needs to be re-written again on this
+ * thread for it to take effect. This might be a PIC32-only issue?
*/
-#ifdef CONFIG_SCHED_WORKQUEUE
- irqstate_t flags = enter_critical_section();
- leave_critical_section(flags);
-#endif
+ flags = up_irq_save();
+ up_irq_restore(flags);
#endif
}
diff --git a/arch/mips/src/common/up_releasestack.c b/arch/mips/src/common/up_releasestack.c
index a322f4c24c8dddfa34b8aed60bbb43794546011e..d08bc2e6d91d7bb8e49afc3d8b035e6287d3fcf8 100644
--- a/arch/mips/src/common/up_releasestack.c
+++ b/arch/mips/src/common/up_releasestack.c
@@ -66,7 +66,7 @@
* A task has been stopped. Free all stack related resources retained in
* the defunct TCB.
*
- * Input Parmeters
+ * Input Parameters:
* - dtcb: The TCB containing information about the stack to be released
* - ttype: The thread type. This may be one of following (defined in
* include/nuttx/sched.h):
diff --git a/arch/mips/src/common/up_stackframe.c b/arch/mips/src/common/up_stackframe.c
index 6c631f3e1fc383b8b45b93baa1941d36a92e5fe1..45c8c05908802318c2c7c4128d3d37540df00201 100644
--- a/arch/mips/src/common/up_stackframe.c
+++ b/arch/mips/src/common/up_stackframe.c
@@ -100,7 +100,7 @@
* been removed from the stack. This will still be the initial value
* of the stack pointer when the task is started.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - frame_size: The size of the stack frame to allocate.
*
diff --git a/arch/mips/src/common/up_usestack.c b/arch/mips/src/common/up_usestack.c
index b4e3098fc47af5dcd9cba7649d1746352dc0b87a..041057a40e36ca3ba447deefee8c61a45057b0c1 100644
--- a/arch/mips/src/common/up_usestack.c
+++ b/arch/mips/src/common/up_usestack.c
@@ -98,7 +98,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The
* initial value of the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The allocated stack size.
*
diff --git a/arch/mips/src/mips32/up_blocktask.c b/arch/mips/src/mips32/up_blocktask.c
index 1ad66ce9db6ef2b3eb266560e84c4b37d6c44604..6ee466611de4a21b132375f67a8872593273e598 100644
--- a/arch/mips/src/mips32/up_blocktask.c
+++ b/arch/mips/src/mips32/up_blocktask.c
@@ -63,7 +63,7 @@
* the ready to run list must be stopped. Save its context
* and move it to the inactive list specified by task_state.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to a task in the ready-to-run list (normally
* the task at the head of the list). It most be
* stopped, its context saved and moved into one of the
diff --git a/arch/mips/src/mips32/up_reprioritizertr.c b/arch/mips/src/mips32/up_reprioritizertr.c
index 22a204d58bafd42d472bfbe288d13475e5836f01..cae6ed3af5ea985d9fec647d0d40dee06d6c1a8b 100644
--- a/arch/mips/src/mips32/up_reprioritizertr.c
+++ b/arch/mips/src/mips32/up_reprioritizertr.c
@@ -70,7 +70,7 @@
* the priority of the current, running task and it now has the
* priority.
*
- * Inputs:
+ * Input Parameters:
* tcb: The TCB of the task that has been reprioritized
* priority: The new task priority
*
diff --git a/arch/mips/src/mips32/up_unblocktask.c b/arch/mips/src/mips32/up_unblocktask.c
index 9e72ef17a6a811d2019248bce4fe03dae586cb2b..8400b1f7cf3412cfce79ae247b2cc0b12a5b43da 100644
--- a/arch/mips/src/mips32/up_unblocktask.c
+++ b/arch/mips/src/mips32/up_unblocktask.c
@@ -63,7 +63,7 @@
* but has been prepped to execute. Move the TCB to the
* ready-to-run list, restore its context, and start execution.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to the tcb to be unblocked. This tcb is
* in one of the waiting tasks lists. It must be moved to
* the ready-to-run list and, if it is the highest priority
diff --git a/arch/mips/src/mips32/up_vfork.c b/arch/mips/src/mips32/up_vfork.c
index 06b79f7bb13743527e02a91b7ccaa3378aa338e6..d62c2dd62323c1427cc3180a0381f02dac6e9a5d 100644
--- a/arch/mips/src/mips32/up_vfork.c
+++ b/arch/mips/src/mips32/up_vfork.c
@@ -100,10 +100,10 @@
*
* task_vforkabort() may be called if an error occurs between steps 3 and 6.
*
- * Input Paremeters:
+ * Input Parameters:
* context - Caller context information saved by vfork()
*
- * Return:
+ * Returned Value:
* Upon successful completion, vfork() returns 0 to the child process and
* returns the process ID of the child process to the parent process.
* Otherwise, -1 is returned to the parent, no child process is created,
diff --git a/arch/mips/src/mips32/vfork.S b/arch/mips/src/mips32/vfork.S
index 7012b45a41d53c4dc297ddbd0385c46232571343..bfcd9e51f490212202bcb3eec4c89541ac79a01a 100644
--- a/arch/mips/src/mips32/vfork.S
+++ b/arch/mips/src/mips32/vfork.S
@@ -86,10 +86,10 @@
* 5) up_vfork() then calls task_vforkstart()
* 6) task_vforkstart() then executes the child thread.
*
- * Input Paremeters:
+ * Input Parameters:
* None
*
- * Return:
+ * Returned Value:
* Upon successful completion, vfork() returns 0 to the child process and returns
* the process ID of the child process to the parent process. Otherwise, -1 is
* returned to the parent, no child process is created, and errno is set to
diff --git a/arch/mips/src/pic32mx/pic32mx-ethernet.c b/arch/mips/src/pic32mx/pic32mx-ethernet.c
index f436b298b6ac16d37c36db4409cdcaa86704911f..d772a8ba14b36aac096975852d94bbe2646e4ae5 100644
--- a/arch/mips/src/pic32mx/pic32mx-ethernet.c
+++ b/arch/mips/src/pic32mx/pic32mx-ethernet.c
@@ -3348,7 +3348,7 @@ static inline int pic32mx_ethinitialize(int intf)
priv->pd_irqsrc = ??; /* Ethernet controller IRQ source number */
#endif
- /* Create a watchdog for timing polling for and timing of transmisstions */
+ /* Create a watchdog for timing polling for and timing of transmissions */
priv->pd_txpoll = wd_create(); /* Create periodic poll timer */
priv->pd_txtimeout = wd_create(); /* Create TX timeout timer */
diff --git a/arch/mips/src/pic32mx/pic32mx-spi.c b/arch/mips/src/pic32mx/pic32mx-spi.c
index e09688e42c5ee4745729cee8bf9e41dc73fc10cd..ed3e8bae41b6b517ffa099c029ea5cce38cdcbd0 100644
--- a/arch/mips/src/pic32mx/pic32mx-spi.c
+++ b/arch/mips/src/pic32mx/pic32mx-spi.c
@@ -842,7 +842,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/mips/src/pic32mx/pic32mx-usbdev.c b/arch/mips/src/pic32mx/pic32mx-usbdev.c
index b184ff41ecd4221ebc17f5b2a51b73431cb4a2ce..82b3185181496d7dd85ebe08b4fd54b32be5ab24 100644
--- a/arch/mips/src/pic32mx/pic32mx-usbdev.c
+++ b/arch/mips/src/pic32mx/pic32mx-usbdev.c
@@ -1031,7 +1031,8 @@ static void pic32mx_delayedrestart(struct pic32mx_usbdev_s *priv, uint8_t epno)
/* And start (or re-start) the watchdog timer */
- wd_start(priv->wdog, RESTART_DELAY, pic32mx_rqrestart, 1, (uint32_t)priv);
+ (void)wd_start(priv->wdog, RESTART_DELAY, pic32mx_rqrestart, 1,
+ (uint32_t)priv);
}
/****************************************************************************
diff --git a/arch/mips/src/pic32mx/pic32mx.h b/arch/mips/src/pic32mx/pic32mx.h
index 480ff80fb8099fa0d6da9a8dd52f68cd619bcb9f..e76f02c8719c0a16f91deace5666dbad15d26723 100644
--- a/arch/mips/src/pic32mx/pic32mx.h
+++ b/arch/mips/src/pic32mx/pic32mx.h
@@ -391,7 +391,7 @@ void pic32mx_dumpgpio(uint32_t pinset, const char *msg);
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/mips/src/pic32mz/chip/pic32mz-spi.h b/arch/mips/src/pic32mz/chip/pic32mz-spi.h
index d4f5fe42a501d4fb96e099a7f2223e082cb92f39..c2359c0ae44b59487e8a078bb0a839ecf95e1ce5 100644
--- a/arch/mips/src/pic32mz/chip/pic32mz-spi.h
+++ b/arch/mips/src/pic32mz/chip/pic32mz-spi.h
@@ -110,7 +110,7 @@
#define PIC32MZ_SPI1_CON2SET (PIC32MZ_SPI1_K1BASE+PIC32MZ_SPI_CON2SET_OFFSET)
#define PIC32MZ_SPI1_CON2INV (PIC32MZ_SPI1_K1BASE+PIC32MZ_SPI_CON2INV_OFFSET)
-#if PIC32MZ_NSPI > 1
+#if CHIP_NSPI > 1
# define PIC32MZ_SPI2_CON (PIC32MZ_SPI2_K1BASE+PIC32MZ_SPI_CON_OFFSET)
# define PIC32MZ_SPI2_CONCLR (PIC32MZ_SPI2_K1BASE+PIC32MZ_SPI_CONCLR_OFFSET)
# define PIC32MZ_SPI2_CONSET (PIC32MZ_SPI2_K1BASE+PIC32MZ_SPI_CONSET_OFFSET)
@@ -128,7 +128,7 @@
# define PIC32MZ_SPI2_CON2INV (PIC32MZ_SPI2_K1BASE+PIC32MZ_SPI_CON2INV_OFFSET)
#endif
-#if PIC32MZ_NSPI > 2
+#if CHIP_NSPI > 2
# define PIC32MZ_SPI3_CON (PIC32MZ_SPI3_K1BASE+PIC32MZ_SPI_CON_OFFSET)
# define PIC32MZ_SPI3_CONCLR (PIC32MZ_SPI3_K1BASE+PIC32MZ_SPI_CONCLR_OFFSET)
# define PIC32MZ_SPI3_CONSET (PIC32MZ_SPI3_K1BASE+PIC32MZ_SPI_CONSET_OFFSET)
@@ -145,7 +145,7 @@
# define PIC32MZ_SPI3_CON2INV (PIC32MZ_SPI3_K1BASE+PIC32MZ_SPI_CON2INV_OFFSET)
#endif
-#if PIC32MZ_NSPI > 3
+#if CHIP_NSPI > 3
# define PIC32MZ_SPI4_CON (PIC32MZ_SPI4_K1BASE+PIC32MZ_SPI_CON_OFFSET)
# define PIC32MZ_SPI4_CONCLR (PIC32MZ_SPI4_K1BASE+PIC32MZ_SPI_CONCLR_OFFSET)
# define PIC32MZ_SPI4_CONSET (PIC32MZ_SPI4_K1BASE+PIC32MZ_SPI_CONSET_OFFSET)
@@ -162,7 +162,7 @@
# define PIC32MZ_SPI4_CON2INV (PIC32MZ_SPI4_K1BASE+PIC32MZ_SPI_CON2INV_OFFSET)
#endif
-#if PIC32MZ_NSPI > 4
+#if CHIP_NSPI > 4
# define PIC32MZ_SPI5_CON (PIC32MZ_SPI5_K1BASE+PIC32MZ_SPI_CON_OFFSET)
# define PIC32MZ_SPI5_CONCLR (PIC32MZ_SPI5_K1BASE+PIC32MZ_SPI_CONCLR_OFFSET)
# define PIC32MZ_SPI5_CONSET (PIC32MZ_SPI5_K1BASE+PIC32MZ_SPI_CONSET_OFFSET)
@@ -179,7 +179,7 @@
# define PIC32MZ_SPI5_CON2INV (PIC32MZ_SPI5_K1BASE+PIC32MZ_SPI_CON2INV_OFFSET)
#endif
-#if PIC32MZ_NSPI > 5
+#if CHIP_NSPI > 5
# define PIC32MZ_SPI6_CON (PIC32MZ_SPI6_K1BASE+PIC32MZ_SPI_CON_OFFSET)
# define PIC32MZ_SPI6_CONCLR (PIC32MZ_SPI6_K1BASE+PIC32MZ_SPI_CONCLR_OFFSET)
# define PIC32MZ_SPI6_CONSET (PIC32MZ_SPI6_K1BASE+PIC32MZ_SPI_CONSET_OFFSET)
@@ -275,6 +275,7 @@
#define SPI_STAT_SPIRBF (1 << 0) /* Bit 0: SPI receive buffer full status */
#define SPI_STAT_SPITBF (1 << 1) /* Bit 1: SPI transmit buffer full status */
+ /* Bit 2: Reserved */
#define SPI_STAT_SPITBE (1 << 3) /* Bit 3: SPI transmit buffer empty status */
/* Bit 4: Reserved */
#define SPI_STAT_SPIRBE (1 << 5) /* Bit 5: RX FIFO Empty */
diff --git a/arch/mips/src/pic32mz/pic32mz-ethernet.c b/arch/mips/src/pic32mz/pic32mz-ethernet.c
index 5e1b2f5e0467af3a0f188ea8aa564164ad4f3d65..046b2861e93f4d3d9baebee7c9db62467f0dffd2 100644
--- a/arch/mips/src/pic32mz/pic32mz-ethernet.c
+++ b/arch/mips/src/pic32mz/pic32mz-ethernet.c
@@ -3384,7 +3384,7 @@ static inline int pic32mz_ethinitialize(int intf)
priv->pd_irqsrc = ??; /* Ethernet controller IRQ source number */
#endif
- /* Create a watchdog for timing polling for and timing of transmisstions */
+ /* Create a watchdog for timing polling for and timing of transmissions */
priv->pd_txpoll = wd_create(); /* Create periodic poll timer */
priv->pd_txtimeout = wd_create(); /* Create TX timeout timer */
diff --git a/arch/mips/src/pic32mz/pic32mz-gpio.c b/arch/mips/src/pic32mz/pic32mz-gpio.c
index 3d247edc5b33b5e183d7ece4c0bf3efde38b63af..0ec2c44fecdd47b53a594ecdaedf0f9783c145b0 100644
--- a/arch/mips/src/pic32mz/pic32mz-gpio.c
+++ b/arch/mips/src/pic32mz/pic32mz-gpio.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/mips/src/pic32mz/pic32mz-gpio.c
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -332,10 +332,10 @@ void pic32mz_dumpgpio(uint32_t pinset, const char *msg)
getreg32(base + PIC32MZ_IOPORT_PORT_OFFSET),
getreg32(base + PIC32MZ_IOPORT_LAT_OFFSET),
getreg32(base + PIC32MZ_IOPORT_ODC_OFFSET));
- gpioinfo(" CNCON: %08x CNEN: %08x CNPUE: %08x\n",
- getreg32(PIC32MZ_IOPORT_CNCON),
- getreg32(PIC32MZ_IOPORT_CNEN),
- getreg32(PIC32MZ_IOPORT_CNPUE));
+ gpioinfo(" CNCON: %08x CNEN: %08x CNPU: %08x\n",
+ getreg32(base + PIC32MZ_IOPORT_CNCON_OFFSET),
+ getreg32(base + PIC32MZ_IOPORT_CNEN_OFFSET),
+ getreg32(base + PIC32MZ_IOPORT_CNPU_OFFSET));
sched_unlock();
}
}
diff --git a/arch/mips/src/pic32mz/pic32mz-serial.c b/arch/mips/src/pic32mz/pic32mz-serial.c
index cfce690614e62494ed24fbfd85847564d0d0ea29..b4d6e8e791d0aae25b776c2131d5fa40f5a4eb9b 100644
--- a/arch/mips/src/pic32mz/pic32mz-serial.c
+++ b/arch/mips/src/pic32mz/pic32mz-serial.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/mips/src/pic32mz/pic32mz-serial.c
*
- * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015, 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -96,10 +96,10 @@
# define CONSOLE_DEV g_uart4port /* UART4 is console */
# define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */
# define UART4_ASSIGNED 1
-#elif defined(CONFIG_UART4_SERIAL_CONSOLE)
-# define CONSOLE_DEV g_uart5port /* UART4 is console */
-# define TTYS0_DEV g_uart5port /* UART4 is ttyS0 */
-# define UART4_ASSIGNED 1
+#elif defined(CONFIG_UART5_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart5port /* UART5 is console */
+# define TTYS0_DEV g_uart5port /* UART5 is ttyS0 */
+# define UART5_ASSIGNED 1
#elif defined(CONFIG_UART6_SERIAL_CONSOLE)
# define CONSOLE_DEV g_uart6port /* UART6 is console */
# define TTYS5_DEV g_uart6port /* UART6 is ttyS0 */
@@ -118,9 +118,9 @@
# elif defined(CONFIG_PIC32MZ_UART4)
# define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */
# define UART4_ASSIGNED 1
-# elif defined(CONFIG_PIC32MZ_UART4)
-# define TTYS0_DEV g_uart5port /* UART4 is ttyS0 */
-# define UART4_ASSIGNED 1
+# elif defined(CONFIG_PIC32MZ_UART5)
+# define TTYS0_DEV g_uart5port /* UART5 is ttyS0 */
+# define UART5_ASSIGNED 1
# elif defined(CONFIG_PIC32MZ_UART6)
# define TTYS0_DEV g_uart6port /* UART6 is ttyS0 */
# define UART6_ASSIGNED 1
diff --git a/arch/mips/src/pic32mz/pic32mz-spi.c b/arch/mips/src/pic32mz/pic32mz-spi.c
index 287c538b7d03c3a74a682f8022fd681d623be3db..ea2f906cb918a2af03f74f0d6460b55cc168063a 100644
--- a/arch/mips/src/pic32mz/pic32mz-spi.c
+++ b/arch/mips/src/pic32mz/pic32mz-spi.c
@@ -1199,7 +1199,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/mips/src/pic32mz/pic32mz-spi.h b/arch/mips/src/pic32mz/pic32mz-spi.h
index ce4d772e0a64de925edbf20d9b183f10b076e655..e8a11d3f04c1cf7a715b13c7441bb3cfb491ed11 100644
--- a/arch/mips/src/pic32mz/pic32mz-spi.h
+++ b/arch/mips/src/pic32mz/pic32mz-spi.h
@@ -78,7 +78,7 @@ struct spi_dev_s; /* Forward reference */
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
@@ -170,6 +170,58 @@ int pic32mz_spi6cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#endif
+/****************************************************************************
+ * Name: pic32mz_spi1/2/...register
+ *
+ * Description:
+ * If the board supports a card detect callback to inform the SPI-based
+ * MMC/SD driver when an SD card is inserted or removed, then
+ * CONFIG_SPI_CALLBACK should be defined and the following function(s)
+ * must be implemented. These functions implements the registercallback
+ * method of the SPI interface (see include/nuttx/spi/spi.h for details)
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * callback - The function to call on the media change
+ * arg - A caller provided value to return with the callback
+ *
+ * Returned Value:
+ * 0 on success; negated errno on failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_CALLBACK
+#ifdef CONFIG_PIC32MZ_SPI1
+int pic32mz_spi1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
+ FAR void *arg);
+#endif
+
+#ifdef CONFIG_PIC32MZ_SPI2
+int pic32mz_spi2register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
+ FAR void *arg);
+#endif
+
+#ifdef CONFIG_PIC32MZ_SPI3
+int pic32mz_spi3register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
+ FAR void *arg);
+#endif
+
+#ifdef CONFIG_PIC32MZ_SPI4
+int pic32mz_spi4register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
+ FAR void *arg);
+#endif
+
+#ifdef CONFIG_PIC32MZ_SPI5
+int pic32mz_spi5register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
+ FAR void *arg);
+#endif
+
+#ifdef CONFIG_PIC32MZ_SPI6
+int pic32mz_spi6register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
+ FAR void *arg);
+#endif
+#endif /* CONFIG_SPI_CALLBACK */
+
#undef EXTERN
#if defined(__cplusplus)
}
diff --git a/arch/misoc/src/common/misoc_net.c b/arch/misoc/src/common/misoc_net.c
index a7df3654352d7b99c8af4dc27016a32d9379ba0a..595cbbbcff2c8804454d690db1afbb10c6f0a422 100644
--- a/arch/misoc/src/common/misoc_net.c
+++ b/arch/misoc/src/common/misoc_net.c
@@ -1172,7 +1172,7 @@ int misoc_net_initialize(int intf)
#endif
priv->misoc_net_dev.d_private = (FAR void *)g_misoc_net; /* Used to recover private state from dev */
- /* Create a watchdog for timing polling for and timing of transmisstions */
+ /* Create a watchdog for timing polling for and timing of transmissions */
priv->misoc_net_txpoll = wd_create(); /* Create periodic poll timer */
priv->misoc_net_txtimeout = wd_create(); /* Create TX timeout timer */
diff --git a/arch/misoc/src/lm32/lm32_blocktask.c b/arch/misoc/src/lm32/lm32_blocktask.c
index f313da11cca3f3ad37f01a814c2d89b198e85e0b..7bc951cfbf475b6407ebd14df046be68b71336b9 100644
--- a/arch/misoc/src/lm32/lm32_blocktask.c
+++ b/arch/misoc/src/lm32/lm32_blocktask.c
@@ -64,7 +64,7 @@
* the ready to run list must be stopped. Save its context
* and move it to the inactive list specified by task_state.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to a task in the ready-to-run list (normally
* the task at the head of the list). It most be
* stopped, its context saved and moved into one of the
diff --git a/arch/misoc/src/lm32/lm32_createstack.c b/arch/misoc/src/lm32/lm32_createstack.c
index 31c7f2422616526e3d2d03c1ddd678a1518a9f11..a9aa3143a1003f0534a4a42bfd5ec8e0e00f3175 100644
--- a/arch/misoc/src/lm32/lm32_createstack.c
+++ b/arch/misoc/src/lm32/lm32_createstack.c
@@ -99,7 +99,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
* the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The requested stack size. At least this much
* must be allocated.
diff --git a/arch/misoc/src/lm32/lm32_releasestack.c b/arch/misoc/src/lm32/lm32_releasestack.c
index fa88500bf9d04beff9cfea29695be2db3357d557..63f4ab8f993fe6abd2bc641d452d558ad77ced3c 100644
--- a/arch/misoc/src/lm32/lm32_releasestack.c
+++ b/arch/misoc/src/lm32/lm32_releasestack.c
@@ -59,7 +59,7 @@
* A task has been stopped. Free all stack related resources retained in
* the defunct TCB.
*
- * Input Parmeters
+ * Input Parameters:
* - dtcb: The TCB containing information about the stack to be released
* - ttype: The thread type. This may be one of following (defined in
* include/nuttx/sched.h):
diff --git a/arch/misoc/src/lm32/lm32_reprioritizertr.c b/arch/misoc/src/lm32/lm32_reprioritizertr.c
index e6b42611018b928e66eca1b246c1489d6710f721..735b69ced743639e8b0de5e8dd3545d7c6fd213e 100644
--- a/arch/misoc/src/lm32/lm32_reprioritizertr.c
+++ b/arch/misoc/src/lm32/lm32_reprioritizertr.c
@@ -70,7 +70,7 @@
* the priority of the current, running task and it now has the
* priority.
*
- * Inputs:
+ * Input Parameters:
* tcb: The TCB of the task that has been reprioritized
* priority: The new task priority
*
diff --git a/arch/misoc/src/lm32/lm32_stackframe.c b/arch/misoc/src/lm32/lm32_stackframe.c
index 981c655f81f1c5873b4c8ba431a52ba3970ea3cb..0791201b4e8dfa45be58ae2a7202b7af89c59be5 100644
--- a/arch/misoc/src/lm32/lm32_stackframe.c
+++ b/arch/misoc/src/lm32/lm32_stackframe.c
@@ -94,7 +94,7 @@
* been removed from the stack. This will still be the initial value
* of the stack pointer when the task is started.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - frame_size: The size of the stack frame to allocate.
*
diff --git a/arch/misoc/src/lm32/lm32_unblocktask.c b/arch/misoc/src/lm32/lm32_unblocktask.c
index 74b1d92472c890453bebf57fbba8725ce48732b3..8dedd5299325d89c10481ff497b13f33c097208b 100644
--- a/arch/misoc/src/lm32/lm32_unblocktask.c
+++ b/arch/misoc/src/lm32/lm32_unblocktask.c
@@ -64,7 +64,7 @@
* but has been prepped to execute. Move the TCB to the
* ready-to-run list, restore its context, and start execution.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to the tcb to be unblocked. This tcb is
* in one of the waiting tasks lists. It must be moved to
* the ready-to-run list and, if it is the highest priority
diff --git a/arch/renesas/src/common/up_blocktask.c b/arch/renesas/src/common/up_blocktask.c
index 9e8ba57db75b6d0b4c030cd42f7aa0db2267b9bb..9ceda2e1e2f1f793cfba5ad525803243e3a5536d 100644
--- a/arch/renesas/src/common/up_blocktask.c
+++ b/arch/renesas/src/common/up_blocktask.c
@@ -61,7 +61,7 @@
* the ready to run list must be stopped. Save its context
* and move it to the inactive list specified by task_state.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to a task in the ready-to-run list (normally
* the task at the head of the list). It most be
* stopped, its context saved and moved into one of the
diff --git a/arch/renesas/src/common/up_createstack.c b/arch/renesas/src/common/up_createstack.c
index 1bbf3cc8e0f20b89b60c820861ba8855c425bdb4..f4461a08b3dd923fdb7c5993cd1a0b45ab00208b 100644
--- a/arch/renesas/src/common/up_createstack.c
+++ b/arch/renesas/src/common/up_createstack.c
@@ -78,7 +78,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
* the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The requested stack size. At least this much
* must be allocated.
diff --git a/arch/renesas/src/common/up_releasestack.c b/arch/renesas/src/common/up_releasestack.c
index e2b5948b142fb84272ab588875403528e17dcefc..5b309bde16de376ab45399b212a6dde0ffcbd462 100644
--- a/arch/renesas/src/common/up_releasestack.c
+++ b/arch/renesas/src/common/up_releasestack.c
@@ -66,7 +66,7 @@
* A task has been stopped. Free all stack related resources retained in
* the defunct TCB.
*
- * Input Parmeters
+ * Input Parameters:
* - dtcb: The TCB containing information about the stack to be released
* - ttype: The thread type. This may be one of following (defined in
* include/nuttx/sched.h):
diff --git a/arch/renesas/src/common/up_reprioritizertr.c b/arch/renesas/src/common/up_reprioritizertr.c
index c476dbad376420d5ff9fc712764c9bdb3d754c0b..2733ecb8d971a4fa8426ab2665bdc20aca692913 100644
--- a/arch/renesas/src/common/up_reprioritizertr.c
+++ b/arch/renesas/src/common/up_reprioritizertr.c
@@ -68,7 +68,7 @@
* the priority of the current, running task and it now has the
* priority.
*
- * Inputs:
+ * Input Parameters:
* tcb: The TCB of the task that has been reprioritized
* priority: The new task priority
*
diff --git a/arch/renesas/src/common/up_stackframe.c b/arch/renesas/src/common/up_stackframe.c
index 811fcd4aad1b007466f7258b522b4dd4a4e8afeb..d3512ec9c95ecba0c5f3e7eba21bc0e68ac67f17 100644
--- a/arch/renesas/src/common/up_stackframe.c
+++ b/arch/renesas/src/common/up_stackframe.c
@@ -96,7 +96,7 @@
* been removed from the stack. This will still be the initial value
* of the stack pointer when the task is started.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - frame_size: The size of the stack frame to allocate.
*
diff --git a/arch/renesas/src/common/up_unblocktask.c b/arch/renesas/src/common/up_unblocktask.c
index de3008f98a00bb11ee11c698d95c9d61b94f1c28..30a9b4af9cb1621ce9a698f74e10bea9cd4fec15 100644
--- a/arch/renesas/src/common/up_unblocktask.c
+++ b/arch/renesas/src/common/up_unblocktask.c
@@ -61,7 +61,7 @@
* but has been prepped to execute. Move the TCB to the
* ready-to-run list, restore its context, and start execution.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to the tcb to be unblocked. This tcb is
* in one of the waiting tasks lists. It must be moved to
* the ready-to-run list and, if it is the highest priority
diff --git a/arch/renesas/src/common/up_usestack.c b/arch/renesas/src/common/up_usestack.c
index de4c4aca95f7cdcf5e21539a6badc85171bb01c6..9fce7d59653724620fd0c4a4b822fe8525700d73 100644
--- a/arch/renesas/src/common/up_usestack.c
+++ b/arch/renesas/src/common/up_usestack.c
@@ -78,7 +78,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The
* initial value of the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The allocated stack size.
*
diff --git a/arch/risc-v/src/common/up_createstack.c b/arch/risc-v/src/common/up_createstack.c
index 494d54e4abcb3fe16b5809f51dd6a902acd3132d..1861707685a4e98fe8b8c5840a7cad75b8814fc9 100644
--- a/arch/risc-v/src/common/up_createstack.c
+++ b/arch/risc-v/src/common/up_createstack.c
@@ -99,7 +99,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
* the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The requested stack size. At least this much
* must be allocated.
diff --git a/arch/risc-v/src/common/up_releasestack.c b/arch/risc-v/src/common/up_releasestack.c
index 15301c49d2704a17134c257572df806930f73511..dac7cea0d6ded0aece92e0171233d40464e04415 100644
--- a/arch/risc-v/src/common/up_releasestack.c
+++ b/arch/risc-v/src/common/up_releasestack.c
@@ -66,7 +66,7 @@
* A task has been stopped. Free all stack related resources retained in
* the defunct TCB.
*
- * Input Parmeters
+ * Input Parameters:
* - dtcb: The TCB containing information about the stack to be released
* - ttype: The thread type. This may be one of following (defined in
* include/nuttx/sched.h):
diff --git a/arch/risc-v/src/common/up_stackframe.c b/arch/risc-v/src/common/up_stackframe.c
index b3cb9801d4d2bdb09c73f01b627aa0168b291662..be7b797d2c2bd2a9d34f2687d37a181425a781d0 100644
--- a/arch/risc-v/src/common/up_stackframe.c
+++ b/arch/risc-v/src/common/up_stackframe.c
@@ -100,7 +100,7 @@
* been removed from the stack. This will still be the initial value
* of the stack pointer when the task is started.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - frame_size: The size of the stack frame to allocate.
*
diff --git a/arch/risc-v/src/common/up_usestack.c b/arch/risc-v/src/common/up_usestack.c
index 605bb79b045ee06b3a29dc9b50571d252cd8aaac..49333a5a12218b9d4e86b9dad7dabd4f4f111b8c 100644
--- a/arch/risc-v/src/common/up_usestack.c
+++ b/arch/risc-v/src/common/up_usestack.c
@@ -98,7 +98,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The
* initial value of the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The allocated stack size.
*
diff --git a/arch/risc-v/src/nr5m100/nr5_allocateheap.c b/arch/risc-v/src/nr5m100/nr5_allocateheap.c
index 3467cee05cbf4262f0fac6ebb4cef0820c747ee0..38fb84c162c4ec6dc5e1295534e02298da3cf96a 100644
--- a/arch/risc-v/src/nr5m100/nr5_allocateheap.c
+++ b/arch/risc-v/src/nr5m100/nr5_allocateheap.c
@@ -51,7 +51,7 @@
/************************************************************************************
* Name: up_addregion
*
- * Descripton:
+ * Description:
* RAM may be added in non-contiguous chunks. This routine adds all chunks
* that may be used for heap.
*
diff --git a/arch/risc-v/src/nr5m100/nr5_timer.h b/arch/risc-v/src/nr5m100/nr5_timer.h
index 2a6d15c3e3d874a00aa8b718dc0bfffd28050692..5994df9bee110b9d8c7771bfccf2dab97d9727fa 100644
--- a/arch/risc-v/src/nr5m100/nr5_timer.h
+++ b/arch/risc-v/src/nr5m100/nr5_timer.h
@@ -148,7 +148,7 @@ int nr5_timer_deinit(FAR struct nr5_timer_dev_s *dev);
* devpath - The full path to the timer device. This should be of the form /dev/timer0
* timer - the timer number.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
diff --git a/arch/risc-v/src/rv32im/up_blocktask.c b/arch/risc-v/src/rv32im/up_blocktask.c
index 530797da2b189fee6e7843c5925bc7c72e266d9a..0ac7327e120ef2c9485311758a65d0608bc0df55 100644
--- a/arch/risc-v/src/rv32im/up_blocktask.c
+++ b/arch/risc-v/src/rv32im/up_blocktask.c
@@ -63,7 +63,7 @@
* the ready to run list must be stopped. Save its context
* and move it to the inactive list specified by task_state.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to a task in the ready-to-run list (normally
* the task at the head of the list). It most be
* stopped, its context saved and moved into one of the
diff --git a/arch/risc-v/src/rv32im/up_reprioritizertr.c b/arch/risc-v/src/rv32im/up_reprioritizertr.c
index 26ed4ab2d10a3f62c6a4a16806004f28b5cb4ae0..e286d5026ec2e97fb35408fb554781930f47ebda 100644
--- a/arch/risc-v/src/rv32im/up_reprioritizertr.c
+++ b/arch/risc-v/src/rv32im/up_reprioritizertr.c
@@ -70,7 +70,7 @@
* the priority of the current, running task and it now has the
* priority.
*
- * Inputs:
+ * Input Parameters:
* tcb: The TCB of the task that has been reprioritized
* priority: The new task priority
*
diff --git a/arch/risc-v/src/rv32im/up_unblocktask.c b/arch/risc-v/src/rv32im/up_unblocktask.c
index 1b7350e05b1ced91addcd74d8175b14f6ffddf25..3bb71380dde102ea80e4f76b7f3c6eb6406ede1d 100644
--- a/arch/risc-v/src/rv32im/up_unblocktask.c
+++ b/arch/risc-v/src/rv32im/up_unblocktask.c
@@ -63,7 +63,7 @@
* but has been prepped to execute. Move the TCB to the
* ready-to-run list, restore its context, and start execution.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to the tcb to be unblocked. This tcb is
* in one of the waiting tasks lists. It must be moved to
* the ready-to-run list and, if it is the highest priority
diff --git a/arch/risc-v/src/rv32im/up_vfork.c b/arch/risc-v/src/rv32im/up_vfork.c
index f2f5332beceb8417ff9261836ccacd6563e9dc7a..d38d29c158fe7faeb2bd38ccfa9040449d5954fa 100644
--- a/arch/risc-v/src/rv32im/up_vfork.c
+++ b/arch/risc-v/src/rv32im/up_vfork.c
@@ -100,10 +100,10 @@
*
* task_vforkabort() may be called if an error occurs between steps 3 and 6.
*
- * Input Paremeters:
+ * Input Parameters:
* context - Caller context information saved by vfork()
*
- * Return:
+ * Returned Value:
* Upon successful completion, vfork() returns 0 to the child process and
* returns the process ID of the child process to the parent process.
* Otherwise, -1 is returned to the parent, no child process is created,
diff --git a/arch/sim/include/spinlock.h b/arch/sim/include/spinlock.h
index 85333276b12cbe4edf8977bf290674292b21c816..9bfc5f40a87f1b35997278305abec8a2bfe439de 100644
--- a/arch/sim/include/spinlock.h
+++ b/arch/sim/include/spinlock.h
@@ -69,7 +69,7 @@ typedef bool spinlock_t;
* Description:
* Perform an atomic test and set operation on the provided spinlock.
*
- * This function must be provided via the architecture-specific logoic.
+ * This function must be provided via the architecture-specific logic.
*
* Input Parameters:
* lock - The address of spinlock object.
diff --git a/arch/sim/src/up_blocktask.c b/arch/sim/src/up_blocktask.c
index 27223b19c3bc902fbb2758f8a7bc16aa114b6785..86a46453ecf8f7580fdd36101997b0d3fdeb8bf4 100644
--- a/arch/sim/src/up_blocktask.c
+++ b/arch/sim/src/up_blocktask.c
@@ -61,7 +61,7 @@
* the ready to run list must be stopped. Save its context
* and move it to the inactive list specified by task_state.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to a task in the ready-to-run list (normally
* the task at the head of the list). It most be
* stopped, its context saved and moved into one of the
diff --git a/arch/sim/src/up_cpuidlestack.c b/arch/sim/src/up_cpuidlestack.c
index c11d14e4a9905ff23c15487871d726b6646cbe2d..4a237c1b6bb6290a9f5c0bd476fec0965b3cc2ea 100644
--- a/arch/sim/src/up_cpuidlestack.c
+++ b/arch/sim/src/up_cpuidlestack.c
@@ -85,7 +85,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
* the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - cpu: CPU index that indicates which CPU the IDLE task is
* being created for.
* - tcb: The TCB of new CPU IDLE task
diff --git a/arch/sim/src/up_createstack.c b/arch/sim/src/up_createstack.c
index 96a4097a234cfc6444e23b4cd6af7d988ac14d51..2d511ba6c552a968620ca68a9cce8edfeac8bee4 100644
--- a/arch/sim/src/up_createstack.c
+++ b/arch/sim/src/up_createstack.c
@@ -84,7 +84,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
* the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The requested stack size. At least this much
* must be allocated.
diff --git a/arch/sim/src/up_framebuffer.c b/arch/sim/src/up_framebuffer.c
index 195eadd6a461b3740f4291c0fdcf705095e1bcdf..8178c3994d954937804ee5f197545b58daf5c95d 100644
--- a/arch/sim/src/up_framebuffer.c
+++ b/arch/sim/src/up_framebuffer.c
@@ -308,7 +308,7 @@ static int up_getcursor(FAR struct fb_vtable_s *vtable,
#endif
/****************************************************************************
- * Name:
+ * Name: up_setcursor
****************************************************************************/
#ifdef CONFIG_FB_HWCURSOR
@@ -356,7 +356,7 @@ static int up_setcursor(FAR struct fb_vtable_s *vtable,
* Description:
* Initialize the framebuffer video hardware associated with the display.
*
- * Input parameters:
+ * Input Parameters:
* display - In the case of hardware with multiple displays, this
* specifies the display. Normally this is zero.
*
@@ -384,7 +384,7 @@ int up_fbinitialize(int display)
* Return a a reference to the framebuffer object for the specified video
* plane of the specified plane. Many OSDs support multiple planes of video.
*
- * Input parameters:
+ * Input Parameters:
* display - In the case of hardware with multiple displays, this
* specifies the display. Normally this is zero.
* vplane - Identifies the plane being queried.
diff --git a/arch/sim/src/up_qspiflash.c b/arch/sim/src/up_qspiflash.c
index c94986b3d388537d3e71afc2eaa689f5461452cb..f01002d7fe973bca19bf618d9c49cbb3b3857ef1 100644
--- a/arch/sim/src/up_qspiflash.c
+++ b/arch/sim/src/up_qspiflash.c
@@ -577,7 +577,7 @@ static int qspiflash_command(FAR struct qspi_dev_s *dev, FAR struct qspi_cmdinfo
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/sim/src/up_releasestack.c b/arch/sim/src/up_releasestack.c
index e62cf2adf81123fdbc901945b48aec03bffcddf0..87a30261264587d5736e4a574501132d4694ac22 100644
--- a/arch/sim/src/up_releasestack.c
+++ b/arch/sim/src/up_releasestack.c
@@ -57,7 +57,7 @@
* A task has been stopped. Free all stack related resources retained in
* the defunct TCB.
*
- * Input Parmeters
+ * Input Parameters:
* - dtcb: The TCB containing information about the stack to be released
* - ttype: The thread type. This may be one of following (defined in
* include/nuttx/sched.h):
diff --git a/arch/sim/src/up_reprioritizertr.c b/arch/sim/src/up_reprioritizertr.c
index 048c311559607353625a2e62729997eb22b7ed5a..36e34230477ef54cca7587e939a7538e66e1a717 100644
--- a/arch/sim/src/up_reprioritizertr.c
+++ b/arch/sim/src/up_reprioritizertr.c
@@ -68,7 +68,7 @@
* the priority of the current, running task and it now has the
* priority.
*
- * Inputs:
+ * Input Parameters:
* tcb: The TCB of the task that has been reprioritized
* priority: The new task priority
*
diff --git a/arch/sim/src/up_spiflash.c b/arch/sim/src/up_spiflash.c
index 677bdafd969271bb0adde863b65eb4d952d9f7e7..a75cb82948b0b83a10a9f2943927bca415d56656 100644
--- a/arch/sim/src/up_spiflash.c
+++ b/arch/sim/src/up_spiflash.c
@@ -897,7 +897,7 @@ static uint16_t spiflash_readword(FAR struct sim_spiflashdev_s *priv)
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/sim/src/up_stackframe.c b/arch/sim/src/up_stackframe.c
index 3e5b8a089deb7798ccf432dff3a125f568b4a325..624520dc208f6f517f80d133cc310eeef0e4bd97 100644
--- a/arch/sim/src/up_stackframe.c
+++ b/arch/sim/src/up_stackframe.c
@@ -90,7 +90,7 @@
* been removed from the stack. This will still be the initial value
* of the stack pointer when the task is started.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - frame_size: The size of the stack frame to allocate.
*
diff --git a/arch/sim/src/up_testset.c b/arch/sim/src/up_testset.c
index d1b754bca066c9085d07fbd8daa02d6dc3d383ca..1f825e64154e355868b8becf37a3c07d108b7b16 100644
--- a/arch/sim/src/up_testset.c
+++ b/arch/sim/src/up_testset.c
@@ -73,7 +73,7 @@ static pthread_mutex_t g_tsmutex = PTHREAD_MUTEX_INITIALIZER;
* Description:
* Perform an atomic test and set operation on the provided spinlock.
*
- * This function must be provided via the architecture-specific logoic.
+ * This function must be provided via the architecture-specific logic.
*
* Input Parameters:
* lock - The address of spinlock object.
diff --git a/arch/sim/src/up_touchscreen.c b/arch/sim/src/up_touchscreen.c
index 49e0954b5c3e9c1424fe8a10b07105468b1413bd..7e5d4a255d85efc74ac5bec8d32e37531f58839a 100644
--- a/arch/sim/src/up_touchscreen.c
+++ b/arch/sim/src/up_touchscreen.c
@@ -486,7 +486,7 @@ errout:
}
/****************************************************************************
- * Name:up_ioctl
+ * Name: up_ioctl
****************************************************************************/
static int up_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
diff --git a/arch/sim/src/up_unblocktask.c b/arch/sim/src/up_unblocktask.c
index 5217efeb8fbe8e4db28d9292b9c712f5788377bd..03e8e847f9eba31afab9e4ea6c2fdfdacf29fa5c 100644
--- a/arch/sim/src/up_unblocktask.c
+++ b/arch/sim/src/up_unblocktask.c
@@ -60,7 +60,7 @@
* but has been prepped to execute. Move the TCB to the
* ready-to-run list, restore its context, and start execution.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to the tcb to be unblocked. This tcb is
* in one of the waiting tasks lists. It must be moved to
* the ready-to-run list and, if it is the highest priority
diff --git a/arch/sim/src/up_usestack.c b/arch/sim/src/up_usestack.c
index 3b428d8222cce23f9de39f2a7f7176abf39dd1bd..f31ed5aae3bf42778055f2078bc523051c473701 100644
--- a/arch/sim/src/up_usestack.c
+++ b/arch/sim/src/up_usestack.c
@@ -85,7 +85,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The
* initial value of the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The allocated stack size.
*
diff --git a/arch/x86/src/common/up_blocktask.c b/arch/x86/src/common/up_blocktask.c
index e5a4845e2444f80581581da527e5392ee4b2a633..34f7f9fa26e76e916e791416700a9f9cf99cfc60 100644
--- a/arch/x86/src/common/up_blocktask.c
+++ b/arch/x86/src/common/up_blocktask.c
@@ -62,7 +62,7 @@
* be stopped. Save its context and move it to the inactive list specified
* by task_state.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to a task in the ready-to-run list (normally the task at the
* head of the list). It most be stopped, its context saved and moved
* into one of the waiting task lists. It it was the task at the head
diff --git a/arch/x86/src/common/up_reprioritizertr.c b/arch/x86/src/common/up_reprioritizertr.c
index 110d26a6717924603532138d56d5843e410b851b..75428b84c98b9de1a4fd102def0a392ea941c09d 100644
--- a/arch/x86/src/common/up_reprioritizertr.c
+++ b/arch/x86/src/common/up_reprioritizertr.c
@@ -68,7 +68,7 @@
* the priority of the current, running task and it now has the
* priority.
*
- * Inputs:
+ * Input Parameters:
* tcb: The TCB of the task that has been reprioritized
* priority: The new task priority
*
diff --git a/arch/x86/src/common/up_unblocktask.c b/arch/x86/src/common/up_unblocktask.c
index 706d36808c841d76ae1854a5aabd9a13b5782151..8b3b4b3f2496edab122a4af443f59e8938420bb0 100644
--- a/arch/x86/src/common/up_unblocktask.c
+++ b/arch/x86/src/common/up_unblocktask.c
@@ -61,7 +61,7 @@
* execute. Move the TCB to the ready-to-run list, restore its context,
* and start execution.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to the tcb to be unblocked. This tcb is in one of the
* waiting tasks lists. It must be moved to the ready-to-run list and,
* if it is the highest priority ready to run task, executed.
diff --git a/arch/x86/src/i486/up_createstack.c b/arch/x86/src/i486/up_createstack.c
index f51d6f2ca2b29e9c31d47b29cd7d79c769e79755..8173457e80a0913dd3f4b18871ecb5c52b77af90 100644
--- a/arch/x86/src/i486/up_createstack.c
+++ b/arch/x86/src/i486/up_createstack.c
@@ -80,7 +80,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
* the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The requested stack size. At least this much
* must be allocated.
diff --git a/arch/x86/src/i486/up_irq.c b/arch/x86/src/i486/up_irq.c
index b216a24a719170da4e910c8fb539788c4be1e283..8689769ead586d15bb84316bfad910fb586dacb9 100644
--- a/arch/x86/src/i486/up_irq.c
+++ b/arch/x86/src/i486/up_irq.c
@@ -81,7 +81,7 @@ static struct idt_entry_s idt_entries[256];
****************************************************************************/
/****************************************************************************
- * Name idt_outb
+ * Name: idt_outb
*
* Description:
* A slightly slower version of outb
@@ -94,7 +94,7 @@ static void idt_outb(uint8_t val, uint16_t addr)
}
/****************************************************************************
- * Name up_remappic
+ * Name: up_remappic
*
* Description:
* Remap the PIC. The Programmable Interrupt Controller (PIC) is used to
@@ -142,7 +142,7 @@ static void up_remappic(void)
}
/****************************************************************************
- * Name up_idtentry
+ * Name: up_idtentry
*
* Description:
* Initialize one IDT entry.
@@ -168,7 +168,7 @@ static void up_idtentry(unsigned int index, uint32_t base, uint16_t sel,
}
/****************************************************************************
- * Name up_idtinit
+ * Name: up_idtinit
*
* Description:
* Initialize the IDT. The Interrupt Descriptor Table (IDT) is a data
diff --git a/arch/x86/src/i486/up_releasestack.c b/arch/x86/src/i486/up_releasestack.c
index 0f23cd3fb7541639a3d05e7d2125001ad2bc6f2c..e83434024ee123ebcd6ea572721a7f112b7f25d6 100644
--- a/arch/x86/src/i486/up_releasestack.c
+++ b/arch/x86/src/i486/up_releasestack.c
@@ -66,7 +66,7 @@
* A task has been stopped. Free all stack related resources retained in
* the defunct TCB.
*
- * Input Parmeters
+ * Input Parameters:
* - dtcb: The TCB containing information about the stack to be released
* - ttype: The thread type. This may be one of following (defined in
* include/nuttx/sched.h):
diff --git a/arch/x86/src/i486/up_stackframe.c b/arch/x86/src/i486/up_stackframe.c
index fab05bff9c079bbe3e17e4e703f22084a487faf5..62bd968a0f7625a0be3f77f8a43fd8588ba28fbe 100644
--- a/arch/x86/src/i486/up_stackframe.c
+++ b/arch/x86/src/i486/up_stackframe.c
@@ -99,7 +99,7 @@
* been removed from the stack. This will still be the initial value
* of the stack pointer when the task is started.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - frame_size: The size of the stack frame to allocate.
*
diff --git a/arch/x86/src/i486/up_usestack.c b/arch/x86/src/i486/up_usestack.c
index b2005fe2de857a4e3c1f78abba2f10945e2ff677..59221bedd6b5f3a5d8ccb939df9e0c8587ce0df8 100644
--- a/arch/x86/src/i486/up_usestack.c
+++ b/arch/x86/src/i486/up_usestack.c
@@ -78,7 +78,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The
* initial value of the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The allocated stack size.
*
diff --git a/arch/x86/src/qemu/qemu.h b/arch/x86/src/qemu/qemu.h
index 561c68da4427af6baead48357cef4bb4f7312469..80eceb18b301a4af75b98146a9c1b8384f48d356 100644
--- a/arch/x86/src/qemu/qemu.h
+++ b/arch/x86/src/qemu/qemu.h
@@ -201,7 +201,7 @@ int i486_dumpgpio(uint16_t pinset, const char *msg);
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/x86/src/qemu/qemu_handlers.c b/arch/x86/src/qemu/qemu_handlers.c
index 0f84efb31354ee3a87fc0eb6e405e081fdb8e7d5..610e4b2ee86843c55b3d042275f2c2291419d6d8 100644
--- a/arch/x86/src/qemu/qemu_handlers.c
+++ b/arch/x86/src/qemu/qemu_handlers.c
@@ -65,7 +65,7 @@ static void idt_outb(uint8_t val, uint16_t addr) noinline_function;
****************************************************************************/
/****************************************************************************
- * Name idt_outb
+ * Name: idt_outb
*
* Description:
* A slightly slower version of outb
diff --git a/arch/x86/src/qemu/qemu_vga.c b/arch/x86/src/qemu/qemu_vga.c
index 151333933207087d0f941465338f757958c862fa..f29b74abc425bbcb77d0073aa522006fad249dc6 100644
--- a/arch/x86/src/qemu/qemu_vga.c
+++ b/arch/x86/src/qemu/qemu_vga.c
@@ -183,7 +183,8 @@ static const struct file_operations g_vgaops =
* you'll need to switch planes to access the whole screen but
* that allows you using any resolution, up to 400x600
*
- * Returns 0=ok, -n=fail
+ * Returned Value:
+ * 0=ok, -n=fail
*/
static int init_graph_vga(int width, int height,int chain4)
diff --git a/arch/xtensa/include/spinlock.h b/arch/xtensa/include/spinlock.h
index 9d0ef213d01b15e9c3865cfc1e020a34765ab799..644253f85433f93de5bb2b523cd30dbb377b34da 100644
--- a/arch/xtensa/include/spinlock.h
+++ b/arch/xtensa/include/spinlock.h
@@ -79,7 +79,7 @@ typedef uint32_t spinlock_t;
* Description:
* Perform an atomic test and set operation on the provided spinlock.
*
- * This function must be provided via the architecture-specific logoic.
+ * This function must be provided via the architecture-specific logic.
*
* Input Parameters:
* lock - The address of spinlock object.
diff --git a/arch/xtensa/src/common/xtensa_assert.c b/arch/xtensa/src/common/xtensa_assert.c
index 24b7fd7e23b70761a06b0ffa71cf32ccef61ec04..e290be637f9d87251d5efe9817a252ea22eabd3c 100644
--- a/arch/xtensa/src/common/xtensa_assert.c
+++ b/arch/xtensa/src/common/xtensa_assert.c
@@ -180,7 +180,7 @@ void up_assert(const uint8_t *filename, int lineno)
* - Co-processor exception
* - High priority level2-6 Exception.
*
- * Input parameters:
+ * Input Parameters:
* xcptcode - Identifies the unhandled exception (see include/esp32/irq.h)
* regs - The register save are at the time of the interrupt.
*
@@ -280,7 +280,7 @@ void xtensa_panic(int xptcode, uint32_t *regs)
* cause varies 32..39.
* 40..63 Reserved
*
- * Input parameters:
+ * Input Parameters:
* exccause - Identifies the EXCCAUSE of the user exception
* regs - The register save are at the time of the interrupt.
*
diff --git a/arch/xtensa/src/common/xtensa_blocktask.c b/arch/xtensa/src/common/xtensa_blocktask.c
index fb1c0f910bb1fb8993753da2b643df287c209d1d..592da9a3f7e67068c5974048a142c8ffa14b4f2b 100644
--- a/arch/xtensa/src/common/xtensa_blocktask.c
+++ b/arch/xtensa/src/common/xtensa_blocktask.c
@@ -63,7 +63,7 @@
* the ready to run list must be stopped. Save its context
* and move it to the inactive list specified by task_state.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to a task in the ready-to-run list (normally
* the task at the head of the list). It most be
* stopped, its context saved and moved into one of the
diff --git a/arch/xtensa/src/common/xtensa_checkstack.c b/arch/xtensa/src/common/xtensa_checkstack.c
index 4853513905721cc9b8242c6eb550ed6cc28ec9a7..bcfbece0d4adc7235e10401da15d41afdf43e2d3 100644
--- a/arch/xtensa/src/common/xtensa_checkstack.c
+++ b/arch/xtensa/src/common/xtensa_checkstack.c
@@ -72,7 +72,7 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size);
* alloc - Allocation base address of the stack
* size - The size of the stack in bytes
*
- * Returned value:
+ * Returned Value:
* The estimated amount of stack space used.
*
****************************************************************************/
@@ -174,7 +174,7 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size)
* Input Parameters:
* None
*
- * Returned value:
+ * Returned Value:
* The estimated amount of stack space used.
*
****************************************************************************/
diff --git a/arch/xtensa/src/common/xtensa_createstack.c b/arch/xtensa/src/common/xtensa_createstack.c
index 68308fb527e2316f18cd32847bd177f2de460a4a..1632ac445fc6d1e299db163bfb080df71f629d86 100644
--- a/arch/xtensa/src/common/xtensa_createstack.c
+++ b/arch/xtensa/src/common/xtensa_createstack.c
@@ -91,7 +91,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
* the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The requested stack size. At least this much
* must be allocated.
diff --git a/arch/xtensa/src/common/xtensa_releasestack.c b/arch/xtensa/src/common/xtensa_releasestack.c
index 94bb2d8cd8ad91c7164b3871c48525b49766e4cc..738da79284a5c9678331f1f395a1322a58a1ce80 100644
--- a/arch/xtensa/src/common/xtensa_releasestack.c
+++ b/arch/xtensa/src/common/xtensa_releasestack.c
@@ -58,7 +58,7 @@
* A task has been stopped. Free all stack related resources retained in
* the defunct TCB.
*
- * Input Parmeters
+ * Input Parameters:
* - dtcb: The TCB containing information about the stack to be released
* - ttype: The thread type. This may be one of following (defined in
* include/nuttx/sched.h):
diff --git a/arch/xtensa/src/common/xtensa_reprioritizertr.c b/arch/xtensa/src/common/xtensa_reprioritizertr.c
index 0226d18f7250ca3bb09143ca126358f6df17ec6e..617bb50c619b385de745f8bf2a1e368673c256e3 100644
--- a/arch/xtensa/src/common/xtensa_reprioritizertr.c
+++ b/arch/xtensa/src/common/xtensa_reprioritizertr.c
@@ -70,7 +70,7 @@
* the priority of the current, running task and it now has the
* priority.
*
- * Inputs:
+ * Input Parameters:
* tcb: The TCB of the task that has been reprioritized
* priority: The new task priority
*
diff --git a/arch/xtensa/src/common/xtensa_schedsigaction.c b/arch/xtensa/src/common/xtensa_schedsigaction.c
index 2dd39913351909eadf1a93a5a0c0c4c363b40f5b..9747d201d343632d7745d1e94850276c206ddae3 100644
--- a/arch/xtensa/src/common/xtensa_schedsigaction.c
+++ b/arch/xtensa/src/common/xtensa_schedsigaction.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/xtensa/src/common/arm_schedulesigaction.c
*
- * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2016-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -114,7 +114,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
if (tcb == this_task())
{
/* CASE 1: We are not in an interrupt handler and a task is
- * signalling itself for some reason.
+ * signaling itself for some reason.
*/
if (!CURRENT_REGS)
@@ -131,7 +131,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*
* Hmmm... there looks like a latent bug here: The following logic
* would fail in the strange case where we are in an interrupt
- * handler, the thread is signalling itself, but a context switch
+ * handler, the thread is signaling itself, but a context switch
* to another task has occurred so that CURRENT_REGS does not
* refer to the thread of this_task()!
*/
@@ -169,7 +169,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
/* Otherwise, we are (1) signaling a task is not running from an
* interrupt handler or (2) we are not in an interrupt handler and the
- * running task is signalling some non-running task.
+ * running task is signaling some non-running task.
*/
else
@@ -230,7 +230,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
cpu = tcb->cpu;
/* CASE 1: We are not in an interrupt handler and a task is
- * signalling itself for some reason.
+ * signaling itself for some reason.
*/
if (cpu == me && !CURRENT_REGS)
@@ -246,61 +246,63 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* CPU. In the former case, we will have to PAUSE the other CPU
* first. But in either case, we will have to modify the return
* state as well as the state in the TCB.
- *
- * Hmmm... there looks like a latent bug here: The following logic
- * would fail in the strange case where we are in an interrupt
- * handler, the thread is signalling itself, but a context switch
- * to another task has occurred so that CURRENT_REGS does not
- * refer to the thread of this_task()!
*/
else
{
- /* If we signalling a task running on the other CPU, we have
+ /* If we signaling a task running on the other CPU, we have
* to PAUSE the other CPU.
*/
if (cpu != me)
{
+ /* Pause the CPU */
+
up_cpu_pause(cpu);
- }
- /* Save the return pc and ps. These will be restored by the
- * signal trampoline after the signals have been delivered.
- *
- * NOTE: that hi-priority interrupts are not disabled.
- */
+ /* Wait while the pause request is pending */
- tcb->xcp.sigdeliver = sigdeliver;
- tcb->xcp.saved_pc = CURRENT_REGS[REG_PC];
- tcb->xcp.saved_ps = CURRENT_REGS[REG_PS];
+ while (up_cpu_pausereq(cpu))
+ {
+ }
- /* Increment the IRQ lock count so that when the task is restarted,
- * it will hold the IRQ spinlock.
- */
+ /* Now tcb on the other CPU can be accessed safely */
- DEBUGASSERT(tcb->irqcount < INT16_MAX);
- tcb->irqcount++;
+ /* Copy tcb->xcp.regs to tcp.xcp.saved. These will be restored
+ * by the signal trampoline after the signal has been delivered.
+ *
+ * NOTE: that hi-priority interrupts are not disabled.
+ */
- /* Handle a possible race condition where the TCB was suspended
- * just before we paused the other CPU. The critical section
- * established above will prevent new threads from running on
- * that CPU, but it will not guarantee that the running thread
- * did not suspend itself (allowing any threads "assigned" to
- * the CPU to run).
- */
+ tcb->xcp.sigdeliver = sigdeliver;
+ tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC];
+ tcb->xcp.saved_ps = tcb->xcp.regs[REG_PS];
- if (tcb->task_state != TSTATE_TASK_RUNNING)
- {
- tcb->xcp.regs[REG_PC] = (uint32_t)_xtensa_sig_trampoline;
+ /* Then set up to vector to the trampoline with interrupts
+ * disabled
+ */
+
+ CURRENT_REGS[REG_PC] = (uint32_t)_xtensa_sig_trampoline;
#ifdef __XTENSA_CALL0_ABI__
- tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM);
+ CURRENT_REGS[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM);
#else
- tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
+ CURRENT_REGS[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
#endif
}
else
{
+ /* tcb is running on the same CPU */
+
+ /* Copy tcb->xcp.regs to tcp.xcp.saved. These will be restored
+ * by the signal trampoline after the signal has been delivered.
+ *
+ * NOTE: that hi-priority interrupts are not disabled.
+ */
+
+ tcb->xcp.sigdeliver = sigdeliver;
+ tcb->xcp.saved_pc = CURRENT_REGS[REG_PC];
+ tcb->xcp.saved_ps = CURRENT_REGS[REG_PS];
+
/* Then set up to vector to the trampoline with interrupts
* disabled
*/
@@ -311,16 +313,6 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
#else
CURRENT_REGS[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
#endif
- /* In an SMP configuration, the interrupt disable logic also
- * involves spinlocks that are configured per the TCB irqcount
- * field. This is logically equivalent to enter_critical_section().
- * The matching call to leave_critical_section() will be
- * performed in up_sigdeliver().
- */
-
- spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock,
- &g_cpu_irqlock);
-
/* And make sure that the saved context in the TCB is the same
* as the interrupt return context.
*/
@@ -328,6 +320,23 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
xtensa_savestate(tcb->xcp.regs);
}
+ /* Increment the IRQ lock count so that when the task is restarted,
+ * it will hold the IRQ spinlock.
+ */
+
+ DEBUGASSERT(tcb->irqcount < INT16_MAX);
+ tcb->irqcount++;
+
+ /* In an SMP configuration, the interrupt disable logic also
+ * involves spinlocks that are configured per the TCB irqcount
+ * field. This is logically equivalent to enter_critical_section().
+ * The matching call to leave_critical_section() will be
+ * performed in up_sigdeliver().
+ */
+
+ spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock,
+ &g_cpu_irqlock);
+
/* RESUME the other CPU if it was PAUSED */
if (cpu != me)
@@ -339,7 +348,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
/* Otherwise, we are (1) signaling a task is not running from an
* interrupt handler or (2) we are not in an interrupt handler and the
- * running task is signalling some other non-running task.
+ * running task is signaling some other non-running task.
*/
else
diff --git a/arch/xtensa/src/common/xtensa_stackframe.c b/arch/xtensa/src/common/xtensa_stackframe.c
index 388238d8de342597a4dfaa962aef5d31f8da488d..884225d69a768c2f24a607c7f3fc9dddf95b1cea 100644
--- a/arch/xtensa/src/common/xtensa_stackframe.c
+++ b/arch/xtensa/src/common/xtensa_stackframe.c
@@ -92,7 +92,7 @@
* been removed from the stack. This will still be the initial value
* of the stack pointer when the task is started.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - frame_size: The size of the stack frame to allocate.
*
diff --git a/arch/xtensa/src/common/xtensa_testset.c b/arch/xtensa/src/common/xtensa_testset.c
index d8fdec3c00b6b06b0a0da2147b803cef6797df25..480a61052f556ce5fc778861ac72ee48ebbb68b4 100644
--- a/arch/xtensa/src/common/xtensa_testset.c
+++ b/arch/xtensa/src/common/xtensa_testset.c
@@ -91,7 +91,7 @@ static inline uint32_t xtensa_compareset(FAR volatile uint32_t *addr,
* Description:
* Perform an atomic test and set operation on the provided spinlock.
*
- * This function must be provided via the architecture-specific logoic.
+ * This function must be provided via the architecture-specific logic.
*
* Input Parameters:
* lock - The address of spinlock object.
diff --git a/arch/xtensa/src/common/xtensa_unblocktask.c b/arch/xtensa/src/common/xtensa_unblocktask.c
index 40ecf73c56b8dbaaf6c1318c84ffe958f6760243..e7fb168ba7a4714a6bc7e49d406e3d3f5ace732b 100644
--- a/arch/xtensa/src/common/xtensa_unblocktask.c
+++ b/arch/xtensa/src/common/xtensa_unblocktask.c
@@ -63,7 +63,7 @@
* but has been prepped to execute. Move the TCB to the
* ready-to-run list, restore its context, and start execution.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to the tcb to be unblocked. This tcb is
* in one of the waiting tasks lists. It must be moved to
* the ready-to-run list and, if it is the highest priority
diff --git a/arch/xtensa/src/common/xtensa_usestack.c b/arch/xtensa/src/common/xtensa_usestack.c
index 0b5db031e91d93d942f11ab484edadb36b066072..4faff7341b2a4ff11fdbfd717e438b731f15758c 100644
--- a/arch/xtensa/src/common/xtensa_usestack.c
+++ b/arch/xtensa/src/common/xtensa_usestack.c
@@ -90,7 +90,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The
* initial value of the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The allocated stack size.
*
diff --git a/arch/xtensa/src/esp32/esp32_cpuidlestack.c b/arch/xtensa/src/esp32/esp32_cpuidlestack.c
index ea475b79b3f6f21036565f6730bd32d29e9a6acb..8239acb96d0dc74c273fddb1a19a94c5789ec884 100644
--- a/arch/xtensa/src/esp32/esp32_cpuidlestack.c
+++ b/arch/xtensa/src/esp32/esp32_cpuidlestack.c
@@ -83,7 +83,7 @@ uint32_t g_cpu1_idlestack[CPU1_IDLETHREAD_STACKWORDS]
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
* the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - cpu: CPU index that indicates which CPU the IDLE task is
* being created for.
* - tcb: The TCB of new CPU IDLE task
diff --git a/arch/xtensa/src/esp32/rom/esp32_gpio.h b/arch/xtensa/src/esp32/rom/esp32_gpio.h
index c29d21ee46236273d0486cb4fc2ef4afe9aa1a6f..38eae27c80ad5d9c27773698a3bac6312ffc0086 100644
--- a/arch/xtensa/src/esp32/rom/esp32_gpio.h
+++ b/arch/xtensa/src/esp32/rom/esp32_gpio.h
@@ -329,7 +329,7 @@ void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv,
bool oen_inv);
/****************************************************************************
- * Name:
+ * Name: gpio_pad_select_gpio
*
* Description:
* Select pad as a gpio function from IOMUX.
diff --git a/arch/z16/src/common/up_blocktask.c b/arch/z16/src/common/up_blocktask.c
index 8328086de622b75e53dbc2e6b9fde822e465520a..0893c933e636ce02bd71662317d75423ef610b9e 100644
--- a/arch/z16/src/common/up_blocktask.c
+++ b/arch/z16/src/common/up_blocktask.c
@@ -61,7 +61,7 @@
* the ready to run list must be stopped. Save its context
* and move it to the inactive list specified by task_state.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to a task in the ready-to-run list (normally
* the task at the head of the list). It most be
* stopped, its context saved and moved into one of the
diff --git a/arch/z16/src/common/up_createstack.c b/arch/z16/src/common/up_createstack.c
index 2c35e68aef8e40c9bf28c181542b4a2874e44220..0bab2d3ab3621902a33c5948bb3e30265f823469 100644
--- a/arch/z16/src/common/up_createstack.c
+++ b/arch/z16/src/common/up_createstack.c
@@ -79,7 +79,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
* the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The requested stack size. At least this much
* must be allocated.
diff --git a/arch/z16/src/common/up_releasestack.c b/arch/z16/src/common/up_releasestack.c
index e0f4c4b27fe33a9a0a836ac8ac6af289298029f1..8d0698ecfdc9343869609413a93788c9100b89c9 100644
--- a/arch/z16/src/common/up_releasestack.c
+++ b/arch/z16/src/common/up_releasestack.c
@@ -66,7 +66,7 @@
* A task has been stopped. Free all stack related resources retained in
* the defunct TCB.
*
- * Input Parmeters
+ * Input Parameters:
* - dtcb: The TCB containing information about the stack to be released
* - ttype: The thread type. This may be one of following (defined in
* include/nuttx/sched.h):
diff --git a/arch/z16/src/common/up_reprioritizertr.c b/arch/z16/src/common/up_reprioritizertr.c
index d4fde47f31d7a94150486ed4db78c776c79c9c69..588ec4d68fd6414682b28659b5f3c081ba44ad2d 100644
--- a/arch/z16/src/common/up_reprioritizertr.c
+++ b/arch/z16/src/common/up_reprioritizertr.c
@@ -69,7 +69,7 @@
* the priority of the current, running task and it now has the
* priority.
*
- * Inputs:
+ * Input Parameters:
* tcb: The TCB of the task that has been reprioritized
* priority: The new task priority
*
diff --git a/arch/z16/src/common/up_stackframe.c b/arch/z16/src/common/up_stackframe.c
index 6a2fe6d3476cdb9cdfad44943c85df7b22107051..1bed013d99590e313f0ef41e676a9f7d3af24ac6 100644
--- a/arch/z16/src/common/up_stackframe.c
+++ b/arch/z16/src/common/up_stackframe.c
@@ -97,7 +97,7 @@
* been removed from the stack. This will still be the initial value
* of the stack pointer when the task is started.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - frame_size: The size of the stack frame to allocate.
*
diff --git a/arch/z16/src/common/up_unblocktask.c b/arch/z16/src/common/up_unblocktask.c
index d9de4e43b95030761a314d7869f5ffea4f033f25..2b09dbc301ca0b9e757e76ef526e79fc36be32f2 100644
--- a/arch/z16/src/common/up_unblocktask.c
+++ b/arch/z16/src/common/up_unblocktask.c
@@ -62,7 +62,7 @@
* but has been prepped to execute. Move the TCB to the
* ready-to-run list, restore its context, and start execution.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to the tcb to be unblocked. This tcb is
* in one of the waiting tasks lists. It must be moved to
* the ready-to-run list and, if it is the highest priority
diff --git a/arch/z16/src/common/up_usestack.c b/arch/z16/src/common/up_usestack.c
index d65609a67d0cae50da5ce0f309f0b998c26694b3..044ecdc3474924c8c6c545e6417c7a93553bf8f7 100644
--- a/arch/z16/src/common/up_usestack.c
+++ b/arch/z16/src/common/up_usestack.c
@@ -78,7 +78,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The
* initial value of the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The allocated stack size.
*
diff --git a/arch/z16/src/z16f/z16f_espi.c b/arch/z16/src/z16f/z16f_espi.c
index da5b88611ee4d22fb3eb8feb7603d5dc2f5be3eb..2a590d96133defc15ca8b0cb28d7f9404095a60e 100644
--- a/arch/z16/src/z16f/z16f_espi.c
+++ b/arch/z16/src/z16f/z16f_espi.c
@@ -788,7 +788,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* port - Identifies the "logical" SPI port. Must be zero in this case.
*
* Returned Value:
diff --git a/arch/z16/src/z16f/z16f_lowuart.S b/arch/z16/src/z16f/z16f_lowuart.S
index ef7c31a6ca4872f4d48be3cee53911625baab5f9..0a893d758583dce81db6aaf5a8397483d2520bc0 100644
--- a/arch/z16/src/z16f/z16f_lowuart.S
+++ b/arch/z16/src/z16f/z16f_lowuart.S
@@ -191,7 +191,7 @@ _up_lowputc:
* Parameters:
* r1 = character
*
- * Return:
+ * Returned Value:
* None
*
* Modifies r0
@@ -230,7 +230,7 @@ _z16f_xmitc1:
* Parmeters:
* None
*
- * Return
+ * Returned Value:
* R0 = Character read
*
*************************************************************************/
diff --git a/arch/z80/src/common/up_blocktask.c b/arch/z80/src/common/up_blocktask.c
index a4aa7b8ed507c28b6f84b03dd56cd6e9445ea59a..6910c87b08edb829efa201610ed85fa93db1f7dd 100644
--- a/arch/z80/src/common/up_blocktask.c
+++ b/arch/z80/src/common/up_blocktask.c
@@ -63,7 +63,7 @@
* the ready to run list must be stopped. Save its context
* and move it to the inactive list specified by task_state.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to a task in the ready-to-run list (normally
* the task at the head of the list). It most be
* stopped, its context saved and moved into one of the
diff --git a/arch/z80/src/common/up_createstack.c b/arch/z80/src/common/up_createstack.c
index a0a2bc2507d029d3a0fd996d2736c10e2b466171..388cfb184d3e8e616d667891d763f7df385d42ee 100644
--- a/arch/z80/src/common/up_createstack.c
+++ b/arch/z80/src/common/up_createstack.c
@@ -78,7 +78,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
* the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The requested stack size. At least this much
* must be allocated.
diff --git a/arch/z80/src/common/up_releasestack.c b/arch/z80/src/common/up_releasestack.c
index 31237a3ee669a3750855fb37b1a6e5bbd2b36be3..5862240d1f9ab48d04ce6c22d73c0033ba1c459e 100644
--- a/arch/z80/src/common/up_releasestack.c
+++ b/arch/z80/src/common/up_releasestack.c
@@ -66,7 +66,7 @@
* A task has been stopped. Free all stack related resources retained in
* the defunct TCB.
*
- * Input Parmeters
+ * Input Parameters:
* - dtcb: The TCB containing information about the stack to be released
* - ttype: The thread type. This may be one of following (defined in
* include/nuttx/sched.h):
diff --git a/arch/z80/src/common/up_reprioritizertr.c b/arch/z80/src/common/up_reprioritizertr.c
index 04675918fdb2933ffe2bd9ed636d818c2d83b254..118ed179c5d329a43836f88ccafaeb44ec68aa01 100644
--- a/arch/z80/src/common/up_reprioritizertr.c
+++ b/arch/z80/src/common/up_reprioritizertr.c
@@ -71,7 +71,7 @@
* the priority of the current, running task and it now has the
* priority.
*
- * Inputs:
+ * Input Parameters:
* tcb: The TCB of the task that has been reprioritized
* priority: The new task priority
*
diff --git a/arch/z80/src/common/up_stackframe.c b/arch/z80/src/common/up_stackframe.c
index 8f4a0f180623672827930602707ca523647bce2a..60ad0851ce5378f1bf51bc07b19303613ad59044 100644
--- a/arch/z80/src/common/up_stackframe.c
+++ b/arch/z80/src/common/up_stackframe.c
@@ -88,7 +88,7 @@
* been removed from the stack. This will still be the initial value
* of the stack pointer when the task is started.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - frame_size: The size of the stack frame to allocate.
*
diff --git a/arch/z80/src/common/up_unblocktask.c b/arch/z80/src/common/up_unblocktask.c
index a27a8e1ddd0c9c38e600581856baa268968477f7..66f7337dc6408fbc7806c61771079cf14ca28708 100644
--- a/arch/z80/src/common/up_unblocktask.c
+++ b/arch/z80/src/common/up_unblocktask.c
@@ -64,7 +64,7 @@
* but has been prepped to execute. Move the TCB to the
* ready-to-run list, restore its context, and start execution.
*
- * Inputs:
+ * Input Parameters:
* tcb: Refers to the tcb to be unblocked. This tcb is
* in one of the waiting tasks lists. It must be moved to
* the ready-to-run list and, if it is the highest priority
diff --git a/arch/z80/src/common/up_usestack.c b/arch/z80/src/common/up_usestack.c
index dd82424d33fc22e0b348906a85f89b2d85f0c713..7c75a14419c7e46b96ff1fb4f0c052ddbada3827 100644
--- a/arch/z80/src/common/up_usestack.c
+++ b/arch/z80/src/common/up_usestack.c
@@ -77,7 +77,7 @@
* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The
* initial value of the stack pointer.
*
- * Inputs:
+ * Input Parameters:
* - tcb: The TCB of new task
* - stack_size: The allocated stack size.
*
diff --git a/arch/z80/src/ez80/ez80_emac.c b/arch/z80/src/ez80/ez80_emac.c
index 55896c08ff6013b3b5a2d7f13469ba20bbeb122c..7ef110f8112e79fc302bfaea8157a1b2d0110732 100644
--- a/arch/z80/src/ez80/ez80_emac.c
+++ b/arch/z80/src/ez80/ez80_emac.c
@@ -2537,7 +2537,7 @@ int up_netinitialize(void)
#endif
priv->dev.d_private = (FAR void*)&g_emac; /* Used to recover private state from dev */
- /* Create a watchdog for timing polling for and timing of transmisstions */
+ /* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create(); /* Create periodic poll timer */
priv->txtimeout = wd_create(); /* Create TX timeout timer */
diff --git a/arch/z80/src/ez80/ez80_i2c.c b/arch/z80/src/ez80/ez80_i2c.c
index 6413a39d4b6bd860f28b1e44ce4a545cc9cd6c18..a7b7403e672038ece6846095850f675b78a9d5dd 100644
--- a/arch/z80/src/ez80/ez80_i2c.c
+++ b/arch/z80/src/ez80/ez80_i2c.c
@@ -929,7 +929,7 @@ static int ez80_i2c_transfer(FAR struct i2c_master_s *dev,
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple I2C interfaces)
*
* Returned Value:
diff --git a/arch/z80/src/ez80/ez80_spi.c b/arch/z80/src/ez80/ez80_spi.c
index d7f14c7e015056ea0f14b28b7cc157b2eaaf4e6f..5f337d441ab2f7dfaa685b951e297bcdf2861f8f 100644
--- a/arch/z80/src/ez80/ez80_spi.c
+++ b/arch/z80/src/ez80/ez80_spi.c
@@ -438,7 +438,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t bu
* required. Theregore, all GPIO chip management is deferred to board-
* specific logic.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/z80/src/ez80/ez80f91_i2c.h b/arch/z80/src/ez80/ez80f91_i2c.h
index b59d4ffc7b157d164e43d204dd6440f59461d1ba..a296eeab7089a745313e1b55a4e9710c543fc26e 100644
--- a/arch/z80/src/ez80/ez80f91_i2c.h
+++ b/arch/z80/src/ez80/ez80f91_i2c.h
@@ -150,7 +150,7 @@ extern "C"
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
@@ -166,7 +166,7 @@ FAR struct i2c_master_s *ez80_i2cbus_initialize(int port);
* Description:
* De-initialize the selected I2C port, and power down the device.
*
- * Input Parameter:
+ * Input Parameters:
* Device structure as returned by the ez80_i2cbus_initialize()
*
* Returned Value:
diff --git a/arch/z80/src/ez80/ez80f91_spi.h b/arch/z80/src/ez80/ez80f91_spi.h
index fe7c34bb7e49e3566de06cdbd8f743046f372e8f..0c49cad1d7b699209d1d93fbf58f1c57e97d894d 100644
--- a/arch/z80/src/ez80/ez80f91_spi.h
+++ b/arch/z80/src/ez80/ez80f91_spi.h
@@ -114,7 +114,7 @@ extern "C"
* required. Theregore, all GPIO chip management is deferred to board-
* specific logic.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/arch/z80/src/z8/z8_i2c.c b/arch/z80/src/z8/z8_i2c.c
index 465debc4037eb5812b51660a4f407a97ab84c982..599e6adb323bea81e23fd48eb664964d6fbea5ff 100644
--- a/arch/z80/src/z8/z8_i2c.c
+++ b/arch/z80/src/z8/z8_i2c.c
@@ -638,7 +638,7 @@ static int z8_i2c_reset(FAR struct i2c_master_s * dev)
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple I2C interfaces)
*
* Returned Value:
diff --git a/audio/audio.c b/audio/audio.c
index e4acb10b895e70a0bcfb1e310ecdd1919abc993b..1dde458efd51f4f70415c0da43d7f187981c158a 100644
--- a/audio/audio.c
+++ b/audio/audio.c
@@ -233,9 +233,9 @@ static int audio_close(FAR struct file *filep)
lower->ops->shutdown(lower);
}
+
ret = OK;
-//errout_with_sem:
nxsem_post(&upper->exclsem);
errout:
@@ -680,7 +680,7 @@ static int audio_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
* to enqueue additional buffers and "wake them up" for further
* processing.
*
- * Input parameters:
+ * Input Parameters:
* handle - This is the handle that was provided to the lower-half
* start() method.
* apb - A pointer to the previsously enqueued ap_buffer_s
@@ -767,7 +767,7 @@ static inline void audio_complete(FAR struct audio_upperhalf_s *upper,
* Provides a callback interface for lower-half drivers to call to the
* upper-half for buffer dequeueing, error reporting, etc.
*
- * Input parameters:
+ * Input Parameters:
* priv - Private context data owned by the upper-half
* reason - The reason code for the callback
* apb - A pointer to the previsously enqueued ap_buffer_s
@@ -854,7 +854,7 @@ static void audio_callback(FAR void *handle, uint16_t reason,
* When this function is called, the "lower half" driver should be in the
* reset state (as if the shutdown() method had already been called).
*
- * Input parameters:
+ * Input Parameters:
* path - The full path to the driver to be registers in the NuttX pseudo-
* filesystem. The recommended convention is to name Audio drivers
* based on the function they provide, such as "/dev/pcm0", "/dev/mp31",
diff --git a/binfmt/binfmt.h b/binfmt/binfmt.h
index cfde554d4e453f3262db9bed85b9e01685fd4a36..84775cfbd9f4391a30571e208676dd86e79d948a 100644
--- a/binfmt/binfmt.h
+++ b/binfmt/binfmt.h
@@ -78,7 +78,7 @@ EXTERN FAR struct binfmt_s *g_binfmts;
* Description:
* Dump the contents of struct binary_s.
*
- * Input Parameter:
+ * Input Parameters:
* bin - Load structure
*
* Returned Value:
@@ -101,7 +101,7 @@ int dump_module(FAR const struct binary_s *bin);
* address environment of the new process address environment. So we
* do not have any real option other than to copy the callers argv[] list.
*
- * Input Parameter:
+ * Input Parameters:
* bin - Load structure
* argv - Argument list
*
@@ -118,7 +118,7 @@ int binfmt_copyargv(FAR struct binary_s *bin, FAR char * const *argv);
* Description:
* Release the copied argv[] list.
*
- * Input Parameter:
+ * Input Parameters:
* bin - Load structure
*
* Returned Value:
diff --git a/binfmt/binfmt_copyargv.c b/binfmt/binfmt_copyargv.c
index f0a594f5a6d20e2408aad0874d1a207852373aa5..c3f3dbcc083a772d562b25c34825933405b6c8f5 100644
--- a/binfmt/binfmt_copyargv.c
+++ b/binfmt/binfmt_copyargv.c
@@ -72,7 +72,7 @@
* address environment of the new process address environment. So we
* do not have any real option other than to copy the callers argv[] list.
*
- * Input Parameter:
+ * Input Parameters:
* bin - Load structure
* argv - Argument list
*
@@ -167,7 +167,7 @@ int binfmt_copyargv(FAR struct binary_s *bin, FAR char * const *argv)
* Description:
* Release the copied argv[] list.
*
- * Input Parameter:
+ * Input Parameters:
* binp - Load structure
*
* Returned Value:
diff --git a/binfmt/binfmt_loadmodule.c b/binfmt/binfmt_loadmodule.c
index 375616203a41b8ea1d2a3e572aec4b543d0bdda8..ea5def2acbaf09c5e74ae524cb1c4d42a30a4c1a 100644
--- a/binfmt/binfmt_loadmodule.c
+++ b/binfmt/binfmt_loadmodule.c
@@ -1,7 +1,7 @@
/****************************************************************************
* binfmt/binfmt_loadmodule.c
*
- * Copyright (C) 2009, 2014, 2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009, 2014, 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -43,6 +43,7 @@
#include
#include
+#include
#include
#include
@@ -88,11 +89,10 @@ static int load_default_priority(FAR struct binary_s *bin)
/* Get the priority of this thread */
- ret = sched_getparam(0, ¶m);
+ ret = nxsched_getparam(0, ¶m);
if (ret < 0)
{
- ret = -get_errno();
- berr("ERROR: sched_getparam failed: %d\n", ret);
+ berr("ERROR: nxsched_getparam failed: %d\n", ret);
return ret;
}
diff --git a/binfmt/binfmt_schedunload.c b/binfmt/binfmt_schedunload.c
index f742b49396257607b0c946ee2607eaf4ead292c5..1996acd107544e0d27cad04f8ea978f4005cbd09 100644
--- a/binfmt/binfmt_schedunload.c
+++ b/binfmt/binfmt_schedunload.c
@@ -52,14 +52,6 @@
#if !defined(CONFIG_BINFMT_DISABLE) && defined(CONFIG_SCHED_HAVE_PARENT)
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
/****************************************************************************
* Private Data
****************************************************************************/
@@ -82,7 +74,7 @@ FAR struct binary_s *g_unloadhead;
*
* This function will add one structure to the linked list
*
- * Input Parameter:
+ * Input Parameters:
* pid - The task ID of the child task
* bin - This structure must have been allocated with kmm_malloc() and must
* persist until the task unloads
@@ -125,7 +117,7 @@ static void unload_list_add(pid_t pid, FAR struct binary_s *bin)
*
* This function will remove one structure to the linked list
*
- * Input Parameter:
+ * Input Parameters:
* pid - The task ID of the child task
*
* Returned Value:
@@ -192,7 +184,7 @@ static FAR struct binary_s *unload_list_remove(pid_t pid)
* bin was allocated with kmm_malloc() or friends and will also automatically
* free the structure with kmm_free() when the task exists.
*
- * Input Parameter:
+ * Input Parameters:
* pid - The ID of the task that just exited
* arg - A reference to the load structure cast to FAR void *
*
@@ -251,7 +243,7 @@ static void unload_callback(int signo, siginfo_t *info, void *ucontext)
* or friends. It will also automatically free the structure with kmm_free()
* after unloading the module.
*
- * Input Parameter:
+ * Input Parameters:
* pid - The task ID of the child task
* bin - This structure must have been allocated with kmm_malloc() and must
* persist until the task unloads
diff --git a/binfmt/binfmt_unregister.c b/binfmt/binfmt_unregister.c
index f97b06ff2da702ee26af72c61d1b9015d3fbe095..e0a6fe80e649a5c71bb517ae72b230c92fee07aa 100644
--- a/binfmt/binfmt_unregister.c
+++ b/binfmt/binfmt_unregister.c
@@ -50,22 +50,6 @@
#ifndef CONFIG_BINFMT_DISABLE
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
diff --git a/binfmt/builtin.c b/binfmt/builtin.c
index 88ad846c7fc21031d826d79cabb4dcfbb2bef721..fda996429f22f9c088991a4568d8ad76167d7392 100644
--- a/binfmt/builtin.c
+++ b/binfmt/builtin.c
@@ -195,7 +195,7 @@ int builtin_initialize(void)
void builtin_uninitialize(void)
{
- unregister_binfmt(&g_builtin_binfmt);
+ (void)unregister_binfmt(&g_builtin_binfmt);
}
#endif /* CONFIG_BUILTIN */
diff --git a/binfmt/elf.c b/binfmt/elf.c
index 37b1e117cd4f4271fe461921ff9318de47a0cc0a..d4e227c26c33ddfe61456674d7be142c6907719e 100644
--- a/binfmt/elf.c
+++ b/binfmt/elf.c
@@ -362,7 +362,7 @@ int elf_initialize(void)
void elf_uninitialize(void)
{
- unregister_binfmt(&g_elfbinfmt);
+ (void)unregister_binfmt(&g_elfbinfmt);
}
#endif /* CONFIG_ELF */
diff --git a/binfmt/libelf/libelf_init.c b/binfmt/libelf/libelf_init.c
index 7307261df623eedaec37ecfde97ef1922c96a9d7..3e09a6676aa95cd1187f535f17b3d4846b24f7a8 100644
--- a/binfmt/libelf/libelf_init.c
+++ b/binfmt/libelf/libelf_init.c
@@ -101,7 +101,7 @@ static inline int elf_filelen(FAR struct elf_loadinfo_s *loadinfo,
ret = stat(filename, &buf);
if (ret < 0)
{
- int errval = errno;
+ int errval = get_errno();
berr("Failed to stat file: %d\n", errval);
return -errval;
}
@@ -165,7 +165,7 @@ int elf_init(FAR const char *filename, FAR struct elf_loadinfo_s *loadinfo)
loadinfo->filfd = open(filename, O_RDONLY);
if (loadinfo->filfd < 0)
{
- int errval = errno;
+ int errval = get_errno();
berr("Failed to open ELF binary %s: %d\n", filename, errval);
return -errval;
}
diff --git a/binfmt/libelf/libelf_read.c b/binfmt/libelf/libelf_read.c
index 490ba1fdd9029d6bdf112ed33a1189ba3817b136..a240e107fbcc6553916d121dd273f669e553b5f7 100644
--- a/binfmt/libelf/libelf_read.c
+++ b/binfmt/libelf/libelf_read.c
@@ -127,7 +127,7 @@ int elf_read(FAR struct elf_loadinfo_s *loadinfo, FAR uint8_t *buffer,
rpos = lseek(loadinfo->filfd, offset, SEEK_SET);
if (rpos != offset)
{
- int errval = errno;
+ int errval = get_errno();
berr("Failed to seek to position %lu: %d\n",
(unsigned long)offset, errval);
return -errval;
diff --git a/binfmt/libnxflat/libnxflat_init.c b/binfmt/libnxflat/libnxflat_init.c
index eff6cd8b29dad8065a2e190cdb41b62edafd352f..d3f48c0073b0d3558d920e4907c0bd60d911f86c 100644
--- a/binfmt/libnxflat/libnxflat_init.c
+++ b/binfmt/libnxflat/libnxflat_init.c
@@ -111,7 +111,7 @@ int nxflat_init(const char *filename, struct nxflat_loadinfo_s *loadinfo)
loadinfo->filfd = open(filename, O_RDONLY);
if (loadinfo->filfd < 0)
{
- int errval = errno;
+ int errval = get_errno();
berr("Failed to open NXFLAT binary %s: %d\n", filename, errval);
return -errval;
}
diff --git a/binfmt/libnxflat/libnxflat_read.c b/binfmt/libnxflat/libnxflat_read.c
index 720f7256796d6674b76bc2099b76c9c3acb5de8c..09016f5d3da6027949ba4be60629b2ec48aef704 100644
--- a/binfmt/libnxflat/libnxflat_read.c
+++ b/binfmt/libnxflat/libnxflat_read.c
@@ -131,7 +131,7 @@ int nxflat_read(struct nxflat_loadinfo_s *loadinfo, char *buffer,
rpos = lseek(loadinfo->filfd, offset, SEEK_SET);
if (rpos != offset)
{
- int errval = errno;
+ int errval = get_errno();
berr("Failed to seek to position %d: %d\n", offset, errval);
return -errval;
}
diff --git a/binfmt/nxflat.c b/binfmt/nxflat.c
index c2f1c06f78b0f0385f73ea9f33f2317d480ee4b7..16fdc17e181f353630a275f97bf2b61e1e085f93 100644
--- a/binfmt/nxflat.c
+++ b/binfmt/nxflat.c
@@ -274,7 +274,7 @@ int nxflat_initialize(void)
void nxflat_uninitialize(void)
{
- unregister_binfmt(&g_nxflatbinfmt);
+ (void)unregister_binfmt(&g_nxflatbinfmt);
}
#endif /* CONFIG_NXFLAT */
diff --git a/binfmt/pcode.c b/binfmt/pcode.c
index 7e38c14e9b2d981fb78ab41052d1b16f0596dc5a..b8fc5aaf09197b5e0b6bf7fd71c342212c221e5e 100644
--- a/binfmt/pcode.c
+++ b/binfmt/pcode.c
@@ -583,11 +583,7 @@ void pcode_uninitialize(void)
ret = unregister_binfmt(&g_pcode_binfmt);
if (ret < 0)
{
- int errval = get_errno();
- DEBUGASSERT(errval > 0);
-
- berr("ERROR: unregister_binfmt() failed: %d\n", errval);
- UNUSED(errval);
+ berr("ERROR: unregister_binfmt() failed: %d\n", ret);
}
#ifdef CONFIG_BINFMT_PCODE_TEST_FS
diff --git a/configs/Kconfig b/configs/Kconfig
index c278ece1e8d677905c752aac7acc422be220f7eb..bf770edd1dcc0ed827fc230179cbdc451de18f6c 100644
--- a/configs/Kconfig
+++ b/configs/Kconfig
@@ -2351,15 +2351,6 @@ config BOARDCTL_USBDEVCTRL
---help---
Enables support for the BOARDIOC_USBDEV_CONTROL boardctl() command.
-config BOARDCTL_TSCTEST
- bool "Enable touchscreen test interfaces"
- default n
- ---help---
- Enables support for the BOARDIOC_TSCTEST_SETUP and
- BOARDIOC_TSCTEST_TEARDOWN boardctl() commands. Architecture
- specific logic must provide board_tsc_setup() and
- board_tsc_teardown() interfaces.
-
config BOARDCTL_IOCTL
bool "Board-specific boardctl() commands"
default n
diff --git a/configs/arduino-due/README.txt b/configs/arduino-due/README.txt
index bb6d7f08aa8ad1197ce4e99a1fc82938a624040b..0de6bcb4d22b2fb73a3bbc9b88d8156ddd9fe194 100644
--- a/configs/arduino-due/README.txt
+++ b/configs/arduino-due/README.txt
@@ -330,6 +330,12 @@ Serial Consoles
Loading Code
============
+ [NOTE: I believe that there have been significant changes to the more
+ recent tool environment such that Bossac may no longer be usable. I
+ don't know that for certain and perhaps someone with more knowledge of
+ the tools than I could make this work. See the Flip'n'Clip SAM3X README
+ file for additional information.]
+
Installing the Arduino USB Driver under Windows:
------------------------------------------------
diff --git a/configs/arduino-due/nsh/defconfig b/configs/arduino-due/nsh/defconfig
index 15814e72310a2dd88fe34e517bf6d0aee79c1235..a791c14a5b1b925e76d932a398e098f6f269bba7 100644
--- a/configs/arduino-due/nsh/defconfig
+++ b/configs/arduino-due/nsh/defconfig
@@ -11,9 +11,6 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
CONFIG_BOARD_LOOPSPERMSEC=6965
CONFIG_BUILTIN=y
CONFIG_CXX_NEWLONG=y
-CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NSH=y
CONFIG_FS_PROCFS=y
@@ -24,6 +21,7 @@ CONFIG_MAX_WDOGPARMS=2
CONFIG_MM_REGIONS=3
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
+CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_DISABLE_IFUPDOWN=y
CONFIG_NSH_FILEIOSIZE=512
@@ -40,7 +38,7 @@ CONFIG_SDCLONE_DISABLE=y
CONFIG_START_DAY=28
CONFIG_START_MONTH=6
CONFIG_START_YEAR=2013
-CONFIG_TASK_NAME_SIZE=0
+CONFIG_TASK_NAME_SIZE=32
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WDOG_INTRESERVE=0
diff --git a/configs/arduino-due/src/arduino-due.h b/configs/arduino-due/src/arduino-due.h
index 0e2b6736b347bd156fb3c25fd49247146ab77108..01768855d7601d5bfef8f3aca188df5dc4a31a59 100644
--- a/configs/arduino-due/src/arduino-due.h
+++ b/configs/arduino-due/src/arduino-due.h
@@ -166,7 +166,7 @@
* and the SD card.
* 2. UART0 cannot be used. USARTs on the COMM connector should be available.
* 3. Parallel data is not contiguous in the PIO register
- * 4. Touchcontroller /CS pin is connected to ground (always selected).
+ * 4. Touch controller /CS pin is connected to ground (always selected).
* 5. Either PA28 or PC29 may drive PWM10
*/
@@ -308,7 +308,7 @@
* Public Functions
************************************************************************************/
-/****************************************************************************
+/************************************************************************************
* Name: sam_bringup
*
* Description:
@@ -320,23 +320,44 @@
* CONFIG_BOARD_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
* Called from the NSH library
*
- ****************************************************************************/
+ ************************************************************************************/
int sam_bringup(void);
-/****************************************************************************
+/************************************************************************************
* Name: sam_sdinitialize
*
* Description:
* Initialize the SPI-based SD card.
*
- ****************************************************************************/
+ ************************************************************************************/
#if defined(CONFIG_ARDUINO_ITHEAD_TFT) && defined(CONFIG_SPI_BITBANG) && \
defined(CONFIG_MMCSD_SPI)
int sam_sdinitialize(int minor);
#endif
+/************************************************************************************
+ * Name: sam_tsc_setup
+ *
+ * Description:
+ * This function is called by board-bringup logic to configure the touchscreen
+ * device. This function will register the driver as /dev/inputN where N is the
+ * minor device number.
+ *
+ * Input Parameters:
+ * minor - The input device minor number
+ *
+ * Returned Value:
+ * Zero is returned on success. Otherwise, a negated errno value is returned to
+ * indicate the nature of the failure.
+ *
+ ************************************************************************************/
+
+#if defined(CONFIG_ARDUINO_ITHEAD_TFT) && defined(CONFIG_SPI_BITBANG) && \
+ defined(CONFIG_INPUT_ADS7843E)
+int sam_tsc_setup(int minor);
+#endif
#endif /* __ASSEMBLY__ */
#endif /* __CONFIGS_ARDUINO_DUE_SRC_ARDUNO_DUE_H */
diff --git a/configs/arduino-due/src/sam_bringup.c b/configs/arduino-due/src/sam_bringup.c
index 298a5b0dbb9704828450ed394b3629a041c9ed73..50dc141500b6377b56d241c0bf4e8f41d2b02b91 100644
--- a/configs/arduino-due/src/sam_bringup.c
+++ b/configs/arduino-due/src/sam_bringup.c
@@ -118,6 +118,17 @@ int sam_bringup(void)
}
#endif
+#if defined(CONFIG_ARDUINO_ITHEAD_TFT) && defined(CONFIG_SPI_BITBANG) && \
+ defined(CONFIG_INPUT_ADS7843E)
+ /* Initialize the touchscreen */
+
+ ret = sam_tsc_setup(0);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: sam_tsc_setup failed: %d\n", ret);
+ }
+#endif
+
UNUSED(ret);
return OK;
}
diff --git a/configs/arduino-due/src/sam_touchscreen.c b/configs/arduino-due/src/sam_touchscreen.c
index 4e78c9376a161598eca7b0a1097862bc9c8d166f..48dae4c1625653ff823bcff3dc61efc62d02bb1f 100644
--- a/configs/arduino-due/src/sam_touchscreen.c
+++ b/configs/arduino-due/src/sam_touchscreen.c
@@ -336,13 +336,12 @@ static FAR struct spi_dev_s *sam_tsc_spiinitialize(void)
****************************************************************************/
/****************************************************************************
- * Name: board_tsc_setup
+ * Name: sam_tsc_setup
*
* Description:
- * Each board that supports a touchscreen device must provide this function.
- * This function is called by application-specific, setup logic to
- * configure the touchscreen device. This function will register the driver
- * as /dev/inputN where N is the minor device number.
+ * This function is called by board-bringup logic to configure the
+ * touchscreen device. This function will register the driver as
+ * /dev/inputN where N is the minor device number.
*
* Input Parameters:
* minor - The input device minor number
@@ -353,79 +352,42 @@ static FAR struct spi_dev_s *sam_tsc_spiinitialize(void)
*
****************************************************************************/
-int board_tsc_setup(int minor)
+int sam_tsc_setup(int minor)
{
FAR struct spi_dev_s *dev;
- static bool initialized = false;
int ret;
iinfo("minor %d\n", minor);
DEBUGASSERT(minor == 0);
- /* Have we already initialized? Since we never uninitialize we must prevent
- * multiple initializations. This is necessary, for example, when the
- * touchscreen example is used as a built-in application in NSH and can be
- * called numerous time. It will attempt to initialize each time.
- */
+ /* Configure and enable the XPT2046 interrupt pin as an input */
- if (!initialized)
- {
- /* Configure and enable the XPT2046 interrupt pin as an input */
-
- (void)sam_configgpio(GPIO_TSC_IRQ);
-
- /* Configure the PIO interrupt */
+ (void)sam_configgpio(GPIO_TSC_IRQ);
- sam_gpioirq(SAM_TSC_IRQ);
+ /* Configure the PIO interrupt */
- /* Get an instance of the SPI interface for the touchscreen chip select */
+ sam_gpioirq(SAM_TSC_IRQ);
- dev = sam_tsc_spiinitialize();
- if (!dev)
- {
- ierr("ERROR: Failed to initialize bit bang SPI\n");
- return -ENODEV;
- }
+ /* Get an instance of the SPI interface for the touchscreen chip select */
- /* Initialize and register the SPI touschscreen device */
-
- ret = ads7843e_register(dev, &g_tscinfo, CONFIG_ADS7843E_DEVMINOR);
- if (ret < 0)
- {
- ierr("ERROR: Failed to register touchscreen device\n");
- /* up_spiuninitialize(dev); */
- return -ENODEV;
- }
+ dev = sam_tsc_spiinitialize();
+ if (!dev)
+ {
+ ierr("ERROR: Failed to initialize bit bang SPI\n");
+ return -ENODEV;
+ }
- /* Now we are initialized */
+ /* Initialize and register the SPI touschscreen device */
- initialized = true;
+ ret = ads7843e_register(dev, &g_tscinfo, CONFIG_ADS7843E_DEVMINOR);
+ if (ret < 0)
+ {
+ ierr("ERROR: Failed to register touchscreen device\n");
+ /* up_spiuninitialize(dev); */
+ return -ENODEV;
}
return OK;
}
-/****************************************************************************
- * Name: board_tsc_teardown
- *
- * Description:
- * Each board that supports a touchscreen device must provide this function.
- * This function is called by application-specific, setup logic to
- * uninitialize the touchscreen device.
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
-void board_tsc_teardown(void)
-{
- /* No support for un-initializing the touchscreen XPT2046 device. It will
- * continue to run and process touch interrupts in the background.
- */
-}
-
#endif /* CONFIG_ARDUINO_ITHEAD_TFT && CONFIG_SPI_BITBANG && CONFIG_INPUT_ADS7843E */
diff --git a/configs/boardctl.c b/configs/boardctl.c
index d5404711354126b8a5cf3eac2d57a17ef17fa677..d7e6d3c4ee6f8d0f5bb279f058d2f5f556cca9f6 100644
--- a/configs/boardctl.c
+++ b/configs/boardctl.c
@@ -401,35 +401,6 @@ int boardctl(unsigned int cmd, uintptr_t arg)
break;
#endif
-#ifdef CONFIG_BOARDCTL_TSCTEST
- /* CMD: BOARDIOC_TSCTEST_SETUP
- * DESCRIPTION: Touchscreen controller test configuration
- * ARG: Touch controller device minor number
- * CONFIGURATION: CONFIG_LIB_BOARDCTL && CONFIG_BOARDCTL_TSCTEST
- * DEPENDENCIES: Board logic must provide board_tsc_setup()
- */
-
- case BOARDIOC_TSCTEST_SETUP:
- {
- ret = board_tsc_setup((int)arg);
- }
- break;
-
- /* CMD: BOARDIOC_TSCTEST_TEARDOWN
- * DESCRIPTION: Touchscreen controller test configuration
- * ARG: None
- * CONFIGURATION: CONFIG_LIB_BOARDCTL && CONFIG_BOARDCTL_TSCTEST
- * DEPENDENCIES: Board logic must provide board_tsc_teardown()
- */
-
- case BOARDIOC_TSCTEST_TEARDOWN:
- {
- board_tsc_teardown();
- ret = OK;
- }
- break;
-#endif
-
default:
{
#ifdef CONFIG_BOARDCTL_IOCTL
diff --git a/configs/cloudctrl/src/stm32_usb.c b/configs/cloudctrl/src/stm32_usb.c
index 955377a5dd8cc1d85baa2fe985b427b7653804f2..bf13400a5b804ca8dffb8d10ffdafb2e837ceb70 100644
--- a/configs/cloudctrl/src/stm32_usb.c
+++ b/configs/cloudctrl/src/stm32_usb.c
@@ -48,6 +48,7 @@
#include
#include
+#include
#include
#include
#include
@@ -209,9 +210,9 @@ int stm32_usbhost_initialize(void)
uinfo("Start usbhost_waiter\n");
- pid = task_create("usbhost", CONFIG_USBHOST_DEFPRIO,
- CONFIG_USBHOST_STACKSIZE,
- (main_t)usbhost_waiter, (FAR char * const *)NULL);
+ pid = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO,
+ CONFIG_USBHOST_STACKSIZE,
+ (main_t)usbhost_waiter, (FAR char * const *)NULL);
return pid < 0 ? -ENOEXEC : OK;
}
@@ -272,11 +273,11 @@ void stm32_usbhost_vbusdrive(int iface, bool enable)
* Setup to receive an interrupt-level callback if an overcurrent condition is
* detected.
*
- * Input Parameter:
+ * Input Parameters:
* handler - New overcurrent interrupt handler
* arg - The argument provided for the interrupt handler
*
- * Returned value:
+ * Returned Value:
* Zero (OK) is returned on success. Otherwise, a negated errno value is returned
* to indicate the nature of the failure.
*
diff --git a/configs/dk-tm4c129x/include/board.h b/configs/dk-tm4c129x/include/board.h
index 5279f43cf3264bd6efca01e6bd4c172eef5b179e..c52a8f3b3ef29ce94ebb15a0e841948fd2b14e05 100644
--- a/configs/dk-tm4c129x/include/board.h
+++ b/configs/dk-tm4c129x/include/board.h
@@ -255,7 +255,7 @@
* Description:
* Initialize and register the TMP-100 Temperature Sensor driver.
*
- * Input parameters:
+ * Input Parameters:
* devpath - The full path to the driver to register. E.g., "/dev/temp0"
*
* Returned Value:
diff --git a/configs/dk-tm4c129x/src/tm4c_tmp100.c b/configs/dk-tm4c129x/src/tm4c_tmp100.c
index 29ab1a9aeb1362723c7fcdb7ed4a4c34e96d0af2..0238c62bb5e0b88eb3e70343d976ead17728decc 100644
--- a/configs/dk-tm4c129x/src/tm4c_tmp100.c
+++ b/configs/dk-tm4c129x/src/tm4c_tmp100.c
@@ -68,7 +68,7 @@
* Description:
* Initialize and register the LM-75 Temperature Sensor driver.
*
- * Input parameters:
+ * Input Parameters:
* devpath - The full path to the driver to register. E.g., "/dev/temp0"
*
* Returned Value:
diff --git a/configs/ea3131/src/lpc31_usbhost.c b/configs/ea3131/src/lpc31_usbhost.c
index fe16aa16378afecbe9ba8e50d414af6da84060ff..eee4f004decde2e6faec9f919920bb97a97e39e8 100644
--- a/configs/ea3131/src/lpc31_usbhost.c
+++ b/configs/ea3131/src/lpc31_usbhost.c
@@ -48,6 +48,7 @@
#include
#include
+#include
#include
#include
#include
@@ -225,8 +226,9 @@ int lpc31_usbhost_initialize(void)
/* Start a thread to handle device connection. */
- pid = task_create("EHCI Monitor", CONFIG_USBHOST_DEFPRIO, CONFIG_USBHOST_STACKSIZE,
- (main_t)ehci_waiter, (FAR char * const *)NULL);
+ pid = kthread_create("EHCI Monitor", CONFIG_USBHOST_DEFPRIO,
+ CONFIG_USBHOST_STACKSIZE,
+ (main_t)ehci_waiter, (FAR char * const *)NULL);
if (pid < 0)
{
uerr("ERROR: Failed to create ehci_waiter task: %d\n", ret);
@@ -284,11 +286,11 @@ void lpc31_usbhost_vbusdrive(int rhport, bool enable)
* Setup to receive an interrupt-level callback if an overcurrent condition is
* detected.
*
- * Input parameter:
+ * Input Parameters:
* handler - New overcurrent interrupt handler
* arg - The argument that will accompany the interrupt
*
- * Returned value:
+ * Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on failure.
*
************************************************************************************/
diff --git a/configs/flipnclick-pic32mz/Kconfig b/configs/flipnclick-pic32mz/Kconfig
index 109d9a47f37b61662703e7d75d7ddb838b2dfb4a..befce845ba996418745e0bebebb8a58f72429174 100644
--- a/configs/flipnclick-pic32mz/Kconfig
+++ b/configs/flipnclick-pic32mz/Kconfig
@@ -4,4 +4,30 @@
#
if ARCH_BOARD_FLIPNCLICK_PIC32MZ
-endif
+
+config FLIPNCLICK_PIC32MZ_SSD1306
+ bool "SSD1306 Click Present"
+ default n
+ depends on LCD_SSD1306
+ select NXSTART_EXTERNINIT if NX
+
+choice
+ prompt "SSD1306 mikroBUS"
+ default FLIPNCLICK_PIC32MZ_SSD1306_MBA
+ depends on FLIPNCLICK_PIC32MZ_SSD1306
+
+config FLIPNCLICK_PIC32MZ_SSD1306_MBA
+ bool "mikroBUS A"
+
+config FLIPNCLICK_PIC32MZ_SSD1306_MBB
+ bool "mikroBUS B"
+
+config FLIPNCLICK_PIC32MZ_SSD1306_MBC
+ bool "mikroBUS C"
+
+config FLIPNCLICK_PIC32MZ_SSD1306_MBD
+ bool "mikroBUS D"
+
+endchoice # SSD1306 mikroBUS
+
+endif # ARCH_BOARD_FLIPNCLICK_PIC32MZ
diff --git a/configs/flipnclick-pic32mz/README.txt b/configs/flipnclick-pic32mz/README.txt
index 000cda2fcc0b43686d5a2493a023704476bb045f..5707bd1569a2853180a1815fa54f632232810b48 100644
--- a/configs/flipnclick-pic32mz/README.txt
+++ b/configs/flipnclick-pic32mz/README.txt
@@ -11,10 +11,13 @@ Contents
Port Status
On Board Debug Support
+ Using the mikroProg
Creating Compatible NuttX HEX files
Tool Issues
Serial Console
+ SPI
LEDs
+ SSD1306 OLED
Configurations
Port Status
@@ -25,8 +28,20 @@ Port Status
2018-01-08: Created the basic board configuration for the Mikroe
Flip&Click PIC32MZ board. No testing has yet been performed. At this
point, I have not even figured out how I am going to load and debug
- new firmware. I need understand how the memory map is set up when used
- with the mikroBootloader.
+ new firmware.
+ 2018-02-08: I received a mikroProg PIC32 debugger (Thanks go to John Legg
+ of the Debug Shop!).
+ 2018-02-09: The NSH configuration is now functional, but only with the
+ RS-232 Click in mikroBUS slot B. There is, apparently, some mis-
+ information about how UART4 RX is connected in mikroBUS slot A; I
+ cannot receive serial there. But life is good in slot B.
+ 2018-02-10: Added the nxlines configuration to test the custom HiletGo
+ OLED on a Click proto board. Debug output indicates that the example is
+ running error free yet nothing appears on the OLED in mikroBUS slot A.
+ I tried slot D with same result. I also ported the configuration to
+ the Flip&Click SAM3X and got the same result. There could be SPI issues
+ on the PIC32MX, but more likely that there is an error in my custom
+ HiletGo Click. Damn!
On Board Debug Support
======================
@@ -46,7 +61,8 @@ On Board Debug Support
There is a simple application available at Mikroe that will allow you
to write .hex files via the USB HID bootloader. However, in order to
use the bootloader, you will have to control the memory map so that the
- downloaded code does not clobber the bootloader.
+ downloaded code does not clobber the bootloader code FLASH, data
+ memory, exception vectors, etc.
At this point, I have found no documentation describing how to build
the code outside of the Mikroe toolchain for use with the Mikroe
@@ -62,6 +78,66 @@ On Board Debug Support
would, most likely, clobber the USB HID bootloader (and possibly the
Arduino support as well).
+Using the mikroProg
+===================
+
+ WARNINGS:
+
+ 1. Following there steps will most certainly overwrite the bootloader
+ that was factory installed in FLASH!
+
+ 2. Due to the position and orientation of the mikroProg connector you
+ may lose functionality: If you attach mikroProg to the red side of
+ the board, you will not be able to use the Arduino Shield Connector
+ while the mikroProg connected. If you attach mikroProg to the white
+ side of the board, you will similarly lose access to mikroBUS
+ connectors A and D.
+
+ Hindsight is 20/20 and in retrospect I would look for a right handler
+ header to priven the mikroProg connector from interfering with the
+ Arduino connection.
+
+ Hardware setup
+ --------------
+
+ You will need to add a five pin header to the mikroProg connector between
+ the A and D mikroBUS sockets.
+
+ Connect the mikroProg to the outer 5 pins of the mikroProg's 10-pin
+ connector to the 5-pin header, respecting the pin 1 position: The
+ colored wire on the ribbon cable should be on the same side as the tiny
+ arrow on the board indicating pin 1.
+
+ Connect the mikroProg to your computer with the provided USB cable; also
+ power the Flip'n'Clip board with another USB cable connected to the
+ computer. Either USB port will provide power.
+
+ Installing the Software
+ -----------------------
+
+ From the mikroProg website https://www.mikroe.com/mikroprog-pic-dspic-pic32
+ Download:
+
+ Drivers for mikroProg Suite
+ https://download.mikroe.com/setups/drivers/mikroprog/pic-dspic-pic32/mikroprog-pic-dspic-pic32-drivers.zip
+
+ mikroProg Suite for PIC, dsPIC, PIC32 v260
+ https://download.mikroe.com/setups/programming-software/mikroprog/pic-dspic-pic32/mikroprog-suite-pic-dspic-pic32-programming-software-setup-v260.zip
+
+ Install the mikroProg Suite. From things I have read, I gather that you
+ must be Administrator when installing the tool The instructions say that
+ it will automatically install the drivers. It did not for me.
+
+ To install the drivers... You will find several directories under
+ mikroprog-pic-dspic-pic32-drivers/. Select the correct directory and run
+ the .EXE file you find there.
+
+ When I started the mikroProg suite, it could not find the USB driver.
+ After a few frustrating hours of struggling with the drivers, I found
+ that if I start the mikroProg suite as a normal user, it does not find
+ the driver. But if I instead start the mikroProg suite as Administrator...
+ There it is! A little awkward but works just fine.
+
Creating Compatible NuttX HEX files
===================================
@@ -90,7 +166,8 @@ Creating Compatible NuttX HEX files
cd tools/pic32mx
make
- Now you will have an excecutable file call mkpichex (or mkpichex.exe on
+ Now you will have an executable
+ file call mkpichex (or mkpichex.exe on
Cygwin). This program will take the nutt.hex file as an input, it will
convert all of the KSEG0 and KSEG1 addresses to physical address, and
it will write the modified file, replacing the original nuttx.hex.
@@ -100,7 +177,7 @@ Creating Compatible NuttX HEX files
export PATH=??? # Add the NuttX tools/pic32mx directory to your
# PATH variable
make # Build nuttx and nuttx.hex
- mkpichex $PWD # Convert addresses in nuttx.hex. $PWD is the path
+ mkpichex $PWD # Convert addresses in nuttx.hex. $PWD is the path
# to the top-level build directory. It is the only
# required input to mkpichex.
@@ -142,8 +219,49 @@ Serial Console
will leave that as an exercise for the interested reader.
The outputs from these pins is 3.3V. You will need to connect RS232
- transceiver to get the signals to RS232 levels (or connect to the
- USB virtual COM port in the case of UART0).
+ transceiver to get the signals to RS-232 levels. The simplest options are
+ an expensive Arduino RS-232 shield or a Mikroe RS-232 Click board.
+
+ STATUS: I have been unable to get the RS-232 Click to work in the mikroBUS
+ A slot. The PIC32MZ did not receive serial input. It appears that there
+ is an error in the some documentation: Either RG9 is not connected to
+ UART4_RX or the PPS bit definitions are documented incorrectly for UART4.
+
+ Switching to UART3 eliminates the problem and the serial console is fully
+ functional. I have not tried the other options of UART1, 2, or 5.
+
+SPI
+===
+
+ SPI3 is available on pins D10-D13 of the Arduino Shield connectors where
+ you would expect then. The SPI connector is configured as follows:
+
+ Pin J1 Board Signal PIC32MZ
+ --- -- ------------ -------
+ D10 8 SPI3_SCK RB14
+ D11 7 SPI3_MISO RB9
+ D12 6 SPI3_MOSI RB10
+ D13 5 SPI3_SS RB9
+
+ SPI1 and SPI2 are also available on the mikroBUS Click connectors (in
+ addition to 5V and GND). The connectivity between connectors A and B and
+ between C and D differs only in the chip select pin:
+
+ MikroBUS A: MikroBUS B:
+ Pin Board Signal PIC32MZ Pin Board Signal PIC32MZ
+ ---- ------------ ------- ---- ------------ -------
+ CS SPI2_SS1 RA0 CS SPI2_SS0 RE4
+ SCK SPI2_SCK RG6 SCK SPI2_SCK RG6
+ MISO SPI2_MISO RC4 MISO SPI2_MISO RC4
+ MOSI SPI2_MOSI RB5 MOSI SPI2_MOSI RB5
+
+ MikroBUS C: MikroBUS D:
+ Pin Board Signal PIC32MZ Pin Board Signal PIC32MZ
+ ---- ------------ ------- ---- ------------ -------
+ CS SPI1_SS0 RD12 CS SPI1_SS1 RD13
+ SCK SPI1_SCK RD1 SCK SPI1_SCK RD1
+ MISO SPI1_MISO RD2 MISO SPI1_MISO RD2
+ MOSI SPI1_MOSI RD3 MOSI SPI1_MOSI RD3
LEDs and Buttons
================
@@ -183,8 +301,8 @@ LEDs and Buttons
LED_PANIC The system has crashed 2Hz N/C N/C N/C N/C
LED_IDLE MCU is is sleep mode ---- Not used -----
- Thus if LED L is glowing on and all other LEDs are off (except LED D which
- was left on but is no longer controlled by NuttX and so may be in any
+ Thus if LED L is glowing faintly and all other LEDs are off (except LED D
+ which was left on but is no longer controlled by NuttX and so may be in any
state), NuttX has successfully booted and is, apparently, running normally
and taking interrupts. If any of LEDs A-D are statically set, then NuttX
failed to boot and the LED indicates the initialization phase where the
@@ -208,6 +326,27 @@ LEDs and Buttons
The switches have external pull-up resistors. The switches are pulled high
(+3.3V) and grounded when pressed.
+SSD1306 OLED
+============
+
+ Hardware
+ --------
+ The HiletGo is a 128x64 OLED that can be driven either via SPI or I2C (SPI
+ is the default and is what is used here). I have mounted the OLED on a
+ proto click board. The OLED is connected as follows:
+
+ OLED ALIAS DESCRIPTION PROTO CLICK
+ ----- ----------- ------------- -----------------
+ GND Ground GND
+ VCC Power Supply 5V (3-5V)
+ D0 SCL,CLK,SCK Clock SCK
+ D1 SDA,MOSI Data MOSI,SDI
+ RES RST,RESET Reset RST (GPIO OUTPUT)
+ DC AO Data/Command INT (GPIO OUTPUT)
+ CS Chip Select CS (GPIO OUTPUT)
+
+ NOTE that this is a write-only display (MOSI only)!
+
Configurations
==============
@@ -257,9 +396,9 @@ Where is one of the following:
NOTES:
- 1. Serial Console. UART 4 is configured as the Serial Console. This
+ 1. Serial Console. UART3 is configured as the Serial Console. This
assumes that you will be using a Mikroe RS-232 Click card in the
- mikroBUS A slot. Other serial consoles may be selected by re-
+ mikroBUS B slot. Other serial consoles may be selected by re-
configuring (see the section "Serial Consoles" above).
2. Toolchain
@@ -273,3 +412,28 @@ Where is one of the following:
CONFIG_PIC32MZ_DEBUGGER_ENABLE=n : Debugger is disabled
CONFIG_PIC32MZ_TRACE_ENABLE=n : Trace is disabled
CONFIG_PIC32MZ_JTAG_ENABLE=n : JTAG is disabled
+
+ nxlines
+
+ This is an NSH configuration that supports the NX graphics example at
+ apps/examples/nxlines as a built-in application.
+
+ NOTES:
+
+ 1. This configuration derives from the nsh configuration. All of the
+ notes there apply here as well.
+
+ 2. The default configuration assumes there is the custom HiletGo OLED
+ in the mikroBUS A slot (and a Mikroe RS-232 Click card in the
+ mikroBUS B slot). That is easily changed by reconfiguring, however.
+ See the section entitled "HiletGo OLED" for information about this
+ custom click card.
+
+ STATUS:
+
+ 2018-02-10: The debug output indicates that the nxlines example is
+ running with no errors, however, nothing appears on the OLED display.
+ I tried slot D with same result. I also ported the configuration to
+ the Flip&Click SAM3X and got the same result. There could be SPI issues
+ on the PIC32MX, but more likely that there is an error in my custom
+ HiletGo Click. Damn!
diff --git a/configs/flipnclick-pic32mz/include/board.h b/configs/flipnclick-pic32mz/include/board.h
index 490a8cde3fb6d9cc02630a7fb4d5d7ee14f6ff52..9fa460dd5d3e008af93a7d7c6858794aa2ff94cf 100644
--- a/configs/flipnclick-pic32mz/include/board.h
+++ b/configs/flipnclick-pic32mz/include/board.h
@@ -240,7 +240,7 @@
#define LED_PANIC 4 /* The system has crashed 2Hz N/C N/C N/C N/C */
#undef LED_IDLE /* MCU is is sleep mode ---- Not used ----- */
-/* Thus if LED L is glowing on and all other LEDs are off (except LED D which
+/* Thus if LED L is faintly glowing and all other LEDs are off (except LED D which
* was left on but is no longer controlled by NuttX and so may be in any state),
* NuttX has successfully booted and is, apparently, running normally and taking
* interrupts. If any of LEDs A-D are statically set, then NuttX failed to boot
@@ -303,6 +303,52 @@
#define BOARD_U5RX_PPS U5RXR_RPD14
#define BOARD_U5TX_PPS U5TX_RPD15R
+/* SPI **********************************************************************/
+/* SPI3 is available on pins D10-D13 of the Arduino Shield connectors where
+ * you would expect then. The SPI connector is configured as follows:
+ *
+ * Pin J1 Board Signal PIC32MZ
+ * --- -- ------------ -------
+ * D10 8 SPI3_SCK RB14
+ * D11 7 SPI3_MISO RB9
+ * D12 6 SPI3_MOSI RB10
+ * D13 5 SPI3_SS RB9
+ *
+ * SPI1 and SPI2 are also available on the mikroBUS Click connectors (in
+ * addition to 5V and GND). The connectivity between connectors A and B and
+ * between C and D differs only in the chip select pin:
+ *
+ * MikroBUS A: MikroBUS B:
+ * Pin Board Signal PIC32MZ Pin Board Signal PIC32MZ
+ * ---- ------------ ------- ---- ------------ -------
+ * CS SPI2_SS1 RA0 CS SPI2_SS0 RE4
+ * SCK SPI2_SCK RG6 SCK SPI2_SCK RG6
+ * MISO SPI2_MISO RC4 MISO SPI2_MISO RC4
+ * MOSI SPI2_MOSI RB5 MOSI SPI2_MOSI RB5
+ *
+ * MikroBUS C: MikroBUS D:
+ * Pin Board Signal PIC32MZ Pin Board Signal PIC32MZ
+ * ---- ------------ ------- ---- ------------ -------
+ * CS SPI1_SS0 RD12 CS SPI1_SS1 RD13
+ * SCK SPI1_SCK RD1 SCK SPI1_SCK RD1
+ * MISO SPI1_MISO RD2 MISO SPI1_MISO RD2
+ * MOSI SPI1_MOSI RD3 MOSI SPI1_MOSI RD3
+ *
+ * Chip select pin definitions are provided in
+ * configs/flipnclick-pic32mz/src/flipnclick-pic32mz.h.
+ *
+ * CLK (output) pins have no alternative pin configurations.
+ */
+
+#define BOARD_SDI1_PPS SDI1R_RPD2
+#define BOARD_SDO1_PPS SDO1_RPD3R
+
+#define BOARD_SDI2_PPS SDI2R_RPC4
+#define BOARD_SDO2_PPS SDO2_RPB5R
+
+#define BOARD_SDI3_PPS SDI3R_RPB9
+#define BOARD_SDO3_PPS SDO3_RPB9R
+
/****************************************************************************
* Public Types
****************************************************************************/
diff --git a/configs/flipnclick-pic32mz/nsh/defconfig b/configs/flipnclick-pic32mz/nsh/defconfig
index 93cfe3849c628a9988761ba8a67255c2525f8647..7087220d9fc84cf8bd28b81ed42adc9f2f8dc29e 100644
--- a/configs/flipnclick-pic32mz/nsh/defconfig
+++ b/configs/flipnclick-pic32mz/nsh/defconfig
@@ -1,6 +1,6 @@
# CONFIG_ARCH_RAMFUNCS is not set
-# CONFIG_NSH_DISABLE_IFCONFIG is not set
-# CONFIG_NSH_DISABLE_PS is not set
+# CONFIG_PIC32MZ_DEBUGGER_ENABLE is not set
+# CONFIG_PIC32MZ_TRACE_ENABLE is not set
CONFIG_ARCH_BOARD_FLIPNCLICK_PIC32MZ=y
CONFIG_ARCH_BOARD="flipnclick-pic32mz"
CONFIG_ARCH_CHIP_PIC32MZ=y
@@ -11,11 +11,11 @@ CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="mips"
CONFIG_BOARD_LOOPSPERMSEC=7245
CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
CONFIG_EXAMPLES_NSH=y
CONFIG_FAT_LCNAMES=y
CONFIG_FAT_LFN=y
CONFIG_FS_FAT=y
+CONFIG_FS_PROCFS=y
CONFIG_HOST_WINDOWS=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_INTELHEX_BINARY=y
@@ -29,11 +29,12 @@ CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_DISABLE_IFUPDOWN=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_PIC32MZ_ICESEL_CH2=y
-CONFIG_PIC32MZ_UART4=y
+CONFIG_PIC32MZ_UART3=y
CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=8
@@ -45,7 +46,6 @@ CONFIG_SDCLONE_DISABLE=y
CONFIG_START_DAY=7
CONFIG_START_MONTH=3
CONFIG_START_YEAR=2012
-CONFIG_TASK_NAME_SIZE=0
-CONFIG_UART4_SERIAL_CONSOLE=y
+CONFIG_UART3_SERIAL_CONSOLE=y
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WDOG_INTRESERVE=1
diff --git a/configs/flipnclick-pic32mz/nxlines/defconfig b/configs/flipnclick-pic32mz/nxlines/defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..bf09c0b9ac4d99ce1b0791b02c0d568099ca2361
--- /dev/null
+++ b/configs/flipnclick-pic32mz/nxlines/defconfig
@@ -0,0 +1,62 @@
+# CONFIG_ARCH_RAMFUNCS is not set
+# CONFIG_NX_DISABLE_1BPP is not set
+# CONFIG_PIC32MZ_DEBUGGER_ENABLE is not set
+# CONFIG_PIC32MZ_TRACE_ENABLE is not set
+CONFIG_ARCH_BOARD_FLIPNCLICK_PIC32MZ=y
+CONFIG_ARCH_BOARD="flipnclick-pic32mz"
+CONFIG_ARCH_CHIP_PIC32MZ=y
+CONFIG_ARCH_CHIP_PIC32MZ2048EFH=y
+CONFIG_ARCH_CHIP_PIC32MZEF=y
+CONFIG_ARCH_MIPS=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH="mips"
+CONFIG_BOARD_LOOPSPERMSEC=7245
+CONFIG_BUILTIN=y
+CONFIG_EXAMPLES_NSH=y
+CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=4
+CONFIG_EXAMPLES_NXLINES_BPP=1
+CONFIG_EXAMPLES_NXLINES_LINEWIDTH=4
+CONFIG_EXAMPLES_NXLINES=y
+CONFIG_FLIPNCLICK_PIC32MZ_SSD1306=y
+CONFIG_FS_PROCFS=y
+CONFIG_HOST_WINDOWS=y
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LCD_HILETGO=y
+CONFIG_LCD_MAXCONTRAST=255
+CONFIG_LCD=y
+CONFIG_MAX_TASKS=16
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_MIPS_MICROMIPS=y
+CONFIG_MIPS32_TOOLCHAIN_PINGUINOW=y
+CONFIG_MMCSD=y
+CONFIG_MQ_MAXMSGSIZE=64
+CONFIG_MTD=y
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_NX_BLOCKING=y
+CONFIG_NX=y
+CONFIG_NXFONT_TOM_THUMB_4X6=y
+CONFIG_NXTK_BORDERWIDTH=2
+CONFIG_PIC32MZ_ICESEL_CH2=y
+CONFIG_PIC32MZ_SPI2=y
+CONFIG_PIC32MZ_UART3=y
+CONFIG_PREALLOC_MQ_MSGS=8
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_PREALLOC_WDOGS=8
+CONFIG_RAM_SIZE=131072
+CONFIG_RAM_START=0xa0000000
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_START_DAY=10
+CONFIG_START_MONTH=2
+CONFIG_UART3_SERIAL_CONSOLE=y
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_WDOG_INTRESERVE=1
diff --git a/configs/flipnclick-pic32mz/src/Makefile b/configs/flipnclick-pic32mz/src/Makefile
index c8226dc95ef47b0b714eed37113e81ecea41b12e..529b5c926ce8d2bb9bbd15c6ae743368bcd66c13 100644
--- a/configs/flipnclick-pic32mz/src/Makefile
+++ b/configs/flipnclick-pic32mz/src/Makefile
@@ -1,7 +1,7 @@
############################################################################
# configs/flipnclick-pic32mz/src/Makefile
#
-# Copyright (C) 2015 Gregory Nutt. All rights reserved.
+# Copyright (C) 2018 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt
#
# Redistribution and use in source and binary forms, with or without
@@ -50,4 +50,8 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y)
CSRCS += pic32mz_buttons.c
endif
+ifeq ($(CONFIG_FLIPNCLICK_PIC32MZ_SSD1306),y)
+CSRCS += pic32mz_ssd1306.c
+endif
+
include $(TOPDIR)/configs/Board.mk
diff --git a/configs/flipnclick-pic32mz/src/flipnclick-pic32mz.h b/configs/flipnclick-pic32mz/src/flipnclick-pic32mz.h
index a1cbc0a8ebc6a19dc6a2421fda7897b1ba9d8e0f..f349e69f63f3b918f3613a49dd1c90053fcafbe5 100644
--- a/configs/flipnclick-pic32mz/src/flipnclick-pic32mz.h
+++ b/configs/flipnclick-pic32mz/src/flipnclick-pic32mz.h
@@ -48,6 +48,22 @@
****************************************************************************/
/* Configuration ************************************************************/
+#define HAVE_SSD1306 1
+
+/* The SSD1306 LCD must be selected, installed on the Flip&Click, and must
+ * be configured to use the SPI interface.
+ */
+
+#if !defined(CONFIG_FLIPNCLICK_PIC32MZ_SSD1306) || \
+ !defined(CONFIG_LCD_SSD1306_SPI)
+# undef HAVE_SSD1306
+# undef CONFIG_FLIPNCLICK_PIC32MZ_SSD1306
+# undef CONFIG_FLIPNCLICK_PIC32MZ_SSD1306_MBA
+# undef CONFIG_FLIPNCLICK_PIC32MZ_SSD1306_MBB
+# undef CONFIG_FLIPNCLICK_PIC32MZ_SSD1306_MBC
+# undef CONFIG_FLIPNCLICK_PIC32MZ_SSD1306_MBD
+#endif
+
/* LEDs *********************************************************************/
/* There are four LEDs on the top, red side of the board. Only one can be
* controlled by software:
@@ -85,6 +101,119 @@
#define GPIO_T1 (GPIO_INPUT | GPIO_INTERRUPT | GPIO_PORTD | GPIO_PIN10)
#define GPIO_T2 (GPIO_INPUT | GPIO_INTERRUPT | GPIO_PORTD | GPIO_PIN11)
+/* SPI Chip Selects
+ *
+ * SPI3 is available on pins D10-D13 of the Arduino Shield connectors where
+ * you would expect then. The SPI connector is configured as follows:
+ *
+ * Pin J1 Board Signal PIC32MZ
+ * --- -- ------------ -------
+ * D10 8 SPI3_SCK RB14
+ * D10 7 SPI3_MISO RB9
+ * D11 6 SPI3_MOSI RB10
+ * D13 5 SPI3_SS RB9
+ */
+
+#define GPIO_ARD_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORTB | GPIO_PIN14)
+
+/* SPI1 and SPI2 are also available on the mikroBUS Click connectors (in
+ * addition to 5V and GND). The connectivity between connectors A and B and
+ * between C and D differs only in the chip select pin:
+ *
+ * MikroBUS A: MikroBUS B:
+ * Pin Board Signal PIC32MZ Pin Board Signal PIC32MZ
+ * ---- ------------ ------- ---- ------------ -------
+ * CS SPI2_SS1 RA0 CS SPI2_SS0 RE4
+ * SCK SPI2_SCK RG6 SCK SPI2_SCK RG6
+ * MISO SPI2_MISO RC4 MISO SPI2_MISO RC4
+ * MOSI SPI2_MOSI RB5 MOSI SPI2_MOSI RB5
+ *
+ * MikroBUS C: MikroBUS D:
+ * Pin Board Signal PIC32MZ Pin Board Signal PIC32MZ
+ * ---- ------------ ------- ---- ------------ -------
+ * CS SPI1_SS0 RD12 CS SPI1_SS1 RD13
+ * SCK SPI1_SCK RD1 SCK SPI1_SCK RD1
+ * MISO SPI1_MISO RD2 MISO SPI1_MISO RD2
+ * MOSI SPI1_MOSI RD3 MOSI SPI1_MOSI RD3
+ */
+
+#define GPIO_MBA_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORTA | GPIO_PIN0)
+#define GPIO_MBB_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORTE | GPIO_PIN4)
+#define GPIO_MBC_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORTD | GPIO_PIN12)
+#define GPIO_MBD_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORTD | GPIO_PIN13)
+
+/* SSD1306 OLED
+ *
+ * The HiletGo is a 128x64 OLED that can be driven either via SPI or I2C (SPI
+ * is the default and is what is used here). I have mounted the OLED on a
+ * proto click board. The OLED is connected as follows:
+ *
+ * OLED ALIAS DESCRIPTION PROTO CLICK
+ * ----- ----------- ------------- -----------------
+ * GND Ground GND
+ * VCC Power Supply 5V (3-5V)
+ * D0 SCL,CLK,SCK Clock SCK
+ * D1 SDA,MOSI Data MOSI,SDI
+ * RES RST,RESET Reset RST (GPIO OUTPUT)
+ * DC AO Data/Command INT (GPIO OUTPUT)
+ * CS Chip Select CS (GPIO OUTPUT)
+ *
+ * NOTE that this is a write-only display (MOSI only)!
+ *
+ * MikroBUS A: MikroBUS B:
+ * Pin Board Signal PIC32MZ Pin Board Signal PIC32MZ
+ * ---- ------------ ------- ---- ------------ -------
+ * RST RST4 RE2 RST RST3 RG13
+ * DC INT4 RD9 DC INT3 RG1
+ *
+ * MikroBUS C: MikroBUS D:
+ * Pin Board Signal PIC32MZ Pin Board Signal PIC32MZ
+ * ---- ------------ ------- ---- ------------ -------
+ * RST RST1 RG14 RST RST2 RG12
+ * DC INT1 RD5 DC INT2 RD4
+ */
+
+#if defined(CONFIG_FLIPNCLICK_PIC32MZ_SSD1306_MBA)
+# ifndef CONFIG_PIC32MZ_SPI2
+# error "The OLED driver requires CONFIG_PIC32MZ_SPI2 in the configuration"
+# endif
+
+# define SSD1306_SPI_BUS 2
+# define GPIO_SSD1306_CS GPIO_MBA_CS
+# define GPIO_SSD1306_RST (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTE | GPIO_PIN2)
+# define GPIO_SSD1306_DC (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTD | GPIO_PIN9)
+
+#elif defined(CONFIG_FLIPNCLICK_PIC32MZ_SSD1306_MBB)
+# ifndef CONFIG_PIC32MZ_SPI2
+# error "The OLED driver requires CONFIG_PIC32MZ_SPI2 in the configuration"
+# endif
+
+# define SSD1306_SPI_BUS 2
+# define GPIO_SSD1306_CS GPIO_MBB_CS
+# define GPIO_SSD1306_RST (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTG | GPIO_PIN13)
+# define GPIO_SSD1306_DC (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTG | GPIO_PIN1)
+
+#elif defined(CONFIG_FLIPNCLICK_PIC32MZ_SSD1306_MBC)
+# ifndef CONFIG_PIC32MZ_SPI1
+# error "The OLED driver requires CONFIG_PIC32MZ_SPI1 in the configuration"
+# endif
+
+# define SSD1306_SPI_BUS 1
+# define GPIO_SSD1306_CS GPIO_MBC_CS
+# define GPIO_SSD1306_RST (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTG | GPIO_PIN14)
+# define GPIO_SSD1306_DC (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTD | GPIO_PIN5)
+
+#elif defined(CONFIG_FLIPNCLICK_PIC32MZ_SSD1306_MBD)
+# ifndef CONFIG_PIC32MZ_SPI1
+# error "The OLED driver requires CONFIG_PIC32MZ_SPI1 in the configuration"
+# endif
+
+# define SSD1306_SPI_BUS 1
+# define GPIO_SSD1306_CS GPIO_MBD_CS
+# define GPIO_SSD1306_RST (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTG | GPIO_PIN12)
+# define GPIO_SSD1306_DC (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTD | GPIO_PIN4)
+#endif
+
/****************************************************************************
* Public Types
****************************************************************************/
@@ -141,6 +270,21 @@ void pic32mz_led_initialize(void);
int pic32mz_bringup(void);
+/****************************************************************************
+ * Name: pic32mz_graphics_setup
+ *
+ * Description:
+ * Called by either NX initialization logic (via board_graphics_setup) or
+ * directly from the board bring-up logic in order to configure the
+ * SSD1306 OLED.
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_SSD1306
+struct lcd_dev_s; /* Forward reference */
+FAR struct lcd_dev_s *pic32mz_graphics_setup(unsigned int devno);
+#endif
+
#undef EXTERN
#ifdef __cplusplus
}
diff --git a/configs/flipnclick-pic32mz/src/pic32mz_autoleds.c b/configs/flipnclick-pic32mz/src/pic32mz_autoleds.c
index 01d05ea00d07159628af4bdce10c0a6625642ced..fc229ea532ec5d83ca10f12f2d631586fe58d96d 100644
--- a/configs/flipnclick-pic32mz/src/pic32mz_autoleds.c
+++ b/configs/flipnclick-pic32mz/src/pic32mz_autoleds.c
@@ -57,6 +57,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* There are four LEDs on the top, red side of the board. Only one can be
* controlled by software:
*
@@ -89,8 +90,8 @@
* LED_PANIC The system has crashed 2Hz N/C N/C N/C N/C
* LED_IDLE MCU is is sleep mode ---- Not used -----
*
- * Thus if LED L is glowing on and all other LEDs are off (except LED D
- * which was left on but is no longer controlled by NuttX and so may be in
+ * Thus if LED L is faintly glowing and all other LEDs are off (except LED
+ * D which was left on but is no longer controlled by NuttX and so may be in
* any state), NuttX has successfully booted and is, apparently, running
* normally and taking interrupts. If any of LEDs A-D are statically set,
* then NuttX failed to boot and the LED indicates the initialization phase
@@ -122,7 +123,7 @@ static void board_autoled_setone(int ledndx)
pic32mz_gpiowrite(GPIO_LED_L, ledon[INDEX_LED_L]);
pic32mz_gpiowrite(GPIO_LED_A, ledon[INDEX_LED_A]);
pic32mz_gpiowrite(GPIO_LED_B, ledon[INDEX_LED_B]);
- pic32mz_gpiowrite(GPIO_LED_C, ledon[INDEX_LED_D]);
+ pic32mz_gpiowrite(GPIO_LED_C, ledon[INDEX_LED_C]);
pic32mz_gpiowrite(GPIO_LED_D, ledon[INDEX_LED_D]);
}
@@ -175,7 +176,7 @@ void board_autoled_on(int led)
board_autoled_setone(INDEX_LED_B);
break;
- case 2:
+ case 2:
board_autoled_setone(INDEX_LED_C);
break;
diff --git a/configs/flipnclick-pic32mz/src/pic32mz_bringup.c b/configs/flipnclick-pic32mz/src/pic32mz_bringup.c
index 3ce4337fe40b44b7687b6e5cafc3f763b08311ee..c24c4cc9ea09deac2d08c3897c03a907d2210b7d 100644
--- a/configs/flipnclick-pic32mz/src/pic32mz_bringup.c
+++ b/configs/flipnclick-pic32mz/src/pic32mz_bringup.c
@@ -40,6 +40,8 @@
#include
#include
+#include
+#include
#include "flipnclick-pic32mz.h"
@@ -59,6 +61,26 @@ int pic32mz_bringup(void)
{
int ret;
+#ifdef CONFIG_FS_PROCFS
+ /* Mount the procfs file system */
+
+ ret = mount(NULL, "/proc", "procfs", 0, NULL);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR,"ERROR: Failed to mount procfs at /proc: %d\n",
+ ret);
+ }
+#endif
+
+#if defined(HAVE_SSD1306) && !defined(CONFIG_NXSTART_EXTERNINIT)
+ /* Configure the SSD1306 OLED */
+
+ if (pic32mz_graphics_setup(0) == NULL)
+ {
+ syslog(LOG_ERR,"ERROR: Failed to configure the SSD1306 OLED\n");
+ }
+#endif
+
UNUSED(ret);
return OK;
}
diff --git a/configs/flipnclick-pic32mz/src/pic32mz_spi.c b/configs/flipnclick-pic32mz/src/pic32mz_spi.c
index c1387b8054f66efe784516cc7ba8d0e8f65ab772..5817945842e62de6a8873c0330ee51aec4959bed 100644
--- a/configs/flipnclick-pic32mz/src/pic32mz_spi.c
+++ b/configs/flipnclick-pic32mz/src/pic32mz_spi.c
@@ -43,9 +43,12 @@
#include
#include
+#include
+
#include
#include "up_arch.h"
+#include "pic32mz-gpio.h"
#include "flipnclick-pic32mz.h"
@@ -65,9 +68,12 @@
void weak_function pic32mz_spidev_initialize(void)
{
- /* Configure the SPI chip select GPIOs */
+#ifdef HAVE_SSD1306
+ /* Configure the SSD1306 chip select and command/data GPIOs */
-#warning "Missing logic"
+ (void)pic32mz_configgpio(GPIO_SSD1306_CS);
+ (void)pic32mz_configgpio(GPIO_SSD1306_DC);
+#endif
}
/************************************************************************************
@@ -104,95 +110,130 @@ struct spi_dev_s;
void pic32mz_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
{
spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
-#warning "Missing logic"
+
+#if defined(CONFIG_FLIPNCLICK_PIC32MZ_SSD1306_MBC) || \
+ defined(CONFIG_FLIPNCLICK_PIC32MZ_SSD1306_MBD)
+ if (devid == SPIDEV_DISPLAY(0))
+ {
+ /* Low: the display is selected
+ * High: the display is deselected
+ */
+
+ pic32mz_gpiowrite(GPIO_SSD1306_CS, !selected);
+ }
+#endif
}
uint8_t pic32mz_spi1status(FAR struct spi_dev_s *dev, uint32_t devid)
{
spiinfo("Returning nothing\n");
-#warning "Missing logic"
return 0;
}
#ifdef CONFIG_SPI_CMDDATA
int pic32mz_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
-#warning "Missing logic"
+#if defined(CONFIG_FLIPNCLICK_PIC32MZ_SSD1306_MBC) || \
+ defined(CONFIG_FLIPNCLICK_PIC32MZ_SSD1306_MBD)
+ if (devid == SPIDEV_DISPLAY(0))
+ {
+ /* High: the inputs are treated as display data.
+ * Low: the inputs are transferred to the command registers.
+ */
+
+ pic32mz_gpiowrite(GPIO_SSD1306_DC, !cmd);
+ }
+#endif
+
return 0;
}
#endif
-#endif
+#endif /* CONFIG_PIC32MZ_SPI1 */
#ifdef CONFIG_PIC32MZ_SPI2
void pic32mz_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
{
spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
-#warning "Missing logic"
+
+#if defined(CONFIG_FLIPNCLICK_PIC32MZ_SSD1306_MBA) || \
+ defined(CONFIG_FLIPNCLICK_PIC32MZ_SSD1306_MBB)
+ if (devid == SPIDEV_DISPLAY(0))
+ {
+ /* Low: the display is selected
+ * High: the display is deselected
+ */
+
+ pic32mz_gpiowrite(GPIO_SSD1306_CS, !selected);
+ }
+#endif
}
uint8_t pic32mz_spi2status(FAR struct spi_dev_s *dev, uint32_t devid)
{
spiinfo("Returning nothing\n");
-#warning "Missing logic"
return 0;
}
#ifdef CONFIG_SPI_CMDDATA
int pic32mz_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
-#warning "Missing logic"
+#if defined(CONFIG_FLIPNCLICK_PIC32MZ_SSD1306_MBA) || \
+ defined(CONFIG_FLIPNCLICK_PIC32MZ_SSD1306_MBB)
+ if (devid == SPIDEV_DISPLAY(0))
+ {
+ /* High: the inputs are treated as display data.
+ * Low: the inputs are transferred to the command registers.
+ */
+
+ pic32mz_gpiowrite(GPIO_SSD1306_DC, !cmd);
+ }
+#endif
+
return 0;
}
#endif
-#endif
+#endif /* CONFIG_PIC32MZ_SPI2 */
#ifdef CONFIG_PIC32MZ_SPI3
void pic32mz_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
{
spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
-#warning "Missing logic"
}
uint8_t pic32mz_spi3status(FAR struct spi_dev_s *dev, uint32_t devid)
{
spiinfo("Returning nothing\n");
-#warning "Missing logic"
return 0;
}
#ifdef CONFIG_SPI_CMDDATA
int pic32mz_spi3cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
-#warning "Missing logic"
return 0;
}
#endif
-#endif
+#endif /* CONFIG_PIC32MZ_SPI3 */
#ifdef CONFIG_PIC32MZ_SPI4
void pic32mz_spi4select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
{
spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
-#warning "Missing logic"
}
uint8_t pic32mz_spi4status(FAR struct spi_dev_s *dev, uint32_t devid)
{
spiinfo("Returning nothing\n");
-#warning "Missing logic"
return 0;
}
#ifdef CONFIG_SPI_CMDDATA
int pic32mz_spi4cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
-#warning "Missing logic"
return 0;
}
#endif
-#endif
+#endif /* CONFIG_PIC32MZ_SPI4 */
#ifdef CONFIG_PIC32MZ_SPI5
void pic32mz_spi5select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
{
spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
-#warning "Missing logic"
}
uint8_t pic32mz_spi5status(FAR struct spi_dev_s *dev, uint32_t devid)
@@ -208,7 +249,7 @@ int pic32mz_spi5cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
return 0;
}
#endif
-#endif
+#endif /* CONFIG_PIC32MZ_SPI5 */
#ifdef CONFIG_PIC32MZ_SPI6
void pic32mz_spi6select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
@@ -230,6 +271,82 @@ int pic32mz_spi6cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
return 0;
}
#endif
-#endif
+#endif /* CONFIG_PIC32MZ_SPI6 */
+
+/****************************************************************************
+ * Name: pic32mz_spi1/2/...register
+ *
+ * Description:
+ * If the board supports a card detect callback to inform the SPI-based
+ * MMC/SD driver when an SD card is inserted or removed, then
+ * CONFIG_SPI_CALLBACK should be defined and the following function(s)
+ * must be implemented. These functions implements the registercallback
+ * method of the SPI interface (see include/nuttx/spi/spi.h for details)
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * callback - The function to call on the media change
+ * arg - A caller provided value to return with the callback
+ *
+ * Returned Value:
+ * 0 on success; negated errno on failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_CALLBACK
+#ifdef CONFIG_PIC32MZ_SPI1
+int pic32mz_spi1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
+ FAR void *arg)
+{
+#warning Missing logic
+ return -ENOSYS;
+}
+#endif /* CONFIG_PIC32MZ_SPI1 */
+
+#ifdef CONFIG_PIC32MZ_SPI2
+int pic32mz_spi2register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
+ FAR void *arg)
+{
+#warning Missing logic
+ return -ENOSYS;
+}
+#endif /* CONFIG_PIC32MZ_SPI2 */
+
+#ifdef CONFIG_PIC32MZ_SPI3
+int pic32mz_spi3register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
+ FAR void *arg)
+{
+#warning Missing logic
+ return -ENOSYS;
+}
+#endif /* CONFIG_PIC32MZ_SPI3 */
+
+#ifdef CONFIG_PIC32MZ_SPI4
+int pic32mz_spi4register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
+ FAR void *arg)
+{
+#warning Missing logic
+ return -ENOSYS;
+}
+#endif /* CONFIG_PIC32MZ_SPI4 */
+
+#ifdef CONFIG_PIC32MZ_SPI5
+int pic32mz_spi5register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
+ FAR void *arg)
+{
+#warning Missing logic
+ return -ENOSYS;
+}
+#endif /* CONFIG_PIC32MZ_SPI5 */
+
+#ifdef CONFIG_PIC32MZ_SPI6
+int pic32mz_spi6register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
+ FAR void *arg)
+{
+#warning Missing logic
+ return -ENOSYS;
+}
+#endif /* CONFIG_PIC32MZ_SPI6 */
+#endif /* CONFIG_SPI_CALLBACK */
#endif /* CONFIG_PIC32MZ_SPI */
diff --git a/configs/flipnclick-pic32mz/src/pic32mz_ssd1306.c b/configs/flipnclick-pic32mz/src/pic32mz_ssd1306.c
new file mode 100644
index 0000000000000000000000000000000000000000..47e4b29b6f4970454e89bcf1e14c4d24aaa83efd
--- /dev/null
+++ b/configs/flipnclick-pic32mz/src/pic32mz_ssd1306.c
@@ -0,0 +1,172 @@
+/****************************************************************************
+ * config/flipnclick-pic32mz/src/pic32mz_ssd1306.c
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* SSD1306 OLED
+ *
+ * The HiletGo is a 128x64 OLED that can be driven either via SPI or I2C (SPI
+ * is the default and is what is used here). I have mounted the OLED on a
+ * proto click board. The OLED is connected as follows:
+ *
+ * OLED ALIAS DESCRIPTION PROTO CLICK
+ * ----- ----------- ------------- -----------------
+ * GND Ground GND
+ * VCC Power Supply 5V (3-5V)
+ * D0 SCL,CLK,SCK Clock SCK
+ * D1 SDA,MOSI Data MOSI,SDI
+ * RES RST,RESET Reset RST (GPIO OUTPUT)
+ * DC AO Data/Command INT (GPIO OUTPUT)
+ * CS Chip Select CS (GPIO OUTPUT)
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+
+#include
+#include
+#include
+#include
+
+#if defined(CONFIG_VIDEO_FB) && defined(CONFIG_LCD_FRAMEBUFFER)
+# include
+#endif
+
+#include "pic32mz-gpio.h"
+#include "pic32mz-spi.h"
+
+#include "flipnclick-pic32mz.h"
+
+#ifdef HAVE_SSD1306
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* Configuration ************************************************************/
+
+#ifndef CONFIG_SPI_CMDDATA
+# error "The OLED driver requires CONFIG_SPI_CMDDATA in the configuration"
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: pic32mz_graphics_setup
+ *
+ * Description:
+ * Called by either NX initialization logic (via board_graphics_setup) or
+ * directly from the board bring-up logic in order to configure the
+ * SSD1306 OLED.
+ *
+ ****************************************************************************/
+
+FAR struct lcd_dev_s *pic32mz_graphics_setup(unsigned int devno)
+{
+ FAR struct spi_dev_s *spi;
+ FAR struct lcd_dev_s *dev;
+
+ /* Configure the OLED GPIOs. This initial configuration is RESET low,
+ * putting the OLED into reset state.
+ */
+
+ (void)pic32mz_configgpio(GPIO_SSD1306_RST);
+
+ /* Wait a bit then release the OLED from the reset state */
+
+ up_mdelay(20);
+ pic32mz_gpiowrite(GPIO_SSD1306_RST, true);
+
+ /* Get the SPI1 port interface */
+
+ spi = pic32mz_spibus_initialize(SSD1306_SPI_BUS);
+ if (!spi)
+ {
+ lcderr("ERROR: Failed to initialize SPI port 1\n");
+ }
+ else
+ {
+ /* Bind the SPI port to the OLED */
+
+ dev = ssd1306_initialize(spi, NULL, devno);
+ if (!dev)
+ {
+ lcderr("ERROR: Failed to bind SPI port 1 to OLED %d: %d\n", devno);
+ }
+ else
+ {
+ lcdinfo("Bound SPI port 1 to OLED %d\n", devno);
+
+ /* And turn the OLED on */
+
+ (void)dev->setpower(dev, CONFIG_LCD_MAXPOWER);
+
+#if defined(CONFIG_VIDEO_FB) && defined(CONFIG_LCD_FRAMEBUFFER)
+ /* Initialize and register the simulated framebuffer driver */
+
+ ret = fb_register(0, 0);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret);
+ }
+#endif
+
+ return dev;
+ }
+ }
+
+ return NULL;
+}
+
+/****************************************************************************
+ * Name: board_graphics_setup
+ *
+ * Description:
+ * Called by NX initialization logic to configure the OLED.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NXSTART_EXTERNINIT
+FAR struct lcd_dev_s *board_graphics_setup(unsigned int devno)
+{
+ return pic32mz_graphics_setup(devno);
+}
+#endif
+
+#endif /* HAVE_SSD1306 */
diff --git a/configs/flipnclick-sam3x/Kconfig b/configs/flipnclick-sam3x/Kconfig
index 166b712c2a9d0ca41732341b3702f528896af141..07f939ec79bf177a261ad5520986668da139bdb8 100644
--- a/configs/flipnclick-sam3x/Kconfig
+++ b/configs/flipnclick-sam3x/Kconfig
@@ -4,4 +4,30 @@
#
if ARCH_BOARD_FLIPNCLICK_SAM3X
+
+config FLIPNCLICK_SAM3X_SSD1306
+ bool "SSD1306 Click Present"
+ default n
+ depends on LCD_SSD1306
+ select NXSTART_EXTERNINIT if NX
+
+choice
+ prompt "SSD1306 mikroBUS"
+ default FLIPNCLICK_SAM3X_SSD1306_MBA
+ depends on FLIPNCLICK_SAM3X_SSD1306
+
+config FLIPNCLICK_SAM3X_SSD1306_MBA
+ bool "mikroBUS A"
+
+config FLIPNCLICK_SAM3X_SSD1306_MBB
+ bool "mikroBUS B"
+
+config FLIPNCLICK_SAM3X_SSD1306_MBC
+ bool "mikroBUS C"
+
+config FLIPNCLICK_SAM3X_SSD1306_MBD
+ bool "mikroBUS D"
+
+endchoice # SSD1306 mikroBUS
+
endif
diff --git a/configs/flipnclick-sam3x/README.txt b/configs/flipnclick-sam3x/README.txt
index 38c319414f6c9229c69b7f4e343ec884916dee85..c4d154ae4587443f1acf6aa221898499f73ef996 100644
--- a/configs/flipnclick-sam3x/README.txt
+++ b/configs/flipnclick-sam3x/README.txt
@@ -14,6 +14,9 @@ Contents
- STATUS
- Buttons and LEDs
- Serial Consoles
+ - SPI
+ - I2C
+ - SSD1306 OLED
- Loading Code
- Flip&Click SAM3X-specific Configuration Options
- Configurations
@@ -22,23 +25,16 @@ STATUS
======
2018-01-07: Created the configuration. At present it does not work; I
- believe because of tool-related issues. I do the following:
-
- a) Open TeraTerm, select COM7 at 1200 baud, type a few ENTERs, and
- close teraterm.
-
- b) Execute the following command which claims to have successfully
- written to FLASH.
-
- bossac.exe --info --debug --port COM7 --usb-port=0 --erase --write --verify -b nuttx.bin -R
-
- But the code does not boot. There is no indication of life.
-
- c) Repeat a) then
-
- bossac.exe --info --debug --port COM7 --usb-port=0 --verify -b nuttx.bin
-
- And it says that the content of the FLASH is not good.
+ believe because of tool-related issues. See discussion under "Loading
+ Code" below.
+ 2018-01-24: I ordered a JTAG connector and soldered that to the Flip'n'Click
+ and I am now successfully able to load code. The NSH configuration appears
+ to be fully functional.
+ 2018-02-11: Added the nxlines configuration to test the custom HiletGo
+ OLED on a Click proto board. This is the same logic from the Flip&Click
+ PIC32MZ and the result is the same: No complaints from the software, but
+ nothing appears on the OLED. There is, most likely, an error in my custom
+ HiletGo Click. Damn!
Buttons and LEDs
================
@@ -81,8 +77,8 @@ Buttons and LEDs
LED_PANIC The system has crashed 2Hz N/C N/C N/C N/C
LED_IDLE MCU is is sleep mode ---- Not used -----
- Thus if LED L is glowing on and all other LEDs are off (except LED D which
- was left on but is no longer controlled by NuttX and so may be in any
+ Thus if LED L is glowing faintly and all other LEDs are off (except LED D
+ which was left on but is no longer controlled by NuttX and so may be in any
state), NuttX has successfully booted and is, apparently, running normally
and taking interrupts. If any of LEDs A-D are statically set, then NuttX
failed to boot and the LED indicates the initialization phase where the
@@ -99,10 +95,11 @@ Serial Consoles
serial chip connected to the first of the MCU (RX0 and TX0 on PA8 and PA9,
respectively). The output from that port is visible using the Arduino tool.
- Any of UART and USART0-3 may be used as a serial console. By default,
- UART0 is used as the serial console in all configurations. But that is
- easily changed by modifying the configuration as described under
- "Configurations" below.
+ [NOTE: My experience so far: I get serial output on the virtual COM port
+ via the UART, but I receive no serial input for keyboard data entered in
+ the PC serial terminal. I have not investigated this problem. It may
+ be something as simple as the Rx pin configuration. Instead, I just
+ switched to USART0.]
Other convenient U[S]ARTs that may be used as the Serial console include:
@@ -125,9 +122,103 @@ Serial Consoles
transceiver to get the signals to RS232 levels (or connect to the
USB virtual COM port in the case of UART0).
+ Any of UART and USART0-3 may be used as a serial console. UART0 would
+ be the preferred default console setting. However, due to the communication
+ problems mentioned above, USART0 is used as the default serial console
+ in all configurations. But that is easily changed by modifying the
+ configuration as described under "Configurations" below.
+
+SPI
+===
+
+ SPI0 is available on the Arduino compatible SPI connector (but no SPI is
+ available on pins D10-D13 of the main Arduino Shield connectors where
+ you might expect then). The SPI connector is configured as follows:
+
+ Pin Board Signal SAM3X Pin Board Signal SAM3X
+ --- ------------ ----- --- ------------ -----
+ 1 SPI0_MISO PA25 2 VCC-5V N/A
+ 3 SPI0_SCK PA27 4 SPI0_MOSI PA26
+ 5 MRST NRSTB 6 GND N/A
+
+ SPI0 is also available on each of the mikroBUS Click connectors (in
+ addition to 5V and GND). The connectivity differs only in the chip
+ select pin:
+
+ MikroBUS A: MikroBUS B:
+ Pin Board Signal SAM3X Pin Board Signal SAM3X
+ ---- ------------ ----- ---- ------------ -----
+ CS SPI0_CS0 PA28 CS PA29 PA29
+ SCK SPI0_SCK PA27 SCK SPI0_SCK PA27
+ MISO SPI0_MISO PA25 MISO SPI0_MISO PA25
+ MOSI SPI0_MOSI PA26 MOSI SPI0_MOSI PA26
+
+ MikroBUS C: MikroBUS D:
+ Pin Board Signal SAM3X Pin Board Signal SAM3X
+ ---- ------------ ----- ---- ------------ -----
+ CS SPI0_CS2 PB21 CS SPI0_CS3 PB23
+ SCK SPI0_SCK PA27 SCK SPI0_SCK PA27
+ MISO SPI0_MISO PA25 MISO SPI0_MISO PA25
+ MOSI SPI0_MOSI PA26 MOSI SPI0_MOSI PA26
+
+I2C
+===
+
+ I2C0 is available on pins D16-D17 of the Arduino Shield connectors where
+ you would expect then. The SPI connector is configured as follows:
+
+ Pin Label J1 Board Signal SAM3X
+ --- ----- -- ------------ -----
+ D16 SCL1 8 I2C0_SCL PA17
+ D17 SDA1 7 I2C0_SDA PA18
+
+ I2C0 and I2C1 are also available on the mikroBUS Click connectors (in
+ addition to 5V and GND). The connectors A and B share I2C0 with the
+ Arduino shield connector. Connectors C and D both connect to I2C1:
+
+ MikroBUS A: MikroBUS B:
+ Pin Board Signal SAM3X Pin Board Signal SAM3X
+ ---- ------------ ----- ---- ------------ -------
+ SCL I2C0_SCL PA17 SCL I2C0_SCL PA17
+ SDA I2C0_SDA PA1 SDA I2C0_SDA PA18
+
+ MikroBUS C: MikroBUS D:
+ Pin Board Signal SAM3X Pin Board Signal SAM3X
+ ---- ------------ ----- ---- ------------ -------
+ SCL I2C1_SCL PB13 SCL I2C1_SCL PB13
+ SDA I2C1_SDA PB12 SDA I2C1_SDA PB12
+
+SSD1306 OLED
+============
+
+ Hardware
+ --------
+ The HiletGo is a 128x64 OLED that can be driven either via SPI or I2C (SPI
+ is the default and is what is used here). I have mounted the OLED on a
+ proto click board. The OLED is connected as follows:
+
+ OLED ALIAS DESCRIPTION PROTO CLICK
+ ----- ----------- ------------- -----------------
+ GND Ground GND
+ VCC Power Supply 5V (3-5V)
+ D0 SCL,CLK,SCK Clock SCK
+ D1 SDA,MOSI Data MOSI,SDI
+ RES RST,RESET Reset RST (GPIO OUTPUT)
+ DC AO Data/Command INT (GPIO OUTPUT)
+ CS Chip Select CS (GPIO OUTPUT)
+
+ NOTE that this is a write-only display (MOSI only)!
+
Loading Code
============
+ [NOTE: This text was mostly copied from the Arduino Due README.txt. I
+ believe, however, that there have been significant changes to the
+ tool environment such that Bossac may no longer be usable. I don't
+ know that for certain and perhaps someone with more knowledge of
+ the tools than I could make this work. See STATUS below for the
+ current issues that I see.]
+
Installing the Arduino USB Driver under Windows
-----------------------------------------------
@@ -302,6 +393,25 @@ Loading Code
$ bossac.exe --port=COM7 --usb-port=false --boot=1
Set boot flash true
+ STATUS:
+ At present this procedure does not work. I do the following:
+
+ a) Open TeraTerm, select COM7 at 1200 baud, type a few ENTERs, and
+ close teraterm.
+
+ b) Execute the following command which claims to have successfully
+ written to FLASH.
+
+ bossac.exe --info --debug --port COM7 --usb-port=0 --erase --write --verify -b nuttx.bin -R
+
+ But the code does not boot. There is no indication of life.
+
+ c) Repeat a) then
+
+ bossac.exe --info --debug --port COM7 --usb-port=0 --verify -b nuttx.bin
+
+ And it says that the content of the FLASH is not good.
+
Uploading NuttX to the Flip&Click Using JTAG
--------------------------------------------
@@ -309,24 +419,29 @@ Loading Code
PIN SIGNAL JTAG STANDARD NOTES
--- -------------- ----------------- --------------------------------
- 1 3.3V VTref
+ 1 VCC-3.3V VTref
2 JTAG_TMS SWDIO/TMS SAM3X pin 31, Pulled up on board
3 GND GND
4 JTAG_TCK SWDCLK/TCK SAM3X pin 28, Pulled up on board
5 GND GND
- 6 JTAG_TDO SWO/EXta/TRACECTL SAM3X pin 30, ulled up on board
+ 6 JTAG_TDO SWO/EXta/TRACECTL SAM3X pin 30, Pulled up on board
7 N/C Key
8 JTAG_TDI NC/EXTb/TDI SAM3X pin 29, Pulled up on board
9 GND GNDDetect
- 10 MASTER-RESET nReset
+ 10 MRST nReset
- NOTE: The 10-pin JTAG connector is not populated on the Flip&Click SAM3X.
+ NOTE: The 10-pin JTAG connector is not populated on the Flip&Click
+ SAM3X. This is the part number for the SMD connector recommended by
+ ARM.com: Samtec FTSH-105-01-L-DV-K. For example:
+
+ https://www.digikey.com/product-detail/en/samtec-inc/FTSH-105-01-L-DV-K/SAM8799-ND/1875039
You should be able to use a 10- to 20-pin adapter to connect a SAM-ICE
- debugger to the Flip&Click SAM3X. I have this Olimex adapter:
- https://www.olimex.com/Products/ARM/JTAG/ARM-JTAG-20-10/ . But so far I
- have been unable to get the get the SAM-ICE to communicate with the
- Flip&Click.
+ or J-Link debugger to the Flip&Click SAM3X. I have this Olimex adapter:
+ https://www.olimex.com/Products/ARM/JTAG/ARM-JTAG-20-10/ . I have been
+ loading code and debugging with no problems using JTAG.
+
+ You can find photos my setup here: http://www.nuttx.org/doku.php?id=wiki:howtos:flipnclick-sam3x
Flip&Click SAM3X-specific Configuration Options
===============================================
@@ -426,7 +541,7 @@ Flip&Click SAM3X-specific Configuration Options
CONFIG_SAM34_GPIOF_IRQ
Configurations
-^^^^^^^^^^^^^^
+==============
Each Flip&Click SAM3X configuration is maintained in a sub-directory and
can be selected as follow:
@@ -461,15 +576,16 @@ Configurations
reconfiguration process.
2. Unless stated otherwise, all configurations generate console
- output on UART0 which is available both on the USB virtual COM port
- and on the PWML connector (see the section "Serial Consoles" above).
+ output on USART0 which is available either on the Arduion Shield
+ connector or on mikroBUS A as described above in the section entitled
+ "Serial Consoles".
3. Unless otherwise stated, the configurations are setup for
Cygwin under Windows:
Build Setup:
CONFIG_HOST_WINDOWS=y : Microsoft Windows
- CONFIG_WINDIWS_CYGWIN=y : Cygwin under Windoes
+ CONFIG_WINDIWS_CYGWIN=y : Cygwin under Windows
3. All of these configurations are set up to build under Windows using the
"GNU Tools for ARM Embedded Processors" that is maintained by ARM
@@ -498,3 +614,23 @@ Configuration sub-directories
Application Configuration:
CONFIG_NSH_BUILTIN_APPS=y : Enable starting apps from NSH command line
+
+ nxlines
+
+ This is an NSH configuration that supports the NX graphics example at
+ apps/examples/nxlines as a built-in application.
+
+ NOTES:
+
+ 1. This configuration derives from the nsh configuration. All of the
+ notes there apply here as well.
+
+ 2. The default configuration assumes there is the custom HiletGo OLED
+ in the mikroBUS B slot (and a Mikroe RS-232 Click card in the
+ mikroBUS A slot). That is easily changed by reconfiguring, however.
+ See the section entitled "HiletGo OLED" for information about this
+ custom click card.
+
+ STATUS:
+ 2018-02-11: No complaints from the software, but nothing appears on the
+ OLED. There is, most likely, an error in my custom HiletGo Click. Damn!
diff --git a/configs/flipnclick-sam3x/include/board.h b/configs/flipnclick-sam3x/include/board.h
index 0e2b42fe5d046c6cd3063da5d8a316bf736282af..2c648e7bcd366d8a46f04eb980b6268debc54ec7 100644
--- a/configs/flipnclick-sam3x/include/board.h
+++ b/configs/flipnclick-sam3x/include/board.h
@@ -79,7 +79,7 @@
/* PLLA configuration.
*
* Divider = 1
- * Multipler = 14
+ * Multiplier = 14
*/
#define BOARD_CKGR_PLLAR_MUL (13 << PMC_CKGR_PLLAR_MUL_SHIFT)
@@ -211,7 +211,7 @@
#define LED_PANIC 4 /* The system has crashed 2Hz N/C N/C N/C N/C */
#undef LED_IDLE /* MCU is is sleep mode ---- Not used ----- */
-/* Thus if LED L is glowing on and all other LEDs are off (except LED D which
+/* Thus if LED L is faintly glowing and all other LEDs are off (except LED D which
* was left on but is no longer controlled by NuttX and so may be in any state),
* NuttX has successfully booted and is, apparently, running normally and taking
* interrupts. If any of LEDs A-D are statically set, then NuttX failed to boot
@@ -255,4 +255,73 @@
* There are no alternatives for these pins.
*/
+/* SPI:
+ *
+ * SPI0 is available on the Arduino compatible SPI connector (but no SPI is
+ * available on pins D10-D13 of the main Arduino Shield connectors where
+ * you might expect then). The SPI connector is configured as follows:
+ *
+ * Pin Board Signal SAM3X Pin Board Signal SAM3X
+ * --- ------------ ----- --- ------------ -----
+ * 1 SPI0_MISO PA25 2 VCC-5V N/A
+ * 3 SPI0_SCK PA27 4 SPI0_MOSI PA26
+ * 5 MRST NRSTB 6 GND N/A
+ *
+ * SPI0 is also available on each of the mikroBUS Click connectors (in
+ * addition to 5V and GND). The connectivity differs only in the chip
+ * select pin:
+ *
+ * MikroBUS A: MikroBUS B:
+ * Pin Board Signal SAM3X Pin Board Signal SAM3X
+ * ---- ------------ ----- ---- ------------ -----
+ * CS SPI0_CS0 PA28 CS PA29 PA29
+ * SCK SPI0_SCK PA27 SCK SPI0_SCK PA27
+ * MISO SPI0_MISO PA25 MISO SPI0_MISO PA25
+ * MOSI SPI0_MOSI PA26 MOSI SPI0_MOSI PA26
+ *
+ * MikroBUS C: MikroBUS D:
+ * Pin Board Signal SAM3X Pin Board Signal SAM3X
+ * ---- ------------ ----- ---- ------------ -----
+ * CS SPI0_CS2 PB21 CS SPI0_CS3 PB23
+ * SCK SPI0_SCK PA27 SCK SPI0_SCK PA27
+ * MISO SPI0_MISO PA25 MISO SPI0_MISO PA25
+ * MOSI SPI0_MOSI PA26 MOSI SPI0_MOSI PA26
+ *
+ * Chip select pin definitions are provided in
+ * configs/flipnclick-sam3x/src/flipnclick-3x.h.
+ *
+ * There are no alternative pin selections for SPI0_MISO and SPIO_MOSI.
+ */
+
+#define GPIO_SPI0_SPCK GPIO_SPI0_SPCK_1
+
+/* I2C (aka TWI):
+ *
+ * I2C0 is available on pins D16-D17 of the Arduino Shield connectors where
+ * you would expect then. The SPI connector is configured as follows:
+ *
+ * Pin Label J1 Board Signal SAM3X
+ * --- ----- -- ------------ -----
+ * D16 SCL1 8 I2C0_SCL PA17
+ * D17 SDA1 7 I2C0_SDA PA18
+ *
+ * I2C0 and I2C1 are also available on the mikroBUS Click connectors (in
+ * addition to 5V and GND). The connectors A and B share I2C0 with the
+ * Arduino shield connector. Connectors C and D both connect to I2C1:
+ *
+ * MikroBUS A: MikroBUS B:
+ * Pin Board Signal SAM3X Pin Board Signal SAM3X
+ * ---- ------------ ----- ---- ------------ -------
+ * SCL I2C0_SCL PA18 SCL I2C0_SCL PA18
+ * SDA I2C0_SDA PA17 SDA I2C0_SDA PA17
+ *
+ * MikroBUS C: MikroBUS D:
+ * Pin Board Signal SAM3X Pin Board Signal SAM3X
+ * ---- ------------ ----- ---- ------------ -------
+ * SCL I2C1_SCL PB13 SCL I2C1_SCL PB13
+ * SDA I2C1_SDA PB12 SDA I2C1_SDA PB12
+ *
+ * There are no alternative pin selections for TWI0 and TWI1.
+ */
+
#endif /* __CONFIGS_FLIPNCLICK_SAM3X_INCLUDE_BOARD_H */
diff --git a/configs/flipnclick-sam3x/nsh/defconfig b/configs/flipnclick-sam3x/nsh/defconfig
index 79057461ad69e6838a1c971524cd704d86776fa6..545918a2cf359d9a1be79d020127930f43319310 100644
--- a/configs/flipnclick-sam3x/nsh/defconfig
+++ b/configs/flipnclick-sam3x/nsh/defconfig
@@ -1,4 +1,5 @@
# CONFIG_ARCH_RAMFUNCS is not set
+# CONFIG_SAM34_UART0 is not set
CONFIG_ARCH_BOARD_FLIPNCLICK_SAM3X=y
CONFIG_ARCH_BOARD="flipnclick-sam3x"
CONFIG_ARCH_CHIP_ATSAM3X8E=y
@@ -8,9 +9,6 @@ CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_BOARD_LOOPSPERMSEC=6965
CONFIG_BUILTIN=y
-CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NSH=y
CONFIG_FS_PROCFS=y
@@ -22,6 +20,7 @@ CONFIG_MAX_WDOGPARMS=2
CONFIG_MM_REGIONS=3
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
+CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_DISABLE_IFUPDOWN=y
CONFIG_NSH_FILEIOSIZE=512
@@ -33,12 +32,13 @@ CONFIG_RAM_SIZE=65536
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
+CONFIG_SAM34_USART0=y
CONFIG_SCHED_WAITPID=y
CONFIG_SDCLONE_DISABLE=y
CONFIG_START_DAY=28
CONFIG_START_MONTH=6
CONFIG_START_YEAR=2013
-CONFIG_TASK_NAME_SIZE=0
-CONFIG_UART0_SERIAL_CONSOLE=y
+CONFIG_TASK_NAME_SIZE=31
+CONFIG_USART0_SERIAL_CONSOLE=y
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WDOG_INTRESERVE=0
diff --git a/configs/flipnclick-sam3x/nxlines/defconfig b/configs/flipnclick-sam3x/nxlines/defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..84685e922c87ca8c6d2c385513370ddeffaa4387
--- /dev/null
+++ b/configs/flipnclick-sam3x/nxlines/defconfig
@@ -0,0 +1,58 @@
+# CONFIG_ARCH_RAMFUNCS is not set
+# CONFIG_NX_DISABLE_1BPP is not set
+# CONFIG_SAM34_UART0 is not set
+CONFIG_ARCH_BOARD_FLIPNCLICK_SAM3X=y
+CONFIG_ARCH_BOARD="flipnclick-sam3x"
+CONFIG_ARCH_CHIP_ATSAM3X8E=y
+CONFIG_ARCH_CHIP_SAM34=y
+CONFIG_ARCH_CHIP_SAM3X=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH="arm"
+CONFIG_BOARD_LOOPSPERMSEC=6965
+CONFIG_BUILTIN=y
+CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
+CONFIG_EXAMPLES_NSH=y
+CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=4
+CONFIG_EXAMPLES_NXLINES_BPP=1
+CONFIG_EXAMPLES_NXLINES_LINEWIDTH=4
+CONFIG_EXAMPLES_NXLINES=y
+CONFIG_FLIPNCLICK_SAM3X_SSD1306_MBB=y
+CONFIG_FLIPNCLICK_SAM3X_SSD1306=y
+CONFIG_FS_PROCFS=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_HOST_WINDOWS=y
+CONFIG_LCD_HILETGO=y
+CONFIG_LCD_MAXCONTRAST=255
+CONFIG_LCD=y
+CONFIG_MAX_TASKS=16
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_MM_REGIONS=3
+CONFIG_MQ_MAXMSGSIZE=64
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_NX_BLOCKING=y
+CONFIG_NX=y
+CONFIG_NXFONT_TOM_THUMB_4X6=y
+CONFIG_NXTK_BORDERWIDTH=2
+CONFIG_PREALLOC_MQ_MSGS=8
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_PREALLOC_WDOGS=4
+CONFIG_RAM_SIZE=65536
+CONFIG_RAM_START=0x20000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SAM34_SPI0=y
+CONFIG_SAM34_USART0=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_START_DAY=11
+CONFIG_START_MONTH=2
+CONFIG_USART0_SERIAL_CONSOLE=y
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_WDOG_INTRESERVE=0
diff --git a/configs/flipnclick-sam3x/src/Makefile b/configs/flipnclick-sam3x/src/Makefile
index b2e781f6a9d42a7b130eadef06ee72fe9aab266e..542654f163eade9750fd81b595634d6283821fbc 100644
--- a/configs/flipnclick-sam3x/src/Makefile
+++ b/configs/flipnclick-sam3x/src/Makefile
@@ -48,4 +48,12 @@ ifeq ($(CONFIG_LIB_BOARDCTL),y)
CSRCS += sam_appinit.c
endif
+ifeq ($(CONFIG_SAM34_SPI0),y)
+CSRCS += sam_spi0.c
+endif
+
+ifeq ($(CONFIG_FLIPNCLICK_SAM3X_SSD1306),y)
+CSRCS += sam_ssd1306.c
+endif
+
include $(TOPDIR)/configs/Board.mk
diff --git a/configs/flipnclick-sam3x/src/flipnclick-sam3x.h b/configs/flipnclick-sam3x/src/flipnclick-sam3x.h
index e35dacbe6d1e3ceb03915d009ecef366e2c706b3..0bde2f81e52ac0c924262049e0eec54d482bea7b 100644
--- a/configs/flipnclick-sam3x/src/flipnclick-sam3x.h
+++ b/configs/flipnclick-sam3x/src/flipnclick-sam3x.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __CONFIGS_FLIPNCLICK_SAM3X_SRC_ARDUNO_DUE_H
-#define __CONFIGS_FLIPNCLICK_SAM3X_SRC_ARDUNO_DUE_H
+#ifndef __CONFIGS_FLIPNCLICK_SAM3X_SRC_FLIPNCLICK_SAM3X_H
+#define __CONFIGS_FLIPNCLICK_SAM3X_SRC_FLIPNCLICK_SAM3X_H
/************************************************************************************
* Included Files
@@ -53,6 +53,24 @@
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
+/* Configuration ************************************************************/
+
+#define HAVE_SSD1306 1
+
+/* The SSD1306 LCD must be selected, installed on the Flip&Click, and must
+ * be configured to use the SPI interface.
+ */
+
+#if !defined(CONFIG_FLIPNCLICK_SAM3X_SSD1306) || \
+ !defined(CONFIG_LCD_SSD1306_SPI)
+# undef HAVE_SSD1306
+# undef CONFIG_FLIPNCLICK_SAM3X_SSD1306
+# undef CONFIG_FLIPNCLICK_SAM3X_SSD1306_MBA
+# undef CONFIG_FLIPNCLICK_SAM3X_SSD1306_MBB
+# undef CONFIG_FLIPNCLICK_SAM3X_SSD1306_MBC
+# undef CONFIG_FLIPNCLICK_SAM3X_SSD1306_MBD
+#endif
+
/* There are four LEDs on the top, blue side of the board. Only one can be
* controlled by software:
*
@@ -68,17 +86,150 @@
* A high output value illuminates the LEDs.
*/
-#define GPIO_LED_L (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_CLEAR | \
+#define GPIO_LED_L (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
GPIO_PORT_PIOB | GPIO_PIN27)
-#define GPIO_LED_A (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_CLEAR | \
+#define GPIO_LED_A (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
GPIO_PORT_PIOC | GPIO_PIN6)
-#define GPIO_LED_B (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_CLEAR | \
+#define GPIO_LED_B (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
GPIO_PORT_PIOC | GPIO_PIN5)
-#define GPIO_LED_C (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_CLEAR | \
+#define GPIO_LED_C (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
GPIO_PORT_PIOC | GPIO_PIN7)
-#define GPIO_LED_D (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_CLEAR | \
+#define GPIO_LED_D (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
GPIO_PORT_PIOC | GPIO_PIN8)
+/* SPI chip select pins.
+ *
+ * SPI0 is available on the Arduino compatible SPI connector (but no SPI is
+ * available on pins D10-D13 of the main Arduino Shield connectors where
+ * you might expect then). The SPI connector is configured as follows:
+ *
+ * Pin Board Signal SAM3X Pin Board Signal SAM3X
+ * --- ------------ ----- --- ------------ -----
+ * 1 SPI0_MISO PA25 2 VCC-5V N/A
+ * 3 SPI0_SCK PA27 4 SPI0_MOSI PA26
+ * 5 MRST NRSTB 6 GND N/A
+ *
+ * SPI0 is also available on each of the mikroBUS Click connectors (in
+ * addition to 5V and GND). The connectivity differs only in the chip
+ * select pin:
+ *
+ * MikroBUS A: MikroBUS B:
+ * Pin Board Signal SAM3X Pin Board Signal SAM3X
+ * ---- ------------ ----- ---- ------------ -----
+ * CS SPI0_CS0 PA28 CS PA29 PA29
+ * SCK SPI0_SCK PA27 SCK SPI0_SCK PA27
+ * MISO SPI0_MISO PA25 MISO SPI0_MISO PA25
+ * MOSI SPI0_MOSI PA26 MOSI SPI0_MOSI PA26
+ *
+ * MikroBUS C: MikroBUS D:
+ * Pin Board Signal SAM3X Pin Board Signal SAM3X
+ * ---- ------------ ----- ---- ------------ -----
+ * CS SPI0_CS2 PB21 CS SPI0_CS3 PB23
+ * SCK SPI0_SCK PA27 SCK SPI0_SCK PA27
+ * MISO SPI0_MISO PA25 MISO SPI0_MISO PA25
+ * MOSI SPI0_MOSI PA26 MOSI SPI0_MOSI PA26
+ */
+
+#define GPIO_MBA_CS (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_SET | \
+ GPIO_PORT_PIOA | GPIO_PIN28)
+#define MBA_CSNUM 0
+
+#define GPIO_MBB_CS (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_SET | \
+ GPIO_PORT_PIOA | GPIO_PIN29)
+#define MBB_CSNUM 1
+
+#define GPIO_MBC_CS (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_SET | \
+ GPIO_PORT_PIOB | GPIO_PIN21)
+#define MBC_CSNUM 2
+
+#define GPIO_MBD_CS (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_SET | \
+ GPIO_PORT_PIOB | GPIO_PIN23)
+#define MBD_CSNUM 3
+
+/* SSD1306 OLED
+ *
+ * The HiletGo is a 128x64 OLED that can be driven either via SPI or I2C (SPI
+ * is the default and is what is used here). I have mounted the OLED on a
+ * proto click board. The OLED is connected as follows:
+ *
+ * OLED ALIAS DESCRIPTION PROTO CLICK
+ * ----- ----------- ------------- -----------------
+ * GND Ground GND
+ * VCC Power Supply 5V (3-5V)
+ * D0 SCL,CLK,SCK Clock SCK
+ * D1 SDA,MOSI Data MOSI,SDI
+ * RES RST,RESET Reset RST (GPIO OUTPUT)
+ * DC AO Data/Command INT (GPIO OUTPUT)
+ * CS Chip Select CS (GPIO OUTPUT)
+ *
+ * NOTE that this is a write-only display (MOSI only)!
+ *
+ * MikroBUS A: MikroBUS B:
+ * Pin Board Signal SAM3X Pin Board Signal SAM3X
+ * ---- ------------ ----- ---- ------------ -------
+ * RST RSTA PC1 RST RSTB PC2
+ * DC INTA PD1 DC INTB PD2
+ *
+ * MikroBUS C: MikroBUS D:
+ * Pin Board Signal SAM3X Pin Board Signal SAM3X
+ * ---- ------------ ----- ---- ------------ -------
+ * RST RSTC PC3 RST RSTD PC4
+ * DC INTC PD3 DC INTD PD6
+ */
+
+#if defined(CONFIG_FLIPNCLICK_SAM3X_SSD1306_MBA)
+# ifndef CONFIG_SAM34_SPI0
+# error "The OLED driver requires CONFIG_SAM34_SPI0 in the configuration"
+# endif
+
+# define SSD1306_SPI_BUS 0
+# define SSD1306_CSNUM MBA_CSNUM
+# define GPIO_SSD1306_CS GPIO_MBA_CS
+# define GPIO_SSD1306_RST (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
+ GPIO_PORT_PIOC | GPIO_PIN1)
+# define GPIO_SSD1306_DC (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
+ GPIO_PORT_PIOD | GPIO_PIN1)
+
+#elif defined(CONFIG_FLIPNCLICK_SAM3X_SSD1306_MBB)
+# ifndef CONFIG_SAM34_SPI0
+# error "The OLED driver requires CONFIG_SAM34_SPI0 in the configuration"
+# endif
+
+# define SSD1306_SPI_BUS 0
+# define SSD1306_CSNUM MBB_CSNUM
+# define GPIO_SSD1306_CS GPIO_MBB_CS
+# define GPIO_SSD1306_RST (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
+ GPIO_PORT_PIOC | GPIO_PIN2)
+# define GPIO_SSD1306_DC (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
+ GPIO_PORT_PIOD | GPIO_PIN2)
+
+#elif defined(CONFIG_FLIPNCLICK_SAM3X_SSD1306_MBC)
+# ifndef CONFIG_SAM34_SPI0
+# error "The OLED driver requires CONFIG_SAM34_SPI0 in the configuration"
+# endif
+
+# define SSD1306_SPI_BUS 0
+# define SSD1306_CSNUM MBC_CSNUM
+# define GPIO_SSD1306_CS GPIO_MBC_CS
+# define GPIO_SSD1306_RST (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
+ GPIO_PORT_PIOC | GPIO_PIN3)
+# define GPIO_SSD1306_DC (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
+ GPIO_PORT_PIOD | GPIO_PIN3)
+
+#elif defined(CONFIG_FLIPNCLICK_SAM3X_SSD1306_MBD)
+# ifndef CONFIG_SAM34_SPI0
+# error "The OLED driver requires CONFIG_SAM34_SPI0 in the configuration"
+# endif
+
+# define SSD1306_SPI_BUS 0
+# define SSD1306_CSNUM MBD_CSNUM
+# define GPIO_SSD1306_CS GPIO_MBD_CS
+# define GPIO_SSD1306_RST (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
+ GPIO_PORT_PIOC | GPIO_PIN4)
+# define GPIO_SSD1306_DC (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
+ GPIO_PORT_PIOD | GPIO_PIN6)
+#endif
+
/************************************************************************************
* Public Types
************************************************************************************/
@@ -109,6 +260,21 @@
int sam_bringup(void);
+/****************************************************************************
+ * Name: sam_graphics_setup
+ *
+ * Description:
+ * Called by either NX initialization logic (via board_graphics_setup) or
+ * directly from the board bring-up logic in order to configure the
+ * SSD1306 OLED.
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_SSD1306
+struct lcd_dev_s; /* Forward reference */
+FAR struct lcd_dev_s *sam_graphics_setup(unsigned int devno);
+#endif
+
#endif /* __ASSEMBLY__ */
-#endif /* __CONFIGS_FLIPNCLICK_SAM3X_SRC_ARDUNO_DUE_H */
+#endif /* __CONFIGS_FLIPNCLICK_SAM3X_SRC_FLIPNCLICK_SAM3X_H */
diff --git a/configs/flipnclick-sam3x/src/sam_autoleds.c b/configs/flipnclick-sam3x/src/sam_autoleds.c
index 3f0b450178d88468c1e0d98d9a68e36cfc1e0b37..ff309be24aa1f115a2d9b0d77ab8ece4919c2b9d 100644
--- a/configs/flipnclick-sam3x/src/sam_autoleds.c
+++ b/configs/flipnclick-sam3x/src/sam_autoleds.c
@@ -64,8 +64,8 @@
* LED_PANIC The system has crashed 2Hz N/C N/C N/C N/C
* LED_IDLE MCU is is sleep mode ---- Not used -----
*
- * Thus if LED L is glowing on and all other LEDs are off (except LED D
- * which was left on but is no longer controlled by NuttX and so may be in
+ * Thus if LED L is faintly glowing and all other LEDs are off (except LED
+ * D which was left on but is no longer controlled by NuttX and so may be in
* any state), NuttX has successfully booted and is, apparently, running
* normally and taking interrupts. If any of LEDs A-D are statically set,
* then NuttX failed to boot and the LED indicates the initialization phase
@@ -99,7 +99,7 @@
#ifdef CONFIG_ARCH_LEDS
/****************************************************************************
- * Processor Definitinos
+ * Processor Definitions
****************************************************************************/
/* LED indices */
@@ -123,7 +123,7 @@ static void board_autoled_setone(int ledndx)
sam_gpiowrite(GPIO_LED_L, ledon[INDEX_LED_L]);
sam_gpiowrite(GPIO_LED_A, ledon[INDEX_LED_A]);
sam_gpiowrite(GPIO_LED_B, ledon[INDEX_LED_B]);
- sam_gpiowrite(GPIO_LED_C, ledon[INDEX_LED_D]);
+ sam_gpiowrite(GPIO_LED_C, ledon[INDEX_LED_C]);
sam_gpiowrite(GPIO_LED_D, ledon[INDEX_LED_D]);
}
@@ -176,7 +176,7 @@ void board_autoled_on(int led)
board_autoled_setone(INDEX_LED_B);
break;
- case 2:
+ case 2:
board_autoled_setone(INDEX_LED_C);
break;
diff --git a/configs/flipnclick-sam3x/src/sam_bringup.c b/configs/flipnclick-sam3x/src/sam_bringup.c
index 28a9d427357e4fce8bca49ed72c1b95a54a6b6a9..3d1d229bb13104f516a4778bf762dc6438547b55 100644
--- a/configs/flipnclick-sam3x/src/sam_bringup.c
+++ b/configs/flipnclick-sam3x/src/sam_bringup.c
@@ -84,6 +84,15 @@ int sam_bringup(void)
}
#endif
+#if defined(HAVE_SSD1306) && !defined(CONFIG_NXSTART_EXTERNINIT)
+ /* Configure the SSD1306 OLED */
+
+ if (sam_graphics_setup(0) == NULL)
+ {
+ syslog(LOG_ERR,"ERROR: Failed to configure the SSD1306 OLED\n");
+ }
+#endif
+
UNUSED(ret);
return OK;
}
diff --git a/configs/flipnclick-sam3x/src/sam_spi0.c b/configs/flipnclick-sam3x/src/sam_spi0.c
new file mode 100644
index 0000000000000000000000000000000000000000..40c6bc2fd0a011e2c62814fbef9f7a4279c40813
--- /dev/null
+++ b/configs/flipnclick-sam3x/src/sam_spi0.c
@@ -0,0 +1,220 @@
+/************************************************************************************
+ * configs/flipnclick-sam3x/src/sam_spi0.c
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "up_arch.h"
+#include "chip.h"
+#include "sam_gpio.h"
+#include "sam_spi.h"
+
+#include "flipnclick-sam3x.h"
+
+#ifdef CONFIG_SAM34_SPI0
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: sam_spidev_initialize
+ *
+ * Description:
+ * Called to configure SPI chip select GPIO pins for the SAM4E-EK board.
+ *
+ ************************************************************************************/
+
+void weak_function sam_spidev_initialize(void)
+{
+#ifdef HAVE_SSD1306
+ /* Configure the SSD1306 chip select and command/data GPIOs */
+
+ sam_configgpio(GPIO_SSD1306_CS);
+ sam_configgpio(GPIO_SSD1306_DC);
+#endif
+}
+
+/****************************************************************************
+ * Name: sam_spi0select, sam_spi0status, and sam_spic0mddata
+ *
+ * Description:
+ * These external functions must be provided by board-specific logic. They
+ * include:
+ *
+ * o sam_spi0select is a functions tomanage the board-specific chip selects
+ * o sam_spi0status and sam_spic0mddata: Implementations of the status
+ * and cmddata methods of the SPI interface defined by struct spi_ops_
+ * (see include/nuttx/spi/spi.h). All other methods including
+ * sam_spibus_initialize()) are provided by common SAM3/4 logic.
+ *
+ * To use this common SPI logic on your board:
+ *
+ * 1. Provide logic in sam_boardinitialize() to configure SPI chip select
+ * pins.
+ * 2. Provide sam_spi0select() and sam_spi0status() functions in your board-
+ * specific logic. These functions will perform chip selection and
+ * status operations using GPIOs in the way your board is configured.
+ * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
+ * sam_spic0mddata() functions in your board-specific logic. This
+ * function will perform cmd/data selection operations using GPIOs in
+ * the way your board is configured.
+ * 3. Add a call to sam_spibus_initialize() in your low level application
+ * initialization logic
+ * 4. The handle returned by sam_spibus_initialize() may then be used to bind the
+ * SPI driver to higher level logic (e.g., calling
+ * mmcsd_spislotinitialize(), for example, will bind the SPI driver to
+ * the SPI MMC/SD driver).
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_spi0select
+ *
+ * Description:
+ * PIO chip select pins may be programmed by the board specific logic in
+ * one of two different ways. First, the pins may be programmed as SPI
+ * peripherals. In that case, the pins are completely controlled by the
+ * SPI driver. This method still needs to be provided, but it may be only
+ * a stub.
+ *
+ * An alternative way to program the PIO chip select pins is as a normal
+ * GPIO output. In that case, the automatic control of the CS pins is
+ * bypassed and this function must provide control of the chip select.
+ * NOTE: In this case, the GPIO output pin does *not* have to be the
+ * same as the NPCS pin normal associated with the chip select number.
+ *
+ * Input Parameters:
+ * devid - Identifies the (logical) device
+ * selected - TRUE:Select the device, FALSE:De-select the device
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void sam_spi0select(uint32_t devid, bool selected)
+{
+ spiinfo("devid: %08x CS: %s\n",
+ (unsigned int)devid, selected ? "assert" : "de-assert");
+
+#ifdef HAVE_SSD1306
+ if (devid == SPIDEV_DISPLAY(0))
+ {
+ /* Low: the display is selected
+ * High: the display is deselected
+ */
+
+ sam_gpiowrite(GPIO_SSD1306_CS, !selected);
+ }
+#endif
+}
+
+/****************************************************************************
+ * Name: sam_spi0status
+ *
+ * Description:
+ * Return status information associated with the SPI device.
+ *
+ * Input Parameters:
+ * devid - Identifies the (logical) device
+ *
+ * Returned Value:
+ * Bit-encoded SPI status (see include/nuttx/spi/spi.h.
+ *
+ ****************************************************************************/
+
+uint8_t sam_spi0status(FAR struct spi_dev_s *dev, uint32_t devid)
+{
+ spiinfo("Returning nothing\n");
+ return 0;
+}
+/****************************************************************************
+ * Name: sam_spi0cmddata
+ *
+ * Description:
+ * Some SPI devices require an additional control to determine if the SPI
+ * data being sent is a command or is data. If CONFIG_SPI_CMDDATA then
+ * this function will be called to different be command and data transfers.
+ *
+ * This is often needed, for example, by LCD drivers. Some LCD hardware
+ * may be configured to use 9-bit data transfers with the 9th bit
+ * indicating command or data. That same hardware may be configurable,
+ * instead, to use 8-bit data but to require an additional, board-
+ * specific PIO control to distinguish command and data. This function
+ * would be needed in that latter case.
+ *
+ * Input Parameters:
+ * dev - SPI device info
+ * devid - Identifies the (logical) device
+ *
+ * Returned Value:
+ * Zero on success; a negated errno on failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_CMDDATA
+int sam_spi0cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
+{
+ spiinfo("devid: %08x %s\n", (unsigned int)devid, cmd ? "cmd" : "data");
+
+#ifdef HAVE_SSD1306
+ if (devid == SPIDEV_DISPLAY(0))
+ {
+ /* High: the inputs are treated as display data.
+ * Low: the inputs are transferred to the command registers.
+ */
+
+ sam_gpiowrite(GPIO_SSD1306_DC, !cmd);
+ }
+#endif
+
+ return 0;
+
+}
+#endif
+
+#endif /* CONFIG_SAM34_SPI0 */
diff --git a/configs/flipnclick-sam3x/src/sam_ssd1306.c b/configs/flipnclick-sam3x/src/sam_ssd1306.c
new file mode 100644
index 0000000000000000000000000000000000000000..f6cfa857e2aefcc226cd84ce109c0d8a0e2dcf42
--- /dev/null
+++ b/configs/flipnclick-sam3x/src/sam_ssd1306.c
@@ -0,0 +1,172 @@
+/****************************************************************************
+ * config/flipnclick-sam3x/src/sam_ssd1306.c
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* SSD1306 OLED
+ *
+ * The HiletGo is a 128x64 OLED that can be driven either via SPI or I2C (SPI
+ * is the default and is what is used here). I have mounted the OLED on a
+ * proto click board. The OLED is connected as follows:
+ *
+ * OLED ALIAS DESCRIPTION PROTO CLICK
+ * ----- ----------- ------------- -----------------
+ * GND Ground GND
+ * VCC Power Supply 5V (3-5V)
+ * D0 SCL,CLK,SCK Clock SCK
+ * D1 SDA,MOSI Data MOSI,SDI
+ * RES RST,RESET Reset RST (GPIO OUTPUT)
+ * DC AO Data/Command INT (GPIO OUTPUT)
+ * CS Chip Select CS (GPIO OUTPUT)
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+
+#include
+#include
+#include
+#include
+
+#if defined(CONFIG_VIDEO_FB) && defined(CONFIG_LCD_FRAMEBUFFER)
+# include
+#endif
+
+#include "sam_gpio.h"
+#include "sam_spi.h"
+
+#include "flipnclick-sam3x.h"
+
+#ifdef HAVE_SSD1306
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* Configuration ************************************************************/
+
+#ifndef CONFIG_SPI_CMDDATA
+# error "The OLED driver requires CONFIG_SPI_CMDDATA in the configuration"
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_graphics_setup
+ *
+ * Description:
+ * Called by either NX initialization logic (via board_graphics_setup) or
+ * directly from the board bring-up logic in order to configure the
+ * SSD1306 OLED.
+ *
+ ****************************************************************************/
+
+FAR struct lcd_dev_s *sam_graphics_setup(unsigned int devno)
+{
+ FAR struct spi_dev_s *spi;
+ FAR struct lcd_dev_s *dev;
+
+ /* Configure the OLED GPIOs. This initial configuration is RESET low,
+ * putting the OLED into reset state.
+ */
+
+ sam_configgpio(GPIO_SSD1306_RST);
+
+ /* Wait a bit then release the OLED from the reset state */
+
+ up_mdelay(20);
+ sam_gpiowrite(GPIO_SSD1306_RST, true);
+
+ /* Get the SPI1 port interface */
+
+ spi = sam_spibus_initialize(GPIO_SSD1306_CS);
+ if (!spi)
+ {
+ lcderr("ERROR: Failed to initialize SPI port 1\n");
+ }
+ else
+ {
+ /* Bind the SPI port to the OLED */
+
+ dev = ssd1306_initialize(spi, NULL, devno);
+ if (!dev)
+ {
+ lcderr("ERROR: Failed to bind SPI port 1 to OLED %d: %d\n", devno);
+ }
+ else
+ {
+ lcdinfo("Bound SPI port 1 to OLED %d\n", devno);
+
+ /* And turn the OLED on */
+
+ (void)dev->setpower(dev, CONFIG_LCD_MAXPOWER);
+
+#if defined(CONFIG_VIDEO_FB) && defined(CONFIG_LCD_FRAMEBUFFER)
+ /* Initialize and register the simulated framebuffer driver */
+
+ ret = fb_register(0, 0);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret);
+ }
+#endif
+
+ return dev;
+ }
+ }
+
+ return NULL;
+}
+
+/****************************************************************************
+ * Name: board_graphics_setup
+ *
+ * Description:
+ * Called by NX initialization logic to configure the OLED.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NXSTART_EXTERNINIT
+FAR struct lcd_dev_s *board_graphics_setup(unsigned int devno)
+{
+ return sam_graphics_setup(devno);
+}
+#endif
+
+#endif /* HAVE_SSD1306 */
diff --git a/configs/freedom-k64f/README.txt b/configs/freedom-k64f/README.txt
index 5559b2fe5f1363fc99c9ae7fba92f4575446f1fc..a2ce126b7de7b6746e4d25213f7aa77a10ea27a4 100644
--- a/configs/freedom-k64f/README.txt
+++ b/configs/freedom-k64f/README.txt
@@ -618,7 +618,7 @@ GNU Toolchain Options
=====================
The NuttX make system supports several GNU-based toolchains under Linux,
- Cygwin under Windows, and Windoes native. To select a toolchain:
+ Cygwin under Windows, and Windows native. To select a toolchain:
1. Use 'make menuconfig' and select the toolchain that you are using
under the System Type menu.
diff --git a/configs/freedom-k66f/README.txt b/configs/freedom-k66f/README.txt
index 7f5da7cffaa2a67a14457a2e98600406c73e9e3c..c78a3c4c807884bda0648d58c0f5d9aaa516b758 100644
--- a/configs/freedom-k66f/README.txt
+++ b/configs/freedom-k66f/README.txt
@@ -621,7 +621,7 @@ GNU Toolchain Options
=====================
The NuttX make system supports several GNU-based toolchains under Linux,
- Cygwin under Windows, and Windoes native. To select a toolchain:
+ Cygwin under Windows, and Windows native. To select a toolchain:
1. Use 'make menuconfig' and select the toolchain that you are using
under the System Type menu.
@@ -972,4 +972,5 @@ Status
2017-02-14: nsh: SDHC DMA is not working yet. Buttons and SDIO with
automounter is working.
netnsh:Is building but Ehternet is not working yet. TX is called but
- not IRQ is issued.
\ No newline at end of file
+ not IRQ is issued.
+
diff --git a/configs/freedom-kl25z/src/kl_cc3000.c b/configs/freedom-kl25z/src/kl_cc3000.c
index e233a64d062f16223ba31159b02be995d4abe089..c446ff870b6956fb33b51f63755917daedc225f3 100644
--- a/configs/freedom-kl25z/src/kl_cc3000.c
+++ b/configs/freedom-kl25z/src/kl_cc3000.c
@@ -334,7 +334,7 @@ int wireless_archinitialize(size_t max_rx_size)
* Warning: This function must be called before ANY other wlan driver
* function
*
- * Input Parmeters:
+ * Input Parameters:
* sWlanCB Asynchronous events callback.
* 0 no event call back.
* - Call back parameters:
diff --git a/configs/freedom-kl25z/src/kl_spi.c b/configs/freedom-kl25z/src/kl_spi.c
index e952963d1be54d780787f9685ad40c56e85b2bcf..566af53909b282b95b4fbfb46bb0a76754218d77 100644
--- a/configs/freedom-kl25z/src/kl_spi.c
+++ b/configs/freedom-kl25z/src/kl_spi.c
@@ -133,7 +133,7 @@ void weak_function kl_spidev_initialize(void)
* devid - Identifies the (logical) device
* selected - TRUE:Select the device, FALSE:De-select the device
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -182,7 +182,7 @@ void kl_spi1select(FAR struct spi_dev_s *dev, uint32_t devid,
* Input Parameters:
* devid - Identifies the (logical) device
*
- * Returned Values:
+ * Returned Value:
* Bit-encoded SPI status (see include/nuttx/spi/spi.h.
*
****************************************************************************/
@@ -213,7 +213,7 @@ uint8_t kl_spi1status(FAR struct spi_dev_s *dev, uint32_t devid)
* devid - Identifies the (logical) device
* cmd - Determines where command or data should be selected.
*
- * Returned Values:
+ * Returned Value:
* Bit-encoded SPI status (see include/nuttx/spi/spi.h.
*
****************************************************************************/
diff --git a/configs/freedom-kl26z/src/kl_spi.c b/configs/freedom-kl26z/src/kl_spi.c
index 4c94db9fa3098019654161242ccfbb95872b5738..01cb52fc912efa632680851155e5d320226d368d 100644
--- a/configs/freedom-kl26z/src/kl_spi.c
+++ b/configs/freedom-kl26z/src/kl_spi.c
@@ -124,7 +124,7 @@ void weak_function kl_spidev_initialize(void)
* devid - Identifies the (logical) device
* selected - TRUE:Select the device, FALSE:De-select the device
*
- * Returned Values:
+ * Returned Value:
* None
*
****************************************************************************/
@@ -156,7 +156,7 @@ void kl_spi1select(FAR struct spi_dev_s *dev, uint32_t devid,
* Input Parameters:
* devid - Identifies the (logical) device
*
- * Returned Values:
+ * Returned Value:
* Bit-encoded SPI status (see include/nuttx/spi/spi.h.
*
****************************************************************************/
@@ -187,7 +187,7 @@ uint8_t kl_spi1status(FAR struct spi_dev_s *dev, uint32_t devid)
* devid - Identifies the (logical) device
* cmd - Determines where command or data should be selected.
*
- * Returned Values:
+ * Returned Value:
* Bit-encoded SPI status (see include/nuttx/spi/spi.h.
*
****************************************************************************/
diff --git a/configs/hymini-stm32v/src/hymini-stm32v.h b/configs/hymini-stm32v/src/hymini-stm32v.h
index f821d03465d779b6a762098b1893a3abba7b21cc..cdfd96704a27c0d15ce3c699577169aa23bb71fb 100644
--- a/configs/hymini-stm32v/src/hymini-stm32v.h
+++ b/configs/hymini-stm32v/src/hymini-stm32v.h
@@ -1,7 +1,7 @@
/************************************************************************************
* configs/hymini-stm32v/src/hymini-stm32v.h
*
- * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009, 2011, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
* Laurent Latil
*
@@ -122,7 +122,7 @@
*
************************************************************************************/
-extern void weak_function stm32_spidev_initialize(void);
+void weak_function stm32_spidev_initialize(void);
/************************************************************************************
* Name: stm32_usbinitialize
@@ -132,7 +132,28 @@ extern void weak_function stm32_spidev_initialize(void);
*
************************************************************************************/
-extern void weak_function stm32_usbinitialize(void);
+void weak_function stm32_usbinitialize(void);
+
+/************************************************************************************
+ * Name: stm32_tsc_setup
+ *
+ * Description:
+ * This function is called by board-bringup logic to configure the touchscreen
+ * device. This function will register the driver as /dev/inputN where N is the
+ * minor device number.
+ *
+ * Input Parameters:
+ * minor - The input device minor number
+ *
+ * Returned Value:
+ * Zero is returned on success. Otherwise, a negated errno value is returned to
+ * indicate the nature of the failure.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_INPUT
+int stm32_tsc_setup(int minor);
+#endif
#endif /* __ASSEMBLY__ */
#endif /* __CONFIGS_HYMINI_STM32V_H */
diff --git a/configs/hymini-stm32v/src/stm32_appinit.c b/configs/hymini-stm32v/src/stm32_appinit.c
index 5b99c4445b668c38fc53f9278a3291c29c451caf..85be09ecb7dae51fdbdfba2add1bb201ec852dae 100644
--- a/configs/hymini-stm32v/src/stm32_appinit.c
+++ b/configs/hymini-stm32v/src/stm32_appinit.c
@@ -1,7 +1,7 @@
/****************************************************************************
* config/hymini-stm32v/src/stm32_appinit.c
*
- * Copyright (C) 2009, 2011, 2016-2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009, 2011, 2016-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -170,10 +170,11 @@ static int nsh_cdinterrupt(int irq, FAR void *context, FAR void *arg)
int board_app_initialize(uintptr_t arg)
{
-#ifdef NSH_HAVEMMCSD
int ret;
+#ifdef NSH_HAVEMMCSD
/* Card detect */
+
bool cd_status;
/* Configure the card detect GPIO */
@@ -220,5 +221,17 @@ int board_app_initialize(uintptr_t arg)
sdio_mediachange(g_sdiodev, cd_status);
#endif
+
+#ifdef CONFIG_INPUT
+ /* Initialize the touchscreen */
+
+ ret = stm32_tsc_setup(0);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret);
+ }
+#endif
+
+ UNUSED(ret);
return OK;
}
diff --git a/configs/hymini-stm32v/src/stm32_ts.c b/configs/hymini-stm32v/src/stm32_ts.c
index 781eafc9f15313bc43eb47b8dc8be52fcf8b77ee..59f7caa0509a7f4374e8149bcef8bcbee31a0b3d 100644
--- a/configs/hymini-stm32v/src/stm32_ts.c
+++ b/configs/hymini-stm32v/src/stm32_ts.c
@@ -53,7 +53,7 @@
#include "hymini-stm32v.h"
/************************************************************************************
- * Pre-processor Defintiions
+ * Pre-processor Definitions
************************************************************************************/
#if !defined(CONFIG_STM32_SPI1)
@@ -136,13 +136,12 @@ static bool hymini_ts_pendown(FAR struct ads7843e_config_s *state)
}
/****************************************************************************
- * Name: board_tsc_setup
+ * Name: stm32_tsc_setup
*
* Description:
- * Each board that supports a touchscreen device must provide this function.
- * This function is called by application-specific, setup logic to
- * configure the touchscreen device. This function will register the driver
- * as /dev/inputN where N is the minor device number.
+ * This function is called by board-bringup logic to configure the
+ * touchscreen device. This function will register the driver as
+ * /dev/inputN where N is the minor device number.
*
* Input Parameters:
* minor - The input device minor number
@@ -153,7 +152,7 @@ static bool hymini_ts_pendown(FAR struct ads7843e_config_s *state)
*
****************************************************************************/
-int board_tsc_setup(int minor)
+int stm32_tsc_setup(int minor)
{
FAR struct spi_dev_s *dev;
@@ -172,24 +171,3 @@ int board_tsc_setup(int minor)
return ads7843e_register(dev, &ts_cfg, minor);
}
-
-/****************************************************************************
- * Name: board_tsc_teardown
- *
- * Description:
- * Each board that supports a touchscreen device must provide this function.
- * This function is called by application-specific, setup logic to
- * uninitialize the touchscreen device.
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * None.
- *
- ****************************************************************************/
-
-void board_tsc_teardown(void)
-{
- /* FIXME What can/should we do here ? */
-}
diff --git a/configs/indium-f7/src/stm32_usb.c b/configs/indium-f7/src/stm32_usb.c
index 794975f51c33b465e69fa236562bfd42a1a331cd..9089232cec761d2d6510c4e2574e5ceb689b716c 100644
--- a/configs/indium-f7/src/stm32_usb.c
+++ b/configs/indium-f7/src/stm32_usb.c
@@ -49,6 +49,7 @@
#include
#include
+#include
#include
#include
#include
@@ -240,9 +241,9 @@ int stm32_usbhost_initialize(void)
uinfo("Start usbhost_waiter\n");
- pid = task_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO,
- CONFIG_STM32F4DISCO_USBHOST_STACKSIZE,
- (main_t)usbhost_waiter, (FAR char * const *)NULL);
+ pid = kthread_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO,
+ CONFIG_STM32F4DISCO_USBHOST_STACKSIZE,
+ (main_t)usbhost_waiter, (FAR char * const *)NULL);
return pid < 0 ? -ENOEXEC : OK;
}
@@ -294,11 +295,11 @@ void stm32_usbhost_vbusdrive(int iface, bool enable)
* Setup to receive an interrupt-level callback if an overcurrent condition is
* detected.
*
- * Input Parameter:
+ * Input Parameters:
* handler - New overcurrent interrupt handler
* arg - The argument provided for the interrupt handler
*
- * Returned value:
+ * Returned Value:
* Zero (OK) is returned on success. Otherwise, a negated errno value is returned
* to indicate the nature of the failure.
*
diff --git a/configs/lc823450-xgevk/README.txt b/configs/lc823450-xgevk/README.txt
index 63db6a0a3088f93213d7da54f0d04b05745a5265..a152c893e1f74c6a84a2f3e719185f4d46d150d6 100644
--- a/configs/lc823450-xgevk/README.txt
+++ b/configs/lc823450-xgevk/README.txt
@@ -45,13 +45,33 @@ to set MSP (main stack pointer) as follows.
SMP related Status
^^^^^^^^^^^^^^^^^^
-Currently all applications except for ostest work in SMP mode but might stop
-due to deadlocks or ASSERT().
-
CPU activities are shown at D9 (CPU0) and D10 (CPU1) respectively.
-1. "nsh> smp" works but the result will be corrupted.
-2. "nsh> ostest" works but might cause a deadlock or assertion.
+Currently all applications except for ostest work in SMP mode but might stop
+due to deadlocks or ASSERT(). For a workaround, please try
+
+$ cd apps; git diff
+diff --git a/examples/ostest/waitpid.c b/examples/ostest/waitpid.c
+index 687f50ca..8418eff8 100644
+--- a/examples/ostest/waitpid.c
++++ b/examples/ostest/waitpid.c
+@@ -54,7 +54,7 @@
+ ****************************************************************************/
+
+ #define RETURN_STATUS 14
+-#define NCHILDREN 3
++#define NCHILDREN 2
+ #define PRIORITY 100
+
+ /****************************************************************************
+
+If other deadlocks or ASSERT() still happen, please try the following.
+
+$ cd nuttx; git revert e238c8b0904988b966c3b33e7df2ba3faba52e2b
+
+This will revert the changes for clock_systimer() for 64bit so that it can
+use spinlock to protect the internal data. We think that there still exist
+race conditions somewhere in SMP logic but the revert might relax the conditions.
Other Status
^^^^^^^^^^^^
diff --git a/configs/lc823450-xgevk/audio/defconfig b/configs/lc823450-xgevk/audio/defconfig
index ae8ef0ad3763e87ee2fdb116ec8ff549c8cda39a..e06f30abc50630677f90a55b893f54623373724c 100644
--- a/configs/lc823450-xgevk/audio/defconfig
+++ b/configs/lc823450-xgevk/audio/defconfig
@@ -127,6 +127,7 @@ CONFIG_START_MONTH=10
CONFIG_START_YEAR=2013
CONFIG_SYSTEM_I2CTOOL=y
CONFIG_SYSTEM_NXPLAYER=y
+CONFIG_SYSTEM_TIME64=y
CONFIG_SYSTEM_USBMSC_CMD_STACKSIZE=2048
CONFIG_SYSTEM_USBMSC_DEVPATH1="/dev/mtdblock0p10"
CONFIG_SYSTEM_USBMSC_DEVPATH2="/dev/mtdblock1"
diff --git a/configs/lc823450-xgevk/nsh/defconfig b/configs/lc823450-xgevk/nsh/defconfig
index 74040a673989e2b1560fd721fe0ace0af5220e23..91b32fbe49b1c52197313dd51952ef8f35ca0de6 100644
--- a/configs/lc823450-xgevk/nsh/defconfig
+++ b/configs/lc823450-xgevk/nsh/defconfig
@@ -124,6 +124,7 @@ CONFIG_START_DAY=3
CONFIG_START_MONTH=10
CONFIG_START_YEAR=2013
CONFIG_SYSTEM_I2CTOOL=y
+CONFIG_SYSTEM_TIME64=y
CONFIG_TASK_NAME_SIZE=24
CONFIG_UART0_RXBUFSIZE=512
CONFIG_UART0_SERIAL_CONSOLE=y
diff --git a/configs/lc823450-xgevk/rndis/defconfig b/configs/lc823450-xgevk/rndis/defconfig
index c07e826ca66abe90b886e1d4afc831ab0c683c92..32a899edd9d64cf7d6220426702365fb678c24df 100644
--- a/configs/lc823450-xgevk/rndis/defconfig
+++ b/configs/lc823450-xgevk/rndis/defconfig
@@ -150,6 +150,9 @@ CONFIG_SCHED_HAVE_PARENT=y
CONFIG_SCHED_HPWORKPERIOD=50000
CONFIG_SCHED_HPWORKPRIORITY=192
CONFIG_SCHED_HPWORK=y
+CONFIG_SCHED_INSTRUMENTATION_BUFFER=y
+CONFIG_SCHED_INSTRUMENTATION_PREEMPTION=y
+CONFIG_SCHED_INSTRUMENTATION=y
CONFIG_SCHED_LPWORK=y
CONFIG_SCHED_ONEXIT_MAX=32
CONFIG_SCHED_ONEXIT=y
@@ -169,6 +172,7 @@ CONFIG_START_YEAR=2013
CONFIG_SYSTEM_I2CTOOL=y
CONFIG_SYSTEM_NXPLAYER=y
CONFIG_SYSTEM_PING=y
+CONFIG_SYSTEM_TIME64=y
CONFIG_TASK_NAME_SIZE=24
CONFIG_TELNET_CHARACTER_MODE=y
CONFIG_UART0_RXBUFSIZE=512
diff --git a/configs/lc823450-xgevk/src/lc823450_bringup.c b/configs/lc823450-xgevk/src/lc823450_bringup.c
index 8b41c839fe5f4c84aa4f7ef3c354f6d8b73e1de1..d80e5f0a0206cfcd1be773f133f07bd99fb7b37e 100644
--- a/configs/lc823450-xgevk/src/lc823450_bringup.c
+++ b/configs/lc823450-xgevk/src/lc823450_bringup.c
@@ -49,6 +49,8 @@
# include
#endif
+#include
+
#ifdef CONFIG_RNDIS
# include
#endif
@@ -132,7 +134,7 @@ int lc823450_bringup(void)
/* NOTE: pid=4 is assumed to be lpwork */
- sched_setaffinity(4, sizeof(cpu_set_t), &cpuset);
+ (void)nxsched_setaffinity(4, sizeof(cpu_set_t), &cpuset);
#endif
/* If we got here then perhaps not all initialization was successful, but
diff --git a/configs/lc823450-xgevk/usb/defconfig b/configs/lc823450-xgevk/usb/defconfig
index 4b680dbd510be51c813643b17f67c16c44a842f3..3ca1889d1bfd1ae42160c806008c2c4c6df56336 100644
--- a/configs/lc823450-xgevk/usb/defconfig
+++ b/configs/lc823450-xgevk/usb/defconfig
@@ -126,6 +126,7 @@ CONFIG_START_DAY=3
CONFIG_START_MONTH=10
CONFIG_START_YEAR=2013
CONFIG_SYSTEM_I2CTOOL=y
+CONFIG_SYSTEM_TIME64=y
CONFIG_SYSTEM_USBMSC_CMD_STACKSIZE=2048
CONFIG_SYSTEM_USBMSC_DEVPATH1="/dev/mtdblock0p10"
CONFIG_SYSTEM_USBMSC_DEVPATH2="/dev/mtdblock1"
diff --git a/configs/lpcxpresso-lpc54628/README.txt b/configs/lpcxpresso-lpc54628/README.txt
index 31a65ff18e3d55f91c789ca21886b39b77317bb9..c9b3cbb52482e2eb5e83e566599099ec69f5e0df 100644
--- a/configs/lpcxpresso-lpc54628/README.txt
+++ b/configs/lpcxpresso-lpc54628/README.txt
@@ -24,6 +24,12 @@ README
device functionality
- 10/100Mbps Ethernet (RJ45 connector)
+CONTENTS
+========
+
+ - STATUS
+ - Configurations
+
STATUS
======
@@ -86,20 +92,15 @@ STATUS
of this writing. Also added the netnsh configuration will, eventually,
be used to test the Ethernet driver.
2018-01-01: There Ethernet driver appears to be fully functional although
- more testing is certainly needed. I believe that there is a memory
- corruption issue in the current configuration that cause problems
- occasionally. For example, after a longer Telnet session, I sometimes
- see the following DEBUGASSERT after exiting the session from the host:
-
- up_assert: Assertion failed at file:mm_heap/mm_free.c line: 129
-
- which is a clear indication heap corruption. Increasing the size of some
- stacks might correct this problem, but I have not yet experimented with
- that. I have not seen the problem in any other context.
+ more testing is certainly needed.
+ 2018-01-14: The basic SPI driver is code complete but still untested. It
+ is "basic" in the sense that it supports only polled mode (no DMA).
+ 2018-01-18: Added the lvgl configuration. See notes under "Configuration
+ Sub-directories" for additional status.
- There is still no support for the Accelerometer, SPIFI, or USB. There is a
- complete but not-yet-functional SD card. There is a partial SPI driver,
- but no on-board SPI devices to test it.
+ There is still no support for the Accelerometer, SPIFI, or USB. There is
+ a complete but not-yet-functional SD card driver and and tested SPI
+ driver. There are no on-board devices to support SPI testing.
Configurations
==============
@@ -157,7 +158,7 @@ Configurations
System Type -> Toolchain:
CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain
- Configuration sub-directories
+ Configuration Sub-directories
-----------------------------
fb:
@@ -230,6 +231,39 @@ Configurations
interrupts are not supported on P4. So polled mode only for this
puppy.
+ lvgl
+ ----
+ This is a demonstration of the LittlevGL graphics library running on
+ the NuttX frame buffer driver (as in the fb configuration). You can
+ find LittlevGL here:
+
+ https://littlevgl.com/
+ https://github.com/littlevgl
+
+ This configuration uses the LittlevGL demonstration at apps/examples/lvgldemo.
+
+ NOTES:
+
+ 1. The LittlevGL demonstration is quit large, due mostly to some large
+ graphic images. So memory is tight in the LPC54628's 512Kb FLASH. In
+ fact, if you disable optimization, the demo will not fit into FLASH
+ memory (at least not with debug output also enabled).
+
+ A longer term solution might load the large images into the abundant
+ SDRAM at runtime instead of linking it statically in FLASH.
+
+ STATUS:
+
+ 2018-01-18: The demo is basically function but has some issues:
+
+ a) The font is too big on the "Write" screen. They don't fit in on
+ the keyboard.
+ b) The "List" display is filled with a big box that says "Click a
+ button to copy its text to Text area." There are no buttons and
+ nothing to click on (maybe they are behind the big box?). This
+ may also be a font size issue.
+ c) The "Chart" display looks okay.
+
netnsh:
------
This is a special version of the NuttShell (nsh) configuration that is
@@ -265,7 +299,6 @@ Configurations
$ telnet fc00::42
-
nsh:
Configures the NuttShell (nsh) application located at examples/nsh.
@@ -477,4 +510,3 @@ Configurations
$ cd ~//nuttx
$ make
-
diff --git a/configs/lpcxpresso-lpc54628/fb/defconfig b/configs/lpcxpresso-lpc54628/fb/defconfig
index 2234418cfcc7429fd86517b85c2e825919e4ef97..afc8562724e24b91323164c3ae7793afbb4a6524 100644
--- a/configs/lpcxpresso-lpc54628/fb/defconfig
+++ b/configs/lpcxpresso-lpc54628/fb/defconfig
@@ -1,5 +1,4 @@
# CONFIG_ARCH_FPU is not set
-# CONFIG_EXAMPLES_TOUCHSCREEN_ARCHINIT is not set
CONFIG_ARCH_BOARD_LPCXPRESSO_LPC54628=y
CONFIG_ARCH_BOARD="lpcxpresso-lpc54628"
CONFIG_ARCH_CHIP_LPC54628=y
@@ -64,7 +63,7 @@ CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=4
CONFIG_RAM_SIZE=163840
-CONFIG_RAM_START=0x10000000
+CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_HPWORK=y
diff --git a/configs/lpcxpresso-lpc54628/include/board.h b/configs/lpcxpresso-lpc54628/include/board.h
index 2ca923462a6649c9f3d67c2287a2bd7dca98a54f..802d35575c02a7cac336753798a46905e7a8a0c7 100644
--- a/configs/lpcxpresso-lpc54628/include/board.h
+++ b/configs/lpcxpresso-lpc54628/include/board.h
@@ -306,7 +306,7 @@
/* Pin Disambiguation *******************************************************/
/* Flexcomm0/USART0
*
- * USART0 connects to the serial bridge on LPC4322JET100 and is typlical used
+ * USART0 connects to the serial bridge on LPC4322JET100 and is typically used
* for the serial console.
*
* BRIDGE_UART_RXD -> P0_29-ISP_FC0_RXD -> P0.29 GPIO_FC0_RXD_SDA_MOSI_2
@@ -316,6 +316,18 @@
#define GPIO_USART0_RXD (GPIO_FC0_RXD_SDA_MOSI_2 | GPIO_FILTER_OFF)
#define GPIO_USART0_TXD (GPIO_FC0_TXD_SCL_MISO_2 | GPIO_FILTER_OFF)
+/* An alternative for the serial console is a Arduino Uno compatible serial
+ * shield:
+ *
+ * Arduino Uno J13 Board Signal
+ * ----------- ------ ----------------
+ * D0 RX Pin 15 P3_26-FC4_RXD
+ * D1 TX Pin 13 P3_27-FC4_TXD
+ */
+
+#define GPIO_USART4_RXD (GPIO_FC4_RXD_SDA_MOSI_2 | GPIO_FILTER_OFF)
+#define GPIO_USART4_TXD (GPIO_FC4_TXD_SCL_MISO_2 | GPIO_FILTER_OFF)
+
/* Flexcomm2/I2C
*
* For I2C:
@@ -329,8 +341,14 @@
* Type I pins need for high speed I2C need:
* GPIO_FILTER_OFF + GPIO_I2C_FILTER_OFF + GPIO_I2CDRIVE_HIGH
*
- * The touchscreen controller is on I2C2: SCL P3.24, SDA P3.23. These are
- * both Type D/I pins.
+ * There are several on-board devices using I2C2:
+ *
+ * Codec I2C address: 0x1a
+ * Accel I2C address: 0x1d
+ * Touch panel I2C address: 0x38
+ *
+ * In addition, these same I2C2 pins are brought out through D14 and D15 of
+ * the Arduino Uno connector.
*/
#if defined(CONFIG_LPC54_I2C_FAST)
@@ -351,6 +369,35 @@
GPIO_FILTER_OFF | _I2CFILTER | \
_I2CDRIVE)
+/* Flexcomm2/SPI
+ *
+ * There are no SPI devices on board the LPCXpresso-LPC54628. SPI is
+ * available on the Arduino Uno compatible connector, however:
+ *
+ * Arduino Uno J9 Board Signal Pin Type
+ * ----------- ------ ---------------- ---------
+ * D10 SSEL Pin 15 P3_20-FC9_SCK Type D
+ * D11 MOSI Pin 13 P3_21-FC9_MOSI Type A
+ * D12 MISO Pin 11 P3_22-FC9_MISO Type A
+ * D13 SCK Pin 9 P3_30-FC9_SSELn0 Type D
+ *
+ * For SPI:
+ * Type A & D pins need:
+ * GPIO_PUSHPULL (on outputs) + GPIO_SLEW_STANDARD (Type D) +
+ * GPIO_FILTER_OFF
+ * GPIO_SLEW_FAST is optional for high data rates (Type D).
+ * Type I need:
+ * GPIO_I2C_FILTER_OFF + GPIO_I2CDRIVE_LOW + GPIO_FILTER_OFF +
+ * GPIO_I2CSLEW_GPIO
+ */
+
+#define GPIO_FC9_RXD_SDA_MOSI (GPIO_FC9_RXD_SDA_MOSI_1 | \
+ GPIO_PUSHPULL | GPIO_FILTER_OFF)
+#define GPIO_FC9_TXD_SCL_MISO (GPIO_FC9_TXD_SCL_MISO_1 | \
+ GPIO_FILTER_OFF)
+#define GPIO_FC9_SCK (GPIO_FC9_SCK_1 | GPIO_PUSHPULL | \
+ GPIO_SLEW_STANDARD | GPIO_FILTER_OFF)
+
/* SD/MMC
*
* P2_10-SD_CDn
@@ -412,7 +459,6 @@
* feature.
*/
-
#define GPIO_ENET_MDIO GPIO_ENET_MDIO_2 /* P4.16 */
#define GPIO_ENET_MDC GPIO_ENET_MDC_2 /* P4.15 */
diff --git a/configs/lpcxpresso-lpc54628/lvgl/defconfig b/configs/lpcxpresso-lpc54628/lvgl/defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..69faf20696f8095665da4850c30ab5acc4760338
--- /dev/null
+++ b/configs/lpcxpresso-lpc54628/lvgl/defconfig
@@ -0,0 +1,71 @@
+# CONFIG_ARCH_FPU is not set
+# CONFIG_LV_FONT_ANTIALIAS is not set
+CONFIG_ARCH_BOARD_LPCXPRESSO_LPC54628=y
+CONFIG_ARCH_BOARD="lpcxpresso-lpc54628"
+CONFIG_ARCH_CHIP_LPC54628=y
+CONFIG_ARCH_CHIP_LPC54XX=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH_STDARG_H=y
+CONFIG_ARCH="arm"
+CONFIG_BOARD_LOOPSPERMSEC=21082
+CONFIG_BUILTIN=y
+CONFIG_DRIVERS_VIDEO=y
+CONFIG_EXAMPLES_LVGLDEMO=y
+CONFIG_FS_PROCFS=y
+CONFIG_FT5X06_POLLMODE=y
+CONFIG_FT5X06_SINGLEPOINT=y
+CONFIG_FT5X06_SWAPXY=y
+CONFIG_GRAPHICS_LVGL=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_HOST_WINDOWS=y
+CONFIG_INPUT_FT5X06=y
+CONFIG_INPUT=y
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LIB_BOARDCTL=y
+CONFIG_LPC54_EMC_DYNAMIC_CS0_OFFSET=0x00080000
+CONFIG_LPC54_EMC_DYNAMIC_CS0_SIZE=0x00f80000
+CONFIG_LPC54_EMC_DYNAMIC_CS0=y
+CONFIG_LPC54_EMC=y
+CONFIG_LPC54_GPIOIRQ=y
+CONFIG_LPC54_I2C2_MASTER=y
+CONFIG_LPC54_LCD_BGR=y
+CONFIG_LPC54_LCD_BPP16_565=y
+CONFIG_LPC54_LCD_HBACKPORCH=43
+CONFIG_LPC54_LCD_HFRONTPORCH=8
+CONFIG_LPC54_LCD_VBACKPORCH=12
+CONFIG_LPC54_LCD_VFRONTPORCH=4
+CONFIG_LPC54_LCD_VPULSE=10
+CONFIG_LPC54_LCD_VRAMBASE=0xa0000000
+CONFIG_LPC54_LCD=y
+CONFIG_LPC54_USART0=y
+CONFIG_LV_HOR_RES=480
+CONFIG_LV_VER_RES=272
+CONFIG_MAX_TASKS=16
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_MM_REGIONS=2
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_PREALLOC_MQ_MSGS=4
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_PREALLOC_WDOGS=4
+CONFIG_RAM_SIZE=163840
+CONFIG_RAM_START=0x20000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_HPWORK=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_TASK_NAME_SIZE=32
+CONFIG_USART0_SERIAL_CONSOLE=y
+CONFIG_USE_LV_FONT_DEJAVU_40_CYRILLIC=y
+CONFIG_USE_LV_FONT_DEJAVU_40_LATIN_EXT_A=y
+CONFIG_USE_LV_FONT_DEJAVU_40_LATIN_EXT_B=y
+CONFIG_USE_LV_FONT_DEJAVU_40_SUP=y
+CONFIG_USE_LV_FONT_SYMBOL_40_BASIC=y
+CONFIG_USE_LV_FONT_SYMBOL_40_FEEDBACK=y
+CONFIG_USE_LV_FONT_SYMBOL_40_FILE=y
+CONFIG_USER_ENTRYPOINT="lvgldemo_main"
+CONFIG_VIDEO_FB=y
+CONFIG_WDOG_INTRESERVE=0
diff --git a/configs/lpcxpresso-lpc54628/netnsh/defconfig b/configs/lpcxpresso-lpc54628/netnsh/defconfig
index 89836e6010933641640224f819f5eab7c76a3939..b84ff13d81e9d022fb5af77364cddfb053d62d73 100644
--- a/configs/lpcxpresso-lpc54628/netnsh/defconfig
+++ b/configs/lpcxpresso-lpc54628/netnsh/defconfig
@@ -55,7 +55,7 @@ CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=4
CONFIG_RAM_SIZE=163840
-CONFIG_RAM_START=0x10000000
+CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_HPWORK=y
diff --git a/configs/lpcxpresso-lpc54628/nsh/defconfig b/configs/lpcxpresso-lpc54628/nsh/defconfig
index 70d2e780688fc5bd250aec768fc137873f1034a3..bdcaa769d364502f108e762884ac46bb462973aa 100644
--- a/configs/lpcxpresso-lpc54628/nsh/defconfig
+++ b/configs/lpcxpresso-lpc54628/nsh/defconfig
@@ -42,7 +42,7 @@ CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=4
CONFIG_RAM_SIZE=163840
-CONFIG_RAM_START=0x10000000
+CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_RTC_ALARM=y
diff --git a/configs/lpcxpresso-lpc54628/nxwm/defconfig b/configs/lpcxpresso-lpc54628/nxwm/defconfig
index 4c2f839ee1a434daa462dc0351ee6ddbeb9a1aaa..6bcffd4a4b5939dfcd434f23fcebba045ba1eb2f 100644
--- a/configs/lpcxpresso-lpc54628/nxwm/defconfig
+++ b/configs/lpcxpresso-lpc54628/nxwm/defconfig
@@ -2,7 +2,6 @@
# CONFIG_NX_DISABLE_16BPP is not set
# CONFIG_NXFONTS_DISABLE_16BPP is not set
# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set
-# CONFIG_NXWM_TOUCHSCREEN_DEVINIT is not set
CONFIG_ARCH_BOARD_LPCXPRESSO_LPC54628=y
CONFIG_ARCH_BOARD="lpcxpresso-lpc54628"
CONFIG_ARCH_CHIP_LPC54628=y
@@ -11,7 +10,6 @@ CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH_STDARG_H=y
CONFIG_ARCH="arm"
-CONFIG_BOARD_INITIALIZE=y
CONFIG_BOARD_LOOPSPERMSEC=21082
CONFIG_BUILTIN=y
CONFIG_FAT_LCNAMES=y
@@ -87,7 +85,7 @@ CONFIG_NXWM=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=8
CONFIG_RAM_SIZE=163840
-CONFIG_RAM_START=0x10000000
+CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_HPWORK=y
diff --git a/configs/lpcxpresso-lpc54628/scripts/flash.ld b/configs/lpcxpresso-lpc54628/scripts/flash.ld
index fc09e2fffc5a443499319069f3d9fd19abe8470d..42a0396af854c0327936d8bb61a6260f31f9d852 100644
--- a/configs/lpcxpresso-lpc54628/scripts/flash.ld
+++ b/configs/lpcxpresso-lpc54628/scripts/flash.ld
@@ -33,7 +33,7 @@
*
****************************************************************************/
-/* The LPC54628 on the LPCXPressio has 512Kb of FLASH at address 0x0000:0000.
+/* The LPC54628 on the LPCXPresso has 512Kb of FLASH at address 0x0000:0000.
* The Main SRAM is comprised of up to a total 160 KB of contiguous, on-chip
* static RAM memory beginning at address 0x2000:0000 (this is in addition
* to SRAMX aso the total device SRAM can be up to 200 KB).
diff --git a/configs/lpcxpresso-lpc54628/src/lpc54_ft5x06.c b/configs/lpcxpresso-lpc54628/src/lpc54_ft5x06.c
index 162089b190bb2b3382358c7dc2e3039ff2830610..8893f08ff6532d4306f6851e1dc2bfe4759052dc 100644
--- a/configs/lpcxpresso-lpc54628/src/lpc54_ft5x06.c
+++ b/configs/lpcxpresso-lpc54628/src/lpc54_ft5x06.c
@@ -245,25 +245,4 @@ int lpc54_ft5x06_register(void)
return OK;
}
-/****************************************************************************
- * Name: board_tsc_setup and board_tsc_teardown
- *
- * Description:
- * Stubs for expected interfaces. This implementation does not permit the
- * application to mange the touch screen controller.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_BOARDCTL_TSCTEST
-int board_tsc_setup(int minor)
-{
- DEBUGASSERT(minor == 0);
- return OK;
-}
-
-void board_tsc_teardown(void)
-{
-}
-#endif
-
#endif /* HAVE_FT5x06*/
diff --git a/configs/mcb1700/src/lpc17_bringup.c b/configs/mcb1700/src/lpc17_bringup.c
index 6b5da0d75eebd8b6713d851e6499e2842146fcd1..8e87b8592724183e773cd10ca045b5e8f3f12620 100644
--- a/configs/mcb1700/src/lpc17_bringup.c
+++ b/configs/mcb1700/src/lpc17_bringup.c
@@ -45,6 +45,7 @@
#include
#include
+#include
#include
#include
#include
@@ -301,9 +302,9 @@ static int nsh_usbhostinitialize(void)
syslog(LOG_ERR, "ERROR: Start nsh_waiter\n");
- pid = task_create("usbhost", CONFIG_MCB1700_USBHOST_PRIO,
- CONFIG_MCB1700_USBHOST_STACKSIZE,
- (main_t)nsh_waiter, (FAR char * const *)NULL);
+ pid = kthread_create("usbhost", CONFIG_MCB1700_USBHOST_PRIO,
+ CONFIG_MCB1700_USBHOST_STACKSIZE,
+ (main_t)nsh_waiter, (FAR char * const *)NULL);
return pid < 0 ? -ENOEXEC : OK;
}
diff --git a/configs/mcu123-lpc214x/src/lpc2148_spi1.c b/configs/mcu123-lpc214x/src/lpc2148_spi1.c
index a5001a5a0c26fff96ee6dee3e704891695b1d4e2..8a4675fc9c7bd6ff6e93175a270c9996b97ec244 100644
--- a/configs/mcu123-lpc214x/src/lpc2148_spi1.c
+++ b/configs/mcu123-lpc214x/src/lpc2148_spi1.c
@@ -525,7 +525,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
* Description:
* Initialize the selected SPI port
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/configs/mikroe-stm32f4/fulldemo/defconfig b/configs/mikroe-stm32f4/fulldemo/defconfig
index 0896fb141259e03b54aaff1536d048b323e03b03..dab8c12914e617652f3f9f8f2f5d0d14025e624f 100644
--- a/configs/mikroe-stm32f4/fulldemo/defconfig
+++ b/configs/mikroe-stm32f4/fulldemo/defconfig
@@ -45,6 +45,7 @@ CONFIG_INTELHEX_BINARY=y
CONFIG_LCD_MIO283QT2=y
CONFIG_LCD=y
CONFIG_LIBC_PERROR_STDOUT=y
+CONFIG_LIB_BOARDCTL=y
CONFIG_LIBC_STRERROR=y
CONFIG_M25P_MANUFACTURER=0x1C
CONFIG_M25P_MEMORY_TYPE=0x31
diff --git a/configs/mikroe-stm32f4/src/mikroe-stm32f4.h b/configs/mikroe-stm32f4/src/mikroe-stm32f4.h
index 4b8bcc3dafac837ab50a8436c82013b36cd26d17..0df889c4246807872e7c8cfbc0497920cd18b24c 100644
--- a/configs/mikroe-stm32f4/src/mikroe-stm32f4.h
+++ b/configs/mikroe-stm32f4/src/mikroe-stm32f4.h
@@ -1,7 +1,7 @@
/****************************************************************************************************
* configs/mikroe-stm32f4/src/mikroe-stm32f4.h
*
- * Copyright (C) 2011-2013, 2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011-2013, 2016, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -218,7 +218,7 @@ void weak_function stm32_spidev_initialize(void);
* Name: stm32_usbinitialize
*
* Description:
- * Called from stm32_usbinitialize very early in inialization to setup USB-related
+ * Called from stm32_usbinitialize very early in initialization to setup USB-related
* GPIO pins for the Mikroe-stm32f4 board.
*
****************************************************************************************************/
@@ -227,13 +227,13 @@ void weak_function stm32_spidev_initialize(void);
void weak_function stm32_usbinitialize(void);
#endif
-/************************************************************************************
+/****************************************************************************************************
* Name: stm32_pwm_setup
*
* Description:
* Initialize PWM and register the PWM device.
*
- ************************************************************************************/
+ ****************************************************************************************************/
#ifdef CONFIG_PWM
int stm32_pwm_setup(void);
@@ -252,13 +252,13 @@ int stm32_pwm_setup(void);
# error "The Mikroe-STM32F4 board does not support HOST OTG, only device!"
#endif
-/****************************************************************************
+/****************************************************************************************************
* Name: stm32_qencoder_initialize
*
* Description:
* Initialize and register a qencoder
*
- ****************************************************************************/
+ ****************************************************************************************************/
#ifdef CONFIG_SENSORS_QENCODER
int stm32_qencoder_initialize(FAR const char *devpath, int timer);
@@ -277,6 +277,26 @@ int stm32_qencoder_initialize(FAR const char *devpath, int timer);
void stm32_lcdinitialize(void);
#endif
+/****************************************************************************************************
+ * Name: stm32_tsc_setup
+ *
+ * Description:
+ * This function is called by board-bringup logic to configure the touchscreen device. This
+ * function will register the driver as /dev/inputN where N is the minor device number.
+ *
+ * Input Parameters:
+ * minor - The input device minor number
+ *
+ * Returned Value:
+ * Zero is returned on success. Otherwise, a negated errno value is returned to indicate the
+ * nature of the failure.
+ *
+ ****************************************************************************************************/
+
+#ifdef CONFIG_INPUT
+int stm32_tsc_setup(int minor);
+#endif
+
/****************************************************************************************************
* Name: up_vs1053initialize
*
diff --git a/configs/mikroe-stm32f4/src/stm32_appinit.c b/configs/mikroe-stm32f4/src/stm32_appinit.c
index 134f819fc4ccffe6c1dca7850a9a39f06b117daa..18028def31237923f4f96907ec36b20566e1e1aa 100644
--- a/configs/mikroe-stm32f4/src/stm32_appinit.c
+++ b/configs/mikroe-stm32f4/src/stm32_appinit.c
@@ -1,7 +1,7 @@
/****************************************************************************
* config/mikroe_stm32f4/src/stm32_appinit.c
*
- * Copyright (C) 2012-2013, 2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012-2013, 2016, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -350,6 +350,16 @@ int board_app_initialize(uintptr_t arg)
}
#endif
+#ifdef CONFIG_INPUT
+ /* Initialize the touchscreen */
+
+ ret = stm32_tsc_setup(0);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret);
+ }
+#endif
+
#ifdef CONFIG_PWM
/* Initialize PWM and register the PWM device. */
diff --git a/configs/mikroe-stm32f4/src/stm32_pm.c b/configs/mikroe-stm32f4/src/stm32_pm.c
index c5f89f50abbdb9f9655bdd3bb187273fa138925b..4ff3d14badd7c162458bcabd48b4cd1f75dad955 100644
--- a/configs/mikroe-stm32f4/src/stm32_pm.c
+++ b/configs/mikroe-stm32f4/src/stm32_pm.c
@@ -78,10 +78,10 @@
* *before* any other device drivers are initialized (since they may
* attempt to register with the power management subsystem).
*
- * Input parameters:
+ * Input Parameters:
* None.
*
- * Returned value:
+ * Returned Value:
* None.
*
****************************************************************************/
diff --git a/configs/mikroe-stm32f4/src/stm32_touchscreen.c b/configs/mikroe-stm32f4/src/stm32_touchscreen.c
index 8dfb259f48b637349fffbaed5eccfbbc7221db24..7273285db9640ebecbd272b21ec31d3831d17fd4 100644
--- a/configs/mikroe-stm32f4/src/stm32_touchscreen.c
+++ b/configs/mikroe-stm32f4/src/stm32_touchscreen.c
@@ -1328,7 +1328,7 @@ errout:
}
/****************************************************************************
- * Name:tc_ioctl
+ * Name: tc_ioctl
****************************************************************************/
static int tc_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
@@ -1474,13 +1474,12 @@ errout:
************************************************************************************/
/****************************************************************************
- * Name: board_tsc_setup
+ * Name: stm32_tsc_setup
*
* Description:
- * Each board that supports a touchscreen device must provide this function.
- * This function is called by application-specific, setup logic to
- * configure the touchscreen device. This function will register the driver
- * as /dev/inputN where N is the minor device number.
+ * This function is called by board-bringup logic to configure the
+ * touchscreen device. This function will register the driver as
+ * /dev/inputN where N is the minor device number.
*
* Input Parameters:
* minor - The input device minor number
@@ -1491,7 +1490,7 @@ errout:
*
****************************************************************************/
-int board_tsc_setup(int minor)
+int stm32_tsc_setup(int minor)
{
FAR struct tc_dev_s *priv;
char devname[DEV_NAMELEN];
@@ -1583,25 +1582,4 @@ errout_with_priv:
return ret;
}
-/****************************************************************************
- * Name: board_tsc_teardown
- *
- * Description:
- * Each board that supports a touchscreen device must provide this function.
- * This function is called by application-specific, setup logic to
- * uninitialize the touchscreen device.
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * None.
- *
- ****************************************************************************/
-
-void board_tsc_teardown(void)
-{
- /* Need to unregister the /dev/inputN device here. */
-}
-
#endif /* CONFIG_INPUT */
diff --git a/configs/mikroe-stm32f4/src/stm32_usb.c b/configs/mikroe-stm32f4/src/stm32_usb.c
index 8047a631fd3c14316b00b9faf356aeef6baa58f2..e242c690604b2bf28f94a31e6e46e590ed7b6912 100644
--- a/configs/mikroe-stm32f4/src/stm32_usb.c
+++ b/configs/mikroe-stm32f4/src/stm32_usb.c
@@ -47,6 +47,7 @@
#include
#include
+#include
#include
#include
#include
@@ -208,9 +209,9 @@ int stm32_usbhost_initialize(void)
uinfo("Start usbhost_waiter\n");
- pid = task_create("usbhost", CONFIG_USBHOST_DEFPRIO,
- CONFIG_USBHOST_STACKSIZE,
- (main_t)usbhost_waiter, (FAR char * const *)NULL);
+ pid = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO,
+ CONFIG_USBHOST_STACKSIZE,
+ (main_t)usbhost_waiter, (FAR char * const *)NULL);
return pid < 0 ? -ENOEXEC : OK;
}
@@ -271,11 +272,11 @@ void stm32_usbhost_vbusdrive(int iface, bool enable)
* Setup to receive an interrupt-level callback if an overcurrent condition is
* detected.
*
- * Input Parameter:
+ * Input Parameters:
* handler - New overcurrent interrupt handler
* arg - The argument provided for the interrupt handler
*
- * Returned value:
+ * Returned Value:
* Zero (OK) is returned on success. Otherwise, a negated errno value is returned
* to indicate the nature of the failure.
*
diff --git a/configs/nucleo-144/src/stm32_usb.c b/configs/nucleo-144/src/stm32_usb.c
index 597570ae1831bfccbf80307475aca496b91f1549..82118d87fac40f578fd190bb00457339c6ab8d61 100644
--- a/configs/nucleo-144/src/stm32_usb.c
+++ b/configs/nucleo-144/src/stm32_usb.c
@@ -48,6 +48,7 @@
#include
#include
+#include
#include
#include
#include
@@ -239,9 +240,9 @@ int stm32_usbhost_initialize(void)
uinfo("Start usbhost_waiter\n");
- pid = task_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO,
- CONFIG_STM32F4DISCO_USBHOST_STACKSIZE,
- (main_t)usbhost_waiter, (FAR char * const *)NULL);
+ pid = kthread_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO,
+ CONFIG_STM32F4DISCO_USBHOST_STACKSIZE,
+ (main_t)usbhost_waiter, (FAR char * const *)NULL);
return pid < 0 ? -ENOEXEC : OK;
}
@@ -293,11 +294,11 @@ void stm32_usbhost_vbusdrive(int iface, bool enable)
* Setup to receive an interrupt-level callback if an overcurrent condition is
* detected.
*
- * Input Parameter:
+ * Input Parameters:
* handler - New overcurrent interrupt handler
* arg - The argument provided for the interrupt handler
*
- * Returned value:
+ * Returned Value:
* Zero (OK) is returned on success. Otherwise, a negated errno value is returned
* to indicate the nature of the failure.
*
diff --git a/configs/nucleo-f072rb/src/stm32_userleds.c b/configs/nucleo-f072rb/src/stm32_userleds.c
index 0b967fc662dc8f1dee2b59d4238f767447d4d1e6..8febc96b4676015fc611c461714c277fb41c7019 100644
--- a/configs/nucleo-f072rb/src/stm32_userleds.c
+++ b/configs/nucleo-f072rb/src/stm32_userleds.c
@@ -181,9 +181,9 @@ void board_userled_initialize(void)
void board_userled(int led, bool ledon)
{
- if (led == 1)
+ if (led == BOARD_LD2)
{
- stm32f0_gpiowrite(GPIO_LD2, ldeon);
+ stm32f0_gpiowrite(GPIO_LD2, ledon);
}
}
@@ -193,10 +193,7 @@ void board_userled(int led, bool ledon)
void board_userled_all(uint8_t ledset)
{
- if (led == 1)
- {
- stm32f0_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0);
- }
+ stm32f0_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0);
}
/****************************************************************************
diff --git a/configs/nucleo-f091rc/src/stm32_userleds.c b/configs/nucleo-f091rc/src/stm32_userleds.c
index b13c1882b73b76baab6f2601a0138b84e2b97341..f62e84a30e44464c171f3c8af2adf8a538325f61 100644
--- a/configs/nucleo-f091rc/src/stm32_userleds.c
+++ b/configs/nucleo-f091rc/src/stm32_userleds.c
@@ -181,9 +181,9 @@ void board_userled_initialize(void)
void board_userled(int led, bool ledon)
{
- if (led == 1)
+ if (led == BOARD_LD2)
{
- stm32f0_gpiowrite(GPIO_LD2, ldeon);
+ stm32f0_gpiowrite(GPIO_LD2, ledon);
}
}
@@ -193,10 +193,7 @@ void board_userled(int led, bool ledon)
void board_userled_all(uint8_t ledset)
{
- if (led == 1)
- {
- stm32f0_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0);
- }
+ stm32f0_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0);
}
/****************************************************************************
diff --git a/configs/nucleo-f303re/src/nucleo-f303re.h b/configs/nucleo-f303re/src/nucleo-f303re.h
index e11495f5f151437efce03975ab336fe790f8ece2..f5ee979d7aa1db82099bffdcbb8c4106b1d53b15 100644
--- a/configs/nucleo-f303re/src/nucleo-f303re.h
+++ b/configs/nucleo-f303re/src/nucleo-f303re.h
@@ -145,7 +145,7 @@ void weak_function stm32_spidev_initialize(void);
* devpath - The full path to the timer device. This should be of the form /dev/timer0
* timer - The timer's number.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
diff --git a/configs/nucleo-f303re/src/stm32_timer.c b/configs/nucleo-f303re/src/stm32_timer.c
index fd82bb6d4f7d64ab5a99ae7a421002846ea858e8..a13edd2943c7fa8db1b28d52c3ed7ba013c3a636 100644
--- a/configs/nucleo-f303re/src/stm32_timer.c
+++ b/configs/nucleo-f303re/src/stm32_timer.c
@@ -68,7 +68,7 @@
* form /dev/timer0
* timer - The timer's number.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
diff --git a/configs/nucleo-f334r8/src/nucleo-f334r8.h b/configs/nucleo-f334r8/src/nucleo-f334r8.h
index 4b2929f8aac18d730712c67494d713b208b11115..463f20cb24de4401d8cb516a9b5ddd52a5d272c3 100644
--- a/configs/nucleo-f334r8/src/nucleo-f334r8.h
+++ b/configs/nucleo-f334r8/src/nucleo-f334r8.h
@@ -132,7 +132,7 @@ void weak_function stm32_spidev_initialize(void);
* devpath - The full path to the timer device. This should be of the form /dev/timer0
* timer - The timer's number.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
diff --git a/configs/nucleo-f410rb/src/stm32_userleds.c b/configs/nucleo-f410rb/src/stm32_userleds.c
index bdd1be2b181bb4eef7458dca436be37f54ba6432..fb283a50cc7f4e2120d114178c0411e2423dadb8 100644
--- a/configs/nucleo-f410rb/src/stm32_userleds.c
+++ b/configs/nucleo-f410rb/src/stm32_userleds.c
@@ -181,9 +181,9 @@ void board_userled_initialize(void)
void board_userled(int led, bool ledon)
{
- if (led == 1)
+ if (led == BOARD_LD2)
{
- stm32_gpiowrite(GPIO_LD2, ldeon);
+ stm32_gpiowrite(GPIO_LD2, ledon);
}
}
@@ -193,10 +193,7 @@ void board_userled(int led, bool ledon)
void board_userled_all(uint8_t ledset)
{
- if (led == 1)
- {
- stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0);
- }
+ stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0);
}
/****************************************************************************
diff --git a/configs/nucleo-l432kc/README.txt b/configs/nucleo-l432kc/README.txt
index 33ebc530cdb55df93560e176baf4bc365814a71e..a922e17638609d388c4b9d751f521e40b7f96645 100644
--- a/configs/nucleo-l432kc/README.txt
+++ b/configs/nucleo-l432kc/README.txt
@@ -230,12 +230,10 @@ NuttX EABI "buildroot" Toolchain
1. You must have already configured Nuttx in /nuttx.
- $ (cd tools; ./configure.sh nucleo-f4x1re/f401-nsh)
+ $ tools/configure.sh nucleo-l432kc/nsh
$ make qconfig
$ V=1 make context all 2>&1 | tee mout
- Use the f411-nsh configuration if you have the Nucleo-F411RE board.
-
2. Download the latest buildroot package into
3. unpack the buildroot tarball. The resulting directory may
@@ -298,14 +296,13 @@ NXFLAT Toolchain
mbed
====
- The Nucleo-F401RE includes boot loader from mbed:
+ The Nucleo-L432KC includes boot loader from mbed:
- https://mbed.org/platforms/ST-Nucleo-F401RE/
https://mbed.org/handbook/Homepage
Using the mbed loader:
- 1. Connect the Nucleo-F4x1RE to the host PC using the USB connector.
+ 1. Connect the Nucleo-L432kc to the host PC using the USB connector.
2. A new file system will appear called NUCLEO; open it with Windows
Explorer (assuming that you are using Windows).
3. Drag and drop nuttx.bin into the MBED window. This will load the
@@ -322,9 +319,9 @@ Hardware
LEDs
----
- The Nucleo F401RE and Nucleo F411RE provide a single user LED, LD2. LD2
+ The Nucleo L432KC provides a single user LED, LD2. LD2
is the green LED connected to Arduino signal D13 corresponding to MCU I/O
- PA5 (pin 21) or PB13 (pin 34) depending on the STM32target.
+ PB3 (pin 26).
- When the I/O is HIGH value, the LED is on.
- When the I/O is LOW, the LED is off.
@@ -367,7 +364,7 @@ Serial Consoles
TTL to RS-232 converter connection:
- Nucleo CN10 STM32F4x1RE
+ Nucleo CN10 STM32L432KC
----------- ------------
Pin 21 PA9 USART1_RX *Warning you make need to reverse RX/TX on
Pin 33 PA10 USART1_TX some RS-232 converters
@@ -399,7 +396,7 @@ Serial Consoles
TTL to RS-232 converter connection:
- Nucleo CN9 STM32F4x1RE
+ Nucleo CN9 STM32L432KC
----------- ------------
Pin 1 PA3 USART2_RX *Warning you make need to reverse RX/TX on
Pin 2 PA2 USART2_TX some RS-232 converters
@@ -457,7 +454,7 @@ Configurations
nsh:
---------
Configures the NuttShell (nsh) located at apps/examples/nsh for the
- Nucleo-F401RE board. The Configuration enables the serial interfaces
+ Nucleo-L432KC board. The Configuration enables the serial interfaces
on UART2. Support for builtin applications is enabled, but in the base
configuration no builtin applications are selected (see NOTES below).
@@ -484,7 +481,7 @@ Configurations
Consoles). I have been using a TTL-to-RS-232 converter connected
as shown below:
- Nucleo CN10 STM32F4x1RE
+ Nucleo CN10 STM32L432KC
----------- ------------
Pin 21 PA9 USART1_RX *Warning you make need to reverse RX/TX on
Pin 33 PA10 USART1_TX some RS-232 converters
diff --git a/configs/nucleo-l432kc/include/board.h b/configs/nucleo-l432kc/include/board.h
index cbec4b9c37ad2a6556734ee179c861d8d1c911c9..041a755787c970dc5fbd56e4ace759f3f8d32086 100644
--- a/configs/nucleo-l432kc/include/board.h
+++ b/configs/nucleo-l432kc/include/board.h
@@ -45,7 +45,9 @@
# include
#endif
+#ifdef __KERNEL__
#include
+#endif
/************************************************************************************
* Pre-processor Definitions
@@ -144,9 +146,9 @@
/* LEDs
*
- * The Nucleo l476RG board provides a single user LED, LD2. LD2
- * is the green LED connected to Arduino signal D13 corresponding to MCU I/O
- * PA5 (pin 21) or PB13 (pin 34) depending on the STM32 target.
+ * The Nucleo l432kc board provides a single user LED, LD2. LD2
+ * is the green LED connected to Arduino signal D13 corresponding to
+ * MCU I/O PB3 (pin 26).
*
* - When the I/O is HIGH value, the LED is on.
* - When the I/O is LOW, the LED is off.
@@ -264,4 +266,4 @@ void stm32l4_board_initialize(void);
#endif
#endif /* __ASSEMBLY__ */
-#endif /* __CONFIGS_NUCLEO_F476RG_INCLUDE_BOARD_H */
+#endif /* __CONFIGS_NUCLEO_L432KC_INCLUDE_BOARD_H */
diff --git a/configs/nucleo-l432kc/src/nucleo-l432kc.h b/configs/nucleo-l432kc/src/nucleo-l432kc.h
index a9ce4bee64732f57156a61bfb4d0a810181ff83f..e5c34816bb903768741bcd8d82cb928dfac643f3 100644
--- a/configs/nucleo-l432kc/src/nucleo-l432kc.h
+++ b/configs/nucleo-l432kc/src/nucleo-l432kc.h
@@ -77,7 +77,7 @@
#endif
/* LED. User LD2: the green LED is a user LED connected to Arduino signal D13
- * corresponding to MCU I/O PA5 (pin 21) or PB13 (pin 34) depending on the STM32
+ * corresponding to MCU I/O PB3 (pin 26)
* target.
*
* - When the I/O is HIGH value, the LED is on.
@@ -85,8 +85,9 @@
*/
#define GPIO_LD2 \
- (GPIO_PORTA | GPIO_PIN5 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \
+ (GPIO_PORTB | GPIO_PIN3 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \
GPIO_SPEED_50MHz)
+#define LED_DRIVER_PATH "/dev/userleds"
/* Buttons
*
diff --git a/configs/nucleo-l432kc/src/stm32_appinit.c b/configs/nucleo-l432kc/src/stm32_appinit.c
index 0422e0cf20c155114cf3dfdbf69096602994fcdf..d3a725c776abff37878c3938ea7d364dad017509 100644
--- a/configs/nucleo-l432kc/src/stm32_appinit.c
+++ b/configs/nucleo-l432kc/src/stm32_appinit.c
@@ -51,6 +51,7 @@
#include
#include
#include
+#include
#include
#include
@@ -135,6 +136,16 @@ int board_app_initialize(uintptr_t arg)
}
#endif
+#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER)
+ /* Register the LED driver */
+
+ ret = userled_lower_initialize(LED_DRIVER_PATH);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret);
+ }
+#endif
+
#ifdef HAVE_RTC_DRIVER
/* Instantiate the STM32L4 lower-half RTC driver */
diff --git a/configs/nucleo-l432kc/src/stm32_timer.c b/configs/nucleo-l432kc/src/stm32_timer.c
index 8750ba76b9f2f35b299e03f00ebf9ce6b9c2a142..f7183936d66c1e1af31fb7a1ce20ab44ca40389e 100644
--- a/configs/nucleo-l432kc/src/stm32_timer.c
+++ b/configs/nucleo-l432kc/src/stm32_timer.c
@@ -68,7 +68,7 @@
* form /dev/timer0
* timer - The timer's number.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
diff --git a/configs/nucleo-l432kc/src/stm32_userleds.c b/configs/nucleo-l432kc/src/stm32_userleds.c
index 0ff3ce66c866d01aafa3b7c3954b02f0be645bc1..8dec7afee3c4e56c3dfb3b375d864a37cd7d649f 100644
--- a/configs/nucleo-l432kc/src/stm32_userleds.c
+++ b/configs/nucleo-l432kc/src/stm32_userleds.c
@@ -181,7 +181,7 @@ void board_userled_initialize(void)
void board_userled(int led, bool ledon)
{
- if (led == 1)
+ if (led == BOARD_LD2)
{
stm32l4_gpiowrite(GPIO_LD2, ledon);
}
@@ -193,10 +193,7 @@ void board_userled(int led, bool ledon)
void board_userled_all(uint8_t ledset)
{
- if (led == 1)
- {
- stm32l4_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0);
- }
+ stm32l4_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0);
}
/****************************************************************************
diff --git a/configs/nucleo-l452re/src/stm32_userleds.c b/configs/nucleo-l452re/src/stm32_userleds.c
index 77ba277c34285a1f699aad01fc3602ea17b185de..4ed1b8d807e8c584111cfc0d193d08034fe334e0 100644
--- a/configs/nucleo-l452re/src/stm32_userleds.c
+++ b/configs/nucleo-l452re/src/stm32_userleds.c
@@ -181,9 +181,9 @@ void board_userled_initialize(void)
void board_userled(int led, bool ledon)
{
- if (led == 1)
+ if (led == BOARD_LD2)
{
- stm32l4_gpiowrite(GPIO_LD2, ldeon);
+ stm32l4_gpiowrite(GPIO_LD2, ledon);
}
}
@@ -193,10 +193,7 @@ void board_userled(int led, bool ledon)
void board_userled_all(uint8_t ledset)
{
- if (led == 1)
- {
- stm32l4_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0);
- }
+ stm32l4_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0);
}
/****************************************************************************
diff --git a/configs/nucleo-l476rg/src/stm32_timer.c b/configs/nucleo-l476rg/src/stm32_timer.c
index 2d6f83835ee1e99656c2a0ff218cc5ae6a25ffe7..9f578b5bc6b2459d5bc83e6d599f574d1b36936e 100644
--- a/configs/nucleo-l476rg/src/stm32_timer.c
+++ b/configs/nucleo-l476rg/src/stm32_timer.c
@@ -68,7 +68,7 @@
* form /dev/timer0
* timer - The timer's number.
*
- * Returned Values:
+ * Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
diff --git a/configs/nucleo-l476rg/src/stm32_userleds.c b/configs/nucleo-l476rg/src/stm32_userleds.c
index 53d9193230ab20d528488f0f83a8e17c20e8f764..9464a6ad341153563fa96f43c7c44ec7198ce71e 100644
--- a/configs/nucleo-l476rg/src/stm32_userleds.c
+++ b/configs/nucleo-l476rg/src/stm32_userleds.c
@@ -172,7 +172,7 @@ void board_userled_initialize(void)
{
/* Configure LD2 GPIO for output */
- stm32_configgpio(GPIO_LD2);
+ stm32l4_configgpio(GPIO_LD2);
}
/****************************************************************************
@@ -181,9 +181,9 @@ void board_userled_initialize(void)
void board_userled(int led, bool ledon)
{
- if (led == 1)
+ if (led == BOARD_LD2)
{
- stm32_gpiowrite(GPIO_LD2, ldeon);
+ stm32l4_gpiowrite(GPIO_LD2, ledon);
}
}
@@ -193,10 +193,7 @@ void board_userled(int led, bool ledon)
void board_userled_all(uint8_t ledset)
{
- if (led == 1)
- {
- stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0);
- }
+ stm32l4_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0);
}
/****************************************************************************
diff --git a/configs/nucleo-l496zg/src/stm32_usb.c b/configs/nucleo-l496zg/src/stm32_usb.c
index 505d78445a41d2c9223138d853ad3b2ed9bdd0ce..a5a0937b05922867c45a5ee2c5826a92a4ca4f80 100644
--- a/configs/nucleo-l496zg/src/stm32_usb.c
+++ b/configs/nucleo-l496zg/src/stm32_usb.c
@@ -48,6 +48,7 @@
#include
#include
+#include
#include
#include
#include
@@ -239,9 +240,9 @@ int stm32_usbhost_initialize(void)
uinfo("Start usbhost_waiter\n");
- pid = task_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO,
- CONFIG_STM32F4DISCO_USBHOST_STACKSIZE,
- (main_t)usbhost_waiter, (FAR char * const *)NULL);
+ pid = kthread_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO,
+ CONFIG_STM32F4DISCO_USBHOST_STACKSIZE,
+ (main_t)usbhost_waiter, (FAR char * const *)NULL);
return pid < 0 ? -ENOEXEC : OK;
}
@@ -293,11 +294,11 @@ void stm32_usbhost_vbusdrive(int iface, bool enable)
* Setup to receive an interrupt-level callback if an overcurrent condition is
* detected.
*
- * Input Parameter:
+ * Input Parameters:
* handler - New overcurrent interrupt handler
* arg - The argument provided for the interrupt handler
*
- * Returned value:
+ * Returned Value:
* Zero (OK) is returned on success. Otherwise, a negated errno value is returned
* to indicate the nature of the failure.
*
diff --git a/configs/olimex-lpc-h3131/include/board.h b/configs/olimex-lpc-h3131/include/board.h
index a411461668bda0a948d5d7c2506afe113ba069c1..2b9ace582b0a93c87d4292eaa94da13f71df3f23 100644
--- a/configs/olimex-lpc-h3131/include/board.h
+++ b/configs/olimex-lpc-h3131/include/board.h
@@ -174,11 +174,11 @@ extern "C"
* Setup to receive an interrupt-level callback if an overcurrent condition is
* detected.
*
- * Input parameter:
+ * Input Parameters:
* handler - New overcurrent interrupt handler
* arg - The argument that will accompany the interrupt
*
- * Returned value:
+ * Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on failure.
*
************************************************************************************/
diff --git a/configs/olimex-lpc-h3131/src/lpc31_usbhost.c b/configs/olimex-lpc-h3131/src/lpc31_usbhost.c
index 18b865b7dbe65f2cddef216498804c5cd87a06a5..f267b235e76ac1667945cc568c0127f90612bcb1 100644
--- a/configs/olimex-lpc-h3131/src/lpc31_usbhost.c
+++ b/configs/olimex-lpc-h3131/src/lpc31_usbhost.c
@@ -48,6 +48,7 @@
#include
#include
+#include
#include
#include
#include
@@ -230,8 +231,9 @@ int lpc31_usbhost_initialize(void)
/* Start a thread to handle device connection. */
- pid = task_create("EHCI Monitor", CONFIG_USBHOST_DEFPRIO, CONFIG_USBHOST_STACKSIZE,
- (main_t)ehci_waiter, (FAR char * const *)NULL);
+ pid = kthread_create("EHCI Monitor", CONFIG_USBHOST_DEFPRIO,i
+ CONFIG_USBHOST_STACKSIZE,
+ (main_t)ehci_waiter, (FAR char * const *)NULL);
if (pid < 0)
{
uerr("ERROR: Failed to create ehci_waiter task: %d\n", ret);
@@ -291,11 +293,11 @@ void lpc31_usbhost_vbusdrive(int rhport, bool enable)
* Setup to receive an interrupt-level callback if an overcurrent condition is
* detected.
*
- * Input parameter:
+ * Input Parameters:
* handler - New overcurrent interrupt handler
* arg - The argument that will accompany the interrupt
*
- * Returned value:
+ * Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on failure.
*
************************************************************************************/
diff --git a/configs/olimex-lpc1766stk/src/lpc1766stk.h b/configs/olimex-lpc1766stk/src/lpc1766stk.h
index e591862819a519056e9d5fd33a16ad6f8b225082..bb67e6b7efd4aa7dd8b6a73d091061b99d6dfc4e 100644
--- a/configs/olimex-lpc1766stk/src/lpc1766stk.h
+++ b/configs/olimex-lpc1766stk/src/lpc1766stk.h
@@ -1,7 +1,7 @@
/************************************************************************************
* configs/olimex-lpc1766stk/src/lpc1766stk.h
*
- * Copyright (C) 2010-2011, 2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2010-2011, 2016, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -272,6 +272,27 @@ void weak_function lpc1766stk_sspdev_initialize(void);
int lpc1766stk_can_setup(void);
#endif
+/************************************************************************************
+ * Name: lpc1766stk_hidmouse_setup
+ *
+ * Description:
+ * This function is called by board-bringup logic to configure the HID mouse
+ * device. This function will register the driver as /dev/inputN where N is the
+ * minor device number.
+ *
+ * Input Parameters:
+ * minor - The input device minor number
+ *
+ * Returned Value:
+ * Zero is returned on success. Otherwise, a negated errno value is returned to
+ * indicate the nature of the failure.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_USBHOST_HIDMOUSE
+int lpc1766stk_hidmouse_setup(int minor);
+#endif
+
#endif /* __ASSEMBLY__ */
#endif /* _CONFIGS_OLIMEX_LPC1766STK_SRC_LPC1766STK_H */
diff --git a/configs/olimex-lpc1766stk/src/lpc17_appinit.c b/configs/olimex-lpc1766stk/src/lpc17_appinit.c
index 22e4858fc3eb08fa4d424aa2cf86eb20be160901..8a5d9a2fd4f80875e401cf6ec24a8b1480273120 100644
--- a/configs/olimex-lpc1766stk/src/lpc17_appinit.c
+++ b/configs/olimex-lpc1766stk/src/lpc17_appinit.c
@@ -1,7 +1,7 @@
/****************************************************************************
* config/olimex-lpc1766stk/src/lpc17_appinit.c
*
- * Copyright (C) 2010, 2013-2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2010, 2013-2016, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -45,6 +45,7 @@
#include
#include
+#include
#include
#include
#include
@@ -301,9 +302,9 @@ static int nsh_usbhostinitialize(void)
syslog(LOG_ERR, "ERROR: Start nsh_waiter\n");
- pid = task_create("usbhost", CONFIG_LPC1766STK_USBHOST_PRIO,
- CONFIG_LPC1766STK_USBHOST_STACKSIZE,
- (main_t)nsh_waiter, (FAR char * const *)NULL);
+ pid = kthread_create("usbhost", CONFIG_LPC1766STK_USBHOST_PRIO,
+ CONFIG_LPC1766STK_USBHOST_STACKSIZE,
+ (main_t)nsh_waiter, (FAR char * const *)NULL);
return pid < 0 ? -ENOEXEC : OK;
}
@@ -362,6 +363,16 @@ int board_app_initialize(uintptr_t arg)
syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret);
}
+#ifdef CONFIG_USBHOST_HIDMOUSE
+ /* Initialize the HID Mouse class */
+
+ ret = lpc1766stk_hidmouse_setup(0);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: lpc1766stk_hidmouse_setup failed: %d\n", ret);
+ }
+#endif
+
#ifdef CONFIG_CAN
/* Initialize CAN and register the CAN driver. */
diff --git a/configs/olimex-lpc1766stk/src/lpc17_hidmouse.c b/configs/olimex-lpc1766stk/src/lpc17_hidmouse.c
index f583d52679213d618ac69e0ae3a99e4a19dd06cf..c4b6792d12f6c3f026ff30cdc51c244f3305436a 100644
--- a/configs/olimex-lpc1766stk/src/lpc17_hidmouse.c
+++ b/configs/olimex-lpc1766stk/src/lpc17_hidmouse.c
@@ -71,17 +71,15 @@
****************************************************************************/
/****************************************************************************
- * Name: board_tsc_setup
+ * Name: lpc1766stk_hidmouse_setup
*
* Description:
- * Each board that supports a touchscreen device must provide this
- * function. This function is called by application-specific, setup logic
- * to configure the USB HID mouse driver that emulates a touchscreen
- * device. This function will register the driver as /dev/mouseN where N
- * is the minor device number.
+ * This function is called by board-bringup logic to configure the HID
+ * mouse device. This function will register the driver as /dev/inputN
+ * where N is the minor device number.
*
* Input Parameters:
- * minor - The mouse device minor number
+ * minor - The mouse device minor number
*
* Returned Value:
* Zero is returned on success. Otherwise, a negated errno value is
@@ -89,7 +87,7 @@
*
****************************************************************************/
-int board_tsc_setup(int minor)
+int lpc1766stk_hidmouse_setup(int minor)
{
static bool initialized = false;
int ret;
@@ -132,27 +130,4 @@ int board_tsc_setup(int minor)
return OK;
}
-/****************************************************************************
- * Name: board_tsc_teardown
- *
- * Description:
- * Each board that supports a touchscreen device must provide this function.
- * This function is called by application-specific, setup logic to
- * uninitialize the touchscreen device.
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
-void board_tsc_teardown(void)
-{
- /* No support for un-initializing the USB mouse driver. It will continue
- * to run and process touch interrupts in the background.
- */
-}
-
#endif /* CONFIG_USBHOST_HIDMOUSE */
diff --git a/configs/olimex-stm32-e407/src/stm32_usb.c b/configs/olimex-stm32-e407/src/stm32_usb.c
index f59dc54486b2f559993a50f3f71cbdac83a0c7a6..5e28e17faa5a1da67b033682e74348b1a2330fc2 100644
--- a/configs/olimex-stm32-e407/src/stm32_usb.c
+++ b/configs/olimex-stm32-e407/src/stm32_usb.c
@@ -47,6 +47,7 @@
#include
#include
+#include
#include
#include
#include
@@ -237,9 +238,9 @@ int stm32_usbhost_initialize(void)
uinfo("Start usbhost_waiter\n");
- pid = task_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO,
- CONFIG_STM32F4DISCO_USBHOST_STACKSIZE,
- (main_t)usbhost_waiter, (FAR char * const *)NULL);
+ pid = kthread_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO,
+ CONFIG_STM32F4DISCO_USBHOST_STACKSIZE,
+ (main_t)usbhost_waiter, (FAR char * const *)NULL);
return pid < 0 ? -ENOEXEC : OK;
}
@@ -300,11 +301,11 @@ void stm32_usbhost_vbusdrive(int iface, bool enable)
* Setup to receive an interrupt-level callback if an overcurrent condition is
* detected.
*
- * Input Parameter:
+ * Input Parameters:
* handler - New overcurrent interrupt handler
* arg - The argument provided for the interrupt handler
*
- * Returned value:
+ * Returned Value:
* Zero (OK) is returned on success. Otherwise, a negated errno value is returned
* to indicate the nature of the failure.
*
diff --git a/configs/olimex-stm32-h407/src/stm32_usb.c b/configs/olimex-stm32-h407/src/stm32_usb.c
index a5148f1e578a441b706ecd2230f0e639a244f197..584e8c0a4e31c162f585ab8a45fbe94802b2ff95 100644
--- a/configs/olimex-stm32-h407/src/stm32_usb.c
+++ b/configs/olimex-stm32-h407/src/stm32_usb.c
@@ -47,6 +47,7 @@
#include
#include
+#include
#include
#include
#include
@@ -215,9 +216,9 @@ int stm32_usbhost_initialize(void)
uinfo("Start usbhost_waiter\n");
- pid = task_create("usbhost", CONFIG_STM32H407_USBHOST_PRIO,
- CONFIG_STM32H407_USBHOST_STACKSIZE,
- (main_t)usbhost_waiter, (FAR char * const *)NULL);
+ pid = kthread_create("usbhost", CONFIG_STM32H407_USBHOST_PRIO,
+ CONFIG_STM32H407_USBHOST_STACKSIZE,
+ (main_t)usbhost_waiter, (FAR char * const *)NULL);
return pid < 0 ? -ENOEXEC : OK;
}
@@ -282,7 +283,7 @@ void stm32_usbhost_vbusdrive(int iface, bool enable)
* handler - New overcurrent interrupt handler
* arg - The argument provided for the interrupt handler
*
- * Returned value:
+ * Returned Value:
* Zero (OK) is returned on success. Otherwise, a negated errno value is returned
* to indicate the nature of the failure.
*
diff --git a/configs/olimex-stm32-p207/src/stm32_usb.c b/configs/olimex-stm32-p207/src/stm32_usb.c
index fdef1532dc03d19ca76912fc6e46c3222a561fea..8195a326d28f58cb435dddba62a409182f9e015b 100644
--- a/configs/olimex-stm32-p207/src/stm32_usb.c
+++ b/configs/olimex-stm32-p207/src/stm32_usb.c
@@ -47,6 +47,7 @@
#include
#include
+#include
#include
#include
#include
@@ -219,9 +220,9 @@ int stm32_usbhost_initialize(void)
uinfo("Start usbhost_waiter\n");
- pid = task_create("usbhost", CONFIG_USBHOST_DEFPRIO,
- CONFIG_USBHOST_STACKSIZE,
- (main_t)usbhost_waiter, (FAR char * const *)NULL);
+ pid = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO,
+ CONFIG_USBHOST_STACKSIZE,
+ (main_t)usbhost_waiter, (FAR char * const *)NULL);
return pid < 0 ? -ENOEXEC : OK;
}
@@ -236,11 +237,11 @@ int stm32_usbhost_initialize(void)
* Setup to receive an interrupt-level callback if an overcurrent condition is
* detected.
*
- * Input Parameter:
+ * Input Parameters:
* handler - New overcurrent interrupt handler
* arg - The argument provided for the interrupt handler
*
- * Returned value:
+ * Returned Value:
* Zero (OK) is returned on success. Otherwise, a negated errno value is returned
* to indicate the nature of the failure.
*
diff --git a/configs/olimex-stm32-p407/src/stm32_usb.c b/configs/olimex-stm32-p407/src/stm32_usb.c
index 2456beecf6026de6a3980ab649d7f9be6e21bc57..428b44af6248d58d6ca294312d92345ca5ee4445 100644
--- a/configs/olimex-stm32-p407/src/stm32_usb.c
+++ b/configs/olimex-stm32-p407/src/stm32_usb.c
@@ -47,6 +47,7 @@
#include
#include
+#include
#include
#include
#include
@@ -236,9 +237,9 @@ int stm32_usbhost_setup(void)
uinfo("Start usbhost_waiter\n");
- pid = task_create("usbhost", CONFIG_OLIMEXP407_USBHOST_PRIO,
- CONFIG_OLIMEXP407_USBHOST_STACKSIZE,
- (main_t)usbhost_waiter, (FAR char * const *)NULL);
+ pid = kthread_create("usbhost", CONFIG_OLIMEXP407_USBHOST_PRIO,
+ CONFIG_OLIMEXP407_USBHOST_STACKSIZE,
+ (main_t)usbhost_waiter, (FAR char * const *)NULL);
return pid < 0 ? -ENOEXEC : OK;
}
@@ -299,11 +300,11 @@ void stm32_usbhost_vbusdrive(int iface, bool enable)
* Setup to receive an interrupt-level callback if an overcurrent condition is
* detected.
*
- * Input Parameter:
+ * Input Parameters:
* handler - New overcurrent interrupt handler
* arg - The argument provided for the interrupt handler
*
- * Returned value:
+ * Returned Value:
* Zero (OK) is returned on success. Otherwise, a negated errno value is returned
* to indicate the nature of the failure.
*
diff --git a/configs/olimex-strp711/src/str71_spi.c b/configs/olimex-strp711/src/str71_spi.c
index 1c18a4e5536ee1c7cc08d6a0548b18bd395572b9..f73dc744d511bd66f84bd740a8fc63604960bdc6 100644
--- a/configs/olimex-strp711/src/str71_spi.c
+++ b/configs/olimex-strp711/src/str71_spi.c
@@ -952,7 +952,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t bu
* Initialize the selected SPI port. This function could get called
* multiple times for each STR7 devices that needs an SPI reference.
*
- * Input Parameter:
+ * Input Parameters:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
diff --git a/configs/olimexino-stm32/can/defconfig b/configs/olimexino-stm32/can/defconfig
index 0791cf78896bb3acec7037a85f6ff25838837a7e..8ed1c496421684fbc18fad0235326b867e25671f 100644
--- a/configs/olimexino-stm32/can/defconfig
+++ b/configs/olimexino-stm32/can/defconfig
@@ -48,7 +48,7 @@ CONFIG_I2C=y
CONFIG_IDLETHREAD_STACKSIZE=300
CONFIG_INTELHEX_BINARY=y
CONFIG_LIB_SENDFILE_BUFSIZE=0
-CONFIG_MAX_TASKS=12
+CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2
CONFIG_MM_SMALL=y
CONFIG_NAME_MAX=8
diff --git a/configs/olimexino-stm32/composite/defconfig b/configs/olimexino-stm32/composite/defconfig
index ad25c1672df44afad64988bea346a67957a24d5b..868b2a697ef47e583579ca8f1b72ccb5b86d23af 100644
--- a/configs/olimexino-stm32/composite/defconfig
+++ b/configs/olimexino-stm32/composite/defconfig
@@ -66,7 +66,7 @@ CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_IDLETHREAD_STACKSIZE=300
CONFIG_INTELHEX_BINARY=y
CONFIG_LIB_SENDFILE_BUFSIZE=0
-CONFIG_MAX_TASKS=12
+CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2
CONFIG_MM_SMALL=y
CONFIG_MMCSD=y
diff --git a/configs/olimexino-stm32/nsh/defconfig b/configs/olimexino-stm32/nsh/defconfig
index 30a421918e32dad9584f799cad9313a22dbf31ff..0bd53f08b208b7eb86b234eaec18d50117594aa3 100644
--- a/configs/olimexino-stm32/nsh/defconfig
+++ b/configs/olimexino-stm32/nsh/defconfig
@@ -54,7 +54,7 @@ CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_IDLETHREAD_STACKSIZE=300
CONFIG_INTELHEX_BINARY=y
CONFIG_LIB_SENDFILE_BUFSIZE=0
-CONFIG_MAX_TASKS=12
+CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2
CONFIG_MM_SMALL=y
CONFIG_MMCSD=y
diff --git a/configs/olimexino-stm32/src/olimexino-stm32.h b/configs/olimexino-stm32/src/olimexino-stm32.h
index 987c55c00f76913a038456726c5c67b43d5b0797..c3383eb8a2fb4f52441c280d248cde21f8222615 100644
--- a/configs/olimexino-stm32/src/olimexino-stm32.h
+++ b/configs/olimexino-stm32/src/olimexino-stm32.h
@@ -163,7 +163,7 @@ void stm32_usbinitialize(void);
* Description:
* Called to setup set a call back for USB power state changes.
*
- * Inputs:
+ * Input Parameters:
* pwr_changed_handler: An interrupt handler that will be called on VBUS power
* state changes.
*
diff --git a/configs/olimexino-stm32/src/stm32_usbdev.c b/configs/olimexino-stm32/src/stm32_usbdev.c
index 148ae44312950c9bb3f53d677e09641c2c07753a..a2814fc361f6e4b0d4ebd16e079d9657e5dbe005 100644
--- a/configs/olimexino-stm32/src/stm32_usbdev.c
+++ b/configs/olimexino-stm32/src/stm32_usbdev.c
@@ -69,7 +69,7 @@
* Name: stm32_usb_set_pwr_callback()
*
* Description:
- * Inputs:
+ * Input Parameters:
* pwr_changed_handler: An interrupt handler that will be called on VBUS power
* state changes.
*
diff --git a/configs/open1788/src/lpc17_appinit.c b/configs/open1788/src/lpc17_appinit.c
index 19cc0ee0ac317717d8adbdcd5bcdc66d16f433f7..ee557911a5f0adbdf08f35b36fa62ffad83b44d7 100644
--- a/configs/open1788/src/lpc17_appinit.c
+++ b/configs/open1788/src/lpc17_appinit.c
@@ -89,6 +89,6 @@ int board_app_initialize(uintptr_t arg)
#else
/* Perform board-specific initialization */
- return lpc17_bringup();
+ return open1788_bringup();
#endif
}
diff --git a/configs/open1788/src/lpc17_boardinitialize.c b/configs/open1788/src/lpc17_boardinitialize.c
index 12109ea14e71dab411f8ce5ffa1f86a565098e05..1058f6cc7edd152d77d5939ea9ca75414d843fde 100644
--- a/configs/open1788/src/lpc17_boardinitialize.c
+++ b/configs/open1788/src/lpc17_boardinitialize.c
@@ -137,6 +137,6 @@ void board_initialize(void)
{
/* Perform board-specific initialization */
- (void)lpc17_bringup();
+ (void)open1788_bringup();
}
#endif
diff --git a/configs/open1788/src/lpc17_bringup.c b/configs/open1788/src/lpc17_bringup.c
index 98a79fcf4ec1c3129fd3871531c3393ef0064aa5..44d9228f2409525786e4442e6cd7363212e29af0 100644
--- a/configs/open1788/src/lpc17_bringup.c
+++ b/configs/open1788/src/lpc17_bringup.c
@@ -46,6 +46,7 @@
#include
#include
+#include
#include
#include
#include
@@ -245,12 +246,11 @@ static int nsh_sdinitialize(void)
lpc17_configgpio(GPIO_SD_CD);
+#ifdef NSH_HAVE_MMCSD_CDINT
/* Attach an interrupt handler to get notifications when a card is
* inserted or deleted.
*/
-#ifdef NSH_HAVE_MMCSD_CDINT
-
(void)irq_attach(LPC17_IRQ_P0p13, nsh_cdinterrupt, NULL);
up_enable_irq(LPC17_IRQ_P0p13);
@@ -344,9 +344,9 @@ static int nsh_usbhostinitialize(void)
syslog(LOG_INFO, "Start nsh_waiter\n");
- pid = task_create("usbhost", CONFIG_USBHOST_DEFPRIO,
- CONFIG_USBHOST_STACKSIZE,
- (main_t)nsh_waiter, (FAR char * const *)NULL);
+ pid = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO,
+ CONFIG_USBHOST_STACKSIZE,
+ (main_t)nsh_waiter, (FAR char * const *)NULL);
return pid < 0 ? -ENOEXEC : OK;
}
@@ -361,7 +361,7 @@ static int nsh_usbhostinitialize(void)
****************************************************************************/
/****************************************************************************
- * Name: lpc17_bringup
+ * Name: open1788_bringup
*
* Description:
* Perform architecture-specific initialization
@@ -374,7 +374,7 @@ static int nsh_usbhostinitialize(void)
*
****************************************************************************/
-int lpc17_bringup(void)
+int open1788_bringup(void)
{
int ret;
@@ -398,6 +398,16 @@ int lpc17_bringup(void)
}
#endif
+#ifdef CONFIG_INPUT_ADS7843E
+ /* Initialize the touchscreen */
+
+ ret = open1788_tsc_setup(0);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: open1788_tsc_setup failed: %d\n", ret);
+ }
+#endif
+
#ifdef CONFIG_OPEN1788_DJOYSTICK
/* Initialize and register the joystick driver */
diff --git a/configs/open1788/src/lpc17_touchscreen.c b/configs/open1788/src/lpc17_touchscreen.c
index eb63f526145a681c0051d8191d5594e00842808b..65a0f33faef7186ec35e0f76eeb24d9f175cc089 100644
--- a/configs/open1788/src/lpc17_touchscreen.c
+++ b/configs/open1788/src/lpc17_touchscreen.c
@@ -1,6 +1,5 @@
/************************************************************************************
* configs/open1788/src/lpc17_touchscreen.c
- * arch/arm/src/board/lpc17_touchscreen.c
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -255,13 +254,12 @@ static bool tsc_pendown(FAR struct ads7843e_config_s *state)
****************************************************************************/
/****************************************************************************
- * Name: board_tsc_setup
+ * Name: open1788_tsc_setup
*
* Description:
- * Each board that supports a touchscreen device must provide this
- * function. This function is called by application-specific, setup logic
- * to configure the touchscreen device. This function will register the
- * driver as /dev/inputN where N is the minor device number.
+ * This function is called by board-bringup logic to configure the
+ * touchscreen device. This function will register the driver as
+ * /dev/inputN where N is the minor device number.
*
* Input Parameters:
* minor - The input device minor number
@@ -272,76 +270,45 @@ static bool tsc_pendown(FAR struct ads7843e_config_s *state)
*
****************************************************************************/
-int board_tsc_setup(int minor)
+int open1788_tsc_setup(int minor)
{
- static bool initialized = false;
FAR struct spi_dev_s *dev;
int ret;
- iinfo("initialized:%d minor:%d\n", initialized, minor);
+ iinfo("minor:%d\n", minor);
DEBUGASSERT(minor == 0);
- /* Since there is no uninitialized logic, this initialization can be
- * performed only one time.
- */
-
- if (!initialized)
- {
- /* Configure and enable the XPT2046 PENIRQ pin as an interrupting input. */
+ /* Configure and enable the XPT2046 PENIRQ pin as an interrupting input. */
- (void)lpc17_configgpio(GPIO_TC_PENIRQ);
+ (void)lpc17_configgpio(GPIO_TC_PENIRQ);
- /* Configure the XPT2046 BUSY pin as a normal input. */
+ /* Configure the XPT2046 BUSY pin as a normal input. */
#ifndef XPT2046_NO_BUSY
- (void)lpc17_configgpio(GPIO_TC_BUSY);
+ (void)lpc17_configgpio(GPIO_TC_BUSY);
#endif
- /* Get an instance of the SPI interface */
+ /* Get an instance of the SPI interface */
- dev = lpc17_sspbus_initialize(CONFIG_ADS7843E_SPIDEV);
- if (!dev)
- {
- ierr("ERROR: Failed to initialize SPI bus %d\n", CONFIG_ADS7843E_SPIDEV);
- return -ENODEV;
- }
-
- /* Initialize and register the SPI touchscreen device */
+ dev = lpc17_sspbus_initialize(CONFIG_ADS7843E_SPIDEV);
+ if (!dev)
+ {
+ ierr("ERROR: Failed to initialize SPI bus %d\n", CONFIG_ADS7843E_SPIDEV);
+ return -ENODEV;
+ }
- ret = ads7843e_register(dev, &g_tscinfo, CONFIG_ADS7843E_DEVMINOR);
- if (ret < 0)
- {
- ierr("ERROR: Failed to register touchscreen device minor=%d\n",
- CONFIG_ADS7843E_DEVMINOR);
- /* up_spiuninitialize(dev); */
- return -ENODEV;
- }
+ /* Initialize and register the SPI touchscreen device */
- initialized = true;
+ ret = ads7843e_register(dev, &g_tscinfo, CONFIG_ADS7843E_DEVMINOR);
+ if (ret < 0)
+ {
+ ierr("ERROR: Failed to register touchscreen device minor=%d\n",
+ CONFIG_ADS7843E_DEVMINOR);
+ /* up_spiuninitialize(dev); */
+ return -ENODEV;
}
return OK;
}
-/****************************************************************************
- * Name: board_tsc_teardown
- *
- * Description:
- * Each board that supports a touchscreen device must provide this function.
- * This function is called by application-specific, setup logic to
- * uninitialize the touchscreen device.
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * None.
- *
- ****************************************************************************/
-
-void board_tsc_teardown(void)
-{
- /* No support for un-initializing the touchscreen XPT2046 device yet */
-}
-
#endif /* CONFIG_INPUT_ADS7843E */
diff --git a/configs/open1788/src/open1788.h b/configs/open1788/src/open1788.h
index 589d78b261b5ed164dae27045c77eda500ab897f..4a8254348bc4dc99eabd91d6a1841a89966c806b 100644
--- a/configs/open1788/src/open1788.h
+++ b/configs/open1788/src/open1788.h
@@ -2,7 +2,7 @@
* configs/open1788/src/open1788.h
* arch/arm/src/board/open1788.n
*
- * Copyright (C) 2013, 2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -162,7 +162,7 @@
************************************************************************************/
/************************************************************************************
- * Name: lpc17_bringup
+ * Name: open1788_bringup
*
* Description:
* Perform architecture-specific initialization
@@ -175,7 +175,7 @@
*
************************************************************************************/
-int lpc17_bringup(void);
+int open1788_bringup(void);
/************************************************************************************
* Name: open1788_sspdev_initialize
@@ -237,13 +237,34 @@ void open1788_nand_initialize(void);
void open1788_lcd_initialize(void);
#endif
-/****************************************************************************
+/************************************************************************************
+ * Name: open1788_tsc_setup
+ *
+ * Description:
+ * This function is called by board-bringup logic to configure the touchscreen
+ * device. This function will register the driver as /dev/inputN where N is the
+ * minor device number.
+ *
+ * Input Parameters:
+ * minor - The input device minor number
+ *
+ * Returned Value:
+ * Zero is returned on success. Otherwise, a negated errno value is returned to
+ * indicate the nature of the failure.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_INPUT_ADS7843E
+int open1788_tsc_setup(int minor);
+#endif
+
+/************************************************************************************
* Name: lpc17_djoy_initialization
*
* Description:
* Initialize and register the discrete joystick driver
*
- ****************************************************************************/
+ ************************************************************************************/
#ifdef CONFIG_OPEN1788_DJOYSTICK
int lpc17_djoy_initialization(void);
diff --git a/configs/photon/src/photon.h b/configs/photon/src/photon.h
index f98c223341f26e46ff2e0706570cc445cbad4f21..5b2412f7e029ee765b6ba1f7b6e9ea7bbedbf551 100644
--- a/configs/photon/src/photon.h
+++ b/configs/photon/src/photon.h
@@ -120,7 +120,7 @@ void weak_function stm32_spidev_initialize(void);
* Description:
* Perform architecture-specific initialization of the Watchdog hardware.
*
- * Input parameters:
+ * Input Parameters:
* None
*
* Returned Value:
@@ -138,7 +138,7 @@ int photon_watchdog_initialize(void);
* Description:
* Initialize wlan hardware and driver for Photon board.
*
- * Input parameters:
+ * Input Parameters:
* None
*
* Returned Value:
diff --git a/configs/pic32mx-starterkit/src/pic32mx_appinit.c b/configs/pic32mx-starterkit/src/pic32mx_appinit.c
index 68aadbcce2b48f74d800cf150e6d7d71de9962f6..12ad25b4b9a41b5ca92dfeb1727d8eb8eacb5630 100644
--- a/configs/pic32mx-starterkit/src/pic32mx_appinit.c
+++ b/configs/pic32mx-starterkit/src/pic32mx_appinit.c
@@ -45,6 +45,7 @@
#include
#include
+#include